Acer aspire s3-951 Schematics

5

4

3

2

1

Hummingbird1_HR

DIS/UMA/Muxless Schematics Document

D D

Sandy Bridge

Intel PCH

C C

DY :None Installed DIS:DIS installed DIS_Muxless :BOTH DIS or Muxless installed DIS_PX:BOTH DIS or PX installed

ANNIE: ONLY FOR ANNIE solution. PSL: KBC795 PSL circuit for 10mW solution installed. 10mW: External circuit for 10mW solution installed. 65W: for 65W adaptor installed. 90W: for 90W adaptor installed.

DIS_PX_Muxless:DIS or PX or Muxless installed. Muxless: Muxless installed.(PX4.0) PX:MUX installed.(PX3.0) PX_Muxless:BOTH PX or Muxless installed.

B B

UMA:UMA installed UMA_Muxless:BOTH UMA or Muxless installed UMA_PX_Muxless:UMA or PX or Muxless installed

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, April 17, 2012

Date: Sheet of

Cover Page

Hummingbird1_HR

Taipei Hsien 221, Taiwan, R.O.C.

1 102

1

-2

5

Project code : 91.4QP01.001 PCB P/N : Revision : 2

D D

C C

HDMI

LCD

B B

HP1

A A

2CH SPEAKER

51

49

Left Side: USB x 2

CAMERA

Internal Digital MIC

5

49

Hummingbird1_HR Block Diagram

HDMI

LVDS(Single Channel)

USB2.0 x 3

Azalia CODEC

ALC271X-VB3

4

Intel CPU

Sandy Bridge FSB: 1066 MHz

4,5,6,7,8,9,10,11,12,13

FDIx4x2

DMIx4

Intel

PCH Cougar Point

14 USB 2.0/1.1 ports

ETHERNET (10/100/1000Mb)

High Definition Audio

SATA ports (6) PCIE ports (8)

LPC I/F ACPI 1.1

17,18,19,20,21,22,23,24,25,26

AZALIA

SPI

Flash ROM

4MB

29

Touch PAD

4

LPC Bus

60

KBC

NUVOTON

NPCE795P

Int. KB

3

DDRIII 1066/1333 Channel A

FPC

FFC

SATA x1

LPC debug port

SMBus

27

Thermal

ENE P2800

3

MINI Board

Card Reader

Board

71

2869 2569

Fan

PCI-E x1

USB x1

SATA x1

Charger signal

USB 2.0 x 1

28

RAM x 8

Mini-Card

802.11a/b/g

M-SATA

HDD

56

2

Charger Circuit

CardReader

RTS5129

2

1

SYSTEM DC/DC

APL5916KAI

INPUTS

1D05V_PWR

OUTPUTS

0D85V_S0

48

CPU DC/DC

NCP6131S52MNR

INPUTS

DCBATOUT

SYSTEM DC/DC

UP6128PQDD

INPUTS

RAM x 8

DCBATOUT

SYSTEM DC/DC

UP6183PQAG

RAM x 8

INPUTS

DCBATOUT 5V_S5

SYSTEM DC/DC

RAM x 8

UP6165BQKF

INPUTS

DCBATOUT

SYSTEM DC/DC

NCP5911MNTBG

INPUTS

DCBATOUT

VGA

RT8208BGQW

INPUTS

DCBATOUT

TI CHARGER

BQ24745RHDR

INPUTS

DCBATOUT

26

SYSTEM DC/DC

RT9025

INPUTS

3D3V_S0

SYSTEM DC/DC

SD/MMC

RT9025-25PSP

INPUTS OUTPUTS

26

1D5V_S3 1V_VGA_S0 3D3V_S5

Switches

INPUTS OUTPUTS

1D5V_S3

PCB LAYER

L1:Top L2:VCC

HR PX

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, April 17, 2012

Date: Sheet of

Block Diagram

Hummingbird1_HR

L3:Signal

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

2 102

1

42~43

OUTPUTS

VCC_CORE

45

OUTPUTS

1D05V_VTT

41

OUTPUTS

5V_AUX_S5 3D3V_AUX_S5

3D3V_S5

46

OUTPUTS

1D5V_S3 0D75V_S0 DDR_VREF_S3

44

OUTPUTS

VCC_GFXCORE_PWR

92

OUTPUTS

VGA_CORE

40

OUTPUTS

BT+

47

OUTPUTS

1D8V_S0

93

1D8V_VGA_S0

1D5V_VGA_S0 3D3V_VGA_S03D3V_S0

L4:Signal L5:GND L6:Bottom

-2

A

PCH Strapping

Name Schematics Notes

SPKR

INIT3_3V# Weak internal pull-up. Leave as "No Connect". GNT3#/GPIO55

4 4

GNT2#/GPIO53 GNT1#/GPIO51

SPI_MOSI

NV_ALE

Reboot option at power-up

Internal weak Pull-down.

Default Mode:

Connect to Vcc3_3 with 8.2-kΩ

No Reboot Mode with TCO Disabled:

- 10-kΩ weak pull-up resistor.

GNT[3:0]# functionality is not available on Mobile. Mobile: Used as GPIO only Pull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3power rail.

Enable Danbury:

Disable Danbury:

Enable Danbury:

Disable Danbury:

Huron River Schematic Checklist Rev.0_7

Connect to Vcc3_3 with 8.2-k? weak pull-up resistor.

Left floating, no pull-down required.

Connect to +NVRAM_VCCQ with 8.2-kohm weak pull-up resistor [CRB has it pulled up with 1-kohm no-stuff resistor]

Leave floating (internal pull-down)

B

C

Processor Strapping

Pin Name Strap Description Configuration (Default value for each bit is

CFG[2]

PCI-Express Static Lane Reversal

CFG[4]

CFG[6:5]

CFG[7]

PCI-Express Port Bifurcation Straps

PEG DEFER TRAINING

1 unless specified otherwise)

1:

Normal Operation. Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

0:

Disabled - No Physical Display Port attached to

1:

Embedded DisplayPort. Enabled - An external Display Port device is

0:

connectd to the EMBEDDED display Port

11 : x16 - Device 1 functions 1 and 2 disabled 10 : x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01 : Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00 : x8, x4, x4 - Device 1 functions 1 and 2 enabled

1:

PEG Train immediately following xxRESETB de assertion PEG Wait for BIOS for training

0:

D

Huron River Schematic Checklist Rev.0_7

Default Value

1

0

11

1

E

NC_CLE DMI termination voltage. Weak internal pull-up. Do not pull low.

Low (0) - Flash Descriptor Security will be overridden. Also, when this signals is sampled on the rising edge of PWROK then it will also disable Intel ME and its features.

HAD_DOCK_EN# /GPIO[33]

3 3

High (1) - Security measure defined in the Flash Descriptor will be enabled. Platform design should provide appropriate pull-up or pull-down depending on the desired settings. If a jumper option is used to tie this signal to GND as required by the functional strap, the signal should be pulled low through a weak pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently. Note: CRB recommends 1-kohm pull-down for FD Override. There is an internal pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for strapping functions.

HDA_SDO Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#. HDA_SYNC

GPIO15

GPIO8

2 2

GPIO27

Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#. Low (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no

confidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality

Note : This is an un-muxed signal. This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low. Sampled at rising edge of RSMRST#. CRB has a 1-kohm pull-up on this signal to +3.3VA rail.

GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down using a 1k +/- 5% resistor. When this signal is sampled high at the rising edge of RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is enabled.

Default = Do not connect (floating)

High(1) = Enables the internal VccVRM to have a clean supply for analog rails. No need to use on-board filter circuit. Low (0) = Disables the VccVRM. Need to use on-board filter circuits for analog rails.

POWER PLANE

5V_S0 3D3V_S0 1D8V_S0 1D5V_S0 1D05V_VTT 0D85V_S0 0D75V_S0 VCC_CORE VCC_GFXCORE 1D8V_VGA_S0 3D3V_VGA_S0 1V_VGA_S0

5V_USBX_S3 1D5V_S3 DDR_VREF_S3

BT+ DCBATOUT 5V_S5 5V_AUX_S5 3D3V_S5 3D3V_AUX_S5

3D3V_AUX_KBC

3D3V_AUX_S5

VOLTAGE DESCRIPTION

5V

3.3V

1.8V

1.5V

1.05V

0.95 - 0.85V

0.75V

0.35V to 1.5V

0.4 to 1.25V

1.8V

3.3V 1V

5V

1.5V

0.75V

6V-14.1V 6V-14.1V 5V 5V

3.3V

3.3V3D3V_LAN_S5

3.3V

Voltage Rails

ACTIVE IN

S0

CPU Core Rail Graphics Core Rail

S3

AC Brick Mode only

All S states

WOL_EN

DSW, Sx ON for supporting Deep Sleep states

G3, Sx

Legacy WOL

Powered by Li Coin Cell in G3 and +V3ALW in Sx

USB Table

Pair

PCIE Routing

0 1

LANE1 Mini Card2(WWAN) LANE2 LANE3 Card Reader

1 1

LANE5 LANE6 LANE7 LANE8 New Card

Mini Card1(WLAN)

Onboard LANLANE4

USB3.0

Intel GBE LAN

Dock

SATA Table

SATA

Pair

0 1 2 3 4 5

Device

HDD1 HDD2

N/A N/A

ODD

ESATA

2 3 4 5 6 7 8 9 10 11 12 13

Device Touch Panel / 3G SIM USB Ext. port 1 (HS)

Fingerprint

BLUETOOTH Mini Card2 (WWAN) CARD READER X X

USB Ext. port 4 / E-SATA /USB CHARGER

USB Ext. port 2 EDP CAMERA Mini Card1 (WLAN) CAMERA

New Card

SMBus ADDRESSES

2

I C / SMBus Addresses

Device

EC SMBus 1 Battery CHARGER

EC SMBus 2 PCH eDP

PCH SMBus SO-DIMMA (SPD) SO-DIMMB (SPD) Digital Pot G-Sensor MINI

Address Hex Bus Ref Des

HURON RIVER ORB

BAT_SCL/BAT_SDA BAT_SCL/BAT_SDA BAT_SCL/BAT_SDA

SML1_CLK/SML1_DATA SML1_CLK/SML1_DATA SML1_CLK/SML1_DATA

PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, April 17, 2012

Date: Sheet of

Table of Content

Hummingbird1_HR

Taipei Hsien 221, Taiwan, R.O.C.

3 102

-2

5

4

3

2

1

SSID = CPU

Signal Routing Guideline: PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.

1 OF 9

CPU1A

D D

C C

B B

NOTE. Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort.

Note: Intel DMI supports both Lane Reversal and polarity inversion but only at PCH side. This is enabled via a soft strap.

Note: Intel FDI supports both Lane Reversal and polarity inversion but only at PCH side. This is enabled via a soft strap.

Note: Lane reversal does not apply to FDI sideband signals.

1D05V_VTT

Signal Routing Guideline: EDP_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. EDP_COMPIO keep W/S=4/15 mils and routing length less than 500 mils.

DMI_TXN[3:0]19

DMI_TXP[3:0]19

DMI_RXN[3:0]19

DMI_RXP[3:0]19

FDI_TXN[7:0]19

FDI_TXP[7:0]19

FDI_FSYNC019 FDI_FSYNC119

FDI_INT19 FDI_LSYNC019

FDI_LSYNC119

R402 24D9R2F-L-GPR402 24D9R2F-L-GP

R403

1 2 1 2

10KR2J-3-GP

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7

FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7

DP_COMP eDP_HPD

M2

DMI_RX#0

P6

DMI_RX#1

P1

DMI_RX#2

P10

DMI_RX#3

N3

DMI_RX0

P7

DMI_RX1

P3

DMI_RX2

P11

DMI_RX3

K1

DMI_TX#0

M8

DMI_TX#1

N4

DMI_TX#2

R2

DMI_TX#3

K3

DMI_TX0

M7

DMI_TX1

P4

DMI_TX2

T3

DMI_TX3

U7

FDI0_TX#0

W11

FDI0_TX#1

W1

FDI0_TX#2

AA6

FDI0_TX#3

W6

FDI1_TX#0

V4

FDI1_TX#1

Y2

FDI1_TX#2

AC9

FDI1_TX#3

U6

FDI0_TX0

W10

FDI0_TX1

W3

FDI0_TX2

AA7

FDI0_TX3

W7

FDI1_TX0

T4

FDI1_TX1

AA3

FDI1_TX2

AC8

FDI1_TX3

AA11

FDI0_FSYNC

AC12

FDI1_FSYNC

U11

FDI_INT

AA10

FDI0_LSYNC

AG8

FDI1_LSYNC

AF3

EDP_COMPIO

AD2

EDP_ICOMPO

AG11

EDP_HPD

AG4

EDP_AUX#

AF4

EDP_AUX

AC3

EDP_TX#0

AC4

EDP_TX#1

AE11

EDP_TX#2

AE7

EDP_TX#3

AC1

EDP_TX0

AA4

EDP_TX1

AE10

EDP_TX2

AE6

EDP_TX3

SANDYBRIDGE-1-GP-U-NF

DMI

Intel(R) FDI

DP

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8

PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15

SANDYBRIDGE

PEG_RX10

PEG_RX11

PEG_RX12

PEG_RX13

PEG_RX14

PEG_RX15

PEG_TX#0

PEG_TX#1

PEG_TX#2

PEG_TX#3

PEG_TX#4

PEG_TX#5

PEG_TX#6

PEG_TX#7

PEG_TX#8

PEG_TX#9 PEG_TX#10 PEG_TX#11 PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15

PCI EXPRESS -- GRAPHICS

PEG_TX10

PEG_TX11

PEG_TX12

PEG_TX13

PEG_TX14

PEG_TX15

1 OF 9

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8 PEG_RX9

PEG_TX0 PEG_TX1 PEG_TX2 PEG_TX3 PEG_TX4 PEG_TX5 PEG_TX6 PEG_TX7 PEG_TX8 PEG_TX9

G3 G1 G4

H22 J21 B22 D21 A19 D17 B14 D13 A11 B10 G8 A8 B6 H8 E5 K7

K22 K19 C21 D19 C19 D16 C13 D12 C11 C9 F8 C8 C5 H6 F6 K6

G22 C23 D23 F21 H19 C17 K15 F17 F14 A15 J14 H13 M10 F10 D9 J4

F22 A23 D24 E21 G19 B18 K17 G17 E14 C15 K13 G13 K10 G10 D8 K4

PEG_IRCOMP_R

R401 24D9R2F-L-GPR401 24D9R2F-L-GP

1 2

1D05V_VTT

NOTE: Select a Fast FET similar to 2N7002E whose rise/ fall time is less than 6 ns. If HPD on eDP interface is disabled, connect it to CPU VCCIO via a 10-kΩ pull-Up resistor on the motherboard.

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, April 17, 2012

Date: Sheet of

CPU (PCIE/DMI/FDI)

Hummingbird1_HR

Taipei Hsien 221, Taiwan, R.O.C.

4 102

-2

SSID = CPU

5

H_SNB_IVB#18

1D05V_VTT

R501

1 2

D D

62R2J-GP

C C

H_PROCHOT#

12

CRB : 47pf CEKLT:43pf

Connect EC to PROCHOT# through inverting OD buffer.

C502

C502 SC47P50V2JN-3GP

SC47P50V2JN-3GP

H_CPUPW RGD22,36,97

PM_DRAM_PWRGD19,37 VDDPWRGOOD37

PLT_RST#18,27,36,71,82,97

H_PM_SYNC19

XDP_DBRESET#

H_PECI22,27

H_PROCHOT#27,42

H_THERMTRIP#22,36

R503 10KR2J-3-GPR503 10KR2J-3-GP

1 2

3D3V_S0

RN503

RN503 SRN1K5J-1-GP

SRN1K5J-1-GP

1

8

2

7

3

6

4 5

BUF_CPU_RST#

R513

1 2

56R2J-4-GP

R505

1 2

0R2J-2-GP

DY

4

H_PROCHOT#_R

VDDPWRGOOD

BUF_CPU_RST#

CPU1B

F49

PROC_SELECT#

C57

PROC_DETECT#

C49

CATERR#

A48

PECI

C45

PROCHOT#

D45

THERMTRIP#

C48

PM_SYNC

B46

UNCOREPWRGOOD

BE45

SM_DRAMPWROK

D44

RESET#

SANDYBRIDGE-1-GP-U-NF

3

2 OF 9

J3

MISC

CLOCKS

THERMAL

DDR3

MISC

DDR3

SANDYBRIDGE

PWR MANAGEMENT

MISC

JTAG & BPM

BCLK

BCLK#

DPLL_REF_CLK

DPLL_REF_CLK#

BCLK_ITP

BCLK_ITP#

SM_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

PRDY# PREQ#

TCK TMS

TRST#

TDI

TDO

DBR#

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

H2

CLK_DP_P_R

AG3

CLK_DP_N_R

AG1

N59 N58

AT30

4K99R2F-L-GP

SM_RCOMP_0

BF44

SM_RCOMP_1

BE43

SM_RCOMP_2

BG43

Signal Routing Guideline: SM_RCOMP keep routing length less than 500 mils.

N53 N55

L56 L55

XDP_TRST#

J58 M60

XDP_TDO

L59

XDP_DBRESET#

K58

G58 E55 E59 G55 G59 H60 J59 J61

RN504

RN504 SRN1KJ-7-GP

SRN1KJ-7-GP

1

4

2 3

DY

R502

12

R506 140R2F-GPR506 140R2F-GP

1 2

R507 25D5R2F-GPR507 25D5R2F-GP

1 2

R508 200R2F-L-GPR508 200R2F-L-GP

1 2

2

CLK_EXP_P 20 CLK_EXP_N 20

1D05V_VTT

SM_DRAMRST# 37

XDP_TDO XDP_TRST#

Disabling Guidelines: If motherboard only supports external graphics or without eDP: Connect DPLL_REF_SSCLK on Processor to GND through 1K +/- 5% resistor. Connect DPLL_REF_SSCLK# on Processor to VCCP through 1K +/- 5% resistorpower (~15 mW) may be wasted.

1D05V_VTT

RN502

RN502 SRN51J-GP

SRN51J-GP

2 3 1

4

1

B B

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, April 17, 2012

Date: Sheet of

CPU (THERMAL/CLOCK/PM )

Hummingbird1_HR

Taipei Hsien 221, Taiwan, R.O.C.

5 102

-2

5

4

3

2

1

SSID = CPU

3 OF 9

CPU1C

M_A_DQ[63:0]14

D D

C C

B B

M_A_DQ[63:0]

M_A_BS014 M_A_BS114 M_A_BS214

M_A_CAS#14 M_A_RAS#14 M_A_WE#14

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

AG6

AP11

AJ10

AR11

AP6 AU6 AV9 AR6 AP8

AT13

AU13

BC7

BB7 BA13 BB11

BA7

BA9

BB9 AY13 AV14 AR14 AY17 AR19 BA14 AU14 BB14 BB17 BA45 AR43

AW48

BC48 BC45 AR45

AT48 AY48 BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56 AP50 AP53 AV54

AT54 AP56 AP52 AN57 AN53 AG56 AG53 AN55 AN52 AG55 AK56

BD37

BF36 BA28

BE39 BD39

AT41

AJ6 AL6 AJ8

AL8 AL7

CPU1C

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

SA_BS0 SA_BS1 SA_BS2

SA_CAS# SA_RAS# SA_WE#

SANDYBRIDGE

DDR SYSTEM MEMORY A

3 OF 9

SA_CLK0

SA_CLK#0

SA_CKE0

SA_CLK1

SA_CLK#1

SA_CKE1

SA_CS#0 SA_CS#1

SA_ODT0 SA_ODT1

SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

AU36 AV36 AY26

AT40 AU40 BB26

BB40 BC41

AY40 BA41

AL11 AR8 AV11 AT17 AV45 AY51 AT55 AK55

AJ11 AR10 AY11 AU17 AW45 AV51 AT56 AK54

BG35 BB34 BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32 BE37 BA30 BC30 AW41 AY28 AU26

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DIM0_CLK_DDR0 14 M_A_DIM0_CLK_DDR#0 14 M_A_DIM0_CKE0 14

M_A_DIM0_CLK_DDR1 14 M_A_DIM0_CLK_DDR#1 14 M_A_DIM0_CKE1 14

M_A_DIM0_CS#0 14 M_A_DIM0_CS#1 14

M_A_DIM0_ODT0 14 M_A_DIM0_ODT1 14

M_A_DQS#[7:0] 14

M_A_DQS[7:0] 14

M_A_A[15:0] 14

AL4

AL1 AN3 AR4 AK4 AK3 AN4 AR1 AU4 AT2 AV4 BA4 AU3 AR3 AY2 BA3 BE9 BD9

BD13 BF12

BF8

BD10 BD14 BE13 BF16 BE17 BE18 BE21 BE14 BG14 BG18 BF19 BD50 BF48 BD53 BF52 BD49 BE49 BD54 BE53 BF56 BE57 BC59 AY60 BE54 BG54

BA58 AW59 AW58

AU58

AN61

AN59

AU59

AU61

AN58

AR58

AK58

AL58 AG58 AG59 AM60

AL59 AF61 AH60

BG39 BD42 AT22

AV43 BF40 BD45

CPU1D

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_BS0 SB_BS1 SB_BS2

SB_CAS# SB_RAS# SB_WE#

SANDYBRIDGE

DDR SYSTEM MEMORY B

4 OF 9

SB_CLK0

SB_CLK#0

SB_CKE0

SB_CLK1

SB_CLK#1

SB_CKE1

SB_CS#0 SB_CS#1

SB_ODT0 SB_ODT1

SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7

SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

BA34 AY34 AR22

BA36 BB36 BF27

BE41 BE47

AT43 BG47

AL3 AV3 BG11 BD17 BG51 BA59 AT60 AK59

AM2 AV1 BE11 BD18 BE51 BA61 AR59 AK61

BF32 BE33 BD33 AU30 BD30 AV30 BG30 BD29 BE30 BE28 BD43 AT28 AV28 BD46 AT26 AU22

SANDYBRIDGE-1-GP-U-NF

A A

5

4

3

SANDYBRIDGE-1-GP-U-NF

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, April 17, 2012

Date: Sheet of

CPU (DDR)

Hummingbird1_HR

Taipei Hsien 221, Taiwan, R.O.C.

6 102

1

-2

5

4

3

2

1

SSID = CPU

5 OF 9

CPU1E

B50

CFG0

C51

CFG2

12

R702

D D

DY

R702 1KR2J-1-GP

1KR2J-1-GP

B4:VREF_DQ CHA

M_VREF_DQ_DIMM0_C M_VREF_DQ_DIMM1_C

C C

RN701

SRN1KJ-7-GP

D1:VREF_DQ CHB

4

1

2 3

CFG1

B54

CFG2

D53

CFG3

A51

CFG4

C53

CFG5

C55

CFG6

H49

CFG7

A55

CFG8

H51

CFG9

K49

CFG10

K53

CFG11

F53

CFG12

G53

CFG13

L51

CFG14

F51

CFG15

D52

CFG16

L53

CFG17

H43

VCC_VAL_SENSE

K43

VSS_VAL_SENSE

H45

VAXG_VAL_SENSE

K45

VSSAXG_VAL_SENSE

F48

VCC_DIE_SENSE

H48

RSVD#H48

K48

RSVD#K48

BA19

RSVD#BA19

AV19

RSVD#AV19

AT21

RSVD#AT21

BB21

RSVD#BB21

BB19

RSVD#BB19

AY21

RSVD#AY21

BA22

RSVD#BA22

AY22

RSVD#AY22

AU19

RSVD#AU19

AU21

RSVD#AU21

BD21

RSVD#BD21

BD22

RSVD#BD22

BD25

RSVD#BD25

BD26

RSVD#BD26

BG22

RSVD#BG22

BE22

RSVD#BE22

BG26

RSVD#BG26

BE26

RSVD#BE26

BF23

RSVD#BF23

BE24

RSVD#BE24

SANDYBRIDGE

RESERVED

5 OF 9

RSVD#BE7

RSVD#BG7

RSVD#N42

RSVD#L42 RSVD#L45 RSVD#L47

RSVD#M13 RSVD#M14 RSVD#U14

RSVD#W14

RSVD#P13

RSVD#AT49

RSVD#K24

RSVD#AH2 RSVD#AG13 RSVD#AM14 RSVD#AM15

RSVD#N50

DC_TEST_A4 DC_TEST_C4 DC_TEST_D3

DC_TEST_D1 DC_TEST_A58 DC_TEST_A59 DC_TEST_C59 DC_TEST_A61 DC_TEST_C61 DC_TEST_D61

DC_TEST_BD61

DC_TEST_BE61

DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58

DC_TEST_BG4 DC_TEST_BG3

DC_TEST_BE3

DC_TEST_BG1

DC_TEST_BE1 DC_TEST_BD1

BE7 BG7

N42 L42 L45 L47

M13 M14 U14 W14 P13

AT49 K24

AH2 AG13 AM14 AM15

N50

A4 C4 D3 D1 A58 A59 C59 A61 C61 D61 BD61 BE61 BE59 BG61 BG59 BG58 BG4 BG3 BE3 BG1 BE1 BD1

PEG Static Lane Reversal

CFG2

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

Display Port Presence Strap CFG4

1: Disabled; No Physical Display Port attached to Embedded Display Port

0: Enabled; An external Display Port device is connected to the Embedded Display Port

PCIE Port Bifurcation Straps

CFG[6:5]

11: x16 - Device 1 functions 1 and 2 disabled

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

PEG DEFER TRAINING

CFG7

1: PEG Train immediately following xxRESETB de assertion

0: PEG Wait for BIOS for training

SANDYBRIDGE-1-GP-U-NF

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, April 17, 2012

Date: Sheet of

CPU (RESERVED)

Hummingbird1_HR

Taipei Hsien 221, Taiwan, R.O.C.

7 102

1

-2

SSID = CPU

5

4

CPU1F

3

6 OF 9

2

1

VCC_CORE

A26

VCC

A29

VCC

A31

VCC

D D

VCC_CORE

C C

PROCESSOR CORE POWER: 53A

12

C821

SC2D2U6D3V2MX-GP

12

C824

C822

SC2D2U6D3V2MX-GP

C824

C823

SC2D2U6D3V2MX-GP

12

C826

C825

SC2D2U6D3V2MX-GP

C828

C827

SC2D2U6D3V2MX-GP

12

C829

C830

SC2D2U6D3V2MX-GP

12

C831

SC2D2U6D3V2MX-GP

12

C833

C834

C832

SC2D2U6D3V2MX-GP

C834

SC2D2U6D3V2MX-GP

Layout Note: 2.2u Cap place under CPU

B B

12

C837

SC2D2U6D3V2MX-GP

12

C841

SC2D2U6D3V2MX-GP

12

C848

C847

SC2D2U6D3V2MX-GP

A34 A35 A38 A39 A42 C26 C27 C32 C34 C37 C39 C42 D27 D32 D34 D37 D39 D42 E26 E28 E32 E34 E37 E38 F25 F26 F28 F32 F34 F37 F38 F42 G42 H25 H26 H28 H29 H32 H34 H35 H37 H38 H40

K26 K27 K29 K32 K34 K35 K37 K39 K42 L25 L28 L33 L36 L40 N26 N30 N34 N38

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

J25

VCC

J26

VCC

J28

VCC

J29

VCC

J32

VCC

J34

VCC

J35

VCC

J37

VCC

J38

VCC

J40

VCC

J42

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

SANDYBRIDGE

CORE SUPPLY

PEG AND DDR

POWER

VCC Output Decoupling CAP Recommendation:

1. 1.9m ohm loadline design:(for SV) 4 x 470 uF 25 x 22 uF 35 x 2.2uF

2. 2.9m ohm loadline design: (for ULV/LV) 3 x 330uF 12 x 22uF 16 x 2.2uF

A A

SANDYBRIDGE-1-GP-U-NF

5

4

3

SVID QUIET RAILS

VCC_SENSE VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

VCCIO VCCIO

VCCIO_SEL

VCCPQE VCCPQE

VIDALERT#

VIDSCLK

VIDSOUT

AF46 AG48 AG50 AG51 AJ17 AJ21 AJ25 AJ43 AJ47 AK50 AK51 AL14 AL15 AL16 AL20 AL22 AL26 AL45 AL48 AM16 AM17 AM21 AM43 AM47 AN20 AN42 AN45 AN48

AA14 AA15 AB17 AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15

W16 W17

H_VCCP_SEL_L

BC22

+V1.05S_VCCPQE

AM25 AN22

C877

SC1U6D3V2KX-GP

H_CPU_SVIDALRT#

A44

H_CPU_SVIDCLK

B43

H_CPU_SVIDDAT

C44

F43 G43

R805

AN16 AN17

VCCIO Output Decoupling CAP Recommendation: 2 x 330 uF 10 x 10 uF (0603) 26 x 1uF(0402)

PROCESSOR VCCIO: 8.5A

12

C854

C853

SC10U6D3V3MX-GP

Layout Note: 10u Cap place during CPU & VR

12

C857

SC1U10V2KX-1GP

12

C859

C858

SC1U10V2KX-1GP

Layout Note: 1u Cap place under CPU

12

C884

C883

SC1U10V2KX-1GP

12

C861

C860

SC1U10V2KX-1GP

12

C885

C886

SC1U10V2KX-1GP

Check Pull high ??

PROCESSOR 1.05V Quiet rail for DDR block (BGA only)

+V1.05S_VCCPQE should be short to +V1.05S_VCCP_DDR_R on board

For CRB VIDSOUT need to pull high 130 ohm closr to CPU and IMVP7 For CRB VIDALERT# need to pull high 75 ohm close to CPU

1D05V_VTT

R804

R804 130R2F-1-GP

130R2F-1-GP

1 2

VCC_CORE

12

R801

R801 100R2F-L1-GP-U

100R2F-L1-GP-U

12

R802

R802 100R2F-L1-GP-U

100R2F-L1-GP-U

2

12

R807

R807 10R2F-L-GP

10R2F-L-GP

1

TP805TP805

R806

1 2

12

0R0402-PAD

R803 43R2J-GPR803 43R2J-GP

1 2

10R2F-L-GP

DY

VCCIO_SENSE 45 VSSIO_SENSE 45

DY

1D05V_VTT

1 2

1D05V_VTT

12

C856

SC10U6D3V3MX-GP

1D05V_VTT

12

C862

C863

SC1U10V2KX-1GP

12

C878

C887

SC1U10V2KX-1GP

VR_SVID_ALERT# 42

H_CPU_SVIDCLK 42

SC1U10V2KX-1GP

H_CPU_SVIDDAT 42

12

C864

SC1U10V2KX-1GP

C866

SC1U10V2KX-1GP

12

C880

SC1U10V2KX-1GP

Place near processor

VCCSENSE 42 VSSSENSE 42

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Tuesday, April 17, 2012

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU (VCC_CORE)

Hummingbird1_HR

1

8 102

-2

5

SSID = CPU

4

CPU1G

3

7 OF 9

2

1

S3 power reduction DDR Vref schematic

AA46

VAXG

AB47

VAXG

AB50

VAXG

AB51

VAXG

AB52

VAXG

AB53

VAXG

AB55

VAXG

D D

12

C919

12

C912

C911

SC1U10V2KX-1GP

C C

12

C940

C941

SC1U10V2KX-1GP

12

C913

C914

SC1U10V2KX-1GP

12

C943

C942

SC1U10V2KX-1GP

12

C915

C916

SC1U10V2KX-1GP

12

C949

SC1U10V2KX-1GP

12

C917

SC1U10V2KX-1GP

VAXG Output Decoupling CAP Recommendation:

1. 3.9m ohm loadline design:(for GT2) 2 x 470 uF 6 x 22 uF (0805) 6 x 10 uF (0603) 11 x 1 uF (0402)

2. 4.6m ohm loadline design:(for GT1) 2 x 330 uF 5 x 22 uF (0805)

VCC_GFXCORE

VCC_AXG_SENSE42 VSS_AXG_SENSE42

B B

VCCPLL Output Decoupling CAP Recommendation: 1 x 330 uF 2 x 1 uF (0402)

1D05V_VTT

R911

Celeron

12

0R5J-5-GP

R910

A A

0R5J-5-GP

0R5J-5-GP R913

R913

0R5J-5-GP

12

5

6 x 10 uF (0603) 6 x 1 uF (0402)

12

R906

R906 10R2F-L-GP

10R2F-L-GP

12

R907

R907 10R2F-L-GP

10R2F-L-GP

1D8V_S0

0D85V_S0

Celeron

Layout Note: Place under CPU

Celeron

VCC_AXG_SENSE VSS_AXG_SENSE

PROCESSOR VCCPLL: 1.2A

12

C928

C929

SC1U10V2KX-1GP

PROCESSOR VCCSA: 6A

12

C921

SC10U6D3V3MX-GP

12

C923

12

C927

SC10U6D3V3MX-GP

12

SC1U10V2KX-1GP

4

AB56

VAXG

AB58

VAXG

AB59

VAXG

AC61

VAXG

AD47

VAXG

AD48

VAXG

AD50

VAXG

AD51

VAXG

AD52

C950

SC1U10V2KX-1GP

C918

SC1U10V2KX-1GP

C951

SC1U10V2KX-1GP

VAXG

AD53

VAXG

AD55

VAXG

AD56

VAXG

AD58

VAXG

AD59

VAXG

AE46

VAXG

N45

VAXG

P47

VAXG

P48

VAXG

P50

VAXG

P51

VAXG

P52

VAXG

P53

VAXG

P55

VAXG

P56

VAXG

P61

VAXG

T48

VAXG

T58

VAXG

T59

VAXG

T61

VAXG

U46

VAXG

V47

VAXG

V48

VAXG

V50

VAXG

V51

VAXG

V52

VAXG

V53

VAXG

V55

VAXG

V56

VAXG

V58

VAXG

V59

VAXG

W50

VAXG

W51

VAXG

W52

VAXG

W53

VAXG

W55

VAXG

W56

VAXG

W61

VAXG

Y48

VAXG

Y61

VAXG

F45

VAXG_SENSE

G45

VSSAXG_SENSE

BB3

VCCPLL

BC1

VCCPLL

BC4

VCCPLL

L17

VCCSA

L21

VCCSA

N16

VCCSA

N20

VCCSA

N22

VCCSA

P17

VCCSA

P20

VCCSA

R16

VCCSA

R18

VCCSA

R21

VCCSA

U15

VCCSA

V16

VCCSA

V17

VCCSA

V18

VCCSA

V21

VCCSA

W20

VCCSA

SANDYBRIDGE-1-GP-U-NF

SANDYBRIDGE

GRAPHICS

POWER

SENSE

LINES

SENSE

LINES

1.8V RAIL

SA RAIL

SENSE LINES

Power Delivery DG; #139028 A 1-K pull-down resistor should be placed on the VCCSA_VID lines.

SM_VREF

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

DDR3 - 1.5V RAILS

VDDQ VDDQ VDDQ VDDQ

VCCDQ VCCDQ

QUIET RAILS

VDDQ_SENSE

VSS_SENSE_VDDQ

VCCSA_SENSE

VID0

VCCSA_VID

VID1

VCCSA_VID

3

Refer to the latest Huron River Mainstream PDG (Doc# 438297) for more details

+V_SM_VREF_CNT

AY43

AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33

+1.5S_VCCD_Q

AM28 AN26

C948

SC1U6D3V2KX-GP

12

C930

Layout Note: Place during CPU & VR

Layout Note: Place under CPU

12

C936

VDDQ Output Decoupling Recommendation: 1 x 330 uF 8 x 10uF (0603) 10 x 1 uF (0402)

1D5V_S0

R909

1 2

12

0R0402-PAD

+V_SM_VREF_CNT 37

PROCESSOR VDDQ: 10A

12

C931

SC22U4V3MX-GP

12

C937

SC1U10V2KX-1GP

12

C932

C933

SC22U4V3MX-GP

12

C938

C939

SC1U10V2KX-1GP

Routing Guideline: Power from DDR_VREF_S3 and +V_SM_VREF_CNT should have 10 mils trace width.

SC22U4V3MX-GP

12

C952

SC1U10V2KX-1GP

PROCESSOR DDR 1.5V QUIET RAIL (BGA only)

+V1.5S_VCCD_Q should be short to +V1.5S_VCCDDQ on board

TP_VDDQ_SENSE

BC43 BA43

U10

D48 D49

TP_VDDQ_VSS

1 1

Delete off page H_FC_C22 SA

H_FC_C22 VCCSA_SEL

TP901 TPAD14-GPTP901 TPAD14-GP TP902 TPAD14-GPTP902 TPAD14-GP

VCCSA_SENSE

4

RN901

RN901 SRN1KJ-11-GP-U

SRN1KJ-11-GP-U

1

2 3

12

R912

R912 10R2J-2-GP

10R2J-2-GP

VCCSA_SEL 48

2

Notice:pull-high 100k or 10k

Delete off page VCCSA_SENSE SA

1D5V_S0VCC_GFXCORE

12

EC901

SCD1U50V3KX-GP

12

C953

C954

SC1U10V2KX-1GP

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, April 17, 2012

Date: Sheet of

C956

C955

Layout Note: Place near SM_VREF pin

SC1U10V2KX-1GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU (VCC_GFXCORE)

Hummingbird1_HR

1

9 102

-2

5

4

3

2

1

SSID = CPU

D D

C C

B B

A A

5

CPU1H

A13

VSS

A17

VSS

A21

VSS

A25

VSS

A28

VSS

A33

VSS

A37

VSS

A40

VSS

A45

VSS

A49

VSS

A53

VSS

A9

VSS

AA1

VSS

AA13

VSS

AA50

VSS

AA51

VSS

AA52

VSS

AA53

VSS

AA55

VSS

AA56

VSS

AA8

VSS

AB16

VSS

AB18

VSS

AB21

VSS

AB48

VSS

AB61

VSS

AC10

VSS

AC14

VSS

AC46

VSS

AC6

VSS

AD17

VSS

AD20

VSS

AD4

VSS

AD61

VSS

AE13

VSS

AE8

VSS

AF1

VSS

AF17

VSS

AF21

VSS

AF47

VSS

AF48

VSS

AF50

VSS

AF51

VSS

AF52

VSS

AF53

VSS

AF55

VSS

AF56

VSS

AF58

VSS

AF59

VSS

AG10

VSS

AG14

VSS

AG18

VSS

AG47

VSS

AG52

VSS

AG61

VSS

AG7

VSS

AH4

VSS

AH58

VSS

AJ13

VSS

AJ16

VSS

AJ20

VSS

AJ22

VSS

AJ26

VSS

AJ30

VSS

AJ34

VSS

AJ38

VSS

AJ42

VSS

AJ45

VSS

AJ48

VSS

AJ7

VSS

AK1

VSS

AK52

VSS

AL10

VSS

AL13

VSS

AL17

VSS

AL21

VSS

AL25

VSS

AL28

VSS

AL33

VSS

AL36

VSS

AL40

VSS

AL43

VSS

AL47

VSS

AL61

VSS

AM13

VSS

AM20

VSS

AM22

VSS

AM26

VSS

AM30

VSS

AM34

VSS

SANDYBRIDGE-1-GP-U-NF

SANDYBRIDGE

VSS

4

8 OF 9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AM38 AM4 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP10 AP51 AP55 AP7 AR13 AR17 AR21 AR41 AR48 AR61 AR7 AT14 AT19 AT36 AT4 AT45 AT52 AT58 AU1 AU11 AU28 AU32 AU51 AU7 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW13 AW43 AW61 AW7 AY14 AY19 AY30 AY36 AY4 AY41 AY45 AY49 AY55 AY58 AY9 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC13 BC5 BC57 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BD8 BE5 BG13

9 OF 9

CPU1I

SANDYBRIDGE

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SANDYBRIDGE

VSS

NCTF_VSS_NCTF#A5

NCTF_VSS_NCTF#A57

NCTF_VSS_NCTF#BC61

NCTF_VSS_NCTF#BG5

NCTF_VSS_NCTF#BG57

NCTF_VSS_NCTF#C3

NCTF

NCTF_VSS_NCTF#E1

NCTF_VSS_NCTF#E61

NCTF TEST PIN:

A5,A57,BC61,BG5,BG57,C3,E1,E61

NCTF TEST PIN:

A5,A57,BC61,BG5,BG57,C3,E1,E61

2

BG17 BG21 BG24 BG28 BG37 BG41 BG45 BG49 BG53

BG9

C29 C35 C40 D10 D14 D18 D22 D26 D29 D35

D4 D40 D43 D46 D50 D54 D58

D6 E25 E29

E3 E35 E40 F13 F15 F19 F29 F35 F40 F55

G48 G51

G6

G61

H10 H14 H17 H21

H4 H53 H58

J1 J49 J55

K11 K21 K51

K8 L16 L20 L22 L26 L30 L34 L38 L43 L48 L61

M11 M15

SANDYBRIDGE-1-GP-U-NF

3

9 OF 9

M4

VSS

M58

VSS

M6

VSS

N1

VSS

N17

VSS

N21

VSS

N25

VSS

N28

VSS

N33

VSS

N36

VSS

N40

VSS

N43

VSS

N47

VSS

N48

VSS

N51

VSS

N52

VSS

N56

VSS

N61

VSS

P14

VSS

P16

VSS

P18

VSS

P21

VSS

P58

VSS

P59

VSS

P9

VSS

R17

VSS

R20

VSS

R4

VSS

R46

VSS

T1

VSS

T47

VSS

T50

VSS

T51

VSS

T52

VSS

T53

VSS

T55

VSS

T56

VSS

U13

VSS

U8

VSS

V20

VSS

V61

VSS

W13

VSS

W15

VSS

W18

VSS

W21

VSS

W46

VSS

W8

VSS

Y4

VSS

Y47

VSS

Y58

VSS

Y59

VSS

A5 A57 BC61 BD3

VSS_NCTF

BD59

VSS_NCTF

BE4

VSS_NCTF

BE58

VSS_NCTF

BG5 BG57 C3 C58

VSS_NCTF

D59

VSS_NCTF

E1 E61

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, April 17, 2012

Date: Sheet of

CPU (VSS)

Hummingbird1_HR

Taipei Hsien 221, Taiwan, R.O.C.

1

10 102

-2

5

D D

4

3

2

1

Blanking

C C

B B

HR PX

Wistron Corporation

A A

Title

XDP

Size Document Number Rev

Size Document Number Rev A4

A4

Tuesday, April 17, 2012

Date: Sheet of

5

4

3

Date: Sheet of

2

XDP

Hummingbird1_HR

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

-2

11 102

1

-2

5

D D

C C

4

3

2

1

(Blanking)

B B

Wistron Corporation

A A

Title

Reserved

Size Document Number Rev

Size Document Number Rev A4

A4

Tuesday, April 17, 2012

Date: Sheet of

5

4

3

Date: Sheet of

2

Reserved

Hummingbird1_HR

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

-2

12 102

1

-2

5

D D

C C

4

3

2

1

(Blanking)

B B

Wistron Corporation

A A

Title

Reserved

Size Document Number Rev

Size Document Number Rev A4

A4

Tuesday, April 17, 2012

Date: Sheet of

5

4

3

Date: Sheet of

2

Reserved

Hummingbird1_HR

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

-2

13 102

1

-2

PCH_SMBDATA 20 PCH_SMBCLK 20

5

M_A_A[15:0] 6

M_A_DQ[63:0] 6

M_A_DQS#[7:0] 6 M_A_DQS[7:0] 6

1D5V_S3

RAM1

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

NF#E3/DQ 4

K1

VDD

NF#E8/DQ 5

K9

VDD

NF#D2/DQ 6

M1

VDD

NF#E7/DQ 7

M9

VDD

B9

DM/TDQS

VDDQ

C1

NF#A7/TD QS#

VDDQ

E2

VDDQ

E9

VDDQ

M_A_A0

K3

A0

M_A_A1

L7

A1

M_A_A2

L3

A2

M_A_A3

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

J2

BA0

K8

BA1

J3

BA2

F7

CK

G7

CK#

G9

CKE

F3

RAS#

G3

CAS#

H3

WE#

H2

CS#

N2

RESET#

MT41J256M8HX-187E-D-GP

RAM5

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

K1

VDD

K9

VDD

M1

VDD

M9

VDD

B9

VDDQ

C1

VDDQ

E2

VDDQ

E9

VDDQ

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

J2

BA0

K8

BA1

J3

BA2

F7

CK

G7

CK#

G9

CKE

F3

RAS#

G3

CAS#

H3

WE#

H2

CS#

N2

RESET#

MT41J256M8HX-187E-D-GP

NF#E3/DQ 4 NF#E8/DQ 5 NF#D2/DQ 6 NF#E7/DQ 7

DM/TDQS

NF#A7/TD QS#

VREFCA VREFDQ

DQS#

NC#F1 NC#F9 NC#H1 NC#H9 NC#J7 NC#A3

VSSQ VSSQ VSSQ VSSQ VSSQ

NC#F1 NC#F9 NC#H1 NC#H9 NC#J7 NC#A3

DQ0 DQ1 DQ2 DQ3

DQS

ODT

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14

M_A_BS06 M_A_BS16 M_A_BS26

M_A_DIM0_CLK_DDR06

M_A_DIM0_CLK_DDR#06

M_A_DIM0_CKE06

M_A_RAS#6 M_A_CAS#6

M_A_WE#6

M_A_DIM0_CS#06

DDR3_DRAMRST#37

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14

M_A_BS06 M_A_BS16 M_A_BS26

M_A_DIM0_CLK_DDR06

M_A_DIM0_CLK_DDR#06

M_A_DIM0_CKE06

M_A_RAS#6 M_A_CAS#6

M_A_WE#6

M_A_DIM0_CS#06

DDR3_DRAMRST#37

SSID = MEMORY

D D

C C

4

1D5V_S3 1D5V_S3

RAM2

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14

RAM2

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

NF#E3/DQ 4

K1

VDD

NF#E8/DQ 5

K9

VDD

NF#D2/DQ 6

M1

VDD

NF#E7/DQ 7

M9

VDD

B9

DM/TDQS

VDDQ

C1

NF#A7/TD QS#

VDDQ

E2

VDDQ

E9

VDDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A14

J2

BA0 BA1

J3

BA2

CK CK# CKE

RAS# CAS# WE#

CS# RESET#

MT41J256M8HX-187E-D-GP

RAM6

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A14

J2

BA0 BA1

J3

BA2

CK CK# CKE

RAS# CAS# WE#

CS# RESET#

MT41J256M8HX-187E-D-GP

VREFCA VREFDQ

NF#E3/DQ 4 NF#E8/DQ 5 NF#D2/DQ 6 NF#E7/DQ 7

DM/TDQS

NF#A7/TD QS#

VREFCA VREFDQ

DQS#

NC#F1 NC#F9 NC#H1 NC#H9 NC#J7 NC#A3

VSSQ VSSQ VSSQ VSSQ VSSQ

DQS#

NC#F1 NC#F9 NC#H1 NC#H9 NC#J7 NC#A3

VSSQ VSSQ VSSQ VSSQ VSSQ

K3 L7 L3 K2 L8 L2 M8 M2 N8 M3 H7 M7 K7 N3 N7

K8

F7 G7 G9

F3 G3 H3

H2 N2

1D5V_S31D5V_S3

A2 A9 D7 G2 G8 K1 K9 M1 M9

B9 C1 E2 E9

K3 L7 L3 K2 L8 L2 M8 M2 N8 M3 H7 M7 K7 N3 N7

K8

F7 G7 G9

F3 G3 H3

H2 N2

M_A_DQ1

B3

DQ0

M_A_DQ3

C7

DQ1

M_A_DQ4

C2

DQ2

M_A_DQ7

C8

DQ3

M_A_DQ5

E3

M_A_DQ6

E8

M_A_DQ0

D2

M_A_DQ2

E7

B7 A7

M_A_DQS0

C3

DQS

M_A_DQS#0

D3

DQS#

G1

ODT

J8 E1

VRAM_CH_A_ZQ_1

H8

ZQ

F1 F9 H1 H9

M_A_A15

J7 A3

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

A8

VSS

A1

VSS

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

M_A_DQ37

B3

M_A_DQ34

C7

M_A_DQ36

C2

M_A_DQ38

C8

M_A_DQ33

E3

M_A_DQ39

E8

M_A_DQ32

D2

M_A_DQ35

E7

B7 A7

M_A_DQS4

C3

M_A_DQS#4 M_A_DQS#5

D3

G1

M_A_DIM0_ODT0 6

J8 E1

VRAM_CH_A_ZQ_5 VRAM_CH_A_ZQ_6

H8

ZQ

F1 F9 H1 H9 J7 A3

B1 D8 F2 F8 J1 J9 L1 L9 N1 N9 A8 A1

B2 B8 C9 D1 D9

DDR_VREF_S3

12

R8806

R8806 240R2F-1-GP

240R2F-1-GP

R8802

R8802 240R2F-1-GP

240R2F-1-GP

M_A_DIM0_ODT0 6

M_A_BS06 M_A_BS16 M_A_BS26

M_A_DIM0_CLK_DDR06

M_A_DIM0_CLK_DDR#06

M_A_DIM0_CKE06

M_A_RAS#6 M_A_CAS#6

M_A_WE#6

M_A_DIM0_CS#06 M_A_DIM0_CS#06

DDR3_DRAMRST#37 DDR3_DRAMRST#37

M_A_BS06 M_A_BS16 M_A_BS26

M_A_DIM0_CLK_DDR06

M_A_DIM0_CLK_DDR#06

M_A_DIM0_CKE06

M_A_RAS#6 M_A_CAS#6

M_A_WE#6

M_A_DIM0_CS#06

DDR3_DRAMRST#37

3

1D5V_S3

RAM3

A2

M_A_A0 M_A_A2

M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14

1D5V_S3

M_A_A0 M_A_A2

M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

K1

VDD

K9

VDD

M1

VDD

M9

VDD

B9

VDDQ

C1

VDDQ

E2

VDDQ

E9

VDDQ

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

J2

BA0

K8

BA1

J3

BA2

F7

CK

G7

CK#

G9

CKE

F3

RAS#

G3

CAS#

H3

WE#

H2

CS#

N2

RESET#

MT41J256M8HX-187E-D-GP

RAM7

A2 A9 D7 G2 G8 K1 K9 M1 M9

B9 C1 E2 E9

K3 L7 L3 K2 L8 L2 M8 M2 N8 M3 H7 M7 K7 N3 N7

J2 K8 J3

F7 G7 G9

F3 G3 H3

H2 N2

MT41J256M8HX-187E-D-GP

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A14

BA0 BA1 BA2

CK CK# CKE

RAS# CAS# WE#

CS# RESET#

M_A_DQ15

B3

DQ0

M_A_DQ12

C7

DQ1

M_A_DQ14

C2

DQ2

M_A_DQ8

C8

DQ3

M_A_DQ10

E3

M_A_DQ9

E8

M_A_DQ11

D2

M_A_DQ13

E7

B7 A7

M_A_DQS1 M_A_DQS#2

C3

DQS

M_A_DQS#1

D3

G1

ODT

J8 E1 H8

ZQ

F1 F9 H1 H9 J7 A3

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

A8

VSS

A1

VSS

B2 B8 C9 D1 D9

B3

DQ0

C7

DQ1

C2

DQ2

C8

DQ3

E3 E8 D2 E7

B7 A7

C3

DQS

D3

G1

ODT

J8 E1 H8

ZQ

F1 F9 H1 H9 J7 A3

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

A8

VSS

A1

VSS

B2 B8 C9 D1 D9

DDR_VREF_S3 DDR_VREF_S3

VRAM_CH_A_ZQ_2

12

R8803

R8803 240R2F-1-GP

240R2F-1-GP

M_A_A15

M_A_BS06 M_A_BS16 M_A_BS26

M_A_DIM0_CLK_DDR06

M_A_DIM0_CLK_DDR#06

M_A_DIM0_CKE06

M_A_RAS#6 M_A_CAS#6

M_A_WE#6

M_A_DIM0_CS#06

DDR3_DRAMRST#37

M_A_DQ46 M_A_DQ44 M_A_DQ45 M_A_DQ41 M_A_DQ47 M_A_DQ42 M_A_DQ43 M_A_DQ40

M_A_DQS5

M_A_DIM0_ODT0 6

DDR_VREF_S3DDR_VREF_S3

12

R8807

R8807 240R2F-1-GP

240R2F-1-GP

M_A_A15M_A_A15

M_A_BS06 M_A_BS16 M_A_BS26

M_A_DIM0_CLK_DDR06

M_A_DIM0_CLK_DDR#06

M_A_DIM0_CKE06

M_A_RAS#6 M_A_CAS#6

M_A_WE#6

M_A_DIM0_CS#06

DDR3_DRAMRST#37

NF#E3/DQ 4 NF#E8/DQ 5 NF#D2/DQ 6 NF#E7/DQ 7

DM/TDQS

NF#A7/TD QS#

VREFCA

VREFDQ

DQ0 DQ1 DQ2 DQ3

DQS

DQS#

ODT

ZQ

NC#F1 NC#F9 NC#H1 NC#H9 NC#J7 NC#A3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ

NF#E3/DQ 4 NF#E8/DQ 5 NF#D2/DQ 6 NF#E7/DQ 7

NF#A7/TD QS#

2

M_A_DQ22

B3

M_A_DQ18

C7

M_A_DQ20

C2

M_A_DQ23

C8

M_A_DQ17

E3

M_A_DQ19

E8

M_A_DQ16

D2

M_A_DQ21

E7

B7 A7

M_A_DQS2

C3 D3

G1 J8

E1

VRAM_CH_A_ZQ_3

H8

F1 F9 H1 H9

M_A_A15

J7 A3

B1 D8 F2 F8 J1 J9 L1 L9 N1 N9 A8 A1

B2 B8 C9 D1 D9

M_A_DQ55

B3

DQ0

M_A_DQ51

C7

DQ1

M_A_DQ53

C2

DQ2

M_A_DQ50

C8

DQ3

M_A_DQ52

E3

M_A_DQ54

E8

M_A_DQ48

D2

M_A_DQ49

E7

B7

DM/TDQS

A7

M_A_DQS6

C3

DQS

M_A_DQS#6 M_A_DQS7

D3

DQS#

G1

ODT

J8

VREFCA

E1

VREFDQ

VRAM_CH_A_ZQ_7

H8

ZQ

F1

NC#F1

F9

NC#F9

H1

NC#H1

H9

NC#H9

M_A_A15

J7

NC#J7

A3

NC#A3

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

A8

VSS

A1

VSS

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

DDR_VREF_S3

12

R8804

R8804 240R2F-1-GP

240R2F-1-GP

M_A_DIM0_ODT0 6

DDR_VREF_S3

12

R8808

R8808 240R2F-1-GP

240R2F-1-GP

M_A_BS06 M_A_BS16 M_A_BS26

M_A_DIM0_CLK_DDR06

M_A_DIM0_CLK_DDR#06

M_A_DIM0_CKE06

M_A_RAS#6 M_A_CAS#6 M_A_WE#6

1D5V_S3

M_A_BS06 M_A_BS16 M_A_BS26

M_A_DIM0_CLK_DDR06

M_A_DIM0_CLK_DDR#06

M_A_DIM0_CKE06

M_A_RAS#6 M_A_CAS#6

M_A_WE#6

M_A_DIM0_CS#06

DDR3_DRAMRST#37

M_A_A0M_A_A1 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14

A2 A9 D7 G2 G8 K1 K9 M1 M9

B9 C1 E2 E9

K3 L7 L3 K2 L8 L2 M8 M2 N8 M3 H7 M7 K7 N3 N7

J2 K8 J3

F7 G7 G9

F3 G3 H3

H2 N2

A2 A9 D7 G2 G8 K1 K9 M1 M9

B9 C1 E2 E9

K3 L7 L3 K2 L8 L2 M8 M2 N8 M3 H7 M7 K7 N3 N7

J2 K8 J3

F7 G7 G9

F3 G3 H3

H2 N2

RAM4

VDD VDD VDD VDD VDD

NF#E3/DQ 4

VDD

NF#E8/DQ 5

VDD

NF#D2/DQ 6

VDD

NF#E7/DQ 7

VDD VDDQ

NF#A7/TD QS#

VDDQ VDDQ VDDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A14

BA0 BA1 BA2

CK CK# CKE

RAS# CAS# WE#

CS# RESET#

MT41J256M8HX-187E-D-GP

RAM8

VDD VDD VDD VDD VDD

NF#E3/DQ 4

VDD

NF#E8/DQ 5

VDD

NF#D2/DQ 6

VDD

NF#E7/DQ 7

VDD VDDQ

NF#A7/TD QS#

VDDQ VDDQ VDDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A14

BA0 BA1 BA2

CK CK# CKE

RAS# CAS# WE#

CS# RESET#

MT41J256M8HX-187E-D-GP

DM/TDQS

VREFCA VREFDQ

DM/TDQS

VREFCA VREFDQ

1

M_A_DQ31

B3

DQ0

M_A_DQ30

C7

DQ1

M_A_DQ25

C2

DQ2

M_A_DQ29

C8

DQ3

M_A_DQ27

E3

M_A_DQ28

E8

M_A_DQ26

D2

M_A_DQ24

E7

B7 A7

M_A_DQS3

C3

DQS

M_A_DQS#3

D3

DQS#

G1

ODT

J8 E1

VRAM_CH_A_ZQ_4

H8

ZQ

F1

NC#F1

F9

NC#F9

H1

NC#H1

H9

NC#H9

M_A_A15

J7

NC#J7

A3

NC#A3

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

A8

VSS

A1

VSS

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

M_A_DQ63

B3

DQ0

M_A_DQ57

C7

DQ1

M_A_DQ58

C2

DQ2

M_A_DQ61

C8

DQ3

M_A_DQ59

E3

M_A_DQ60

E8

M_A_DQ62

D2

M_A_DQ56

E7

B7 A7

C3

DQS

M_A_DQS#7

D3

DQS#

G1

ODT

J8 E1

VRAM_CH_A_ZQ_8

H8

ZQ

F1

NC#F1

F9

NC#F9

H1

NC#H1

H9

NC#H9

M_A_A15

J7

NC#J7

A3

NC#A3

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

A8

VSS

A1

VSS

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

12

M_A_DIM0_ODT0 6

DDR_VREF_S3

12

R8805

R8805 240R2F-1-GP

240R2F-1-GP

R8809

R8809 240R2F-1-GP

240R2F-1-GP

M_A_DIM0_ODT0 6M_A_DIM0_ODT0 6

B B

1D5V_S3

12

SCD1U10V2KX-5GP

C1518

C1516

3D3V_S0

U201

1

8

A0

VCC

2

7

A1

WP

3

6

A2

SCL

DY

R1440

R1440 1K21R2F

1K21R2F

1 2

SPD Reserved

5

GND4SDA

AT24C02C-XHM-T-GP

DY

R1439

1K21R2F

1 2

DY

A A

PCH_SMBCLK 20

5

PCH_SMBDATA 20

12

SCD1U10V2KX-5GP

EC1502

EC1501

12

SCD1U10V2KX-5GP

EC1505

EC1504

EC1503

4

SCD1U10V2KX-5GP

12

EC1506

SODIMM A DECOUPLING

12

C1404

C1403

SC10U6D3V3MX-GP

12

C1417

C1416

SCD1U10V2KX-5GP

Layout Note: Place these Caps near SO-DIMMA.

SC56P50V2JN-2GP

12

C1406

C1405

SC10U6D3V3MX-GP

12

C1420

C1418

SCD1U10V2KX-5GP

0D75V_S0

12

C1407

C1408

C1409

SCD1U50V3KX-GP

SC10U6D3V3MX-GP

12

C1422

C1423

C1425

SCD1U10V2KX-5GP

R1407

M_A_DIM0_CKE0

1 2

R1408

33R2F-3-GP

M_A_DIM0_CKE1

1 2

33R2F-3-GP

R1409

M_A_DIM0_ODT0

1 2

33R2F-3-GP

R1410

M_A_DIM0_ODT1

1 2

33R2F-3-GP

R1411

M_A_DIM0_CS#0

1 2

33R2F-3-GP

R1412

M_A_DIM0_CS#1

1 2

33R2F-3-GP

R1413

M_A_RAS#

1 2

33R2F-3-GP

R1414

M_A_CAS#

1 2

R1415

33R2F-3-GP

M_A_WE#

1 2

33R2F-3-GP

R1416

M_A_BS0

1 2

33R2F-3-GP

R1417

M_A_BS1

1 2

R1418

33R2F-3-GP

M_A_BS2

1 2

33R2F-3-GP

12

C1410

SCD1U50V3KX-GP

12

C1424

SCD1U10V2KX-5GP

SC4D7U6D3V3KX-GP

C1440

C1441

C1442

SC4D7U6D3V3KX-GP

M_A_DIM0_CKE1 6

M_A_DIM0_ODT1 6

M_A_DIM0_CS#1 6

12

C1443

C1444

SC4D7U6D3V3KX-GP

0D75V_S0

R1419

R1419 R1420

R1420 R1421

R1421 R1422

R1422 R1423

R1423 R1424

R1424 R1425

R1425 R1426

R1426 R1427

R1427 R1428

R1428 R1429

R1429 R1430

R1430 R1431

R1431 R1432

R1432 R1433

R1433 R1434

R1434

3

12

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

DDR_VREF_S3

12

C1412

C1414

SCD1U10V2KX-5GP

33R2F-3-GP

33R2F-3-GP 33R2F-3-GP

33R2F-3-GP

12

C1411

SCD1U10V2KX-5GP

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

12

C1413

SCD1U10V2KX-5GP

C1415

C1426

SCD1U10V2KX-5GP

12

C1428

SCD1U10V2KX-5GP

󰍢

12

C1446

C1445

C1427

SC4D7U6D3V3KX-GP

SCD1U10V2KX-5GP

or DY?

M_A_DIM0_CLK_DDR16

M_A_DIM0_CLK_DDR#16

2

0D75V_S0

12

M_A_DIM0_CLK_DDR0

M_A_DIM0_CLK_DDR#0

M_A_DIM0_CLK_DDR1

M_A_DIM0_CLK_DDR#1

Place these caps close to VTT1 and VTT2.

12

C1419

C1421

SC1U6D3V2KX-GP

C1430

C1430 SC12P50V2JN-3GP

SC12P50V2JN-3GP

1 2

C1431

C1431 SC12P50V2JN-3GP

SC12P50V2JN-3GP

1 2

0D75V_S0

1 2

R1435

R1435 33R2F-3-GP

33R2F-3-GP

R1436

R1436 33R2F-3-GP

33R2F-3-GP

1 2

12

R1437

R1437 33R2F-3-GP

33R2F-3-GP

R1438

R1438 33R2F-3-GP

33R2F-3-GP

C1520

SC1U6D3V2KX-GP

12

C1522

SC1U6D3V2KX-GP

C1432

1 2

SCD1U10V2KX-5GP

1 2

C1433

SCD1U10V2KX-5GP

HR PX

Title

Size Document Number Rev

Size Document Number Rev A1

A1

Tuesday, April 17, 2012

Date: Sheet of

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

DDR3-SODIMM1

Hummingbird1_HR

14 102

-2

5

4

3

2

1

SSID = MEMORY

D D

C C

B B

A A

5

4

3

2

HR PX

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Tuesday, April 17, 2012

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

DDR3-SODIMM2

Hummingbird1_HR

1

15 102

-2

5

D D

4

3

2

1

C C

B B

A A

5

(Blanking)

4

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

DDR3-SODIMM2

Size Document Number Rev

Size Document Number Rev A4

A4

Tuesday, April 17, 2012

Date: Sheet of

3

Date: Sheet of

2

DDR3-SODIMM2

Hummingbird1_HR

16 102

1

-2

5

3D3V_S0

RN1703

RN1703 SRN2K2J-1-GP

SRN2K2J-1-GP

D D

2 3 1

4

LVDS_DDC_CLK LVDS_DDC_DATA

4

3

2

1

4 OF 10

PCH1D

RN1701

RN1701 SRN2K2J-1-GP

SRN2K2J-1-GP

2 3 1

RN1702

RN1702 SRN100KJ-6-GP

SRN100KJ-6-GP

1 2 3

C C

4

L_CTRL_DATA L_CTRL_CLK

PANEL_BLEN LCDVDD_EN

L_DDC_DATA(PAGE17): This signal is on the LVDS interface. This signal needs to be left NC if eDP is used for the local flat panel display

Place near PCH

2K37R2F-GP

R1701

12

Impedance:90 ohm

Close to PCH side

B B

Delete CRT pull down resistor

PANEL_BLEN27

LCDVDD_EN49

LBKLT_CTL49

LVDS_DDC_CLK49 LVDS_DDC_DATA49

RN1704

RN1704 SRN0J-6-GP

SRN0J-6-GP

1 2 3

LVDSA_CLK#49 LVDSA_CLK49

LVDSA_DATA0#49 LVDSA_DATA1#49 LVDSA_DATA2#49

LVDSA_DATA049 LVDSA_DATA149 LVDSA_DATA249

1KR2D-1-GP

L_CTRL_CLK L_CTRL_DATA

LVDS_IBG

LVDS_VREFH

4

LVDS_VREFL

3D3V_S0

4

1

2 3

R1702

RN1707

RN1707 SRN4K7J-8-GP

SRN4K7J-8-GP

DDCCLK DDCDATA

DAC_IREF_R

12

PCH1D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

COUGAR-GP-U2-NF

Cougar

Cougar Point

Point

LVDS

CRT

Digital Display Interface

4 OF 10

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN

SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

P38 M39

AT49 AT47 AT40

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

DDBP_DATA2# DDBP_DATA2 DDBP_DATA1# DDBP_DATA1 DDBP_DATA0# DDBP_DATA0 DDBP_CLK# DDBP_CLK

Impedance:90 ohm

3D3V_S0

4

RN1706

HDMI

HDMI HDMI

HDMI

RN1706 SRN2K2J-1-GP

SRN2K2J-1-GP

HDMI

1

2 3

C1701 SCD1U10V2KX-5GP

1 2

C1702 SCD1U10V2KX-5GP

1 2

C1703 SCD1U10V2KX-5GP

1 2

C1704 SCD1U10V2KX-5GP

1 2

C1705 SCD1U10V2KX-5GP

1 2

C1706 SCD1U10V2KX-5GP

1 2

C1707 SCD1U10V2KX-5GP

1 2

C1708 SCD1U10V2KX-5GP

1 2

DDI Port B Detect:(SDVO_CTRL_ DATA) 1: Port B detected 0: Port B not detected

PCH_HDMI_CLK 51 PCH_HDMI_DATA 51

Close to Connector side

TM request to change 85-ohm

HDMI_PCH_DET 51 HDMI_DATA2_R# 51

HDMI_DATA2_R 51 HDMI_DATA1_R# 51 HDMI_DATA1_R 51 HDMI_DATA0_R# 51 HDMI_DATA0_R 51 HDMI_CLK_R# 51 HDMI_CLK_R 51

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, April 17, 2012

Date: Sheet of

PCH (LVDS/CRT/DDI)

Hummingbird1_HR

Taipei Hsien 221, Taiwan, R.O.C.

17 102

1

-2

5

4

3

2

1

SSID = PCH

RN1801

RN1801 SRN8K2J-2-GP-U

D D

3D3V_S0

INT_PIRQF# INT_PIRQD#

INT_PIRQB#

A16 swap override Strap/Top-Block Swap Override jumper

PCI_GNT#3 Low = A16 swap

C C

GNT1#/GPIO51 BOOT BIOS LocationSATA1GP/GPIO19

0 0 LPC 0 1 Reserved

SRN8K2J-2-GP-U

1 2 3 4 5 6

override/Top-Block Swap Override enabled High = Default

10 9 8 7

BOOT BIOS Strap

USB30_SMI# INT_PIRQA#INT_PIRQC# INT_PIRQE# INT_PIRQH#

3D3V_S0

DGPU_HOLD_RST# DGPU_PW R_EN#

RN1803

RN1803 SRN10KJ-5-GP

SRN10KJ-5-GP

2 3 1

DY

4

BG26

BJ26

BH25

BJ16 BG16 AH38 AH37 AK43 AK45

C18 N30

AH12

AM4 AM5

Y13 K24

L24 AB46 AB45

B21

M20 AY16 BG46

BE28 BC30 BE32

BJ32 BC28 BE30

BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28

AW30

PCH1E

Cougar

TP1

Point

TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11

H3

TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20

TP21 TP22 TP23 TP24

TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP40

NVRAM

RSVD

Reserved 01

11

B B

SPI(Default)

DGPU_HOLD_RST#

DGPU_PWR_EN#

DEBUG Card

PCH KBC

INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#

DGPU_HOLD_RST#

INT_PIRQE# INT_PIRQF# USB30_SMI# INT_PIRQH#

PLT_RST#5,27,36,71,82,97

DGPU_SELECT#

DGPU_PW R_EN#

CLK_PCI_LPC_R CLK_PCI_FB_R CLK_PCI_KBC_R

TP1806TPAD14-GP TP1806TPAD14-GP

1

Strap pin ,Internal PU

TP1804TPAD14-GP TP1804TPAD14-GP

1

R1804 22R2J-2-GPR1804 22R2J-2-GP

CLK_PCI_LPC71 CLK_PCI_FB20 CLK_PCI_KBC27

1 2

R1805 22R2J-2-GPR1805 22R2J-2-GP

1 2

R1806 22R2J-2-GPR1806 22R2J-2-GP

1 2

DGPU_PW M_SELECT#

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1#/GPIO50

C44

REQ2#/GPIO52

E40

REQ3#/GPIO54

D47

GNT1#/GPIO51

E42

GNT2#/GPIO53

F46

GNT3#/GPIO55

G42

PIRQE#/GPIO2

G40

PIRQF#/GPIO3

C42

PIRQG#/GPIO4

D44

PIRQH#/GPIO5

K10

PME#

C6

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

COUGAR-GP-U2-NF

PCI

USB

5 OF 10

RSVD RSVD RSVD RSVD

RSVD RSVD

RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

RSVD

DF_TVS

RSVD RSVD RSVD

RSVD RSVD

RSVD

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N

USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USBRBIAS#

USBRBIAS

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43

OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14

AY7 AV7 AU3 BG4

AT10 BC8

AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6

AV5 AY1

AV10 AT8 AY5

BA2 AT12

BF3

C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

C33

B33

A14 K20 B17 C16 L16 A16 D14 C14

DMI & FDI Termination Voltage

NV_CLE

Set to Vss when LOW Set to Vcc when HIGH

CRB : 2.2K CEKLT: 1K

1D8V_S0

12

R1808

R1808 2K2R2J-2-GP

2K2R2J-2-GP

NV_CLE

1 2

R1809

R1809 1KR2J-1-GP

1KR2J-1-GP

H_SNB_IVB# 5

USB Ext. port 1 (HS) External debug port use on Huron river platform

USB Table

USB_PN1 61 USB_PP1 61

USB_PN5 82 USB_PP5 82

USB_PN9 61 USB_PP9 61

USB_PN11 82 USB_PP11 82 USB_PN12 49 USB_PP12 49

USB_RBIAS

R1811

R1811 22D6R2F-L1-GP

22D6R2F-L1-GP

OC

1 2

3D3V_S5

R1820

R1820 10KR2J-3-GP

10KR2J-3-GP

1 2

Pair

0 1 2 3 4 5 6 7 8 9 10 11 12 13

Device Touch Panel / 3G SIM(DY) USB Ext. port 1 (HS) Fingerprint(DY) BLUETOOT Mini Card2 (WWAN) (DY) CARD READER X X

USB Ext. port 4 / E-SATA /USB CHARGER

USB Ext. port 2 EDP CAMERA(DY) Mini Card1 (WLAN) CAMERA New Card(DY)

OC[3:0]# for Device 29 (Ports 0-7) OC[7:4]# for Device 26 (Ports 8-13)

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, April 17, 2012

Date: Sheet of

PCH (PCI/USB/NVRAM)

Hummingbird1_HR

Taipei Hsien 221, Taiwan, R.O.C.

18 102

1

-2

5

4

3

2

1

SSID = PCH

D D

Signal Routing Guideline: DMI_ZCOMP keep W=4 mils and routing length less than 500 mils. DMI_IRCOMP keep W=4 mils and routing length less than 500 mils.

1D05V_VTT

R1901 49D9R2F-GPR1901 49D9R2F-GP R1902 750R2F-GPR1902 750R2F-GP

R1926

R1926 10KR2J-3-GP

10KR2J-3-GP

1 2

DY

C C

DY

1 2

R1904

R1904 100KR2J-1-GP

100KR2J-1-GP

S0_PWR_GOOD after PM_SLP_S3# delay 200 ms

B B

A A

SYS_PWROK PWROK

3D3V_S5

5

3D3V_S0

S0_PWR_GOOD27,42

RN1901

RN1901 SRN10KJ-6-GP

SRN10KJ-6-GP

8 7 6

R1921

R1921 10KR2J-3-GP

10KR2J-3-GP

R1908

R1908 100KR2J-1-GP

100KR2J-1-GP

DMI_RXN[3:0]4

DMI_RXP[3:0]4

DMI_TXN[3:0]4

1 2 1 2

1 2

R1905

R1905 10KR2J-3-GP

10KR2J-3-GP

SUS_PW R_ACK27

1 2 3 45

12

DMI_TXP[3:0]4

SYS_PWROK36

R1924

R1924 0R0402-PAD

0R0402-PAD

PM_PWRBTN#27,97

AC_PRESENT27

BATLOW # AC_PRESENT SUS_PW R_ACK PM_RI#

PCIE_WAKE#

DMI_RXN04 DMI_RXN14 DMI_RXN24 DMI_RXN34

DMI_RXP04 DMI_RXP14 DMI_RXP24 DMI_RXP34

DMI_COMP_R RBIAS_CPY

SUS_PW R_ACK

SYS_RESET#

12

PM_DRAM_PWRGD5,37

DMI_TXN04 DMI_TXN14 DMI_TXN24 DMI_TXN34

DMI_TXP04 DMI_TXP14 DMI_TXP24 DMI_TXP34

PWROK

PM_RSMRST#

BATLOW #

PM_RI#

PCIE_WAKE# CRB : 1K

PCH1C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPWRDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT/GPIO31

E10

BATLOW#/GPIO72

A10

RI#

COUGAR-GP-U2-NF

CEKLT: 10K

PWRBTN# This signal has an internal pull-up resistor

12

PM_RSMRST#

PM_RSMRST# CRB : PL 10K ANNIE : PL 100K

4

Cougar

Cougar Point

Point

DMI

FDI

DMI

FDI

CLKRUN#/GPIO32

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

System Power Management

SLP_LAN#/GPIO29

3D3V_AUX_S5

1 2

3 OF 10

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

FDI_INT FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

R1916

R1916 10KR2J-3-GP

10KR2J-3-GP

3V_5V_POK_#

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

AW16 AV12 BC10 AV14 BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

R1909

R1909 100KR2J-1-GP

100KR2J-1-GP

12

FDI_TXN[7:0] 4 FDI_TXP[7:0] 4

FDI_TXN0 4 FDI_TXN1 4 FDI_TXN2 4 FDI_TXN3 4 FDI_TXN4 4 FDI_TXN5 4 FDI_TXN6 4 FDI_TXN7 4

FDI_TXP0 4 FDI_TXP1 4 FDI_TXP2 4 FDI_TXP3 4 FDI_TXP4 4 FDI_TXP5 4 FDI_TXP6 4 FDI_TXP7 4

FDI_INT 4 FDI_FSYNC0 4 FDI_FSYNC1 4 FDI_LSYNC0 4 FDI_LSYNC1 4

DSWODVREN

PCH_DPW ROK

PCIE_WAKE# 82

PM_CLKRUN# 27

PCH_SUSCLK_KBC 27

PM_SLP_S4# 27,46

PM_SLP_S3# 27,29,36,37,47

H_PM_SYNC 5

34 2

5

1

6

3

R1910

R1910 0R0402-PAD

0R0402-PAD

1 2 1 2

DY

R1911

R1911 10KR2J-3-GP

10KR2J-3-GP

PM_RSMRST#

1 2

Q1901

Q1901 2N7002KDW-GP

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

PM_RSMRST#

R1912

R1912 1KR2J-1-GP

1KR2J-1-GP

For platforms not supporting Deep S4/S5

1.VccSUS3_3 and VccDSW3_3 will rise at the same time (connected on board)

2.DPWROK and RSMRST# will rise at the same time (connected on board)

3.SLP_SUS# and SUSACK# are left as ‘no connect’

4.SUSWARN# used as SUSPWRDNACK/GPIO30

RTC_AUX_S5

DSWODVREN - On Die DSW VR Enable

HIGH Enabled (DEFAULT)

LOW Disabled

RTC_AUX_S5

R1917 330KR2J-L1-GPR1917 330KR2J-L1-GP

1 2

DSWODVREN

PM_CLKRUN#

RSMRST#_KBC 27

3V_5V_POK 41

2

R1918 330KR2J-L1-GP

1 2

DY

R1919

R1919 8K2R2J-3-GP

8K2R2J-3-GP

1 2

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, April 17, 2012

Date: Sheet of

3D3V_S0

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCH (DM I/FDI/PM)

Hummingbird1_HR

19 102

1

-2

5

SSID = PCH

USB3.0 CLK

D D

C C

B B

A A

3D3V_S0

RN2018

RN2018 SRN10KJ-5-GP

SRN10KJ-5-GP

1 2 3

PCIE_CLK_RQ2#

4

CLK_PCIE_WLAN_REQ1#

PCIECLKRQ1# and PCIECLKRQ2# Support S0 power only

check list: A 10K-ohm PU still need to be used

PCIE_RXN682

PCIE_RXP682 PCIE_TXN682 PCIE_TXP682

C2001 SCD1U10V2KX-5GPC2001 SCD1U10V2KX-5GP

1 2

C2002 SCD1U10V2KX-5GPC2002 SCD1U10V2KX-5GP

1 2

WWAN CLK

WLAN CLK

CLK_PCIE_WLAN#82 CLK_PCIE_WLAN82

CLK_PCIE_WLAN_REQ#82

PEG_B_CLKRQ#22

5

RN2012

RN2012 SRN0J-6-GP

SRN0J-6-GP

2 3 1

PEG_B_CLKRQ#

PCIE_CLK_REQ6#

PCIE_TXN6_C PCIE_TXP6_C

CLK_PCIE_WWAN_REQ#

CLK_PCIE_WLAN_REQ1#

PCIE_CLK_RQ2#

PCIE_CLK_LAN_RQ#

USB3_PEGB_CLKREQ#

CLK_PCH_SRC6_N CLK_PCH_SRC6_P

4

PCIE_CLK_REQ5#

CLK_PCIE_NEW_REQ#

4

PCH1B

BG34

BJ34 AV32 AU32

BE34

BF34 BB32 AY32

BG36

BJ36 AV34 AU34

BF36 BE36 AY34 BB34

BG37 BH37 AY36 BB36

BJ38 BG38 AU36 AV36

BG40

BJ40 AY40 BB40

BE38 BC38

AW38

AY38

Y40 Y39

J2

AB49 AB47

M1

AA48 AA47

V10

Y37 Y36

A8

Y43 Y45

L12

V45 V46

L14

AB42 AB40

E6

V40 V42

T13

V38 V37

K12

AK14 AK13

COUGAR-GP-U2-NF

– Prioritize 27/14/24/48/25-MHz FLEX on FLEX1 and FLEX3 – Do not configure 27/14/24/48/25-MHz FLEX clock on FLEX0 and FLEX2 if more than 2 PCI clocks + PCI loopback are routed.

4

Cougar

PERN1 PERP1

Point

PETN1

W-WAN

PETP1 PERN2

PERP2

WLAN

PETN2 PETP2

PERN3 PERP3

Card Reader

PETN3 PETP3

PERN4 PERP4

LAN

PETN4 PETP4

PERN5 PERP5

USB3.0

PETN5 PETP5

PERN6 PERP6

Intel GBE LAN

PETN6 PETP6

PERN7 PERP7

Dock

PETN7 PETP7

PERN8

NEW CARD

PERP8 PETN8 PETP8

CLKOUT_PCIE0N CLKOUT_PCIE0P

PCIECLKRQ0#/GPIO73

CLKOUT_PCIE1N CLKOUT_PCIE1P

PCIECLKRQ1#/GPIO18

CLKOUT_PCIE2N CLKOUT_PCIE2P

PCIECLKRQ2#/GPIO20

CLKOUT_PCIE3N CLKOUT_PCIE3P

PCIECLKRQ3#/GPIO25

CLKOUT_PCIE4N CLKOUT_PCIE4P

PCIECLKRQ4#/GPIO26

CLKOUT_PCIE5N CLKOUT_PCIE5P

PCIECLKRQ5#/GPIO44

CLKOUT_PEG_B_N CLKOUT_PEG_B_P

PEG_B_CLKRQ#/GPIO56

CLKOUT_PCIE6N CLKOUT_PCIE6P

PCIECLKRQ6#/GPIO45 CLKOUT_PCIE7N

CLKOUT_PCIE7P PCIECLKRQ7#/GPIO46 CLKOUT_ITPXDP_N

CLKOUT_ITPXDP_P

SMBALERT#/GPIO11

SML0ALERT#/GPIO60

SMBUSController

SML1ALERT#/PCHHOT#/GPIO74

SML1CLK/GPIO58

SML1DATA/GPIO75

PCI-E*

Link

PEG_A_CLKRQ#/GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N

CLOCKS

CLKOUT_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_PCILOOPBACK

CLKOUTFLEX0/GPIO64 CLKOUTFLEX1/GPIO65 CLKOUTFLEX2/GPIO66 CLKOUTFLEX3/GPIO67

FLEX CLOCKS

CLKOUT_DP_N

CLKOUT_DP_P

CLKIN_DMI_N

CLKIN_DMI_P

CLKIN_SATA_N CLKIN_SATA_P

XCLK_RCOMP

2 OF 10

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

REFCLK14IN

XTAL25_IN

XTAL25_OUT

3

E12 H14 C9

A12 C8 G12

C13 E14 M16

M7

T11

P10

M10

AB37 AB38

AV22 AU22

AM12 AM13

BF18 BE18

BJ30 BG30

G24 E24

AK7 AK5

K45

H45

V47 V49

Y47

K43 F47 H47 K49

3

SMB_CLK SMB_DATA

SML0_CLK SML0_DATA

PCH_GPIO74

For DIS_PX mode or MXM mode.

PEG_CLKREQ#_R

CLK_EXP_N 5 CLK_EXP_P 5

CLK_BUF_EXP_N CLK_BUF_EXP_P

CLK_BUF_CPYCLK_N CLK_BUF_CPYCLK_P

CLK_BUF_DOT96_N CLK_BUF_DOT96_P

CLK_BUF_CKSSCD_N CLK_BUF_CKSSCD_P

CLK_BUF_REF14

XTAL25_IN XTAL25_OUT

XCLK_RCOMP

DGPU_PRSNT#

VRAM_SIZE3

1 2

R2007

R2007 90D9R2F-1-GP

90D9R2F-1-GP

EC_SWI# 27

DDR3 DIMM

DRAMRST_CNTRL_PCH 37

SML1_CLK 27 SML1_DATA 27

PEG_CLKREQ#_R

2 3 1

4

RN2008

RN2008 SRN10KJ-5-GP

SRN10KJ-5-GP

CLK_PCI_FB 18

1D05V_VTT

VRAM_SIZE3 22

2

KBC

2nd = 84.DM601.03F

3D3V_S5

12

check list: A 10K-ohm PU still need to be used

CLK_BUF_REF14 CLK_BUF_CKSSCD_P CLK_BUF_CKSSCD_N

2

3D3V_S0

SMB_DATA

Q2001

Q2001 2N7002KDW-GP

2N7002KDW-GP

84.2N702.A3F

SMB_CLK

R2004

R2004 10KR2J-3-GP

10KR2J-3-GP

3D3V_S0

4

1

2 3

Delete Pull down R

RN2009

RN2009 SRN10KJ-L3-GP

SRN10KJ-L3-GP

1 2 3 4 5 6

need very close to PCH

1

RN2007

RN2007 SRN2K2J-1-GP

SRN2K2J-1-GP

1 2 3

6 5

XTAL25_IN

XTAL25_OUT

RN2010

RN2010 SRN10KJ-5-GP

SRN10KJ-5-GP

DGPU_PRSNT#

4

1 2 34

R2006

R2006 1M1R2J-GP

1M1R2J-GP

1 2

SMB_CLK SMB_DATA

SML0_DATA SML0_CLK

SML1_CLK SML1_DATA

PCH_GPIO74 PCIE_CLK_REQ6#

DRAMRST_CNTRL_PCH

PCH_SMBDATA 14

PCH_SMBCLK 14

SC12P50V2JN-3GP

X2001

X2001 XTAL-25MHZ-102-GP

XTAL-25MHZ-102-GP

82.30020.851

2nd = 82.30020.791

1 2

SC12P50V2JN-3GP

UMA_DISCRETE# UMA: 1 1 DIS :0 1 SG(PX) : 0 0 Optimus(Muxless) : 1 0

UMA_DIS# 22

3D3V_S5

4

4 2 3

1 1

2 3

1 2

R2009

R2009 1KR2J-1-GP

1KR2J-1-GP

C2008

C2007

RN2003

1

SRN2K2J-1-GP

23

RN2004

23

SRN2K2J-1-GP

1

RN2005

RN2005 SRN2K2J-1-GP

SRN2K2J-1-GP

4

RN2006

4

SRN10KJ-5-GP

12

-SA Athero suggest PU 4.7K

PCIE_CLK_LAN_RQ#

R2003

1 2

4K7R2J-2-GP

2 3 1

RN2001

RN2001 SRN10KJ-5-GP

10

CLK_BUF_EXP_P

9

CLK_BUF_EXP_N

8

CLK_BUF_DOT96_N

7

CLK_BUF_DOT96_P

Title

PCH (PCI-E/SMBUS/CLOCK/CL)

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, April 17, 2012

Date: Sheet of

SRN10KJ-5-GP RN2002

RN2002 SRN10KJ-6-GP

SRN10KJ-6-GP

1 2 3 4 5

Hummingbird1_HR

CLK_PCIE_WWAN_REQ# USB3_PEGB_CLKREQ#

4

PCIE_CLK_REQ5#

8

CLK_PCIE_NEW_REQ#

7

EC_SWI#

6

PCH_GPIO24

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

PCH_GPIO24 22

20 102

3D3V_S5

-2

5

4

3

2

1

SSID = PCH

RTC_X1

1 2

R2101 10MR2J-L-GPR2101 10MR2J-L-GP

X2101

X2101 X-32D768KHZ-34GPU

X-32D768KHZ-34GPU

82.30001.661

D D

12

SC5P50V2CN-2GP

C C

+3VS_+1.5VS_HDA_IO

B B

+3VS_+1.5VS_HDA_IO

This signal has a weak internal pull down. On Die PLL VR is supplied by 1.5V when sampled high, 1.8 V when sampled low. Needs to be pulled High for Huron River platform. co-operate with R2310

A A

82.30001.661

2nd = 82.30001.B21

1

C2101

2 3

Freq tolertance :+/- 20 ppm

HDA_CODEC_SYNC29 HDA_CODEC_SDOUT29

HDA_CODEC_RST#29 HDA_CODEC_BITCLK29

1 2

5V_S0

HDA_CODEC_SYNC

4

CL = 7pF

DY

R2102

R2102 1KR2J-1-GP

1KR2J-1-GP

R2103

R2103 1KR2J-1-GP

1KR2J-1-GP

G

S

RTC_X2

12

C2102

C2102 SC5P50V2CN-2GP

SC5P50V2CN-2GP

R2122

R2122 33R2J-2-GP

33R2J-2-GP

R2123

R2123 33R2J-2-GP

33R2J-2-GP

1 2 3

RN2102

RN2102 SRN33J-5-GP-U

SRN33J-5-GP-U

Flash Descriptor Security Overide

HDA_SDOUT

HDA_SPKR

HDA_SYNC

D

Q2101

Q2101 2N7002K-2-GP

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

5

12

DY

12

4

No Reboot Strap

PLL ODVR VOLTAGE

HDA_SYNC_R HDA_SYNC

RTC_AUX_S5

2 3 1

4

C2104

12

C2103

C2103 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

21

12

G2101

G2101 GAP-OPEN

GAP-OPEN

RTC Reset

ME_UNLOCK27

DY

4

1 2

RN2104

RN2104 SRN20KJ-GP-U

SRN20KJ-GP-U

SC1U6D3V2KX-GP

HDA_SYNC HDA_SDOUT

HDA_RST# HDA_BITCLK

Low = Default High = Enable

Low = Default High = No Reboot

Low = 1.8V (Default) High = 1.5V

R2124

R2124 33R2J-2-GP

33R2J-2-GP

1 2

HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used to sample 1.5V VccVRM supply mode. 1K external pull-up resistor is required on this signal on the board. Signal may have leakage paths via powered off devices (Audio Codec) and hence contend with the external pull-up. A blocking FET is recommended in such a case to isolate HDA_SYNC from the Audio Codec device until after the Strap sampling is complete.

INTVRMEN- Integrated SUS

1.05V VRM Enable High - Enable internal VRs Low - Enable external VRs

RTC_AUX_S5

HDA_SPKR29

HDA_SDIN029

R2107

1 2

1KR2J-1-GP

SPI_CLK_R27,60 SPI_CS0#_R27,60

SPI_SI_R27,60

SPI_SO_R27,60

EC2102

SC4D7P50V2CN-1GP

DY

RTC_X1 RTC_X2 RTC_RST#

R2108

R2108 33R2J-2-GP

33R2J-2-GP

R2109

R2109 33R2J-2-GP

33R2J-2-GP

SC4D7P50V2CN-1GP

SRTC_RST# SM_INTRUDER#

12

PCH_INTVRMEN

HDA_BITCLK HDA_SYNC

HDA_RST#

PCH_JTAG_TCK_BUF

12

PCH_SPI_CLK PCH_SPI_CS0#

PCH_SPI_SI

1M1R2J-GP

R2104

1 2

R2105

330KR2F-L-GP

R2121

R2121 4K7R2J-2-GP

4K7R2J-2-GP

1 2 1 2

1 2

R2110 33R2J-2-GPR2110 33R2J-2-GP

EC2103

1 2

HDA_SDOUT

SPI_CS0#_RHDA_CODEC_BITCLK HDA_CODEC_SDOUT

EC2101

1 2

DY

1 OF 10

PCH1A

A20 C20 D20

G22

K22 C17

N34

L34 T10 K34

E34

G34

C34 A34

A36

C36 N32

J3 H7 K5 H1

T3

Y14

T1

V4 U3

COUGAR-GP-U2-NF

71.COUGA.00U

SC4D7P50V2CN-1GP

3

Cougar

RTCX1

Point

RTCX2 RTCRST# SRTCRST# INTRUDER# INTVRMEN

HDA_BCLK HDA_SYNC SPKR HDA_RST#

HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3

HDA_SDO

HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO13

JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO

SPI_CLK SPI_CS0# SPI_CS1#

SPI_MOSI SPI_MISO

RTCIHDA

JTAG

SPI

1 OF 10

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

LPC

FWH4/LFRAME#

LDRQ0#

LDRQ1#/GPIO23

SERIRQ

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN SATA1RXP

SATA 6G

SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN

SATA

SATA4TXP SATA5RXN

SATA5RXP SATA5TXN SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED# SATA0GP/GPIO21 SATA1GP/GPIO19

C38 A38 B37 C37

D36 E36

K36 V5

AM3 AM1 AP7 AP5

AM10 AM8 AP11 AP10

AD7 AD5 AH5 AH4

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11 Y10

AB12 AB13

AH1

P3 V14 P1

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

LPC_FRAME# 27,71

INT_SERIRQ 27

SATA_COMP

SATA3_COMP

RBIAS_SATA3

SATA_LED# SATA_DET#0

Strap pin ,Internal PU

SWAP pin from Page 22

2

LPC_AD[0..3] 27,71

check list:8.2K PU CRB :10K PU

SATA_RXN0 56 SATA_RXP0 56 SATA_TXN0 56 SATA_TXP0 56

SATA_RXN1 82 SATA_RXP1 82 SATA_TXN1 82 SATA_TXP1 82

R2112 37D4R2F-GPR2112 37D4R2F-GP

1 2

R2113 49D9R2F-GPR2113 49D9R2F-GP

1 2

R2114 750R2F-GPR2114 750R2F-GP

1 2

SATA_LED# 22

S_GPIO22

PCH_TEMP_ALERT#22,27

Title

PCH (SPI/RTC/LPC/SATA/IHDA)

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, April 17, 2012

Date: Sheet of

HDD1

M-SATA

1D05V_VTT

S_GPIO PCH_TEMP_ALERT# INT_SERIRQ SATA_DET#0

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Hummingbird1_HR

21 102

1

RN2103

RN2103 SRN10KJ-6-GP

SRN10KJ-6-GP

1 2 3 4 5

8 7 6

3D3V_S0

-2

5

4

3

2

1

3D3V_S0

RN2203

RN2203 SRN10KJ-5-GP

SRN10KJ-5-GP

1 2 3

GPIO27 has a weak[20K] internal pull up. To enable on-die PLL Voltage regurator, should not place external pull down.

D D

INTERNAL GFX EXTERNAL GFX

R2205 DY 10K

H_RCIN#

4

H_A20GATE

check list: if are unused,PU or PD

Note: For PCH debug with XDP, need to NO STUFF R2218

3D3V_S0

R2206 100K DY

C C

B B

GFX_CRB_DET

12

R2206

R2206 100KR2J-1-GP

100KR2J-1-GP

SWAP pin from Page 20

SATA_LED#21

SWAP pin from Page 20

PEG_B_CLKRQ#20

EC_SMI# EC_SCI# DGPU_HPD_INTR#

PSW_CLR# FP_DET# MFG_MODE

SATA_LED#

PEG_B_CLKRQ# USB3_PW R_ON PCH_GPIO12

PCH_GPIO15

Pass Word Clear

3D3V_S0

RN2201

RN2201 SRN10KJ-6-GP

SRN10KJ-6-GP

1

8

2

7

3

6

4 5

RN2202

RN2202 SRN10KJ-6-GP

SRN10KJ-6-GP

1

8

2

7

3

6

4 5

3D3V_S5

RN2204

RN2204 SRN10KJ-6-GP

SRN10KJ-6-GP

1

8

2

7

3

6

45

R2201

1 2

1KR2J-1-GP

PLL ON DIE VR ENABLE

VRAM Frequency Pull high: 800MHZ Pull low :900MHZ

3D3V_S0

12

R2218

R2218 10KR2J-3-GP

10KR2J-3-GP

A A

DY

12

PCH_GPIO22

R2219

R2219 10KR2J-3-GP

10KR2J-3-GP

4G

2G

12

R2214

10KR2J-3-GP

VRAM_SIZE4

12

R2221

10KR2J-3-GP

5

MICRON_ELPIDA

NOTE:This signal has a weak internal pull-up 20K

ENABLED -- HIGH (R2212 UNSTUFFED) DEFAULT DISABLED -- LOW (R2212 STUFFED)

3D3V_S0

12

R2220

10KR2J-3-GP

12

R2215

NANY_S/H

10KR2J-3-GP

12

R2216

ELPIDA_S/H

(GPIO70 Pin2)

10KR2J-3-GP

VRAM_SIZE1 VRAM_SIZE2

(GPIO71 Pin1)(GPIO48 Pin4) (GPIO65 Pin3)

12

R2217

MICRON_NANY

10KR2J-3-GP

3D3V_S0

12

10KR2J-3-GP

VRAM_SIZE3

12

10KR2J-3-GP

SSID = PCH

R2202

R2202 10KR2J-3-GP

10KR2J-3-GP

1 2

TPAD14-GP

PCH_GPIO2420

TPAD14-GP

PCH_TEMP_ALERT#21,27

R2230

DYRAM

R2231

RAM

4

S_GPIO21

EC_SCI#27

PSW_CLR#

21

G2201

G2201 GAP-OPEN

GAP-OPEN

VRAM_SIZE3 20

TP2204

TP2203

S_GPIO EC_SMI# DGPU_HPD_INTR#

ICC_EN# PCH_GPIO12 PCH_GPIO15

SATA_ODD_PRSNT#

DGPU_PW ROK

1

PCH_GPIO22

PCH_GPIO24

PCH_GPIO27

1

PLL_ODVR_EN

FP_DET# DMI_OVRVLTG FDI_OVRVLTG MFG_MODE GFX_CRB_DET VRAM_SIZE4 PCH_TEMP_ALERT# USB3_PW R_ON

PCH1F

T7

BMBUSY#/GPIO0

A42

TACH1/GPIO1

H36

TACH2/GPIO6

E38

TACH3/GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL/GPIO12

G2

GPIO15

U2

SATA4GP/GPIO16

D40

TACH0/GPIO17

T5

SCLOCK/GPIO22

E8

GPIO24/MEM_LED

E16

GPIO27

P8

GPIO28

K1

STP_PCI#/GPIO34

K4

GPIO35

V8

SATA2GP/GPIO36

M5

SATA3GP/GPIO37

N2

SLOAD/GPIO38

M3

SDATAOUT0/GPIO39

V13

SDATAOUT1/GPIO48

V3

SATA5GP/GPIO49

D6

GPIO57

A4

NCTF_VSS#A4

A44

NCTF_VSS#A44

A45

NCTF_VSS#A45

A46

NCTF_VSS#A46

A5

NCTF_VSS#A5

A6

NCTF_VSS#A6

B3

NCTF_VSS#B3

B47

NCTF_VSS#B47

BD1

NCTF_VSS#BD1

BD49

NCTF_VSS#BD49

BE1

NCTF_VSS#BE1

BE49

NCTF_VSS#BE49

BF1

NCTF_VSS#BF1

BF49

NCTF_VSS#BF49

COUGAR-GP-U2-NF

3

Cougar

Cougar Point

Point

NCTF TEST PIN:

A4,A44,A45,A46,A5,A6,B3,B47,BD1,BD49,BE1,BE49,BF1,BF49

BG2,BG48,BH3,BH47,BJ4,BJ44,BJ45,BJ46,BJ5,BJ6,C2,C48

GPIO

CPU/MISC

NCTF

D1,D49,E1,E49,F1,F49

6 OF 10

TACH4/GPIO68 TACH5/GPIO69 TACH6/GPIO70 TACH7/GPIO71

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

INIT3_3V#

TS_VSS1 TS_VSS2 TS_VSS3 TS_VSS4

NC_1

NCTF_VSS#BG2

NCTF_VSS#BG48

NCTF_VSS#BH3

NCTF_VSS#BH47

NCTF_VSS#BJ4 NCTF_VSS#BJ44 NCTF_VSS#BJ45 NCTF_VSS#BJ46

NCTF_VSS#BJ5

NCTF_VSS#BJ6

NCTF_VSS#C2

NCTF_VSS#C48

NCTF_VSS#D1

NCTF_VSS#D49

NCTF_VSS#E1

NCTF_VSS#E49

NCTF_VSS#F1

NCTF_VSS#F49

SATA_ODD_PWRGT

C40 B41

VRAM_SIZE1

C41

VRAM_SIZE2

A40

P4

H_PECI_R

AU16 P5 AY11

PCH_THERMTRIP_R

AY10 T14

AH8 AK11 AH10 AK10 P37

BG2 BG48 BH3 BH47 BJ4 BJ44 BJ45 BJ46 BJ5 BJ6 C2 C48 D1 D49 E1 E49 F1 F49

FDI_OVRVLTG

12

R2208

R2208 10KR2J-3-GP

10KR2J-3-GP

DMI_OVRVLTG

12

R2210

R2210 10KR2J-3-GP

10KR2J-3-GP

ICC_EN#

12

R2211

R2211 1KR2J-1-GP

1KR2J-1-GP

PLL_ODVR_EN

TP2205 TPAD14-GPTP2205 TPAD14-GP

1

UMA_DIS# 20

H_A20GATE 27

R2203

1 2

0R2J-2-GP

DY

H_RCIN# 27 H_CPUPW RGD 5,36,97

DY

PCH_THERMTRIP_R

design guide and CRB cirucit stuff 390-ohm JE40_HR stuff 54.9-ohm

TS Signal Disable Guideline: TS_VSS1, TS_VSS2, TS_VSS3 and TS_VSS4 should not float on the motherboard. They should be tied to GND directly.

H_PECI 5,27

R2204

1 2

390R2F-2GP

H_THERMTRIP# 5,36

FDI TERMINATION VOLTAGE OVERRIDE

GPIO37 (FDI_OVRVLTG)

LOW - Tx, Rx terminated to same voltage (DC Coupling Model DEFAULT)

DMI TERMINATION VOLTAGE OVERRIDE

GPIO36 (DMI_OVRVLTG)

Integrated Clock Enable functionality is achieved via soft-strap. The default is integrated clock enable.

LOW - Tx, Rx terminated to same voltage (DC Coupling Model DEFAULT)

Integrated Clock Chip Enable

ICC_EN#

HIGH (R2211 DY)- DISABLED [DEFAULT]

LOW (R2211)- ENABLED

GPIO8 has a weak[20K] internal pull up.

Integrated Clock Enable functionality is achieved via soft-strap. The default is integrated clock enable.

12

R2212

R2212 1KR2J-1-GP

1KR2J-1-GP

DY

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, April 17, 2012

Date: Sheet of

PCH (GPIO/CPU)

Hummingbird1_HR

Taipei Hsien 221, Taiwan, R.O.C.

22 102

1

-2

5

1D05V_VTT

12

C2301

1D05V_VTT

12

DY

C2301

C2306

SC10U6D3V5KX-1GP

SC1U6D3V2KX-GP

D D

C C

B B

12

C2302

12

C2307

3D3V_S0

SC1U6D3V2KX-GP

12

6A(total)

12

C2303

SC1U6D3V2KX-GP

12

C2308

SC1U6D3V2KX-GP

C2310

C2310 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

1D5V_S0

4

12

C2304

SC1U6D3V2KX-GP

1D05V_VTT

12

C2309

SC1U6D3V2KX-GP

230mA(Total)

1D05V_VTT

PCH1G

AA23

VCCCORE

AC23

VCCCORE

AD21

VCCCORE

AD23

VCCCORE

AF21

VCCCORE

AF23

VCCCORE

AG21

VCCCORE

AG23

VCCCORE

AG24

VCCCORE

AG26

VCCCORE

AG27

VCCCORE

AG29

VCCCORE

AJ23

VCCCORE

AJ26

VCCCORE

AJ27

VCCCORE

AJ29

VCCCORE

AJ31

VCCCORE

AN19

VCCIO

BJ22

VCCAPLLEXP

AN16

VCCIO

AN17

VCCIO

AN21

VCCIO

AN26

VCCIO

AN27

VCCIO

AP21

VCCIO

AP23

VCCIO

AP24

VCCIO

AP26

VCCIO

AT24

VCCIO

AN33

VCCIO

AN34

VCCIO

BH29

VCC3_3

AP16

VCCVRM

BG6

VCCAFDIPLL

AP17

VCCIO

AU20

VCCDMI

COUGAR-GP-U2-NF

POWER

Cougar

Cougar Point

Point

VCC CORE

VCCIO

FDI

3

7 OF 10

+VCCA_DAC_1_2

U48

VCCADAC

U47

CRTLVDS

DMI

NAND / SPI HVCMOS

VSSADAC

VCCALVDS

VSSALVDS

VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS

VCC3_3

VCCVRM

VCCDMI

VCCCLKDMI

VccDFTERM

VCCSPI

+3VS_VCCA_LVDS

AK36 AK37

AM37 AM38 AP36 AP37

V33

V34

12

C2319

C2319 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

AT16

170mA(Total)

AT20

AB36

75mA

AG16

AG17

AJ16

AJ17

SCD1U10V2KX-5GP

V1

12

3D3V_S0

12

C2320

C2320 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

+1.05VS_VCC_DMI_CCI

12

C2321

SC1U6D3V2KX-GP

12

C2326

C2323

C2323 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C2313

SCD01U16V2KX-3GP

12

C2316

1D5V_S0

1D05V_VTT

12

C2325

SC10U6D3V5KX-1GP

DY

12

C2322

C2322 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

3D3V_S5

12

C2314

SCD1U10V2KX-5GP

+1.8VS_VCCTX_LVDS

12

SCD01U16V2KX-3GP

L2303

L2303 IND-10UH-218-GP

IND-10UH-218-GP

1 2

68.10050.10Y

2nd = 68.10090.10B

1D8V_S0

C2317

C2318

SCD01U16V2KX-3GP

DY

1 2

R2315

1 2

0R0402-PAD

1 2

SC1U25V3KX-1-GP

1D05V_VTT

2

R23040R0603-PAD R23040R0603-PAD

R2305

R2305 0R5J-5-GP

0R5J-5-GP

1

3D3V_S0

12

1D8V_S0

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, April 17, 2012

Date: Sheet of

PCH (POWER1)

Hummingbird1_HR

Taipei Hsien 221, Taiwan, R.O.C.

23 102

1

-2

5

4

3

2

1

10 OF 10

POWER

PCH1J

SSID = PCH

(0.1uFx1)

(10uFx1) (1uFx1)

D D

C2402

SC1U10V2KX-1GP

1D05V_VTT

1.01A (Total current of VCCASW)

C2404

C2403

+VCCRTCEXT

12

1D05V_VTT

12

1D05V_VTT

RTC_AUX_S5

C2403

1 2

SC10U6D3V3MX-GP

0.16A (Totally current of VCCVRM

(0.1uFx1)

1D05V_VTT

0.055A

1D05V_VTT

(1uFx1)

0.001A

12

6uA

12

C2420

DY

SC1U6D3V2KX-GP

Change to 0603 package

C C

1D05V_VTT

B B

L2402

L2402 IND-10UH-218-GP

IND-10UH-218-GP

1 2

68.10050.10Y

2nd = 68.10090.10B

L2403

L2403 IND-10UH-218-GP

IND-10UH-218-GP

1 2

68.10050.10Y

2nd = 68.10090.10B

+1.05VS_VCCA_A_DPL+1.05VS_VCCA_A_DPL

+1.05VS_VCCA_B_DPL+1.05VS_VCCA_B_DPL

(1uFx1) (220uFx1)

12

C2409

C2409 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

(1uFx1) (220uFx1)

12

C2410

C2410 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C2411

SCD1U10V2KX-5GP

(1uFx1)

C2414

1D5V_S0

12

A A

5

C2421

SCD1U16V2KX-3GP

C2422

SCD1U16V2KX-3GP

C2414

SC1U6D3V2KX-GP

(0.1uFx2) (4.7uFx1_0603)

(0.1uFx2) (1uFx1)

3D3V_S5

3D3V_S0

12

C2406

C2407

SC1U6D3V2KX-GP

(22uFx2_0603)

(1uFx3)

C2412

C2412 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

1 2

C2413

C2413 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

1 2

12

C2417

SC4D7U6D3V3KX-GP

4

0.002A

1D05V_VTT

SC1U6D3V2KX-GP

C2418

AFR suggest DY Cayp to prevent leakage current

(10uFx1)

12

C2408

DY

SC1U6D3V2KX-GP

1D5V_S0

+1.05VS_VCCA_A_DPL +1.05VS_VCCA_B_DPL

(1uFx1)

0.095A

JE40 modify

(1uFx1)

+VCCSST

12

(0.1uFx1)

C2415

C2415 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

C2419

SCD1U10V2KX-5GP

DY

SCD1U10V2KX-5GP

PCH1J

AD49

T16

V12

T38

BH23 AL29

AL24

AA19 AA21 AA24 AA26 AA27 AA29 AA31 AC26 AC27 AC29 AC31 AD29 AD31

W21 W23 W24 W26 W29 W31 W33

N16

Y49

BD47 BF47

AF17 AF33 AF34

AG34

AG33

V16

T17 V19

BJ8

A22

COUGAR-GP-U2-NF

VCCACLK

VCCDSW3_3

DCPSUSBYP

VCC3_3

VCCAPLLDMI2 VCCIO

DCPSUS

VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW

DCPRTC

VCCVRM

VCCADPLLA VCCADPLLB

VCCIO VCCDIFFCLKN VCCDIFFCLKN VCCDIFFCLKN

VCCSSC

DCPSST

DCPSUS DCPSUS

V_PROC_IO

VCCRTC

POWER

Cougar

Cougar Point

Point

Clock and Miscellaneous

CPURTC

3

PCI/GPIO/LPCMISC

SATA USB

HDA

10 OF 10

VCCIO VCCIO VCCIO VCCIO VCCIO

VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3

VCCIO

V5REF_SUS

DCPSUS

VCCSUS3_3

V5REF

VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3

VCC3_3 VCC3_3 VCC3_3

VCC3_3

VCCIO

VCCIO VCCIO

VCCIO

VCCAPLLSATA

VCCVRM

VCCIO VCCIO VCCIO

VCCASW

VCCSUSHDA

1D05V_VTT

N26 P26 P28 T27 T29

0.097A (Totally current of VCCSUS3_3)

T23 T24 V23 V24 P24

T26

M26

AN23 AN24

P34

N20 N22 P20 P22

AA16 W16 T34

SCD1U10V2KX-5GP

AJ2

AF13

AH13 AH14

AF14 AK1

AF11

AC16 AC17 AD17

T21

V21

T19

P32

12

1D05V_VTT

+5VA_PCH_VCC5REFSUS

3D3V_S5

+5VS_PCH_VCC5REF

C2430

1D5V_S0

1D05V_VTT

+3VS_+1.5VS_HDA_IO

0.01A

(1uFx1)

C2423

C2423 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

3D3V_S5

(1uFx1)

12

C2428

C2428 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

3D3V_S0

12

C2429

C2429 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

C2432

C2432 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

1D05V_VTT

(1uFx1)

12

C2435

C2435 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

(0.1uFx1)

12

C2433

C2433 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

C2424

C2424 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

C2425

C2425 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

(0.1uFx2)

12

C2431

C2431 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

3D3V_S0

1D05V_VTT

(0.1uFx1)

(1uFx1)

2

3D3V_S5

(0.1uFx1)

3D3V_S5

(0.1uFx1)

0.001A

3D3V_S5

D2401

D2401 CH751H-40PT-GP

CH751H-40PT-GP

21

83.R0304.A8F

2nd = 83.R2004.B8F

1 2

R2408

R2408 10R2J-2-GP

10R2J-2-GP

12

C2426

C2426 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

3D3V_S0

D2402

D2402 CH751H-40PT-GP

CH751H-40PT-GP

21

83.R0304.A8F

2nd = 83.R2004.B8F

DY

1 2

R2407

R2407 10R2J-2-GP

12

+3VS_+1.5VS_HDA_IO

R2409 0R3J-0-U-GPR2409 0R3J-0-U-GP

R2415 0R3J-0-U-GP

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, April 17, 2012

Date: Sheet of

PCH (POWER2)

Hummingbird1_HR

10R2J-2-GP

C2427

C2427 SC1U10V2KX-1GP

SC1U10V2KX-1GP

1 2

DY

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

5V_S5

(0.1uFx1)

5V_S0

24 102

1

(1uFx1)

3D3V_S5

1D5V_S0

-2

5

4

3

2

1

SSID = PCH

D D

C C

B B

A A

5

PCH1H

H5

VSS

AA17

VSS

AA2

VSS

AA3

VSS

AA33

VSS

AA34

VSS

AB11

VSS

AB14

VSS

AB39

VSS

AB4

VSS

AB43

VSS

AB5

VSS

AB7

VSS

AC19

VSS

AC2

VSS

AC21

VSS

AC24

VSS

AC33

VSS

AC34

VSS

AC48

VSS

AD10

VSS

AD11

VSS

AD12

VSS

AD13

VSS

AD19

VSS

AD24

VSS

AD26

VSS

AD27

VSS

AD33

VSS

AD34

VSS

AD36

VSS

AD37

VSS

AD38

VSS

AD39

VSS

AD4

VSS

AD40

VSS

AD42

VSS

AD43

VSS

AD45

VSS

AD46

VSS

AD8

VSS

AE2

VSS

AE3

VSS

AF10

VSS

AF12

VSS

AD14

VSS

AD16

VSS

AF16

VSS

AF19

VSS

AF24

VSS

AF26

VSS

AF27

VSS

AF29

VSS

AF31

VSS

AF38

VSS

AF4

VSS

AF42

VSS

AF46

VSS

AF5

VSS

AF7

VSS

AF8

VSS

AG19

VSS

AG2

VSS

AG31

VSS

AG48

VSS

AH11

VSS

AH3

VSS

AH36

VSS

AH39

VSS

AH40

VSS

AH42

VSS

AH46

VSS

AH7

VSS

AJ19

VSS

AJ21

VSS

AJ24

VSS

AJ33

VSS

AJ34

VSS

AK12

VSS

AK3

VSS

COUGAR-GP-U2-NF

Cougar

Cougar Point

Point

8 OF 10

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28

4

PCH1I

AY4

VSS

AY42

VSS

AY46

VSS

AY8

VSS

B11

VSS

B15

VSS

B19

VSS

B23

VSS

B27

VSS

B31

VSS

B35

VSS

B39

VSS

B7

VSS

F45

VSS

BB12

VSS

BB16

VSS

BB20

VSS

BB22

VSS

BB24

VSS

BB28

VSS

BB30

VSS

BB38

VSS

BB4

VSS

BB46

VSS

BC14

VSS

BC18

VSS

BC2

VSS

BC22

VSS

BC26

VSS

BC32

VSS

BC34

VSS

BC36

VSS

BC40

VSS

BC42

VSS

BC48

VSS

BD46

VSS

BD5

VSS

BE22

VSS

BE26

VSS

BE40

VSS

BF10

VSS

BF12

VSS

BF16

VSS

BF20

VSS

BF22

VSS

BF24

VSS

BF26

VSS

BF28

VSS

BD3

VSS

BF30

VSS

BF38

VSS

BF40

VSS

BF8

VSS

BG17

VSS

BG21

VSS

BG33

VSS

BG44

VSS

BG8

VSS

BH11

VSS

BH15

VSS

BH17

VSS

BH19

VSS

H10

VSS

BH27

VSS

BH31

VSS

BH33

VSS

BH35

VSS

BH39

VSS

BH43

VSS

BH7

VSS

D3

VSS

D12

VSS

D16

VSS

D18

VSS

D22

VSS

D24

VSS

D26

VSS

D30

VSS

D32

VSS

D34

VSS

D38

VSS

D42

VSS

D8

VSS

E18

VSS

E26

VSS

G18

VSS

G20

VSS

G26

VSS

G28

VSS

G36

VSS

G48

VSS

H12

VSS

H18

VSS

H22

VSS

H24

VSS

H26

VSS

H30

VSS

H32

VSS

H34

VSS

F3

VSS

COUGAR-GP-U2-NF

3

Cougar

Cougar Point

Point

9 OF 10

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, April 17, 2012

Date: Sheet of

2

Date: Sheet of

PCH (VSS)

Hummingbird1_HR

Taipei Hsien 221, Taiwan, R.O.C.

25 102

1

-2

5

D D

C C

4

3

2

1

Blanking

B B

Wistron Corporation

A A

Title

Clock(colay)

Size Document Number Rev

Size Document Number Rev A4

A4

Tuesday, April 17, 2012

Date: Sheet of

5

4

3

Date: Sheet of

2

Clock(colay)

Hummingbird1_HR

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

-2

26 102

1

-2

3D3V_AUX_KBC

12

C2704

C2701

D D

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

Check KBC

C C

0604 Modify: RN2704 pull-Low 10K Resistor to DY on BLUETOOTH_EN.

3D3V_S0

1 2

B B

3D3V_AUX_KBC

1 2 3

EC_GPIO47 High Active

PROCHOT _EC

12

R2732

100KR2J-1-GP

A A

100KR2J-1-GP

5

SSID = KBC

12

C2706

C2707

SCD1U10V2KX-5GP

AD_IA82

C2714 SCD 1U10V2KX-5GP

1 2

DY

PCB_VER_AD

D

ADT_TYPE

EC_GPIO6

AC_IN# EC_GPIO72

DISCRETE#

KBC_VCORF

12

C2712

C2712 SC1U10V3ZY-6GP

SC1U10V3ZY-6GP

PURE_HW _SHUTDO WN#28,36

EC_SPI_DI_C

12

R2773

R2773 100KR2J-1-GP

100KR2J-1-GP

H_PROCHO T#_EC

T8_THERM28 HW_RF _Kill82

SUS_PWR _ACK19

SYS_THRM28

ALL_POWER _OK37,42,48

DC_BATFU LL82

AD_OFF82

GPI_SENSE65

S5_ENABLE36,97

BAT_IN#82

LID_CLOSE#70

RSMRST#_KBC19

PM_SLP_S4#19,46

ME_UNLOCK21

DBC_EN49

WIFI_RF_EN82 BLUETOOTH _EN82 S0_PWR_GO OD19,42

USB_PWR _EN#61

AC_PRESENT19

R2776

R2776 10KR2J-3-GP

10KR2J-3-GP

SB LID_CLOSE# can not pull high, because push pull suggest RN2708 Pin5 change FAN_TACH1

RN2707

RN2707 SRN100KJ-6-G P

SRN100KJ-6-G P

R2770

1KR2J-1-GP

1 2

FAN_TACH 1 28

CHG_ON#

4

STOP_CHG#

AD_OFF

G

S

Q2702

Q2702 2N7002K-2-GP

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

5

12

C2710

SCD1U10V2KX-5GP

U2701A

U2701A NPCE795PA0DX -GP-U

NPCE795PA0DX -GP-U

R2733

R2733 0R0402-PAD

0R0402-PAD

1 2

104

97 98 99

100 101

105 106

79 95 96

108

93 94

114 109

14 15 80 17 20 21 23 26 73 74 75 82 83 84

91 110 112 107

44

RSMRST#_KBC

12

VCC19VCC46VCC76VCC88VCC VREF GPIO90/AD0

GPIO91/AD1 GPIO92/AD2 GPIO93/AD3

GPIO94/DA0 GPIO95/DA1 GPIO96/DA2

GPIO2 GPIO3/AD6 GPIO4/AD5 GPIO5/AD4 PSL_IN2#_GPIO6 GPIO7/AD7 GPIO16

6

GPIO24 GPIO30 GPIO34/CIRRXL GPIO36 GPIO41 GPIO42/TCK GPIO43/TMS GPIO44/TDI GPIO46/CIRRXM/TRST# GPIO51 PSL_IN1_GPIO70 PSL_OUT_GPIO71 VBKUP GPIO75 GPO76/SHBM GPIO77 GPIO81 GPO82/IOX_LDSH/TEST# GPIO84/IOX_SCLK/XORTR# GPIO97

VCORF

GND18GND45GND78GND89GND

NOTE: Connect GND and AGND planes via either 0R resistor or one point layout connection.

2 3 1

R2777

R2777 100KR2J-1-GP

100KR2J-1-GP

H_PROCHO T# 5,42

115

GND

5

116

RN2709

RN2709 SRN10KJ-5-G P

SRN10KJ-5-G P

EC_SWI#20

EC_SCI#22

4

3D3V_S0

12

C2702

SCD1U10V2KX- 5GP

C2711

C2711 SC220P50V2KX-3GP

LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

ECSCI#_KBC ECSWI#_KBC

PROCHOT _EC

E

B

C

ECSWI#_KBC

ECSCI#_KBC

ECRST#

SC220P50V2KX-3GP

1 2

DY

R2735

1 2

0R0402-PAD

CHG_ON# 82

R2737 0R2J-2-GPR 2737 0R2J-2-GP R2722 33R2J-2-GPR2722 33R2J- 2-GP

12

C2715

SC1U6D3V2KX-GP

DY

N/A65W

100.0K

10.0K

20.0K

47.0K

64.9K

INT_SERIRQ 21 PM_CLKRUN # 19

PANEL_BLEN 17 PCH_TEMP_ALE RT# 21,22 H_A20GATE 22

H_RCIN# 22

BLON_OUT 49

TPDATA 69 TPCLK 69

BAT_SCL 82 BAT_SDA 82 SML1_CLK 20 SML1_DATA 20

12 12 12 12

102

4

1 OF 2

VDD

AVCC

GPIO11/CLKRUN#

GPIO65/SMI#

ECSCI#/GPIO54

GPIO10/LPCPD#

GPIO67/PWUREQ#

GPIO85/GA20

KBRST#/GPIO86

GPIO52/PSDAT3/RDY#

GPIO50/PSCLK3/TDO

GPIO27/PSDAT2

GPIO26/PSCLK2

GPIO35/PSDAT1

GPIO37/PSCLK1

GPIO17/SCL1 GPIO22/SDA1 GPIO73/SCL2 GPIO74/SDA2 GPIO23/SCL3 GPIO31/SDA3 GPIO47/SCL4 GPIO53/SDA4

F_SDI/F_SDIO1

F_SDIO/F_SDIO0

3D3V_AUX_S5

PURE_HW _SHUTDO WN#_RPURE_HW_SHUT DOWN #_R

4

PLT_RST#_EC

7

LRESET#

2

LCLK

3

LFRAME#

1

LAD3

128

LAD2

127

LAD1

126

LAD0

125

SERIRQ

8 9 29 124 123 121 122

27 25 11 10 71 72

70 69 67 68 119 120 24 28

EC_SPI_CS#_C

90

F_CS0#

EC_SPI_CLK_C

92

F_SCK

EC_SPI_DI_C

86

EC_SPI_DO_C

87

AGND

103

NOTE: Locate resistors R2719 and R2722 close to the NPCE791L.

Q2701

Q2701 MMBT3906-4-GP

MMBT3906-4-GP

84.T3906.A11

2nd = 84.03906.F11

R2758

1 2

0R0402-PAD

R2759

1 2

0R0402-PAD

ADT_TYPE A/D(PIN99) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

90W 30W

40W 120W 0.82V33.0K Reserved

PLT_RST# 5,18,36,71,82,9 7

CLK_PCI_KBC 18

LPC_FRAME# 21,71

LPC_AD[0..3] 21,71

<------ TP

<------ BATTERY / CHARGER <------PCH / EDP

33R2J-2-GPR2736 33R2J-2-GPR2736 33R2J-2-GPR2719 33R2J- 2-GPR2719

PCB_VER_AD

SPI_CS0#_R 21,60 SPI_CLK_R 21,60

SPI_SO_R 21,60

SPI_SI_R 21,60

PURE_HW _SHUTDO WN#

100.0K N/A

100.0K

4

3

3D3V_AUX_KBC

12

R2724

R2724 76K8R2F-GP

76K8R2F-GP

PCB VERSION

12

R2726

R2726 100KR2F-L1-GP

100KR2F-L1-GP

PCB VERSION A/D(PIN98) PULL-LOW RESISTOR

U2702

U2702 G690L293T73UF-G P

G690L293T73UF-G P

74.00690.I7B

1

DY

GND

VCC

2

RESET#

Prevent BIOS data loss

BLUETOOTH _EN

1 2

DY

R2774

R2774 10KR2J-3-GP

10KR2J-3-GP

0604 Modify: RN2704 pull-Low 10K Resistor to DY on BLUETOOTH_EN.

3.3V 0V

0.3V

0.55V

1.06V

1.3VReserved 100.0K

3

SA SB SC

-1

-1M

-2

-3M

-1M For PCH B3

STDBY_LED82

PCH_SUSCL K_KBC19

H_PECI5,22

1D05V_VTT

C2716 need very close to EC

3D3V_AUX_S5

3

65W_90W# High: 65W / Low 40W DISCRETE# High: UMA / Low: Discrete

100.0K

PULL-HIGH RESISTOR VOLTAGE

10.0K

20.0K

33.0K

47.0K

64.9K

76.8 100K

143.0K

174.0K

FAN_TACH 128

PM_PWRBT N#19,97

PM_SLP_S3#19,29,36,37,47 CHARGE_LED82

KBC_BEEP29

BRIGHTNESS49

STOP_CHG#82

FAN1_PWM28

STDBY_LED

PWRLED82

AMP_MUTE#29AC_IN#82

R2721 43R2J-GPR2721 43R2J-GP

1 2

R2720

1 2

0R0402-PAD

ECRST#

E51_RxD82

E51_TxD82

AMP_MUTE#

PECI EC_VTT

12

C2716

EC GPIO standard PH/PL

3D3V_AUX_KBC

RN2701

RN2701 SRN4K7J-8-G P

SRN4K7J-8-G P

2 3 1

R2775

RN2705

SRN10KJ-5-G P

2 3 1

R2769

100KR2J-1-GP

ADT_TYPE DISCRETE#

SCD1U16V2KX-3GP

390KR2F-GP

4

12

4

12

31

117

63 64

32

118

62 65 81 66 22 16

85

113 111

30 77

13 12

BAT_SCL BAT_SDA

BAT_IN#

S5_ENABLE

2

3.0V

2.75V

2.48V

2.24V

2.0V

1.87V

1.65V-3

1.358V

1.204V

U2701B

U2701B NPCE795PA0DX -GP-U

NPCE795PA0DX -GP-U

GPIO56/TA1 GPIO20/TA2 GPIO14/TB1 GPIO01/TB2

GPIO15/A_PWM GPIO21/B_PWM GPIO13/C_PWM GPIO32/D_PWM GPIO66/G_PWM GPIO33/H_PWM GPIO45/E_PWM GPIO40/F_PWM

VCC_POR#

GPIO87/CIRRXM/SIN_CR GPIO83/SOUT_CR/TRIST#

GPIO55/CLKOUT/IOX_DIN_DIO GPIO00/EXTCLK

PECI VTT

ECRST#

AC_IN#

Delete DIS_UMA

3D3V_AUX_KBC

10KR2J-3-GP

12

R2707

100KR2F-L1-GP

65W

12

R2708

100KR2F-L1-GP

40W

2

2 OF 2

KBSOUT0/JENK#

KBSOUT1/TCK KBSOUT2/TMS

KBSOUT3/TDI

KBSOUT4/JEN0#

KBSOUT5/TDO

KBSOUT6/RDY#

KBSOUT7

KBSOUT8 KBSOUT9/SDP_VIS# KBSOUT10/P80_CLK

KBSOUT11/P80_DAT

KBSOUT12/GPIO64 KBSOUT13/GPIO63 KBSOUT14/GPIO62

KBSOUT15/GPIO61/XOR_OUT

GPIO60/KBSOUT16 GPIO57/KBSOUT17

KBSIN0 KBSIN1 KBSIN2 KBSIN3 KBSIN4 KBSIN5 KBSIN6 KBSIN7

12

R2710

1

KCOL0

53

KCOL1

52

KCOL2

51

KCOL3

50

KCOL4

49

KCOL5

48

KCOL6

47

KCOL7

43

KCOL8

42

KCOL9

41

KCOL10

40

KCOL11

39

KCOL12

38

KCOL13

37

KCOL14

36

KCOL15

35 34 33

KROW0

54

KROW1

55

KROW2

56

KROW3

57

KROW4

58

KROW5

59

KROW6

60

KROW7

61

PSL SOLUTION (Power Switch Control Logic)

KBC_PWR BTN#29,82

KCOL[0..15] 69

KROW[0..7] 69

3D3V_AUX_KBC

R2772

1 2

0R0402-PAD

3D3V_AUX_S5

NO PSL SOLUTION

EC_GPIO72

R2756

RTC_AUX_S5

3D3V_AUX_S5

HR PX

Title

Size Document Number Rev

Size Document Number Rev A2

A2

Tuesday, April 17, 2012

Date: Sheet of

1 2

0R0402-PAD

1 2

DY

R2760

R2760 0R2J-2-GP

0R2J-2-GP

3D3V_AUX_S5

R2704

R2704 330KR2J-L1-GP

330KR2J-L1-GP

1 2

KBC_PWR BTN#R

12

R27800R 0603-PAD R27800R0603-PAD

GAP-OPEN

R2757

G2701

470R2J-2-GP

2 1

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

KBC Nuvoton NPCE795

Hummingbird1_HR

EC_GPIO6

12

C2717

SC220P50V2KX-3GP

DY

27 102

-2

1

5

4

3

2

1

SSID = Thermal

3D3V_S0

12

C2802

D D

Layout notice : Both DXN and DXP routing 10 mil trace width and 10 mil spacing.

12

2ND = 84.03904.P11

3

84.03904.L06

R2808

DY

C C

84.03904.L06

NTC-100K-8-GP

Q2801

1

PMBS3904-1-GP

2

2.System Sensor, Put on palm rest

P2800_DXP

12

C2806

C2806 SC470P50V3JN-2GP

SC470P50V3JN-2GP

P2800_DXN

12

C2807

SC2200P50V2KX-2GP

Thermal sensor P2800

3D3V_S0

SCD1U10V2KX-5GP

ADJ

12

C2805

P2800EB0-GP

VCC DXP DXN OTZ

DY

TDR

GND

U2801

C2805

TDL ADJ

R2804

0R2J-2-GP

DY

3D3V_S0

5 6

THERM_SYS_SHDN# ADJ

7 8

74.02800.B71

1.H/W T8 Shutdown

12

R2827

R2827 0R2J-2-GP

0R2J-2-GP

DY

-SA thermal setting H/W shutdown 90-degree

SCD1U10V2KX-5GP

4 3 2 1

SYS_THRM 27 T8_THERM 27

*Layout* 15 mil

21

D2802

D2802 CH551H-30PT-GP

CH551H-30PT-GP

83.R5003.C8F

2ND = 83.R5003.H8H

3rd = 83.5R003.08F

FAN_TACH127

21

D2801

D2801 CH551H-30PT-GP

CH551H-30PT-GP

83.R5003.C8F

2ND = 83.R5003.H8H

3rd = 83.5R003.08F

FAN_TACH1_C

FAN1_PW M27

1 2

R2806

R2806 0R0402-PAD

0R0402-PAD

5V_S0

C2809

SC4D7U6D3V3KX-GP

ACES-CON4-5-GP

12

C2808

4 3 2

1

12

FAN1_PW M_R FAN_TACH1_C

5V_S0

For PWM FAN

SCD1U10V2KX-5GP

FAN1

6

5

2nd = 20.F1261.004

20.F0866.004

[Rev B]

3D3V_S0

12

R2809

R2809 100KR2J-1-GP

100KR2J-1-GP

B B

PURE_HW _SHUTDOWN#27,36

A A

5

4

3

DY

12

R2812

12

C2811

10KR2J-3-GP

SCD1U10V2KX-5GP

DY

D

Q2802

Q2802 2N7002K-2-GP

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

2

THERM_SYS_SHDN#

S

G

HR PX

Title

Thermal P2800/Fan Controllor P2793

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet of

Date: Sheet of

R2810

R2810 0R2J-2-GP

0R2J-2-GP

1 2

DY

Tuesday, April 17, 2012

3D3V_S0

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Hummingbird1_HR

1

IMVP_PWRGD 36,42

28 102

-2

5

U2902

AUD_AGND

1

EN

2

GND VIN3VOUT

G9090-475T12U-GP

74.09090.F3F

HDA_CODEC_BITCLK21

HDA_CODEC_SDOUT21

R2926

R2926 0R2J-2-GP

0R2J-2-GP 0R2J-2-GP

0R2J-2-GP

1 2 1 2

R2930

DIGITAL

(include thermal pad) Spilt by DGND

12

C2910

SCD1U10V2KX-5GP

ALC271X-VB3-GR-GP

71.00271.A03

PM_SLP_S3#19,27,36,37,47

D D

C C

B B

5V_S5

12

C2927

SC1U10V2KX-1GP

if use LDO,have to PVDD have been ramp up after AVDD,if not,might occur issue

PM_SLP_S3# driver strength is insufficient,if no stuff,waveform will abnormally when S3 mode

DMIC_CLK58 DMIC_DATA58

AUD_SPK_R+82

AUD_SPK_R-82

AUD_SPK_L-82

AUD_SPK_L+82

5VA_S0

CLOSE TO PIN38

5

NC#5

4

HDA_SDIN021

EAPD PD#

DMIC_CLK_R

EAPD

5V_S0

AUD_AGND

U2901

CLOSE TO PIN35

C2911

SC2D2U10V3KX-1GP

1 2

CLOSE TO PIN34

C2912

A A

5

AUD_AGND

AUD_HP1_JACK_R258 AUD_HP1_JACK_L258

12

SC2D2U10V3KX-1GP

2 3 1

5VA_S0

12

C2928

AUD_AGND

R2924

1 2

180R2F-1-GP

49

GND

48

SPDIFO

47

EAPD

46

PVDD2

45

SPK-OUT-R+

44

SPK-OUT-R-

43

PVSS2

42

PVSS1

41

SPK-OUT-L-

40

SPK-OUT-L+

39

PVDD1

38

AVDD2

37

AVSS2

SRN47J-7-GP

RN2904

4

-SA

SC10U10V5KX-2GP

CLOSE TO PIN1 and 9

R2915

1 2

22R2J-2-GP

R2914

1 2

0R2J-2-GP

3D3V_S0

1

2

3

4

5

PD#

DVDD

GPIO1/DMIC-CLK

GPIO0/DMIC-DATA

1.3A 100mA

CBP36CBN35CPVEE34HPOUT-R/PORT-I-R33HPOUT-L/PORT-I-L32MIC1-VREFO-L31MIC1-VREFO-R30MIC2-VREFO29LDO-CAP28VREF27AVSS126AVDD1

CPVEE

AUD_CBN

AUD_CBP

HP_OUT_R_AUD

HP_OUT_L_AUD

4

12

C2903

ACZ_BITCLK_AUDIO_+

6

7

8

BCLK

DVSS

SDATA-OUT

100mA

3D3V_S0

12

C2904

SC10U6D3V3MX-GP

SCD1U10V2KX-5GP

AUD_3VD_R

AC97_DATIN

AUDIO_PC_BEEP

9

10

11

12

SYNC

RESET#

PCBEEP

DVDD-IO

SDATA-IN

SENSE_A

LINE2-L/PORT-E-L

LINE2-R/PORT-E-R

MIC2-L/PORT-F-L

MIC2-R/PORT-F-R

SENSE_B

MONO-OUT

MIC1-L/PORT-B-L MIC1-R/PORT-B-R LINE1-L/PORT-C-L

LINE1-R/PORT-C-R

ANALOG

25

MIC2V

VREF

LDO_CAP_AUDIO

AUD_AGND

MIC2V

12

DY

JDREF

5VA_S0

12

R2925

R2925 0R2J-2-GP

0R2J-2-GP

1 2

R2902

R2902 0R2J-2-GP

0R2J-2-GP

1 2

DY

HDA_CODEC_SYNC 21

HDA_CODEC_RST# 21

C2909

SC22P50V2JN-4GP

ALC268_SENSE_A

13 14 15 16 17 18 19 20 21 22 23 24

AUD_AGND

C2913

SCD1U10V2KX-5GP

3

5V_S0

12

C2906

SC10U6D3V3MX-GP

CLOSE TO PIN39 and 46

3D3V_S0

1D5V_S0

R2907 39K2R2F-L-GPR2907 39K2R2F-L-GP

1 2

MIC2-L_PORT-B MIC2-R_PORT-B ALC268_SENSE_B

JDREF

12

R2909

R2909 20KR2F-L-GP

20KR2F-L-GP

C2920 SC2D2U10V3KX-1GPC2920 SC2D2U10V3KX-1GP

1 2

C2919 SC2D2U10V3KX-1GPC2919 SC2D2U10V3KX-1GP

1 2

R2920

1 2

20KR2F-L-GP

CLOSE TO PIN19

C2916

1 2

SCD1U10V2KX-5GP

1 2

3

12

C2907

SCD1U10V2KX-5GP

AUDIO_PC_BEEP

Delete R/C Sa

COMBO_MIC_JD#

AUD_AGND

C2914

C2914 SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

R2922

R2922 2D2R3J-2-GP

2D2R3J-2-GP

DY

G2901

1 2

GAP-CLOSE

G2903

1 2

GAP-CLOSE

12

C2921

SC1U6D3V2KX-GP

COMBO_MIC

AUD_HP1_JD# 58

DY

AUD_AGND

1 2

CLOSE TO PIN18

AUD_AGND

12

AUD_AGND

1st = 63.R0034.1DL

12

C2922

R2906

SC100P50V2JN-3GP

4K7R2J-2-GP

R2919

1 2

22K1R2F-L-GP

COMBO_MIC_R

PD#

2

12

EC2908

EC2905

2

SCD1U10V2KX-5GP

1st = 63.R0034.1DL

RN2901

RN2901 SRN47K-2-GP-U

SRN47K-2-GP-U

4

COMBO_MIC_QDMIC_DATA_R

C2915

C2926

1 2

AUD_AGND

SC10U6D3V5KX-1GP

1 2

D2901

D2901 BAW56-5-GP

BAW56-5-GP

83.00056.Q11

2nd = 83.00056.K11

1

EMI ASK to change to 0R 0812

12

EC2917

SCD1U10V2KX-5GP

1st = 63.R0034.1DL

KBC_BEEP_1AUDIO_BEEP

1

SPKR_SB_1

23

D

G

TVL-0402-01-AB1-GP

12

AUD_AGND

83.00402.0A0

R2929

1KR2F-3-GP

3

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet of

Date: Sheet of

EC2923

EC2918

COMBO_MIC_JD#

AUD_AGND

1

2

Tuesday, April 17, 2012

SCD1U10V2KX-5GP

1st = 63.R0034.1DL

R2904

R2904 0R0402-PAD

0R0402-PAD

1 2

R2905

R2905 0R0402-PAD

0R0402-PAD

Q2901

Q2901 BSS138-8-GP

BSS138-8-GP

84.00138.H31

ESD protection: 2KV

Max Vgs(th) 1.8V

S

MIC2V Ref voltage is 2.5V becasue Vgs(th)concern cann't use 2N702 for desing

R2917

R2917 2K2R2J-2-GP

2K2R2J-2-GP

1 2

12

R2927

R2927 22K1R2F-L-GP

22K1R2F-L-GP

AUD_AGND

2

AMP_MUTE#_R

1

D2902

D2902 BAS16-6-GP

BAS16-6-GP

83.00016.K11

2ND = 83.00016.F11

3

Audio Codec

Hummingbird1_HR

KBC_BEEP 27

HDA_SPKR 21

MIC2V

COMBO_MIC 58

PM_SLP_S3# 19,27,36,37,47

R2928 0R2J-2-GPR2928 0R2J-2-GP

1 2

KBC_PW RBTN# 27,82

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

29 102

1

AMP_MUTE# 27

-2

5

4

3

2

1

AUDIO OP AMPLIFIER

D D

C C

Blanking

B B

Wistron Corporation

A A

Title

Audio AMP

Size Document Number Rev

Size Document Number Rev A4

A4

Tuesday, April 17, 2012

Date: Sheet of

5

4

3

Date: Sheet of

2

Audio AMP

Hummingbird1_HR

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

-2

30 102

1

-2

Acer aspire s3-951 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual