Acer Aspire One 522 Schematics

ZZZ1

ZZZ2

PCB

M/B

M/B DAZ@

DAZ@

11/18 ZZZ2 for DAZ P/N:DAZ0IV00101

1 1

ZZZ1

LA-7072P

M/B

M/B DA@

DA@

ZZZ3

LS-7072P

LED/B

LED/B DA@

DA@

ZZZ4

LS-7073P

TP/B

TP/B DA@

DA@

11/18 LA-7072P P/N from DA60000LA00 to DA60000LA10 LS-7072P P/N from DA40000Z300 to DA40000Z310 LS-7073P P/N from DA40000Z400 to DA40000Z410

11/22 LS-7073P P/N from DA40000Z410 to DA20000Z410

Compal Confidential

2 2

P0VE6 LA7072P Schematics Document

AMD Ontario Processor with DDRIII + Hudson M1

10.1" M/B

3 3

2010-11-18

Rev : 1.0

4 4

Security Classifica tion

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

http://laptop-motherboard-schematic.blogspot.com/

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/12 2012/08/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Cover Page

P0VE6 Schematics

136Monday, November 22, 2010

1.0

Compal Confidential

Model Name : P0VE6 / P0VH6

Brazos Platform

File Name : LA-7072P

1 1

HDMI RGB LVDS

HDMI Conn.

Page 9

2 2

Fan Circuit

PWM

D-Sub Conn.

Page 10

Page 26

LVDS Conn.

Page 8

PCI-Express X3

100MHz

Port 1

WWAN

JMINI1

WLAN

JMINI2

Media processor Wireless Card

Port 1

Page 19

3 3

Port 3 Port 2

Page 20

PCIE Gen1 2.5GT/S

Port 2Port 3

LAN(10/100mbE)

AR8152

Page 17

RJ-45

Page 17

AMD

Ontario FT1

APU

BGA 413-Ball

19mm X 19mm

UMI x4 Gen.1

2.5GT/s per Lane

AMD

Hudson M1

FCH

BGA 605-Ball

23mm X 23mm

Page 11,12,13,14,15

LPC

33MHz

ENE KB930

Page 25

Page 4,5,6

Memory Bus (DDRIII)

Single Channel

1.5V DDRIII 800/1066

6.4G/8.5G

100M/133M

USB Conn.x1

(Right Side) Port 2

Page 24

USB

HD Audio

SATA

Gen1 1.5GT/S ,Gen2 3GT/S

USB Conn.x2

(Left Side) Port 0, 1

3.3V 48MHz

3.3V 24MHz

HDD

Small Board

204 Pin DDRIII SO-DIMM x1

BANK 0, 1, 2, 3

Page 7

Camera Bluetooth

Port 5

Page 24 Page 19 Page 18

Page 8

100MHz

Port 7

Card Reader

ENE 6250 / 6252

Port 6

3G Card

Port 3

(2.5") Port 0

Page 21

HDA Codec+AMP

CX20584

Page 19

Page 16

LED/B

LS-7072P

TP BTN/B

LS-7073P

HP Jack x1 MIC Jack x1

Page 23

RTC Ckt.

Page 11

BIOS ROM

4 4

Power Button

Page 22

DC/DC Interface Ckt.

Page 27

http://laptop-motherboard-schematic.blogspot.com/

2MB

Page 26

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/12 2012/08/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Block Diagrams

P0VE6 Schematics

236Monday, November 15, 2010

1.0

Voltage Rails

Power Plane Description

VIN

B+

+APU_CORE

1 1

2 2

+APU_CORE_NB 1.0V switched power rail ON OFF

+1.5V

+0.75VS 0.75VS swit ched power ra il for DDR ter minator

+1.05VS

+1.1VS 1.1VS switched power rail ON OFF OFF

+1.8VS 1.8V switched power rail

+3VALW

+3VS

+1.5VS 1.5VS switched power rail ON OFF OFF

+5VALW

+5VS

+VSB VSB always on power rail ON ON*

+RTCBATT

Note : ON* means that t his power plane is ON only with A C power available, otherwise it is OFF.

EC SM Bus1 address

Device

Smart Batter y

Adapter power supply ( 19V)

AC or battery power rail for powe r circuit.

Core voltage for CPU (0.7-1.2V)

1.5V power rail for CPU VDDIO and DDRIII

1.05V swit ched power rai l for NB VDDC & VGA

3.3V always on power rail

3.3V switched power rail

5V always on power rail

5V switched power rail

RTC power

EC SM Bus2 address

Address Address

0001-011xb

HEX

16H

Device

SB-TSI

S1 S3 S5

N/A N/A N/A

ON OFF

ON OFF OFF

1001-100xb

N/AN/AN/A

OFF

ON ON*

ON ON*ON+1.1VALW 1.1V always on power rail

OFF

ON*

OFFON

OFF

ONON

HEX

98H

FCH Hudson-M1 USB Port List

USB1.1

Port0

Port1

USB2.0

Port0

Port1

Port2

Port3

Port4

Port5

Port6

Port7

Port8

Port9

Port10

Port11

Port12

Port13

Right USB2

Right USB3

WWAN

SIM

USB Camera

CardReader

WiMax

Brazos PCIE Port List

PCIE0

APUFCH

PCIE1

PCIE2

PCIE3

PCIE0

PCIE1

PCIE2

PCIE3

WWAN

LANLeft USB1

WLAN

FCH Hudson-M1 SATA Port List

SATA0

SATA1

SATA2

SATA3

SATA4

SATA5

HDD

SM Bus Controller 0

Device Address

APU SIC/SID (FCH_SMB3)

H_THERMTRIP# (FCH_ALERT#)

3 3

SM Bus Controller 1

Device Address HEX

DDR DIMM1 (FCH_SMB0)

(FCH_SMB1 ~ FCH_SMB4, SMB_ALERT#)

HEX

(FCH_SMB0)

1001-000xb



Board ID / SKU ID Table for AD channel

Vcc +3VALW

Board ID

1 2 3 4 5 6 7 NC

100K +/- 5%Ra

Rb V min

AD_BID

8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

0 V

V typ

AD_BID

0 V 0 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

2.200 V

3.300 V

2.341 V

3.300 V

max

PCB Revision

0.1

0.2

SMBUS Control Table

BOM Structure

EC_SMB_CK1

HDMI@ : HDMI function BT@ : BT function CONN@ : Connetors 45@ : 45 Level 3G@ : 3G function

4 4

3G_MP@: 3G & Media processor function

CHARGE@: Charge BATT

NONCHARGE@: nonCharge BATT

http://laptop-motherboard-schematic.blogspot.com/

EC_SMB_DA1

EC_SMB_CK2 EC_SMB_DA2

HDMI_DATA HDMI_CLK

EDID_DATA EDID_CLK

FCH_SMDAT0 FCH_SMCLK0

Security Classifica tion

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Source BATT DIMM MINI Card LCD DDC ROM HDMI DDC ROM APU

KB930

APU FT1

FCH M1

Compal Secret Data

2010/08/12 2012/08/12

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Notes List

P0VE6 Schematics

1.0

336Monday, November 15, 2010

1.0

S IC ONTARIO ZMC50AFPB22GT 1G BGA 413P ABO !

+1.8VS

D D

R3 1K_0402_5%R3 1K_0402_5%

1 2

R4 1K_0402_5%R4 1K_0402_5%

1 2

R8 510_0402_1%R8 510_0402_1%

1 2

R6 1K_0402_5%R6 1K_0402_5%

1 2

SA00004KD40

C50@

APU_SVC APU_SVD

TEST_25_L

TEST36

10/08 Add U1(C50@) SA00004BM30 S IC ONTARIO ZM101034B2238 1G BGA ABO!

11/03 APU P/N update to SA00004DF60(C30) SA00004BM80(C50)

11/29 Change U1 from SA00004BM80 to SA00004KD40

+3VS

R10 10K_0402_5%R10 10K_0402_5%

1 2

R11 10K_0402_5%R11 10K_0402_5%

1 2

R13 1K_0402_5%R13 1K_0402_5%

1 2

R14 1K_0402_5%R14 1K_0402_5%

1 2

R16 1K_0402_5%R16 1K_0402_5%

1 2

R17 1K_0402_5%R17 1K_0402_5%

1 2

C405 100P_0402_50V8JC405 100P_0402_50V8J

1 2

10/05 Add 100p(C405) on LDT_RST#

HDMI_DATA

HDMI_CLK APU_PROCHOT# APU_ALERT#_R

APU_SIC APU_SID

LDT_RST#

Power Circuit

9/9 Change R24 from @ to mount R26 from mount to @

C C

R23 0_0402_5%@R 23 0_0402_5%@

FCH_PROCHOT#<11>

EC_PROCHOT#<25>

1 2

R27 0_0402_5%R27 0_0402_5%

1 2

9/15 Change R24 from mount to @

APU_PROCHOT#

Connection to EC, FCH input need to pull-down

Power Circuit

+3VS

R32

R32 10K_0402_5%

10K_0402_5%

R33

1K_0402_5%

B B

If FCH internal pull-up disabled, level-shifter could be deleted. Need BIOS to disable internal pull-up!!

DMN66D0LDW-7_SOT363-6

A A

DMN66D0LDW-7_SOT363-6

1K_0402_5%

APU_THERMTRIP#

1 2

Q2A

Q2B

3 1

MMBT3904_NL_SOT23-3

1 2

R34 0_0402_5%@R34 0_0402_5%@

+3VS

R39

R39 10K_0402_5%

10K_0402_5%

EC_SMB_DAAPU_SID

1 2

R49 0_0402_5%R49 0_0402_5%

EC_SMB_CKAPU_SIC

1 2

R52 0_0402_5%R52 0_0402_5%

R47 0_0402_5%

R48 0_0402_5%R48 0_0402_5%

8/19 Change Q2A Q2B SB00000DH00 (S TR DMN66D0LDW-7 2N SOT363-6)

R50 0_0402_5%

R51 0_0402_5%R51 0_0402_5%

Power Circuit

9/6 Add R379, R380 for APU_VDDNB_RUN_FB_L

H_THERMTRIP# <12>

2N7002DW-T/R7

Vgs(th): min 1.0V

If Q8 or R429, R432 implemented, EC side pull-up need to be mounted

1 2

Typ 1.6V Max 2.0V

FCH_SID

EC_SMB_DA2

FCH_SIC

EC_SMB_CK2

http://laptop-motherboard-schematic.blogspot.com/

10/27 APU P/N update to B0 stepping

C1 .1U_0402_16V7KC1 .1U_0402_16V7K

HDMI_TX2P<9> HDMI_TX2N<9>

HDMI_TX1P<9> HDMI_TX1N<9>

HDMI_TX0P<9> HDMI_TX0N<9>

HDMI_CLKP<9> HDMI_CLKN<9>

APU_ALERT#_FCH<13> APU_ALERT#_EC<25>

APU_CLK<11> APU_CLK#<11>

DISP_CLK<11> DISP_CLK#<11>

APU_SVC<35>

APU_SVD<35>

APU_VDDNB_RUN_FB_H<35> APU_VDD0_RUN_FB_H<35>

APU_VDD0_RUN_FB_L<35>

FCH_SID <12>

EC_SMB_DA2 <25>

FCH_SIC <12>

EC_SMB_CK2 <25>

1 2

C6 .1U_0402_16V7KC6 .1U_0402_16V7K

1 2

C2 .1U_0402_16V7KC2 .1U_0402_16V7K

1 2

C3 .1U_0402_16V7KC3 .1U_0402_16V7K

1 2

C7 .1U_0402_16V7KC7 .1U_0402_16V7K

1 2

C8 .1U_0402_16V7KC8 .1U_0402_16V7K

1 2

C4 .1U_0402_16V7KC4 .1U_0402_16V7K

1 2

C5 .1U_0402_16V7KC5 .1U_0402_16V7K

1 2

LVDS_A2<8> LVDS_A2#<8>

LVDS_A1<8> LVDS_A1#<8>

LVDS_A0<8> LVDS_A0#<8>

LVDS_ACLK<8> LVDS_ACLK#<8>

LDT_RST#<11> APU_PWRGD<11>

R24 0_0402_5%@R 24 0_0402_5%@

1 2

R26 0_0402_5%@R 26 0_0402_5%@

1 2

T9 PADT9 PAD T10PADT10PAD

Close to APU

T14PADT14PAD

R379 0_0402_5%R379 0_0402_5%

1 2

R380 0_0402_5%R380 0_0402_5%

1 2

T0 FCH

TO EC

T0 FCH

TO EC

10/08 Change U1 P/N to SA00004DF20 S IC ONTARIO ZM121034B1238 1.2G BGA ABO!

SA00004DF60

U1B

HDMI_TX2P_C HDMI_TX2N_C

HDMI_TX1P_C HDMI_TX1N_C

HDMI_TX0P_C HDMI_TX0N_C

HDMI_CLKP_C HDMI_CLKN_C

APU_SIC APU_SID

APU_PROCHOT# APU_THERMTRIP#

APU_ALERT#_R

APU_TDI APU_TDO APU_TCK APU_TMS APU_TRST# APU_DBRDY APU_DBREQ#

8/31 Change U1 P/N to SA00004DF00 S IC ONTARIO ZM121034B1238 1.2G BGA 413P

U1B

TDP1_TXP0

TDP1_TXN0

TDP1_TXP1

TDP1_TXN1

D10

TDP1_TXP2

C10

TDP1_TXN2

A10

TDP1_TXP3

B10

TDP1_TXN3

LTDP0_TXP0

LTDP0_TXN0

LTDP0_TXP1

LTDP0_TXN1

LTDP0_TXP2

LTDP0_TXN2

LTDP0_TXP3

LTDP0_TXN3

CLKIN_H

CLKIN_L

DISP_CLKIN_H

DISP_CLKIN_L

SVC

SVD

SIC

SID

RESET_L

PWROK

PROCHOT_L

THERMTRIP_L

ALERT_L

TDI

TDO

TCK

TMS

TRST_L

DBRDY

DBREQ_L

VDDCR_NB_SENSE

VDDCR_CPU_SENSE

VDDIO_MEM_S_SENSE

VSS_SENSE

RSVD_1

W11

RSVD_2

RSVD_3

S IC ONTARIO 2M121134B1240 1.2G BGA 413P ABO !

C30@

DISPLAYPORT 1

DISPLAYPORT 0

CLK

SER

JTAG CTRL

DP MISC

VGA DAC

TEST

DP_ZVSS

DP_BLON

DP_DIGON

DP_VARY_BL

TDP1_AUXP

TDP1_AUXN

TDP1_HPD

LTDP0_AUXP LTDP0_AUXN

LTDP0_HPD

DAC_RED

DAC_REDB

DAC_GREEN

DAC_GREENB

DAC_BLUE

DAC_BLUEB

DAC_HSYNC DAC_VSYNC

DAC_SCL DAC_SDA

DAC_ZVSS

TEST14 TEST15 TEST16 TEST17 TEST18 TEST19

TEST25_H

TEST25_L

TEST28_H

TEST28_L

TEST31

TEST33_H

TEST33_L

TEST34_H

TEST34_L

TEST35 TEST36 TEST37

TEST38

DMAACTIVE_L

TEST4 TEST5 TEST6

DP_ZVSS

G2 H2 H1

HDMI_CLK

HDMI_DATA

EDID_CLK

EDID_DATA

LTDP0_HPD

C12

R12 150_0402_1%R12 150_0402_1%

D13 A12 B12 A13 B13

E1 E2

F2 D4

D12

R1 R2 R6 T5 E4 K4 L1 L2 M2 K1 K2 L5 M5 M21 J18 J19 U15 T15 H4 N5 R5

K3 T1

1 2

R15 150_0402_1%R15 150_0402_1%

1 2

R18 150_0402_1%R18 150_0402_1%

1 2

DAC_ZVSS

TEST15

TEST18 TEST19 TEST25_H TEST_25_L

TEST31 TEST33_H TEST33_L

TEST35 TEST36 TEST37

R31 1K_0402_5%R31 1K_0402_5%

PADT2PAD

PADT8PAD

PAD

1 2

9/17 Remove JHDT1 R40, R44, R45, R46 , Add T26~T32

AMD Debug

9/20 Delete R41~R43

+1.8VS

1K_0402_5%

R37

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/12 2012/08/12

APU_TRST#

Compal Secret Data

Deciphered Date

Display

LVDS

eDP

+3VS

R1 150_0402_1%R1 150_0402_1%

1 2

APU_ENBKL <25> APU_ENVDD <8> APU_BLPWM <8>

HDMI_CLK <9>

HDMI_DATA <9>

HDMI_DET <9>

EDID_CLK <8>

R9 100K_0402_5%R9 100K_0402_5%

1 2

R19 499_0402_1%R19 499_0402_1%

1 2

R20 1K_0402_5%R20 1K_0402_5%

1 2

R21 1K_0402_5%R21 1K_0402_5%

1 2

R22 1K_0402_5%R22 1K_0402_5%

1 2

R25 510_0402_1%R25 510_0402_1%

1 2

C9 0.1U_0402_16V4ZC9 0.1U_0402_16V4Z

1 2

C10 0.1U_0402_16V4ZC10 0.1U_0402_16V4Z

1 2

R30 1K_0402_5%@R30 1K_0402_5%@

1 2

R386 1K_0402_5%R386 1K_0402_5%

1 2

T13

EDID_DATA <8>

DAC_RED <10>

DAC_GRN <10>

DAC_BLU <10>

CRT_HSYNC <10> CRT_VSYNC <10>

CRT_DDC_CLK <10> CRT_DDC_DATA <10>

10/01 Remove T1,T3~T7,T11,T12,T31, T32

R9 R352

mount



R28 51_0402_1%R28 51_0402_1% R29 51_0402_1%R29 51_0402_1%

8/25 Pull-up 100k(@ R352) to +3VS on LTDP0_HPD for eDP

R352 100K_0402_5%@R 352 100K_0402_5%@

1 2

1 2 1 2

+1.8VS

mount

9/9 Add R386 (1k@) to +1.8VS on TEST35

9/13 Change R30 from mount to @, R386 from @ to mount (AMD Recommend)

T29

PAD

T30

PAD

ALLOW_STOP# <11>APU_VDDNB_RUN_FB_L<35>

+1.8VS

APU_TCK

APU_TMS

APU_TDI

APU_TDO

APU_PWRGD

LDT_RST#

APU_DBRDY

APU_DBREQ#

Custom

Date: Sheet

R35 1K_0402_5%R35 1K_0402_5%

R36 1K_0402_5%R36 1K_0402_5%

R38 1K_0402_5%R38 1K_0402_5%

R5 300_0402_5%R5 300_0402_5%

R7 300_0402_5%R7 300_0402_5%

R2 300_0402_5%R2 300_0402_5%

Compal Electronics, Inc.

Title

Size Document Number Rev

Compal Electronics, Inc.

)7&75/'3&57

39(6FKHPDWLFV

+1.8VS

436Monday, November 29, 2010

1.0

U1E

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6

4 4

3 3

2 2

DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

DDR_A_BS0<7> DDR_A_BS1<7> DDR_A_BS2<7>

DDR_A_DQS0<7> DDR_A_DQS#0<7> DDR_A_DQS1<7> DDR_A_DQS#1<7> DDR_A_DQS2<7> DDR_A_DQS#2<7> DDR_A_DQS3<7> DDR_A_DQS#3<7> DDR_A_DQS4<7> DDR_A_DQS#4<7> DDR_A_DQS5<7> DDR_A_DQS#5<7> DDR_A_DQS6<7> DDR_A_DQS#6<7> DDR_A_DQS7<7> DDR_A_DQS#7<7>

DDR_A_CLK0<7> DDR_A_CLK#0<7> DDR_A_CLK1<7> DDR_A_CLK#1<7>

DDR_RST#<7>

DDR_EVENT#<7>

DDR_CKE0<7> DDR_CKE1<7>

DDR_A_ODT0<7> DDR_A_ODT1<7>

DDR_CS0_DIMMA#<7> DDR_CS1_DIMMA#<7>

DDR_A_RAS#<7> DDR_A_CAS#<7> DDR_A_WE#<7>

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7

DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1

DDR_RST# DDR_EVENT#

DDR_CKE0 DDR_CKE1

DDR_A_ODT0 DDR_A_ODT1

DDR_CS0_DIMMA# DDR_CS1_DIMMA#

DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

U1E

R17

M_ADD0

H19

M_ADD1

J17

M_ADD2

H18

M_ADD3

H17

M_ADD4

G17

M_ADD5

H15

M_ADD6

G18

M_ADD7

F19

M_ADD8

E19

M_ADD9

T19

M_ADD10

F17

M_ADD11

E18

M_ADD12

W17

M_ADD13

E16

M_ADD14

G15

M_ADD15

R18

M_BANK0

T18

M_BANK1

F16

M_BANK2

D15

M_DM0

B19

M_DM1

D21

M_DM2

H22

M_DM3

P23

M_DM4

V23

M_DM5

AB20

M_DM6

AA16

M_DM7

A16

M_DQS_H0

B16

M_DQS_L0

B20

M_DQS_H1

A20

M_DQS_L1

E23

M_DQS_H2

E22

M_DQS_L2

J22

M_DQS_H3

J23

M_DQS_L3

R22

M_DQS_H4

P22

M_DQS_L4

W22

M_DQS_H5

V22

M_DQS_L5

AC20

M_DQS_H6

AC21

M_DQS_L6

AB16

M_DQS_H7

AC16

M_DQS_L7

M17

M_CLK_H0

M16

M_CLK_L0

M19

M_CLK_H1

M18

M_CLK_L1

N18

M_CLK_H2

N19

M_CLK_L2

L18

M_CLK_H3

L17

M_CLK_L3

L23

M_RESET_L

N17

M_EVENT_L

F15

M_CKE0

E15

M_CKE1

W19

M0_ODT0

V15

M0_ODT1

U19

M1_ODT0

W15

M1_ODT1

T17

M0_CS_L0

W16

M0_CS_L1

U17

M1_CS_L0

V16

M1_CS_L1

U18

M_RAS_L

V19

M_CAS_L

V17

M_WE_L

S IC ONTARIO 2M121134B1240 1.2G BGA 413P ABO !

C30@

DDR SYSTEM MEMORY

M_DATA0 M_DATA1 M_DATA2 M_DATA3 M_DATA4 M_DATA5 M_DATA6 M_DATA7

M_DATA8

M_DATA9 M_DATA10 M_DATA11 M_DATA12 M_DATA13 M_DATA14 M_DATA15

M_DATA16 M_DATA17 M_DATA18 M_DATA19 M_DATA20 M_DATA21 M_DATA22 M_DATA23

M_DATA24 M_DATA25 M_DATA26 M_DATA27 M_DATA28 M_DATA29 M_DATA30 M_DATA31

M_DATA32 M_DATA33 M_DATA34 M_DATA35 M_DATA36 M_DATA37 M_DATA38 M_DATA39

M_DATA40 M_DATA41 M_DATA42 M_DATA43 M_DATA44 M_DATA45 M_DATA46 M_DATA47

M_DATA48 M_DATA49 M_DATA50 M_DATA51 M_DATA52 M_DATA53 M_DATA54 M_DATA55

M_DATA56 M_DATA57 M_DATA58 M_DATA59 M_DATA60 M_DATA61 M_DATA62 M_DATA63

M_VREF

M_ZVDDIO_ME M_S

B14 A15 A17 D18 A14 C14 C16 D16

C18 A19 B21 D20 A18 B18 A21 C20

C23 D23 F23 F22 C22 D22 F20 F21

H21 H23 K22 K21 G23 H20 K20 K23

N23 P21 T20 T23 M20 P20 R23 T22

V20 V21 Y23 Y22 T21 U23 W23 Y21

Y20 AB22 AC19 AA18 AA23 AA20 AB19 Y18

AC17 Y16 AB14 AC14 AC18 AB18 AB15 AC15

M23

M22

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7

DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15

DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23

DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31

DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39

DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47

DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55

DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

+MEM_VREF

+M_ZVDDIO

R55

39.2_0402_1%

DDR_A_MA[0..15]

DDR_A_DM[0..7]

+1.05VS

UMI_RX0P<11> UMI_RX0N<11>

UMI_RX1P<11> UMI_RX1N<11>

UMI_RX2P<11> UMI_RX2N<11>

UMI_RX3P<11> UMI_RX3N<11>

+1.5V

DDR_A_D[0..63]

Less than 1"

DDR_A_D[0..63] <7>

DDR_A_MA[0..15] <7>

DDR_A_DM[0..7] <7>

1 2

R53 2K_0402_1%R53 2K_0402_1%

P_ZVDD_10

8/22 Delete C11~C18 (No VGA)

9/6 Change PCI-E from FCH to APU

9/6 Update PCI-E port List

9/15 Change PCI-E from APU to FCH

U1A

AA6

P_GPP_RXP0

P_GPP_RXN0

AB4

P_GPP_RXP1

AC4

P_GPP_RXN1

AA1

P_GPP_RXP2

AA2

P_GPP_RXN2

P_GPP_RXP3

P_GPP_RXN3

Y14

P_ZVDD_10

AA12

P_UMI_RXP0

Y12

P_UMI_RXN0

AA10

P_UMI_RXP1

Y10

P_UMI_RXN1

AB10

P_UMI_RXP2

AC10

P_UMI_RXN2

AC7

P_UMI_RXP3

AB7

P_UMI_RXN3

S IC ONTARIO 2M121134B1240 1.2G BGA 413P ABO !

C30@

P_GPP_TXP0 P_GPP_TXN0

P_GPP_TXP1 P_GPP_TXN1

P_GPP_TXP2 P_GPP_TXN2

P_GPP_TXP3

PCIE I/F

P_GPP_TXN3

P_UMI_TXP0 P_UMI_TXN0

P_UMI_TXP1 P_UMI_TXN1

P_UMI_TXP2 P_UMI_TXN2

P_UMI_TXP3

UMI I/F

P_UMI_TXN3

P_ZVSS

AB6 AC6

AB3 AC3

Y1 Y2

V3 V4

AA14

AB12 AC12

AC11 AB11

AA8 Y8

AB8 AC8

P_ZVSS

R54 1.27K_0402_1%R54 1.27K_0402_1%

1 2

Less than 1"

UMI_TX0P_C UMI_TX0N_C

UMI_TX1P_C UMI_TX1N_C

UMI_TX2P_C UMI_TX2N_C

UMI_TX3P_C UMI_TX3N_C

C19 .1U_0402_16V7KC19 .1U_0402_16V7K C20 .1U_0402_16V7KC20 .1U_0402_16V7K

C21 .1U_0402_16V7KC21 .1U_0402_16V7K C22 .1U_0402_16V7KC22 .1U_0402_16V7K

C23 .1U_0402_16V7KC23 .1U_0402_16V7K C24 .1U_0402_16V7KC24 .1U_0402_16V7K

C25 .1U_0402_16V7KC25 .1U_0402_16V7K C26 .1U_0402_16V7KC26 .1U_0402_16V7K

1 2 1 2

UMI_TX0P <11> UMI_TX0N <11>

UMI_TX1P <11> UMI_TX1N <11>

UMI_TX2P <11> UMI_TX2N <11>

UMI_TX3P <11> UMI_TX3N <11>

9/11 Delete DDR Signal link to JDIMM2

+1.5V

R57

1 2

1K_0402_5%

1 1

DDR_EVENT#

R56

1K_0402_1%

1 2

R58

1K_0402_1%

C27

1000P_0402_50V7K

1 2

Place within 1000 mils to APU 20100526

http://laptop-motherboard-schematic.blogspot.com/

C28

+MEM_VREF

0.1U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INF ORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INF ORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INF ORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPET ENT DIVISION OF R&D DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRON ICS, INC. NEITHER THIS SHEET NO R THE INFORMATION IT CON TAINS

DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRON ICS, INC. NEITHER THIS SHEET NO R THE INFORMATION IT CON TAINS

DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRON ICS, INC. NEITHER THIS SHEET NO R THE INFORMATION IT CON TAINS MAY BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WIT HOUT PRIOR WRIT TEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WIT HOUT PRIOR WRIT TEN CONSENT OF CO MPAL ELECTRONICS, INC.

2010/08/12 2012/08/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

FT1 DDRIII/UMI/PCIE

P0VE6 Schematics

536Wednesday, November 17, 2010

1.0

+APU_CORE

10U_0603_6.3V6M

1U_0402_6.3V6K

.1U_0402_16V7K

10U_0603_6.3V6M

1U_0402_6.3V6K

.1U_0402_16V7K

10U_0603_6.3V6M

C56

C72

C79

C42

C30

10U_0603_6.3V6M

.1U_0402_16V7K

10U_0603_6.3V6M

1U_0402_6.3V6K

C47

C80

10U_0603_6.3V6M

180P_0402_50V8J

POWER

SGA20331E10

http://laptop-motherboard-schematic.blogspot.com/

D D

C31

C43

C52

+APU_CORE_NB

C C

C68

C75

C84

B B

10U_0603_6.3V6M

1U_0402_6.3V6K

.1U_0402_16V7K

10U_0603_6.3V6M

1U_0402_6.3V6K

.1U_0402_16V7K

C29

C44

C53

C69

C76

C85

POWER

C92

10U_0603_6.3V6M

+APU_CORE

C99

C99 470U_X_2VM_R6M

470U_X_2VM_R6M

SGA00003K00

A A

SGA20331E10

10U_0603_6.3V6M

1U_0402_6.3V6K

.1U_0402_16V7K

10U_0603_6.3V6M

1U_0402_6.3V6K

.1U_0402_16V7K

+1.05VS

C93

C93 220U_D2_2VY_R15M

220U_D2_2VY_R15M

SGA00004L00

+APU_CORE_NB

C114

C32

C45

C54

C70

C77

C86

C100

C100 470U_X_2VM_R6M

470U_X_2VM_R6M

330U_D2_2V_Y

C41

10U_0603_6.3V6M

C46

1U_0402_6.3V6K

C55

.1U_0402_16V7K

C71

10U_0603_6.3V6M

C78

1U_0402_6.3V6K

C87

.1U_0402_16V7K

9/20 Change C93 to SGA00004L00

8/25 Change C101 from mount to @

9/15 Remove C101, C113

9/15 Change C99,C100 to 470U(SG A00003K00)

C102

Near CPU Socket

C117

Near CPU Socket Near CPU Socket

4500 mA

C33

C48

C81

330U_D2_2V_Y

+APU_CORE

10U_0603_6.3V6M

8000 mA

+APU_CORE_NB

180P_0402_50V8J

2000 mA

+1.5V

180P_0402_50V8J

8/22 Change C111~C113 from E-Cap to Poly-Cap (SG A20331E10)

8/25 Change C111 from poly-cap to E-cap (SF000002Z00)

9/11 Change C111 to SGA20331E10

C111

+1.5V

C82

10U_0603_6.3V6M

C88

1U_0402_6.3V6K

C94

.1U_0402_16V7K

+1.5V +1.8VS

POWER POWER

C115

22U_0805_6.3V6M

U1C

VDDCR_CPU_1

VDDCR_CPU_2

VDDCR_CPU_3

VDDCR_CPU_4

VDDCR_CPU_5

VDDCR_CPU_6

VDDCR_CPU_7

VDDCR_CPU_8

VDDCR_CPU_9

VDDCR_CPU_10

VDDCR_CPU_11

VDDCR_CPU_12

VDDCR_CPU_13

VDDCR_CPU_14

VDDCR_CPU_15

VDDCR_NB_1

E11

VDDCR_NB_2

E13

VDDCR_NB_3

VDDCR_NB_4

F12

VDDCR_NB_5

G11

VDDCR_NB_6

G13

VDDCR_NB_7

VDDCR_NB_8

H12

VDDCR_NB_9

K11

VDDCR_NB_10

K13

VDDCR_NB_11

L10

VDDCR_NB_12

L12

VDDCR_NB_13

L14

VDDCR_NB_14

M11

VDDCR_NB_15

M12

VDDCR_NB_16

M13

VDDCR_NB_17

N10

VDDCR_NB_18

N12

VDDCR_NB_19

N14

VDDCR_NB_20

P11

VDDCR_NB_21

P13

VDDCR_NB_22

G16

VDDIO_ MEM_S_1

G19

VDDIO_ MEM_S_2

E17

VDDIO_ MEM_S_3

J16

VDDIO_ MEM_S_4

L16

VDDIO_ MEM_S_5

L19

VDDIO_ MEM_S_6

N16

VDDIO_ MEM_S_7

R16

VDDIO_ MEM_S_8

R19

VDDIO_ MEM_S_9

W18

VDDIO_ MEM_S_10

U16

VDDIO_ MEM_S_11

S IC ONTARIO 2M121134B1240 1.2G BGA 413P ABO !

C30@

C83

10U_0603_6.3V6M

1U_0402_6.3V6K

.1U_0402_16V7K

C112

330U_D2_2V_Y

C90

C96

C89

C95

SGA20331E10

Near CPU Socket

CPU CORE

DAC

GPU AND NB CORE

POWER

DDR3

C91

1U_0402_6.3V6K

C97

.1U_0402_16V7K

C116

TSense/PLL/DP/PCIE/IO

VDD_18_1

VDD_18_2

VDD_18_3

VDD_18_4

VDD_18_5

VDD_18_6

VDD_18_7

VDD_18_DAC

DIS PLL

U11

VDDPL_10

PCIE/IO/DDR3 Phy

U13

VDD_10_1

W13

VDD_10_2

V12

VDD_10_3

T12

VDD_10_4

DP Phy/IO

VDD_33

1U_0402_6.3V6K

C98

180P_0402_50V8J

10U_0603_6.3V6M

2000 mA

+VDD_18

C34

W = 20 mil / Spcae = 20 mil

+VDD_18_DAC

C49

W = 15 mil / Spcae = 20 mil

+VDDL_10

C57

5500 mA

500 mA

+VDD_10

C61

+VDD_33

C73

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C35

180P_0402_50V8J

C50

180P_0402_50V8J

C58

180P_0402_50V8J

C62

180P_0402_50V8J

C74

.1U_0402_16V7K

C36

C37

1U_0402_6.3V6K

.1U_0402_16V7K

C51

10U_0603_6.3V6M

1U_0402_6.3V6K

C59

C60

1U_0402_6.3V6K

.1U_0402_16V7K

C64

C63

.1U_0402_16V7K

R333

1 2

0_0603_5%

1U_0402_6.3V6K

8/22 Reserve R333 ( 0 ohm 0603 )

2010/08/12 2012/08/12

C38

1U_0402_6.3V6K

FBMA-L11-201209-221LMA30T_0805

10U_0603_6.3V6M

C65

1U_0402_6.3V6K

+3VS

C39

C40

1U_0402_6.3V6K

+1.8VS

FBMA-L11-201209-221LMA30T_0805

C67

C66

1U_0402_6.3V6K

10U_0603_6.3V6M

Compal Secret Dat a

Deciphered Dat e

10U_0603_6.3V6M

8/25 Change +1.0VS to +1.05VS

10U_0603_6.3V6M

+1.8VS

FBMA-L11-201209-221LMA30T_0805

+1.05VS

FBMA-L11-201209-221LMA30T_0805

U1D

VSS_1

VSS_2

B11

VSS_3

B17

VSS_4

B22

VSS_5

VSS_6

VSS_7

VSS_8

VSS_9

D11

VSS_10

D14

VSS_11

B15

VSS_12

D17

VSS_13

D19

VSS_14

VSS_15

VSS_16

E12

VSS_17

E20

VSS_18

VSS_19

F11

VSS_20

F13

VSS_21

VSS_22

VSS_23

VSS_24

VSS_25

G12

VSS_26

G20

VSS_27

G22

VSS_28

VSS_29

H11

VSS_30

H13

VSS_31

VSS_32

VSS_33

VSS_34

J20

VSS_35

K10

VSS_36

K14

VSS_37

VSS_38

VSS_39

VSS_40

L11

VSS_41

L13

VSS_42

L20

VSS_43

L22

VSS_44

VSS_45

VSS_46

VSS_47

VSS_48

N11

VSS_49

S IC ONTARIO 2M121134B1240 1.2G BGA 413P ABO !

By case (Along split)

+1.5V

C103

.1U_0402_16V7K

C104

C105

.1U_0402_16V7K

Title

Size Document Number Rev

Date: Sheet

N13

VSS_50

N20

VSS_51

N22

VSS_52

P10

VSS_53

P14

VSS_54

VSS_55

VSS_56

R20

VSS_57

VSS_58

VSS_59

T11

VSS_60

T13

VSS_61

VSS_62

VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97

VSSBG_DAC

C107

180P_0402_50V8J

U7 U12 U20 U22 V8 V9 V11 V13 W1 W2 W4 W5 W7 W12 W20 Y5 Y7 Y9 Y11 Y13 Y15 Y17 Y19 AA4 AA22 AB2 AB5 AB9 AB13 AB17 AB21 AC5 AC9 AC13 A11

C108

180P_0402_50V8J

C109

GND

C106

180P_0402_50V8J

Compal Electronics, Inc.

P07-FT1 PWR/VSS

P0VE6 Schematics

636Wednesday, November 17, 2010

C110

180P_0402_50V8J

1.0

+1.5V

3500 mA

DDR_A_D4 DDR_A_D5

DDR_A_D6 DDR_A_D7

DDR_A_D12 DDR_A_D13

DDR_A_DM1

DDR_A_D14 DDR_A_D15

DDR_A_D20 DDR_A_D21

DDR_A_DM2

DDR_A_D22 DDR_A_D23

DDR_A_D28 DDR_A_D29

DDR_A_D30 DDR_A_D31

R397

1 2

100_0402_1%

DDR_A_MA15 DDR_A_MA14

DDR_A_MA11 DDR_A_MA7

DDR_A_MA6 DDR_A_MA4

DDR_A_MA2 DDR_A_MA0

DDR_A_D36 DDR_A_D37

DDR_A_DM4

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_DM6

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_D62 DDR_A_D63

DDR_A_DQS#0 <5> DDR_A_DQS0 <5>

DDR_RST# <5>

8/19 Change JDIMM1 to SP07000LT00(LCN_DAN06-K4406-0103_204P)

9/13 Update JDIMM1 to LCN_DAN06-K4406-0102_204P

9/23 Reserve R396,R397 on CKE0 & CKE1(S3 hang Issue)

DDR_A_DQS#3 <5> DDR_A_DQS3 <5>

+1.5V

DDR_CKE1 <5>

C120

0.1U_0402_16V4Z

10/11 Change R396 R397 from @ to mount (For A1 APU,B0 APU no Need)

DDR_A_CLK1 <5> DDR_A_CLK#1 <5>

DDR_A_BS1 <5> DDR_A_RAS# <5>

DDR_CS0_DIMMA# <5> DDR_A_ODT0 <5>

DDR_A_ODT1 <5>

W=20mil

+VREF_CA

+0.75VS

C132

DDR_A_DQS#5 <5> DDR_A_DQS5 <5>

DDR_A_DQS#7 <5> DDR_A_DQS7 <5>

DDR_EVENT# <5> FCH_SMDAT0 <12,19,20> FCH_SMCLK0 <12,19,20>

C133

1000P_0402_50V7K

0.1U_0402_16V4Z

100 mA

Security Classifica tion

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/12 2012/08/12

DDR_A_D[0..63]

DDR_A_M A[0..15]

DDR_A_DM[0..7]

0.1U_0402_16V4Z

C121

0.1U_0402_16V4Z

Compal Secret Data

Deciphered Date

DDR_A_D[0..63] <5>

DDR_A_M A[0..15] <5>

DDR_A_DM[0..7] <5>

0.1U_0402_16V4Z

C122

C123

C124

0.1U_0402_16V4Z

+1.5V

R59

R59 1K_0402_1%

1K_0402_1%

0.1U_0402_16V4Z

C125

+VREF_DQ

0.1U_0402_16V4Z

C126

1 2

C127

R61

R61 1K_0402_1%

1K_0402_1%

C128

0.1U_0402_16V4Z

+VREF_CA

0.1U_0402_16V4Z

9/11 Change C137 to SGA00004L00

CRB 0.1u X1 4.7u X1

+0.75VS

C134

0.1U_0402_16V4Z

Place near JDIMM1

8/25 Change C137 from poly-cap to E-cap (SF000002Y00) 8/25 Reserve C381 E-cap (SF000002Y00) on +1.5V

C136

C135

0.1U_0402_16V4Z

CRB 100U X2

4.7U_0603_6.3V6K

9/11 Remove C381

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

DDR3 SODIMM-I Socket

P0VE6 Schematics

C129

0.1U_0402_16V4Z

+1.5V

SGA00004L00

+1.5V

R60

R60 1K_0402_1%

1K_0402_1%

1 2

R62

R62 1K_0402_1%

1K_0402_1%

1 2

0.1U_0402_16V4Z

C130

C137

C137 220U_D2_2VY_R15M

220U_D2_2VY_R15M

736Wednesday, November 17, 2010

C131

1.0

DDR_A_D0 DDR_A_D1

DDR_A_DM0

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_DM3

DDR_A_D26 DDR_A_D27

R396

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

DDR_A_MA10

DDR_A_MA13

DDR_A_D32 DDR_A_D33

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_DM7

DDR_A_D58 DDR_A_D59

R64

10K_0402_5%

+1.5V

JDIMM1

3 5 7

9 11 13 15 17 19 21 23 25 27

33 35

39 41

45 47 49 51 53 55 57 59

67 69

73 75 77 79 81 83 85 87 89 91 93 95 97 99

101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

205

LCN_DAN06-K4406-0102

http://laptop-motherboard-schematic.blogspot.com/

CONN@JDIMM1

CONN@

VREF_DQ1VSS1 VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS129RESET# VSS1131VSS12 DQ10 DQ11 VSS1337VSS14 DQ16 DQ17 VSS1543VSS16 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS2261DQS#3 DM3 VSS2365VSS24 DQ26 DQ27 VSS2571VSS26

CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1

DQ4 DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6

DQ7 VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1 CK1#

VDD12

BA1

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35 DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47 DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

SCL VTT2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78

A15

A14

82 84

A11

88 90

94 96

100 102 104 106 108 110 112 114

S0#

116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

W=20mil

+VREF_DQ

C118

D D

C C

B B

A A

+3VS

DDR_CS1_DIMMA#<5>

C138

C119

0.1U_0402_16V4Z

DDR_A_DQS#1<5> DDR_A_DQS1<5>

DDR_A_DQS#2<5> DDR_A_DQS2<5>

DDR_CKE0<5>

DDR_A_BS2<5>

DDR_A_CLK0<5> DDR_A_CLK#0<5>

DDR_A_BS0<5>

DDR_A_WE#<5> DDR_A_CAS#<5>

DDR_A_DQS#4<5> DDR_A_DQS4<5>

DDR_A_DQS#6<5> DDR_A_DQS6<5>

1000P_0402_50V7K

1 2

100_0402_1%

R63 10K_0402_5%R63 10K_0402_5%

1 2

C139

0.1U_0402_16V4Z

2.2U_0603_6.3V6K

+3VS

About Camera

112

JUMP_43X39

+CAM_VCC

0.1U_0402_16V4Z

C161

LCD POWER CIRCUIT

R67

D D

470_0402_5%

R67

W=40mils

Q32A

DMN66D0LDW-7_SOT363-6

Q32A

+3VALW

R68

100K_0402_5%

1 2

R69 4.7K_0402_5%R69 4.7K_0402_5%

+LCDVDD_R

W=40mils W=40mils

0.1U_0402_16V4Z

C165

0.047U_0402_16V4Z

8/31 Change R68.2 link to +3VALW

9/24 Change Q3 to SB000007H10

11/02 Change Q3 PN to SB934130020

+LCDVDD

C162

AP2301GN-HF_SOT23-3

C163

4.7U_0603_6.3V6K

+3VS+LCDVDD

C164

4.7U_0603_6.3V6K

9/15 Remove D1 L5 R71 R72 C166 C167 for layout spacing

9/23 Add D1 L5 R71 R72 C166 C167 for ESD

9/23 Remove D1 C166 C167

INVT_PWM <25>

APU_BLPWM <4>

R73

2.2K_0402_5%

1 2

R383

9/24 Swap L5

APU

100K_0402_5%

@R 383

1 2

C169

1000P_0402_50V7K

3G@

)RU5)

R710_0402_5% R710_0402_5%

@L5

USB20_N5_1 USB20_N5

USB20_P5_1

WCM2012F2S-900T04_0805

R720_0402_5% R720_0402_5%

USB20_P5

10/04 Add 100p(C401) on INVT_PWM

C401

INVTPWM

C401

100P_0402_50V8J

10/04 Change C401 on INVTPWM



Display

R331 0 ohm

R332

R381

R382

R383

R73

R75 2.2k ohm 100k ohm

LVDS eDP

0 ohm

@ 100k ohm

2.2k ohm @

USB20_N5 <12>

USB20_P5 <12>

0.1uF

8/26 Change Q4 Q5 to Q32A Q32B (SB00000DH00) Standard Part

Q32B

APU_ENVDD<4>

C C

100K_0402_5%

R70

1 2

9/9 Reserve 100k PD to GND on INVTPWM

CMOS & LCD/PANEL BD. Conn.

8/25 JLVDS1.5 change to INT_MIC0 JLVDS1.6 change to GNDA

Q32B DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

8/26 Change Q3 to SB934130020 Standard Part

9/17 Change R387 from @ to mount

100K_0402_5%

1 2

INVTPWM

R387

R3100_0402_5% @ R3100_0402_5% @

R3110_0402_5% R3110_0402_5%

8/31 Update JLVDS1 Pin definition Delete R74 R76

9/13 Update LVDS Pin definition, Add R74,R76

9/13 Add Net Name +3VS_DMIC

JLVDS1

1 2

B B

A A

3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

293033

ACES_88341-3000B001

CONN@

USB20_P5_1 USB20_N5_1

LVDS_ACLK_R LVDS_ACLK#_R

LVDS_A2_R LVDS_A2#_R

LVDS_A1_R LVDS_A1#_R

LVDS_A0_R LVDS_A0#_R

EDID_DATA_R EDID_CLK_R BKOFF# INVTPWM +3VS_LVDS +LCDVDD_L

FBMA-L11-201209-221LMA30T_0805

+LEDVDD

1 2

10/01 Remove R74,R76

camera

W=20mil

+CAM_VCC

12 12

BKOFF# <25>

+LCDVDD

FBMA-L11-201209-221LMA30T_0805

C170

C170 330P_0402_50V7K

330P_0402_50V7K

3G@

8/22 Reserve R327~R332( 0 ohm) for eDP

8/31 Reserve R353 R354 on LVDS_ACLK

R3530_0402_5% R3530_0402_5% R3540_0402_5% R3540_0402_5%

R3270_0402_5% R3270_0402_5% R3280_0402_5% R3280_0402_5%

R3290_0402_5% R3290_0402_5% R3300_0402_5% R3300_0402_5%

R3310_0402_5% R3310_0402_5% R3320_0402_5% R3320_0402_5%

R3810_0402_5% R3810_0402_5% R3820_0402_5% R3820_0402_5%

R3340_0402_5% R3340_0402_5%

EDID_DATA EDID_CLK

+3VS

W=20mil

LVDS_ACLK <4> LVDS_ACLK# <4>

LVDS_A2 <4> LVDS_A2# <4>

LVDS_A1 <4> LVDS_A1# <4>

LVDS_A0 <4> LVDS_A0# <4>

EDID_DATA <4> EDID_CLK <4>

8/22 Reserve R334(0402 0 ohm)

W=20mil

B+

C171

C171 100P_0402_50V8J

100P_0402_50V8J

3G@

EDID_CLK_R

EDID_DATA_R

9/7 Reserve R381,R382( 0 ohm)R383(100k@) for eDP

+3VS

R75

2.2K_0402_5%

INVT_PW M

BKOFF#

C168

220P_0402_50V7K

3G@

1 2

9/3 Pull-Down 10k(R377) to GND on BKOFF#

BKOFF#

R377 10K_0402_5%R377 10K_0402_5%

1 2

http://laptop-motherboard-schematic.blogspot.com/

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/12 2012/08/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

LVDS / Camera

P0VE6 Schematics

836Wednesday, November 17, 2010

1.0

R77 0_0402_5%HDMI@R77 0_0402_5%HDMI@

HDMI_CLKP<4> HDMI_CLKN<4> HDMI_TX0P<4> HDMI_TX0N<4> HDMI_TX1P<4> HDMI_TX1N<4> HDMI_TX2P<4> HDMI_TX2N<4>

D D

1 2

R78 0_0402_5%HDMI@R78 0_0402_5%HDMI@

1 2

R79 0_0402_5%HDMI@R79 0_0402_5%HDMI@

1 2

R80 0_0402_5%HDMI@R80 0_0402_5%HDMI@

1 2

R81 0_0402_5%HDMI@R81 0_0402_5%HDMI@

1 2

R82 0_0402_5%HDMI@R82 0_0402_5%HDMI@

1 2

R83 0_0402_5%HDMI@R83 0_0402_5%HDMI@

1 2

R84 0_0402_5%HDMI@R84 0_0402_5%HDMI@

1 2

HDMI_CLK+_CONN

HDMI_CLK-_CONN

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_TX1+_CONN

HDMI_TX1-_CONN

HDMI_TX2+_CONN

HDMI_TX2-_CONN

D2 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

D3 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

+5VS+5VS +5VS

HDMI_HPDHDMICLK_RHDMIDAT_R

D4 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

EMI/ESD

+3VS

@L8

HDMI_CLKP

HDMI_CLKN

HDMI_TX0P

HDMI_TX0N

HDMI_TX1P

C C

HDMI_TX1N

HDMI_TX2P

HDMI_TX2N

WCM-2012-900T_4P

@L9

WCM-2012-900T_4P

L10

@L10

WCM-2012-900T_4P

L11

@L11

WCM-2012-900T_4P

HDMI_CLK+_CONN

HDMI_CLK-_CONN

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_TX1+_CONN

HDMI_TX1-_CONN

HDMI_TX2+_CONN

HDMI_TX2-_CONN

HDMI_CLK+_CONN

HDMI_CLK-_CONN

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_TX1+_CONN

HDMI_TX1-_CONN

HDMI_TX2+_CONN

HDMI_TX2-_CONN

R85 499_0402_1%HDMI@R85 499_0402_1%HDMI@

R86 499_0402_1%HDMI@R86 499_0402_1%HDMI@

R87 499_0402_1%HDMI@R87 499_0402_1%HDMI@

R88 499_0402_1%HDMI@R88 499_0402_1%HDMI@

R89 499_0402_1%HDMI@R89 499_0402_1%HDMI@

R90 499_0402_1%HDMI@R90 499_0402_1%HDMI@

R91 499_0402_1%HDMI@R91 499_0402_1%HDMI@

R93 499_0402_1%HDMI@R93 499_0402_1%HDMI@

+5VS

NEAR CONNECT

1 2

R95

R95 100K_0402_5%

100K_0402_5%

Q7 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

HDMI@

10/29 Add C409~C412(0.1U) on +5VS_HDMI 10/29 Add C415~C416(0.1U) on +5VS_HDMI_F

8/26 Change Q7 to SB000009610 Standard Part

10/27 Change D5 P/N from SC1B491D000 to SCS00003H00

10/27 Change F2 P/N from SP04301P120 to SP 040001B00

B B

R99

1 2

0_0402_5%

HDMI@

MMBT3904_NL_SOT23-3

HDMI_DET<4>

A A

9/20 Change R99 from HDMI@ to @

9/20 Change Q8,R100 from @ to HDMI@

+3VS

3 1

R103

R103 100K_0402_5%

100K_0402_5%

HDMI@

R100

1 2

150K_0402_5%

HDMI@

R101

200K_0402_5%

HDMI_HPD

1 2

10/28 Change JHDMI1 footprint from ACON_HMR2E-AK120D_19P-T to ACON_HMR2E-AK120D_19P-S

R102

R102 100K_0402_5%

100K_0402_5%

10/07 Update JHDMI1 footprint from ACON_HMR2E-AK120D_19P to ACON_HMR2E-AK120D_19P-T

HDMI_CLK<4>

HDMI_DATA<4>

Q9B

Q9B DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

HDMI@

1 2

R92

1 2

R94

8/19 Change Q9A Q9B to SB00000DH00 (S TR DMN66D0LDW-7 2N SOT363-6)

+5VS_HDMI +5VS_HDMI_F

C4090.1U_0402_16V4Z

HDMI@

C4090.1U_0402_16V4Z

C4100.1U_0402_16V4Z

C4110.1U_0402_16V4Z

C4120.1U_0402_16V4Z

R96

0_0805_5%

+5VS

+5VS_HDMI

W=60mil

HDMI@

2.2K_0402_5%

8/23 Update JHDMI1 Symbol (SUYIN_100042GR019S268ZR_19P-T) 8/23 Update JHDMI1 Symbol (SUYIN_100042GR019M23DZL_19P-T)

HDMI@

R98

R97

2.2K_0402_5%

1 2

1.1A_6V_SMD1812P110TF

HDMI_CLK-_CONN

HDMI_CLK+_CONN HDMI_TX0-_CONN

HDMI_TX0+_CONN HDMI_TX1-_CONN

HDMI_TX1+_CONN HDMI_TX2-_CONN

HDMI_TX2+_CONN

HDMI@

W=60mil

9/20 Add F2 on HDMI

HDMI@

D5 RB491D_SC59-3

RB491D_SC59-3

HDMI@F2

HDMI@

HDMI_HPD +5VS_HDMI_F

HDMIDAT_R HDMICLK_R

Q9A

Q9A DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

HDMI@

0_0402_5%@

C4150.1U_0402_16V4Z

C4160.1U_0402_16V4Z

C172

0.1U_0402_16V4Z

HDMI@

JHDMI1

HP_DET

+5V

DDC/CEC_GND

SDA

SCL

Reserved

CEC

CK-

CK_shield

CK+

D0-

D0_shield

D0+

D1-

D1_shield

D1+

D2-

D2_shield

D2+

ACON_HMR2E-AK120D

CONN@

GND GND GND GND

20 21 22 23

HDMICLK_R

HDMIDAT_R

9/7 Update JHDMI1 Symbol (ACON_HMR2E-AK120D_19P)

Security Classifica tion

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

http://laptop-motherboard-schematic.blogspot.com/

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/12 2012/08/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

HDMI Connector

P0VE6 Schematics

936Wednesday, November 17, 2010

1.0

Close to CRT CONN for ESD.

Modify C31- C308 C303 C307 C306 C304 BOM Structure 0615

1 1

DAC_RED<4>

DAC_GRN<4>

DAC_BLU<4>

2 2

CRT_HSYNC<4>

8/21 Change U2 U3 to SA00000RZ00 (TC7SET125FUF_S C70-5)

CRT_VSYNC<4>

3 3

8/21 Reserve R325 R326 for CRT buffer cost down

2.2K_0402_5%

CRT_DDC_DATA<4>

4 4

CRT_DDC_CLK<4>

R104

R109

150_0402_1%

+3VS

R105

2.2K_0402_5%

R108

150_0402_1%

R106

150_0402_1%

1 2

C179 0.1U_0402_16V4ZC179 0.1U_0402_16V4Z

IN A

GND3OUT Y

TC7SET125FUF_SC70-5

R325 0_0402_5%@R325 0_0402_5%@

1 2

C180 0.1U_0402_16V4ZC180 0.1U_0402_16V4Z

IN A

GND3OUT Y

TC7SET125FUF_SC70-5

R326 0_0402_5%@R326 0_0402_5%@

1 2

2.2K_0402_5%

Q11B

DMN66D0LDW-7_SOT363-6

Q11A

Q11A DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

Vcc

10/4 Change from +CRT_VCC to +CRT_VCC_F

R110

8/19 Change Q11A Q11B to SB00000DH00 (S TR DMN66D0LDW-7 2N SOT363-6)

http://laptop-motherboard-schematic.blogspot.com/

Change L12. L14, L15 to SM01000C600 2010/04/06

C176

C177

10P_0402_50V8J

+5VS

CRT_HSYNC_R

CRT_VSYNC_R

+CRT_VCC_F+3VS

R111

2.2K_0402_5%

VGA_DDC_DAT

VGA_DDC_CLK

R375 39_0402_5%R375 39_0402_5%

R376 39_0402_5%R376 39_0402_5%

10P_0402_50V8J

1 2

8/26 Update D8 P/N to SCS00003H00

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

L12

CHENG-HANN MBK1005470YZF 0402

1 2

L13

CHENG-HANN MBK1005470YZF 0402

1 2

L14

CHENG-HANN MBK1005470YZF 0402

1 2

C178

10P_0402_50V8J

C173

10P_0402_50V8J

C174

C174 10P_0402_50V8J

10P_0402_50V8J

8/31 Delete Net Name: CRT_HSYNC_1, CRT_VSYNC_1

9/3 Add R375 R376 for CRT

CRT PORT

+CRT_VCC

+5VS

W=40mils

2 1

RB491D_SC59-3

8/26 Update F1 P/N to SP040001B00

2010/08/12 2012/08/12

1.1A_6VDC_FUSE

CRT11 RED

VGA_DDC_DAT GREEN

JVGA_HS BLUE

JVGA_VS CRT4

VGA_DDC_CLK

Compal Secret Data

Deciphered Date

+CRT_VCC_F

PJDLC05C_SOT23-3

C175

10P_0402_50V8J

CRT_DET

8/22 Update JCRT1 Symbol from database (SUYIN_070546FR015M21TZR_15P)

0.1U_0402_16V4Z

C181

1 2

JCRT1

1 7

2 8

3 9

4 10 15

SUYIN_070546FR015M21TZR

CONN@

CRT_DET#

R112

R112 100K_0402_5%

100K_0402_5%

1 2

+CRT_VCC

RED

PJDLC05C_SOT23-3

GREEN

BLUE

JVGA_HS

JVGA_VS

+3VS

R107

R107 10K_0402_5%

10K_0402_5%

1 2

Q10

Q10 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

High: CRT Plugged

CRT_DET

CRT_DET#

8/26 Change Q10 to SB000009610 Standard Part

11/01 Add Net CRT4, CRT11 on JCRT.4 , JCRT. 11

16 17

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

CRT PORT

P0VE6 Schematics

1.0

10 36Wednesday, November 17, 2010

1.0

+3VALW

C182

0.1U_0402_16V4Z

A_RST#

R114

8.2K_0402_5%

1 2

1 1

NC7SZ08P5X_NL_SC70-5

R120 0_0402_5%@R120 0_0402_5%@

1 2

PLT_RST#

R115

R115 100K_0402_5%

100K_0402_5%

9/2 Change R120 from 0603 to 0402

9/16 Change U4,C182 from @ to mount, R120, R115 from mount to @

9/27 Change R115 from @ to mount

2 2

9/9 Add R384(@ 0 ohm) R385(0 ohm) on PCI-E RST

9/20 C183.2 link to R119.2 Foll ow CRB

PLT_RST# <17,19,20,25>

A_RST#

R119 33_0402_5%R119 33_0402_5%

UMI_RX0P<5> UMI_RX0N<5> UMI_RX1P<5> UMI_RX1N<5> UMI_RX2P<5> UMI_RX2N<5> UMI_RX3P<5> UMI_RX3N<5>

UMI_TX0P<5> UMI_TX0N<5> UMI_TX1P<5> UMI_TX1N<5> UMI_TX2P<5> UMI_TX2N<5> UMI_TX3P<5> UMI_TX3N<5>

+PCIE_VDDAN

PCIE_FTX_C_DRX_P1<19> PCIE_FTX_C_DRX_N1<19> PCIE_FTX_C_DRX_P2<17> PCIE_FTX_C_DRX_N2<17> PCIE_FTX_C_DRX_P3<20> PCIE_FTX_C_DRX_N3<20>

9/6 Change PCI-E from FCH to APU

9/15 Change PCI-E from APU to FCH

8/25 Update JBATT1 Symbol (LOTES_AAA-BAT-019-K01_2P)

+RTCBATT1

CONN@

JBATT1

LAN

LOTES_AAA-BAT-019-K01

3 3

WLAN

WWAN

DISP_CLK<4> DISP_CLK#<4>

APU_CLK<4> APU_CLK#<4>

CLK_PCIE_LAN<17> CLK_PCIE_LAN#<17>

CLK_PCIE_WLAN<20> CLK_PCIE_WLAN#<20>

CLK_PCIE_WWAN<19> CLK_PCIE_WWAN#<19>

9/6 Change D10 to SC600000B00 Standard Part

+RTCBATT1_R

W=20mil

+CHGRTC

D10

BAV70W_SOT323-3

NONCHARGE@

9/13 Add Net Name +RTCBATT1_RR

1 2

R244 1K_0402_5%

NONCHARGE@

+RTCBATT1+RTCBATT

9/13 Add NONCHARGE@ for D10 R244

CLK_48M_CR<18>

9/13 Change Net Name +RTCBATT1 to +RTCBATT2

+RTCBATT2_R

CHARGE@

+RTCBATT

CHARGE@

C392

0.1U_0402_16V4Z

4 4

D23

BAS40-04_SOT23-3

10/07 Change R392 from 1k to 0 ohm

10/08 Change R392 from 0 ohm to 1k ohm

9/13 Add C392,R392,D23(CHARGE@) for RTC Charge Circuit

+RTCBATT2

R3920_0402_5%

CHARGE@

+CHGRTC

11/01 Change R392 from 1k to 0 ohm

http://laptop-motherboard-schematic.blogspot.com/

150P_0402_50V8J

R121 590_0402_1%R121 590_0402_1% R118 2K_0402_1%R118 2K_0402_1%

C183

C184 .1U_0402_16V7KC184 .1U_0402_16V7K

1 2

C185 .1U_0402_16V7KC185 .1U_0402_16V7K

1 2

C188 .1U_0402_16V7KC188 .1U_0402_16V7K

1 2

C186 .1U_0402_16V7KC186 .1U_0402_16V7K

1 2

C187 .1U_0402_16V7KC187 .1U_0402_16V7K

1 2

C189 .1U_0402_16V7KC189 .1U_0402_16V7K

1 2

C190 .1U_0402_16V7KC190 .1U_0402_16V7K

1 2

C191 .1U_0402_16V7KC191 .1U_0402_16V7K

1 2

C192 .1U_0402_16V7KC192 .1U_0402_16V7K

1 2

C193 .1U_0402_16V7KC193 .1U_0402_16V7K

1 2

C194 .1U_0402_16V7KC194 .1U_0402_16V7K

1 2

C195 .1U_0402_16V7KC195 .1U_0402_16V7K

1 2

C379 .1U_0402_16V7KC379 .1U_0402_16V7K

1 2

C380 .1U_0402_16V7KC380 .1U_0402_16V7K

1 2

WWAN LAN WLAN

12 12

PCIE_FRX_DTX_P1<19> PCIE_FRX_DTX_N1<19> PCIE_FRX_DTX_P2<17> PCIE_FRX_DTX_N2<17> PCIE_FRX_DTX_P3<20> PCIE_FRX_DTX_N3<20>

R384 0_0402_5%@R384 0_0402_5%@ R385 0_0402_5%R385 0_0402_5%

1 2 1 2

PCIE_CALRP PCIE_CALRN

PCIE_FTX_DRX_P1 PCIE_FTX_DRX_N1 PCIE_FTX_DRX_P2 PCIE_FTX_DRX_N2 PCIE_FTX_DRX_P3 PCIE_FTX_DRX_N3

close to FCH within 1"

R125 0_0402_5%R125 0_0402_5%

1 2

R126 0_0402_5%R126 0_0402_5%

1 2

R127 0_0402_5%R127 0_0402_5%

1 2

R128 0_0402_5%R128 0_0402_5%

1 2

8/21 Delete R130,R131(No VGA)

R132 0_0402_5%R132 0_0402_5%

1 2

R133 0_0402_5%R133 0_0402_5%

1 2

R134 0_0402_5%R134 0_0402_5%

1 2

R135 0_0402_5%R135 0_0402_5%

1 2

R348 0_0402_5%R348 0_0402_5%

1 2

R349 0_0402_5%R349 0_0402_5%

1 2

DISP_CLK_R DISP_CLK#_R

APU_CLK_R APU_CLK#_R

CLK_PCIE_LAN_R CLK_PCIE_LAN#_R

CLK_PCIE_WLAN_R CLK_PCIE_WLAN#_R

CLK_PCIE_WWAN_R CLK_PCIE_WWAN#_R

8/23 Add R348 R349 for WWAN PCIE

9/1 Add R372 on CLK_48M_CR

9/7 Change R372 to 22 ohm

R372 22_0402_5%R372 22_0402_5%

1 2

C198

22P_0402_50V8J

C199

22P_0402_50V8J

1 2

1M_0603_5%

R139

25MHZ_20PF_7A25000012

10/08 Update U5 to SA000046H70 S IC 218-0792006 A13 HUDSON-M1 605P ABO!

U5E

PCIE_RST_L

UMI_RX0P_C UMI_RX0N_C UMI_RX1P_C UMI_RX1N_C UMI_RX2P_C UMI_RX2N_C UMI_RX3P_C UMI_RX3N_C

CLK_48M_CR_R

25M_CLK_X1

25M_CLK_X2 +RTCBATT_R

A_RST_L

AD26

UMI_TX0P

AD27

UMI_TX0N

AC28

UMI_TX1P

AC29

UMI_TX1N

AB29

UMI_TX2P

AB28

UMI_TX2N

AB26

UMI_TX3P

AB27

UMI_TX3N

AE24

UMI_RX0P

AE23

UMI_RX0N

AD25

UMI_RX1P

AD24

UMI_RX1N

AC24

UMI_RX2P

AC25

UMI_RX2N

AB25

UMI_RX3P

AB24

UMI_RX3N

AD29

PCIE_CALRP

AD28

PCIE_CALRN

AA28

GPP_TX0P

AA29

GPP_TX0N

Y29

GPP_TX1P

Y28

GPP_TX1N

Y26

GPP_TX2P

Y27

GPP_TX2N

W28

GPP_TX3P

W29

GPP_TX3N

AA22

GPP_RX0P

Y21

GPP_RX0N

AA25

GPP_RX1P

AA24

GPP_RX1N

W23

GPP_RX2P

V24

GPP_RX2N

W24

GPP_RX3P

W25

GPP_RX3N

M23

PCIE_RCLKP/NB_LNK_CLKP

P23

PCIE_RCLKN/NB_LNK_CLKN

U29

NB_DISP_CLKP

U28

NB_DISP_CLKN

T26

NB_HT_CLKP

T27

NB_HT_CLKN

V21

CPU_HT_CLKP

T21

CPU_HT_CLKN

V23

SLT_GFX_CLKP

T23

SLT_GFX_CLKN

L29

GPP_CLK0P

L28

GPP_CLK0N

N29

GPP_CLK1P

N28

GPP_CLK1N

M29

GPP_CLK2P

M28

GPP_CLK2N

T25

GPP_CLK3P

V25

GPP_CLK3N

L24

GPP_CLK4P

L23

GPP_CLK4N

P25

GPP_CLK5P

M25

GPP_CLK5N

P29

GPP_CLK6P

P28

GPP_CLK6N

N26

GPP_CLK7P

N27

GPP_CLK7N

T29

GPP_CLK8P

T28

GPP_CLK8N

L25

14M_25M_48M_OSC

L26

25M_X1

L27

25M_X2

S IC 218-0792006 A13 HUDSON-M1 FCBGA 0FA

PCI EXPRESS I/F

CLOCK GENERATOR

PCI CLKS

PCICLK4/14M_OSC/GPO39

PCI I/F

REQ2_L/CLK_REQ8_L/GPIO41 REQ3_L/CLK_REQ5_L/GPIO42

GNT3_L/CLK_REQ7_L/GPIO46

LPC

LDRQ1_L/CLK_REQ6_L/GPIO49

CPU

ALLOW_LDTSTP/DMA_ACTIVE_L

RTC

INTRUDER_ALERT_L

PCICLK1/GPO3 6 PCICLK2/GPO3 7 PCICLK3/GPO3 8

AD10/GPIO10 AD11/GPIO11 AD12/GPIO12 AD13/GPIO13 AD14/GPIO14 AD15/GPIO15 AD16/GPIO16 AD17/GPIO17 AD18/GPIO18 AD19/GPIO19 AD20/GPIO20 AD21/GPIO21 AD22/GPIO22 AD23/GPIO23 AD24/GPIO24 AD25/GPIO25 AD26/GPIO26 AD27/GPIO27 AD28/GPIO28 AD29/GPIO29 AD30/GPIO30 AD31/GPIO31

REQ1_L/GPIO40

GNT1_L/GPO44 GNT2_L/GPO45

INTE_L/GPIO32

INTF_L/GPIO33 INTG_L/GPIO34 INTH_L/GPIO35

SERIRQ/GPIO48

PROCHOT_L

VDDBT_RTC_G

PCICLK0

PCIRST_L

AD0/GPIO0 AD1/GPIO1 AD2/GPIO2 AD3/GPIO3 AD4/GPIO4 AD5/GPIO5 AD6/GPIO6 AD7/GPIO7 AD8/GPIO8 AD9/GPIO9

CBE0_L CBE1_L CBE2_L CBE3_L

FRAME_L

DEVSEL_L

IRDY_L

TRDY_L

PAR STOP_L PERR_L SERR_L REQ0_L

GNT0_L

CLKRUN_L

LOCK_L

LPCCLK0 LPCCLK1

LAD0 LAD1 LAD2 LAD3

LFRAME_L

LDRQ0_L

LDT_PG

LDT_STP_L LDT_RST_L

32K_X1

32K_X2

RTCCLK

W2 W1 W3 W4 Y1

AA1 AA4 AA3 AB1 AA5 AB2 AB6 AB5 AA6 AC2 AC3 AC4 AC1 AD1 AD2 AC6 AE2 AE1 AF8 AE3 AF1 AG1 AF2 AE9 AD9 AC11 AF6 AF4 AF3 AH2 AG2 AH3 AA8 AD5 AD8 AA10 AE8 AB9 AJ3 AE7 AC5 AF5 AE6 AE4 AE11 AH5 AH4 AC12 AD12 AJ5 AH6 AB12 AB11 AD7

AJ6 AG6 AG4 AJ4

H24 H25 J27 J26 H29 H28 G28 J25 AA18 AB19

G21 H21 K19 G22 J24

D2 B2 B1

SA000046HA0

8/25 Change FCH(U5) PN to SA000046H30

11/04 Change U5 PN to SA000046HA0 (S IC 218-0792006 A13 HUDSON-M1 FCBGA 0FA)

Security Classifica tion

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/12 2012/08/12

Compal Secret Data

Deciphered Date

T16PADT16PAD

PCI_CLK2

T17PADT17PAD

PE_GPIO0

10/05 PD 10k(R405) on CLKRUN

GPIO42

GPIO46

RTC_32KHI

RTC_32KHO

T18

PAD

PE_GPIO1

T19

PAD

1 2

R136 0_0402_5%R136 0_0402_5%

1 2

R137 22_0402_5%R137 22_0402_5%

1 2

R138 0_0402_5%R138 0_0402_5%

1 2

SUSCLK <25>

C200

1U_0402_6.3V6K

+3VS

Watchdog timer on NB_PWRGD

enable for pull-up disable for pull-down 20100527

R113

PCI_CLK1 <15>

PCI_CLK3 <15> PCI_CLK4 <15>

R113

10K_0402_5%

R116

10K_0402_5%

9/9 Change R117 R122 from mount to @ 9/15 PU PE_GPIO1 100k to +5VALW

PE_GPIO1

PE_GPIO0

10/11 Change Y1 from SJ100006600 to SJ132P7KW10

PCI_AD23 <15> PCI_AD24 <15> PCI_AD25 <15> PCI_AD26 <15> PCI_AD27 <15>

R405

10K_0402_5%

LPC_AD0 <25> LPC_AD1 <25> LPC_AD2 <25> LPC_AD3 <25> LPC_FRAME# <25>

SERIRQ <25>

ALLOW_STOP# <4> FCH_PROCHOT# <4> APU_PWRGD <4>

LDT_RST# <4>

R123 20M_0402_5%@ R123 20M_0402_5%@

1 2

C196

1 2

22P_0402_50V8J

R124

20M_0603_5%

C197

1 2

22P_0402_50V8J

APU_PWRGD

LPCCLK0 <15>

LPC_CLK0_EC < 25> CLK_PCI_DB <15>

11/15 Delete net U5_G22

10/07 Change R140 from 560 to 1k ohm

11/01 Add Net U5_G22 on U5.G22

1 2

R140 1K_0402_5%R140 1K_0402_5%

+RTCBATT

for Clear CMOS

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

R117 100K_0402_5%R117 100K_0402_5%

1 2

R122 100K_0402_5%@R 122 100K_0402_5%@

1 2

Close to FCH

RTC_32KHO

+1.8VS +3VS

FDV301N_NL_SOT23-3

Q12

OSC

32.768KHZ_12.5PF_9H03200413

RTC_32KHI

R129

10K_0402_5%

C396

C396 100P_0402_50V8J

100P_0402_50V8J

H_PWRGD_L <35>

10/04 Add 100p(C396) on H_PWRGD_L

W=20mil

CLRP1

@CLRP1

SHORT PADS

)&+3&,(3&,$&3,/3&57&

39(6FKHPDWLFV

11 36Wednesday, November 17, 2010

+5VALW

1.0

+ 25 hidden pages

Acer Aspire One 522 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual