Acer Aspire A715-71 Schematics

A

1 1

2 2

Co

B

C

D

mpal Confidential

E

C5

3 3

MMH MB Schematic Document

LA-E911

P

Rev:1A

2017.

4 4

Security Clas sification

Security Clas sification

Security Clas sification

Issued Date

Issued Date

Issued Date

TH

TH

TH

IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL

IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL

IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

04.11

01/29 2017/01/10

01/29 2017/01/10

01/29 2017/01/10

2016/

2016/

2016/

C

mpal Secret Data

mpal Secret Data

mpal Secret Data

Co

Co

Co

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

tle

tle

tle

Ti

Ti

Ti

Cover Sheet

Cover Sheet

Cover Sheet

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

stom

stom

stom

Cu

Cu

Cu

C5PM2_LA-E361P

Date: Sheet

Date: Sheet

D

Date: Sheet

164Tuesday, April 11, 2017

164Tuesday, April 11, 2017

164Tuesday, April 11, 2017

of

of

E

of

1A

1A

1A

A

B

C

D

E

Fan Control*2

Int

eDP

Mem

ory BUS

1 1

2 2

3 3

NGF

WLA

USB

HDMI

CON

F

N

port 7

N

Car

page 31

HDM

I x 4 lanes

page 37

PCI

E 2.0

5GT/s

3

port

page 34

PCI

E 3.0 x4

8GT/s

t 9-12

Por

page 32

PCIE 2.0
5GT/s

port

4

LAN(GbE)/CardReader

ltek 8411H

Rea

d Reader

page

RJ4

32.

5 conn.

Nvi

dia N17P-GX

with gDDR5 x4

page 23~29

SAT

PA R

SAT

38

page

page 30

eDP

PEG
8GT/s

Fle

xible IO

page

38

SA

A3.0

T

6.0 Gb/s

port

3

A Re-Driver

A D E P S 8 5 2 7

A HDD Conn.

Kab

(42X28) (SKL-H_4+2)

x16

ENE
KB9022/9032

ylake H PROCESSOR

BGA1440

cessor

Pro

X4

DMI

page 06~13

Skylake PCH - H
FCBGA(23X23)

837pin

LPC

CLK=

page 39

FCBGA

/eSPI BUS

24MHz

page 16~22

TP

M

page 41

Dua

1.2V

USBx8

HD

l Channel

DDR4 1333/1600

USB

3.0

conn

US

B (port 2)

48M

z

H

Audio

3.3V 24MHz

page 35

SPI

RTC

CKT.

page 21

Power On/Off CKT.

41

page

DC/DC Interface CKT.

4 4

w

er Circuit DC/DC

Po

page 43

page

44~61

A

Sub B

oard

LS-

E911P

Hall sensor/B

LS­USB

E912P

2/B

page 33

page 33

Touch Pad Int. KB D

PS2

/ I2C

page 41

Security Clas sification

Security Clas sification

Security Clas sification

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

Issued Date

Issued Date

Issued Date

page

SP

ROM x1

I

page 17

41

al Secret Data

al Secret Data

al Secret Data

Comp

Comp

2016/01/29 2017/01/10

2016/01/29 2017/01/10

2016/01/29 2017/01/10

C

Comp

Deciphered Date

Deciphered Date

Deciphered Date

D

erleaved

Memory

USB

3.0

Type -C x2

(po

rt 3,4)

/B

USB

page 36

. Speaker

Int

260 pi

n DDR4-SO-DIMM X1

BANK

0, 1, 2, 3

260pin

DDR4-SO-DIMM X1

BANK

4, 5, 6, 7

S

CMO
Camera

B (port 9)

US

2.0

USB

US

/B (port 5,6)

B

page 33

Codec

HDA

ALC

255

page 40

. DMIC

Int

le

le

le

tom

tom

tom

C5M

C5M

C5M

on Camera

Com

Com

Com

Blo

Blo

Blo

MH M/B LA-E911P

MH M/B LA-E911P

MH M/B LA-E911P

page 40

Tit

Tit

Tit

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Cus

Cus

Cus

Date: Sheet

Date: Sheet

Date: Sheet

page

30

page 30 page

pal Electronics, Inc.

pal Electronics, Inc.

pal Electronics, Inc.

ck Diagrams

ck Diagrams

ck Diagrams

E

page 42

page 14

page 15

ger Print

Fin

(port 10)

USB

page 42

UAJ

on Sub/B

264Tuesday, April 11, 2017

264Tuesday, April 11, 2017

264Tuesday, April 11, 2017

of

of

of

33

1A

1A

1A

A

1 1

CPU_

CPU_

XDP_TMS<9,18>

CPU_

XDP_TDI<9,18>

XDP_TDO<9,18>

CPU_

XDP_TCK0<9,18>

CPU_

JTAG_TCK1<18>

PCH_

If

need debug from usb port. this cmc@ need pop

+1.

0VS_VCCSTG

TMS/TDI

pin CPU on-die termination

2 2

1.0

Modify

Place

Place

to PCH side

to CPU side

+1.

0VS_VCCSTG

RC5

RC6

RC7

RC1

RC8

RC1

CPU_

CPU_
CPU_
PCH_

1 2

4 51_0402_5%@

1 2

3 51_0402_1%CMC@

XDP_TMS
XDP_TDI

XDP_TDO
XDP_TCK0
JTAG_TCK1

12

51_0402_5%CMC@

12

51_0402_5%CMC@

100_0402_1%CMC@

12

100_0402_1%CMC@

12

CPU_

CPU_

CPU_

CPU_

PCH_

CPU_

XDP_TCK0

B

XDP_TMS

XDP_TDI

XDP_TDO

JTAG_TCK1

XDP_TDO

C

AKE_HALO

1_TXP[0]

1_TXP[1]
1_TXN[1]
1_TXP[2]
1_TXN[2]
1_TXP[3]
1_TXN[3]

1_AUXP
1_AUXN

2_TXP[0]
2_TXN[0]
2_TXP[1]
2_TXN[1]
2_TXP[2]
2_TXN[2]
2_TXP[3]
2_TXN[3]

2_AUXP
2_AUXN

3_TXP[0]
3_TXN[0]
3_TXP[1]
3_TXN[1]
3_TXP[2]
3_TXN[2]
3_TXP[3]
3_TXN[3]

3_AUXP
3_AUXN

SKYL

BGA144 0

4

OF 14

ED
EDP_TXN[0]
ED
ED
ED
ED
ED
ED

ED
ED

P_DISP_UTIL

ED

P_RCOMP

ED

OC_AUDIO_CLK

PR

OC_AUDIO_SDI

PR

PR

OC_AUDIO_SDO

P_TXP[0]

P_TXP[1]
P_TXN[1]
P_TXN[2]
P_TXP[2]
P_TXN[3]
P_TXP[3]

P_AUXP
P_AUXN

K36

DDI

K37

DDI1_TXN[0]

J35

DDI

J34

DDI

H37

DDI

H36

DDI

J37

DDI

J38

DDI

D27

DDI

E27

DDI

H34

DDI

H33

DDI

F37

DDI

G38

DDI

F34

DDI

F35

DDI

E37

DDI

E36

DDI

F26

DDI

E26

DDI

C34

DDI

D34

DDI

B36

DDI

B34

DDI

F33

DDI

E33

DDI

C33

DDI

B33

DDI

A27

DDI

B27

DDI

SKL-H_BGA1440

@

UC1D

D

D29
E29
F28
E28
B29
A29
B28
C28

C26
B26

A33

EDP_

COMP

D37

G27
G25
G29

?REV = 1

CAD note:
Trace width=20 mils,Spacing=25mil,Max length=100mils

CPU_

DISPA_SDI

TXP0 <30>

EDP_

TXN0 <30>

EDP_

TXP1 <30>

EDP_
EDP_

TXN1 <30>

EDP_

TXN2 <30>

EDP_

TXP2 <30>

EDP_

TXN3 <30>
TXP3 <30>

EDP_

AUXP <30>

EDP_

AUXN <30>

EDP_

RC2

20_0402_5%

Close to CPU

<eDP>

0VS_VCCIO

+1.

12

RC124.9_0402_1%

DISPA_BCLK <18>

CPU_
CPU_

12

DISPA_SDO <18>

CPU_

DISPA_SDI_R <18>

E

3 3

UC1

SR32S@

IC CL8067702870309 SR32S B0 2.5G ABO!

S

SA0000AD850

UV1

G0@

IC N17P-G0-A1 FCBGA 908P GPU 1706

S

SA0000A0540

UC1

SR32Q@

IC CL8067702870109 SR32Q B0 2.8G ABO!

S

SA0000AD750

UV1

G1@

IC N17P-G1-A1 FCBGA 908P GPU 1707

S

SA0000A0660

UH1

SR30W@

IC GL82HM175 SR30W D1 FCBGA PCH-H ABO!

S

SA0000ADB30

1.A Modify

ZZZ

DAZ@

C5MMH LA-E911P LS-E911P/E912P

PCB

DAZ20Z00102

1A Modify

4 4

Security Clas sification

Security Clas sification

Security Clas sification

2016/11/03 2017/01/10

2016/11/03 2017/01/10

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2016/11/03 2017/01/10

C

mpal Secret Data

mpal Secret Data

mpal Secret Data

Co

Co

Co

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

tle

tle

tle

Ti

Ti

Ti

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Cu

Cu

Cu

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SKL-H(1/9)DDI,EDP

SKL-H(1/9)DDI,EDP

SKL-H(1/9)DDI,EDP

stom

stom

stom

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

1A

1A

1A

664Tuesday, April 11, 2017

664Tuesday, April 11, 2017

664Tuesday, April 11, 2017

of

of

E

of

A

terleaved Memory

In

B

C

D

E

DDR_

DDR_

DDR_

DDR_

A_D[0..15]<14>

A_D[16..31]<14>

A_D[32..47]<14>

A_D[48..63]<14>

1 1

2 2

3 3

DDR_

A_D0
A_D1

DDR_

A_D2

DDR_

A_D3

DDR_

A_D4

DDR_
DDR_

A_D5

DDR_A_D6

A_D7

DDR_

A_D8

DDR_

A_D9

DDR_

A_D10

DDR_
DDR_

A_D11

DDR_

A_D12

DDR_

A_D13
A_D14

DDR_

A_D15

DDR_

A_D16

DDR_

A_D17

DDR_

A_D18

DDR_
DDR_

A_D19

DDR_

A_D20
A_D21

DDR_

A_D22

DDR_

A_D23

DDR_

A_D24

DDR_

A_D25

DDR_
DDR_

A_D26

DDR_

A_D27

DDR_

A_D28
A_D29

DDR_

A_D30

DDR_

A_D31

DDR_

A_D32

DDR_
DDR_

A_D33

DDR_

A_D34

DDR_

A_D35
A_D36

DDR_

A_D37

DDR_

A_D38

DDR_

A_D39

DDR_
DDR_

A_D40

DDR_

A_D41

DDR_

A_D42

DDR_

A_D43
A_D44

DDR_

A_D45

DDR_

A_D46

DDR_
DDR_

A_D47

DDR_

A_D48

DDR_

A_D49

DDR_

A_D50
A_D51

DDR_

A_D52

DDR_

A_D53

DDR_
DDR_

A_D54

DDR_

A_D55

DDR_

A_D56

DDR_

A_D57

DDR_

A_D58
A_D59

DDR_

A_D60

DDR_
DDR_

A_D61

DDR_

A_D62
A_D63

DDR_

UC1A

BR6

DDR0

_DQ[0]

BT6

DDR0

_DQ[1]

BP3

_DQ[2]

DDR0

BR3

_DQ[3]

DDR0

BN5

_DQ[4]

DDR0

BP6

DDR0_DQ[5]

BP2

DDR0_DQ[6]

BN3

DDR0

_DQ[7]

BL4

_DQ[8]

DDR0

BL5

_DQ[9]

DDR0

BL2

_DQ[10]

DDR0

BM1

_DQ[11]

DDR0

BK4

DDR0_DQ[12]

BK5

DDR0

_DQ[13]

BK1

DDR0

_DQ[14]

BK2

DDR0

_DQ[15]

BG4

DDR0

_DQ[16]/DDR0_DQ[32]

BG5

_DQ[17]/DDR0_DQ[33]

DDR0

BF4

DDR0_DQ[18]/DDR0_DQ[34]

BF5

DDR0_DQ[19]/DDR0_DQ[35]

BG2

DDR0

_DQ[20]/DDR0_DQ[36]

BG1

DDR0

_DQ[21]/DDR0_DQ[37]

BF1

DDR0

_DQ[22]/DDR0_DQ[38]

BF2

_DQ[23]/DDR0_DQ[39]

DDR0

BD2

_DQ[24]/DDR0_DQ[40]

DDR0

BD1

DDR0_DQ[25]/DDR0_DQ[41]

BC4

DDR0_DQ[26]/DDR0_DQ[42]

BC5

DDR0

_DQ[27]/DDR0_DQ[43]

BD5

DDR0

_DQ[28]/DDR0_DQ[44]

BD4

DDR0

_DQ[29]/DDR0_DQ[45]

BC1

_DQ[30]/DDR0_DQ[46]

DDR0

BC2

_DQ[31]/DDR0_DQ[47]

DDR0

AB1

DDR0_DQ[32]/DDR1_DQ[0]

AB2

DDR0

_DQ[33]/DDR1_DQ[1]

AA4

DDR0

_DQ[34]/DDR1_DQ[2]

AA5

DDR0

_DQ[35]/DDR1_DQ[3]

AB5

DDR0

_DQ[36]/DDR1_DQ[4]

AB4

_DQ[37]/DDR1_DQ[5]

DDR0

AA2

DDR0_DQ[38]/DDR1_DQ[6]

AA1

DDR0_DQ[39]/DDR1_DQ[7]

V5

DDR0

_DQ[40]/DDR1_DQ[8]

V2

DDR0

_DQ[41]/DDR1_DQ[9]

U1

DDR0

_DQ[42]/DDR1_DQ[10]

U2

_DQ[43]/DDR1_DQ[11]

DDR0

V1

_DQ[44]/DDR1_DQ[12]

DDR0

V4

DDR0_DQ[45]/DDR1_DQ[13]

U5

DDR0_DQ[46]/DDR1_DQ[14]

U4

DDR0

_DQ[47]/DDR1_DQ[15]

R2

DDR0

_DQ[48]/DDR1_DQ[32]

P5

DDR0

_DQ[49]/DDR1_DQ[33]

R4

_DQ[50]/DDR1_DQ[34]

DDR0

P4

_DQ[51]/DDR1_DQ[35]

DDR0

R5

DDR0_DQ[52]/DDR1_DQ[36]

P2

DDR0

_DQ[53]/DDR1_DQ[37]

R1

DDR0

_DQ[54]/DDR1_DQ[38]

P1

DDR0

_DQ[55]/DDR1_DQ[39]

M4

DDR0

_DQ[56]/DDR1_DQ[40]

M1

_DQ[57]/DDR1_DQ[41]

DDR0

L4

DDR0_DQ[58]/DDR1_DQ[42]

L2

DDR0_DQ[59]/DDR1_DQ[43]

M5

DDR0

_DQ[60]/DDR1_DQ[44]

M2

DDR0

_DQ[61]/DDR1_DQ[45]

L5

DDR0

_DQ[62]/DDR1_DQ[46]

L1

_DQ[63]/DDR1_DQ[47]

DDR0

BA2

DDR0_ECC[0]

BA1

DDR0_ECC[1]

AY4

DDR0

_ECC[2]

AY5

DDR0

_ECC[3]

BA5

DDR0

_ECC[4]

BA4

_ECC[5]

DDR0

AY1

DDR0

_ECC[6]

AY2

DDR0_ECC[7]

DDR

CHANNEL A

SKL-H_BGA1440

REV = 1

@

SKYLAKE_HALO

BGA1440

_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

DDR0

_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0

_WE#/DDR0_CAB[2]/DDR0_MA[14]

_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR0

_MA[1]/DDR0_CAB[8]/DDR0_MA[1]

DDR0

_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

_MA[5]/DDR0_CAA[0]/DDR0_MA[5]

DDR0
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0

_MA[8]/DDR0_CAA[3]/DDR0_MA[8]

DDR0

_MA[9]/DDR0_CAA[1]/DDR0_MA[9]

DDR0

_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0

_MA[12]/DDR0_CAA[6]/DDR0_MA[12]

DDR0
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0

_MA[15]/DDR0_CAA[8]/DDR0_ACT#

DDR0

_DQSN[2]/DDR0_DQSN[4]

DDR0

_DQSN[3]/DDR0_DQSN[5]

_DQSP[4]/DDR1_DQSP[0]

DDR0
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0

_DQSP[7]/DDR1_DQSP[5]

_DQSP[2]/DDR0_DQSP[4]

DDR0
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0

_DQSN[5]/DDR1_DQSN[1]

DDR0

_DQSN[6]/DDR1_DQSN[4]

DDR0

_DQSN[7]/DDR1_DQSN[5]

1 OF 14

DDR0

_CKP[0]

DDR0

_CKN[0]
_CKN[1]

DDR0

_CKP[1]

DDR0

_CLKP[2]

DDR0

DDR0_CLKN[2]

DDR0_CLKP[3]

DDR0

_CLKN[3]

_CKE[0]

DDR0

_CKE[1]

DDR0

_CKE[2]

DDR0
DDR0_CKE[3]

DDR0

_CS#[0]

DDR0

_CS#[1]

DDR0

_CS#[2]
_CS#[3]

DDR0

DDR0_ODT[0]
DDR0

_ODT[1]

DDR0

_ODT[2]

DDR0

_ODT[3]

DDR0

_MA[3]

DDR0

_MA[4]

DDR0

_PAR

_ALERT#

DDR0

DDR0

_DQSN[0]

DDR0

_DQSN[1]

DDR0

_DQSP[0]
_DQSP[1]

DDR0

DDR0

_DQSP[8]

DDR0_DQSN[8]

?

DDR

CHANNEL B

SKYLAKE_HALO

BGA1440

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1

_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1

_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
_BA[1]/DDR1_CAB[6]/DDR1_BA[1]

DDR1

_BA[2]/DDR1_CAA[5]/DDR1_BG[0]

DDR1

DDR1

_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR1

_MA[1]/DDR1_CAB[8]/DDR1_MA[1]

DDR1

_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1

_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1

_MA[8]/DDR1_CAA[3]/DDR1_MA[8]

DDR1

_MA[9]/DDR1_CAA[1]/DDR1_MA[9]

_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1

_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1

_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1

_MA[15]/DDR1_CAA[8]/DDR1_ACT#

DDR1
DDR1
DDR1
DDR1
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSN[5]/DDR1_DQSN[3]

DDR1
DDR1
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1
DDR1

2

OF 14

DDR1

_CKP[0]
_CKN[0]

DDR1

_CKN[1]

DDR1

_CKP[1]

DDR1

DDR1_CLKP[2]

DDR1_CLKN[2]

DDR1

_CLKP[3]
_CLKN[3]

DDR1

_CKE[0]

DDR1

_CKE[1]

DDR1
DDR1_CKE[2]
DDR1

_CKE[3]

DDR1

_CS#[0]

DDR1

_CS#[1]
_CS#[2]

DDR1
DDR1_CS#[3]

DDR1

_ODT[0]

DDR1

_ODT[1]

DDR1

_ODT[2]
_ODT[3]

DDR1

DDR1

_MA[3]
_MA[4]

DDR1

_PAR

DDR1

_ALERT#

DDR1

_DQSN[0]/DDR0_DQSN[2]
_DQSN[1]/DDR0_DQSN[3]
_DQSN[2]/DDR0_DQSN[6]
_DQSN[3]/DDR0_DQSN[7]

DDR1

_DQSN[6]

DDR1

_DQSN[7]

_DQSP[0]/DDR0_DQSP[2]
_DQSP[1]/DDR0_DQSP[3]

_DQSP[4]/DDR1_DQSP[2]
_DQSP[5]/DDR1_DQSP[3]

DDR1

_DQSP[6]
_DQSP[7]

DDR1

DDR1_DQSP[8]

_DQSN[8]

DDR1

DDR_VREF_CA

_VREF_DQ

DDR0

_VREF_DQ

DDR1

AM9
AN9
AM8
AM7
AM11
AM10
AJ10
AJ11

AT8
AT10
AT7
AT11

AF11
AE7
AF10
AE10

AF7
AE8
AE9
AE11

AH10
AH11
AF8

AH8
AH9
AR9

AJ9
AK6
AK5
AL5
AL6
AM6
AN7
AN10
AN8
AR11
AH7
AN11
AR10
AF9
AR7
AT9

AJ7
AR8

BP9
BL9
BG9
BC9
AC9
W9
R9
M9

BR9
BJ9
BF9
BB9
AA9
V9
P9
L9

AW9
AY9

BN13
BP13
BR13

B_CLK0

DDR_

B_CLK#0

DDR_

B_CLK#1

DDR_

B_CLK1

DDR_

B_CKE0

DDR_
DDR_

B_CKE1

B_CS#0

DDR_

B_CS#1

DDR_

DDR_

B_ODT0
B_ODT1

DDR_

B_MA16

DDR_
DDR_

B_MA14

DDR_

B_MA15

B_BA0

DDR_

B_BA1

DDR_

B_BG0

DDR_

DDR_

B_MA0

DDR_

B_MA1

DDR_

B_MA2
B_MA3

DDR_

B_MA4

DDR_

B_MA5

DDR_

B_MA6

DDR_
DDR_

B_MA7

DDR_

B_MA8

DDR_

B_MA9

DDR_

B_MA10
B_MA11

DDR_

B_MA12

DDR_

B_MA13

DDR_
DDR_

B_BG1

DDR_

B_ACT#

DDR_

B_PARITY
B_ALERT#

DDR_

DDR_

B_DQS#0

DDR_

B_DQS#1

DDR_

B_DQS#2

DDR_

B_DQS#3

DDR_

B_DQS#4
B_DQS#5

DDR_

B_DQS#6

DDR_
DDR_

B_DQS#7

B_DQS0

DDR_
DDR_

B_DQS1

DDR_

B_DQS2
B_DQS3

DDR_

B_DQS4

DDR_

B_DQS5

DDR_
DDR_

B_DQS6

DDR_B_DQS7

+0.6V_VREFCA

+0.6V_B_VREFDQ

B_CLK0 <15>

DDR_

B_CLK#0 <15>

DDR_

B_CLK#1 <15>

DDR_
DDR_

B_CLK1 <15>

DDR_

B_CKE0 <15>

DDR_

B_CKE1 <15>

B_CS#0 <15>

DDR_

B_CS#1 <15>

DDR_

DDR_

B_ODT0 <15>

DDR_

B_ODT1 <15>

DDR_

B_MA16 <15>

DDR_

B_MA14 <15>

DDR_

B_MA15 <15>

B_BA0 <15>

DDR_

B_BA1 <15>

DDR_

B_BG0 <15>

DDR_

DDR_

B_MA0 < 15>

DDR_

B_MA1 < 15>

DDR_

B_MA2 < 15>

DDR_B_MA3 <15>

B_MA4 < 15>

DDR_

B_MA5 < 15>

DDR_
DDR_

B_MA6 < 15>

DDR_

B_MA7 < 15>

DDR_

B_MA8 < 15>

DDR_

B_MA9 < 15>

DDR_B_MA10 <15>

B_MA11 <15>

DDR_

B_MA12 <15>

DDR_

B_MA13 <15>

DDR_
DDR_

B_BG1 <15>

DDR_

B_ACT# <15>

DDR_B_PARITY <15>

B_ALERT# <15>

DDR_

DDR_

B_DQS#0 <15>

DDR_

B_DQS#1 <15>

DDR_

B_DQS#2 <15>

DDR_B_DQS#3 <15>

B_DQS#4 <15>

DDR_

B_DQS#5 <15>

DDR_

B_DQS#6 <15>

DDR_

B_DQS#7 <15>

DDR_

DDR_

B_DQS0 <15>

DDR_B_DQS1 <15>

B_DQS2 <15>

DDR_

B_DQS3 <15>

DDR_

B_DQS4 <15>

DDR_

B_DQS5 <15>

DDR_
DDR_B_DQS6 <15>

B_DQS7 <15>

DDR_

.6V_VREFCA

+0

+0

.6V_B_VREFDQ

DDR_

A_CLK0

AG1

A_CLK#0

DDR_

AG2

A_CLK#1

DDR_

AK1

A_CLK1

DDR_

AK2
AL3
AK3
AL2
AL1

A_CKE0

DDR_

AT1

A_CKE1

DDR_

AT2
AT3
AT5

A_CS#0

DDR_

AD5

A_CS#1

DDR_

AE2
AD2
AE5

DDR_

A_ODT0

AD3

DDR_

A_ODT1

AE4
AE1
AD4

A_BA0

DDR_

AH5

A_BA1

DDR_

AH1

DDR_

A_BG0

AU1

DDR_

A_MA16

AH4

A_MA14

DDR_

AG4

A_MA15

DDR_

AD1

A_MA0

DDR_

AH3

DDR_

A_MA1

AP4

DDR_

A_MA2

AN4

DDR_

A_MA3

AP5

A_MA4

DDR_

AP2

A_MA5

DDR_

AP1

A_MA6

DDR_

AP3

A_MA7

DDR_

AN1

DDR_

A_MA8

AN3

DDR_

A_MA9

AT4

DDR_

A_MA10

AH2

DDR_

A_MA11

AN2

A_MA12

DDR_

AU4

A_MA13

DDR_

AE3

A_BG1

DDR_

AU2

DDR_

A_ACT#

AU3

DDR_

A_PARITY

AG3

DDR_

A_ALERT#

AU5

A_DQS#0

DDR_

BR5

DDR_

A_DQS#1

BL3

DDR_

A_DQS#2

BG3

DDR_

A_DQS#3

BD3

DDR_

A_DQS4

AB3

DDR_

A_DQS5

V3

A_DQS6

DDR_

R3

A_DQS7

DDR_

M3

DDR_

A_DQS0

BP5

A_DQS1

DDR_

BK3

DDR_

A_DQS2

BF3

DDR_

A_DQS3

BC3

A_DQS#4

DDR_

AA3

A_DQS#5

DDR_

U3

A_DQS#6

DDR_

P3

DDR_

A_DQS#7

L3

AY3
BA3

A_CLK0 <14>

DDR_

A_CLK#0 <14>

DDR_

A_CLK#1 <14>

DDR_

A_CLK1 <14>

DDR_

DDR_

A_CKE0 <14>

DDR_

A_CKE1 <14>

A_CS#0 <14>

DDR_

A_CS#1 <14>

DDR_

DDR_

A_ODT0 <14>

DDR_

A_ODT1 <14>

DDR_

A_BA0 <14>

DDR_

A_BA1 <14>

DDR_

A_BG0 <14>

DDR_

A_MA16 <14>
A_MA14 <14>

DDR_

A_MA15 <14>

DDR_

DDR_

A_MA0 <14>

DDR_

A_MA1 <14>

DDR_

A_MA2 <14>

DDR_

A_MA3 <14>

DDR_A_MA4 <14 >

A_MA5 <14>

DDR_

A_MA6 <14>

DDR_
DDR_

A_MA7 <14>

DDR_

A_MA8 <14>

DDR_

A_MA9 <14>

DDR_

A_MA10 <14>

DDR_A_MA11 <14>

A_MA12 <14>

DDR_

A_MA13 <14>

DDR_

A_BG1 <14>

DDR_
DDR_

A_ACT# <14>

DDR_

A_PARITY <14>

DDR_A_ALERT# <14>

A_DQS#0 <14>

DDR_
DDR_

A_DQS#1 <14>

DDR_

A_DQS#2 <14>

DDR_

A_DQS#3 <14>

DDR_A_DQS4 <14>

A_DQS5 <14>

DDR_

A_DQS6 <14>

DDR_

A_DQS7 <14>

DDR_

DDR_

A_DQS0 <14>

DDR_

A_DQS1 <14>

DDR_A_DQS2 <14>

A_DQS3 <14>

DDR_

A_DQS#4 <14>

DDR_

A_DQS#5 <14>

DDR_

A_DQS#6 <14>

DDR_
DDR_A_DQS#7 <14>

DDR_

DDR_

DDR_

DDR_

B_D[0..15]<15>

B_D[16..31]<15>

B_D[32..47]<15>

B_D[48..63]<15>

close

to CPU

B_D0

DDR_

B_D1

DDR_

B_D2

DDR_

B_D3

DDR_
DDR_

B_D4

DDR_B_D5

B_D6

DDR_

B_D7

DDR_

B_D8

DDR_

B_D9

DDR_
DDR_

B_D10

DDR_

B_D11

DDR_

B_D12
B_D13

DDR_

B_D14

DDR_

B_D15

DDR_

B_D16

DDR_

B_D17

DDR_
DDR_

B_D18

DDR_

B_D19
B_D20

DDR_

B_D21

DDR_

B_D22

DDR_

B_D23

DDR_

B_D24

DDR_
DDR_

B_D25

DDR_

B_D26

DDR_

B_D27
B_D28

DDR_

B_D29

DDR_

B_D30

DDR_

B_D31

DDR_
DDR_

B_D32

DDR_

B_D33

DDR_

B_D34
B_D35

DDR_

B_D36

DDR_

B_D37

DDR_

B_D38

DDR_
DDR_

B_D39

DDR_

B_D40

DDR_

B_D41

DDR_

B_D42
B_D43

DDR_

B_D44

DDR_

B_D45

DDR_
DDR_

B_D46

DDR_

B_D47

DDR_

B_D48

DDR_

B_D49
B_D50

DDR_

B_D51

DDR_

B_D52

DDR_
DDR_

B_D53

DDR_

B_D54

DDR_

B_D55

DDR_

B_D56

DDR_

B_D57
B_D58

DDR_

B_D59

DDR_
DDR_

B_D60

DDR_

B_D61
B_D62

DDR_
DDR_

B_D63

SM_RCOMP0

12

RC17121_0402_1%

_RCOMP1

SM

12

RC1

875_0402_1%

SM_RCOMP2

RC19100_0402_1%

12

UC1B

BT11

DDR1

_DQ[0]/DDR0_DQ[16]

BR11

_DQ[1]/DDR0_DQ[17]

DDR1

BT8

_DQ[2]/DDR0_DQ[18]

DDR1

BR8

_DQ[3]/DDR0_DQ[19]

DDR1

BP11

DDR1_DQ[4]/DDR0_DQ[20]

BN11

DDR1_DQ[5]/DDR0_DQ[21]

BP8

DDR1

_DQ[6]/DDR0_DQ[22]

BN8

_DQ[7]/DDR0_DQ[23]

DDR1

BL12

_DQ[8]/DDR0_DQ[24]

DDR1

BL11

_DQ[9]/DDR0_DQ[25]

DDR1

BL8

_DQ[10]/DDR0_DQ[26]

DDR1

BJ8

DDR1_DQ[11]/DDR0_DQ[27]

BJ11

DDR1

_DQ[12]/DDR0_DQ[28]

BJ10

DDR1

_DQ[13]/DDR0_DQ[29]

BL7

DDR1

_DQ[14]/DDR0_DQ[30]

BJ7

DDR1

_DQ[15]/DDR0_DQ[31]

BG11

_DQ[16]/DDR0_DQ[48]

DDR1

BG10

DDR1_DQ[17]/DDR0_DQ[49]

BG8

DDR1_DQ[18]/DDR0_DQ[50]

BF8

DDR1

_DQ[19]/DDR0_DQ[51]

BF11

DDR1

_DQ[20]/DDR0_DQ[52]

BF10

DDR1

_DQ[21]/DDR0_DQ[53]

BG7

_DQ[22]/DDR0_DQ[54]

DDR1

BF7

_DQ[23]/DDR0_DQ[55]

DDR1

BB11

DDR1_DQ[24]/DDR0_DQ[56]

BC11

DDR1_DQ[25]/DDR0_DQ[57]

BB8

DDR1

_DQ[26]/DDR0_DQ[58]

BC8

DDR1

_DQ[27]/DDR0_DQ[59]

BC10

DDR1

_DQ[28]/DDR0_DQ[60]

BB10

_DQ[29]/DDR0_DQ[61]

DDR1

BC7

_DQ[30]/DDR0_DQ[62]

DDR1

BB7

DDR1_DQ[31]/DDR0_DQ[63]

AA11

DDR1

_DQ[32]/DDR1_DQ[16]

AA10

DDR1

_DQ[33]/DDR1_DQ[17]

AC11

DDR1

_DQ[34]/DDR1_DQ[18]

AC10

DDR1

_DQ[35]/DDR1_DQ[19]

AA7

_DQ[36]/DDR1_DQ[20]

DDR1

AA8

DDR1_DQ[37]/DDR1_DQ[21]

AC8

DDR1_DQ[38]/DDR1_DQ[22]

AC7

DDR1

_DQ[39]/DDR1_DQ[23]

W8

DDR1

_DQ[40]/DDR1_DQ[24]

W7

DDR1

_DQ[41]/DDR1_DQ[25]

V10

_DQ[42]/DDR1_DQ[26]

DDR1

V11

_DQ[43]/DDR1_DQ[27]

DDR1

W11

DDR1_DQ[44]/DDR1_DQ[28]

W10

DDR1_DQ[45]/DDR1_DQ[29]

V7

DDR1

_DQ[46]/DDR1_DQ[30]

V8

DDR1

_DQ[47]/DDR1_DQ[31]

R11

DDR1

_DQ[48]

P11

_DQ[49]

DDR1

P7

_DQ[50]

DDR1

R8

DDR1_DQ[51]

R10

DDR1

_DQ[52]

P10

DDR1

_DQ[53]

R7

DDR1

_DQ[54]

P8

DDR1

_DQ[55]

L11

_DQ[56]

DDR1

M11

DDR1_DQ[57]

L7

DDR1_DQ[58]

M8

DDR1

_DQ[59]

L10

DDR1

_DQ[60]

M10

DDR1

_DQ[61]

M7

_DQ[62]

DDR1

L8

_DQ[63]

DDR1

AW11

DDR1_ECC[0]

AY11

DDR1

_ECC[1]

AY8

DDR1

_ECC[2]

AW8

DDR1

_ECC[3]

AY10

_ECC[4]

DDR1

AW10

DDR1

_ECC[5]

AY7

DDR1_ECC[6]

AW7

_ECC[7]

DDR1

G1

DDR_RCOMP[0]

H1

RCOMP[1]

DDR_

J2

RCOMP[2]

DDR_

SKL-H_BGA1440

@

REV = 1 ?

4 4

curity Classification

curity Classificat ion

curity Classificat ion

Se

Se

Se

Is

Is

Is

sued Date

sued Date

sued Date

S SHEE T OF ENGINEERI NG DR AWING IS THE PROPRIE TARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

S SHEE T OF ENGINEERI NG DR AWING IS THE PROPRIE TARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

S SHEE T OF ENGINEERI NG DR AWING IS THE PROPRIE TARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THI

THI

THI
AND TRADE SECRET INFORM ATION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORM ATION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORM ATION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/

2016/

2016/

11/03 2017/01/10

11/03 2017/01/10

11/03 2017/01/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Dat e

Deciphered Dat e

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Ti

Ti

Ti

tle

tle

tle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

stom

stom

stom

Cu

Cu

Cu

Date: Sheet

Date: Sheet

D

Date: Sheet

L-H(2/9)DDRIII

L-H(2/9)DDRIII

L-H(2/9)DDRIII

SK

SK

SK

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

Tuesday, April 11, 2017

Tuesday, April 11, 2017

Tuesday, April 11, 2017

E

1A

1A

1A

64

64

64

7

7

7

of

of

of

A

B

C

D

E

1 1

_GTX_C_HRX_P15

1 2

_GTX_HRX_P15<23>

PEG

_GTX_HRX_N15<23>

PEG

PEG

_GTX_HRX_P14<23>

PEG

_GTX_HRX_N14<23>

_GTX_HRX_P13<23>

PEG

_GTX_HRX_N13<23>

PEG

_GTX_HRX_P12<23>

PEG
PEG

_GTX_HRX_N12<23>

PEG

_GTX_HRX_P11<23>

PEG

_GTX_HRX_N11<23>

_GTX_HRX_P10<23>

PEG

_GTX_HRX_N10<23>

PEG

PEG

_GTX_HRX_P9<23>

PEG

_GTX_HRX_N9<23>

_GTX_HRX_P8<23>

PEG

_GTX_HRX_N8<23>

2 2

3 3

PEG

PEG
PEG

PEG
PEG_GTX_HRX_N6<23>

PEG
PEG

PEG
PEG

PEG
PEG

PEG
PEG

PEG
PEG

PEG
PEG

_GTX_HRX_P7<23>
_GTX_HRX_N7<23>

_GTX_HRX_P6<23>

_GTX_HRX_P5<23>
_GTX_HRX_N5<23>

_GTX_HRX_P4<23>
_GTX_HRX_N4<23>

_GTX_HRX_P3<23>
_GTX_HRX_N3<23>

_GTX_HRX_P2<23>
_GTX_HRX_N2<23>

_GTX_HRX_P1<23>
_GTX_HRX_N1<23>

_GTX_HRX_P0<23>
_GTX_HRX_N0<23>

CC6
CC8

0 0.22U_0201_6.3V6KVGA@

CC1

2 0.22U_0201_6.3V6KVGA@

CC1

CC1

4 0.22U_0201_6.3V6KVGA@

CC1

5 0.22U_0201_6.3V6KVGA@

CC3

7 0.22U_0201_6.3V6KVGA@

CC1

9 0.22U_0201_6.3V6KVGA@

CC1
CC2

1 0.22U_0201_6.3V6KVGA@

CC5
CC2

3 0.22U_0201_6.3V6KVGA@

5 0.22U_0201_6.3V6KVGA@

CC2

7 0.22U_0201_6.3V6KVGA@

CC2

CC2

9 0.22U_0201_6.3V6KVGA@

CC3

1 0.22U_0201_6.3V6KVGA@

CC33 0.22U_0201_6.3V6KVGA@

5 0.22U_0201_6.3V6KVGA@

CC3

7 0.22U_0201_6.3V6KVGA@

CC3
CC3

9 0.22U_0201_6.3V6KVGA@

CC4

1 0.22U_0201_6.3V6KVGA@

CC4

3 0.22U_0201_6.3V6KVGA@

5 0.22U_0201_6.3V6KVGA@

CC4

7 0.22U_0201_6.3V6KVGA@

CC4

CC4

9 0.22U_0201_6.3V6KVGA@

CC5

1 0.22U_0201_6.3V6KVGA@

3 0.22U_0201_6.3V6KVGA@

CC5

5 0.22U_0201_6.3V6KVGA@

CC5

7 0.22U_0201_6.3V6KVGA@

CC5
CC5

9 0.22U_0201_6.3V6KVGA@

CC6

1 0.22U_0201_6.3V6KVGA@

CC6

3 0.22U_0201_6.3V6KVGA@

+1.

CA

D note:
Trace width =12 mi ls,Sp acing =15mi l,Max
length =400mils

1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

0VS_VCCIO

I_CRX_PTX_P0<16>

DM
DM

I_CRX_PTX_N0<16>

DM

I_CRX_PTX_P1<16>
I_CRX_PTX_N1<16>

DM

I_CRX_PTX_P2<16>

DM
DM

I_CRX_PTX_N2<16>

DM

I_CRX_PTX_P3<16>

DM

I_CRX_PTX_N3<16>

0.22U_0201_6.3V6KVGA@

0.22U_0201_6.3V6KVGA@

0.22U_0201_6.3V6KVGA@

0.22U_0201_6.3V6KVGA@

1 2

0 24.9_0402_1%

RC2

PEG
PEG

_GTX_C_HRX_N15

PEG

_GTX_C_HRX_P14
_GTX_C_HRX_N14

PEG

_GTX_C_HRX_P13

PEG

_GTX_C_HRX_N13

PEG

PEG

_GTX_C_HRX_P12

PEG

_GTX_C_HRX_N12

_GTX_C_HRX_P11

PEG

_GTX_C_HRX_N11

PEG

PEG

_GTX_C_HRX_P10

PEG

_GTX_C_HRX_N10

PEG

_GTX_C_HRX_P9
_GTX_C_HRX_N9

PEG

_GTX_C_HRX_P8

PEG
PEG

_GTX_C_HRX_N8

PEG

_GTX_C_HRX_P7

PEG

_GTX_C_HRX_N7

_GTX_C_HRX_P6

PEG

_GTX_C_HRX_N6

PEG

PEG

_GTX_C_HRX_P5

PEG

_GTX_C_HRX_N5

PEG

_GTX_C_HRX_P4
_GTX_C_HRX_N4

PEG

_GTX_C_HRX_P3

PEG
PEG

_GTX_C_HRX_N3

PEG

_GTX_C_HRX_P2

PEG

_GTX_C_HRX_N2

_GTX_C_HRX_P1

PEG

_GTX_C_HRX_N1

PEG

PEG

_GTX_C_HRX_P0

PEG

_GTX_C_HRX_N0

PEG

DM

I_CRX_PTX_P0

DM

I_CRX_PTX_N0

I_CRX_PTX_P1

DM

I_CRX_PTX_N1

DM

DM

I_CRX_PTX_P2

DM

I_CRX_PTX_N2

DMI_CRX_PTX_P3

I_CRX_PTX_N3

DM

_RCOMP

E25

PEG

D25

PEG

E24

PEG

F24

PEG

E23

PEG

D23

PEG_RXN[2]

E22

PEG

F22

PEG

E21

PEG

D21

PEG

E20

PEG

F20

PEG

E19

PEG

D19

PEG

E18

PEG

F18

PEG

D17

PEG

E17

PEG

F16

PEG

E16

PEG

D15

PEG

E15

PEG

F14

PEG

E14

PEG

D13

PEG

E13

PEG

F12

PEG

E12

PEG

D11

PEG

E11

PEG

F10

PEG_RXP[15]

E10

PEG

G2

PEG

D8

DM

E8

DM

E6

DM

F6

DM

D5

DM

E5

DM

J8

DM

J9

DMI_RXN[3]

SKL-H_BGA1440

@

UC1C

_RXP[0]
_RXN[0]

_RXP[1]
_RXN[1]

_RXP[2]

_RXP[3]
_RXN[3]

_RXP[4]
_RXN[4]

_RXP[5]
_RXN[5]

_RXP[6]
_RXN[6]

_RXP[7]
_RXN[7]

_RXP[8]
_RXN[8]

_RXP[9]
_RXN[9]

_RXP[10]
_RXN[10]

_RXP[11]
_RXN[11]

_RXP[12]
_RXN[12]

_RXP[13]
_RXN[13]

_RXP[14]
_RXN[14]

_RXN[15]

_RCOMP

I_RXP[0]
I_RXN[0]

I_RXP[1]
I_RXN[1]

I_RXP[2]
I_RXN[2]

I_RXP[3]

REV = 1

SKYL

AKE_HALO

BGA144 0

3 OF 14

_TXP[0]

PEG

_TXN[0]

PEG

PEG

_TXP[1]
_TXN[1]

PEG

PEG

_TXP[2]

PEG_TXN[2]

PEG

_TXP[3]

PEG

_TXN[3]

_TXP[4]

PEG
PEG

_TXN[4]

_TXP[5]

PEG

_TXN[5]

PEG

PEG

_TXP[6]
_TXN[6]

PEG

PEG

_TXP[7]

PEG

_TXN[7]

_TXP[8]

PEG
PEG

_TXN[8]

_TXP[9]

PEG
PEG

_TXN[9]

_TXP[10]

PEG

_TXN[10]

PEG

PEG

_TXP[11]
_TXN[11]

PEG

PEG

_TXP[12]

PEG

_TXN[12]

_TXP[13]

PEG
PEG

_TXN[13]

_TXP[14]

PEG
PEG

_TXN[14]

PEG_TXP[15]

_TXN[15]

PEG

I_TXP[0]

DM
DM

I_TXN[0]

I_TXP[1]

DM

I_TXN[1]

DM

DM

I_TXP[2]
I_TXN[2]

DM

DM

I_TXP[3]

DMI_TXN[3]

B25
A25

B24
C24

B23
A23

B22
C22

B21
A21

B20
C20

B19
A19

B18
C18

A17
B17

C16
B16

A15
B15

C14
B14

A13
B13

C12
B12

A11
B11

C10
B10

B8
A8

C6
B6

B5
A5

D4
B4

?

_HTX_GRX_P15

PEG
PEG

_HTX_GRX_N15

PEG

_HTX_GRX_P14
_HTX_GRX_N14

PEG

_HTX_GRX_P13

PEG

_HTX_GRX_N13

PEG

PEG

_HTX_GRX_P12

PEG

_HTX_GRX_N12

_HTX_GRX_P11

PEG

_HTX_GRX_N11

PEG

PEG

_HTX_GRX_P10

PEG

_HTX_GRX_N10

PEG

_HTX_GRX_P9
_HTX_GRX_N9

PEG

_HTX_GRX_P8

PEG
PEG

_HTX_GRX_N8

PEG

_HTX_GRX_P7

PEG

_HTX_GRX_N7

_HTX_GRX_P6

PEG

_HTX_GRX_N6

PEG

PEG

_HTX_GRX_P5

PEG

_HTX_GRX_N5

PEG

_HTX_GRX_P4
_HTX_GRX_N4

PEG

_HTX_GRX_P3

PEG
PEG

_HTX_GRX_N3

PEG

_HTX_GRX_P2

PEG

_HTX_GRX_N2

_HTX_GRX_P1

PEG

_HTX_GRX_N1

PEG

PEG

_HTX_GRX_P0

PEG

_HTX_GRX_N0

DM

I_CTX_PRX_P0

DM

I_CTX_PRX_N0

I_CTX_PRX_P1

DM

I_CTX_PRX_N1

DM

DM

I_CTX_PRX_P2

DM

I_CTX_PRX_N2

DMI_CTX_PRX_P3

I_CTX_PRX_N3

DM

22U_0201_6.3V6K VGA@
22U_0201_6.3V6K VGA@

22U_0201_6.3V6K VGA@
22U_0201_6.3V6K VGA@

22U_0201_6.3V6K VGA@

I_CTX_PRX_P0 <16>

DM
DM

I_CTX_PRX_N0 <16>

DM

I_CTX_PRX_P1 <16>
I_CTX_PRX_N1 <16>

DM

I_CTX_PRX_P2 <16>

DM
DM

I_CTX_PRX_N2 <16>

DM

I_CTX_PRX_P3 <16>

DM

I_CTX_PRX_N3 <16>

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

CC70.
CC90.

CC1
CC1

CC10.
CC20.

CC1
CC1

CC2
CC40.

CC2
CC2

CC2
CC2

CC3
CC3

CC340.22U_0201_6.3V6K VGA@
CC3

CC3
CC4

CC4
CC4

CC4
CC4

CC5
CC5

CC5
CC5

CC5
CC6

CC6
CC6

_HTX_C_GRX_P15 <23>

PEG

_HTX_C_GRX_N15 <23>

10.22U_0201_6.3V6K VGA@

30.22U_0201_6.3V6K VGA@

60.22U_0201_6.3V6K VGA@

80.22U_0201_6.3V6K VGA@

00.22U_0201_6.3V6K VGA@

20.22U_0201_6.3V6K VGA@

40.22U_0201_6.3V6K VGA@

60.22U_0201_6.3V6K VGA@

80.22U_0201_6.3V6K VGA@

00.22U_0201_6.3V6K VGA@

20.22U_0201_6.3V6K VGA@

60.22U_0201_6.3V6K VGA@

80.22U_0201_6.3V6K VGA@

00.22U_0201_6.3V6K VGA@

20.22U_0201_6.3V6K VGA@

40.22U_0201_6.3V6K VGA@

60.22U_0201_6.3V6K VGA@

80.22U_0201_6.3V6K VGA@

00.22U_0201_6.3V6K VGA@

20.22U_0201_6.3V6K VGA@

40.22U_0201_6.3V6K VGA@

60.22U_0201_6.3V6K VGA@

80.22U_0201_6.3V6K VGA@

00.22U_0201_6.3V6K VGA@

20.22U_0201_6.3V6K VGA@

40.22U_0201_6.3V6K VGA@

PEG

PEG

_HTX_C_GRX_P14 <23>

PEG

_HTX_C_GRX_N14 <23>

_HTX_C_GRX_P13 <23>

PEG

_HTX_C_GRX_N13 <23>

PEG

PEG

_HTX_C_GRX_P12 <23>

PEG

_HTX_C_GRX_N12 <23>

PEG

_HTX_C_GRX_P11 <23>
_HTX_C_GRX_N11 <23>

PEG

_HTX_C_GRX_P10 <23>

PEG
PEG

_HTX_C_GRX_N10 <23>

PEG

_HTX_C_GRX_P9 <23>

PEG

_HTX_C_GRX_N9 <23>

_HTX_C_GRX_P8 <23>

PEG

_HTX_C_GRX_N8 <23>

PEG

PEG

_HTX_C_GRX_P7 <23>

PEG

_HTX_C_GRX_N7 <23>

PEG

_HTX_C_GRX_P6 <23>
_HTX_C_GRX_N6 <23>

PEG

_HTX_C_GRX_P5 <23>

PEG
PEG

_HTX_C_GRX_N5 <23>

PEG

_HTX_C_GRX_P4 <23>

PEG

_HTX_C_GRX_N4 <23>

_HTX_C_GRX_P3 <23>

PEG

_HTX_C_GRX_N3 <23>

PEG

PEG

_HTX_C_GRX_P2 <23>

PEG

_HTX_C_GRX_N2 <23>

PEG_HTX_C_GRX_P1 <23>

_HTX_C_GRX_N1 <23>

PEG

_HTX_C_GRX_P0 <23>

PEG

_HTX_C_GRX_N0 <23>

PEG

4 4

Security Clas sification

Security Clas sification

Security Clas sification

11/03 2017/01/10

11/03 2017/01/10

11/03 2017/01/10

2016/

2016/

Issued Date

Issued Date

Issued Date

TH

TH

TH

IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL

IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL

IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2016/

C

mpal Secret Data

mpal Secret Data

mpal Secret Data

Co

Co

Co

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

tle

tle

tle

Ti

Ti

Ti

L-H(3/9) PEG,DMI

L-H(3/9) PEG,DMI

L-H(3/9) PEG,DMI

SK

SK

SK

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

stom

stom

stom

Cu

Cu

Cu

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

Date: Sheet

Date: Sheet

D

Date: Sheet

864Tuesday, April 11, 2017

864Tuesday, April 11, 2017

864Tuesday, April 11, 2017

of

of

E

of

1A

1A

1A

A

Alert / Data

SVID

1 1

Place

the PU resistors close to CPU

1 2

RC3

0V_VCCST

+1.

CPU_

0V_VCCST

+1.

From

2 2

From

+1.

3 3

1.0

Modify

4 56_0402_5%

SVID_ALERT#

CPU_

1 2

6 220_0402_5%

RC3

1 2

RC3

8 100_0402_1%

SVID_DAT

EC(open-drain)

RC3

1K_0402_5%

H_

PROCHOT#<39,46>

+1.

RC2

1K_0402_5%

EC OD output

VCCST_PG_R<39,43>

EC_

PM_

DOWN_R<17>

0V_VCCST

1 2

8 1K_0402_5%

RC2

5 .1U_0402_16V7K

CH6

XEMC@

1 2

CH1 .1U_0402_16V7K

EMC@

1 2

CH2 1000P

XEMC@

1 2

CH3

CH6

ESD

.1U_0402_16V7K

EMC@

1 2

1000P

7

Reserve ,pleace close to cpu

+1.

0VS_VCCSTG

12

1

0V_VCCST

12

7

1 2

XEMC@

1 2

_0402_50V7K

_0402_50V7K

499_0402_1%

1 2

RC2

60.4_0402_1%

1 2

20_0402_1%

RC3

@

1K_0402_5%

RC3

3

9

RC3

0

2

ERMTRIP#

TH

H_

CPUPWRGD

PROCHOT#_R

H_

TH

ERMTRIP#

EC_

VCCST_PG

VR)

(To

CPU_

SVID_ALERT#_R <52>

(To VR)

CPU_

SVID_DAT <52>

H_

PROCHOT#_R

VCCST_PG

EC_

PM_

DOWN

12

H_

PECI

B

CPU_

CPU_

SVID_ALERT#
SVID_CLK

CPU_

SVID_DAT

CPU_

PROCHOT#_R

H_

DDR_

PG_CTRL

VCCST_PG

EC_

H_

CPUPWRGD

PL

TRST_CPU#

H_

PM_SYNC

PM_DOWN

PECI

H_
TH

ERMTRIP#

H_
SKL

PAD

BCLK

CPU_

BCLK#

PCIBCLK

CPU_

PCIBCLK#

CPU_

CPU_

24M

CPU_

24M#

SKTOCC#_R

_CNL_N

H_

CATERR#

CPU_

BCLK<19>

CPU_

BCLK#<19>

PCIBCLK<19>

CPU_

PCIBCLK#<19>

CPU_

24M<19>

CPU_
CPU_

24M#<19>

CPU_

SVID_CLK<52>

CPUPWRGD<18>

H_
PL

TRST_CPU#<17>

H_

PM_SYNC<17>

H_

PECI<17,39>

ERMTRIP#<17>

TH

1 2

RC2

SKTOCC#<18>

H_

1 0_0402_5%@

@

0_0402_5%

FLOAT FOR SKL
GND FOR CNL

RC2

@

2

T3

1 2

C

UC1E

B31

BC

LKP

A32

LKN

BC

D35

PC

I_BCLKP

C36

I_BCLKN

PC

E31

CL

K24P

D31

CL

K24N

BH31

DALERT#

VI

BH32

DSCK

VI

BH29

VI

DSOUT

BR30

PR

OCHOT#

BT13

VTT_CNTL

DDR_

H13

VC

CST_PWRGD

BT31

OCPWRGD

PR

BP35

SET#

RE

BM34

PM

_SYNC

BP31

PM_DOWN

BT34

I

PEC

J31

TH

ERMTRIP#

BR33

OCC#

SKT

BN1

OC_SELECT#

PR

BM30

CA

TERR#

SKL-H_BGA1440

REV = 1 ?

@

SKYL

BGA144 0

AKE_HALO

5

OF 14

PR

PR

PROC_TMS

PR

PR

OC_TRST#

OC_PREQ#

PR

OC_PRDY#

PR

G_RCOMP

CF

CF

G[0]
G[1]

CF
CF

G[2]

CF

G[3]
G[4]

CF

G[5]

CF
CF

G[6]

CF

G[7]
G[8]

CF

G[9]

CF

CF

G[10]

CFG[11]

G[12]

CF
CF

G[13]

CF

G[14]
G[15]

CF

CF

G[17]

CF

G[16]
G[19]

CF

G[18]

CF

BPM
BPM
BPM
BPM

OC_TDO

OC_TDI

OC_TCK

D

CF

BN25

G0

CF

BN27
BN26

CF

BN28
BR20

CF

BM20

CF

BT20
BP20

CF

BR23
BR22
BT23
BT22
BM19
BR19
BP19
BT19

BN23
BP23
BP22
BN22

BR27

#[0]

BT27

#[1]

BM31

#[2]

BT30

#[3]

CPU_

BT28

CPU_

BL32

CPU_XDP_TMS

BP28

CPU_

BR28

BP30
BL30
BP27

G_RCOMP

CF

BT25

G2

G4
G5

G7

XDP_TDO
XDP_TDI

XDP_TCK0

@

T1PAD

@

T2PAD

12

RC2

49.9_0402_1%

CPU_
CPU_
CPU_
CPU_

4

XDP_TDO <6,18>
XDP_TDI <6,18>
XDP_TMS <6,18>
XDP_TCK0 <6,18>

G4

G5

CF

CF

G2

PCIE
port
assign

1 x 16
1 x 16

reverse

2 x 8
2 x 8

reverse
1 x 8
+ 2 x 4
1x8+2x4
reverse

RC2

RC2

RC2

*

E

1 2

3 1K_0402_1%

1 2

5 1K_0402_1%@

1 2

6 1K_0402_1%

Config.

Signals

CFG[2]CFG[5]CFG[6]

111

11

11

1

0

00

00

0

1

000

Reference SKL EDS 0.85 Table 6-8
CFG

signals internal PH default value = 1

cription

D

DR_VTT_CNTL to DDR
VTT supplied ramped
<35uS
(tCPU18)

DDR_

PG_CTRL

1U_0201_10V6K

0.

NC1VC

2

A

3

D

GN

UP1G07GW_TSSOP5

74A

2V_VDDQ

+1.

+3VS

12

5

UC2

CC6

5

C

4

Y

12

RC3

5

220K_0402_5%

7

RC3
2M_0402_5%@

1 2

PG_CTRL <48>

SM_

CF

G[0]

CFG[4]

CFG[7]

Stall
lock until de-asserted
— 1 = (Default) Normal Operation;

*

No stall.
— 0 = Stall.

Enable eDP
— 1 = Disabled.
— 0 = Enabled.

*

PEG
— 1 = (default) PEG Train immediately

*

following RESET# de assertion.
— 0 = PEG Wait for BIOS for training

CFG[1]

CFG[3]

Reserved configuration lane.

CFG[8:19]

Des

reset sequence after PCU PLL

Training:

4 4

Security Clas sification

Security Clas sification

Security Clas sification

2016/11/03 2017/01/10

2016/11/03 2017/01/10

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2016/11/03 2017/01/10

C

mpal Secret Data

mpal Secret Data

mpal Secret Data

Co

Co

Co

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

tle

tle

tle

Ti

Ti

Ti

L-H(4/9)CLK,GPIO

L-H(4/9)CLK,GPIO

L-H(4/9)CLK,GPIO

SK

SK

SK

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

stom

stom

stom

Cu

Cu

Cu

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

Date: Sheet

Date: Sheet

D

Date: Sheet

964Tuesday, April 11, 2017

964Tuesday, April 11, 2017

964Tuesday, April 11, 2017

of

of

E

of

1A

1A

1A

A

B

C

D

E

RE

+VCC_CO

1 1

2 2

3 3

4 4

AA13
AA31
AA32
AA33
AA34
AA35
AA36
AA37
AA38
AB29
AB30
AB31
AB32
AB35
AB36
AB37
AB38
AC13
AC14
AC29
AC30
AC31
AC32
AC33
AC34
AC35
AC36
AD13
AD14
AD31
AD32
AD33
AD34
AD35
AD36
AD37
AD38
AE13
AE14
AE30
AE31
AE32
AE35
AE36
AE37
AE38

AF35
AF36
AF37
AF38

K13
K14

N13
N14
N30
N31
N32
N35
N36
N37
N38
P13

L13

SKYLAKE_HALO

G

UC1

A1440

BG

VC

C
C

VC
VC

C

VC

C
C

VC

C

VC
VC

C

VC

C
C

VC

C

VC
VC

C

VCC

C

VC
VC

C

VC

C
C

VC

C

VC
VC

C

VC

C
C

VC

C

VC
VC

C

VC

C
C

VC

C

VC
VC

C

VC

C
C

VC

C

VC
VC

C

VCC

C

VC
VC

C

VC

C
C

VC

C

VC
VC

C

VC

C
C

VC

C

VC
VC

C

VC

C
C

VC

C

VC
VC

C

VC

C
C

VC
VC

C

VC

C

VCC

C

VC

C

VC
VC

C
C

VC

C

VC
VC

C

VC

C
C

VC

C

VC
VC

C

VC

C
C

VC

C

VC

7 OF 14

SKL

-H_BGA1440

REV = 1 ?

@

VC

C_SENSE

VSS_

VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VCC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VCC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VCC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC

SENSE

C
C
C
C
C
C
C
C
C
C
C

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

C
C
C
C
C
C
C
C
C
C
C
C
C

+VCC_CO

V32
V33
V34
V35
V36
V37
V38
W13
W14
W29
W30
W31
W32
W35
W36
W37
W38
Y29
Y30
Y31
Y32
Y33
Y34
Y35
Y36
L14
P29
P30
P31
P32
P33
P34
P35
P36
R13
R31
R32
R33
R34
R35
R36
R37
R38
T29
T30
T31
T32
T35
T36
T37
T38
U29
U30
U31
U32
U33
U34
U35
U36
V13
V14
V31
P14

AG37
AG38

PH/PL
10/07 Dan

RE

Trace

Length < 25 mils

VCCSENSE

VSSSENSE

on pwr side

H-4+2/68A H-4+2/55A

+VCC_G

<52>
<52>

T

SKYLAKE_HALO

H

UC1

A1440

BG34
BG35
BG36
BH33
BH34
BH35
BH36
BH37
BH38

BJ37
BJ38
BL36

BL37
BM36
BM37
BN36
BN37
BN38
BP37
BP38
BR37

BT37
BE38

BF13

BF14

BF29

BF30

BF31

BF32

BF35

BF36

BF37

BF38
BG29
BG30
BG31
BG32
BG33
BC36
BC37
BC38
BD13
BD14
BD29
BD30
BD31
BD32
BD33
BD34
BD35
BD36
BE31
BE32
BE37

BG

VC

CGT

VC

CGT
CGT

VC
VC

CGT

VC

CGT
CGT

VC

CGT

VC
VC

CGT

VC

CGT
CGT

VC

CGT

VC
VC

CGT

VCCGT

CGT

VC
VC

CGT

VC

CGT
CGT

VC

CGT

VC
VC

CGT

VC

CGT
CGT

VC

CGT

VC
VC

CGT

VC

CGT
CGT

VC

CGT

VC
VC

CGT

VC

CGT
CGT

VC

CGT

VC
VC

CGT

VCCGT

CGT

VC
VC

CGT

VC

CGT
CGT

VC

CGT

VC
VC

CGT

VC

CGT
CGT

VC

CGT

VC
VC

CGT

VC

CGT
CGT

VC

CGT

VC
VC

CGT

VC

CGT
CGT

VC
VC

CGT

VC

CGT

VCCGT

CGT

VC

CGT

VC
VC

CGT

8 OF 14

-H_BGA1440

SKL

@

RE

V = 1

VC

CGT

VC

CGT
CGT

VC
VC

CGT

VC

CGT
CGT

VC

CGT

VC
VC

CGT

VC

CGT
CGT

VC

CGT

VC
VC

CGT

VCCGT

CGT

VC
VC

CGT

VC

CGT
CGT

VC

CGT

VC
VC

CGT

VC

CGT
CGT

VC

CGT

VC
VC

CGT

VC

CGT
CGT

VC

CGT

VC
VC

CGT

VC

CGT
CGT

VC

CGT

VC
VC

CGT

VCCGT

CGT

VC
VC

CGT

VC

CGT
CGT

VC

CGT

VC
VC

CGT

VC

CGT
CGT

VC

CGT

VC
VC

CGT

VC

CGT
CGT

VC

CGT

VC
VC

CGT

VC

CGT
CGT

VC
VC

CGT

VC

CGT

VCCGT

CGT

VC

CGT

VC
VC

CGT

AV29
AV30
AV31
AV32
AV33
AV34
AV35
AV36
AW14
AW31
AW32
AW33
AW34
AW35
AW36
AW37
AW38
AY29
AY30
AY31
AY32
AY35
AY36
AY37
AY38
BA13
BA14
BA29
BA30
BA31
BA32
BA33
BA34
BA35
BA36
BB13
BB14
BB31
BB32
BB33
BB34
BB35
BB36
BB37
BB38
BC29
BC30
BC31
BC32
BC35
BE33
BE34
BE35
BE36

?

+VCC_G

T

EDS:Rail is unconnected for Processors without GT3/4.

T

+VCC_G

AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35

AJ36
AK31
AK32
AK33
AK34
AK35
AK36
AK37
AK38

AL13

AL29

AL30

AL31

AL32

AL35

AL36

AL37

AL38
AM13
AM14
AM29
AM30
AM31
AM32
AM33
AM34
AM35
AM36
AN13
AN14
AN31
AN32
AN33
AN34
AN35
AN36
AN37
AN38
AP13
AP14
AP29
AP30
AP31
AP32
AP35
AP36
AP37
AP38
AR29
AR30
AR31
AR32
AR33
AR34
AR35
AR36

AT14

AT31

AT32

AT33

AT34

AT35

AT36

AT37

AT38
AU14
AU29
AU30
AU31
AU32
AU35
AU36
AU37
AU38

UC1

VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VCCGT
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VCCGT
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VCCGT
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VCCGT
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC

SKL

N

CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT

CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT

CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT

CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT

CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT
CGT

-H_BGA1440

SKYL

AKE_HALO

BGA144 0

@

14 OF 14

CGT_SENSE

VC

TX_SENSE

VSSG

VSSG

T_SENSE

VC

CGTX_SENSE

VC

CGTX
CGTX

VC
VC

CGTX

VC

CGTX
CGTX

VC

CGTX

VC
VC

CGTX

VC

CGTX
CGTX

VC

CGTX

VC
VC

CGTX

VCCGTX

CGTX

VC
VC

CGTX

VC

CGTX
CGTX

VC

CGTX

VC
VC

CGTX

VC

CGTX
CGTX

VC

CGTX

VC
VC

CGTX

?

AF29
AF30
AF31
AF32
AF33
AF34
AG13
AG14
AG31
AG32
AG33
AG34
AG35
AG36
AH13
AH14
AH29
AH30
AH31
AH32
AJ13
AJ14

VCCG

AH38
AH35
AH37
AH36

VSSG

T_SENSE

T_SENSE

Trace Length < 25 mils

VCCG

T_SENSE <52>

VSSG

T_SENSE <52>

Security Clas sification

Security Clas sification

Security Clas sification

2016/11/03 2017/01/10

2016/11/03 2017/01/10

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2016/11/03 2017/01/10

C

mpal Secret Data

mpal Secret Data

mpal Secret Data

Co

Co

Co

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

tle

tle

tle

Ti

Ti

Ti

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

stom

stom

stom

Cu

Cu

Cu

Date: Sheet

Date: Sheet

D

Date: Sheet

L-H(5/9)Power,SVID

L-H(5/9)Power,SVID

L-H(5/9)Power,SVID

SK

SK

SK

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

E

1A

1A

1A

10 64Tuesday, April 11, 2017

10 64Tuesday, April 11, 2017

10 64Tuesday, April 11, 2017

of

of

of

A

B

C

D

E

(1

_CLK

+VDDQ

BSC

10U_0603_6.3V6M

1

2

.35V)

+VCCSF

Place at Back Side

+1.

0V_VCCST

1

2

Side

CC7

0

+VCCSF

R_OC_1

1U_0402_6.3V6K

1

CC7

1

2

CC6

7

1U_0402_6.3V6K

Place at Back Side

R_OC_2

1U_0402_6.3V6K

1

2

CC72

2V_VDDQ_CPU

+1.

+1.

C1

12

@

C2

12

@

130mA

VCCSA_

SENSE <52>

VSSSA_

SENSE <52>

O_SENSE <51>

VCCI

O_SENSE <51>

VSSI

2V_VDDQ

For

Power consumption

VCCSA_
VSSSA_

VCCI
VSSI

SENSE
SENSE

O_SENSE
O_SENSE

Measure ment

JUMP_43X118

JUMP_43X118

_CLK

+VDDQ

+VCCSF

R_OC_1

+VCCSF

R_OC_2

0V_VCCST

+1.

+1.

0VS_VCCSTG

+1.0V_VCCSFR

JP

JP

VC

CPLL_OC
CPLL_OC

VC

VC

CSA_SENSE

VSSSA_

CIO_SENSE

VC

VSSI

O_SENSE

DDR4/2.8A

VD

DQ

VD

DQ
DQ

VD

DQ

VD
VD

DQ

VD

DQ
DQ

VD
VD

DQ

VD

DQ
DQ

VD

DQ

VD
VD

DQ

VD

DQ
DQ

VD

DQ

VD
VD

DQ

VDDQ

DQ

VD
VD

DQ

VD

DQ
DQ

VD

DQ

VD
VD

DQ

VD

DQ

DQC

VD

VC

CST

CSTG

VC

VCCSTG

VC

CPLL

VC

CPLL

SENSE

AA6
AE12
AF5
AF6
AG5
AG9
AJ12
AL11
AP6
AP7
AR12
AR6
AT12
AW6
AY6
J5
J6
K12
K6
L12
L6
R6
T6
W6

Y12

BH13
G11

H30

H29

G30

H28
J28

M38
M37

H14
J14

20mA

150mA

SKYLAKE_HALO

K29
K30
K31
K32
K33
K34
K35

M29
M30
M31
M32
M33
M34
M35
M36

AG12

G15
G17
G19
G21
H15
H16
H17
H19
H20
H21
H26
H27

UC1I

J30

VC
VC
VC
VC
VC
VC
VC
VC

L31

VC

L32

VC

L35

VC

L36

VC

L37

VC

L38

VC
VC
VC
VCCSA
VC
VC
VC
VC
VC

VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VCCIO
VC

J15

VC

J16

VC

J17

VC

J19

VC

J20

VC

J21

VC

J26

VC

J27

VC

CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA

CSA
CSA
CSA
CSA
CSA

CIO
CIO
CIO
CIO
CIO
CIO
CIO
CIO
CIO
CIO
CIO

CIO
CIO
CIO
CIO
CIO
CIO
CIO
CIO
CIO

A1440

BG

RVP11 47u*1,10u*7,1u*3
CAP place on PWR side.

1 1

RVP

11

PWR NEED PROVIDE

0.95V FOR VCCIO

+VCC_SA

H-4+2/11.1A

0VS_VCCIO

+1.

H /5.5A

2 2

2V_VDDQ_CPU

+1.

RC4

0

1 2

@

0_0603_5%

Place at Back Side

+1.

2V_VDDQ

1 2

@

RC4

1 0_0402_5%

1 2

@

RC4

2 0_0402_5%

NOTE:
VCCPLL_OC is allowed to be turned off
during S3 & DS3 if it is not powered
directly from VDDQ

+1.

0VS_VCCSTG

(1.0VS)

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

2

CC6

8

CC6

9

2

9 OF 14

SKL

-H_BGA1440

REV = 1

@

3 3

2V_VDDQ_CPU

+1.

10U_0603_6.3V6M

CC7

4

10U_0603_6.3V6M

1

1

CC7

5

2

2

10U_0603_6.3V6M

1

1

CC7

3

2

2

4 4

A

CPU_CORE/VCCGT/VCCSA

10U_0603_6.3V6M

10U_0603_6.3V6M

CC7

6

+1.2V_VDDQ_CPU
22UF/6.3V/0603 * 4
update CRB cap QTY

1

1

CC7

7

2

2

B

10U_0603_6.3V6M

10U_0603_6.3V6M

1

CC7

CC7

9

8

2

: 10UF/6.3V/0603 *10

decoupling capacitor place to PWR side

?

0VS_VCCIO

+1.

22U_0603_6.3V6M

10U_0603_6.3V6M

CC8

1

10U_0603_6.3V6M

1

CC8

2

2

1

2

10U_0603_6.3V6M

1

1

CC8

0

2

2

CC8

3

22U_0603_6.3V6M

CC8

1

1

4

2

2

Place at Back Side

Security Clas sification

Security Clas sification

Security Clas sification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/11/03 2017/01/10

2016/11/03 2017/01/10

2016/11/03 2017/01/10

C

22U_0603_6.3V6M

22U_0603_6.3V6M

CC8

CC8

1

6

5

2

mpal Secret Data

mpal Secret Data

mpal Secret Data

Co

Co

Co

Deciphered Date

Deciphered Date

Deciphered Date

10U_0603_6.3V6M

1

CC91

2

Place at Back Side

+1.

0V_VCCST

1 2

9 0_0402_5%@

RC3

CC8

9

22U_0603_6.3V6M

CC9

1

0

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

CC92

2

2

+1.

0V_VCCSFR

1 2

6 1U_0402_6.3V6K

CC6

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

CC8

CC8

1

1

7

2

2

CC9

1

8

3

2

Follow ORB 3/20

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

tle

tle

tle

Ti

Ti

Ti

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

stom

stom

stom

Cu

Cu

Cu

Date: Sheet

Date: Sheet

D

Date: Sheet

L-H(6/9)POWER

L-H(6/9)POWER

L-H(6/9)POWER

SK

SK

SK

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

E

1A

1A

1A

11 64Tuesday, April 11, 2017

11 64Tuesday, April 11, 2017

11 64Tuesday, April 11, 2017

of

of

of

A

SKYLAKE_HALO

UC1

J

A1440

VC

COPC

VC

COPC
COPC

VC

COPC

VC
VC

COPC

VC

COPC
COPC

VC

COPC

VC
VC

COPC

VC

COPC
COPC

VC
VC

COPC

VC

COPC
COPC

VC

RS

VD

RS

VD
VD

RS

VD

RS
RS

VD

RSVD

VD

RS
RS

VD

RS

VD
VD

RS

VD

RS
RS

VD

RS

VD

VC

COPC_SENSE

VSSO

PC_SENSE

VD

RS
RS

VD

CEOPIO

VC
VC

CEOPIO

VCCEOPIO

RS

VD

RS

VD
VD

RS

VC

CEOPIO_SENSE

PIO_SENSE

VSSEO

RS

VD

RS

VD

VC

C_OPC_1P8

VC

C_OPC_1P8

RS

VD

RS

VD

M#

ZV
MS

M#

M2#

ZV
MS

M2#

C_RCOMP

OP

CE_RCOMP

OP
OP

CE_RCOMP2

-H_BGA1440

REV = 1

BG

BJ17
BJ19

BJ20
BK17
BK19
BK20

RAM

1 1

ED

CRB
EDRAM

2 2

3 3

T4 @
T5 @
T6 @

OP

C_RCOMP

OP

CE_RCOMP

OP

CE_RCOMP2

BL16

BL17

BL18

BL19

BL20

BL21
BM17
BN17

BJ23

BJ26

BJ27
BK23
BK26
BK27

BL23

BL24

BL25

BL26

BL27

BL28
BM24

BL15
BM16

BL22
BM22

BP15
BR15

BT15

BP16
BR16

BT16

BN15
BM15

BP17
BN16

BM14

BL14

BJ35

BJ36

AT13

AW13

AU13
AY13

BT29
BR25
BP25

SKL

@

10 OF 14

B

AKE_HALO

SKYL

UC1

F

BGA144 0

8

Y3

VSS

7

Y3

VSS

Y1

4

VSS

3

Y1

VSS

1

Y1

VSS

0

Y1

VSS

Y9

VSS

Y8

VSS

Y7

VSS

4

W3

VSS

W3

3

VSS

2

W1

VSS

W5

VSS

W4

VSS

W3

VSS

W2

VSS

W1

VSS

V3

0

VSS

9

V2

VSS

2

V1

VSS

V6

VSS

U38

VSS

7

U3

VSS

U6

VSS

T3

4

VSS

3

T3

VSS

4

T1

VSS

3

T1

VSS

T1

2

VSS

1

T1

VSS

0

T1

VSS

T9

VSS

T8

VSS

T7

VSS

T5

VSS

T4

VSS

T3

VSS

T2

VSS

T1

VSS

0

R3

VSS

R29

VSS

2

R1

VSS

8

P3

VSS

P3

7

VSS

2

P1

VSS

P6

VSS

4

N3

VSS

N3

3

VSS

2

N1

VSS

1

N1

VSS

0

N1

VSS

N9

VSS

N8

VSS

N7

VSS

N6

VSS

N5

VSS

N4

VSS

N3

VSS

N2

VSS

N1

VSS

4

M1

VSS

3

M1

VSS

M1

2

VSS

M6

VSS

L34

VSS

L33

VSS

L30

VSS

L29

VSS

8

K3

VSS

1

K1

VSS

K1

0

VSS

K9

VSS

K8

VSS

K7

VSS

?

K5

VSS

K4

VSS

K3

VSS

K2

VSS

6 OF 14

SKL

-H_BGA1440

V = 1

@

NCT

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

FVSS

C

SKYL

UC1

M

AKE_HALO

BGA144 0

VSS
VSS
VSS
VSS

8

VSS

7

VSS

2

VSS

1

VSS

0

VSS
VSS
VSS
VSS
VSS

B9

VSS

4

VSS

3

VSS

4

VSS

2

VSS

30

VSS

29

VSS

12

VSS
VSS

4

VSS

3

VSS

2

VSS

1

VSS

8

VSS

7

VSS

34

VSS

33

VSS

12

VSS

11

VSS

10

VSS

9

VSS

8

VSS

7

VSS

6

VSS

30

VSS

29

VSS

6

VSS
VSS

37

VSS

14

VSS

13

VSS

5

VSS

4

VSS

3

VSS

2

VSS

1

VSS

4

VSS

3

VSS

2

VSS

1

VSS

0

VSS
VSS
VSS

30

VSS

29

VSS

12

VSS
VSS

5

VSS

38

VSS

37

VSS

12

VSS

5

VSS

4

VSS

3

VSS

2

VSS

1

VSS

34

VSS

33

VSS

14

VSS

12

VSS

10

VSS

9

VSS

8

VSS

7

VSS

4

VSS

SKL

@

-H_BGA1440

REV = 1

13 OF 14

NCT
NCT
NCT
NCT
NCT

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

FVSS
FVSS
FVSS
FVSS
FVSS

AK3
AK2
AK4
AJ
AJ
AJ
AJ
AJ
AJ
AJ
AJ
AH
AH
AH
AH
AG
AG
AG
AG
AG
AG
AG6
AF
AF
AF
AF
AF
AF
AF
AE3
AE3
AE6
AD
AD
AD
AD
AD
AD
AD
AD
AD6
AC
AC
AC
AC
AC
AC
AC
AC
AC
AB3
AB3
AB6
AA3
AA2
AA1
A3
A2
A2
A24
A2
A2
A1
A1
A1
A1
A1
A9
A6

B37
B3
A34
A4
A3

?

BA3
BA3
BA1
BA1
BA1

AY3
AY3
AY1

AY1
AW
AW
AW

AV3

AV3

AU

AU

AU

AU

AU

AR38

AR

AR

AR

AP3

AP3

AP1

AP1

AP1

AN

AN

AN

AM

AM

AM

AW5
AW
AW
AW
AW

AT
AT

AM
AM
AM
AM

AM
AL
AL
AL
AL
AL

BB4
BB3
BB2
BB1

BA9
BA8
BA7
BA6

AU
AU
AU
AU

AT

AR
AR
AR
AR
AR

AP9
AP8

AN6
AN

AL
AL
AL
AL

K1

6

J3
J3

3
2

J3

5

J2

2

J2
J1

8
0

J1
J7
J4
H3

5
2

H3

5

H2
H2

2
8

H1

2

H1

1

H1
G2

8
6

G2

4

G2

3

G2
G22

0

G2

8

G1
G1

6
4

G1

2

G1

0

G1
G9
G8
G6
G5
G4

6

F3

1

F3

9

F2
F2

7
5

F2

3

F2

1

F2
F19

7

F1

5

F1
F1

3
1

F1
F9
F8
F5
F4
F3
F2
E3

8
5

E3

4

E3
E9
E4

3

D3

0

D3

8

D2
D26

4

D2

2

D2
D2

0
8

D1

6

D1

4

D1
D1

2
0

D1
D9
D6
D3

7

C3

1

C3

9

C2
C2

7

D38

?RE

D

SKYL

AKE_HALO

UC1

L

0
9

38
37
6
5
4
3
2
1

34
33
12
6
30
29
11
10
8
7

14
13
12
4
3
2
1

4
3

30
29
12
11
10
9
8
7

38
37
12
6
5
4
3
2
1

4
3

0
9

2
0
8
6

2
0
8
6
4
2
0

C1
C1

BT
BT
BT
BT
BT
BT
BT

BT

BT
BR
BR
BR
BR
BR
BR
BR
BR
BR

BR7
BP3
BP3
BP2
BP2
BP2
BP2
BP1
BP1
BP1

BP7
BN
BN
BN
BN
BN
BN
BN
BN
BN18
BN
BN

BN

BN

BN

BN
BM
BM
BM
BM
BM
BM
BM
BM
BM

BM
BM
BM

BL29
BK2
BK1
BK1

BJ

BJ

BJ

BJ
BH
BH

BH
BH
BH
BH

BH
BG
BG
BG
BF
BF12
BE2

BE6

BD
BC
BC
BB1

7

3
C9
32
26
24
21
18
14
12

9

5
36
34
29
26
24
21
18
14
12

4

3

9

6

4

1

8

4

2

34
31
30
29
24
21
20
19

14
12

9

7

4

2
38
35
28
27
26
23
21
13
12

9

6

2

9

5

4
32
31
25
22
14
12

9

8

5

4

1
38
13
12
33

9

9
34
12

2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SKL-H_BGA1440

REV = 1

@

BGA144 0

12 OF 14

NCT
NCT
NCT
NCT
NCT
NCT

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

FVSS
FVSS
FVSS
FVSS
FVSS
FVSS

5

C2

3

C2
C2

1
9

C1

5

C1

1

C1
C8
C5

29

BM

25

BM
BM

18
11

BM

8

BM
BM

7
5

BM

3

BM

38

BL
BL

35
13

BL

6

BL

5

BK2
BK22

3

BK1
BK6
BJ

30
29

BJ

15

BJ

12

BJ
BH

11
10

BH

7

BH

6

BH
BH

3
2

BH

37

BG

14

BG
BG

6

34

BF

6

BF

0

BE3
BE5
BE4
BE3
BE2
BE1

38

BD

37

BD
BD

12
11

BD

10

BD

8

BD
BD

7
6

BD

33

BC
BC

14

BC

13
6

BC

0

BB3

9

BB2
BB6
BB5

C2
BT36
BT35
BT4
BT3
BR38

?

E

4 4

Security Clas sification

Security Clas sification

Security Clas sification

2016/11/03 2017/01/10

2016/11/03 2017/01/10

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2016/11/03 2017/01/10

C

mpal Secret Data

mpal Secret Data

mpal Secret Data

Co

Co

Co

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

tle

tle

tle

Ti

Ti

Ti

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

stom

stom

stom

Cu

Cu

Cu

Date: Sheet

Date: Sheet

D

Date: Sheet

L-H(8/9)GND

L-H(8/9)GND

L-H(8/9)GND

SK

SK

SK

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

E

1A

1A

1A

12 64Tuesday, April 11, 2017

12 64Tuesday, April 11, 2017

12 64Tuesday, April 11, 2017

of

of

of

A

1 1

K

UC1

D1

VD_TP

RS

E1

RS

VD_TP

E3

RS

VD_TP

E2

VD_TP

RS

BR1

RS

VD_TP

BT2

RS

VD_TP

BN35

VD

RS

J24

RS

2 2

C_TRIGIN_R

C_TRIGIN_R<22>

PRO

C_TRIGOUT_R<22>

PRO

3 3

1 2

RC4

30_0402_1%

4

PRO
PRO

C_TRIGOUT

BN33

BL34

AE29
AA14

BR35
BR31
BH30

H24

N29
R14

A36
A37

H23
J23

F30
E30

B30
C30

G3

J3

VD
VD

RS

VD

RS
RS

VD

VD

RS
RS

VD

RS

VD
VD

RS

RS

VD

RS

VD

OC_TRIGIN

PR
PR

OC_TRIGOUT

VD

RS

VD

RS

RS

VD
VD

RS

RS

VD

RSVD

VD

RS
RS

VD

RS

VD

SKL

-H_BGA1440

@

SKYLAKE_HALO

A1440

BG

B

11 OF 14

Rev_0.5

VD_TP

RS
RS

VD_TP

VD_TP

RS

VD_TP

RS

VD_TP

RS

VD_TP

RS

VD_TP

RS
RS

VD_TP

VD_TP

RS

VD_TP

RS

RS
RS

VSS

RS
RS

RS
RS

VSS

RS
RS
RSVD

NCT
NCT
NCT
NCT
NCT
NCT

C

+1

+5VALW

8

CC9
1U_0402_6.3V6K

SON<39,43,48,50>

1.0 Modify

RC4

3

0_0402_5%

12

@

1U_0201_10V6K

0.

0_0402_5%

SUSP#

1.0 Modify

CC9

EN_

@

+1

9

RC4

@

3

BM33
BL33

BJ14
BJ13

BK28

VD

BJ28

VD

18

BJ

BJ16
BK16

BK24
BJ24

BK21

VD

BJ21

VD

BT17

VD

BR17

VD

8

BK1

BJ34
BJ33

G13

VD

AJ8

VD

BL31

NCT

F_0

B2

F

NCT

F_1

B38

F
F
F
F
F

F_2

NCT

BP1

F_3

NCT

BR2

F_4

NCT

C1

F_5

NCT

C38

?REV = 1

T7

PAD@

T8

PAD@

T9

PAD@

T10

PAD@
PAD@

T11

PAD@

T12

43,46,48,50,51>

SY

SUSP#<39,

D

.0VALW TO +1.0V_VCCST

+1.0VALW

1

CC9

1

2

1.0V_VCCSTU

1

CC9

5

1U_0402_6.3V6K

2

4

1U_0402_6.3V6K

2

UC3

1

IN

2

IN

3

VBI

VC

AS

4

ON

Z1334DI-01_DFN8-7_3X3

AO

OU

C_PAD

GN

+1.

0V_VCCST_L

6

T

+1.

0VALW

7
5

D

+1.0V_VCCST: 60mA
R ON = 4.5mΩ
VDROP= 1.32mV
Delay time: 270us

.0VALW TO +1.0VS_VCCSTG

and VCCIO SLEW RATE <=65us

VCCSTG

+5VALW

+1.

0VALW

1

2

6

12

1

2

1

02

CC1
1U_0402_6.3V6K@

2

CC1

00

1U_0402_6.3V6K

UC4

1

IN

2

IN

3

VBI

VC

AS

C_PAD

4

ON

AO

Z1334DI-01_DFN8-7_3X3

OU

GN

D

0VALW

+1.

7
5

0VS_VCCSTG_IO

+1.

6

T

1

JC

112

JUMP_43X79

@

1.0 Modify

RH1

RC4

+1.

2

UNPOP
Default

1 2

69 0_0805_5%@

1 2

5

E

0V_VCCST

1

CC9

0.

1U_0201_10V6K

2

use POWER side

+1.

0VS_VCCIO

+1.

0VS_VCCSTG

@

0_0805_5%

6

1

CC1

1U_0201_10V6K

0.

2

01

+1.0VS_VCCSTG: 60mA
R ON = 4.4mΩ
VDROP= 11mV
Delay time: 9.3us

4 4

Security Clas sification

Security Clas sification

Security Clas sification

2016/11/03 2017/01/10

2016/11/03 2017/01/10

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2016/11/03 2017/01/10

C

mpal Secret Data

mpal Secret Data

mpal Secret Data

Co

Co

Co

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

tle

tle

tle

Ti

Ti

Ti

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

stom

stom

stom

Cu

Cu

Cu

Date: Sheet

Date: Sheet

D

Date: Sheet

L-H(9/9)RSVD

L-H(9/9)RSVD

L-H(9/9)RSVD

SK

SK

SK

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

E

1A

1A

1A

13 64Tuesday, April 11, 2017

13 64Tuesday, April 11, 2017

13 64Tuesday, April 11, 2017

of

of

of

A

B

C

D

E

DDR_

A_DQS#[0..7]<7>

DDR_

A_D[0..63]<7>

A_DQS[0..7]<7>

DDR_

DDR_

A_MA[0..16]<7>

A_BA0<7>

DDR_

DDR_

A_BA1<7>

A_BG0<7>

DDR_
DDR_

DDR_A_CKE1<7>

1U
_0402_6.3V6K

CD5

CD1

9

1

2

DDR_
DDR_
DDR_

DDR_

DDR_

DDR_

A_CS#0<7>

DDR_

CK_SDATA<15,18,38>

D_
D_

CK_SCLK<15,18,38>

A_ODT0<7>

DDR_

DDR_

1

2

10U_0603_6.3V6M

1

2

+0.6VS_VTT

1U
_0402_6.3V6K

CD2

9

A_BG1<7>

A_CLK0<7>
A_CLK#0<7>
A_CLK1<7>

A_CLK#1<7>

A_CKE0<7>

A_CS#1<7>

A_ODT1<7>

1U
_0402_6.3V6K

CD6

10U_0603_6.3V6M

CD2

0

1U
_0402_6.3V6K

1

2

VS

+3

1 1

Layout Note:
Place near JDIMM1

2 2

.2V_VDDQ

+1

1U
_0402_6.3V6K

1

1

CD4

2

2

+1.2V_VDDQ

10U_0603_6.3V6M

10U_0603_6.3V6M

CD1

1

1

8

2

3 3

4 4

2

Layout Note:
Place near JDIMM1.258

1U
_0402_6.3V6K

1

CD2

8

2

Layout Note:
Place near JDIMM1.255

DDR_

A_BA0

DDR_

A_BA1
A_BG0

DDR_
DDR_

A_BG1

A_CLK0

DDR_
DDR_

A_CLK#0
A_CLK1

DDR_
DDR_

A_CLK#1

A_CKE0

DDR_

A_CKE1

DDR_
DDR_

A_CS#0

DDR_

A_CS#1

CK_SDATA

D_
D_

CK_SCLK

A_ODT0

DDR_

A_ODT1

DDR_

Note:

caps close to DIMM

place
4 on each side of DIMM

1U

1U
_0402_6.3V6K

1

2

CD2

1

1

2

CD3

0

0_0402_5%

A

CD7

10U_0603_6.3V6M

@

RD8

1U

1

2

_0402_6.3V6K

1

2

CD2

1

3

2

10U

_0603_6.3V6M

1

2

Place

5

CD3

1U_0201_10V6K

0.

CD9

10U

_0603_6.3V6M

CD3

2

1U_0402_6.3V6K

1

CD1

0

2

10U

_0603_6.3V6M

CD2

1

4

2

10U

_0603_6.3V6M

@

CD3

1

3

2

Holder

+3

VS_DIMMA

1

6

CD3

2

2.2U_0402_6.3V6M

_0402_6.3V6K

1

CD8

2

10U

_0603_6.3V6M

CD2

1

2

2

1U
_0402_6.3V6K

1

CD3

1

2

12

1

2

1

2

1U_0402_6.3V6K

CD2

5

CD1

1

.2V_VDDQ

+1

1

2

CD1

2

Fo

llow

MA51

1

+

CD26

_D2_2V_Y

330U

2

SG

A00009S00
330U 2V H1.9
9mohm POLY

+0

.6V_DDRA_VREFCA

CPU

+0

.6V_VREFCA

CD2

022U_0402_16V7K

0.

RD4

9_0402_1%

24.

Place near to SO-DIMM
connector.

1

3

CD1

2

1U_0201_10V6K

1U_0201_10V6K

0.

0.

1

1

8

7

CD3

CD3

2

2

1U_0201_10V6K

0.

2.2U_0402_6.3V6M

Side

1

2

12

Layout Note:
Place near JDIMM1.257/259

1

2

Layout
Place near JDIMM1.164
within 200mils

B

RD2
2_0402_1%

4

CD1

1U_0402_6.3V6K

DDR_

12

1

2

DRAMRST#<18>

Note:

+1

1U_0402_6.3V6K

.2V_VDDQ

RD1

1 2

RD3

1 2

+2

.5V

1

5

CD1

2

*2015MOW02,

Layout Note:
Place near JDIMM1.164

1

CD1

_0402_1%

2

1U_0201_10V6K

1K

0.

1

CD3

_0402_1%

2

1U_0201_10V6K

1K

0.

1

7

6

CD1

CD1

2

10U_0603_6.3V6M

10U_0603_6.3V6M

XEMC@

CD34100P

_0402_50V8J

Can't install Cap on DRAMRST

Di

mm1 Side

.6V_DDRA_VREFCA

+0

43016 PDG 1.0164

+0

.6V_DDRA_VREFCA

+1

.2V_VDDQ

RD7

@

0_0402_5%

1

2

Layout
PLACE THE CAP within 200mil from Pin108

#5
20mils wide & spacing

A_ACT#<7>

DDR_

DDR_

A_PARITY<7>

DDR_

A_ALERT#<7>

1 2

240_0402_1%

RD5

SPD

Address for CHANNEL0
Write Adress 0xA0
Read Address 0xA1
SA0=0;SA1 =0;SA2=0

+1

.2V_VDDQ

RD6
470_0402_5%

1 2

12

1

CD2

7

1U_0201_10V6K

0.

2

@

NOTE

Security Classifica tion

Security Classifica tion

Security Classifica tion

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

JD

DDR_

A_CLK0

DDR_

A_CLK#0

DDR_

A_CLK1
A_CLK#1

DDR_

DDR_

A_CKE0

DDR_

A_CKE1

A_CS#0

DDR_
DDR_

A_CS#1

A_ODT0

DDR_
DDR_

A_ODT1

DDR_

A_BG0

DDR_

A_BG1
A_BA0

DDR_

A_BA1

DDR_

DDR_

A_MA0

DDR_

A_MA1

DDR_

A_MA2
A_MA3

DDR_

A_MA4

DDR_
DDR_

A_MA5
DDR_A_MA6
DDR_

A_MA7

A_MA8

DDR_

A_MA9

DDR_
DDR_A_MA10

A_MA11

DDR_
DDR_

A_MA12

A_MA13

DDR_

A_MA14

DDR_

A_MA15

DDR_

A_MA16

DDR_

A_ACT#

DDR_

A_PARITY

DDR_

A_ALERT#

DDR_
DDR_

A_EVENT#
DRAMRST#_R

DDR_

CK_SDATA

D_
D_

CK_SCLK

DDR_

A_SA2

A_SA1

DDR_

A_SA0

DDR_

+1

.2V_VDDQ

DDR_

DRAMRST#_R <15>

11/03 2017/01/10

11/03 2017/01/10

11/03 2017/01/10

2016/

2016/

2016/

IMM1A

REVERS

137

0(T)

CK

139

0#(C)

CK

138

CK

1(T)

140

1#(C)

CK

109

E0

CK

110

CK

E1

149

S0

#

157

S1

#

162

S2

#/C0

165

S3

#/C1

155

OD

T0

161

T1

OD

115

0

BG

113

BG

1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A1

0_AP

120

A1

1

119

A1

2

158

3

A1

151

A1

4_WE#

156

5_CAS#

A1

152

A1

6_RAS#

114

ACT#

143

PARITY

116

ERT#

AL

134

EVENT#

108

RE

SET#

254

SDA

253

SC

L

166

SA2

260

SA1

256

SA0

92

0_NC

CB

91

1_NC

CB

101

2_NC

CB

105

3_NC

CB

88

CB

4_NC

87

5_NC

CB

100

CB

6_NC

104

7_NC

CB

97

DQ

S8(T)

95

DQ

S8#(C)

12

DM

0#/DBI0#

33

DM

1#/DBI1#

54

2#/DBI2#

DM

75

DM

3#/DBI3#

178

4#/DBI4#

DM

199

DM

5#/DBI5#

220

6#/DBI6#

DM

241

DM7#/DBI7#

96

8#/DBI8#

DM

LOTES_ADDR0206-P001A

CONN@

mpal Secret Data

mpal Secret Data

mpal Secret Data

Co

Co

Co

Deciphered Date

Deciphered Date

Deciphered Date

E

DQ

DQ

S0#(C)

DQ
DQ
DQ
DQ
DQ
DQ

DQ

S1#(C)

DQ

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ

DQ

S2#(C)

DQ
DQ
DQ
DQ
DQ
DQ
DQ30
DQ

DQS3(T)

S3#(C)

DQ

DQ
DQ33
DQ
DQ35
DQ
DQ
DQ
DQ

DQ

S4#(C)

DQ

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ

DQ

S5#(C)

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQS6(T)

S6#(C)

DQ

DQ
DQ57
DQ
DQ59
DQ60
DQ61
DQ62
DQ63

DQS7(T)

DQS7#(C)

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

S0(T)

DQ
DQ

S1(T)

S2(T)

S4(T)

S5(T)

0
1
2
3
4
5
6
7

8

9
10
11
12
13
14
15

16
17
18
19
20
21
22
23

24
25
26
27
28
29

31

32

34

36
37
38
39

40
41
42
43
44
45
46
47

48
49
50
51
52
53
54
55

56

58

8
7
20
21
4
3
16
17
13
11

28
29
41
42
24
25
38
37
34
32

50
49
62
63
46
45
58
59
55
53

70
71
83
84
66
67
79
80
76
74

174
173
187
186
170
169
183
182
179
177

195
194
207
208
191
190
203
204
200
198

216
215
228
229
211
212
224
225
221
219

237
236
249
250
232
233
245
246
242
240

DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_

DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_

DDR_
DDR_
DDR_
DDR_
DDR_
DDR_A_D21
DDR_
DDR_
DDR_
DDR_A_DQS#2

DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_

DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_

DDR_
DDR_
DDR_
DDR_A_D43
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_

DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_

DDR_
DDR_
DDR_
DDR_
DDR_A_D60
DDR_
DDR_A_D62
DDR_
DDR_A_DQS7
DDR_

D

A_D0
A_D1
A_D2
A_D3
A_D4
A_D5
A_D6
A_D7
A_DQS0
A_DQS#0

A_D8
A_D9
A_D10
A_D11
A_D12
A_D13
A_D14
A_D15
A_DQS1
A_DQS#1

A_D16
A_D17
A_D18
A_D19
A_D20

A_D22
A_D23
A_DQS2

A_D24
A_D25
A_D26
A_D27
A_D28
A_D29
A_D30
A_D31
A_DQS3
A_DQS#3

A_D32
A_D33
A_D34
A_D35
A_D36
A_D37
A_D38
A_D39
A_DQS4
A_DQS#4

A_D40
A_D41
A_D42

A_D44
A_D45
A_D46
A_D47
A_DQS5
A_DQS#5

A_D48
A_D49
A_D50
A_D51
A_D52
A_D53
A_D54
A_D55
A_DQS6
A_DQS#6

A_D56
A_D57
A_D58
A_D59

A_D61

A_D63

A_DQS#7

+1

.2V_VDDQ

+0

.6V_DDRA_VREFCA

+3

In

Ti

Ti

Ti

tle

tle

tle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

stom

stom

stom

Cu

Cu

Cu

Date: Sheet of

Date: Sheet of

Date: Sheet of

VS_DIMMA

Reverse

to 1 DIMMs/channel

2-3A

IMM1B

JD

REVERS

111

D1

VD

112

VD

D2

117

D3

VD

118

VD

D4

123

D5

VD

124

D6

VD

129

D7

VD

130

D8

VD

135

D9

VD

136

D10

VD

255

DSPD

VD

164

EFCA

VR

1

VSS

2

VSS

5

VSS

6

VSS

9

VSS

10

VSS

14

VSS

15

VSS

18

VSS

19

VSS

22

VSS

23

VSS

26

VSS

27

VSS

30

VSS

31

VSS

35

VSS

36

VSS

39

VSS

40

VSS

43

VSS

44

VSS

47

VSS

48

VSS

51

VSS

52

VSS

56

VSS

57

VSS

60

VSS

61

VSS

64

VSS

65

VSS

68

VSS

69

VSS

72

VSS

73

VSS

77

VSS

78

VSS

81

VSS

82

VSS

85

VSS

86

VSS

89

VSS

90

VSS

93

VSS

94

VSS

98

VSS

262

GND

LOTES_ADDR0206-P001A

CONN@

E

D11

VD
VD

D12
D13

VD
VD

D14
D15

VD

D16

VD

D17

VD

D18

VD

D19

VD

T

VT

VPP1
VPP2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

GND

Type-4H

+1

.2V_VDDQ

141
142
147
148
153
154
159
160
163

.6VS_VTT

+0

258

257
259

99
102
103
106
107
167
168
171
172
175
176
180
181
184
185
188
189
192
193
196
197
201
202
205
206
209
210
213
214
217
218
222
223
226
227
230
231
234
235
238
239
243
244
247
248
251
252

261

+2

.5V

terleaved Memory

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

DDR4_DIMMA

DDR4_DIMMA

DDR4_DIMMA

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

E

14 64Tuesday, April 11, 2017

14 64Tuesday, April 11, 2017

14 64Tuesday, April 11, 2017

1A

1A

1A

A

DDR_

B_DQS#[0..7]<7>

DDR_

B_D[0..63]<7>

B_DQS[0..7]<7>

DDR_

DDR_

B_MA[0..16]<7>

DDR_

1U_0402_6.3V6K

CD4

5

10U

_0603_6.3V6M

CD5

9

1

2

0_0402_5%

DDR_
DDR_
DDR_

DDR_
DDR_
DDR_
DDR_

DDR_
DDR_

DDR_

DDR_

D_

CK_SDATA

D_CK_SCLK

DDR_
DDR_B_ODT1

1U_0402_6.3V6K

1

CD4

6

2

10U

_0603_6.3V6M

CD6

1

0

2

1U_0402_6.3V6K

CD6

9

@

5

RD1

12

B_BA0
B_BA1
B_BG0
B_BG1

B_CLK0
B_CLK#0
B_CLK1
B_CLK#1

B_CKE0
B_CKE1

B_CS#0

B_CS#1

B_ODT0

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CD4

7

2

2

10U

_0603_6.3V6M

CD6

CD6

1

1

1

2

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

@

CD7

1

1

0

2

2

Place Holder

2

1

CD7

2

1U_0201_10V6K

0.

CD4

8

10U

_0603_6.3V6M

CD7

1

1

2

1

2

1

2

VS_DIMMB

+3

2.2U_0402_6.3V6M

3

CD7

1U_0402_6.3V6K

CD6

3

+1

CD4

9

@

DDR_

B_BA0<7>
B_BA1<7>

DDR_
DDR_

Note:

CD4

2

10U

_0603_6.3V6M

1U_0402_6.3V6K

1

2

1

2

CD6

6

DDR_
DDR_
DDR_
DDR_

DDR_B_CKE0<7>
DDR_
DDR_
DDR_

D_
D_

1U_0402_6.3V6K

CD5

7

B_BG0<7>

DDR_

B_BG1<7>

B_CLK0<7>
B_CLK#0<7>
B_CLK1<7>
B_CLK#1<7>

B_CKE1<7>
B_CS#0<7>
B_CS#1<7>

CK_SDATA<14,18,38>
CK_SCLK<14,18,38>

B_ODT0<7>

DDR_
DDR_

B_ODT1<7>

Note:
place caps close to DIMM
4 on each side of DIMM

1U_0402_6.3V6K

1

1

CD4

CD4

4

3

2

2

10U

10U

_0603_6.3V6M

_0603_6.3V6M

CD5

1

1

8

2

2

+0

.6VS_VTT

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CD6

CD6

8

7

2

2

+3VS

A

1 1

Layout
Place near JDIMM2

2 2

.2V_VDDQ

+1

1U_0402_6.3V6K

1

2

.2V_VDDQ

+1

10U

_0603_6.3V6M

CD5

1

6

3 3

4 4

2

Layout Note:
Place near JDIMM2.258

1

2

Layout Note:
Place near JDIMM1.255

CPU

+0

.6V_B_VREFDQ

CD4

0.022U_0402_16V7K

RD1

24.9_0402_1%

Place

.2V_VDDQ

1

0

1

CD5

CD5

2

1U_0201_10V6K

0.

llow

Fo
MA51

1

+

4

CD6

_D2_2V_Y

330U

2

SGA00009S00
330U 2V H1.9
9mohm POLY

.6V_DDRB_VREFCA

+0

1

4

CD7

2

B

+1

.2V_VDDQ

RD9

_0402_1%
1K

1

RD1

1K_0402_1%

1

9

+0

2

1U_0201_10V6K

0.

.6V_DDRB_VREFCA

CD3

1 2

1 2

Side

0

RD1
2_0402_1%

12

1

0

2

12

2

near to SO-DIMM connector.

Layout Note:
Place near JDIMM2.257/259

+2

.5V

1

2

1U_0201_10V6K

0.

1

5

CD7

2

1U_0201_10V6K

0.

1

2

1U_0402_6.3V6K

Layout
Place near JDIMM1.164

2.2U_0402_6.3V6M

within 200mils

B

2

CD5

1

1

2

4

3

CD5

CD5

2

1U_0402_6.3V6K

10U_0603_6.3V6M

Note:

C

Di

mm2 Side

Layout Note:
Place near JDIMM2.164

20mils wide & spacing

1

CD4

1

0.

1U_0201_10V6K

2

DDR_

.2V_VDDQ

+1

1

5

CD5

2

10U_0603_6.3V6M

NOTE

Layout
PLACE THE CAP within 200mil from Pin108

*2015MOW02,

DDR_
DDR_

RD1

SPD

Address for CHANNELB
Write Adress 0xA4
Read Address 0xA3
SA0=0;SA1 =1;SA2=0

1

CD65

0.

2

@

Can't install Cap on DRAMRST

Security Classifica tion

Security Classifica tion

Security Classifica tion

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

B_ACT#<7>

B_PARITY<7>
B_ALERT#<7>

1 2

3 240_0402_1%

+3

VS

RD1

1 2

0_0402_5%

From

CPU to CHB

DDR_

1U_0201_10V6K

IMM2A

B_BG0
B_BG1
B_BA0
B_BA1

B_MA0
B_MA1
B_MA2

B_MA4
B_MA5
B_MA6

B_MA8
B_MA9
B_MA10
B_MA11
B_MA12
B_MA13
B_MA14
B_MA15
B_MA16

B_SA2
B_SA1
B_SA0

Co

Co

Co

JD

RESERV

137

0(T)

CK

139

CK

0#(C)

138

1(T)

CK

140

CK

1#(C)

109

CK

E0

110

CK

E1

149

S0

#

157

S1

#

162

S2

#/C0

165

#/C1

S3

155

T0

OD

161

OD

T1

115

0

BG

113

1

BG

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

0_AP

A1

120

A1

1

119

2

A1

158

A1

3

151

4_WE#

A1

156

A15_CAS#

152

6_RAS#

A1

114

T#

AC

143

PAR

ITY

116

ALERT#

134

EVEN

T#

108

RESET#

254

SD

A

253

L

SC

166

SA2

260

SA1

256

SA0

92

0_NC

CB

91

CB

1_NC

101

2_NC

CB

105

CB

3_NC

88

4_NC

CB

87

CB

5_NC

100

CB

6_NC

104

CB

7_NC

97

DQ

S8(T)

95

DQ

S8#(C)

12

DM

0#/DBI0#

33

1#/DBI1#

DM

54

DM

2#/DBI2#

75

3#/DBI3#

DM

178

DM4#/DBI4#

199

5#/DBI5#

DM

220

DM6#/DBI6#

241

7#/DBI7#

DM

96

DM8#/DBI8#

LOTES_ADDR0070-P009A

CONN@

mpal Secret Data

mpal Secret Data

mpal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

E

DQ

DQ

DQ

DQS3#(C)

DQ

DQ

DQS6#(C)

DQS7#(C)

B_CLK0

DDR_
DDR_

B_CLK#0

DDR_

B_CLK1

DDR_

B_CLK#1

B_CKE0

DDR_
DDR_

B_CKE1

DDR_

B_CS#0

DDR_

B_CS#1

DDR_

B_ODT0

DDR_

B_ODT1

DDR_
DDR_
DDR_
DDR_

DDR_
DDR_
DDR_
DDR_B_MA3
DDR_
DDR_
DDR_
DDR_B_MA7
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_

B_ACT#

DDR_

B_PARITY

DDR_
DDR_

B_ALERT#
B_EVENT#

DDR_

DRAMRST#_R

DDR_

D_

CK_SDATA
CK_SCLK

D_

DDR_

4

@

DDR_
DDR_

.2V_VDDQ

+1

DRAMRST#_R <14>

11/03 2017/01/10

11/03 2017/01/10

11/03 2017/01/10

2016/

2016/

2016/

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ

S0(T)

S0#(C)

DQ

DQ
DQ
DQ
DQ
DQ
DQ
DQ
S1(T)

DQ

S1#(C)

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ

S2(T)

S2#(C)

DQ
DQ
DQ
DQ27
DQ
DQ29
DQ
DQ31

DQ

S3(T)

DQ32
DQ
DQ
DQ
DQ
DQ
DQ
DQ
S4(T)

DQ

S4#(C)

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ

S5(T)

S5#(C)

DQ
DQ
DQ
DQ
DQ
DQ53
DQ
DQ55
S6(T)

DQ

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQS7(T)

D

Reverse

2-3A

B_D0

DDR_

8

0

DDR_

B_D1

7

1

DDR_

B_D2

20

2

DDR_

B_D3

21

3

DDR_

B_D4

4

4
5
6
7

8

9
10
11
12
13
14
15

16
17
18
19
20
21
22
23

24
25
26

28

30

33
34
35
36
37
38
39

40
41
42
43
44
45
46
47

48
49
50
51
52

54

D

3
16
17
13
11

28
29
41
42
24
25
38
37
34
32

50
49
62
63
46
45
58
59
55
53

70
71
83
84
66
67
79
80
76
74

174
173
187
186
170
169
183
182
179
177

195
194
207
208
191
190
203
204
200
198

216
215
228
229
211
212
224
225
221
219

237
236
249
250
232
233
245
246
242
240

B_D5

DDR_
DDR_

B_D6

DDR_

B_D7

DDR_

B_DQS0

DDR_

B_DQS#0

DDR_

B_D8
B_D9

DDR_
DDR_

B_D11

DDR_

B_D15
B_D14

DDR_

B_D10

DDR_

B_D12

DDR_
DDR_

B_D13

DDR_

B_DQS1

DDR_

B_DQS#1

B_D16

DDR_
DDR_

B_D17
DDR_B_D19
DDR_

B_D20

B_D22

DDR_

B_D18

DDR_
DDR_B_D23

B_D21

DDR_
DDR_

B_DQS2

B_DQS#2

DDR_

B_D30

DDR_

B_D25

DDR_
DDR_

B_D26

B_D24

DDR_

B_D28

DDR_

B_D27

DDR_

B_D29

DDR_
DDR_

B_D31

B_DQS3

DDR_
DDR_

B_DQS#3

B_D34

DDR_
DDR_

B_D35
DDR_

B_D36
DDR_

B_D32

B_D39

DDR_

B_D38

DDR_
DDR_

B_D37
DDR_

B_D33
DDR_

B_DQS4

B_DQS#4

DDR_

DDR_B_D40
DDR_

B_D41
DDR_

B_D42

B_D43

DDR_

B_D44

DDR_

B_D45

DDR_
DDR_

B_D46
DDR_

B_D47

B_DQS5

DDR_
DDR_

B_DQS#5

DDR_

B_D48
DDR_

B_D52
DDR_

B_D50

B_D55

DDR_

B_D51

DDR_
DDR_

B_D54
DDR_

B_D49

B_D53

DDR_
DDR_

B_DQS6

B_DQS#6

DDR_

DDR_

B_D61
DDR_B_D57
DDR_

B_D60
DDR_B_D56
DDR_

B_D62
DDR_B_D59

B_D63

DDR_
DDR_B_D58

B_DQS7

DDR_
DDR_B_DQS#7

+1

.2V_VDDQ

+0

.6V_DDRB_VREFCA

+3

In

terleaved Memory

Ti

Ti

Ti

tle

tle

tle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

stom

stom

stom

Cu

Cu

Cu

Date: Sheet of

Date: Sheet of

Date: Sheet of

111
112
117
118
123
124
129
130
135
136

VS_DIMMB

255

164

1
2
5
6

9
10
14
15
18
19
22
23
26
27
30
31
35
36
39
40
43
44
47
48
51
52
56
57
60
61
64
65
68
69
72
73
77
78
81
82
85
86
89
90
93
94
98

262

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

DDR4_DIMMB

DDR4_DIMMB

DDR4_DIMMB

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

E

Type-8H

to 1 DIMMs/channel

IMM2B

JD

E

RESERV

D1

VD
VD

D2
D3

VD
VD

D4
D5

VD

D6

VD

D7

VD

D8

VD

D9

VD

D10

VD

DSPD

VD

EFCA

VR

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

GND

LOTES_ADDR0070-P009A

CONN@

141

D11

VD

142

VD

D12

147

D13

VD

148

VD

D14

153

D15

VD

154

D16

VD

159

D17

VD

160

D18

VD

163

D19

VD

258

T

VT

257

VPP1

259

VPP2

99

VSS

102

VSS

103

VSS

106

VSS

107

VSS

167

VSS

168

VSS

171

VSS

172

VSS

175

VSS

176

VSS

180

VSS

181

VSS

184

VSS

185

VSS

188

VSS

189

VSS

192

VSS

193

VSS

196

VSS

197

VSS

201

VSS

202

VSS

205

VSS

206

VSS

209

VSS

210

VSS

213

VSS

214

VSS

217

VSS

218

VSS

222

VSS

223

VSS

226

VSS

227

VSS

230

VSS

231

VSS

234

VSS

235

VSS

238

VSS

239

VSS

243

VSS

244

VSS

247

VSS

248

VSS

251

VSS

252

VSS

261

GND

15 64Tuesday, April 11, 2017

15 64Tuesday, April 11, 2017

E

15 64Tuesday, April 11, 2017

+1

.2V_VDDQ

+0

.6VS_VTT

+2

.5V

1A

1A

1A

A

US

B3_PTX_DRX_N2<35>
B3_PTX_DRX_P2<35>

US

B3_PRX_DTX_N2<35>

1 1

US

B3 MB

USB3 SUB

Type C

USB3

US
US

B3_PRX_DTX_P2<35>

B3_PTX_DRX_N5<33>

US

B3_PTX_DRX_P5<33>

US

B3_PRX_DTX_N5<33>

US

B3_PRX_DTX_P5<33>

US

B3_PTX_DRX_P3<36>

US

B3_PTX_DRX_N3<36>

US

B3_PRX_DTX_P3<36>

US
US

B3_PRX_DTX_N3<36>

US

B3_PTX_DRX_P4<36>
B3_PTX_DRX_N4<36>

US

B3_PRX_DTX_P4<36>

US
US

B3_PRX_DTX_N4<36>

B

UH1F

C11

US

B3_1_TXN

B11

B3_1_TXP

US

B7

B3_1_RXN

US

A7

B3_1_RXP

US

B12

US

B3_2_TXN/SSIC_1_TXN

A12

US

B3_2_TXP/SSIC_1_TXP

C8

B3_2_RXN/SSIC_1_RXN

US

B8

US

B3_2_RXP/SSIC_1_RXP

B15

US

B3_6_TXN

C15

B3_6_TXP

US

K15

B3_6_RXN

US

K13

US

B3_6_RXP

B14

B3_5_TXN

US

C14

US

B3_5_TXP

G13

B3_5_RXN

US

H13

USB3_5_RXP

D13

US

B3_3_TXP/SSIC_2_TXP

C13

US

B3_3_TXN/SSIC_2_TXN

A9

B3_3_RXP/SSIC_2_RXP

US

B10

US

B3_3_RXN/SSIC_2_RXN

B13

US

B3_4_TXP

A14

B3_4_TXN

US

G11

USB3_4_RXP

E11

US

B3_4_RXN

SKL-H-PCH_BGA837

C

-H_PCH

SPT

LPC/eSPI

US
B

SATA

REV = 1.3

@

GP

P_A1/LAD0/E SPI_IO0
P_A2/LAD1/E SPI_IO1

GP

P_A3/LAD2/E SPI_IO2

GP

P_A4/LAD3/E SPI_IO3

GP

GP

P_A5/LFRA ME#/ESPI_CS0#

P_A6/SERIR Q/ESPI_CS1#

GP

GP

P_A7/PIRQA# /ESPI_ALERT0#

P_A0/RCIN# /ESPI_ALERT1#

GP

GP

P_A14/SUS _STAT#/ESPI_RES ET#

GP

P_A9/CLKOU T_LPC0/ESPI_CLK

P_A10/CLKOU T_LPC1

GP

P_G19/SMI#

GP
GPP_G18/NMI#

GP

P_E6/DEVS LP2
P_E5/DEVS LP1

GP
GP

P_E4/DEVS LP0
P_F9/DEVS LP7

GP
GP

P_F8/DEVS LP6
P_F7/DEVS LP5

GP

6

OF 12

GPP_F6/DEV SLP4
GP

P_F5/DEVS LP3

LP

C_AD0

AT22

C_AD1

LP

AV22

C_AD2

LP

AT19

C_AD3

LP

BD16

LP

C_FRAME#

BE16

M_SERIRQ

TP

BA17

LP

C_PIRQA#

AW17
AT17

ESPI

_RST#

BC18

CL

K_LPC

BC17

K_LPC_TPM

CL

AV19

M45
N43

AE45
AG43

SSD

_DEVSLP0

AG42
AB39
AB36
AB43
AB42
AB41

?

RH3
RH4

LP

C_AD0 <39,41>
C_AD1 <39,41>

LP
LP

C_AD2 <39,41>

LP

C_AD3 <39,41>

C_FRAME# <39,41>

LP

M_SERIRQ <39,41>

TP

_RST# <39>

ESPI

12

22_0402_5%

12

22_0402_5%TPM@

SSD

_DEVSLP0 <34>

L

LPC

PC Bus

: +3.3V

To

TPM

CL

K_LPC_R <39>
K_LPC_TPM_R <41>

CL

D

M_SERIRQ

TP

DG requierment 8.2k PH +3VS
CRB 10K PH +3vs

RH1

1 2

10K_0402_5%

E

+3

VS

To EC

VALW_PCH_PRIM

+3

C_PIRQA#

LP

RH5

12

10K_0402_5%

1.0 Modify

US

B_OC0#

CH6

1 2

8

EMC@

1000P

_0402_50V7K

2 2

DM

DM

I_CTX_PRX_N0<8>

DM

I_CTX_PRX_P0<8>
I_CRX_PTX_N0<8>

DM

I_CRX_PTX_P0<8>

DM

I_CTX_PRX_N1<8>

DM
DM

I_CTX_PRX_P1<8>
I_CRX_PTX_N1<8>

DM
DMI_CRX_PTX_P1<8>

I_CTX_PRX_N2<8>

DM
DM

I_CTX_PRX_P2<8>
I_CRX_PTX_N2<8>

DM

I_CRX_PTX_P2<8>

DM
DM

I_CTX_PRX_N3<8>
I_CTX_PRX_P3<8>

DM
DM

I_CRX_PTX_N3<8>
I_CRX_PTX_P3<8>

DM

1 2

RH6

#546884
BO=4 W=12~15 S=12 R=100ohm

3 3

NGFF
WL+BT(KEY E)

GLAN

PC

IE_PRX_DTX_N3<37>

PC

IE_PRX_DTX_P3<37>

IE_PTX_C_DRX_N3<37>

PC
PCIE_PTX_C_DRX_P3<37>

PCIE_PRX_DTX_N4<32>
PC

IE_PRX_DTX_P4<32>

IE_PTX_C_DRX_N4<32>

PC

IE_PTX_C_DRX_P4<32>

PC

P.231 PCIE_RCOMPN/PCIE_RCOMPP

CH5
CH6

CH7
CH8

100_0402_1%

12

.1U_0402_16V7K

12

.1U_0402_16V7K

12

.1U_0402_16V7K

12

.1U_0402_16V7K

I_CTX_PRX_N0
DMI_CTX_PRX_P0
DM

I_CRX_PTX_N0

I_CRX_PTX_P0

DM
DM

I_CTX_PRX_N1
DM

I_CTX_PRX_P1
DM

I_CRX_PTX_N1
DM

I_CRX_PTX_P1

I_CTX_PRX_N2

DM
DM

I_CTX_PRX_P2

I_CRX_PTX_N2

DM
DM

I_CRX_PTX_P2

I_CTX_PRX_N3

DM
DM

I_CTX_PRX_P3
DM

I_CRX_PTX_N3

I_CRX_PTX_P3

DM

IE_RCOMPN

PC
PC

IE_RCOMPP

IE_PRX_DTX_N3

PC
PC

IE_PRX_DTX_P3

PC

IE_PTX_DRX_N3

PC

IE_PTX_DRX_P3
IE_PRX_DTX_N4

PC
PC

IE_PRX_DTX_P4

IE_PTX_DRX_N4

PC
PC

IE_PTX_DRX_P4

UH1B

L27

DM

I_RXN0

N27

DMI_RXP0

C27

DM

I_TXN0

B27

I_TXP0

DM

E24

DM

I_RXN1

G24

DM

I_RXP1

B28

DM

I_TXN1

A28

DM

I_TXP1

G27

I_RXN2

DM

E26

DM

I_RXP2

B29

I_TXN2

DM

C29

DM

I_TXP2

L29

I_RXN3

DM

K29

DM

I_RXP3

B30

DM

I_TXN3

A30

I_TXP3

DM

B18

IE_RCOMPN

PC

C17

PC

IE_RCOMPP

H15

IE1_RXN/USB3_7_RXN

PC

G15

PC

IE1_RXP/USB3_7_RXP

A16

PC

IE1_TXN/USB3_7_TXN

B16

IE1_TXP/USB3_7_TXP

PC

B19

PC

IE2_TXN/USB3_8_TXN

C19

IE2_TXP/USB3_8_TXP

PC

E17

PC

IE2_RXN/USB3_8_RXN

G17

IE2_RXP/USB3_8_RXP

PC

L17

IE3_RXN/USB3_9_RXN

PC

K17

PC

IE3_RXP/USB3_9_RXP

B20

PC

IE3_TXN/USB3_9_TXN

C20

PC

IE3_TXP/USB3_9_TXP

E20

IE4_RXN/USB3_10_RXN

PC

G19

PC

IE4_RXP/USB3_10_RXP

B21

IE4_TXN/USB3_10_TXN

PC

A21

PC

IE4_TXP/USB3_10_TXP

K19

PC

IE5_RXN

L19

IE5_RXP

PC

D22

PCIE5_TXN

C22

IE5_TXP

PC

G22

IE6_RXN

PC

E22

PC

IE6_RXP

B22

IE6_TXN

PC

A23

PC

IE6_TXP

L22

IE7_RXN

PC

K22

PC

IE7_RXP

C23

IE7_TXN

PC

B23

PCIE7_TXP

K24

IE8_RXN

PC

L24

PCIE8_RXP

C24

PC

IE8_TXN

B24

IE8_TXP

PC

SKL-H-PCH_BGA837

@

REV = 1.3

SPT-H_PCH

I

DM

PC
Ie/USB 3

2

OF 12

USB 2.0

GP

P_E9/USB2 _OC0#

GP

P_E10/USB 2_OC1#
P_E11/USB 2_OC2#

GP
GP

P_E12/USB 2_OC3#

P_F15/USB 2_OCB_4

GP
GP

P_F16/USB 2_OCB_5

GP

P_F17/USB 2_OCB_6
P_F18/USB 2_OCB_7

GP

US

US

B2N_1
USB2P_1
US

B2N_2

B2P_2

US
US

B2N_3
US

B2P_3

US

B2N_4
US

B2P_4

B2N_5

US
US

B2P_5

B2N_6

US
US

B2P_6

B2N_7

US
US

B2P_7

US

B2N_8

B2P_8

US
US

B2N_9

B2P_9

US

US

B2N_10
B2P_10

US

B2N_11

US

B2P_11

US
US

B2N_12

US

B2P_12
B2N_13

US
US

B2P_13
B2N_14

US
US

B2P_14

B2_COMP

US

B2_VBUSSENSE

VD_AB13

RS

US

B2_ID

GPD7/RSVD

AF5
AG7

US

B20_N2

AD5

B20_P2

US

AD7

US

B20_N3

AG8

US

B20_P3

AG10
AE1
AE2

B20_N5

US

AC2

US

B20_P5

AC3

B20_N6

US

AF2

US

B20_P6

AF3

B20_N7

US

AB3

US

B20_P7

AB2

US

B20_N8

AL8

B20_P8

US

AL7

US

B20_N9

AA1

B20_P9

US

AA2

US

B20_N10

AJ8

B20_P10

US

AJ7
W2
W3
AD3
AD2
V2
V1
AJ11
AJ13

AD43
AD42
AD39
AC44
Y43
Y41
W44
W43

AG3
AD10
AB13
AG2

BD14

?

CHECK ACER DVR for port use
12/08 Change Port, follow DVR1044_R1.03

US

B_OC0#

US

B_OC1#
B_OC2#

US
US

B_OC3#
B_OC4

US
US

B_OC5
B_OC6

US

B_OC7

US

B2_COMP

US
US

B2_VBUSSENSE

US

B2_ID

546765_2015WW10_Skylake_MOW_Rev _1_0
05/19 RH150

B20_N2 <35>

US

B20_P2 <35>

US
US

B20_N3 <36>
B20_P3 <36>

US

US

B20_N5 <33>
B20_P5 <33>

US

B20_N6 <33>

US
US

B20_P6 <33>
B20_N7 <37>

US
US

B20_P7 <37>
B20_N8 <30>

US
USB20_P8 <30>
US

B20_N9 <30>

US

B20_P9 <30>
B20_N10 <42>

US

B20_P10 <42>

US

B_OC1# <35>

US

1 2

RH7

1 2

RH8

1 2

RH9

USB3 MB

TY

USB2 (SUB/B)

BT

TS

Ca

Fi

113_0402_1%
0_0402_5%@

0_0402_5%@

PE C

mera

ngerPrin t

reference PDG1.0 50-30

H1

US
US
US
US

US
US
US
US

B_OC0#
B_OC1#
B_OC3#
B_OC2#

B_OC5
B_OC4
B_OC6
B_OC7

RP

18
27
36
45

10K_0804_8P4R_5%

RP

H2

18
27
36
45

10K_0804_8P4R_5%

@

VALW_PCH_PRIM

+3

4 4

Se

Se

Se

curity Classification

curity Classification

curity Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/11/03 2017/01/10

2016/11/03 2017/01/10

2016/11/03 2017/01/10

Co

Co

Co

mpal Secret Data

mpal Secret Data

mpal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

tle

tle

tle

Ti

Ti

Ti

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Cu

Cu

Cu

stom

stom

stom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

H(1/7)DMI,PCIE,USB

H(1/7)DMI,PCIE,USB

H(1/7)DMI,PCIE,USB

PC

PC

PC

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

E

1A

1A

16 64Tuesday, April 11, 2017

16 64Tuesday, April 11, 2017

16 64Tuesday, April 11, 2017

1A

A

1 2

EC

_PME#<32,39>

1 1

SPI

VALW_PCH_PRIM

+3

12

RH4

2

10K_0402_5%

10K_0402_5%

DIS,Optimus10

2 2

M.2 SSD PCIE L2

M.2 SSD PCIE L3

3 3

SPI ROM ( 8MByte )

PCH_SPI_CS#0

H_SPI_SO_0_R

PC
PCH_SPI_IO2_0_R

4 4

UMA@

12

RH4

3

VGA@

A

UM

1.A

PCH_SPI_CLK_0_R

DG

GPP_F13

DG

Modify

UH3

1

/CS

2

(IO1)

DO

3

/WP(IO2)

4

GN

D

W2

5Q64FVSSIQ_SO8

SA

000039A40

1 2

A

PU_PRSNT#

PU_PRSNT#

PC
PC

PC
PC

IE_PRX_DTX_P12<34>

PC
PC

OLD(IO3)

/H

@

RH4

4

0_0402_5%

IE_PTX_DRX_P11<34>
IE_PTX_DRX_N11<34>

PC

IE_PRX_DTX_P11<34>

IE_PRX_DTX_N11<34>

PC

IE_PTX_DRX_P12<34>
IE_PTX_DRX_N12<34>

IE_PRX_DTX_N12<34>

+3

VALW_SPI

CH170.

1 2

8

VCC

CLK

DI

(IO0)

H_SPI_IO3_0_R

PC

7

PCH_SPI_CLK_0_R

6

PC

H_SPI_SI_0_R

5

@

1 2

CH1

9

68P_0402_50V8J

RH1

0 0_0402_5%

ROM

PC

IE_PTX_DRX_P11

PC

IE_PTX_DRX_N11

PC

IE_PRX_DTX_P11
IE_PRX_DTX_N11

PC

DG

PC

IE_PTX_DRX_P12
IE_PTX_DRX_N12

PC
PC

IE_PRX_DTX_P12
IE_PRX_DTX_N12

PC

1U_0201_10V6K

@

PU_PRSNT#

DVT modify

PC
PC
PC
PC

PC
PC

EC

_PME#_R

H_SPI_SI
H_SPI_SO
H_SPI_CS#0
H_SPI_CLK

H_SPI_IO2
H_SPI_IO3

AB33
AB35
AA44
AA45

B

UH1A

BD17

GP

P_A11/PME #

AG15

VD

RS

AG14

RS

VD

AF17

VD

RS

AE17

RS

VD

AR19

2

TP

AN17

1

TP

BB29

SPI

0_MOSI

BE30

0_MISO

SPI

BD31

SPI

0_CS0#

BC31

0_CLK

SPI

AW31

SPI

0_CS1#

BC29

0_IO2

SPI

BD30

0_IO3

SPI

AT31

SPI

0_CS2#

AN36

GP

P_D1/SPI1_C LK

AL39

P_D0/SPI1_C S#

GP

AN41

GPP_D3/SPI1 _MOSI

AN38

GP

P_D2/SPI1_M ISO

AH43

GP

P_D22/SPI1_ IO3

AG44

GP

P_D21/SPI1_ IO2

SKL-H-PCH_BGA837

@

UH1C

AV2

_CLK

CL

AV3

CL

_DATA

AW2

_RST#

CL

R44

P_G8/FAN_P WM_0

GP

R43

GPP_G9/FAN_ PWM_1

U39

GP

P_G10/FAN_P WM_2

N42

P_G11/FAN_P WM_3

GP

U43

P_G0/FAN_TA CH_0

GP

U42

GP

P_G1/FAN_TA CH_1

U41

P_G2/FAN_TA CH_2

GP

M44

P_G3/FAN_TA CH_3

GP

U36

GP

P_G4/FAN_TA CH_4

P44

GPP_G5/FAN_ TACH_5

T45

GP

P_G6/FAN_TA CH_6

T44

P_G7/FAN_TA CH_7

GP

B33

PC

IE11_TXP

C33

PC

IE11_TXN

K31

PC

IE11_RXP

L31

IE11_RXN

PC

P_F10/SCLOC K

GP
GP

P_F11/SLOAD
P_F13/SDA TAOUT0

GP
GP

P_F12/SDA TAOUT1

B38

IE14_TXN/SATA1B_TXN

PC

C38

PC

IE14_TXP/SATA1B_TXP

D39

IE14_RXN/SATA1B_RXN

PC

E37

PC

IE14_RXP/SATA1B_RXP

C36

IE13_TXN/SATA0B_TXN

PC

B36

IE13_TXP/SATA0B_TXP

PC

G35

PC

IE13_RXN/SATA0B_RXN

E35

PC

IE13_RXP/SATA0B_RXP

A35

PC

IE12_TXP

B35

IE12_TXN

PC

H33

PC

IE12_RXP

G33

IE12_RXN

PC

J45

IE20_TXP/SATA7_TXP

PC

K44

PC

IE20_TXN/SATA7_TXN

N38

PC

IE20_RXP/SATA7_RXP

N39

PC

IE20_RXN/SATA7_RXN

H44

IE19_TXP/SATA6_TXP

PC

H43

PC

IE19_TXN/SATA6_TXN

L39

IE19_RXP/SATA6_RXP

PC

L37

PC

IE19_RXN/SATA6_RXN

SKL-H-PCH_BGA837

@

Si

ngle SPI ROM_CS0#

To SPI ROM

B

REV = 1.3

SPT

SPT-H_PCH

INK

CL

FAN

?

H_SPI_CS#0

PC

H_SPI_SI_0_R

PC
PCH_SPI_SO_0_R

H_SPI_IO3_0_R

PC
PCH_SPI_CLK_0_R

PC

H_SPI_IO2_0_R

-H_PCH

3 OF 12

RPH3

1

RH3

OF 12

GP

P_B13/PLTR ST#

P_G16/GSXCLK

GP

GP

P_G12/GSXDOU T

P_G13/GSXSLOA D

GP

GP

P_G14/GSXDIN

P_G15/GSXSR ESET#

GP

GP

P_E3/CPU_ GP0

GP

P_E7/CPU_ GP1
P_B3/CPU_ GP2

GP
GP

P_B4/CPU_ GP3

GP

P_H18/SML 4ALERT#

P_H17/SML 4DATA

GP

P_H16/SML 4CLK

GP

GP

P_H15/SML 3ALERT#

P_H14/SML 3DATA

GP

GP

P_H13/SML 3CLK

P_H12/SML 2ALERT#

GP

GPP_H11/SM L2DATA

GP

P_H10/SML 2CLK

IN

TRUDER#

PC

IE9_RXN/SATA0A_RXN

IE9_RXP/SATA0A_RXP

PC
PC

IE9_TXN/SATA0A_TXN

IE9_TXP/SATA0A_TXP

PC

PCIE10_RXN/SATA1A_RXN
PC

IE10_RXP/SATA1A_RXP

IE10_TXN/SATA1A_TXN

PC
PC

IE10_TXP/SATA1A_TXP

PC

IE15_RXN/SATA2_RXN
IE15_RXP/SATA2_RXP

PC

IE15_TXN/SATA2_TXN

PC

PC

IE15_TXP/SATA2_TXP

PC

PC

IE16_RXN/SATA3_RXN

Ie/SATA

IE16_RXP/SATA3_RXP

PC
PC

IE16_TXN/SATA3_TXN

PC

IE16_TXP/SATA3_TXP

PC

IE17_RXN/SATA4_RXN
IE17_RXP/SATA4_RXP

PC
PC

IE17_TXN/SATA4_TXN
IE17_TXP/SATA4_TXP

PC

IE18_RXN/SATA5_RXN

PC
PC

IE18_RXP/SATA5_RXP

PC

IE18_TXN/SATA5_TXN
IE18_TXP/SATA5_TXP

PC

GP

P_E0/SATA XPCIE0/SATAGP0
P_E1/SATA XPCIE1/SATAGP1

GP

P_E2/SATA XPCIE2/SATAGP2

GP

P_F0/SATA XPCIE3/SATAGP3

GP
GP

P_F1/SATA XPCIE4/SATAGP4

GP

P_F2/SATA XPCIE5/SATAGP5
P_F3/SATA XPCIE6/SATAGP6

GP
GP

P_F4/SATA XPCIE7/SATAGP7

GP

P_F21/EDP _BKLTCTL

P_F20/EDP _BKLTEN

GP

GP

ST

HO

1 2

@

5 4.7K_0402_5%

and close UH6

H3

RP

1 8
2 7
3 6
4 5

15_0804_8P4R_5%

1 2

RH3

8 15_0402_5%

C

PL

T_RST#

BB27

P43
R39
R36
R42
R41

AF41
AE44
BC23
BD24

BC36
BE34
BD39
BB36
BA35
BC35
BD35
AW35
BD34

BE11

P_E8/SATA LED#

GP

P_F19/EDP _VDDEN

TH

ERMTRIP#

PEC

_SYNC

PM

PL

TRST_PROC#

_DOWN

PM

+3

VALW_SPI

_INT#

TP

fo

r server and WS use

SM

_INTRUDER#

G31
H31
C31
B31

G29
E29
C32
B32

F41
E41
B39
A39

D43
E42
A41
A40

H42
H40
E45
F45

K37
G37
G45
G44

AD44
AG36
AG35
AG39
AD35
AD31
AD38
AC43
AB44

W36
W35
W42

AJ3
AL3

I

AJ4
AK2
AH2

PL

T_RST# <23,39,41>

12

DH1

751V-40_SOD323-2

RB

4

@

T1

PAD

RH1

2

1M_0402_5%

1 2

PC

IE_PRX_DTX_N9
IE_PRX_DTX_P9

PC
PC

IE_PTX_DRX_N9
IE_PTX_DRX_P9

PC

PCIE_PRX_DTX_N10
PC

IE_PRX_DTX_P10
IE_PTX_DRX_N10

PC
PC

IE_PTX_DRX_P10

SAT

A_PRX_DTX_N2
A_PRX_DTX_P2

SAT

A_PTX_DRX_N2

SAT
SAT

A_PTX_DRX_P2

VS

+3

1 2

1 2

@

1 2

RH19 10K_0402_5%

@

1 2

RH2

PBA@

0 10K_0402_5%

RH21 1K_0402_1%

1 2

@

1 2

2 10K_0402_5%

@

RH2

4 10K_0402_5%

RH2

FOR

SERVER & WS ONLY

PC

H_BKL_PWM
BKL

EN

H_ENVDD

PC

PC

H_THERMTRIP#

PC

H_PECI
PM_SYNC_R

H_
PL

TRST_CPU#

RH2
RH2
RH2

EC

_TP_INT# <39,41>

TCVCC

+R

M.2 SSD PCIE L0

M.2 SSD PCIE L1

A_PRX_DTX_N2 <38>

SAT

SAT

A_PRX_DTX_P2 <38>

SAT

A_PTX_DRX_N2 <38>
A_PTX_DRX_P2 <38>

SAT

6

RH1
10K_0402_5%

SAT

1 2

5 620_0402_5%

1 2

6 12.1_0402_1%@
7 30_0402_1%

A_GP0

H_BKL_PWM <30>

PC

BKL <39>

EN
PC

H_ENVDD <30>

12

TRST_CPU# <9>

PL

_DOWN_R <9>

PM

M.2

PC

IE_PRX_DTX_N9 <34>

PC

IE_PRX_DTX_P9 <34>

PC

IE_PTX_DRX_N9 <34>

IE_PTX_DRX_P9 <34>

PC

IE_PRX_DTX_N10 <34>

PC

IE_PRX_DTX_P10 <34>

PC

PC

IE_PTX_DRX_N10 <34>

PC

IE_PTX_DRX_P10 <34>

SSD PCIE/SATA select pin

SAT

Follow MOW 2015WW09

PC

H_SPI_IO2

H_SPI_SI

PC
PCH_SPI_SO

H_SPI_IO3

PC
PCH_SPI_CLK

PC

H_SPI_IO2

Se

Se

Se

curity Classification

curity Classification

curity Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

H_SPI_IO3

PC

low MOW WW36

Fol
pull down with pre-ES1/ES1 samples

2016/11/03 2017/01/10

2016/11/03 2017/01/10

2016/11/03 2017/01/10

1 2

6 1K_0402_1%@

RH3

1 2

RH4

0 1K_0402_1%@

Co

Co

Co

mpal Secret Data

mpal Secret Data

mpal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

A_GP0 <34>

ERMTRIP# <9>

TH

PECI <9,39>

H_
H_PM_SYNC <9>

VALW_SPI

+3

D

D

HD

PCH
PLTRST
Buf f er

T_RST#

PL

74VHC1G08DFT2G_SC70-5

MC

D

E

+3

VS

_INT#

TP

SPI

0_MOSI
int. PH
This strap should sample HIGH. There should NOT be any
on-board device driving it to opposite direction during
strap sampling.

SPI0_MISO
int. PH
This strap should sample HIGH. There should NOT be any
on-board device driving it to opposite direction during
strap sampling.

SPI0_IO2
int. PH
This strap should sample HIGH. There should NOT be any
on-board device driving it to opposite direction during
strap sampling.

SPI0_IO3
int. PH
This strap should sample HIGH. There should NOT be any
on-board device driving it to opposite direction during
strap sampling.

GP

P_H12
int. PD
This strap should sample LOW.

PC

H_BKL_PWM
BKL

EN
PC

H_PECI

+3

1

IN

2

IN

Cu

Cu

Cu

1 2

RH1

3 100K_0402_5%

1 2

RH3

1 100K_0402_5%

1 2

RH3

2 100K_0402_5%

1 2

RH3

3 10K_0402_5%@

1 2

@

RH3

4 10K_0402_5%

VS

CH160.

1U_0201_10V6K

1 2

5

UH2

P

1

PL

T_RST_BUF#

4

O

2

G

3

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

tle

tle

tle

Ti

Ti

Ti

PC

PC

PC

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

stom

stom

stom

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

Date: Sheet of

Date: Sheet of

Date: Sheet of

12

RH2

8

100K_0402_5%

H(2/7)SPI,SATA,XDP

H(2/7)SPI,SATA,XDP

H(2/7)SPI,SATA,XDP

E

.0VALW_PRIM

+1

PLT_RST_BUF# <32,34,37>

17 64Tuesday, April 11, 2017

17 64Tuesday, April 11, 2017

17 64Tuesday, April 11, 2017

1A

1A

1A

A

HDA

for AUDIO

1 2

_EN<39>

ME

HDA

_SDOUT_R<40>

HDA

_RST_AUDIO#<40>

HDA

_SYNC_R<40>
_BIT_CLK_R<40>

HDA

HDA

1 1

+3

Follow

2 2

+R

_SDIN0<40>

+3

VALW_PCH_PRIM

VALW_DSW

10K_0804_8P4R_5%

543016_SKL_U_Y_PDG_0_9

+3

VALW_DSW

RH4

9 10K_0402_5%

RH5

0 10K_0402_5%@

RH5

1 1K_0402_5%

WAKE # (DS X wa ke ev ent )
10 KΩ pull- up t o Vc cDS W3_3
The pull-up is required even if
PCIe* interface
is not used on the plat f or m.

TCVCC

RH6

CH2

H7

RP

1 2

1 2

1 2

1 2

0 20K_0402_5%

1 2

1 1U_0402_6.3V6K

RH4

SY

18

PC

27

EC

36

LA

45

@

7 0_0402_5%

RP

H6

1 8
2 7
3 6
4 5

33_0804_8P4R_5%

S_RESET#
H_PWROK
_RSMRST#
N_WAKE#

CH6

.1U_0402_16 V7K

XEMC@

PM

AC

WA

HDA
HDA
HDA
HDA

HDA

_SDIN0

2

4

1

_BATLOW#

_PRESENT_R

KE#

H_SRTCRST#

PC

_SDOUT
_RST#
_SYNC
_BIT_CLK

1

CH6

2

0.047U_0402_16V7K

2

XEMC@

U_DISPA_SDO<6>

CP

U_DISPA_SDI_R<6>

CP

CP

U_DISPA_BCLK<6>

H_DMIC_DATA0<40>

PC

H_DMIC_CLK0<40>

PC

Remove CLR ME

H_RTCRST#

PC

H_DPWROK

12

PC

H_PWROK

12

1.0 Modify

H_SML0CLK

PC

H_SML0DATA

PC

_SMB_DA2

EC

EC

_SMB_CK2
H_SML1CLK

PC

PCH_SML1DATA

PC

H_SMBDATA
H_SMBCLK

PC

D_CK_SCLK

CK_SDATA

D_

PC

CLR

CMOS

PCH_SMBALERT#

H_SML0ALERT#

PC
PC

H_SML1ALERT#

(SO-DIMM,G-se

DMN65D8LDW-7_SOT363-6

H_SMBCLK

PC

DMN65D8LDW-7_SOT363-6

H_SMBDATA

PC

DMN65D8LDW-7_SOT363-6

PC

H_SML1CLK

DMN65D8LDW-7_SOT363-6

H_SML1DATA

PC

1 2

3 20K_0402_5%

RH6

1 2

3 1U_0402_6.3V6K

CH2

1 2

MOS1 0_0603_5%@

JC

Place at RAM DOOR

EC

3 3

VALW_PCH_PRIM

+3

4 4

_RSMRST#

SY

S_PWROK

+3

VALW_PCH_PRIM

RH6

RH1
RH1

+3

VALW_PCH_PRIM

RH6

RH6

+3VS

2.2K_0804_8P4R_5%

VALW_PCH_PRIM

+3

+3

VS

2.2K_0804_8P4R_5%

PDG_0_71 requirement PH to +3V_PCH
10/14 Dan

@

4 0_0402_5%

RH5

@

7 0_0402_5%

RH5

1 2

4 4.7K_0402_5%

1 2

67 4.7K_0402_5%@

1 2

68 4.7K_0402_5%@

1 2

5 499_0402_1%

1 2

6 499_0402_1%

H8

RP

18
27
36
45

RP

H9

18
27
36
45

A

B

I_HPD_PCH<23,31>

ose

cl
to PCH

T2
T2

PCH_PWROK<39,43>
EC

HDM

03
04

PC

PC

H_EDP_HPD<30>

RH5
30_0402_1%

1 2

1 2

RH5

8 30_0402_1%

@

PAD

@

PAD

H_RTCRST#<39>

_RSMRST#<39>

4

@

T2

PAD

nsor)

T2

5

@

PAD

T2

7

@

PAD

T1

5

6

CP

CP

PC

H_DMIC_DATA0
H_DMIC_CLK0

PC

H_DMIC_DATA1

PC
PC

H_DMIC_CLK1

(VGA, EC, RTD2168)

+3VS

1A

QH

2

6 1

QH

1B

3 4

+3

QH

2A

2

6 1

QH

2B

3 4

CK_SCLK

D_

5

CK_SDATA

D_

VS

EC

_SMB_CK2

5

_SMB_DA2

EC

B

I_HPD_PCH

HDM

_SCI#_I3

EC

PAD@

PC

H_EDP_HPD

_BIT_CLK

HDA
HDA

_RST#
_SDIN0

HDA

HDA_SDOUT
HDA

_SYNC

U_DISPA_SDO_R

U_DISPA_SDI_R

CP

U_DISPA_BCLK_R

PC

H_RTCRST#

PC

H_SRTCRST#

PC

H_PWROK
_RSMRST#

EC

H_DPWROK

PC
PC

H_SMBALERT#
H_SMBCLK

PC
PC

H_SMBDATA

PC

H_SML0ALERT#
H_SML0CLK

PC
PC

H_SML0DATA
H_SML1ALERT#

PC
PC

H_SML1CLK
H_SML1DATA

PC

(DDR,G-Sensor)

D_

UH1E

AW4

GP

AY2

GP

AV4

GP

BA4

GP

BD7

GP

SKL-H-PCH_BGA837

@

UH1D

BA9

_BCLK

HDA

BD8

HDA

_RST#

BE7

_SDI0

HDA

BC8

HDA

_SDI1

BB7

HDA_SDO

BD9

HDA

_SYNC

BD1

RS

VD_BD1

BE2

VD_BE2

RS

AM1

SPA_SDO

DI

AN2

SPA_SDI

DI

AM2

SPA_BCLK

DI

AL42

GP

P_D8/I2S0_S CLK

AN42

P_D7/I2S0_R XD

GP

AM43

GP

P_D6/I2S0_T XD

AJ33

P_D5/I2S0_S FRM

GP

AH44

GP

P_D20/DMIC _DATA0

AJ35

P_D19/DMIC _CLK0

GP

AJ38

P_D18/DMIC _DATA1

GP

AJ42

GP

P_D17/DMIC _CLK1

BC10

RT

CRST#

BB10

SR

TCRST#

AW11

PC

H_PWROK

BA11

MRST#

RS

AV11

W_PWROK

DS

BB41

GP

P_C2/SMBA LERT#

AW44

P_C0/SMBC LK

GP

BB43

GP

P_C1/SMBD ATA

BA40

GP

P_C5/SML0 ALERT#

AY44

P_C3/SML0 CLK

GP

BB39

GP

P_C4/SML0 DATA

AT27

P_B23/SML 1ALERT#/PCHHOT #

GP

AW42

GP

P_C6/SML1 CLK

AW45

P_C7/SML1 DATA

GP

SKL-H-PCH_BGA837

@

CK_SCLK <14,15,38>

D_

CK_SDATA <14,15,38>

(EC, VGA)

EC

_SMB_CK2 <23,33,39>

_SMB_DA2 <23,33,39>

EC

P_I0/DDPB_ HPD0
P_I1/DDPC_ HPD1
P_I2/DDPD_ HPD2
P_I3/DDPE_ HPD3

P_I4/EDP_H PD

REV = 1.3

REV = 1.3

C

-H_PCH

SPT

DIO

AU

Se

Se

Se

curity Classification

curity Classification

curity Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

GP

P_I7/DDPC_ CTRLCLK

GP

P_I8/DDPC_ CTRLDATA

P_I5/DDPB_ CTRLCLK

GP

GP

P_I6/DDPB_ CTRLDATA

P_I9/DDPD_ CTRLCLK

GP

GP

P_I10/DDPD _CTRLDATA

5

OF 12

-H_PCH

SPT

P_A12/BMB USY#/ISH_GP6/SX_EXIT _HOLDOFF#

GP

GP

SM

BUS

AG

JT

4

OF 12

C

BB3
BD6
BA5
BC4
BE5
BE6

Y44

P_F14

GP

V44

P_F23

GP

W39

GP

P_F22

L43

GP

P_G23

L44

P_G22

GP

U35

GP

P_G21

R35

P_G20

GP

BD36

GP

P_H23

?

BB17

M_RESET#

P_B1

GP
GP

P_B0

P_B11

GP

S_PWROK

WA

KE#

D6/SLP_A#

SL

P_LAN#

D4/SLP_S3#
D5/SLP_S4#

SL

P_SUS#

S_RESET#

P_B14/SPKR

OCPWRGD

P_PMODE

IT

JT

AGX

AG_TMS

JT
JT

AG_TDO

AG_TDI

JT

AG_TCK

JT

?

Co

Co

Co

mpal Secret Data

mpal Secret Data

mpal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

AW22

AR15

AV13

BC14
BD23
AL27
AR27
N44
AN24
AY1

BC13
BC15
AV15
BC26
AW15
BD15
BA13

AN15
BD13
BB19
BD19

BD11
BB15
BB13
AT13
AW1
BD26
AM3

AT2
AR3
AR2
AP1
AP2
AN3

H_

GP

P_A8/CLKR UN#

GP

D11/LANPH YPC

GPD9/SLP_W LAN#

DRA

GP

P_B2/VRAL ERT#

P_G17/ADR_ COMPLETE

GP

SY

GP

P_B12/SLP_ S0#

GP

GP
GP

D10/SLP_S5 #

GP

GPD8/SUSC LK

GP

D0/BATLOW #

P_A15/SUS ACK#

P_A13/SUS WARN#/SUSPW RDNACK

GP

GP

D2/LAN_W AKE#

D1/ACPRE SENT

GP

D3/PWRB TN#

GP

SY

GP

PR

Func

tional Strap Definitions

BALERT# / GPP_C 2

SM
int. PD
0 = Disable Intel ME (TLS) (Default)
1 = Enable Intel ME (TLS)

SML0ALERT# / GPP_C5
int. PD
0 = LPC Is selected for EC. (Default)
1 = eSPI Is selected for EC.

SM

L1ALERT# / PCHHOT# / GPP_B23

int. PD

SPK

R / GPP_B14
int. PD
0 = Disable Top Swap mode. (Default)
1 = Enable Top Swap mode.

_SDO

HDA
int. PD
0 = Enable security measures defined in the Flash
Descriptor. (Default)
1 = Disable Flash Descriptor Security (override).

2016/11/03 2017/01/10

2016/11/03 2017/01/10

2016/11/03 2017/01/10

H_

PM

_CLKRUN#

SLP_WLAN#

DRAMRST#

DDR_
PC

H_VRALERT#

PEC_3A_1P5A#

TY
LA

N_GPO

S_PWROK

SY

WA

KE#
_SLP_A#

PM
SL

P_LAN#

_SLP_S0#_R

PM
PM

_SLP_S3#
_SLP_S4#

PM

_SLP_S5#

PM

SCLK

SU
PM

_BATLOW#

RH6

LA

N_WAKE#

_PRESENT_R

AC
PM

_SLP_SUS#

N_OUT#_R

PBT
SY

S_RESET#

H_SPKR

PC

CPUPWRGD

P_ITP_PMODE

XD
CP

U_XDP_TCK0
U_XDP_TMS

CP
CP

U_XDP_TDO
U_XDP_TDI

CP

H_JTAG_TCK1

PC

D

SKTOCC# <9>

PAD

PAD
PAD

PAD

1 2

@

2 0_0402_5%

PAD

D

PM

@

DDR_

TY

PEC_3A_1P5A# <36>

LA

N_GPO <32>

SY

S_PWROK <39,43>

@
@

PM
PM

@

SCLK <34,37>

SU

@

PC

H_SPKR <40>

H_

CPUPWRGD <9>

@

PAD

CP

U_XDP_TCK0 <6,9>

CP

U_XDP_TMS <6,9>
U_XDP_TDO <6,9>

CP

U_XDP_TDI <6,9>

CP
PC

H_JTAG_TCK1 <6>

PM_CLKRUN#

_CLKRUN# <41>

6

T1

DRAMRST# <14>

7

T1

8

T1

_SLP_S3# <39,43>
_SLP_S4# <39,43>

1

T2

2

@

T2

PAD

SU

SPWRDNACK <39>

T2

3

6

T2

B_CTRLDATA / GPP_I6

DDP
int. PD
0 = Port B is not detected.
1 = Port B is detected. (Default)

DDPC_CTRLDATA / GPP_I8
int. PD
0 = Port C is not detected.
1 = Port C is detected. (Default)

DDPD_CTRLDATA / GPP_I10
int. PD
0 = Port D is not detected. (Default)
1 = Port D is detected.

Ti

Ti

Ti

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Cu

Cu

Cu

Date: Sheet of

Date: Sheet of

Date: Sheet of

PC

PBTN_OUT#_R

PBT

AC

PM

PM

PM_SLP_S0#_R

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

tle

tle

tle

PC

PC

PC

stom

stom

stom

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

E

8.2K

CRB

1 2

RH4

8 10K_0402_5%

H_VRALERT#

_PRESENT_R

SY

SY

RH5

2 10K_0402_5%@

RH5

3 100K_0402_5%

5

@

RH5

N_OUT#_R

_SLP_S3#

_SLP_S4#

S_PWROK

S_RESET#

H(3/7)GPIO,SMBUS

H(3/7)GPIO,SMBUS

H(3/7)GPIO,SMBUS

0_0402_5%

1 2

9

@

RH5

0_0402_5%

1 2

PAD

PAD

66

RH1

0_0402_5%

1 2

@

1 2

1 10K_0402_5%

RH6

1 2

1 .1U_0402_16V7K

CH6

XEMC@

1 2

CH22
.1U_0402_16 V7K

XEMC@

E

+3

VALW_PCH_PRIM

12

+3

12

AC

@

T1

T2

@

18 64Tuesday, April 11, 2017

18 64Tuesday, April 11, 2017

18 64Tuesday, April 11, 2017

+3

VS

VALW_DSW

PBT

N_OUT# <39>

_PRESENT <39>

9

0

_SLP_S0# <39>

PM

1A

1A

1A

A

1

1B Modify

1

1 2

64

RH1

1 2

65

RH1

18P_0402_50V8J

CH2

5

EMC@

EMC@

AL24_OUT

XT

33_0402_1%

XT

AL24_IN

33_0402_1%

24M X'tal

1 2

2 1M_0402_5%

RH7

YH

2

1 1

24MHZ_18PF_XRCGB24M000F2P51R0

3

33P_0402_50V8J

3

NC

NC

CH2

4

2

4

B

C

D

E

1B Modify

RTC X'tal

RT

CX1

1 2

1 10M_0402_5%

RH7

YH

1

1 2

32.768KHZ_9PF_CM7V-T1A9.0PF20PPM

8.2P_0402_50V8D

1

CH2

6

2 2

Follow
10/13 Dan
CHECK NEEDED IF UNUSE?

3 3

4 4

2

PDG 0.71Table 52-17

+3VS

+3VS

0

RPH1

10K_0804_8P4R_5%

1

RPH1

@

10K_0804_8P4R_5%

RPH1

2

@

10K_0804_8P4R_5%

3

RPH1

@

10K_0804_8P4R_5%

12

RH6
10K_0402_5%@

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

CX2

RT

8.2P_0402_50V8D

1

CH2

7

2

8

KREQ_PCIE#3

CL

N_CLKREQ#

LA
VG

A_CLKREQ#

WL

AN_CLKREQ#

NG

FF_CLKREQ#

CL

KREQ_PCIE#12

CL

KREQ_PCIE#7

CL

KREQ_PCIE#10

CLKREQ_PCIE#5

CL

KREQ_PCIE#9

CL

KREQ_PCIE#8

CL

KREQ_PCIE#6

CL

KREQ_PCIE#13

KREQ_PCIE#14

CL

KREQ_PCIE#11

CL

KREQ_PCIE#15

CL

A_CLKREQ# <23>

VG

0VALW_VCCCLK5

+1.

CPU_
CPU_

CPU_
CPU_

24M<9>
24M#<9>

BCLK<9>
BCLK#<9>

XT
XT

N_CLKREQ#<32>

LA

AN_CLKREQ#<37>

WL

NG

AL24_OUT
AL24_IN

RH67

2.7K_0402_1%

FF_CLKREQ#<34>

12

XCL

K_BIASREF

CX1

RT

CX2

RT

A_CLKREQ#

VG

N_CLKREQ#

LA
WL

AN_CLKREQ#

CL

KREQ_PCIE#3

NG

FF_CLKREQ#

CL

KREQ_PCIE#5
KREQ_PCIE#6

CL

KREQ_PCIE#7

CL

KREQ_PCIE#8

CL
CL

KREQ_PCIE#9

CL

KREQ_PCIE#10

CL

KREQ_PCIE#11

CL

KREQ_PCIE#12
KREQ_PCIE#13

CL

KREQ_PCIE#14

CL

KREQ_PCIE#15

CL

AR17

BC9

BD10

BC24

AW24

AT24
BD25
BB24
BE25

AT33
AR31
BD32
BC32
BB31
BC33
BA33

AW33

BB33
BD33

R13
R11

G1

F1

G2
H2

A5
A6

E1

P1
R2

W7

Y5

U2
U3

UH1G

P_A16/CLKOUT_48

GP

CL

KOUT_CPUNSSC_P
KOUT_CPUNSSC_N

CL

CL

KOUT_CPUBCLK_P

CL

KOUT_CPUBCLK_N

AL24_OUT

XT
XT

AL24_IN

LK_BIASREF

XC

RT

CX1

RTCX2

GP

P_B5/SRCCLKREQ0#

GP

P_B6/SRCCLKREQ1#
P_B7/SRCCLKREQ2#

GP

P_B8/SRCCLKREQ3#

GP
GP

P_B9/SRCCLKREQ4#

GP

P_B10/SRCCLKREQ5#
P_H0/SRCCLKREQ6#

GP

P_H1/SRCCLKREQ7#

GP
GP

P_H2/SRCCLKREQ8#

GP

P_H3/SRCCLKREQ9#
P_H4/SRCCLKREQ10#

GP

P_H5/SRCCLKREQ11#

GP
GP

P_H6/SRCCLKREQ12#

GP

P_H7/SRCCLKREQ13#
P_H8/SRCCLKREQ14#

GP
GP

P_H9/SRCCLKREQ15#

CLKOUT_PCIE_N15

KOUT_PCIE_P15

CL

CL

KOUT_PCIE_N14
KOUT_PCIE_P14

CL

CL

KOUT_PCIE_N13

CL

KOUT_PCIE_P13

KOUT_PCIE_N12

CL
CL

KOUT_PCIE_P12

SKL-H-PCH_BGA837

REV = 1.3

@

SPT

-H_PCH

K_CPU_ITP#

CL

7

OF 12

CL

KOUT_ITPXDP_N

KOUT_ITPXDP_P

CL

KOUT_CPUPCIBCLK_N

CL

CL

KOUT_CPUPCIBCLK_P

KOUT_PCIE_N0

CL
CL

KOUT_PCIE_P0

KOUT_PCIE_N1

CL

KOUT_PCIE_P1

CL

CLKOUT_PCIE_N2

KOUT_PCIE_P2

CL

CL

KOUT_PCIE_N3

KOUT_PCIE_P3

CL

CL

KOUT_PCIE_N4

CL

KOUT_PCIE_P4

KOUT_PCIE_N5

CL
CL

KOUT_PCIE_P5

KOUT_PCIE_N6

CL

KOUT_PCIE_P6

CL

CL

KOUT_PCIE_N7

KOUT_PCIE_P7

CL

CL

KOUT_PCIE_N8

CLKOUT_PCIE_P8

KOUT_PCIE_N9

CL
CL

KOUT_PCIE_P9

KOUT_PCIE_N10

CL

CL

KOUT_PCIE_P10

KOUT_PCIE_N11

CL

KOUT_PCIE_P11

CL

?

L1
L2
J1
J2

N7
N8

L7
L5

D3
F2

E5
G4

D5
E6

D8
D7

R8
R7

U5
U7

W10
W11

N3
N2

P3
P2

R3
R4

CL

K_CPU_ITP

CPU_

PCIBCLK#

CPU_

PCIBCLK

K_PEG_VGA#

CL

K_PEG_VGA

CL

CL

K_PCIE_LAN#

CL

K_PCIE_LAN

CLK_PCIE_WLAN#

K_PCIE_WLAN

CL

CL

K_PCIE_NGFF#

CL

K_PCIE_NGFF

PAD

T28

@

PAD

T29

@

CPU_

PCIBCLK# <9>

CPU_

PCIBCLK <9>

K_PEG_VGA# <23>

CL

K_PEG_VGA <2 3>

CL

K_PCIE_LAN# <32>

CL

CL

K_PCIE_LAN <32>

CL

K_PCIE_WLAN# <37>

CL

K_PCIE_WLAN <37>

CL

K_PCIE_NGFF# <34>

CL

K_PCIE_NGFF <34>

DGPU

GLAN

NGFF

M2 SSD

WL+BT(KEY E)

Security Clas sification

Security Clas sification

Security Clas sification

2016/11/03 2017/01/10

2016/11/03 2017/01/10

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2016/11/03 2017/01/10

C

mpal Secret Data

mpal Secret Data

mpal Secret Data

Co

Co

Co

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

tle

tle

tle

Ti

Ti

Ti

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

stom

stom

stom

Cu

Cu

Cu

Date: Sheet

Date: Sheet

D

Date: Sheet

H(4/7)CLK

H(4/7)CLK

H(4/7)CLK

PC

PC

PC

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

E

1A

1A

1A

19 64Tuesday, April 11, 2017

19 64Tuesday, April 11, 2017

19 64Tuesday, April 11, 2017

of

of

of

A

Func

tional Strap Definitions

GSPI1_MOSI / GPP_B22
int. PD
Boot BIOS Destination
0 = SPI (Default)
1 = LPC

1 1

2 2

OSI / GPP_B18

GSPI0_M
int. PD
0 = Disable No Reboot mode. (Default)
1 = Enable No Reboot mode (PCH will disable the TCO
Timer system reboot feature).

+3VS

RH1

+3VS

3 49.9K_0402_1%

RH7

4 49.9K_0402_1%

RH7

RH7

6 49.9K_0402_1%@

RH7

5 49.9K_0402_1%@

4 10K_0402_5%@

12

12

12

12

PC

H internal PU 20K

12

UART

UART

UART

UART

B

EC_

SCI#

_2_CRXD_DTXD

_2_CTXD_DRXD

_2_CCTS_DRTS

_2_CRTS_DCTS

EC_

SCI# <39>

DG

PU_AC_DETECT<23,39>

ouch PAD>

<T

UART

UART

C

-H_PCH

UH1K

AT29

P_B22/GSPI1_MOSI

GP

AR29

GP

EC_

SCI#

6_FB_EN

GC

AC_DET

1 2

RH7

7

0_0402_5%

DG

PU_HOLD_RST#<23>
DG

PU_PWR_EN<23,27>

_2_CTXD_DRXD<37>
_2_CRXD_DTXD<37>

I2

C_1 _SCL<41>

I2

C_1 _SDA<41>

PCH_

@

U_EVENT_R#

GP

DG

PU_HOLD_RST#
PU_PWR_EN

DG

_2_CCTS_DRTS

UART
UART

_2_CRTS_DCTS

UART

_2_CTXD_DRXD

UART

_2_CRXD_DTXD

I2C_ 1_SCL

C_1 _SDA

I2

PCH_

@

PAD

T37

GPP_D4

P_B21/GSPI1_MISO

AV29

GP

P_B20/GSPI1_CLK

BC27

P_B19/GSPI1_CS#

GP

BD28

GP

P_B18/GSPI0_MOSI

BD27

GPP_B17/GSPI0_MISO

AW27

P_B16/GSPI0_CLK

GP

AR24

GP

P_B15/GSPI0_CS#

AV44

P_C9/UART0_TXD

GP

BA41

P_C8/UART0_RXD

GP

AU44

GP

P_C11/UART0_CTS#

AV43

GP

P_C10/UART0_RTS#

AU41

P_C15/UART1_CTS#/ISH_UART1_CTS#

GP

AT44

GP

P_C14/UART1_RTS#/ISH_UART1_RTS#

AT43

GP

P_C13/UART1_TXD/ISH_UART1_TXD

AU43

P_C12/UART1_RXD/ISH_UART1_RXD

GP

AN43

GP

P_C23/UART2_CTS#

AN44

GP

P_C22/UART2_RTS#

AR39

P_C21/UART2_TXD

GP

AR45

P_C20/UART2_RXD

GP

AR41

GPP_C19/I2C1_SCL

AR44

P_C18/I2C1_SDA

GP

AR38

GP

P_C17/I2C0_SCL

AT42

GP

P_C16/I2C0_SDA

AM44

P_D4/ISH_I2C2_SDA/ISH_I2C3_SDA

GP

AJ44

P_D23/ISH_I2C2_SCL/ISH_I2C3_SCL

GP

SKL-H-PCH_BGA837

REV = 1.3

@

SPT

GP

GP

P_D13/ISH_UART0_RXD/SML0BDATA/I2C2_SDA

D

GP

P_D9

GP

P_D10
P_D11

GP

P_D12

GP

GPP_D16/ISH_UART0_CTS#

P_D15/ISH_UART0_RTS#

P_D14/ISH_UART0_TXD/SML0BCLK/I2C2_SCL

GP

P_H20/ISH_I2C0_SCL

GP
GP

P_H19/ISH_I2C0_SDA

P_H22/ISH_I2C1_SCL

GP

P_H21/ISH_I2C1_SDA

GP

P_A23/ISH_GP5

GP
GP

P_A22/ISH_GP4

GPP_A21/ISH_GP3

P_A20/ISH_GP2

GP
GP

P_A19/ISH_GP1

GP

P_A18/ISH_GP0
P_A17/ISH_GP7

GP

OF 12

11

E

VG

A_ID1

AL44

VG

A_ID2

AL36

JECT_ID0

PRO

AL35

JECT_ID1

PRO

AJ39

AJ43
AL43
AK44

SUB_

DET

AK45

BC38
BB38

BD38
BE39

BC22
BD18
BE21
BD22
BD21
BB22
BC19

?

PAD
PAD

PAD
PAD

PAD
PAD

PAD

SUB_

DET <33>

T30

@

T31

@

T32

@

T33

@

T34

@

T35

@

INT

G_

T36

@

_PCH_PRIM

A_ID1

_PCH_PRIM

+3VALW

1 2

RH8

0 2.2K_0402_5%

1 2

1 2.2K_0402_5%

RH8

3 3

+3VS

3 10K_0402_5%VGA@

RH8

RH8

5 10K_0402_5%VGA@

<Touch PAD/PNL>

12

12

I2

C_1 _SCL

I2

C_1 _SDA

DG

PU_PWR_EN

PU_HOLD_RST#

DG

VG

VG

A_ID2

VGA ID

1 2

G1@

RH8

8

1 2

G0@

RH9

0 10K_0402_5%

1 2

@

2

RH9

1 2

RH9

4 10K_0402_5%VGA@

VGA_ID2 VGA_ID1
GPP_D10 GPP_D9

N17P-G0

U_EVENT#

U_EVENT#<23>

D GPU

TO

4 4

GP

GC

6_FB_EN3V3<23>

A

GP

GC

6_FB_EN3V3

1 2

RH8

6

1 2

RH8

7

@

@

0_0402_5%

0_0402_5%

U_EVENT_R#

GP

GC

6_FB_EN

B

N17P-G1
N17E-G1

served

Re

Security Clas sification

Security Clas sification

Security Clas sification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VALW

1K

_0402_1%

_0402_1%

1K

00

0

1

*

01
11

mpal Secret Data

mpal Secret Data

mpal Secret Data

Co

Co

2016/11/03 2017/01/10

2016/11/03 2017/01/10

2016/11/03 2017/01/10

C

Co

Deciphered Date

Deciphered Date

Deciphered Date

JECT_ID0

PRO

PRO

JECT_ID1

Pr

oject ID

C5MMH
C5PRH
Reserved

served

Re

1 2

@

RH8

9

1 2

RH9

1 10K_0402_5%

1 2

@

3

RH9

1 2

RH9

5 10K_0402_5%

00
0
1
11

D

1K

_0402_1%

_0402_1%

1K

_PCH_PRIM

+3VALW

+3VS

RH8

2

@

10K_0402_5%

1 2

G_

INT

Project_ID0Project_ID1

GP

P_D11GPP_D12

@

100K_0402_5%

1 2

RH8

G_

INT <38>

4

1
0

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

tle

tle

tle

Ti

Ti

Ti

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

stom

stom

stom

Cu

Cu

Cu

Date: Sheet

Date: Sheet

Date: Sheet

H(5/7)UART,I2C,GPIO

H(5/7)UART,I2C,GPIO

H(5/7)UART,I2C,GPIO

PC

PC

PC

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

E

20 64Tuesday, April 11, 2017

20 64Tuesday, April 11, 2017

20 64Tuesday, April 11, 2017

of

of

of

1A

1A

1A

A

1.0 Modify

.0VALW

+1

1 1

RH9

JU

MP_43X118

8

2

JC

1 2

@

RH101 for Deep SX

.0VALW_PCH

+1

2 2

1 2

@

RH1

01

RH1

@

1 2

0_0603_5%

1

LH

FBMA-L11-160808-800LMT_0603

1 2

+1

12

+1

0_0805_5%@

+1

0_0402_5%

+1

03

CH30

22U_0603_6.3V6M

.0VALW_PRIM

.0VALW_PCH

.0VALW_DCPDSW

Near PIN
BA29

1

CH28
1U_0402_6.3V6K

2

.0VALW_VCCCLK

1

2

+1

22U_0603_6.3V6M

CH3

1

1

2

.0VALW_VCCCLK5

Near PIN
K2,K3

1

CH32
1U_0402_6.3V6K

2

@

modify follow PDG 05/18

+1

.0VALW_MPHY

RH1

1 2

@

0_0603_5%

USE MPHYGT ON H

NO
CHANGE TO +1.0VALW_MPHY

1 2

LH

3 3

4 4

2

FBMA-L11-160808-800LMT_0603

1 2

LH3

FBMA-L11-160808-800LMT_0603

1 2

@

06 0_0402_5%

RH1

1 2

@

07 0_0402_5%

RH1

+1

04

CH3

22U_0603_6.3V6M

Near

PIN

U21,U23,U25,U26,V26

CH4

22U_0603_6.3V6M

.0VALW_AUSB_AZP LL

+1

CH5

22U_0603_6.3V6M

.0VALW_PRIMAL22

+1

.0VALW_PRIMAD15

+1

1

9

2

1

7

2

1

3

2

2

1

modify follow PDG 05/18

1U_0402_6.3V6K

CH4

1

1

0

2

2

+1

.0VALW_AMPHYPLL

22U_0603_6.3V6M

CH4

1

8

2

Near PIN
AJ5,AL5

1

CH5

4

22U_0603_6.3V6M

2

EMC@

1

CH7
1000P_0402_50V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

CH4

1

1

2

Near PIN V28
Near PIN AC17

Near PIN
A42,A43,B43

1

CH4

9

1U_0402_6.3V6K

2

@

CH4

2

.0VALW_AUSB_AZP LL

Sensitive net cap for AD15

A

B

+1

.0VALW_PRIM

+1

.0VALW_DCPDSW

.0VALW_VCCCLK

+1

+1

.0VALW_VCCCLK5

.0VALW_MPHY

+1

+1.0VALW_AMPHYPLL

+1

.0VALW_MPHY

VALW_HDA

+3
+3

VALW_DSW

Near PIN W15
Add 05/18

VCCMPHY power defined by HSIO lane qty.

Modify

1.0

+1.0VALW_MPHY +1.0VALW_MPHY

2

EMC@

CH69
1000P_0402_50V7K

1

Sensitive net cap for V28,AC171.0 Modify

B

2.899A

0.0454A

0.021A

0.050A

0.024A

0.137A

0.006A

1.307A

0.110A

0.030A

0.533A

0.012A

0.033A

0.075A

1

CH4

4

1U_0402_6.3V6K

2

2

CH70
1000P_0402_50V7K

1

PCH_EDS Table10-4
12/30 J

AA23
AA26
AA28
AC23
AC26
AC28
AE23
AE26

Y23
Y25

BA29

N17
R19
U20
V17
R17

K2
K3

U21
U23
U25
U26
V26
A43
B43
C44
C45
V28

AC17

AJ5
AL5

AN19

BA15

W15

EMC@

UH1H

CPRIM_1P0

VC
VCCPRIM_1P0
VCCPRIM_1P0
VC

CPRIM_1P0

VC

CPRIM_1P0

VC

CPRIM_1P0
CPRIM_1P0

VC

CPRIM_1P0

VC
VCCPRIM_1P0
VCCPRIM_1P0
DCP

DSW_1P0

VC

CCLK1
CCLK3

VC

CCLK4

VC
VCCCLK2
VC

CCLK2

VC

CCLK5

VC

CCLK5

VCCMPHY_1P0
VCCMPHY_1P0
VC

CMPHY_1P0

VC

CMPHY_1P0

VC

CMPHY_1P0
CMPHYPLL_1P0

VC

CMPHYPLL_1P0

VC
VCCPCIE3PLL_1P0
VCCPCIE3PLL_1P0
VC

CAPLLEBB_1P0

VC

CPRIM_1P0

VC

CUSB2PLL_1P0
CUSB2PLL_1P0

VC

CHDAPLL_1P0

VC

VC

CHDA

VC

CDSW_3P3

SKL-H-PCH_BGA837

RE

@

V = 1.3

SPT

-H_PCH

CORE

MPHY

USB

+3

C

VC
CGPIO

VC

8 OF 12

VALW_PCH_PRIM

+3

1

@

2

VALW_PCH_PRIM

22U_0603_6.3V6M

1

@

2

C

D

+3

VALW

RH9

1 2

7

1.0 Modify

1 2

9

RH9

1 2

00

RH1

+3VALW_PCH_PRIM +3VALW_SPI

1 2

RH1

02

AL22

RTC

CSPI

?

BA24
BA31

BC42
BD40
AJ41
AL41
AD41
AN5

AD15
AD13
BA20
BA22
BA26

AJ20
AJ21
AJ23
AJ25

BE41
BE43
BE42
BC44
BA45
BC45
BB45

BD3
BE3
BE4

.0VALW_PRIM

+1

1

@

2

+1

.0VALW_PRIM

22U_0603_6.3V6M

1

@

2

0.0908A

0.195A

0.082A

0.2726A

0.1410A

0.1318A

0.2875A

0.0061A

0.007A

0.0002A

0.029A

0.078A

0.117A

1U_0402_6.3V6K

CH5

2

CH5

1

6

@

2

VCCPRIM_1P0

VC

CDSW_3P3

VC

CPGPPA

CPGPPBCH

VC
VCCPGPPBCH

VCCPGPPEF
VC

CPGPPEF

VC

CPGPPG

VC

CPRIM_3P3

VCCPRIM_1P0

VC

CRTCPRIM_3P3

VC
DCP

VCCPRIM_1P0
VCCPRIM_1P0
VC

CPRIM_1P0

VC

CPRIM_1P0

VC
VCCSPI
VCCSPI

VC

CPGPPD

VC

CPGPPD

VC

CPGPPD
CPGPPD

VC

VCCPRIM_3P3
VC

CPRIM_3P3

VC

CPRIM_3P3

1U_0402_6.3V6K

CH5

1

22U_0603_6.3V6M

CH5

CH5

1

5

7

@

2

CATS

CRTC

+3

VALW_DSW

0_0603_5%@

VALW_PCH_PRIM

+3

0_0805_5%@

+3

@

CH5

8

0_0603_5%

0_0603_5%

VALW_HDA

1

CH6

2

+1

.0VALW_PRIMAL22

+3

VALW_DSW
VALW_PCH_PRIM

+3

+1

.0VALW_PRIMAD15

+3

VS_VCCATS

+3

VALW_PCH_PRIM

+R

TCVCC

CH340.

.0VALW_PRIM

+1

VALW_SPI

+3

+3

VALW_PCH_PRIM

VALW_PCH_PRIM

+3

6

0.

1U_0201_10V6K

1 2

1U_0201_10V6K

RT

0.1U_0201_10V6K

Near PIN BA26

C Battery

CH60

@

22U_0603_6.3V6M

Power Rail Volt age

T54C(V F)

3.383V( MAX)

240 mV

3.143V

+R

TCBATT

+CHGRTC

BA

+3VL_RTC

Result : Pass

curity Classification

curity Classificat ion

curity Classificat ion

Se

Se

Se

Is

Is

Is

sued Date

sued Date

sued Date

S SHEE T OF ENGINEERI NG DR AWING IS THE PROPRIE TARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

S SHEE T OF ENGINEERI NG DR AWING IS THE PROPRIE TARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

S SHEE T OF ENGINEERI NG DR AWING IS THE PROPRIE TARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THI

THI

THI
AND TRADE SECRET INFORM ATION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORM ATION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORM ATION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/

2016/

2016/

01/29 2017/01/10

01/29 2017/01/10

01/29 2017/01/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Dat e

Deciphered Dat e

D

+3

+RTCVCC

1

1

2

2

JRTC1

1

1

2

2

3

GN

D

4

GN

D

ACES_50271-0020N-001

CONN@

02000RO00

SP

VALW_PCH_PRIM

VS

+3

RH1

CH5

9

1U_0402_6.3V6K

1 2

CH2

9 1U_040 2_6.3V6K

@

1 2

3 1U_040 2_6.3V6K

CH3

@

1 2

5

CH3

1 2

CH3

6 1U_040 2_6.3V6K

1 2

CH3

7

1 2

8

CH3

1 2

CH43 0. 1U_0201_10V6K

1 2

CH4

5

1 2

CH46 1U_04 02_6.3V6K

@

1 2

05 0_0402_5%

BAV70W_SOT323-3

2

1

3

RH163 10K_0402_5%

DH3

W

=20mils

:

PN
SC600000B00

Near PIN BA22
09/26 dan

E

Near PIN BD3,BE3,BE4

Near

PIN BA20

1U_0201_10V6K

0.

Near PIN AN5

No requirment
Near PIN BC44

0.

1U_0201_10V6K

Near PIN BC42,BD40

1U_0201_10V6K

0.

Near PIN AJ41 , AL41

Near PIN AD41

0.

1U_0201_10V6K

Near PIN BA20

VS_VCCATS

+3

0 1U_0402_6. 3V6K

1 2

CH5

@

Near PIN
AD13

+C

HGRTC

1 2

Ti

Ti

Ti

tle

tle

tle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

stom

stom

stom

Cu

Cu

Cu

Date: Sheet

Date: Sheet

Date: Sheet

+R

TCBATT

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

H(6/7)POWER

H(6/7)POWER

H(6/7)POWER

PC

PC

PC

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

E

21 64Tuesday, April 11, 2017

21 64Tuesday, April 11, 2017

21 64Tuesday, April 11, 2017

of

of

of

1A

1A

1A