Acer Aspire AO722 Schematic

A

Dr-Bios.com

B

C

D

E

ZZZ0

ZZZ1

ZZZ2

ZZZ3

ZZZ4

ZZZ5

PCB DAZ0I200101

MB DA60000KP10

LA-7071P

PCB

M/B

DAZ@

1 1

LA-7071P

M/B

DA@

LS-7071P

USB IO/B

DA@

LS-7074P

HDD/B

DA@

LS-7075P

LED/B

DA@

LA-7076P

TP/B

DA@

USB IO/B DA60000KQ10 HDD/B DA400011R10 LED/B DA400011T10 TP/B DA400013910

Compal Confidential

2 2

P1VE6 LA7071P Schematics Document

AMD Ontario Processor with DDRIII + Hudson M1

11.6" M/B

3 3

2011-03-17

Rev : 1.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

A

B

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/11/09 2012/11/09

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

P1VE6 Schematics

1 37Thursday, March 17, 2011

E

1.0

A

Dr-Bios.com

Compal Confidential

B

C

D

E

Model Name : P1VE6

Brazos Platform

File Name : LA-7071P

1 1

HDMI

RGB

LVDS

HDMI Conn.

Page 10

2 2

Fan Circuit

PWM

D-Sub Conn.

Page 11

Page 27

LVDS Conn.

Page 9

PCI-Express X3

100MHz

Port 1

WWAN

JMINI1

Media processor Wireless Card

Port 1

Page 20

3 3

WLAN

JMINI2

Port 3 Port 2

Page 21

PCIE Gen1 2.5GT/S

Port 2Port 3

LAN(10/100)

AR8158

Page 18

RJ-45

Page 18

AMD

Ontario FT1

APU

BGA 413-Ball

19mm X 19mm

UMI x4 Gen.1

2.5GT/s per Lane

AMD

Hudson M1

FCH

BGA 605-Ball

23mm X 23mm

Page 12 ~ 16

LPC

33MHz

ENE KB930

Page 26

Page 4,5,6

Memory Bus (DDRIII)

Dual Channel

1.5V DDRIII 800/1066

6.4G/8.5G

100M/133M

USB Conn.x2

(Left Side) Port 0 , 1

USB

HD Audio

SATA

Gen1 1.5GT/S ,Gen2 3GT/S

USB Conn.x1

(Right Side) Port 2

IO/B Page 20 Page 19

3.3V 48MHz

3.3V 24MHz

HDD

Small Board

204 Pin DDRIII SO-DIMM x2

BANK 0, 1, 2, 3

Camera Bluetooth

Port 5

Page 25

100MHz

(2.5")

Port 0

Page 22

Page 9

Page 7 , 8

Port 7

Card Reader

RTS 5138

Port 6

3G Card

Port 3, 9

Page 20

SIM Card

Port 4

Page 20

WLAN

Port 8

Page 21

Deciphered Date

HDD/B

LS-7074P

TP BTN/B

LS-7073P

D

HDA Codec+AMP

CX20584

HP Jack x1 MIC Jack x1

IO/B

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

Compal Electronics, Inc.

Block Diagrams

P1VE6 Schematics

Page 17

2 37Thursday, March 17, 2011

E

IO/B

LS-7071P

RTC Ckt.

Page 12

BIOS ROM

4 4

Power Button

Page 23

DC/DC Interface Ckt.

Page 28

A

B

2MB

Page 27

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

LED/B

LS-7072P

Compal Secret Data

2010/11/09 2012/11/09

Compal Secret Data

1.0

E

Dr-Bios.com

NC

WWAN

LANRight conn

WLAN

D

FCH Hudson-M1 SATA Port List

SATA0

SATA1

SATA2

SATA3

SATA4

SATA5

HDD

NC

A

B

Voltage Rails

Power Plane Description

VIN

B+

+APU_CORE

1 1

2 2

+APU_CORE_NB 1.0V switched power rail ON OFF

+1.5V

+0.75VS 0.75VS switched power rail for DDR terminator

+1.05VS

+1.1VS 1.1VS switched power rail ON OFF OFF

+1.8VS 1.8V switched power rail

+3VALW

+3VS

+1.5VS 1.5VS switched power rail ON OFF OFF

+5VALW

+5VS

+VSB VSB always on power rail ON ON*

+RTCBATT

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

EC SM Bus1 address

Device

Smart Battery

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU (0.7-1.2V)

1.5V power rail for CPU VDDIO and DDRIII

1.05V switched power rail for NB VDDC & VGA

3.3V always on power rail

3.3V switched power rail

5V always on power rail

5V switched power rail

RTC power

EC SM Bus2 address

Address Address

0001-011xb

HEX

16H

Device

SB-TSI

S1 S3 S5

N/A N/A N/A

ON OFF

ON

ON OFF OFF

ON

1001-100xb

N/AN/AN/A

OFF

ON

OFF

ON ON*

ON ON*ON+1.1VALW 1.1V always on power rail

OFF

ON ON*

OFF

OFFON

ONON

HEX

98H

C

FCH Hudson-M1 USB Port List

USB1.1

Port0

Port1

USB2.0

Port0

Port1

Port2

Port3

Port4

Port5

Port6

Port7

Port8

Port9

Port10

Port11

Port12

Port13

NC

Left conn

WWAN

SIM

USB Camera

CardReader

BT

WiMax

WWAN

NC

Brazos PCIE Port List

PCIE0

PCIE1

APUFCH

PCIE2

PCIE3

PCIE0

PCIE1

PCIE2

PCIE3

SM Bus Controller 0

Device Address

APU SIC/SID (FCH_SMB3)

H_THERMTRIP# (FCH_ALERT#)

3 3

SM Bus Controller 1

Device Address HEX

DDR DIMM1 (FCH_SMB0)

(FCH_SMB1 ~ FCH_SMB4, SMB_AL ERT#)

HEX

(FCH_SMB0)

1001-000xb

90

Board ID / SKU ID Table for AD channel

Vcc +3VALW

Board ID

0

*

1 2 3 4 5 6 7 NC

100K +/- 5%Ra

Rb V min

AD_BID

0

8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

0 V

V typ

AD_BID

V

AD_BID

0 V 0 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

2.200 V

3.300 V

2.341 V

3.300 V

max

PCB Revision

0.1

0.2

SMBUS Control Table

BOM Structure

EC_SMB_CK1

HDMI@ : HDMI function BT@ : BT function CONN@ : Connetors 45@ : 45 Level

3G@ : 3G function

4 4

N3G@ : None 3G function CMBS@ : Combo Jack POPO noise Solution NCMBS@: None Combo Jack POPO noise Solution

A

B

EC_SMB_DA1

EC_SMB_CK2 EC_SMB_DA2

HDMI_DATA HDMI_CLK

EDID_DATA EDID_CLK

FCH_SMDAT0 FCH_SMCLK0

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Source BATT DIMM MINI Card LCD DDC ROM HDMI DDC ROM APU

KB930

V

KB930

APU FT1

FCH M1

Compal Secret Data

2010/11/09 2012/11/09

Compal Secret Data

Deciphered Date

VV

D

V

Title

Size Document Number Rev

B

Date: Sheet of

V

Compal Electronics, Inc.

Notes List

P1VE6 Schematics

V

3 37Thursday, March 17, 2011

E

1.0

5

Dr-Bios.com

4

3

2

1

APU C50 P/N change to SA00004KD50 Tock 2010/12/30

SA00004KD50

U1B

A8

TDP1_TXP0

B8

TDP1_TXN0

B9

TDP1_TXP1

A9

TDP1_TXN1

D10

TDP1_TXP2

C10

TDP1_TXN2

A10

TDP1_TXP3

B10

TDP1_TXN3

B5

LTDP0_TXP0

A5

LTDP0_TXN0

D6

LTDP0_TXP1

C6

LTDP0_TXN1

A6

LTDP0_TXP2

B6

LTDP0_TXN2

D8

LTDP0_TXP3

C8

LTDP0_TXN3

V2

CLKIN_H

V1

CLKIN_L

D2

DISP_CLKIN_H

D1

DISP_CLKIN_L

J1

SVC

J2

SVD

P3

SIC

P4

SID

T3

RESET_L

T4

PWROK

U1

PROCHOT_L

U2

THERMTRIP_L

T2

ALERT_L

N2

TDI

N1

TDO

P1

TCK

P2

TMS

M4

TRST_L

M3

DBRDY

M1

DBREQ_L

F4

VDDCR_NB_SENSE

G1

VDDCR_CPU_SENSE

F3

VDDIO_MEM_S_SENSE

F1

VSS_SENSE

B4

RSVD_1

W11

RSVD_2

V5

RSVD_3

S IC ONTARIO CMC50AFPB22GT 1G BGA ABO!

DISPLAYPORT 1

DISPLAYPORT 0

CLK

SER

JTAG CTRL

DP MISC

VGA DAC

TEST

DP_ZVSS

DP_BLON

DP_DIGON

DP_VARY_BL

TDP1_AUXP

TDP1_AUXN

TDP1_HPD

LTDP0_AUXP LTDP0_AUXN

LTDP0_HPD

DAC_RED

DAC_REDB

DAC_GREEN

DAC_GREENB

DAC_BLUE

DAC_BLUEB

DAC_HSYNC

DAC_VSYNC

DAC_SCL

DAC_SDA

DAC_ZVSS

TEST14

TEST15 TEST16

TEST17 TEST18

TEST19

TEST25_H

TEST25_L TEST28_H

TEST28_L

TEST31

TEST33_H TEST33_L

TEST34_H TEST34_L

TEST35 TEST36

TEST37

TEST38

DMAACTIVE_L

TEST4 TEST5

TEST6

DP_ZVSS

H3

G2 H2

H1

HDMI_CLK

B2

HDMI_DATA

C2

C1

EDID_CLK

A3

EDID_DATA

B3

LTDP0_HPD

D3

C12

R12 150_0402_1%R12 150_0402_1%

D13 A12

B12 A13

B13

E1

E2

F2

D4

D12

R1 R2

R6 T5

E4 K4

L1 L2

M2 K1

K2 L5

M5 M21

J18 J19

U15 T15

H4 N5

R5

K3

T1

1 2

R15 150_0402_1%R15 150_0402_1%

1 2

R18 150_0402_1%R18 150_0402_1%

1 2

DAC_ZVSS

TEST15

TEST18 TEST19

TEST25_H

TEST_25_L

TEST31

TEST33_H TEST33_L

TEST35

TEST36 TEST37

R31 1K_0402_5%R31 1K_0402_5%

R1 150_0402_1%R1 150_0402_1%

1 2

R19 499_0402_1%R19 499_0402_1%

1 2

R20 1K_0402_5%R20 1K_0402_5%

1 2

R21 1K_0402_5%R21 1K_0402_5%

1 2

R22 1K_0402_5%R22 1K_0402_5%

1 2

R25 510_0402_1%R25 510_0402_1%

1 2

T8

PAD

C9 0.1U_0402_16V4ZC9 0.1U_0402_16V4Z

1 2

C10 0.1U_0402_16V4ZC10 0.1U_0402_16V4Z

1 2

R30 1K_0402_5%@R30 1K_0402_5%@

1 2

R386 1K_0402_5%R386 1K_0402_5%

1 2

T13

PAD

9/9 Add R386 (1k@) to +1.8VS on TEST35

9/13 Change R30 from mount to @, R386 from @ to mount (AMD Recommend)

1 2

9/17 Remove JHDT1 R40, R44, R45, R46 , Add T26~T32

9/20 Delete R41~R43

APU_PWRGD

1

C421

C421 100P_0402_50V8J

100P_0402_50V8J

2

@

Reserve C421 for APU_PWRGD Michael 2010/11/18

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/11/09 2012/11/09

Compal Secret Data

Deciphered Date

AMD Debug

2

T29

PAD

T30

PAD

APU_ENBKL <26> APU_ENVDD <9>

APU_BLPWM <9>

HDMI_CLK <10>

HDMI_DATA <10>

HDMI_DET <10>

EDID_CLK <9>

EDID_DATA <9>

DAC_RED <11>

DAC_GRN <11>

DAC_BLU <11>

CRT_HSYNC <11>

CRT_VSYNC <11>

CRT_DDC_CLK <11>

CRT_DDC_DATA <11>

10/01 Remove T1,T3~T7,T11,T12,T31,T32

ALLOW_STOP# <12>

+1.8VS

@

APU_TRST#

APU_TDI

APU_TMS

APU_TCK

APU_TDO

APU_PWRGD

LDT_RST#

APU_DBRDY

APU_DBREQ#

Title

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

+1.8VS

D D

R3 1K_0402_5%R3 1K_0402_5%

1 2

R4 1K_0402_5%R4 1K_0402_5%

1 2

R8 510_0402_1%R8 510_0402_1%

1 2

R6 1K_0402_5%R6 1K_0402_5%

1 2

+3VS

R10 10K_0402_5%R10 10K_0402_5%

1 2

R11 10K_0402_5%R11 10K_0402_5%

1 2

R13 1K_0402_5%R13 1K_0402_5%

1 2

R14 1K_0402_5%R14 1K_0402_5%

1 2

R16 1K_0402_5%R16 1K_0402_5%

1 2

R17 1K_0402_5%R17 1K_0402_5%

1 2

Change R10, R11 to RP1 Michael 2010/12/23

C405 100P_0402_50V8JC405 100P_0402_50V8J

1 2

APU_SVC

APU_SVD

TEST_25_L

TEST36

HDMI_DATA

HDMI_CLK

APU_PROCHOT#

APU_ALERT#_R

APU_SIC APU_SID

LDT_RST#

10/05 Add 100p(C405) on LDT_RST#

C C

APU_PROCHOT#

@

1

C429

C429 100P_0402_50V8J

100P_0402_50V8J

2

Add C429 for APU_PROCHOT# Michael 2010/11/18

FCH_PROCHOT#<12>

EC_PROCHOT#<26>

R33

1K_0402_5%

B B

If FCH internal pull-up disab led, level-shif ter could be de leted. Need BIOS to di sable internal pull-up!!

DMN66D0LDW-7_SOT363-6

A A

DMN66D0LDW-7_SOT363-6

1K_0402_5%

APU_THERMTRIP#

@

APU_SIC

@

1

C434

C434 100P_0402_50V8J

100P_0402_50V8J

2

R23 0_0402_5%@R23 0_0402_5%@

1 2

R27 0_0402_5%R27 0_0402_5%

1 2

+3VS

12

R32

R32 10K_0402_5%

10K_0402_5%

B

2

1 2

S

Q2A

S

Q2B

Q1

E

3 1

C

MMBT3904_NL_SOT23-3

1 2

R34 0_0402_5%@R34 0_0402_5%@

+3VS

12

R39

R39 10K_0402_5%

10K_0402_5%

@

2

G

EC_SMB_DAAPU_SID

61

D

1 2

R49 0_0402_5%R49 0_0402_5%

5

G

EC_SMB_CKAPU_SIC

34

D

1 2

R52 0_0402_5%R52 0_0402_5%

5

@

1

2

@

1

2

@

1

2

APU_SVD

C433

C433 100P_0402_50V8J

100P_0402_50V8J

APU_SVC

C432

C432 100P_0402_50V8J

100P_0402_50V8J

Reserve C432, C433, C434, C435 Michael 2010/11/18

APU_SID

C435

C435 100P_0402_50V8J

100P_0402_50V8J

HDMI_TX2P<10> HDMI_TX2N<10>

HDMI_TX1P<10> HDMI_TX1N<10>

HDMI_TX0P<10> HDMI_TX0N<10>

HDMI_CLKP<10> HDMI_CLKN<10>

Power Circuit

C1 .1U_0402_16V7KC1 .1U_0402_16V7K

1 2

C6 .1U_0402_16V7KC6 .1U_0402_16V7K

1 2

C2 .1U_0402_16V7KC2 .1U_0402_16V7K

1 2

C3 .1U_0402_16V7KC3 .1U_0402_16V7K

1 2

C7 .1U_0402_16V7KC7 .1U_0402_16V7K

1 2

C8 .1U_0402_16V7KC8 .1U_0402_16V7K

1 2

C4 .1U_0402_16V7KC4 .1U_0402_16V7K

1 2

C5 .1U_0402_16V7KC5 .1U_0402_16V7K

1 2

APU_CLK<12> APU_CLK#<12>

DISP_CLK<12> DISP_CLK#<12>

APU_SVC<36>

APU_SVD<36>

LVDS_A2<9> LVDS_A2#<9>

LVDS_A1<9> LVDS_A1#<9>

LVDS_A0<9> LVDS_A0#<9>

LVDS_ACLK<9> LVDS_ACLK#<9>

9/9 Change R24 from @ to mount R26 from mount to @

9/15 Change R24 from mount to @

APU_ALERT#_FCH<14>

Connection to EC, FCH input need to pull-down

APU_PROCHOT#

Power Circuit

APU_ALERT#_EC<26>

APU_VDDNB_RUN_FB_ H<36> APU_VDD0_RUN_FB_H<36>

APU_VDD0_RUN_FB_L<36>

APU_VDDNB_RUN_FB_ L<36>

LDT_RST#<12> APU_PWRGD<12>

Close to APU

R24 0_0402_5%@R24 0_0402_5 %@

1 2

R26 0_0402_5%@R26 0_0402_5 %@

1 2

T14PADT14PAD

R379 0_0402_5%R379 0_0402_5%

R380 0_0402_5%R380 0_0402_5%

1 2

APU_TDI

APU_TDO APU_TCK

APU_TMS APU_TRST#

APU_DBRDY APU_DBREQ#

9/6 Add R379, R380 for APU_VDDNB_RUN_FB_L

H_THERMTRIP# <13>

2N7002DW-T/R7

Vgs(th): min 1.0V

If Q8 or R429, R432 implemented, EC side pull-up need to be mounted

@

1 2

R47 0_0402_5%

1 2

R48 0_0402_5%R48 0_0402_5%

8/19 Change Q2A Q2B SB00000DH00 (S TR DMN66D0LDW-7 2N SOT363-6)

@

1 2

R50 0_0402_5%

1 2

R51 0_0402_5%R51 0_0402_5%

Typ 1.6V Max 2.0V

FCH_SID

EC_SMB_DA2

FCH_SIC

EC_SMB_CK2

FCH_SID <13>

EC_SMB_DA2 <26>

FCH_SIC <13>

EC_SMB_CK2 <26>

4

T0 FCH

TO EC

T0 FCH

TO EC

HDMI_TX2P_C

HDMI_TX2N_C

HDMI_TX1P_C

HDMI_TX1N_C

HDMI_TX0P_C

HDMI_TX0N_C

HDMI_CLKP_C

HDMI_CLKN_C

APU_SIC APU_SID

APU_PROCHOT#

APU_THERMTRIP#

APU_ALERT#_R

8/31 Change U1 P/N to SA00004DF00 S IC ONTARIO ZM121034B1238 1.2G BGA 413P

R9 R352

mount

*

R28 51_0402_1%R28 51_0402_1%

R29 51_0402_1%R29 51_0402_1%

@

8/25 Pull-up 100k(@ R352) to +3VS on LTDP0_HPD for eDP

R352 100K_0402_5%@R352 100K_0402_5%@

R9 100K_0402_5%R9 100K_0402_5%

R389 0_0402_5%

Reserve R389 for eDP function Tock 2010/12/30

1 2

+1.8VS

ALLOW_STOP#

1

C438

C438 100P_0402_50V8J

100P_0402_50V8J

2

Reserve C438 for ALLOW_STOP# Michael 2010/11/18

R37 1K_0402_5%R37 1K_0402_5%

R38 1K_0402_5%R38 1K_0402_5%

R36 1K_0402_5%R36 1K_0402_5%

R35 1K_0402_5%R35 1K_0402_5%

R5 300_0402_5%R5 300_0402_5%

R7 300_0402_5%R7 300_0402_5%

R2 300_0402_5%R2 300_0402_5%

Compal Electronics, Inc.

mount

1 2

eDP@

1 2

12

FT1 CTRL/DP/CRT

P1VE6 Schematics

Display

LVDS

@

eDP

DMIC_CLK

+1.8VS

4 37Thursday, March 17, 2011

1

+3VS

DMIC_CLK <9,17>

of

1.0

E

Dr-Bios.com

UMI_TX0P <12> UMI_TX0N <12>

UMI_TX1P <12> UMI_TX1N <12>

UMI_TX2P <12> UMI_TX2N <12>

UMI_TX3P <12> UMI_TX3N <12>

P_ZVSS

P_UMI_TXP0

P_UMI_TXN0

P_UMI_TXP1

P_UMI_TXN1

P_UMI_TXP2

P_UMI_TXN2

P_UMI_TXP3

P_UMI_TXN3

D

AB6 AC6

AB3 AC3

Y1 Y2

V3 V4

AA14

AB12

AC12

AC11

AB11

AA8

Y8

AB8

AC8

P_ZVSS

R54 1.27K_0402_1%R54 1.27K_0402_1%

Less than 1"

UMI_TX0P_C

UMI_TX0N_C

UMI_TX1P_C

UMI_TX1N_C

UMI_TX2P_C

UMI_TX2N_C

UMI_TX3P_C

UMI_TX3N_C

C19 .1U_0402_16V7KC19 .1U_0402_16V7K

C20 .1U_0402_16V7KC20 .1U_0402_16V7K

C21 .1U_0402_16V7KC21 .1U_0402_16V7K

C22 .1U_0402_16V7KC22 .1U_0402_16V7K

C23 .1U_0402_16V7KC23 .1U_0402_16V7K

C24 .1U_0402_16V7KC24 .1U_0402_16V7K

C25 .1U_0402_16V7KC25 .1U_0402_16V7K

C26 .1U_0402_16V7KC26 .1U_0402_16V7K

1 2

A

U1E

DDR_A_MA0

DDR_A_MA1

DDR_A_MA2

DDR_A_MA3

DDR_A_MA4 DDR_A_MA5

DDR_A_MA6

4 4

3 3

2 2

DDR_A_MA7

DDR_A_MA8

DDR_A_MA9

DDR_A_MA10 DDR_A_MA11

DDR_A_MA12

DDR_A_MA13 DDR_A_MA14

DDR_A_MA15

DDR_A_BS0<7,8> DDR_A_BS1<7,8>

DDR_A_BS2<7,8>

DDR_A_DQS0<7,8>

DDR_A_DQS#0<7,8> DDR_A_DQS1<7,8>

DDR_A_DQS#1<7,8> DDR_A_DQS2<7,8>

DDR_A_DQS#2<7,8> DDR_A_DQS3<7,8>

DDR_A_DQS#3<7,8> DDR_A_DQS4<7,8>

DDR_A_DQS#4<7,8> DDR_A_DQS5<7,8>

DDR_A_DQS#5<7,8>

DDR_A_DQS6<7,8>

DDR_A_DQS#6<7,8>

DDR_A_DQS7<7,8>

DDR_A_DQS#7<7,8>

DDR_A_CLK0<7>

DDR_A_CLK#0<7> DDR_A_CLK1<7>

DDR_A_CLK#1<7>

DDR_B_CLK2<8>

DDR_B_CLK#2<8> DDR_B_CLK3<8>

DDR_B_CLK#3<8>

DDR_RST#<7,8>

DDR_EVENT#<7,8>

DDR_CKE0<7,8> DDR_CKE1<7,8>

DDR_A_ODT0<7> DDR_A_ODT1<7>

DDR_B_ODT0<8>

DDR_B_ODT1<8>

DDR_CS0_DIMMA#<7>

DDR_CS1_DIMMA#<7>

DDR_CS0_DIMMB#<8>

DDR_CS1_DIMMB#<8>

DDR_A_RAS#<7,8>

DDR_A_CAS#<7,8> DDR_A_WE#<7,8>

DDR_A_DM0

DDR_A_DM1 DDR_A_DM2

DDR_A_DM3 DDR_A_DM4

DDR_A_DM5 DDR_A_DM6

DDR_A_DM7

DDR_A_DQS0 DDR_A_DQS#0

DDR_A_DQS1 DDR_A_DQS#1

DDR_A_DQS2 DDR_A_DQS#2

DDR_A_DQS3 DDR_A_DQS#3

DDR_A_DQS4 DDR_A_DQS#4

DDR_A_DQS5 DDR_A_DQS#5

DDR_A_DQS6 DDR_A_DQS#6

DDR_A_DQS7 DDR_A_DQS#7

DDR_A_CLK0

DDR_A_CLK#0

DDR_A_CLK1

DDR_A_CLK#1

DDR_B_CLK2 DDR_B_CLK#2

DDR_B_CLK3

DDR_B_CLK#3

DDR_RST#

DDR_EVENT#

DDR_CKE0 DDR_CKE1

DDR_A_ODT0

DDR_A_ODT1

DDR_B_ODT0

DDR_B_ODT1

DDR_CS0_DIMMA# DDR_CS1_DIMMA#

DDR_CS0_DIMMB#

DDR_CS1_DIMMB#

DDR_A_RAS# DDR_A_CAS#

DDR_A_WE#

U1E

R17

M_ADD0

H19

M_ADD1

J17

M_ADD2

H18

M_ADD3

H17

M_ADD4

G17

M_ADD5

H15

M_ADD6

G18

M_ADD7

F19

M_ADD8

E19

M_ADD9

T19

M_ADD10

F17

M_ADD11

E18

M_ADD12

W17

M_ADD13

E16

M_ADD14

G15

M_ADD15

R18

M_BANK0

T18

M_BANK1

F16

M_BANK2

D15

M_DM0

B19

M_DM1

D21

M_DM2

H22

M_DM3

P23

M_DM4

V23

M_DM5

AB20

M_DM6

AA16

M_DM7

A16

M_DQS_H0

B16

M_DQS_L0

B20

M_DQS_H1

A20

M_DQS_L1

E23

M_DQS_H2

E22

M_DQS_L2

J22

M_DQS_H3

J23

M_DQS_L3

R22

M_DQS_H4

P22

M_DQS_L4

W22

M_DQS_H5

V22

M_DQS_L5

AC20

M_DQS_H6

AC21

M_DQS_L6

AB16

M_DQS_H7

AC16

M_DQS_L7

M17

M_CLK_H0

M16

M_CLK_L0

M19

M_CLK_H1

M18

M_CLK_L1

N18

M_CLK_H2

N19

M_CLK_L2

L18

M_CLK_H3

L17

M_CLK_L3

L23

M_RESET_L

N17

M_EVENT_L

F15

M_CKE0

E15

M_CKE1

W19

M0_ODT0

V15

M0_ODT1

U19

M1_ODT0

W15

M1_ODT1

T17

M0_CS_L0

W16

M0_CS_L1

U17

M1_CS_L0

V16

M1_CS_L1

U18

M_RAS_L

V19

M_CAS_L

V17

M_WE_L

S IC ONTARIO CMC50AFPB22GT 1G BGA ABO!

DDR SYSTEM MEMORY

B

M_DATA0

M_DATA1 M_DATA2

M_DATA3 M_DATA4

M_DATA5 M_DATA6

M_DATA7

M_DATA8

M_DATA9

M_DATA10

M_DATA11 M_DATA12

M_DATA13 M_DATA14

M_DATA15

M_DATA16

M_DATA17 M_DATA18

M_DATA19 M_DATA20

M_DATA21 M_DATA22

M_DATA23

M_DATA24

M_DATA25 M_DATA26

M_DATA27 M_DATA28

M_DATA29 M_DATA30

M_DATA31

M_DATA32

M_DATA33 M_DATA34

M_DATA35 M_DATA36

M_DATA37 M_DATA38

M_DATA39

M_DATA40

M_DATA41 M_DATA42

M_DATA43 M_DATA44

M_DATA45 M_DATA46

M_DATA47

M_DATA48

M_DATA49 M_DATA50

M_DATA51 M_DATA52

M_DATA53 M_DATA54

M_DATA55

M_DATA56

M_DATA57 M_DATA58

M_DATA59 M_DATA60

M_DATA61 M_DATA62

M_DATA63

M_VREF

M_ZVDDIO_MEM_S

B14

A15 A17

D18 A14

C14 C16

D16

C18

A19 B21

D20 A18

B18 A21

C20

C23

D23 F23

F22 C22

D22 F20

F21

H21

H23 K22

K21 G23

H20 K20

K23

N23

P21 T20

T23 M20

P20 R23

T22

V20

V21 Y23

Y22 T21

U23 W23

Y21

Y20

AB22 AC19

AA18 AA23

AA20 AB19

Y18

AC17

Y16 AB14

AC14 AC18

AB18 AB15

AC15

M23

M22

DDR_A_D0

DDR_A_D1

DDR_A_D2

DDR_A_D3 DDR_A_D4

DDR_A_D5

DDR_A_D6

DDR_A_D7

DDR_A_D8

DDR_A_D9

DDR_A_D10

DDR_A_D11 DDR_A_D12

DDR_A_D13

DDR_A_D14

DDR_A_D15

DDR_A_D16 DDR_A_D17

DDR_A_D18

DDR_A_D19

DDR_A_D20 DDR_A_D21

DDR_A_D22 DDR_A_D23

DDR_A_D24

DDR_A_D25

DDR_A_D26

DDR_A_D27 DDR_A_D28

DDR_A_D29

DDR_A_D30 DDR_A_D31

DDR_A_D32

DDR_A_D33

DDR_A_D34

DDR_A_D35 DDR_A_D36

DDR_A_D37

DDR_A_D38

DDR_A_D39

DDR_A_D40 DDR_A_D41

DDR_A_D42 DDR_A_D43

DDR_A_D44 DDR_A_D45

DDR_A_D46

DDR_A_D47

DDR_A_D48

DDR_A_D49

DDR_A_D50 DDR_A_D51

DDR_A_D52 DDR_A_D53

DDR_A_D54

DDR_A_D55

DDR_A_D56

DDR_A_D57

DDR_A_D58

DDR_A_D59

DDR_A_D60 DDR_A_D61

DDR_A_D62

DDR_A_D63

+MEM_VREF

+M_ZVDDIO

R55

39.2_0402_1%

DDR_A_D[0..63]

DDR_A_MA[0..15]

DDR_A_DM[0..7]

+1.05VS

UMI_RX0P<12> UMI_RX0N<1 2>

UMI_RX1P<12> UMI_RX1N<1 2>

UMI_RX2P<12> UMI_RX2N<1 2>

UMI_RX3P<12> UMI_RX3N<1 2>

12

+1.5V

C

1 2

R53 2 K_0402_1%R53 2K_0402_1%

Less than 1"

DDR_A_D[0..63] <7,8>

DDR_A_MA[0..15] <7,8>

DDR_A_DM[0..7] <7,8>

P_ZVDD_10

8/22 Delete C11~C18 (No VGA)

9/6 Change PCI-E from FCH to APU

9/6 Update PCI-E port List

9/15 Change PCI-E from APU to FCH

U1A

AA6

P_GPP_RXP0

Y6

P_GPP_RXN0

AB4

P_GPP_RXP1

AC4

P_GPP_RXN1

AA1

P_GPP_RXP2

AA2

P_GPP_RXN2

Y4

P_GPP_RXP3

Y3

P_GPP_RXN3

Y14

P_ZVDD_10

AA12

P_UMI_RXP0

Y12

P_UMI_RXN0

AA10

P_UMI_RXP1

Y10

P_UMI_RXN1

AB10

P_UMI_RXP2

AC10

P_UMI_RXN2

AC7

P_UMI_RXP3

AB7

P_UMI_RXN3

S IC ONTARIO CMC50AFPB22GT 1G BGA ABO!

PCIE I/F

UMI I/F

P_GPP_TXP0 P_GPP_TXN0

P_GPP_TXP1 P_GPP_TXN1

P_GPP_TXP2 P_GPP_TXN2

P_GPP_TXP3 P_GPP_TXN3

9/11 Delete DDR Signal link to JDIMM2

+1.5V

1 1

Reserve C439 for DDR_EVENT# Michael 2010/11/18

R57

1 2

1K_0402_5%

DDR_EVENT#

@

1

2

A

C439

C439 100P_0402_50V8J

100P_0402_50V8J

R56

1K_0402_1%

R58

1K_0402_1%

1 2

1

C27

1000P_0402_50V7K

2

1 2

Place within 1000 mils to APU 20100526

B

C28

+MEM_VREF

1

0.1U_0402_16V4Z

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/11/09 2012/11/09

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

FT1 DDRIII/UMI/PCIE

P1VE6 Schematics

E

5 37Thursday, March 17, 2011

1.0

5

Dr-Bios.com

4

3

2

1

+APU_CORE

1

D D

C31

2

1

C43

2

1

C52

2

+APU_CORE_NB

C C

C68

C75

C84

B B

1

C29

2

10U_0603_6.3V6M

1

C44

2

1U_0402_6.3V6K

1

C53

2

.1U_0402_16V7K

1

C69

2

10U_0603_6.3V6M

1

C76

2

1U_0402_6.3V6K

1

C85

2

.1U_0402_16V7K

POWER

1

C92

@

2

10U_0603_6.3V6M

1U_0402_6.3V6K

.1U_0402_16V7K

10U_0603_6.3V6M

1U_0402_6.3V6K

.1U_0402_16V7K

+1.05VS

1

2

1

C32

2

1

C45

2

1

C54

2

1

C70

2

1

C77

2

1

C86

2

+

C93

220U_D2_2VY_R15M

SGA00004L00

1

C41

2

10U_0603_6.3V6M

1

C46

2

1U_0402_6.3V6K

1

C55

2

.1U_0402_16V7K

1

C71

2

10U_0603_6.3V6M

1

C78

2

1U_0402_6.3V6K

1

C87

2

.1U_0402_16V7K

1

C42

2

10U_0603_6.3V6M

1U_0402_6.3V6K

1

C56

2

.1U_0402_16V7K

1

C72

2

10U_0603_6.3V6M

1

C79

2

1U_0402_6.3V6K

.1U_0402_16V7K

9/20 Change C93 to SGA00004L00

1

C30

2

10U_0603_6.3V6M

1

C47

2

180P_0402_50V8J

1

C80

2

180P_0402_50V8J

9/15 Change C99,C100 to 470U(SGA00003K00)

SGA00003K00

1

+

330U_D2_2V_Y

2

A A

SGA20331E10

change C99,C100 from 470U to 330U , 2011/01/28 Tock change C99,C100 footprint from C_D2 to C_X for placement

+APU_CORE

1

+

C100

C99

C100

330U_D2_2V_Y

2

+APU_CORE_NB

1

+

C114

330U_D2_2V_Y

2

1

C102 10U_0603_6.3V6M

10U_0603_6.3V6M

2

Near CPU Socket

1

C117

10U_0603_6.3V6M

2

Near CPU Socket Near CPU Socket

5

POWER

@

@C102

SGA20331E10

4500 mA

1

C33

2

1

C48

2

1

C81

2

330U_D2_2V_Y

+APU_CORE

10U_0603_6.3V6M

8000 mA

+APU_CORE_NB

180P_0402_50V8J

2000 mA

+1.5V

180P_0402_50V8J

8/22 Change C111~C113 from E-Cap to Poly-Cap (SGA20331E10)

8/25 Change C111 from poly-cap to E-cap (SF000002Z00)

9/11 Change C111 to SGA20331E10

C111

+1.5V

1

C82

2

10U_0603_6.3V6M

1

C88

2

1U_0402_6.3V6K

1

C94

2

.1U_0402_16V7K

+1.5V +1.8VS

POWER POWER

1

+

2

1

C115

2

22U_0805_6.3V6M

U1C

E5

VDDCR_CPU_1

E6

VDDCR_CPU_2

F5

VDDCR_CPU_3

F7

VDDCR_CPU_4

G6

VDDCR_CPU_5

G8

VDDCR_CPU_6

H5

VDDCR_CPU_7

H7

VDDCR_CPU_8

J6

VDDCR_CPU_9

J8

VDDCR_CPU_10

L7

VDDCR_CPU_11

M6

VDDCR_CPU_12

M8

VDDCR_CPU_13

N7

VDDCR_CPU_14

R8

VDDCR_CPU_15

E8

VDDCR_NB_1

E11

VDDCR_NB_2

E13

VDDCR_NB_3

F9

VDDCR_NB_4

F12

VDDCR_NB_5

G11

VDDCR_NB_6

G13

VDDCR_NB_7

H9

VDDCR_NB_8

H12

VDDCR_NB_9

K11

VDDCR_NB_10

K13

VDDCR_NB_11

L10

VDDCR_NB_12

L12

VDDCR_NB_13

L14

VDDCR_NB_14

M11

VDDCR_NB_15

M12

VDDCR_NB_16

M13

VDDCR_NB_17

N10

VDDCR_NB_18

N12

VDDCR_NB_19

N14

VDDCR_NB_20

P11

VDDCR_NB_21

P13

VDDCR_NB_22

G16

VDDIO_MEM_S_1

G19

VDDIO_MEM_S_2

E17

VDDIO_MEM_S_3

J16

VDDIO_MEM_S_4

L16

VDDIO_MEM_S_5

L19

VDDIO_MEM_S_6

N16

VDDIO_MEM_S_7

R16

VDDIO_MEM_S_8

R19

VDDIO_MEM_S_9

W18

VDDIO_MEM_S_10

U16

VDDIO_MEM_S_11

S IC ONTARIO CMC50AFPB22GT 1G BGA ABO!

1

C83

2

10U_0603_6.3V6M

1U_0402_6.3V6K

.1U_0402_16V7K

C112

330U_D2_2V_Y

1

C90

2

1

C96

2

1

+

2

1

C89

2

1

C95

2

SGA20331E10

Near CPU Socket

4

2000 mA

TSense/PLL/DP/PCIE/IO

VDD_18_1 VDD_18_2

VDD_18_3 VDD_18_4

VDD_18_5 VDD_18_6

CPU CORE

VDD_18_7

DAC

VDD_18_DAC

GPU AND NB CORE

POWER

DIS PLL

VDDPL_10

PCIE/IO/DDR3 Phy

VDD_10_1

VDD_10_2 VDD_10_3

VDD_10_4

DDR3

DP Phy/IO

VDD_33

1

C91

2

1U_0402_6.3V6K

.1U_0402_16V7K

1U_0402_6.3V6K

1

C97

2

180P_0402_50V8J

1

C116

@

2

10U_0603_6.3V6M

+VDD_18

U8 W8

U6 U9

W6 T7

V7

W = 20 mil / Spcae = 20 mil

+VDD_18_DAC

W9

W = 15 mil / Spcae = 20 mil

+VDDL_10

U11

5500 mA

+VDD_10

U13

W13 V12

T12

500 mA

+VDD_33

A4

1

C98

2

180P_0402_50V8J

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

1

C34

2

1

C49

2

1

C57

2

1

C61

2

1

C73

2

Issued Date

1

C35

2

180P_0402_50V8J

1

C50

2

180P_0402_50V8J

1

C58

2

180P_0402_50V8J

1

C62

2

180P_0402_50V8J

1

C74

2

.1U_0402_16V7K

1

C36

C37

2

.1U_0402_16V7K

1U_0402_6.3V6K

1

C51

2

10U_0603_6.3V6M

1U_0402_6.3V6K

1

C59

C60

2

.1U_0402_16V7K

1U_0402_6.3V6K

1

C64

C63

2

.1U_0402_16V7K

R333

1 2

0_0603_5%

1U_0402_6.3V6K

8/22 Reserve R333 ( 0 ohm 0603 )

2010/11/09 2012/11/09

1

C38

2

1U_0402_6.3V6K

L2

FBMA-L11-201209-221LMA30T_0805

10U_0603_6.3V6M

1

C65

2

1U_0402_6.3V6K

+3VS

1

C39

C40

2

1U_0402_6.3V6K

+1.8VS

12

FBMA-L11-201209-221LMA30T_0805

1

C67

C66

2

1U_0402_6.3V6K

10U_0603_6.3V6M

Compal Secret Data

Deciphered Date

10U_0603_6.3V6M

8/25 Change +1.0VS to +1.05VS

L3

10U_0603_6.3V6M

+1.8VS

L1

12

FBMA-L11-201209-221LMA30T_0805

+1.05VS

12

L4

12

FBMA-L11-201209-221LMA30T_0805

2

U1D

A7

VSS_1

B7

VSS_2

B11

VSS_3

B17

VSS_4

B22

VSS_5

C4

VSS_6

D5

VSS_7

D7

VSS_8

D9

VSS_9

D11

VSS_10

D14

VSS_11

B15

VSS_12

D17

VSS_13

D19

VSS_14

E7

VSS_15

E9

VSS_16

E12

VSS_17

E20

VSS_18

F8

VSS_19

F11

VSS_20

F13

VSS_21

G4

VSS_22

G5

VSS_23

G7

VSS_24

G9

VSS_25

G12

VSS_26

G20

VSS_27

G22

VSS_28

H6

VSS_29

H11

VSS_30

H13

VSS_31

J4

VSS_32

J5

VSS_33

J7

VSS_34

J20

VSS_35

K10

VSS_36

K14

VSS_37

L4

VSS_38

L6

VSS_39

L8

VSS_40

L11

VSS_41

L13

VSS_42

L20

VSS_43

L22

VSS_44

M7

VSS_45

N4

VSS_46

N6

VSS_47

N8

VSS_48

N11

VSS_49

S IC ONTARIO CMC50AFPB22GT 1G BGA ABO!

By case (Along split)

+1.5V

1

C103

2

.1U_0402_16V7K

1

C105

C104

2

.1U_0402_16V7K

Title

Size Document Number Rev

C

Date: Sheet of

Date: Sheet

VSS_50 VSS_51

VSS_52 VSS_53

VSS_54 VSS_55

VSS_56 VSS_57

VSS_58 VSS_59

VSS_60 VSS_61

VSS_62 VSS_63

GND

VSS_64 VSS_65

VSS_66 VSS_67

VSS_68 VSS_69

VSS_70 VSS_71

VSS_72 VSS_73

VSS_74 VSS_75

VSS_76 VSS_77

VSS_78 VSS_79

VSS_80 VSS_81

VSS_82 VSS_83

VSS_84 VSS_85

VSS_86 VSS_87

VSS_88 VSS_89

VSS_90 VSS_91

VSS_92 VSS_93

VSS_94 VSS_95

VSS_96 VSS_97

VSSBG_DAC

1

C106

2

180P_0402_50V8J

C108

C107

2

180P_0402_50V8J

Compal Electronics, Inc.

P07-FT1 PWR/VSS

P1VE6 Schematics

1

N13 N20

N22 P10

P14 R4

R7 R20

T6 T9

T11 T13

U4 U5

U7 U12

U20 U22

V8 V9

V11 V13

W1 W2

W4 W5

W7 W12

W20 Y5

Y7 Y9

Y11 Y13

Y15 Y17

Y19 AA4

AA22 AB2

AB5 AB9

AB13 AB17

AB21 AC5

AC9 AC13

A11

180P_0402_50V8J

1

C110

C109

2

180P_0402_50V8J

1.0

6 37Thursday, March 17, 2011

1.0

of

5

Dr-Bios.com

4

3

2

1

+1.5V

3500 mA

DDR_A_D4

DDR_A_D5

DDR_A_D6

DDR_A_D7

DDR_A_D12

DDR_A_D13

DDR_A_DM1

DDR_A_D14

DDR_A_D15

DDR_A_D20

DDR_A_D21

DDR_A_DM2

DDR_A_D22

DDR_A_D23

DDR_A_D28

DDR_A_D29

DDR_A_D30

DDR_A_D31

R397

1 2

100_0402_1%

DDR_A_MA15

DDR_A_MA14

DDR_A_MA11

DDR_A_MA7

DDR_A_MA6

DDR_A_MA4

DDR_A_MA2

DDR_A_MA0

DDR_A_D36

DDR_A_D37

DDR_A_DM4

DDR_A_D38

DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_D46

DDR_A_D47

DDR_A_D52

DDR_A_D53

DDR_A_DM6

DDR_A_D54

DDR_A_D55

DDR_A_D60

DDR_A_D61

DDR_A_D62

DDR_A_D63

+0.75VS

100 mA

DDR_A_D0

DDR_A_D1

DDR_A_DM0

DDR_A_D2

DDR_A_D3

DDR_A_D8

DDR_A_D9

DDR_A_D10

DDR_A_D11

DDR_A_D16

DDR_A_D17

DDR_A_D18

DDR_A_D19

DDR_A_D24

DDR_A_D25

DDR_A_DM3

DDR_A_D26

DDR_A_D27

R396

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8

DDR_A_MA5

DDR_A_MA3

DDR_A_MA1

DDR_A_MA10

DDR_A_MA13

DDR_A_D32

DDR_A_D33

DDR_A_D34

DDR_A_D35

DDR_A_D40

DDR_A_D41

DDR_A_DM5

DDR_A_D42

DDR_A_D43

DDR_A_D48

DDR_A_D49

DDR_A_D50 DDR_A_D51

DDR_A_D56

DDR_A_D57

DDR_A_DM7

DDR_A_D58

DDR_A_D59

12

R64

10K_0402_5%

+1.5V

JDIMM1

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

FOX_AS0A621-U4RG-7H

CONN@

CONN@JD IMM1

VSS DQ4

DQ5 VSS

DQS0#

DQS0

VSS DQ6

DQ7 VSS

DQ12 DQ13

VSS DM1

RESET#

VSS

DQ14 DQ15

VSS

DQ20

DQ21

VSS

DM2 VSS

DQ22 DQ23

VSS

DQ28

DQ29

VSS

DQS3#

DQS3

VSS

DQ30

DQ31

VSS

CKE1

VDD

CK1

CK1#

VDD BA1

RAS#

VDD

ODT0

VDD

ODT1

VDD

VREF_CA

VSS

DQ36 DQ37

VSS DM4

VSS

DQ38

DQ39

VSS

DQ44 DQ45

VSS

DQS5#

DQS5

VSS

DQ46 DQ47

VSS

DQ52

DQ53

VSS

DM6 VSS

DQ54 DQ55

VSS

DQ60

DQ61

VSS

DQS7#

DQS7

VSS

DQ62

DQ63

VSS

EVENT#

SDA

SCL

VTT

GND2

BOSS2

2 4

6 8

10 12

14 16

18 20

22 24

26 28

30 32

34 36

38 40

42 44

46 48

50 52

54 56

58 60

62 64

66 68

70 72

74 76

78

A15

80

A14

82 84

A11

86

A7

88

90

A6

92

A4

94 96

A2

98

A0

100

102 104

106 108

110 112

114

S0#

116

118 120

122

NC

124

126 128

130 132

134 136

138 140

142 144

146 148

150 152

154 156

158 160

162 164

166 168

170 172

174 176

178 180

182 184

186 188

190 192

194 196

198 200

202

204

206

208

W=20mil

+VREF_DQ

1

C118

D D

C C

B B

+3VS

A A

2

DDR_CS1_DIMMA#<5 >

C138

1

C119

2

0.1U_0402_16V4Z

DDR_A_DQS#1<5,8>

DDR_A_DQS1<5,8>

DDR_A_DQS#2<5,8>

DDR_A_DQS2<5,8>

DDR_CKE0<5,8>

DDR_A_BS2<5,8>

DDR_A_CLK0<5>

DDR_A_CLK#0<5>

DDR_A_BS0<5,8>

DDR_A_WE#<5,8> DDR_A_CAS#<5,8>

DDR_A_DQS#4<5,8>

DDR_A_DQS4<5,8>

DDR_A_DQS#6<5,8>

DDR_A_DQS6<5,8>

1

2

1000P_0402_50V7K

1 2

100_0402_1%

R63 10K_0402_5%R63 10K_0402_5%

1 2

1

C139

2

0.1U_0402_16V4Z

2.2U_0603_6.3V6K

5

4

Change JDIMM1 socket to SP07000NN00 2010/12/06 Tock Change JDIMM1 socket to SP07000NZ00 2010/12/14 Tock

DDR_A_DQS#0 <5,8>

DDR_A_DQS0 <5,8>

DDR_RST#

1

@

C413

100P_0402_50V8J

DDR_RST# <5,8>

100P_0402_50V8J

2

DDR_A_D[0..63]

DDR_A_MA[0..15]

DDR_A_DM[0..7]

Reserve C413 for DDR_RST# Michael 2010/11/18

9/23 Reserve R396,R397 on CKE0 & CKE1(S3 hang Issue)

DDR_A_DQS#3 <5,8> DDR_A_DQS3 <5,8>

+1.5V

0.1U_0402_16V4Z

2

DDR_CKE1 <5,8>

2

C120

1

0.1U_0402_16V4Z

C121

1

2

C122

1

0.1U_0402_16V4Z

10/11 Change R396 R397 from @ to mount (For A1 APU,B0 APU no Need)

DDR_A_CLK1 <5> DDR_A_CLK#1 <5>

DDR_A_BS1 <5,8> DDR_A_RAS# <5,8>

DDR_CS0_DIMMA# <5> DDR_A_ODT0 <5>

DDR_A_ODT1 <5>

W=20mil

+VREF_CA

1

C132

2

DDR_A_DQS#5 <5,8>

DDR_A_DQS5 <5,8>

DDR_A_DQS#7 <5,8>

DDR_A_DQS7 <5,8>

DDR_EVENT# <5,8>

FCH_SMDAT0 <8,13,20,21>

FCH_SMCLK0 <8,13,20,21>

1

C133

2

1000P_0402_50V7K

0.1U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/11/09 2012/11/09

Compal Secret Data

Deciphered Date

2

C126

@

1

+1.5V

R59

R59 1K_0402_1%

1K_0402_1%

1 2

R61

R61 1K_0402_1%

1K_0402_1%

1 2

0.1U_0402_16V4Z

2

C127

@

1

0.1U_0402_16V4Z

DDR_A_D[0..63] <5,8>

DDR_A_MA[0..15] <5,8>

DDR_A_DM[0..7] <5,8>

0.1U_0402_16V4Z

2

C123

1

0.1U_0402_16V4Z

2

C124

1

0.1U_0402_16V4Z

2

C125

1

+VREF_DQ

0.1U_0402_16V4Z

9/11 Change C137 to SGA00004L00

CRB 0.1u X1 4.7u X1

+0.75VS

2

C136

C134

@

1

0.1U_0402_16V4Z

Place near JDIMM1

8/25 Change C137 from poly-cap to E-cap (SF000002Y00) 8/25 Reserve C381 E-cap (SF000002Y00) on +1.5V

9/11 Remove C381

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet

C136

C135

1

0.1U_0402_16V4Z

Compal Electronics, Inc.

+1.5V

2

C128

@

1

+VREF_CA

0.1U_0402_16V4Z

2

C129

@

1

2

C130

@

1

0.1U_0402_16V4Z

1 2

0.1U_0402_16V4Z

CRB 100U X2

+1.5V

1

2

4.7U_0603_6.3V6K

change C137 to SF000002Y00 2010/12/14 Tock

DDR3 SODIMM-I Socket

P1VE6 Schematics

1

+

@

2

SGA00004L00

1

C137

220U_6.3V_M

7 37Thursday, March 17, 2011

R60

R60 1K_0402_1%

1K_0402_1%

R62

R62 1K_0402_1%

1K_0402_1%

2

@

1

of

C131

1.0

5

Dr-Bios.com

4

3

2

1

+1.5V

3500 mA

DDR_A_D4

DDR_A_D5

DDR_A_D6

DDR_A_D7

DDR_A_D12

DDR_A_D13

DDR_A_DM1

DDR_A_D14

DDR_A_D15

DDR_A_D20 DDR_A_D21

DDR_A_DM2

DDR_A_D22

DDR_A_D23

DDR_A_D28

DDR_A_D29

DDR_A_D30

DDR_A_D31

R401

@

R401

@

1

100_0402_1%

DDR_A_MA15

DDR_A_MA14

DDR_A_MA11

DDR_A_MA7

DDR_A_MA6

DDR_A_MA4

DDR_A_MA2

DDR_A_MA0

DDR_A_D36

DDR_A_D37

DDR_A_DM4

DDR_A_D38

DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_D46

DDR_A_D47

DDR_A_D52

DDR_A_D53

DDR_A_DM6

DDR_A_D54

DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_D62 DDR_A_D63

+0.75VS

100 mA

DDR_A_D0

DDR_A_D1

DDR_A_DM0

DDR_A_D2

DDR_A_D3

DDR_A_D8

DDR_A_D9

DDR_A_D10

DDR_A_D11

DDR_A_D16

DDR_A_D17

DDR_A_D18

DDR_A_D19

DDR_A_D24

DDR_A_D25

DDR_A_DM3

DDR_A_D26

DDR_A_D27

R421

DDR_A_MA12

DDR_A_MA9

DDR_A_MA8

DDR_A_MA5

DDR_A_MA3

DDR_A_MA1

DDR_A_MA10

DDR_A_MA13

DDR_A_D32

DDR_A_D33

DDR_A_D34

DDR_A_D35

DDR_A_D40

DDR_A_D41

DDR_A_DM5

DDR_A_D42

DDR_A_D43

DDR_A_D48

DDR_A_D49

DDR_A_D50

DDR_A_D51

DDR_A_D56

DDR_A_D57

DDR_A_DM7

DDR_A_D58

DDR_A_D59

12

R131

@

+1.5V

JDIMM2

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

55

57

59

61

63

65

67

69

71

2

10K_0402_5%

73

75

77

79

81

83

85

87

89

91

93

95

97

99

101

103

105

107

109

111

113

115

117

119

121

123

125

127

129

131

133

135

137

139

141

143

145

147

149

151

153

155

157

159

161

163

165

167

169

171

173

175

177

179

181

183

185

187

189

191

193

195

197

199

201

203

205

FOX_AS0A621-U4SG-7H

VREF_DQ

VSS2

DQ0

DQ1

VSS4

DM0

VSS5

DQ2

DQ3

VSS7

DQ8

DQ9

VSS9

DQS#1

DQS1

VSS11

DQ10

DQ11

VSS13

DQ16

DQ17

VSS15

DQS#2

DQS2

VSS18

DQ18

DQ19

VSS20

DQ24

DQ25

VSS22

DM3

VSS23

DQ26

DQ27

VSS25

CKE0

VDD1

NC1

BA2

VDD3

A12/BC#

A9

VDD5

A8

A5

VDD7

A3

A1

VDD9

CK0

CK0#

VDD11

A10/AP

BA0

VDD13

WE#

CAS#

VDD15

A13

S1#

VDD17

NCTEST

VSS27

DQ32

DQ33

VSS29

DQS#4

DQS4

VSS32

DQ34

DQ35

VSS34

DQ40

DQ41

VSS36

DM5

VSS37

DQ42

DQ43

VSS39

DQ48

DQ49

VSS41

DQS#6

DQS6

VSS44

DQ50

DQ51

VSS46

DQ56

DQ57

VSS48

DM7

VSS49

DQ58

DQ59

VSS51

SA0

VDDSPD

SA1

VTT1

G1

CONN@

VSS1

DQ4

DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6

DQ7

VSS8

DQ12

DQ13

VSS10

DM1

RESET#

VSS12

DQ14

DQ15

VSS14

DQ20

DQ21

VSS16

DM2

VSS17

DQ22

DQ23

VSS19

DQ28

DQ29

VSS21

DQS#3

DQS3

VSS24

DQ30

DQ31

VSS26

CKE1

VDD2

VDD4

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

BA1

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36

DQ37

VSS30

DM4

VSS31

DQ38

DQ39

VSS33

DQ44

DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46

DQ47

VSS40

DQ52

DQ53

VSS42

DM6

VSS43

DQ54

DQ55

VSS45

DQ60

DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62

DQ63

VSS52

EVENT#

SDA

SCL

VTT2

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

60

62

64

66

68

70

72

74

76

78

A15

80

A14

82

84

A11

86

A7

88

90

A6

92

A4

94

96

A2

98

A0

100

102

104

106

108

110

112

114

S0#

116

118

120

122

124

126

128

130

132

134

136

138

140

142

144

146

148

150

152

154

156

158

160

162

164

166

168

170

172

174

176

178

180

182

184

186

188

190

192

194

196

198

200

202

204

206

G2

W=20mil

+VREF_DQ

1

C166

2

@

+3VS

@

DDR_CS1_DIMMB#<5 >

C158

@

D D

C C

B B

A A

1

C160

2

@

0.1U_0402_16V4Z

DDR_A_DQS#1<5,7> DDR_A_DQS1<5,7>

DDR_A_DQS#2<5,7>

DDR_A_DQS2<5,7>

DDR_CKE0<5,7>

DDR_A_BS2<5,7>

DDR_B_CLK2<5> DDR_B_CLK#2<5>

DDR_A_BS0<5,7>

DDR_A_WE#<5,7>

DDR_A_CAS#<5,7>

DDR_A_DQS#4<5,7>

DDR_A_DQS4<5,7>

DDR_A_DQS#6<5,7>

DDR_A_DQS6<5,7>

1

2

+3VS

2.2U_0603_6.3V6K

1000P_0402_50V7K

@

1

100_0402_1%

R130 10K_040 2_5%@

1

C159

@

2

0.1U_0402_16V4Z

5

4

Change JDIMM2 socket to SP07000NZ00 for reverse 2010/12/06 Tock Change JDIMM2 socket to SP07000NN00 2010/12/14 Tock

DDR_A_DQS#0 <5,7>

DDR_A_DQS0 <5,7>

DDR_RST# <5,7>

DDR_A_DQS#3 <5,7> DDR_A_DQS3 <5,7>

2

DDR_CKE1 <5,7>

1

@

2

DDR_RST#

C414

100P_0402_50V8J

0.1U_0402_16V4Z

Reserve C414 for DDR_RST# Michael 2010/11/18

+1.5V

0.1U_0402_16V4Z

2

C167

@

1

9/23 Reserve R421,R401 on CKE0 & CKE1(S3 hang Issue)

10/11 Change R421 R401 from @ to mount (For A1 APU,B0 APU no Need)

DDR_B_CLK3 <5>

DDR_B_CLK#3 <5>

DDR_A_BS1 <5,7>

DDR_A_RAS# <5,7>

DDR_CS0_DIMMB# <5>

DDR_B_ODT0 <5>

DDR_B_ODT1 <5>

W=20mil

+VREF_CA

1

C146

@

2

DDR_A_DQS#5 <5,7> DDR_A_DQS5 <5,7>

DDR_A_DQS#7 <5,7> DDR_A_DQS7 <5,7>

DDR_EVENT# <5,7>

FCH_SMDAT0 <7,13,20,21>

FCH_SMCLK0 <7,13,20,21>

1

C147

@

2

0.1U_0402_16V4Z

1000P_0402_50V7K

0.1U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/11/09 2012/11/09

DDR_A_D[0..63]

DDR_A_MA[0..15]

DDR_A_DM[0..7]

2

C145

@

1

0.1U_0402_16V4Z

Compal Secret Data

Deciphered Date

DDR_A_D[0..63] <5,7>

DDR_A_MA[0..15] <5,7>

DDR_A_DM[0..7] <5,7>

0.1U_0402_16V4Z

2

C141

@

1

C144

@

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

2

C143

C140

@

1

@

1

0.1U_0402_16V4Z

CRB 0.1u X1 4.7u X1

+0.75VS

2

C148

@

1

Place near JDIMM2

0.1U_0402_16V4Z

2

C150

C154

@

1

0.1U_0402_16V4Z

C154

@

1

2

C153

@

1

0.1U_0402_16V4Z

Title

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

0.1U_0402_16V4Z

2

C151

C149

@

1

0.1U_0402_16V4Z

1

C152

@

2

4.7U_0603_6.3V6K

C149

@

1

Compal Electronics, Inc.Compal Electronics, Inc.

DDR3 SODIMM-II Socket

P1VE6 Schematics

2

C157

@

1

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z

8 37Thursday, March 17, 2011

2

C155

@

1

1.0

of

5

Dr-Bios.com

4

3

2

1

LCD POWER CIRCUIT

+LCDVDD

12

R67

D D

470_0402_5%

R67

W=40mils

Q32A

DMN66D0LDW-7_SOT363-6

Q32A

+3VALW

R68

100K_0402_5%

2

G

1 2

R69 4.7K_0402_5%R69 4.7K_0402_5%

+LCDVDD_R

61

D

S

W=40mils W=40mils

0.1U_0402_16V4Z

1

C165

2

0.047U_0402_16V4Z

12

8/31 Change R68.2 link to +3VALW

11/02 Change Q3 PN to SB934130020

2011/02/11 Change Q3 PN to SB000006R10

Q3

+LCDVDD

C162

1

2

AO3413L_SOT23-3

DGS

1

C163

@

2

4.7U_0603_6.3V6K

Change C163 BOM Struture to @ Michael 2010/11/18

+3VS

3

2

Remove C164 4.7U Michael 2010/11/18

Camera

J1

+3VS

J1

1

JUMP_43X39

@

2

0.1U_0402_16V4Z

+CAM_VCC

C161

1

2

9/15 Remove D1 L5 R71 R72 C166 C167 for layout spacing

9/23 Add D1 L5 R71 R72 C166 C167 for ESD

USB20_N5_1 USB20_N5

USB20_P5_1

L5

1

4

WCM2012F2S-900T04_0805

9/23 Remove D1 C166 C167

9/24 Swap L5

12

R710_0402_5% R710_0402_5%

@

@L5

1

4

2

USB20_P5

3

12

R720_0402_5% R720_0402_5%

8/26 Change Q4 Q5 to Q32A Q32B (SB00000DH00) Standard Part

34

D

Q32B

APU_ENVDD<4>

C C

100K_0402_5%

5

G

R70

1 2

9/9 Reserve 100k PD to GND on INVTPWM

CMOS & LCD/PANEL BD. Conn.

Add R344 0 ohm for +3VS_MIC Michael 2010/11 /18

Connect DMIC_CL K, DMIC_DATA to JLVDS1 pin 5 and 6 Michael 2010/11 /18

B B

A A

DMIC

JLVDS1

31

GND1

32

GND2

33

GND3

34

GND4

35

GND5

36

GND6

STARC_107K30-000001-G2

change JLVDS1 t o SP010011S00 2010/12/14 Tock

8/25 JLVDS1.5 change to INT_MIC0 JLVDS1.6 change to GNDA

8/31 Update JLVDS1 Pin definition Delete R74 R76

9/13 Update LVDS Pin definition, Add R74,R76

9/13 Add Net Name +3VS_DMIC

CONN@

CONN@JLVDS1

1 2

3 4

5 6

7 8

9

10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

+3VS_MIC

USB20_P5_1 USB20_N5_1

DMIC_CLK DMIC_DATA

LVDS_ACLK_R LVDS_ACLK#_R

LVDS_A2_R LVDS_A2#_R

LVDS_A1_R

LVDS_A1#_R

LVDS_A0_R LVDS_A0#_R

EDID_DATA_R EDID_CLK_R

BKOFF# INVTPWM

+3VS_LVDS

+LCDVDD_L

+LEDVDD

R327

0.1U_0402_16V4Z

eDP@

5

Q32B

DMN66D0LDW-7_SOT363-6

S

8/26 Change Q3 to SB934130020 Standard Part

10/01 Remove R74,R76

R3440_0402_5% R3440_0402_5%

12

+CAM_VCC

DMIC_CLK <4,17>

DMIC_DATA <17,26>

1 2

FBMA-L11-201209-221LMA30T_0805

L6

2

1

R328

0.1U_0402_16V4Z

eDP@

SE070104Z80

9/17 Change R387 from @ to mount

100K_0402_5%

R387

1 2

+3VS

camera

W=20mil

DMIC

2

BKOFF# <26>

+LCDVDD

L7

FBMA-L11-201209-221LMA30T_0805

C170

C170 330P_0402_50V7K

330P_0402_50V7K

3G@

R381

0.1U_0402_16V4Z

eDP@

4

8/22 Reserve R327~R332( 0 ohm) for eDP

8/31 Reserve R353 R354 on LVDS_ACLK

R3530_0402_5% LVDS@ R3530_0402_5% LVD S@

12

R3540_0402_5% LVDS@

1

R3270_0402_5% LVDS@ R3270_0402_5% LVDS @

12

R3280_0402_5% LVDS@ R3280_0402_5% LVD S@

12

R3290_0402_5% LVDS@ R3290_0402_5% LVDS @

12

R3300_0402_5% LVDS@ R3300_0402_5% LVDS @

12

R3310_0402_5% LVDS@ R3310_0402_5% LVD S@

12

R3320_0402_5% LVDS@

1

EDID_DATA

R3810_0402_5% LVDS@

1

EDID_CLK

R3820_0402_5% LVDS@

1

R3340_0402_5% R3340_0402_5%

12

+3VS

W=20mil

12

R382

0.1U_0402_16V4Z

eDP@

INVTPWM

LVDS_ACLK <4>

LVDS_ACLK# <4>

LVDS_A2 <4>

LVDS_A2# <4>

LVDS_A1 <4>

LVDS_A1# <4>

LVDS_A0 <4>

LVDS_A0# <4>

9/7 Reserve R381,R382( 0 ohm)R383(100k@) for eDP

EDID_DATA <4>

EDID_CLK <4>

8/22 Reserve R334(0402 0 ohm)

W=20mil

B+

1

C171

C171 100P_0402_50V8J

100P_0402_50V8J

2

3G@

PJDLC05C_SOT23-3

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

@

Issued Date

12

LVDS@

EDID_CLK_R

EDID_DATA_R

220P_0402_50V7K

2

DA2

3

R3100_0402_5% @ R3100_0402_5% @

R3110_0402_5% R3110_0402_5%

INVT_PWM

BKOFF#

R75

C168

3G@

+3VS

2.2K_0402_5%

1 2

1

2

INVT_PWM <26>

APU_BLPWM <4>

R73

1 2

R383

12

EC

APU

LVDS@

2.2K_0402_5%

100K_0402_5%

1

eDP@

C169

1000P_0402_50V7K

3G@

2

For RF

DMIC_CLK

DMIC_DATA

1

3

CA55

2

22P_0402_50V8J

1

2010/11/09 2012/11/09

1

CA56

2

22P_0402_50V8J

Compal Secret Data

Deciphered Date

10/04 Add 100p(C401) on INVT_PWM

C401

INVTPWM

C401

2

1

100P_0402_50V8J

10/04 Change C401 on INVTPWM

R75

Display

100K_0402_5%

eDP@

SD028100380

R327 0 ohm

R328

R381

R382

R383

R73

R75 2.2k ohm 100k ohm

9/3 Pull-Down 10k(R377) to GND on BKOFF#

BKOFF#

2

R377 10K_0402_5%R377 10K_0402_5%

1 2

Title

Size Document Number Rev

B

Date: Sheet of

*

LVDS eDP

0.1uF

0 ohm

@ 100k ohm

2.2k ohm @

Compal Electronics, Inc.

LVDS / Camera / DMIC

0.1uF

P1VE6 Schematics

9 37Thursday, March 17, 2011

1

USB20_N5 <13>

USB20_P5 <13>

1.0

5

Dr-Bios.com

4

3

2

1

HDMI@

R107 0_0402_5%

HDMI@

2

HDMI_CLKN<4>

HDMI_CLKP<4>

HDMI_TX0N<4>

HDMI_TX0P<4>

HDMI_TX1N<4>

HDMI_TX1P<4>

D D

HDMI_TX2N<4>

HDMI_TX2P<4>

HDMI_CLKP

HDMI_CLKN

HDMI_TX0P

HDMI_TX0N

HDMI_TX1P

C C

HDMI_TX1N

HDMI_TX2P

HDMI_TX2N

1

4

1

4

1

4

1

4

1

R112 0_0402_5%

1

HDMI@

R141 0_0402_5%

1

R142 0_0402_5%

1 2

HDMI@

R143 0_0402_5%

HDMI@

1

R187 0_0402_5%

1

HDMI@

R188 0_0402_5%

1 2

R192 0_0402_5%

1

@

L8

@L8

1

4

WCM-2012-900T_4P

@

L9

@L9

1

4

WCM-2012-900T_4P

L10

@

L10

@

1

4

WCM-2012-900T_4P

@

L11

@L11

1

4

WCM-2012-900T_4P

2

3

2

3

2

3

2

3

2

HDMI_CLK+_CONN

HDMI_CLK-_CONN

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_TX1+_CONN

HDMI_TX1-_CONN

HDMI_TX2+_CONN

HDMI_TX2-_CONN

HDMI_CLK-_CONN

HDMI_CLK+_CONN

HDMI_TX0-_CONN

HDMI_TX0+_CONN

HDMI_TX1-_CONN

HDMI_TX1+_CONN

HDMI_TX2-_CONN

HDMI_TX2+_CONN

Change RP13 to R107 , R112 Tock 2010/12/30

Change RP14 to R141 , R142 Tock 2010/12/30

Change RP15 to R143 , R187 Tock 2010/12/30

Change RP16 to R188 , R192 Tock 2010/12/30

Swap HDMI Net of RP13~RP16 for layout Tock 2010/12/24

HDMI_CLK+_CONN

HDMI_CLK-_CONN

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_TX1+_CONN

HDMI_TX1-_CONN

HDMI_TX2+_CONN

HDMI_TX2-_CONN

NEAR CONNECT

1 2

R85 499 _0402_1%HDM I@R85 499_0402_1%HDMI@

1 2

R86 499 _0402_1%HDM I@R86 499_0402_1%HDMI@

1

R87 499 _0402_1%HDM I@

1

R88 499 _0402_1%HDM I@

1

R89 499 _0402_1%HDM I@

1 2

R90 499 _0402_1%HDM I@R90 499_0402_1%HDMI@

1

R91 499 _0402_1%HDM I@

1

R93 499 _0402_1%HDM I@

+5VS

2

12

@

R95

100K_0402_5%

2

G

13

D

Q7

SSM3K7002FU_SC70-3

S

HDMI@

8/26 Change Q7 to SB000009610 Standard Part

+5VS +5VS

3

2

HDMIDAT_R

1

@

D2

D2 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

EMI/ESD

10/29 Add C409~C412(0.1U) on +5VS_HDMI 10/29 Add C415~C416(0.1U) on +5VS_HDMI_F

3

2

1

@

D3

BAT54S-7-F_SOT23-3

HDMI_CLK<4>

HDMI_DATA<4>

12

HDMI@

2

1

HDMI@

2

1

HDMI@

12

HDMI@

C4090.1U_0402_16V4Z

C4100.1U_0402_16V4Z

C4110.1U_0402_16V4Z

C4120.1U_0402_16V4Z

10/27 Change D5 P/N from SC1B491D000 to SCS00003H00

10/27 Change F2 P/N from SP04301P120 to SP040001B00

B B

R99

1

0_0402_5%

@

HDMI@

MMBT3904_NL_SOT23-3

HDMI_DET<4>

9/20 Change R99 from HDMI@ to @

9/20 Change Q8,R100 from @ to HDMI@

2

+3VS

C

Q8

C

E

3 1

12

R103

R103 100K_0402_5%

100K_0402_5%

HDMI@

R100

2

1

2

B

150K_0402_5%

HDMI@

200K_0402_5%

R101

10/28 Change JHDMI1 footprint from ACON_HMR2E-AK120D_19P-T to ACON_HMR2E-AK120D_19P-S

HDMI_HPD

12

@

R102

R102 100K_0402_5%

100K_0402_5%

1 2

10/07 Update JHDMI1 footprint from ACON_HMR2E-AK120D_19P to ACON_HMR2E-AK120D_19P-T

11/16 Update JHDMI1 Symbol (ACON_HMR2E-AK120D_19P)

A A

+5VS

3

2

HDMI_HPDHDMICLK_R

1

@

D4

D4 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

+3VS

G

S

5

G

Q9A

DMN66D0LDW-7_SOT363-6

HDMI@

34

D

S

Q9B

DMN66D0LDW-7_SOT363-6

HDMI@

2

61

D

HDMICLK_R

HDMIDAT_R

8/19 Change Q9A Q9B to SB00000DH00 (S TR DMN66D0LDW-7 2N SOT363-6)

+5VS_HDMI

@

R96

0_0805_5%

HDMI@

R97

2.2K_0402_5%

1 2

+5VS

21

+5VS_HDMI

W=60mil

HDMI@

R98

2.2K_0402_5%

21

HDMI_CLK-_CONN

HDMI_CLK+_CONN

HDMI_TX0-_CONN

HDMI_TX0+_CONN

HDMI_TX1-_CONN

HDMI_TX1+_CONN

HDMI_TX2-_CONN

HDMI_TX2+_CONN

2

1

HDMI@

12

HDMI@

W=60mil

9/20 Add F2 on HDMI

HDMI@

D5

D5 RB491D_SC59-3

RB491D_SC59-3

1

2

HDMI@

F2

HDMI@F2

1.1A_6V_SMD1812P110TF

HDMI_HPD

+5VS_HDMI_F

HDMIDAT_R

HDMICLK_R

C4150.1U_0402_16V4Z

C4160.1U_0402_16V4Z

C172

0.1U_0402_16V4Z

HDMI@

JHDMI1

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

ACON_HMR2E-AK120D

CONN@

+5VS_HDMI_F

GND

GND GND

GND

20

21 22

23

8/23 Update JHDMI1 Symbol (SUYIN_100042GR019S268ZR_19P-T)

9/7 Update JHDMI1 Symbol (ACON_HMR2E-AK120D_19P)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

5

4

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

2010/11/09 2012/11/09

3

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

HDMI Connector

P1VE6 Schematics

10 37Thursday, March 17, 2011

1

1.0

A

Dr-Bios.com

B

C

D

E

Close to CRT CONN for ESD.

3

2

D6

@

Modify C31- C308 C303 C307 C306 C304 BOM Structure 0615

1 1

DAC_RED<4>

DAC_GRN<4>

DAC_BLU<4>

2 2

CRT_HSYNC<4>

8/21 Change U2 U3 to SA00000RZ00 (TC7SET125FUF_SC70-5)

8/21 Reserve R325 R326 for CRT buffer cost down

CRT_VSYNC<4>

3 3

2.2K_0402_5%

CRT_DDC_DATA<4>

4 4

CRT_DDC_CLK<4>

R104

R109

+3VS

150_0402_1%

12

1

R105

2

12

2.2K_0402_5%

R108

150_0402_1%

1

R106

150_0402_1%

2

1 2

C179 0.1U_0402_16V4ZC179 0.1U_0402_16V4Z

U2

1

G

2

IN A

3

TC7SET125FUF_SC70-5

R325 0_0402_5%@R325 0_0402_5%@

1 2

C180 0.1U_0402_16V4ZC180 0.1U_0402_16V4Z

U3

1

2

3

TC7SET125FUF_SC70-5

R326 0_0402_5%@R326 0_0402_5%@

G

2

S

Q11A

DMN66D0LDW-7_SOT363-6

OUT Y

GND

1 2

G

IN A

OUT Y

GND

1 2

2.2K_0402_5%

G

5

G

34

D

S

Q11B

DMN66D0LDW-7_SOT363-6

61

D

Vcc

R110

8/19 Change Q11A Q11B to SB00000DH00 (S TR DMN66D0LDW-7 2N SOT363-6)

A

B

Change L12. L14, L15 to SM01000C600 2010/04/06

1

C176

C177

2

10P_0402_50V8J

+5VS

5

4

+5VS

5

4

CRT_HSYNC_R

CRT_VSYNC_R

+CRT_VCC_F+3VS

R375 39_0402_5%R375 39_0402_5%

R376 39_0402_5%R376 39_0402_5%

10P_0402_50V8J

1 2

8/26 Update D8 P/N to SCS00003H00

8/26 Update F1 P/N to SP040001B00

10/4 Change from +CRT_VCC to +CRT_VCC_F

12

R111

2.2K_0402_5%

VGA_DDC_DAT

VGA_DDC_CLK

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

L12

CHENG-HANN MBK1005470YZF 0402

1 2

L13

CHENG-HANN MBK1005470YZF 0402

1 2

L14

CHENG-HANN MBK1005470YZF 0402

1 2

1

C178

2

10P_0402_50V8J

C173

10P_0402_50V8J

1

2

C174

C174 10P_0402_50V8J

10P_0402_50V8J

8/31 Delete Net Name: CRT_HSYNC_1, CRT_VSYNC_1

9/3 Add R375 R376 for CRT

CRT PORT

+CRT_VCC

+5VS

D8

W=40mils

2 1

RB491D_SC59-3

Add JCRT_4 , JCRT_5 , JCRT_11 2011/01/28 Tock

2010/11/09 2012/11/09

C

F1

1.1A_6VDC_FUSE

T15PADT15PAD

T26PADT26PAD

T27PADT27PAD

Compal Secret Data

JCRT_11

RED

VGA_DDC_DAT GREEN

JVGA_HS

BLUE

JVGA_VS

JCRT_4

VGA_DDC_CLK

JCRT_5

Deciphered Date

1

2

+CRT_VCC_F

21

@

1

PJDLC05C_SOT23-3

1

C175

10P_0402_50V8J

2

Delete Q10 , R107 for CRT Hot Plug detect Circuit 2010/12/15 Tock

8/26 Change Q10 to SB000009610 Standard Part

8/22 Update JCRT1 Symbol from database (SUYIN_070546FR015M21TZR_15P)

0.1U_0402_16V4Z

C181

1 2

JCRT1

6

11

1

7

12

2 8

G

13

G

3

9

14

4

10

15

5

SUYIN_070546FR015M21TZR

CONN@

Delete R112 and net CRT_DET# for CRT Hot Plug detect Circuit 2010/12/15 Tock

D

2

D7

@

1

RED

PJDLC05C_SOT23-3

GREEN

BLUE

JVGA_HS

JVGA_VS

11/01 Add Net CRT4, CRT11 on JCRT.4 , JCRT.11

remove CRT11, C RT4 Tock 2010/11/26

16 17

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

CRT PORT

P1VE6 Schematics

E

11 37Thursday, March 17, 2011

1.0

of

A

Dr-Bios.com

+3VALW

C182

12

5

U4

0.1U_0402_16V4Z

A_RST#

R114

8.2K_0402_5%

@

1 2

1 1

NC7SZ08P5X_NL_SC70-5

R120 0_0402_5%@R120 0_0402_5%@

2

B

1

A

1 2

U4

P

PLT_RST#

4

Y

G

3

12

R115

R115 100K_0402_5%

100K_0402_5%

9/2 Change R120 from 0603 to 0402

9/16 Change U4,C182 from @ to mount, R120, R115 from mount to @

9/27 Change R115 from @ to mount

WWAN FCH TX LAN FCH TX WLAN FCH TX

9/9 Add R384(@ 0 ohm) R385(0 ohm) on PCI-E RST

9/20 C183.2 link to R119.2 Follow CRB

PLT_RST# <18,20,21,26>

A_RST#

R119 33_0402_5%R119 33_0402_5%

UMI_RX0P<5> UMI_RX0N<5>

UMI_RX1P<5> UMI_RX1N<5>

UMI_RX2P<5> UMI_RX2N<5>

UMI_RX3P<5> UMI_RX3N<5>

UMI_TX0P<5>

UMI_TX0N<5> UMI_TX1P<5>

UMI_TX1N<5> UMI_TX2P<5>

UMI_TX2N<5> UMI_TX3P<5>

UMI_TX3N<5>

+PCIE_VDDAN

PCIE_FTX_C_DRX_P1<20> PCIE_FTX_C_DRX_N1<20>

PCIE_FTX_C_DRX_P2<18> PCIE_FTX_C_DRX_N2<18>

PCIE_FTX_C_DRX_P3<21> PCIE_FTX_C_DRX_N3<21>

WWAN FCH RX

2 2

9/6 Change PCI-E from FCH to APU

LAN FCH RX WLAN FCH RX

B

150P_0402_50V8J

R121 590_0402_1%R121 590_0402_1%

R118 2K_0402_1%R118 2K_0402_1%

C183

12

C184 .1U_0402_16 V7KC184 .1U_0402_16 V7K

1 2

C185 .1U_0402_16 V7KC185 .1U_0402_16 V7K

1 2

C188 .1U_0402_16 V7KC188 .1U_0402_16 V7K

1 2

C186 .1U_0402_16 V7KC186 .1U_0402_16 V7K

1 2

C187 .1U_0402_16 V7KC187 .1U_0402_16 V7K

1 2

C189 .1U_0402_16 V7KC189 .1U_0402_16 V7K

1 2

C190 .1U_0402_16 V7KC190 .1U_0402_16 V7K

1 2

C191 .1U_0402_16 V7K

1

C192 .1U_0402_16V7KC192 .1U_0402_16V7K

1 2

C193 .1U_0402_16V7KC193 .1U_0402_16V7K

1 2

C194 .1U_0402_16V7KC194 .1U_0402_16V7K

1 2

C195 .1U_0402_16V7KC195 .1U_0402_16V7K

1 2

C379 .1U_0402_16V7KC379 .1U_0402_16V7K

1 2

C380 .1U_0402_16V7KC380 .1U_0402_16V7K

1 2

2

12

PCIE_FRX_DTX_P1<20> PCIE_FRX_DTX_N1<20>

PCIE_FRX_DTX_P2<18> PCIE_FRX_DTX_N2<18>

PCIE_FRX_DTX_P3<21> PCIE_FRX_DTX_N3<21>

R384 0_0402_5%@R384 0_0402_5%@

R385 0_0402_5%R385 0_0402_5%

1 2

UMI_RX0P_C UMI_RX0N_C

UMI_RX1P_C UMI_RX1N_C

UMI_RX2P_C UMI_RX2N_C

UMI_RX3P_C UMI_RX3N_C

PCIE_CALRP PCIE_CALRN

PCIE_FTX_DRX_P1

PCIE_FTX_DRX_N1

PCIE_FTX_DRX_P2

PCIE_FTX_DRX_N2

PCIE_FTX_DRX_P3

PCIE_FTX_DRX_N3

10/08 Update U5 to SA000046H70 S IC 218-0792006 A13 HUDSON-M1 605P ABO!

U5E

P1

PCIE_RST_L

L1

A_RST_L

AD26

UMI_TX0P

AD27

UMI_TX0N

AC28

UMI_TX1P

AC29

UMI_TX1N

AB29

UMI_TX2P

AB28

UMI_TX2N

AB26

UMI_TX3P

AB27

UMI_TX3N

AE24

UMI_RX0P

AE23

UMI_RX0N

AD25

UMI_RX1P

AD24

UMI_RX1N

AC24

UMI_RX2P

AC25

UMI_RX2N

AB25

UMI_RX3P

AB24

UMI_RX3N

AD29

PCIE_CALRP

AD28

PCIE_CALRN

AA28

GPP_TX0P

AA29

GPP_TX0N

Y29

GPP_TX1P

Y28

GPP_TX1N

Y26

GPP_TX2P

Y27

GPP_TX2N

W28

GPP_TX3P

W29

GPP_TX3N

AA22

GPP_RX0P

Y21

GPP_RX0N

AA25

GPP_RX1P

AA24

GPP_RX1N

W23

GPP_RX2P

V24

GPP_RX2N

W24

GPP_RX3P

W25

GPP_RX3N

9/15 Change PCI-E from APU to FCH

8/25 Update JBATT1 Symbol (LOTES_AAA-BAT-019-K01_2P)

+RTCBATT1

1

CONN@

JBATT1

+

LAN

-

LOTES_AAA-BAT-019-K01

2

3 3

WLAN

WWAN

DISP_CLK< 4>

DISP_CLK#<4>

APU_CLK<4>

APU_CLK#<4>

CLK_PCIE_LAN<18>

CLK_PCIE_LAN#<18>

CLK_PCIE_WLAN<21>

CLK_PCIE_WLAN#<21>

CLK_PCIE_WW AN<20>

CLK_PCIE_WW AN#<20>

close to FCH within 1"

R125 0_0402_5%R125 0_0402_5%

1 2

R126 0_0402_5%R126 0_0402_5%

1 2

R127 0_0402_5%R127 0_0402_5%

1 2

R128 0_0402_5%R128 0_0402_5%

1 2

8/21 Delete R130,R131(No VGA)

R132 0_0402_5%R132 0_0402_5%

1 2

R133 0_0402_5%R133 0_0402_5%

1 2

R134 0_0402_5%R134 0_0402_5%

1 2

R135 0_0402_5%R135 0_0402_5%

1 2

R348 0_0402_5%R348 0_0402_5%

1 2

R349 0_0402_5%R349 0_0402_5%

1 2

DISP_CLK_R DISP_CLK#_R

APU_CLK_R APU_CLK#_R

CLK_PCIE_LAN_R CLK_PCIE_LAN#_R

CLK_PCIE_WLAN_R CLK_PCIE_WLAN#_R

CLK_PCIE_WW AN_R

CLK_PCIE_WW AN#_R

8/23 Add R348 R349 for WWAN PCIE

9/6 Change D10 to SC600000B00 Standard Part

9/13 Add NONCHARGE@ for D10 R244

12/07 Remove BOM structure NONCHARGE@ for D10 R244 Tock

3

+RTCBATT1_R

2

+CHGRTC

1 2

R244 1K_0402_5%R244 1K_0402_5%

D10

1

BAV70W_SOT323-3

W=20mil

4 4

9/13 Add Net Name +RTCBATT1_RR

9/13 Change Net Name +RTCBATT1 to +RTCBATT2

9/13 Add C392,R392,D23(CHARGE@) for RTC Charge Circuit

10/07 Change R392 from 1k to 0 ohm

10/08 Change R392 from 0 ohm to 1k ohm

+RTCBATT1+RTCBATT

9/1 Add R372 on CLK_48M_CR

9/7 Change R372 to 22 ohm

R372 22_0402_5%R372 22_0402_5%

CLK_48M_CR<19>

R388

22_0402_5%

3G@

C361

10P_0402_50V8J

3G@

change R388,C361 BS from @ to 3G@ for RF solution Tock 2011/03/16

22P_0402_50V8J

1 2

1

22P_0402_50V8J

2

reserve R388 , C361 for RF Tock 2010/12/29

1 2

C198

C199

1 2

12

25MHZ_20PF_7A25000012

Y2

CLK_48M_CR_R

1M_0603_5%

1M_0603_5% R139

R139

11/04 Change U5 PN to SA000046HA0 (S IC 218-0792006 A13 HUDSON-M1 FCBGA 0FA)

25M_CLK_X1

25M_CLK_X2

11/01 Change R392 from 1k to 0 ohm

12/07 Remove R392 , C392 , D23 Tock

A

B

M23

PCIE_RCLKP/NB_LNK_CLKP

P23

PCIE_RCLKN/NB_LNK_CLKN

U29

NB_DISP_CLKP

U28

NB_DISP_CLKN

T26

NB_HT_CLKP

T27

NB_HT_CLKN

V21

CPU_HT_CLKP

T21

CPU_HT_CLKN

V23

SLT_GFX_CLKP

T23

SLT_GFX_CLKN

L29

GPP_CLK0P

L28

GPP_CLK0N

N29

GPP_CLK1P

N28

GPP_CLK1N

M29

GPP_CLK2P

M28

GPP_CLK2N

T25

GPP_CLK3P

V25

GPP_CLK3N

L24

GPP_CLK4P

L23

GPP_CLK4N

P25

GPP_CLK5P

M25

GPP_CLK5N

P29

GPP_CLK6P

P28

GPP_CLK6N

N26

GPP_CLK7P

N27

GPP_CLK7N

T29

GPP_CLK8P

T28

GPP_CLK8N

L25

14M_25M_48M_OSC

L26

25M_X1

L27

25M_X2

S IC 218-0792006 A13 HUDSON-M1 FCBGA 0FA

SA000046HA0

8/25 Change FCH(U5) PN to SA000046H30

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

PCI CLKS

PCICLK4/14M_OSC/GPO39

PCI EXPRESS I/F

PCI I/F

REQ2_L/CLK_REQ8_L/GPIO41 REQ3_L/CLK_REQ5_L/GPIO42

GNT3_L/CLK_REQ7_L/GPIO46

CLOCK GENERATOR

LPC

LDRQ1_L/CLK_REQ6_L/GPIO49

CPU

ALLOW_LDTSTP/DMA_AC TIVE_L

RTC

Compal Secret Data

2010/11/09 2012/11/09

C

Compal Secret Data

PCICLK0

PCICLK1/GPO36

PCICLK2/GPO37 PCICLK3/GPO38

PCIRST_L

AD0/GPIO0 AD1/GPIO1

AD2/GPIO2 AD3/GPIO3

AD4/GPIO4 AD5/GPIO5

AD6/GPIO6 AD7/GPIO7

AD8/GPIO8 AD9/GPIO9

AD10/GPIO10 AD11/GPIO11

AD12/GPIO12

AD13/GPIO13

AD14/GPIO14

AD15/GPIO15 AD16/GPIO16

AD17/GPIO17 AD18/GPIO18

AD19/GPIO19 AD20/GPIO20

AD21/GPIO21 AD22/GPIO22

AD23/GPIO23 AD24/GPIO24

AD25/GPIO25 AD26/GPIO26

AD27/GPIO27 AD28/GPIO28

AD29/GPIO29 AD30/GPIO30

AD31/GPIO31

CBE0_L

CBE1_L

CBE2_L

CBE3_L

FRAME_L

DEVSEL_L

IRDY_L

TRDY_L

PAR

STOP_L

PERR_L SERR_L

REQ0_L

REQ1_L/GPIO40

GNT0_L

GNT1_L/GPO44

GNT2_L/GPO45

CLKRUN_L

LOCK_L

INTE_L/GPIO32

INTF_L/GPIO33

INTG_L/GPIO34 INTH_L/GPIO35

LPCCLK0 LPCCLK1

LAD0 LAD1

LAD2 LAD3

LFRAME_L

LDRQ0_L

SERIRQ/GPIO48

PROCHOT_L

LDT_PG

LDT_STP_L

LDT_RST_L

32K_X1

32K_X2

RTCCLK

INTRUDER_ALERT_L

VDDBT_RTC_G

Deciphered Date

D

W2 W1

W3 W4

Y1

V2

AA1 AA4

AA3 AB1

AA5 AB2

AB6 AB5

AA6 AC2

AC3 AC4

AC1

AD1

AD2

AC6 AE2

AE1 AF8

AE3 AF1

AG1 AF2

AE9 AD9

AC11 AF6

AF4 AF3

AH2 AG2

AH3 AA8

AD5

AD8

AA10

AE8 AB9

AJ3 AE7

AC5 AF5

AE6 AE4

AE11 AH5

AH4 AC12

AD12 AJ5

AH6 AB12

AB11 AD7

AJ6 AG6

AG4 AJ4

H24 H25

J27 J26

H29 H28

G28 J25

AA18 AB19

G21 H21

K19 G22

J24

C1

C2

D2

B2 B1

T16PADT16PAD

T17PADT17PAD

PCI_CLK1 <16>

PCI_CLK3 <16>

PCI_CLK4 <16>

PCI_AD23 <16>

PCI_AD24 <16> PCI_AD25 <16>

PCI_AD26 <16> PCI_AD27 <16>

PCI_CLK2

PE_GPIO0

10/05 PD 10k(R405) on CLKRUN

T18

PAD

PE_GPIO1

PAD

R136 0_0402_5%R136 0_0402_5%

R137 22_0402_5 %

R138 0_0402_5%R138 0_0402_5%

U5_G22

RTC_32KHI

RTC_32KHO

R405

T19

1 2

10K_0402_5%

1 2

2

1

1 2

11/01 Add Net U5_G22 on U5.G22

SUSCLK <26>

+RTCBATT_R

1

C200

2

1U_0402_6.3V6K

D

E

+3VS

Watchdog timer on NB_PWRGD

12

@

enable for pull-up disable for pull-down 20100527

R113

10K_0402_5%

12

R116

10K_0402_5%

9/9 Change R117 R122 from mount to @ 9/15 PU PE_GPIO1 100k to +5VALW

PE_GPIO1

R117 100K_0402_5%R117 100K_0402_5%

PE_GPIO0

PE_GPIO0, PE_GP IO1 are for DI S only It's no functio n for UMA P1VE6 follow P5 WE6 Tock 2010 /11/26

1 2

R122 100K_04 02_5%@R122 100K_0402_5%@

1 2

10/11 Change Y1 from SJ100006600 to SJ132P7KW10

Close to FCH

R123 20M _0402_5%@R123 20 M_0402_5%@

1 2

C196

APU_PWRGD

LPC_AD0 <26>

LPC_AD1 <26>

LPC_AD2 <26>

LPC_AD3 <26>

LPC_FRAME# <26>

SERIRQ <26>

ALLOW_STOP# <4>

FCH_PROCHOT# <4> APU_PWRGD <4>

LDT_RST# <4>

C196

2

1

22P_0402_50V8J

R124

20M_0603_5%

C197

1 2

22P_0402_50V8J

+1.8VS +3VS

G

S

FDV301N-NL_SOT23-3

Q12

LPCCLK0 <16>

LPC_CLK0_EC <26> CLK_PCI_DB <16>

10/04 Add 100p(C396) on H_PWRGD_L

T31

reserve C359 for RF

PAD

Tock 2010/12/28

12

10K_0402_5%

2

13

D

LPC_CLK0_EC

RTC_32KHO

Y1

4

NC

OSC

1

NC

OSC

32.768KHZ_12.5PF_Q13MC14610002

RTC_32KHI

12

R129

2

C396

C396 100P_0402_50V8J

100P_0402_50V8J

1

C396 near to PR12 Michael 2010/11/18

1

C359

C359 10P_0402_50V8J

10P_0402_50V8J

2

10/07 Change R140 from 560 to 1k ohm

1 2

R140 1K_0402_5%R140 1K_0402_5%

+RTCBATT

12

W=20mil

@

CLRP1

@CLRP1

SHORT PADS

For Clear CMOS, near to RAM d oor

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

FCH PCIE/PCI/ACPI/LPC/RTC

P1VE6 Schematics

E

3

2

H_PWRGD_L <36>

12 37Thursday, March 17, 2011

of

+5VALW

1.0

B

Dr-Bios.com

FCH_SIC

FCH_SID

USB_OC5# USB_OC4#

1 2

FCH_PCIE_WAKE#<18,20,21>

H_THERMTRIP#<4>

EC_RSMRST#<26>

LAN_CLKREQ#<18>

FCH_SMCLK0<7,8,20,21> FCH_SMDAT0<7,8,20,21>

WWAN_CLK REQ#<20>

WLAN_CLKREQ#<21>

8/22 Delete Net : R161 R162

R166 33_0402_5%R166 33_0402_5%

1 2

R168 33_0402_5%R168 33_0402_5%

1 2

R173 33_0402_5%R173 33_0402_5%

1 2

R174 33_0402_5%

1

R177 10K_0402_5%R177 10K_0402_5%

1 2

EC_SMI#

C441

C441 100P_0402_50V8J

100P_0402_50V8J

@

FCH_PCIE_WAKE#PCI_PME#

C442

C442 100P_0402_50V8J

100P_0402_50V8J

R180 10K_0402_5%R180 10K_0402_5%

Board ID

P1VE6

@

mount

P1VS6

B

PCI_PME#<26>

SLP_S3#<26> SLP_S5#<26>

PBTN_OUT#<26>

GATEA20<26>

KB_RST#<26> EC_SCI#<26>

EC_SMI#<26>

FCH_SPKR<17>

EC_LID_OUT#<26>

USB_OC1#<25>

USB_OC0#<24>

2

R175 10K_04 02_5%

1

R176 10K_04 02_5%R176 10K_04 02_5%

1 2

R181 10K_040 2_5%R181 10K_0402_5%

2

1 2

T23 PADT23 PAD

T24 PAD

FCH_PWRGD

T20PADT20PAD

T21PADT21PAD

T22PADT22PAD

NB_PWRGD

FCH_SMCLK1

FCH_SMDAT1

USB_OC7#

USB_OC5#

USB_OC4#

USB_OC3#

USB_OC2#

HDA_BITCLK

HDA_SDOUT

HDA_SDIN0

HDA_SYNC

HDA_RST#

U5A

J2

PCI_PME_L/GEVENT4_L

K1

RI_L/GEVENT22_L

D3

SPI_CS3_L/GBE_STAT1/GEVENT21_L

F1

SLP_S3_L

H1

SLP_S5_L

F2

PWR_BTN_L

H5

PWR_GOOD

G6

SUS_STAT_L

B3

TEST0

C4

TEST1/TMS

F6

TEST2

AD21

GA20IN/GEVENT0_L

AE21

KBRST_L/GEVENT1_L

K2

LPC_PME_L/GEVENT3_L

J29

LPC_SMI_L/GEVENT23_L

H2

GEVENT5_L

J1

SYS_RESET_L/GEVENT19_L

H6

WAKE_L/GEVENT8_L

F3

IR_RX1/GEVENT20_L

J6

THRMTRIP_L/SMBALERT_L/GEVEN T2_L

AC19

NB_PWRGD

G1

RSMRST_L

AD19

CLK_REQ4_L/SATA_IS0_L/GPIO64

AA16

CLK_REQ3_L/SATA_IS1_L/GPIO63

AB21

SMARTVOLT1/SATA_IS2_L/GPIO50

AC18

CLK_REQ0_L/SATA_IS3_L/GPIO60

AF20

SATA_IS4_L/FANOUT3/GPIO55

AE19

SATA_IS5_L/FANIN3/GPIO59

AF19

SPKR_GPIO66

AD22

SCL0_GPIO43

AE22

SDA0_GPIO47

F5

SCL1_GPIO227

F4

SDA1_GPIO228

AH21

CLK_REQ2_L/FANIN4_GPIO62

AB18

CLK_REQ1_L/FANOUT4_GPIO61

E1

IR_LED_L/LLB_L/GPIO184

AJ21

SMARTVOLT2/SHUTDOWN _L/GPIO51

H4

DDR3_RST_L/GEVENT7_L

D5

GBE_LED0/GPIO183

D7

GBE_LED1/GEVENT9_L

G5

GBE_LED2/GEVENT10_L

K3

GBE_STAT0/GEVENT11_L

AA20

CLK_REQG_L/GPIO65_OSCIN

H3

BLINK/USB_OC7_L/GEVENT18_L

D1

USB_OC6_L/IR_TX1/GEVENT6_L

E4

USB_OC5_L/IR_TX0/GEVENT17_L

D4

USB_OC4_L/IR_RX0/GEVENT16_L

E8

USB_OC3_L/AC_PRES/TDO/GEVENT15_L

F7

USB_OC2_L/TCK/GEVENT14_L

E7

USB_OC1_L/TDI/GEVENT13_L

F8

USB_OC0_L/TRST_L/GEVENT12_L

M3

AZ_BITCLK

N1

AZ_SDOUT

L2

AZ_SDIN0/GPIO167

M2

AZ_SDIN1/GPIO168

M1

AZ_SDIN2/GPIO169

M4

AZ_SDIN3/GPIO170

N2

AZ_SYNC

P2

AZ_RST_L

T1

GBE_COL

T4

GBE_CRS

L6

GBE_MDCK

L5

GBE_MDIO

T9

GBE_RXCLK

U1

GBE_RXD3

U3

GBE_RXD2

T2

GBE_RXD1

U2

GBE_RXD0

T5

GBE_RXCTL/RXDV

V5

GBE_RXERR

P5

GBE_TXCLK

M5

GBE_TXD3

P9

GBE_TXD2

T7

GBE_TXD1

P7

GBE_TXD0

M7

GBE_TXCTL/TXEN

P4

GBE_PHY_PD

M9

GBE_PHY_RST_L

V7

GPIO187

GPIO188

GPIO189 GPIO190

GPIO191GPIO191

GPIO192GPIO192

GBE_PHY_INTR

E23

PS2_DAT/SDA4/GPIO187

E24

PS2_CLK/SCL4/GPIO188

F21

SPI_CS2_L/GBE_STAT2/GPIO166

G29

FC_RST_L/GPO160

D27

PS2KB_DAT/GPIO189

F28

PS2KB_CLK/GPIO190

F29

PS2M_DAT/GPIO191

E27

PS2M_CLK/GPIO192

S IC 218-0792006 A13 HUDSON-M1 FCBGA 0FA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

C397

2

10K_0402_5%

2

12

P0@

R406

10K_0402_5%

12

P1@

R407

1K_0402_5%

A

USB_OC0#

USB_OC3# USB_OC2#

FCH_PCIE_WAKE#

EC_LID_OUT#

WWAN_CLK REQ#

LAN_CLKREQ#

WLAN_CLKREQ#

NB_PWRGD

FCH_SMCLK0

FCH_SMDAT0

R159 0_0402_5%@R159 0_0402_5%@

R160 0_0402_5%R160 0_0402_5%

4

Y

2

@

C202

1

.1U_0402_16V7K

USB_OC7#

USB_OC1#

FCH_SMCLK1

FCH_SMDAT1

EC_RSMRST#

HDA_BITCLK

HDA_SDIN0

HDA_SDOUT

HDA_BITCLK_AUDIO

+3VALW +3VALW

12

@

R409

10K_0402_5%

12

R408

1K_0402_5%

+3VALW

Reserve C418 for KB_RST#, C426 for PBTN_OUT Michael 2010/11/18

KB_RST# PBTN_OUT#

1

C418

C418 100P_0402_50V8J

100P_0402_50V8J

2

@

Reserve C417 for EC_RSMRST# Michael 2010/11/18

12

+3VS

@

C201 .1U_0402_16V 7K

1 2

5

2

P

B

1

A

G

NC7SZ08P5X_NL_SC70-5

3

@

U6

1

2

Reserve C358 for RF Tock 2010/12/28

3G@

C358

3G@C358

22P_0402_50V8J

12

@

R411

10K_0402_5%

GPIO189 GPIO190

12

R410

1K_0402_5%

Change R145, R147, R151, R152 to RP4 Michael 2010/12/23

Change RP4 to R145, R147, R151, R152 for layout Tock 2010/12/27

1 2

R145 10K_040 2_5%R145 10K_0402_5%

1 2

R147 10K_040 2_5%R147 10K_0402_5%

1 2

R151 10K_040 2_5%R151 10K_0402_5%

1 2

R152 10K_040 2_5%R152 10K_0402_5%

1

C426

C426 100P_0402_50V8J

100P_0402_50V8J

2

@

R148 10K_040 2_5%@R148 10K_0402_5%@

+3VALW

EC_RSMRST#

1

C417

C417 100P_0402_50V8J

100P_0402_50V8J

2

@

8/31 Delete Net : SATA_DET#

ICH_POK <26>

VGATE <26,36>

Reserve C422 for ICH_POK Michael 2010/11/18

C422

C422 100P_0402_50V8J

100P_0402_50V8J

@

USB_OC1#

1

C474

C474 100P_0402_50V8J

100P_0402_50V8J

2

Reserve C474 for USB_OC1# Tock 2011/01/07

HDA_BITCLK_AUDIO<17> HDA_SDOUT_AUDIO<17>

HDA_SDIN0<17>

HDA_SYNC_AUDIO<17>

HDA_RST_AUDIO#<17>

EC_SCI#

1

2

1

2

1

2

Reserve C427 , C440, C441, C442, C445 for SCI, SMI, PCIE_WAKE#, GATE20, PCI_PME# Michael 2010/11/18

C440

C440 100P_0402_50V8J

100P_0402_50V8J

@

GATEA20

C427

C427 100P_0402_50V8J

100P_0402_50V8J

@

C445

C445 100P_0402_50V8J

100P_0402_50V8J

@

+3VALW

1

2

1

2

10/27 Change R408 R410 from @ to mount

10/28 Add R413 R414 on GPIO192 for project ID

+3VALW

Change to RP3 to R150 , R153 , R154 , R161 Tock 2010/12/30

1 2

R150 10K_040 2_5%R150 10K_0402_5%

1 2

R153 10K_040 2_5%R153 10K_0402_5%

1 2

R154 10K_040 2_5%R154 10K_0402_5%

1 2

R161 10K_040 2_5%R161 10K_0402_5%

@

1 2

R144 10K_0402_5%

Swap net of RP3 & RP5 for layout

1 1

2 2

3 3

4 4

Tock 2010/12/27

+3VS

1 2

R359 10K_0402_5%R359 10K_0402_5%

1

R155 10K_0402_5%

1 2

R156 10K_0402_5%R156 10K_0402_5%

1 2

R157 4.7K_0402_5%R157 4.7K_0402_5%

1

R149 2.2K_0402_5%

1 2

R158 2.2K_0402_5%R158 2.2K_0402_5%

8/31 Pull up 10k(R359) to +3VS on WWAN_CLKREQ#

Reserve C431 for H_THERMTRIP# Michael 2010/11/18

H_THERMTRIP#

1

C431

C431 100P_0402_50V8J

100P_0402_50V8J

2

FCH_PWRGD<36>

100P_0402_50V8J

+3VALW

R162

1

R186

1 2

R164

1 2

R163

1 2

change RP5 to R162 , R163 , R164 , R186 Tock 2010/12/30

1 2

R165 2.2K_0402_5%R165 2.2K_0402_5%

@

1 2

R170 10K_0402_5%

@

1 2

R171 10K_0402_5%

1

R172 10K_0402_5%

1 2

C358 10P_0402_50V8J

N3G@

co-lay 22P on C358 for 3G @ for RF solution Tock 2011/03/16

Pull-down for e nable high performanc e mode 20100527 (requi red for M1)

+3VALW

12

@

R414

10K_0402_5%

12

R413

1K_0402_5%

R406 R407

change R407,R408,R410,R413 from 10K to 1K 11/26 Tock

change R406 BOM to P0@ , R407 BOM to P1@ 2011/01/04 Tock

A

mount

@

C

USB MISC

ACPI/WAKE UP EVENTS

GPIO

HD AUDIO

GBE LAN

2010/11/09 2012/11/09

C

USBCLK/14M_25M_48M_OSC

USB OC

EC_PWM0/EC_TIMER 0/GPIO197 EC_PWM1/EC_TIMER 1/GPIO198

EC_PWM2/EC_TIMER 2/GPIO199 EC_PWM3/EC_TIMER 3/GPIO200

Compal Secret Data

USB 1.1

USB_FSD1P/GPIO186

USB_FSD0P/GPIO185

USB 2.0

SCL3_LV/GPIO195

SDA3_LV/GPIO196

EMBEDDED CTRL

KSO_10/GPIO219 KSO_11/GPIO220

KSO_12/GPIO221 KSO_13/GPIO222

KSO_14/GPIO223 KSO_15/GPIO224

KSO_16/GPIO225 KSO_17/GPIO226

Deciphered Date

USB_RCOMP

USB_FSD1N

USB_FSD0N

USB_HSD13P USB_HSD13N

USB_HSD12P USB_HSD12N

USB_HSD11P USB_HSD11N

USB_HSD10P USB_HSD10N

USB_HSD9P USB_HSD9N

USB_HSD8P USB_HSD8N

USB_HSD7P USB_HSD7N

USB_HSD6P USB_HSD6N

USB_HSD5P USB_HSD5N

USB_HSD4P USB_HSD4N

USB_HSD3P USB_HSD3N

USB_HSD2P USB_HSD2N

USB_HSD1P USB_HSD1N

USB_HSD0P USB_HSD0N

SCL2/GPIO193

SDA2/GPIO194

KSI_0/GPIO201 KSI_1/GPIO202

KSI_2/GPIO203 KSI_3/GPIO204

KSI_4/GPIO205 KSI_5/GPIO206

KSI_6/GPIO207 KSI_7/GPIO208

KSO_0/GPIO209 KSO_1/GPIO210

KSO_2/GPIO211 KSO_3/GPIO212

KSO_4/GPIO213 KSO_5/GPIO214

KSO_6/GPIO215 KSO_7/GPIO216

KSO_8/GPIO217 KSO_9/GPIO218

D

A10

G19

USB_RCOMP

R146

1 2

11.8K_0402_1%

10mils and <1"

J10 H11

H9 J8

B12 A12

F11 E11

E14 E12

J12 J14

A13 B13

D13 C13

G12 G14

G16 G18

D16 C16

B14 A14

E18 E16

J16 J18

B17 A17

A16 B16

GPIO193

D25 F23

B26 E26

F25 E22

F22 E21

G24 G25

E28 E29

D29 D28

C29 C28

B28 A27

B27 D26

A26 C26

A24 B25

A25 D24

B24 C24

B23 A23

D22 C22

A22 B22

D

R167 10K_040 2_5%R167 10K_0402_5%

GPIO194GPIO194

R169 10K_040 2_5%

2

EC_PWM2

EC_PWM3

8/31 Change R182 from mount to @ Change R183 from @ to mount

9/15 Change R178 from @ to mount

9/15 Update USB Port List

9/1 Update USB Port List

8/23 USB port8 link to SIM

USB20_P9 <20>

USB20_N9 <20>

USB20_P8 <21> USB20_N8 <21>

USB20_P7 <20> USB20_N7 <20>

USB20_P6 <19> USB20_N6 <19>

USB20_P5 <9> USB20_N5 <9>

USB20_P4 <20> USB20_N4 <20>

USB20_P3 <20> USB20_N3 <20>

USB20_P2 <25> USB20_N2 <25>

USB20_P1 <24> USB20_N1 <24>

USB20_P0 <24> USB20_N0 <24>

12

1

FCH_SIC <4>

FCH_SID <4>

Internal Pull-Up available

EC_PWM3 EC_PWM2 ROM TYPE

NC

NC NC

L

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

FCH HDA/USB/ACPI

E

WWAN

WiMax

Bluetooth

Card Reader

Camera

SIM

WWAN

USB Conn.(RS) JUSB1

USB Conn.(LS) IO

R178

1 2

10K_0402_5%

EC_PWM3

EC_PWM2

12

R182

@

2.2K_0402_5%

L

SPI ROM

Reserved

L

H

Reserved

LPC ROM

P1VE6 Schematics

E

+3VALW

10K_0402_5%

2.2K_0402_5%

13 37Thursday, March 17, 2011

R179

@

1 2

12

R183

*

1.0

D

Dr-Bios.com

+3VS

12

R415

@

10K_0402_5%

GPIO56

12

R416

@

10K_0402_5%

10/29 Add R415(@), R416(@) on GPIO56

9/9 Change R189 from mount to @

9/15 Change R189 from @ to mount

APU_ALERT#_FCH <4>

VIN6/GBE_STAT3/ GPIO181 Enable integrat ed pull-down/u p and leave unc onnected

@

C406 100P_0402_50V8J

1 2

10/05 Add 100p(C406) on APU_ALERT#_FCH

Change R193, R188, R197, R198 to RP7 Michael 2010/12/23

Change RP7 to R196 , R197 , R199 , R236 Tock 2010/12/30

Change R199, R196, R187, R192 to RP8 Michael 2010/12/23

Change RP8 to R237 , R239 , R240 , R245 Tock 2010/12/30

APU_ALERT#_FCH

FC_CLK

FC_FBCLKOUT

FC_FBCLKIN

FANOUT0/GPIO52 FANOUT1/GPIO53

FANOUT2/GPIO54

FANIN0/GPIO56

FANIN1/GPIO57 FANIN2/GPIO58

TEMP_COMM

VIN0/GPIO175

VIN1/GPIO176 VIN2/GPIO177

VIN3/GPIO178 VIN4/GPIO179

VIN5/GPIO180

NC1

NC2

C

AH28 AG28

AF26

AF28

AG29 AG26

AF27

U5_AE29

AE29

AF29 AH27

AJ27 AJ26

AH25 AH24

AG23 AH23

AJ22 AG21

AF21 AH22

AJ23 AF23

AJ24 AJ25

AG25 AH26

8/21 Delete Net : ODD_EN 8/22 Delete Net : BT_OFF#, WL_OFF#

W5 W6

Y9

GPIO56

W7

V9 W8

TEMPIN0

B6

TEMPIN1

A6

TEMPIN2

A5 B5

C7

GPIO175

A3

GPIO176

B4

GPIO177

A4

GPIO178

C5

GPIO179

A7

GPIO180

B7

GPIO181

B8

GPIO182

A8

G27

GPIO177

Y2

TEMPIN2 TEMPIN0

GPIO180

11/01 Add Net U5_AE29 on U5.AE29

2011/0103 delete Net U5_AE29 on U5.AE29

2011/01/28 Add Net U5_AE29 on U5.AE29 for Layout test point

T28

PAD

R189 10K_040 2_5%R189 10K_0402_5%

R191 10K_040 2_5%R191 10K_0402_5%

R194 10K_040 2_5%R194 10K_0402_5%

R198 10K_040 2_5%@R198 10K_0402_5%@

R196 10K_040 2_5%R196 10K_0402_5%

R197 10K_040 2_5%R197 10K_0402_5%

R199 10K_040 2_5%R199 10K_0402_5%

R236 10K_040 2_5%R236 10K_0402_5%

GPIO182

R237 10K_040 2_5%R237 10K_0402_5%

GPIO179

R239 10K_040 2_5%R239 10K_0402_5%

TEMPIN1

R240 10K_040 2_5%R240 10K_0402_5%

GPIO176

R245 10K_040 2_5%R245 10K_0402_5%

12

SATA_CALRP

SATA_CALRN

25M_SATA_X1

25M_SATA_X2

GPIO161

B

U5B

AH9

SATA_TX0P

AJ9

SATA_TX0N

AJ8

SATA_RX0N

AH8

SATA_RX0P

AH10

SATA_TX1P

AJ10

SATA_TX1N

AG10

SATA_RX1N

AF10

SATA_RX1P

AG12

SATA_TX2P

AF12

SATA_TX2N

AJ12

SATA_RX2N

AH12

SATA_RX2P

AH14

SATA_TX3P

AJ14

SATA_TX3N

AG14

SATA_RX3N

AF14

SATA_RX3P

AG17

SATA_TX4P

AF17

SATA_TX4N

AJ17

SATA_RX4N

AH17

SATA_RX4P

AJ18

SATA_TX5P

AH18

SATA_TX5N

AH19

SATA_RX5N

AJ19

SATA_RX5P

AB14

SATA_CALRP

AA14

SATA_CALRN

AD11

SATA_ACT_L/GPIO67

AD16

SATA_X1

AC16

SATA_X2

J5

SPI_DI/GPIO164

E2

SPI_DO/GPIO163

K4

SPI_CLK/GPIO162

K9

SPI_CS1_L/GPIO165

G2

ROM_RST_L/GPIO161

S IC 218-0792006 A13 HUDSON-M1 FCBGA 0FA

SERIAL ATA

SPI ROM

FC_OE_L/GPIOD145

FC_AVD_L/GPIOD146

FC_WE_L/GPIOD148

FC_CE1_L/GPIOD149 FC_CE2_L/GPIOD150

FC_INT1/GPIOD144

GPIOD

FC_INT2/GPIOD147

FC_ADQ0/GPIOD128 FC_ADQ1/GPIOD129

FC_ADQ2/GPIOD130 FC_ADQ3/GPIOD131

FC_ADQ4/GPIOD132 FC_ADQ5/GPIOD133

FC_ADQ6/GPIOD134 FC_ADQ7/GPIOD135

FC_ADQ8/GPIOD136 FC_ADQ9/GPIOD137

FC_ADQ10/GPIOD138 FC_ADQ11/GPIOD139

FC_ADQ12/GPIOD140 FC_ADQ13/GPIOD141

FC_ADQ14/GPIOD142 FC_ADQ15/GPIOD143

HW MONITOR

TEMPIN0/GPIO171 TEMPIN1/GPIO172

TEMPIN2/GPIO173

TEMPIN3/TALERT_L/GPIO174

VIN6/GBE_STAT3/GPIO181

VIN7/GBE_LED3/GPIO182

A

1 1

SATA_ITX_C_DRX_P0

SATA_ITX_C_DRX_N0

HDD

C203 0.01U_0402_ 16V7KC203 0.01U_0402_16V7K

SATA_ITX_DRX_P0<22>

SATA_ITX_DRX_N0<22>

SATA_DTX_C_IRX_N0<22>

SATA_DTX_C_IRX_P0<22>

1 2

C204 0.01U_0402_ 16V7KC204 0.01U_0402_16V7K

1 2

8/21 Delete C205~C208 (No ODD ESATA function)

2 2

9/7 Change SATA_CALRN from +1.1VS to +AVDD_SATA

10 mils and < 1"

R184 1K_0402_1%R184 1K_0402_1%

1 2

R185 931_0402_1%R185 931_0402_1%

+AVDD_SATA

HDD_LED#<22>

+3VS

3 3

1 2

R190 10K_0402_5%R190 10K_0402_5%

1 2

C209

@

22P_0402_50V8J

C210

@

22P_0402_50V8J

1 2

12

Y3

@

25MHZ_20PF_7A25000012

T25 PADT25 PAD

@

1M_0603_5%

R195

8/31 remove FCH SPI ROM

E

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

A

B

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/11/09 2012/11/09

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

FCH-SATA/SPI

P1VE6 Schematics

14 37Thursday, March 17, 2011

E

1.0

A

Dr-Bios.com

B

C

D

E

+3VS

R346

1 2

0_0603_5%

1 1

+1.8VS

R207

1 2

0_0603_5%

+1.1VS

L17

FBMA-L11-201209-221LMA30T_0805

2 2

L18

2

+3VALW

FBMA-L11-201209-221LMA30T_0805

L20

+1.1VALW

3 3

2

FBMA-L11-160808-221LMT_2P

1

C213

GPIO I/F implem ented: tied to +1.8V_S0 GPIO I/F not im plemented: tie d to

+1.8V_S0 or 0 o hm to ground

12

R208

@

+3VS

12

1

C241

1

2

C215

C214

2

1

.1U_0402_16V7K

22U_0805_6.3V6M

2

C229

C230

1

0_0402_5%

4.7U_0603_6.3V6K

L16

FBMA-L11-160808-221LMT_2P

C233

1

2

10U_0603_6.3V6M

12

1

C234

2

22U_0805_6.3V6M

1U_0402_6.3V6K

1

C243

C242

2

10U_0603_6.3V6M

2

1

.1U_0402_16V7K

2

1

.1U_0402_16V7K

2

C235

1

C244

2

1U_0402_6.3V6K

1

C249

2

42mA

+VDDIO_33

2

C216

1

.1U_0402_16V7K

+VDDIO_18_FC

0.15mA

2

C231

1

.1U_0402_16V7K

22mA

+VDDPL33_PCIE

1

C232

1115mA

2

+PCIE_VDDAN

2.2U_0603_6.3V6K

2

C236

15mA

1

.1U_0402_16V7K

+VDDPL_33_SATA

+AVDD_SATA

1354mA

534mA

+AVDD_USB

1

C245

2

.1U_0402_16V7K

1U_0402_6.3V6K

88mA

+VDDAN_11_USB

2

C250

1

.1U_0402_16V7K

2.2U_0603_6.3V6K

U5C

AH1

VDDIO_33_PCIGP_1

V6

VDDIO_33_PCIGP_2

Y19

VDDIO_33_PCIGP_3

AE5

VDDIO_33_PCIGP_4

AC21

VDDIO_33_PCIGP_5

AA2

VDDIO_33_PCIGP_6

AB4

VDDIO_33_PCIGP_7

AC8

VDDIO_33_PCIGP_8

AA7

VDDIO_33_PCIGP_9

AA9

VDDIO_33_PCIGP_10

AF7

VDDIO_33_PCIGP_11

AA19

VDDIO_33_PCIGP_12

AF22

VDDIO_18_FC_1

AE25

VDDIO_18_FC_2

AF24

VDDIO_18_FC_3

AC22

VDDIO_18_FC_4

AE28

VDDPL_33_PCIE

U26

VDDAN_11_PCIE_1

V22

VDDAN_11_PCIE_2

V26

VDDAN_11_PCIE_3

V27

VDDAN_11_PCIE_4

V28

VDDAN_11_PCIE_5

V29

VDDAN_11_PCIE_6

W22

VDDAN_11_PCIE_7

W26

VDDAN_11_PCIE_8

AD14

VDDPL_33_SATA

AJ20

VDDAN_11_SATA_1

AF18

VDDAN_11_SATA_4

AH20

VDDAN_11_SATA_2

AG19

VDDAN_11_SATA_3

AE18

VDDAN_11_SATA_5

AD18

VDDAN_11_SATA_6

AE16

VDDAN_11_SATA_7

A18

VDDAN_33_USB_S_1

A19

VDDAN_33_USB_S_2

A20

VDDAN_33_USB_S_3

B18

VDDAN_33_USB_S_4

B19

VDDAN_33_USB_S_5

B20

VDDAN_33_USB_S_6

C18

VDDAN_33_USB_S_7

C20

VDDAN_33_USB_S_8

D18

VDDAN_33_USB_S_9

D19

VDDAN_33_USB_S_10

D20

VDDAN_33_USB_S_11

E19

VDDAN_33_USB_S_12

C11

VDDAN_11_USB_S_1

D11

VDDAN_11_USB_S_2

S IC 218-0792006 A13 HUDSON-M1 FCBGA 0FA

POWER

PCI/GPIO I/O

FLASH I/O

PCI EXPRESS

SERIAL ATA

USB I/O

VDDCR_11_1

VDDCR_11_2 VDDCR_11_3

VDDCR_11_4 VDDCR_11_5

VDDCR_11_6 VDDCR_11_7

VDDCR_11_8 VDDCR_11_9

VDDAN_11_CLK_1 VDDAN_11_CLK_2

VDDAN_11_CLK_3 VDDAN_11_CLK_4

VDDAN_11_CLK_5 VDDAN_11_CLK_6

VDDAN_11_CLK_7 VDDAN_11_CLK_8

VDDRF_GBE_S

VDDIO_33_GBE_S

GBE LAN

VDDCR_11_GBE_S_1 VDDCR_11_GBE_S_2

VDDIO_GBE_S_1 VDDIO_GBE_S_2

VDDIO_33_S_1 VDDIO_33_S_2

VDDIO_33_S_3 VDDIO_33_S_4

VDDIO_33_S_5 VDDIO_33_S_6

VDDIO_33_S_7 VDDIO_33_S_8

CORE S5CORE S0 CLKGEN I/O 3.3V_S5 I/O

VDDCR_11_S_1 VDDCR_11_S_2

VDDIO_AZ_S

VDDCR_11_USB_S_1

VDDCR_11_USB_S_2

VDDPL_33_SYS

PLL

VDDPL_11_SYS_S

VDDPL_33_USB_S

VDDAN_33_HWM _S

VDDXL_33_S

N13

R15 N17

U13 U17

V12 V18

W12 W18

+VDDAN_11_CLK

K28 K29

J28 K26

J21 J20

K21 J22

V1

M10

L7 L9

M6 P8

A21 D21

B21 K10

L10 J9

T6 T8

F26 G26

M8

A11

B11

M21

L22

F19

D6

+VDDXL_33_S

L20

5mA

790mA

382mA

49mA

58mA

+VDDCR_11_USB

1

C217

2

1

C224

2

+VDDIO_33_S

15mA

+VDDIO_AZ

+VDDPL33

+VDDPL11

+AVDD_USB

+VDDAN33_HWM

1

C251

2

1

C218

2

.1U_0402_16V7K

1

C225

2

.1U_0402_16V7K

1

C237

2

2.2U_0603_6.3V6K

1

C239

2

1U_0402_6.3V6K

46mA

65mA

16mA

12mA

FBMA-L11-160808-221LMT_2P

2.2U_0603_6.3V6K

+1.1VS

1

C219

C220

2

1U_0402_6.3V6K

1

C227

C226

2

1U_0402_6.3V6K

1

C221

2

1U_0402_6.3V6K

10U_0603_6.3V6M

L15

1

C228

2

1U_0402_6.3V6K

L15

FBMA-L11-201209-221LMA30T_0805

22U_0805_6.3V6M

8/23 Add R346 R347, +VDDIO_33, +VDDIO_33_S

R347

1 2

0_0603_5%

1

C238

2

2.2U_0603_6.3V6K

0_0603_5%

165mA

1

C240

2

1U_0402_6.3V6K

L21

+1.1VALW

1

C247

C248

C246

2

.1U_0402_16V7K

12

+3VS

C248

2

.1U_0402_16V7K

+1.1VS

1

+

C222

330U_2.5V_M

12

+1.1VS

2

SF000002Z00

8/25 Change C222 from poly-cap to E-cap (SF000002Z00)

+3VALW

L19

1

2

1 2

0_0805_5%

10U_0603_6.3V6M

+1.1VALW

1

C223

2

10U_0603_6.3V6M

For 3V AZ device

+AVDD_SATA

1

C257

2

.1U_0402_16V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

+VDDPL_33_SATA

+VDDPL11

+VDDPL33

+1.1VS

+3VALW

L23

+3VS

+1.1VALW

4 4

+3VS

L23

FBMA-L11-160808-221LMT_2P

C252 2.2U_0603_6.3V6KC252 2.2U_0603_6.3V6K

1 2

L24

FBMA-L11-160808-221LMT_2P

C259 2.2U_0603_6.3V6KC259 2.2U_0603_6.3V6K

1 2

L27

FBMA-L11-160808-221LMT_2P

C262 2.2U_0603_6.3V6KC262 2.2U_0603_6.3V6K

1 2

L22

L25

HWM@

12

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-160808-221LMT_2P

L25

0_0603_5%

SD013000080

NONHWM@

1

C253

1

C260

2

HWM@

HWM@ C260

1

C254

2

22U_0805_6.3V6M

1U_0402_6.3V6K

+VDDAN33_HWM

2

9/3 Change L26 to L25(NONHWM@)

C261

1

.1U_0402_16V7K

2.2U_0603_6.3V6K

1

C256

C255

2

1U_0402_6.3V6K

A

B

+VDDIO_AZ

1

2

C

@

1 2

R209 0_0603_5%

C258

2.2U_0603_6.3V6K

2010/11/09 2012/11/09

+3VALW

+3VS

1 2

R210 0_0603_5%R210 0_0603_5%

change +1.5V to +3VS and mount R210 reserve R209 11/26 Tock

Wake On Ring Not Implemented: Tied to a +1.5V_S0 or +3.3V_S0 rail.

VDDIO_AZ_S and audio CODEC chip HD link IO power rail should be at same voltage level/domain.

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

FCH PWR

P1VE6 Schematics

15 37Thursday, March 17, 2011

E

1.0

3

Dr-Bios.com

Check Internal PU/PD

PCI_CLK1

ALLOW PCIE GEN2

PCI_CLK3

USE DEBUG STRAP

PCI_CLK4

Reserved

LPC_CLK0

internal EC ENABLE

*

FORCE PCIE GEN1

IGNORE DEBUG STRAP

CLKGEN Mode

Internal

internal EC DISABLE

* * *

12

R214

@

10K_0402_5%

12

R219

10K_0402_5%

Disable I2C ROM

+3VALW

R215

R220

@

12

10K_0402_5%

12

10K_0402_5%

+3VS +3VS

R211

10K_0402_5%

R216

@

10K_0402_5%

PCI_AD26

ILA AUTORUN Disabled

+3VS +3VALW

12

R212

R213

@

10K_0402_5%

12

R217

12

R218

10K_0402_5%

PCI_AD25 PCI_AD24

Selects FC PLL

* * * * *

ILA AUTORUN

FC PLL bypassed

Getting Value from I2C EPROM

AJ2

A28 A2

E5 D23

E25 E6

F24 N15

R13 R17

T10 P10

V11 U15

M18 V19

M11 L12

L18 J7

P3 V4

AD6 AD4

AB7 AC9

V8 W9

W10 AJ28

B29 U4

Y18 Y10

Y12 Y11

AA11 AA12

G4 J4

G8 G9

M12 AF25

H7 AH29

V10 P6

N4 L4

L8

M20

H23 H26

AA21 AA23

AB23 AD23

AA26 AC26

Y20 W21

W20 AE26

L21 K20

4

REQUIRED STRAPS

PULL HIGH

PULL LOW

PCI_CLK1<12>

PCI_CLK3<12> PCI_CLK4<12>

LPCCLK0<12> CLK_PCI_DB< 12>

DEBUG STRAPS

FCH M1 HAS 15K INTERNAL PU FOR PCI_AD[27:23]

PCI_AD27

USE internal

PULL HIGH

PULL LOW

PLL generated PLL CLK

BYPASS PCI PLL

5

U5D

Y14

VSSIO_SATA_1

Y16

VSSIO_SATA_2

AB16

VSSIO_SATA_3

AC14

VSSIO_SATA_4

AE12

VSSIO_SATA_5

AE14

VSSIO_SATA_6

AF9

VSSIO_SATA_7

AF11

VSSIO_SATA_8

AF13

D D

C C

B B

VSSIO_SATA_9

AF16

VSSIO_SATA_10

AG8

VSSIO_SATA_11

AH7

VSSIO_SATA_12

AH11

VSSIO_SATA_13

AH13

VSSIO_SATA_14

AH16

VSSIO_SATA_15

AJ7

VSSIO_SATA_16

AJ11

VSSIO_SATA_17

AJ13

VSSIO_SATA_18

AJ16

VSSIO_SATA_19

A9

VSSIO_USB_1

B10

VSSIO_USB_2

K11

VSSIO_USB_3

B9

VSSIO_USB_4

D10

VSSIO_USB_5

D12

VSSIO_USB_6

D14

VSSIO_USB_7

D17

VSSIO_USB_8

E9

VSSIO_USB_9

F9

VSSIO_USB_10

F12

VSSIO_USB_11

F14

VSSIO_USB_12

F16

VSSIO_USB_13

C9

VSSIO_USB_14

G11

VSSIO_USB_15

F18

VSSIO_USB_16

D9

VSSIO_USB_17

H12

VSSIO_USB_18

H14

VSSIO_USB_19

H16

VSSIO_USB_20

H18

VSSIO_USB_21

J11

VSSIO_USB_22

J19

VSSIO_USB_23

K12

VSSIO_USB_24

K14

VSSIO_USB_25

K16

VSSIO_USB_26

K18

VSSIO_USB_27

H19

VSSIO_USB_28

Y4

EFUSE

D8

VSSAN_HWM

M19

VSSXL

P21

VSSIO_PCIECLK_1

P20

VSSIO_PCIECLK_2

M22

VSSIO_PCIECLK_3

M24

VSSIO_PCIECLK_4

M26

VSSIO_PCIECLK_5

P22

VSSIO_PCIECLK_6

P24

VSSIO_PCIECLK_7

P26

VSSIO_PCIECLK_8

T20

VSSIO_PCIECLK_9

T22

VSSIO_PCIECLK_10

T24

VSSIO_PCIECLK_11

V20

VSSIO_PCIECLK_12

J23

VSSIO_PCIECLK_13

S IC 218-0792006 A13 HUDSON-M1 FCBGA 0FA

GND

VSSIO_PCIECLK_14 VSSIO_PCIECLK_15

VSSIO_PCIECLK_16 VSSIO_PCIECLK_17

VSSIO_PCIECLK_18 VSSIO_PCIECLK_19

VSSIO_PCIECLK_20 VSSIO_PCIECLK_21

VSSIO_PCIECLK_22 VSSIO_PCIECLK_23

VSSIO_PCIECLK_24 VSSIO_PCIECLK_25

VSSIO_PCIECLK_26 VSSIO_PCIECLK_27

VSS_1

VSS_2 VSS_3

VSS_4 VSS_5

VSS_6 VSS_7

VSS_8 VSS_9

VSS_10 VSS_11

VSS_12 VSS_13

VSS_14 VSS_15

VSS_16 VSS_17

VSS_18 VSS_19

VSS_20 VSS_21

VSS_22 VSS_23

VSS_24 VSS_25

VSS_26 VSS_27

VSS_28 VSS_29

VSS_30 VSS_31

VSS_32 VSS_33

VSS_34 VSS_35

VSS_36 VSS_37

VSS_38 VSS_39

VSS_40 VSS_41

VSS_42 VSS_43

VSS_44 VSS_45

VSS_46 VSS_47

VSS_48 VSS_49

VSS_50 VSS_51

VSS_52

VSSPL_SYS

2

CLK_PCI_DB

Internal CLKGEN Mode

*

External CLKGEN Mode

9/13 Change R211 from mount to @, R216 from @ to mount

9/13 Change R211 from @ to mount, R216 from mount to @

PCI_AD23 Enable ROM Straps

Required Setting

Reserved

PCI_AD27<12> PCI_AD26<12>

PCI_AD25<12> PCI_AD24<12>

PCI_AD23<12>

R221

Enabled

@

A A

check defaultCheck AD29,AD28 strap function

@

1

12

R222

2.2K_0402_5%

@

12

R223

R224

2.2K_0402_5%

@

12

R225

2.2K_0402_5%

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

2010/11/09 2012/11/09

Compal Secret Data

Title

Deciphered Date

3

2

Title

Size Document Nu mber Rev

B

Date: Sheet of

Compal Electronics, Inc.

FCH-VSS/Strap

P1VE6 Schematics

16 37Thursday, March 17, 2011

1

1.0

5

Dr-Bios.com

1 2

+3VS +3VS_AUDIO

RA340 0_0805_5%RA340 0_0805_5%

Remove RA55,RA5 6 and add RA34 0 for power con sumption 11/26 Tock

D D

+3VS_AUDIO

10U_0603_6.3V6M

CA42

CA43

CA38

CA39

1

2

HP_LEFT

HP_RIGHT

1 2

2.2U_0603_6.3V6K

1 2

2.2U_0603_6.3V6K

1

CA2

2

MIC1_C_L

1 2

2.2U_0603_6.3V6K

MIC1_C_R

1 2

2.2U_0603_6.3V6K

Change RA31/ RA 32 package to 0402 Michael 2010/11 /18

@

+1.5VS

+3VS_AUDIO

9/3 Change CA38~ CA43 from 4.7U to 2.2U Change RA16 from 1k to 100 ohm

C C

Add INT Mic cir cuit on port F Tock 2010/11/26

change RA17 fro m 0 ohm to 100 ohm Tock 2011/01/03

B B

+3VS_AUDIO

INT_MIC0

1 2

RA31 0_0402_5%

1 2

RA32 0_0402_5%

0.1U_0402_16V4Z

RA17

1 2

100_0402_1%

MIC1_L<24>

MIC1_R<24>

1

CA22

CA23

2

10U_0603_6.3V6M

HP_LEFT<24 >

HP_RIGHT<24>

MIC0_R MIC0_C_L

1U_0402_6.3V6K

MIC1_L

MIC1_R

+MIC1_VREFO

change RA19 fro m 10K to 33 oh m Tock 2011/02/11

reserve DA21,DA 22 by vender r eview Tock 2010/12/08

0.1U_0402_16V4Z

1

CA21

CA19

2

CA3

20 mil

+3VS_VAUX

1

2

25

26

27

28

33

34

41

42

22

23

35

36

37

2

0.1U_0402_16V4Z

UA1

0.1U_0402_16V4Z

1U_0402_6.3V6K

MIC0_C_R

20 mil

+3VS_AUDIO

HP_PLUG#<24>

MIC_PLUG#<24>

COM_MIC_PLUG#<24>

Add net GPIO_0 by vender revi ew Tock 2011/01/03

9/7 Add 0.1U (CA50) between GND & GNDA

A A

GND GNDA

HP_PLUG#

MIC_PLUG#

COM_MIC_PLUG#

1 2

CA50 0.1U_0402_16V4ZCA50 0.1U_0402_16V4Z

1 2

CA51 0.1U_0402_16V4ZCA51 0.1U_0402_16V4Z

1 2

CA52 0.1U_0402_16V4ZCA52 0.1U_0402_16V4Z

1 2

CA53 0.1U_0402_16V4ZCA53 0.1U_0402_16V4Z

1 2

CA54 0.1U_0402_16V4ZCA54 0.1U_0402_16V4Z

1 2

RA7 5.11K_0402_1%RA7 5.11K_0402_1%

12

RA34 39.2K_0402_1%RA34 39.2K_0402_1%

1 2

RA18 10K_0402_1%RA18 10K_0402_1%

RA33 20K_0402_1%RA33 20K_0402_1%

12

GPIO_0<24>

20 mil

CA10

0.1U_0402_16V4Z

Remove RA36,RA 37,RA38,RA39 Add CA51,CA52, CA53,CA54 by vender revie w Tock 2010/12/08

5

MONO_IN

EC_MUTE#<26>

SENSEA

1

CA11

2

10U_0603_6.3V6M

13

12

44

43

47

48

+AVEE

24

49

10/11 Update UA1 PN:SA000034020

10/12 Update UA1 PN:SA000034010 (-11Z)

12/08 Update UA1 PN:SA000034020 (-21Z) Tock

08/19 Follow NTUC0

40 mil

+3VS_DVDD

CA20

20 mil

+VDD_IO

1

CA24

2

4

PORTA_L

PORTA_R

VAUX_3.3

PORTD_L

PORTD_R

PORTE_L

PORTE_R

PORTF_L

PORTF_R

FLY_P

FLY_N

PORTC_L

PORTC_R

C_BIAS

PCBEEP

EXT_MUTE#

SENSE A

SENSE B

GPIO0/EAPD#

SPDIFO

AVEE

EP_GND

4

BEEP#<26>

FCH_SPKR<13>

9

21

VDD_IO

4

9/25 Add RA54~RA56

+5VS

60 mil

+5VS_AVDD

31

29

AVDD_5V

AVDD_HP

DVDD_3.3

GPIO1/SPK_MUTE#

CX20584-21Z_QFN48_7X7

RA54 0_0603_5%RA54 0_0603_5%

12

RA40

RA40 0_1206_5%

0_1206_5%

15

18

LPWR5.0

RPWR5.0

SPK_OUT_L+

SPK_OUT_L-

SPK_OUT_R+

SPK_OUT_R-

PORTB_L

PORTB_R

B_BIAS

SDATA_IN

SDATA_OUT

SYNC

RESET#

BIT_CLK

DMIC_3/4

DMIC_CLK0

DMIC_1/2

GPIO2/SPDIF2

FILT_1.8

FILT_1.65

AVDD_3.3

0.1U_0402_16V4Z

@

DA22

12

RB751V-40_SOD323-2

1 2

RA19 33_0402_5%RA19 33_0402_5%

1 2

RA20 10K_0402_5%RA20 10K_0402_5%

@

DA21

12

RB751V-40_SOD323-2

1 2

0.1U_0402_16V4Z

1

CA12

2

60 mil

+CLASSD_5V

1

2

20

CA14

0.1U_0402_16V4Z

CLASSDREF

14

16

19

17

MIC2_C_L

39

MIC2_C_R

40

38

HDA_SDIN0_AUDIO

8

6

10

11

HDA_BITCLK_AUDIO_R

7

1

DMIC_CLK_R

2

3

46

45

5

32

+LDO_OUT_3.3V

30

CA6

0.1U_0402_16V4Z

1 2

RA29 0_0402_5%RA29 0_0402_5%

+FILT_1.8V

+FILT_1.65V

1

2

11/04 Change RA19 RA20 from 47k to 10k

10K_0402_5%

Change RA54 pac kage to 0603 Michael 2010/11 /18

1

CA13

CA13 10U_0805_10V6K

10U_0805_10V6K

2

1

2

10/26 Remove SPKR+ SPKR- function

SPKL+

SPKL-

SPKR+

SPKR-

1 2

HDA_SDOUT_AUDIO <13>

HDA_SYNC_AUDIO <13>

HDA_RST_AUDIO# < 13>

1 2

@

1

CA5

2

10U_0603_6.3V6M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Int. Speaker Conn.

SPKL+

CA33

MONO_IN

1 2

0.1U_0402_16V4Z

2

@

CA34

@ CA34

100P_0402_50V8J

1

RA21

12

1

CA32

@

0.1U_0402_16V4Z

2

08/21 Follow PAV70

11/16 Change CA5,CA8,CA11,CA13,CA17,CA18,CA19,CA23,CA25, package from 0805 to 0603

11/17 Change CA13 CA17 CA18 package from 0603 to 0805

9/6 Update QA2 symbol

10/11 Change RA40 to 0 ohm (1206)

10/12 Change RA40 to 0.1 ohm (1206)

0.1U_0402_16V4Z

1

CA17

CA16

2

10U_0805_10V6K

1 2

@

CA17

2

MIC2_R

1 2

EAPD <26>

CA15

CA40

2.2U_0603_6.3V6K

CA41

2.2U_0603_6.3V6K

RA27 33_0402_5%RA27 33_0402_5%

RA28 0_0402_5%RA28 0_0402_5%

CA31

22P_0402_50V8J

1 2

RA49 90.9_0402_1%

20 mil

1U_0402_6.3V6K

CA1

+LDO_OUT_3.3V

CA1

20 mil

3

10U_0805_10V6K

1

CA18

2

RA16

1 2

100_0402_1%

@

1 2

@

CA36

22P_0402_50V8J

HDA_BITCLK_AUDIO <13>

DMIC_CLK0

DMIC_DATA0

1

2

0.1U_0402_16V4Z

2010/11/09 2012/11/09

12/08 Change RA40 to 0 ohm (1206) Tock

COM_MIC

HDA_SDIN0 <13>

CA48

22P_0402_50V8J

Layout Note: close to UA1

RA51 0_0402_5%@RA51 0_0402_5%@

1 2

RA53 0_0402_5%@RA53 0_0402_5%@

1 2

0.1U_0402_16V4Z

1

CA7

2

1

CA9

2

Compal Secret Data

SPKL-

SPKR-

20mil

10/26 Remove DA4 CA46 CA47 RA23 RA24

10/28 Add JSPK1 (2 pin)

10/28 Add DA4 CA46 CA47 RA23 RA24

COM_MIC <24>

9/1 Add CA49 RA41 on HP_SENSE

08/31 Reserve CA48(22P) on HDA_SDOUT_AUDIO

10U_0603_6.3V6M

12

1

CA8

2

10K_0402_5%

Deciphered Date

2

RA22 0_0603_5%RA22 0_0603_5%

1 2

RA25 0_0603_5%RA25 0_0603_5%

1 2

RA23 0_0603_5%RA23 0_0603_5%

1 2

RA24 0_0603_5%RA24 0_0603_5%

1 2

PJDLC05C_SOT23-3

DMIC_CLK <4,9>

DMIC_DATA <9,26>

Add INT Mic cir cuit on port F Tock 2010/11/26

@

RA26

INT_MIC0

2

3

2

3

2

DA4

DA5

1

DA4 PJDLC05C_SOT23-3

PJDLC05C_SOT23-3

1

1000P_0402_50V7K

1

CA44

2

1000P_0402_50V7K

Port Configuration

Port A: H eadphone j ack (jack shared wi th S/PDIF) Port B: I nternal MI C (mono o r stereo) Port C: M icrophone/ LI/LO jac k Port D: L ine Out ja ck (Optio nal) Port E: L ine In jac k (Option al) Port F: I nternal AM IC Port G: I nternal st ereo spea kers Port J: I nternal st ereo digi tal mic (O ptional) Port H: S /PDIF (jac k shared with headp hone)

10/28 Reserve CA57 CA58 for EMI

11/01 Change CA57, CA58 from @ to mount

Remove CA57 , C A58 Tock 2010/11/29

9/6 UA1 Pin 1 link to GNDA

9/7 Change UA1 Pin1 to GND

9/13 Add RA49 for DMIC

9/13 Add RA50~RA53 for DMIC

10/01 Remove RA50,R52

20 mil

+LDO_INT_MIC

RA15

2.2K_0402_5%

1 2

Title

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

1

2

INT_MIC0 <24 >

Compal Electronics, Inc.

1

JSPK2

SPK_L+

1

SPK_L-

2

SPK_R+SPKR+

3

SPK_R-

4

ACES_88266-04001

CONN@

1

CA47

1000P_0402_50V7K

2

RA42

1 2

1

Delete JSPK1 2010/12/15 Tock

17 37Thursday, March 17, 2011

1000P_0402_50V7K

1

CA45

2

1

CA46

2

1K_0402_5%

CA27

CA27 10U_0805_10V6K

10U_0805_10V6K

Audio Codec CX20584

P1VE6 Schematics

5

G1

6

G2

+LDO_OUT_3.3V

of

1.0

5

Dr-Bios.com

+3V_LAN

RL15 4.7K_0402_5%@

2

RL16 4.7K_0402_5%@

D D

C C

B B

A A

1

2

1

2

CL10

CL10 27P_0402_50V8J

27P_0402_50V8J

1

PLT_RST#

1

CL419

CL419 100P_0402_50V8J

100P_0402_50V8J

2

Reserve DL8 for LAN_CLKREQ# Tock 2011/01/05

RJ45_MIDI0+

RJ45_MIDI0-

RJ45_MIDI1+

RJ45_MIDI1-

change JRJ45 to DC234005300 2010/12/14 Tock

LAN_CLKREQ#_R

PLT_RST#

PCIE_FRX_DTX_P2<12>

PCIE_FRX_DTX_N2<12>

PCIE_FTX_C_DRX_P2<12>

PCIE_FTX_C_DRX_N2<12>

CLK_PCIE_LAN<12>

CLK_PCIE_LAN#<12>

LAN_CLKREQ#<13>

PLT_RST#<12,20,21,26>

LAN_WAKE#<2 6>

FCH_PCIE_WAKE#<13,20,21>

2010.08.21 Follow PAWGC

YL1

LAN_X2LAN_X1

2

1

25MHZ_20PF_7A25000012

Reserve CL419 for PLT_RST# Michael 2010/11/18

DL8

@

DL8

@

2

1

2

3

4

5

6

7

8

LAN_CLKREQ#_RLAN_CLKREQ#

1

RB751V-40_SOD323-2

JRJ45

PR1+

PR1-

PR2+

PR3+

PR3-

PR2-

PR4+

PR4-

SANTA_130451-F

LED_YELLOW_A1

LED_YELLOW_A2

CL6 .1U_0402_16V7KCL6 .1U_0402_16 V7K

CL9 .1U_0402_16V7KCL9 .1U_0402_16 V7K

1 2

RL12 0_0402_5%RL12 0_0402_5%

1 2

RL14 0_0402_5%RL14 0_0402_5%

2

CL11

27P_0402_50V8J

1

+1.7_LX

CONN@

CONN@JRJ45

LED_GREEN_B1

LED_GREEN_B2

GND

PCIE_C_RXP1

12

PCIE_C_RXN1

12

LAN_CLKREQ#_R

PLT_RST#

LAN_WAKE#

LL39

1 2

4.7UH_SIA4012-4R7M_20%

SWR@

9

LAN_ACTIVITY#_R

10

11

LAN_SK_LAN_LINK#_1

12

13

14

LANGND

1

CL39

2

0.1U_0402_16V4Z

1

CL40

2

4

UL1

23

TX_P

22

TX_N

28

RX_P

29

RX_N

26

REFCLK_P

25

REFCLK_N

17

CLKREQ#

3

PERST#

4

WAKE#

18

SMCLK

19

SMDATA

20

TESTMODE

33

GND

LAN_X1

8

LAN_X2

CL33 470P_0402_50V7K

LAN_LINK#

0.1U_0402_16V4Z

XTLO

9

XTLI

21

NC

AR8158-BL1A-RL_QFN32_4X4

+1.7_VDDCT

1

CL548

CL547

SWR@

@

1 2

RL11 511_0402_1%

CL38 1000P_1206_2KV7KCL38 1000P_1206_2KV7K

LL3 MCK3225201YZF_2PLL3 MCK3225201YZF_2P

1 2

2

1 2

2

10U_0805_10V6K

2

1

RJ45_GND

TRXP0

TRXN0 TRXP1

TRXN1

VDD33

VDDCT

VDDCT_REG

DVDDL_REG

AVDDH_REG

AVDDL

AVDDL_REG

LDO@

RL520 0_0402_5%

1 2

SWR@

0.1U_0402_16V4Z

SWR@

0.1U_0402_16V4Z

1

2

PJDLC05C_SOT23-3

31

LED[0]

32

LED[1]

16

LED[2]

12

13 14

15

11

RBIAS

2

1

LX

6

5

30

10

24

27 7

CL549

+3V_LAN

CL32

CL32 470P_0402_50V7K

470P_0402_50V7K

@

For EMI.

1

ACTIVITY

LAN_LINK#

LAN_RBIAS

+3V_LAN

+1.7_LX

+1.7_VDDCT +1.7_VDDCT_REG

+1.1_DVDDL

+2.7_AVDDH

+1.1_AVDDL

+1.7_VDDCT_REG

1

2

RL17 511_0402_1%RL17 511_0402_1%

DL1

2

3

MDI0+

RL527 49.9_0402_1%

MDI0-

MDI1+

MDI1-

+1.1_AVDDL

1

CL564 1U_0402_6.3V6K

1U_0402_6.3V6K

2

5.1K_0402_5%

LANGND

1

RL526 49.9_0402_1%

1

RL529 49.9_0402_1%RL529 49 .9_0402_1%

1 2

RL528 49.9_0402_1%RL528 49 .9_0402_1%

1 2

RL522 2 .37K_0402_1%RL522 2 .37K_0402_1%

1 2

CL552 0.1U_0402_16V4Z

1

CL562 1U_0402_6.3V6KCL562 1U_ 0402_6.3V6K

1 2

CL563 0.1U_0402_16V4ZCL563 0.1U_0402_16V4Z

1 2

CL571 1U_0402_6.3V6K

1

CL572 0.1U_0402_16V4Z

1

CL597

CL568

2

1U_0402_6.3V6K

LDO@

LDO@CL564

RL19

ACTIVITY

12

2

1

CL567

2

0.1U_0402_16V4Z

1

@

CL35

@CL35

470P_0402_50V7K

2

CL550 1000P_0402_50V 7K@C L550 1000P_0402_50V7K@

CL592 0.1U_0402_16V4Z

CL551 1000P_0402_50V 7K@C L551 1000P_0402_50V7K@

CL593 0.1U_0402_16V4ZCL593 0.1U_0402_16V4Z

1

CL569

2

0.1U_0402_16V4Z

Remove DL2~DL13 2010/12/06 Tock

2

1

1 2

Close Pin 11

+3VALW

CL427 1U_0402_6.3V6KCL427 1U_ 0402_6.3V6K

CL436 0.1U_0402_16V4ZCL436 0.1U_0402_16V4Z

CL554 1000P_0402_50V 7K@CL554 1000P_04 02_50V7K@

CL437 0.1U_0402_16V4Z

CL555 1000P_0402_50V 7K@CL555 1000P_0 402_50V7K@

2

Power On strapping

Pin Description Chip Defau lt

H:Over Clo ck Enable

LED0

L:Over Clo ck Disable

W=40mils

RL13 0_0603_5%

2

1

QL1

@

AP2301GN-HF_SOT23-3

3 1

2

CL5

@

+3V_LAN

1

2

*

1A

1

CL8

2

1000P_0402_50V7K

0.1U_0402_16V4Z

close to LAN Pin 1

RL18 10K_0402_5%@R L18 10K_0402_5%@

1 2

2

CL41

@

0.1U_0402_16V4Z

1

12

2

1

+1.7_VDDCT_R

CL15

1000P_1206_2KV7K

RJ45_GND

1

2

EN_WOL# <26>

LL2

2

1

BLM18AG601SN1D_2P

MDI1+

MDI1-

MDI0-

change T1 to SP050005900 <MHPC> but use BOTH_GST5009-LF_24P footprint 2010/12/14 Tock

change TL1 PN to SP050006E00 2011/02/11 Tock

TL1

1

RD+

2

RD-

3

CT

4

NC

5

NC

6

CT

7

TD+

8

TD-

350uH_NS0013LF

12

1

H

1

2

10U_0603_6.3V6M

RJ45_MIDI1+ RJ45_MIDI1-

RJ45_CT0

RJ45_CT1

RJ45_MIDI0+MDI0+

RJ45_MIDI0-

CL34

1

@

2

10U_0603_6.3V6M

1

CL1

CL7

2

1U_0402_6.3V6K

+1.7_VDDCT

16

RX+

15

RX-

14

CT

13

NC

12

NC

11

CT

10

TX+

9

TX-

RJ45_CT0

RL775_0402_ 5% RL775_04 02_5%

RJ45_CT1

RL875_0402_5 % RL875_04 02_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

2010/11/09 2012/11/09

3

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

LAN AR8158

P1VE6 Schematics

1

18 37Thursday, March 17, 2011

of

1.0

5

Dr-Bios.com

4

3

2

1

+CARDPWR

30mil

1

CC9

RC6

100K_0402_5%

D D

C C

100K_0402_5%

CC9

0.1U_0402_16V4Z

2

@

1 2

close pin 22

+CARDPWR +CARDPWR

XDD0_SDCLK_MSD2

XDD1_MSD0

XDD2_SDCMD XDD3

XDD4_SDD3_MSD1

XDD5_SDD2

XDD6_MSBS XD_D7

XDWE#_SDCD#

XDWP#

XDALE_MSD3

XD_CD#

XDDRY_SDWP_MSCLK XDRE#_MSINS#

XDCE#_SDD1 XDCLE_SDD0

Card Reader Connector

JREAD1

22

XD-VCC

30

XD10-D0

29

XD11-D1

28

XD12-D2

27

XD13-D3

26

XD14-D4

25

XD15-D5

24

XD16-D6

23

XD17-D7

33

XD07-WE

32

XD08-WP

34

XD06-ALE

39

XD01-CD

38

XD02-R/B

37

XD03-RE

36

XD04-CE

35

XD05-CLE

31

XD GND

40

XD GND

41

SD CD/WP GND

42

SD CD/WP GND

T-SOL_144-1300002600_NR

CONN@

CONN@JREAD1

SD4-VDD

MS9-VCC

SD5-CLK

SD7-DAT0

SD8-DAT1

SD9-DAT2

SD1-DAT3

SD2-CMD

SD-CD

SD-WP

SD6-VSS SD3-VSS

MS8-SCLK

MS4-DATA0

MS3-DATA1

MS5-DATA2

MS7-DATA3

MS6-INS

MS2-BS

MS1-VSS

MS10-VSS

11

18

9

4

3

21

19

16

1 2

6 13

17

10

8

12

15

14

7

5 20

+CARDPWR

0.1U_0402_16V4Z

close pin 11

XDD0_SDCLK_MSD2

XDCLE_SDD0 XDCE#_SDD1

XDD5_SDD2

XDD4_SDD3_MSD1

XDD2_SDCMD

XDWE#_SDCD#

XDDRY_SDWP_MSCLK

XDD1_MSD0

XDD4_SDD3_MSD1

XDD0_SDCLK_MSD2 XDALE_MSD3

XDRE#_MSINS#

XDD6_MSBS

1

2

30mil

CC8

1

CC7

0.1U_0402_16V4Z

2

close pin 18

RC7

1 2

0_0402_5%

RC8

1 2

0_0402_5%

@

@RC7

@

CC11 4.7P_0402_50V8C

@

@RC8

@

CC12 4.7P_0402_50V8C

Reserve RC7 , CC11 , RC8 , CC12 for EMI Tock 2010/12/28

Remove CC13 by vender review 12/08 Tock

2010.11.02 Del LED circuit

2010.08.19 Copy Symbol from NCQF0

change JREAD1 to SP07000NV00 2010/12/14 Tock

+3VS +3VS_CR

JR1

1

JUMP_43X39

@

@JR1

2

RTS5138

CC2 100P_0402_50V8JCC2 100P_0402_50V8J

12

1 2

RC1 6.2K_0603_1%RC1 6.2K_0603_1%

B B

2

1

CC1

4.7U_0603_6.3V6K

1

2

CC10

0.1U_0402_16V4Z

30mil

USB20_N6<13> USB20_P6<13>

1

10mil

CC3

1U_0402_6.3V6K

2

Close to chip

XDDRY_SDWP_MSCLK_L

A A

XDD0_SDCLK_MSD2_L

Add RC3 , CC5 ,RC4 , CC6 by vender review for EMI sol. 12/08 Tock

change CC5 , CC6 BOM structure to @ 2011/01/03 Tock

1 2

RC3 0_0402_5%R C3 0_0402_5%

1 2

RC4 0_0402_5%R C4 0_0402_5%

5

10mil

RREF

USB20_N6 USB20_P6

+3VS_CR

+CARDPWR VREG

XD_CD#

XDDRY_SDWP_MSCLK_L XDRE#_MSINS#

XDCE#_SDD1 XDCLE_SDD0

XDALE_MSD3

XDDRY_SDWP_MSCLK

1

@

CC5

@CC5

4.7P_0402_50V8C

2

XDD0_SDCLK_MSD2

1

@

CC6

@CC6

4.7P_0402_50V8C

2

10

11 12

UR1

1

2

3

4

5 6

7

8

9

REFE

DM

DP

3V3_IN

CARD_3V3 V18

XD_CD#

SP1

SP2 SP3

SP4 SP5

17

GPIO0

24

CLK_IN

23

XD_D7

22

SP14

21

SP13

20

SP12

19

SP11

18

SP10

16

SP9

15

SP8

14

SP7

13

SP6

EPAD

RTS5138-GR_QFN24_4X4

25

Change net name from XDD5_SDD2_MS_D5 to XDD5_SDD2 11/26 Tock

4

CARD_LED#

XD_D7

XDD6_MSBS XDD5_SDD2

XDD4_SDD3_MSD1 XDD3

XDD2_SDCMD XDD1_MSD0

XDD0_SDCLK_MSD2_L XDWP#

XDWE#_SDCD#

change JREAD1 to SP07000LW00 for Layout 2010/01/05 Tock

+3VS

12

RC5

RC5 10K_0402_5%

10K_0402_5%

CARD_LED# <22>

12

RC2

RC2 22_0402_5%

22_0402_5%

1

CC4

CC4 10P_0402_50V8J

10P_0402_50V8J

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Share Pin

CLK_48M_CR <12>

3

XD SD30mil MS

XD_CD#

SP1

SP2

SP3

SP4

SP5

SP6

SP7

SP8

SP9

SP10

SP11

SP12

SP13

SP14

XD_RDY

XD_RE#

XD_CE#

XD_CLE

XD_ALE

XD_WE#

XD_WP

XD_D0

XD_D1

XD_D2

XD_D3

XD_D4

XD_D5

XD_D6

SD_WP

SD_D1

SD_D0

SD_CD#

SD_CLK

SD_CMD

SD_D3

SD_D2

MS_CLK

MS_INS#

MS_D3

MS_D2

MS_D0

MS_D1

MS_BS

XD_D7

Compal Secret Data

2010/11/09 2012/11/09

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

CARD READER RTS5138

P1VE6 Schematics

19 37Thursday, March 17, 2011

1

1.0

A

Dr-Bios.com

Mini-Express Card for WWAN

3G@

+1.5VS

1 1

1 2

R335 0_0805_5%

Reserve C293 for RF Tock 2010/12/28

8/22 Reserve R335 (0 ohm 0805) Add net +1.5VS_WWAN

8/25 Change C269,C275 to SE000004880 Standard Part

Change JMINI1 to FOX_AS0B246-S50U-7F_52P-T 06/29

10/27 Add R412 (0 ohm) on FCH_PCOE_WAKE#

9/2 Change ICH_PCIE_WAKE# to FCH_PCIE_WAKE#

FCH_PCIE_WAKE#<13,18,21>

WWAN_CLK REQ#<13>

2 2

FCH_PCIE_WAKE#

WWAN_CLK REQ#

CLK_PCIE_WW AN#<12>

CLK_PCIE_WW AN<12>

PCIE_FRX_DTX_N1<12>

PCIE_FRX_DTX_P1<12>

PCIE_FTX_C_DRX_N1<12>

PCIE_FTX_C_DRX_P1<12>

+3VS_WWAN

+1.5VS_WWAN

C293

22P_0402_50V8J

@

1 2

R412 0_0402_5%

C275 10U _0805_10V6K 3G@C275 10U _0805_10V6K 3G@

1 2

WWAN_W AKEUP_R#

B

3G@

0.1U_0402_16V4Z

+3VS

1 3

5 7

9

11

13 15

17 19

21 23

25 27

29 31

33 35

37 39

41 43

45 47

49 51

53

W=40mil

1

C263

2

W=40mil

3G@

1

2

JMINI1

PLAST_SSM010-52-B-K

C268

0.1U_0402_16V4Z

1 2

R227 0_1206_5%

CONN@

CONN@JMINI1

1 3

5 7

10

9

12

11

14

13

16

15

18

17

20

19

22

21

24

23

26

25

28

27

30

29

32

31

34

33

36

35

38

37

40

39

42

41

44

43

46

45

48

47

50

49

52

51

GND2

GND1

+3VS_WWAN

10U_0805_10V6K

3G@

2

4 6

8

3G@

2

4 6

8 10

12 14

16 18

20 22

24 26

28 30

32 34

36 38

40 42

44 46

48 50

52

54

+1.5VS_WWAN

1

C264

2

3G@

1

C269

2

+3VS_WWAN

3G@

0.01U_0402_25V7K

8/31 Change MCP@ to 3G_MP@

3G@

0.1U_0402_16V4Z

1

C270

2

@

1

R228 0_1206_5%

+UIM_PWR

UIM_DATA

UIM_CLK

UIM_RST UIM_VPP

WXMIT_OFF#

R229 0_0402_5%3G@R229 0_0402_5%3G@

1 2

R230 0_0402_5%3G@R230 0_0402_5%3G@

R231 0_0402_5%3G@

WLAN_LED#_R

1

R232 0_0402_5%

9/9 Remove D9

change JMIN1 to SP07000QC00

3G@

C282 1U_0402_6.3V6K

3 3

12

3G@

C283 0.1U_0402_16V4Z

12

3G@

C284 56P_0402_50V8

12

3G@

C285

56P_0402_50V8

2

1

3G@

C278 100P_0402_50V8J

2

1

@

22P_0402_50V8J

C279

22P_0402_50V8J

12

+UIM_PWR

UIM_RST

3G@

+UIM_PWR

UIM_RST

UIM_CLK

1

@

2

C276

56P_0402_50V8

W=20mil

UIM_DATA

1

2

C277

22P_0402_50V8J

+UIM_PWR

Modifiy 05/11

2010/12/14 Tock

USB20_P4<13>

UIM_VPP

USB20_N4<13>

12

@

10K_0402_5%

JSIM1

1

VCC

2

RST

3

CLK

4

Reserved

5

GND

6

VPP

7

I/O

8

Reserved

9

CD

10

GND

11

GND

ACON_SCR4W-8K1000

R233

ACON_SCR4W-8K1000

CONN@

change JSIM1 to SP07000NW00 2010/12/28 Tock

2

3G@

C479

3G@ C4 79

100P_0402_50V8J

1

C

3G@

1

C265

2

47P_0402_50V8J

3G@

1

C271

0.01U_0402_25V7K

2

+3VALW

1

C266

2

3G@

150U_B_6.3VM_R40M

+1.5VS_WWAN

4.7U_0603_6.3V6K

1

C272

C272 47P_0402_50V8J

47P_0402_50V8J

2

C274

@

C274

@

10/04 Add 100p(C402) on BT_ON#

BT_ON#<21,26>

+3VS_WWAN

1

+

2

Close to WWAN CONN

BT@

10/04 Add 100p(C398) on UIM_RST

10/06 Remove C398

WXMIT_OFF# <26>

PLT_RST# <12,18,21,26>

1 2

1

USB20_MINI_N USB20_MINI_P

3G@

2

FCH_SMCLK0 <7,8,13,21>

FCH_SMDAT0 < 7,8,13,21>

WWAN_LED # <21,22>

WLAN_LED# <21,22>

(9~16mA)

10/31 Add R417~R420 for co-lay USB port3 & port9

11/01 Change R417 R418 from mount to @ Change R419 R420 from mount to @ SW request (P0VE6-0045)

PLT_RST#

9/1 Change R234 from mount to @

10K_0402_5% @

WWAN_W AKEUP#<26>

D

+3VS

1

BT@

C267

BT@C 267

0.1U_0402_16V4Z

2

BT@

R226

10K_0402_5%

2

C402

100P_0402_50V8J

1

12

R374

0_0603_5%

+3VALW +3VS

@

1 2

+3V_BT

8/26 Change Q13 to SB934130020 Standard Part

USB20_P7<13>

USB20_N7<13>

USB20_P7 USB20_N7

9/1 Change R230 R231 from NON3G@ to mount

8/22 Update JBT1 Symbol from database (ACES_88266-04001_4P)

R234

USB20_MINI_N

USB20_MINI_P

USB20_MINI_N

+3VALW

12

1 2

R235 0_0402_5%

@

R246 0_0402_5%@

R248 0_0402_5%@R248 0_0402_5%@

R250 0_0402_5%3G@

R252 0_0402_5%3G@

Change R417, R418 to RP9 Michael 2010/12/23

Swap USB net of RP10 for layout Tock 2010/12/24

Change RP9 to R246 , R248 Tock 2010/12/30

WWAN_W AKEUP_R#

1

1 2

1

2

9/3 Reserver +3VALW for BT (R378 R374)

2011/02/11 Change Q13 PN to SB000006R10

BT@

R378

R378 0_0603_5%

0_0603_5%

BT MODULE CONN

Q13

BT@

Q13

BT@

AO3413L_SOT23-3

3

1

DGS

2

Change R419, R420 to RP10 Michael 2010/12/23

Change RP10 to R250 , R252 Tock 2010/12/30

E

+3VS_BT

C273

2

0.1U_0402_16V4Z

+3VS_BT

1 2

3 4

USB20_N3 <13>

USB20_P3 <13>

USB20_P9 <13>

USB20_N9 <13>

BT@

1

JBT1

1 2

5

G1

3

6

G2

4

ACES_88266-04001

CONN@

@

C280 22P_0402_50V8J

2

4 4

1

3G@

C281 22P_0402_50V8J

12

UIM_CLK

Reserve for SIM card does not meet rise time and pull-up is needed.

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

8/22 Update JP1 Symbol from database (TAITW_PMPAT7-08GLBS1N14H0_9P)

10/06 Change C278 to 100p

Compal Secret Data

Issued Date

2010/11/09 2012/11/09

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Mini-Card/BT CONN

P1VE6 Schematics

20 37Thursday, March 17, 2011

E

1.0

5

Dr-Bios.com

4

3

2

1

D D

EC_TX_P80_DATA<26> EC_RX_P80_CLK<26>

EC_TX_P80_DATA EC_RX_P80_CLK

R253 0_0402_5%R253 0_0402_5%

1 2

R254 0_0402_5%R254 0_0402_5%

1 2

EC_TX_P80_DATA_R

EC_TX_P80_CLK_R

Mini-Express Card for WLAN

Change R236, R237 to RP11 Michael 2010/12/23

Change RP11 to R253 , R254 Michael 2010/12/30

+3VS_WLAN

1

2

C C

9/2 Change ICH_PCIE_WAKE# to FCH_PCIE_WAKE#

FCH_PCIE_WAKE#<13,18,20>

WLAN_CLKREQ#<13>

B B

CLK_PCIE_WLAN#<12> CLK_PCIE_WLAN<12>

PCIE_FRX_DTX_N3<12> PCIE_FRX_DTX_P3<12>

PCIE_FTX_C_DRX_N3<12> PCIE_FTX_C_DRX_P3<12>

W=40mil W=40mil

C286

4.7U_0603_6.3V6K

BT_ON#<20,26>

+3VS_WLAN

10U_0603_6.3V6M

C292

1

C287

0.1U_0402_16V4Z

2

1

2

R238

R238 0_0402_5%@

0_0402_5%@

1

C288

C288 47P_0402_50V8J

47P_0402_50V8J

2

12

EC_TX_P80_DATA_R EC_TX_P80_CLK_R

12

R243

R243 100K_0402_5%

100K_0402_5%

change JMIN2 to SP07000QC00 2010/12/14 Tock

JMINI2

1 3

5 7

9

11

13 15

17 19

21 23

25 27

29 31

33 35

37 39

41 43

45 47

49 51

53

PLAST_SSM010-52-B-K

1 3

5 7

9 11

13 15

17 19

21 23

25 27

29 31

33 35

37 39

41 43

45 47

49 51

GND1

CONN@

CONN@JMINI2

GND2

+1.5VS_WLAN

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

1

2

C289

4.7U_0603_6.3V6K

+3VS_WLAN

1

2

1

R255 0_0402_5%R255 0_0402_5%

R256 0_0402_5%R256 0_0402_5%

WWAN_LED #_R

C290

0.1U_0402_16V4Z

J2

J2 JUMP_43X79

JUMP_43X79

@

2

1

1 2

R242

0_0402_5%

1 2

1

C291

C291 47P_0402_50V8J

47P_0402_50V8J

2

+3VS

+1.5VS_WLAN

WL_OFF# <26> PLT_RST# <12,18,20,26>

R241

0_0402_5%

@

1 2

R336 0_0805_5%R336 0_0805_5%

8/22 Reserve R336 (0 ohm 0805) Add net +1.5VS_WLAN

PLT_RST#

1

C446

C446 100P_0402_50V8J

100P_0402_50V8J

2

Add C446 on PLT_RST# for switching noise Tock 2010/12/28

Change RP12 to R255 ,R256 Tock 2010/12/30

FCH_SMCLK0 <7,8,13,20>

FCH_SMDAT0 < 7,8,13,20>

USB20_N8 <13>

USB20_P8 <13>

WWAN_LED # <20,22>

9/20 Add R393 R394 for SMBus

9/17 Remove R239,R240

(9~16mA)

WLAN_LED# <20,22>

+1.5VS_WLAN+1.5VS

5/12 Update WLAN connector(the same as KAV60) 6/1 Revised 37

、、、、39、、、、41、、、、42、、、、

43 to NC 6/12 Update connector to DC040006S00 6/26 Update JMINI1 footprint 7/01 update pin 23,25,31,33

A A

Compal Electronics, Inc.

WLAN

P1VE6 Schematics 1.0

WLAN

LA-6222P

21 37Thursday, March 17, 2011

1

5

4

Title

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

3

2

Date: Sheet of

of

A

Dr-Bios.com

B

C

D

E

F

G

H

10K_0402_5%

4

Y

R373

2

G

+3VS

12

13

D

S

Q35

SSM3K7002FU_SC70-3

2

G

MEDIA_LED#

13

D

Q34

S

SSM3K7002FU_SC70-3

LED PCB CONN

JLED1

W=40mil

PWR_LED#<26>

1 1

PWR_SUSP_LED#<26>

BATT_BLUE_LED#<26> BATT_AMB_LED#<26>

WWAN_LED #<20,21> WLAN_LED#<20,21>

W=40mil

+3VALW

+3VS

MEDIA_LED#

JLED1

1

2

3

4

5

6

7

8

9

10

11

GND

11

12

GND

12

ACES_85201-1205N

CONN@

+3VS

5

U8

2

CARD_LED#<19>

13 14

HDD_LED#<14>

HDD_LED#

NC7SZ08P5X_NL_SC70-5

P

B

1

A

G

3

8/22 Update JP2 Symbol from database (ACES_85201-1605N_16P)

8/24 Update JLED1 Symbol from database (ACES_85201-1205N_12P) & Update pin definition

9/1 Add LED Circuit (LED2~4(SC597UDB000)LED5(SC51 91NB000), R360~R369, Q33)

9/1 Add R373, Q34, Q35 for MEDIA_LED#

9/1 Change All LED power to 5V

9/9 Change LED2~4 footprint to LED_HT-297DQ-GQ_4P

9/11 Remove LED portion

2 2

+5VS_HDD

0.1U_0402_16V4Z

1

3 3

2

1000P_0402_50V7K

1

C12

C11

2

1U_0402_6.3V6K

1

C13

2

10U_0805_10V6K

1

C14

2

Add C11~C14 from HDD board 2011/01/07 Tock

SATA HDD Conn.

8/22 Change C298 from 10U 6.3V to 10U 10V

8/22 Reserve R337 R338 Add net +3VS_HDD,+5VS_HDD

9/1 Change Q33 to SB000009610(SSM3K7002FU_SC70-3)

JHDD1

1

SATA_ITX_DRX_P0<14> SATA_ITX_DRX_N0<14>

SATA_DTX_C_IRX_N0<14> SATA_DTX_C_IRX_P0<14>

+3VS

+5VS

1 2

R337 0_0805_5%R337 0_0805_5%

1 2

R338 0_0805_5%R338 0_0805_5%

W=40mil

+3VS_HDD

+5VS_HDD

W=100mil

4 4

SATA_ITX_DRX_P0

SATA_ITX_DRX_N0

SATA_DTX_C_IRX_N0

SATA_DTX_C_IRX_P0

+3VS_HDD

+5VS_HDD

1

2

3

4

5

6

7

8

9

10

11

GND

11

12

GND

12

ACES_85201-1205N

CONN@

13 14

change JHDD1 to SP01000E400 , delete C293 ~ C298 2010/12/14 Tock

Modify JHDD1 pin define 2010/12/15 Tock

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

A

B

C

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

Compal Secret Data

2010/11/09 2012/11/09

E

Compal Secret Data

Deciphered Date

F

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

SATA CONN./LED/B CONN./BATT CONN.

P1VE6 Schematics

G

P1VE6 Schematics

22 37Thursday, March 17, 2011

of

H

1.0

updated SW1 symbol for SN100002K00

Dr-Bios.com

2010/12/06 Tock

9/6 Change D13 from mount to @

10/05 Remove D13

ON/OFF Button

6

5

G

SW1

EVQPLMA15_4P

4

3

2

1

FOR EMI

PWR_LED1#

ON/OFFBTN#

C299 100P_0402_50V8J@C299 100P_0402_50V8J@

1 2

C301 100P_0402_50V8J@C301 100P_0402_50V8J@

1 2

9/20 Remove R245,R248,D12

EC_ON

1

C473

C473 100P_0402_50V8J

100P_0402_50V8J

2

Reserve C473 for EC_ON Tock 2011/01/07

8/26 Change D11 to SC600000B00 Standard Part

+3VALW

R247

100K_0402_5%

1 2

ON/OFF#

3

51_ON#

2

C300

1000P_0402_50V7K

1

13

D

Q14

2

G

SSM3K7002FU_SC70-3

S

8/26 Change Q14 to SB000009610 Standard Part

ON/OFFBTN#

EC_ON<26>

EC_ON

R249

10K_0402_5%

D11

1

BAV70W_SOT323-3

1 2

ON/OFF# <26>

51_ON# <30>

place close to PR4

51_ON#

1

C478

C478 100P_0402_50V8J

100P_0402_50V8J

2

Reserve C478 for 51_ON# Tock 2011/01/07

9/1 Remove LED2 LED3 circuit, Change 70@ to mount

9/20 Add LED2 LED3 Circuit

9/21 Remove LED2 LED3 Circuit

change R251 from 51 ohm to 220 ohm 2011/03/07 Tock

change R251 from 220 ohm to 100 ohm 2011/03/16 Tock

21

LED2

@

HT-191NB5-DT BLUE 0603

+3VS

(BLUE)

12

R251

R251 100_0402_1%~N

100_0402_1%~N

21

LED1

HT-191NB5-DT BLUE 0603

PWR_LED1#

PWR_LED1# <26>

10mil

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

9/24 Change U9 to SA00001TC00

LID Switch

W=20mil

+3VALW

1

C302

0.1U_0402_16V4Z

Compal Secret Data

2010/11/09 2012/11/09

Compal Secret Data

2

Deciphered Date

1

GND

VDD

OUTPUT

2

3

U9

AH180WG-7_SC59-3

1

C303

2

10P_0402_50V8J

LID_SW# <26>

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

ON/OFF / PWR SW/ LID SW

P1VE6 Schematics

23 37Thursday, March 17, 2011

of

1.0

5

Dr-Bios.com

Change CP1 to C398 , C419 , C448 , C449 Change CP2 to C453 , C450 , C452 , C451 Change CP3 to C457 , C454 , C456 , C455 Tock 2010/12/30

C398 1 00P_0402_50V 8JC39 8 100P_0402 _50V8J

KSO15

KSO14 KSO13

KSO12

D D

KSI7

KSO11 KSO10

KSI6

KSI5

KSO9 KSI4

KSO8

KSI[0..7]

KSO[0..15]

1 2

C419 1 00P_0402_50V 8JC41 9 100P_0402 _50V8J

1 2

C448 1 00P_0402_50V 8JC44 8 100P_0402 _50V8J

1 2

C449 1 00P_0402_50V 8JC44 9 100P_0402 _50V8J

1 2

C453 1 00P_0402_50V 8JC45 3 100P_0402 _50V8J

1 2

C450 1 00P_0402_50V 8JC45 0 100P_0402 _50V8J

1 2

C452 1 00P_0402_50V 8JC45 2 100P_0402 _50V8J

1 2

C451 1 00P_0402_50V 8JC45 1 100P_0402 _50V8J

1 2

C457 1 00P_0402_50V 8J

1 2

C454 1 00P_0402_50V 8JC45 4 100P_0402 _50V8J

1 2

C456 1 00P_0402_50V 8JC45 6 100P_0402 _50V8J

1 2

C455 1 00P_0402_50V 8JC45 5 100P_0402 _50V8J

1 2

KSI[0..7] <26>

KSO[0..15] <26>

8/22 Update JKB1 Symbol from database (ACES_85202-24051_24P) 8/23 Update KB pin definition

Change CP4 to C461 , C458 , C460 , C459 Change CP5 to C465 , C462 , C464 , C463 Change CP6 to C469 , C466 , C468 , C467 Tock 2010/12/30

C461 1 00P_0402_50V 8JC46 1 100P_0402 _50V8J

KSO7

KSO6 KSO5

KSO4

KSO3

KSI3 KSO2

KSO1

KSO0

KSI2 KSI1

KSI0

1 2

C458 1 00P_0402_50V 8JC45 8 100P_0402 _50V8J

1 2

C460 1 00P_0402_50V 8JC46 0 100P_0402 _50V8J

1 2

C459 1 00P_0402_50V 8JC45 9 100P_0402 _50V8J

1 2

C465 1 00P_0402_50V 8JC46 5 100P_0402 _50V8J

1 2

C462 1 00P_0402_50V 8JC46 2 100P_0402 _50V8J

1 2

C464 1 00P_0402_50V 8JC46 4 100P_0402 _50V8J

1 2

C463 1 00P_0402_50V 8JC46 3 100P_0402 _50V8J

1 2

C469 1 00P_0402_50V 8JC46 9 100P_0402 _50V8J

1 2

C466 1 00P_0402_50V 8JC46 6 100P_0402 _50V8J

1 2

C468 1 00P_0402_50V 8JC46 8 100P_0402 _50V8J

1 2

C467 1 00P_0402_50V 8JC46 7 100P_0402 _50V8J

1 2

4

Swap KB signal for layout Tock 2010/12/24

KSI0

KSI1 KSI2

KSO0

KSO1

KSO2

KSI3

KSO3

KSO4

KSO5 KSO6

KSO7

KSO8

KSI4

KSO9

KSI5

KSI6

KSO10 KSO11

KSI7

KSO12

KSO13 KSO14

KSO15

26 25

24 23

22 21

20 19

18 17

16 15

14 13

12 11

10

9

8 7

6 5

4 3

2 1

3

JKB1

G2 G1

24 23

22 21

20 19

18 17

16 15

14 13

12 11

10 9

8 7

6 5

4 3

2 1

ACES_85 202-24051

CONN@

To TP/B Conn.

TP_DATA<26>

TP_CLK<26>

+5VS

0_0402_ 5%

8/22 Update JP3 Symbol from database (ACES_85201-0605N_6P)

8/22 Reserve R339 (0 ohm 0402) Add Net name +5VS_TP

8/24 Update JTP1 Symbol from database (ACES_85201-0405N_4P) & Update pin definition

TP_DATA

TP_CLK

R339

D14

PJDLC05 C_SOT23-3

2

W=20mil

+5VS_TP

12

3

2

@

1

JTP1

1

2

3

4

5

G1

6

G2

ACES_85 201-0405N

CONN@

1

INT_KBD Conn.

Combo Jack

C C

RA14 0_0402_ 5%

+LDO_OU T_3.3V

Add RA58 for ne t GPIO_1 by vender revie w for pop issue Tock 2010/12/08

change GPIO_1 t o GPIO_0 Tock 2011/01/03

GPIO_0<17 >

HP_SENS E

B B

change RA52,DA1 0,CA26 BOM stru cture to @ by vender revie w for pop issue Tock 2010/12/08

HP_SENS E

A A

20K_040 2_5%

1 2

CMBS@

10U_080 5_10V6K

21

DA10 RB491D_S C59-3

CMBS@

1 2

RA52

RA52 100K_04 02_5%

100K_04 02_5%

CMBS@

RA58

270K_04 02_5%

CMBS@

12

RA41

1

2

change CA49 BOM structure to @ change RA41 fro m 47K to 4.7K by vender revie w for pop issue Tock 2010/12/08

CA25

@

12

RA36

1 2

0_0402_ 5%

@

CA49

@CA49

0.1U_040 2_16V4Z

1

CMBS@

CMBS@ RA30

2

100K_04 02_5%

CMBS@

CMBS@ RA5 0

10K_040 2_5%

1

CA26

CA26 1U_0603 _10V6K

1U_0603 _10V6K

2

CMBS@

5

RA30

RA50

HP_PLUG #

34

QA1B

QA1B 2N7002K DWH_SOT36 3-6

2N7002K DWH_SOT36 3-6

COM_MIC_R

12

QA3

13

D

CMBS@

BSS138_ NL_SOT23-3

2

G

S

11/17 Add Combo solution circuit for P0VE6 "POPO" noise

5

QA36

CMBS@

MMBT390 6H_SOT23-3

13

12

RA59

2

220_040 2_5%

CMBS@

1

CA28

10U_080 5_10V6K

change RA9 from 20K to 0 ohm Tock 2011/03/03

HP_PLUG # <17>

Add QA4,RA55,CA 29,RA36 for Int ernal Mic can't record is sue . Tock 201 1/02/21

2

CMBS@

change RA12 BOM structure to @ by vender revie w for pop issue Tock 2010/12/08

RA9

12

0_0402_ 5%

RA13

1 2

2K_0402 _5%

CMBS@

BSS138_ NL_SOT23-3

RA35

2.2K_040 2_5%

NCMBS@

1 2

COM_MIC

12

RA57

RA57 15K_040 2_1%

15K_040 2_1%

CMBS@

QA4

change RA59 fro m 750 to 220 oh m by vender revie w for bo bo noi se Tock 2011/03/16

COM_MIC < 17>

change RA57 fro m 47K to 15K oh m by vender revie w for bo bo noi se Tock 2011/03/16

RA14

1K_0402 _5%

NCMBS@

COM_MIC_P LUG#

61

QA1A

QA1A 2N7002K DWH_SOT36 3-6

2N7002K DWH_SOT36 3-6

2

RA55

13

D

2

G

S

1 2

1

CA29

CA29 1U_0603 _10V6K

1U_0603 _10V6K

2

RA55 10K_040 2_5%

10K_040 2_5%

11/17 Move HP JACK and MIC JACK Circuit to IO Board.

COM_MIC_P LUG# <17>

COM_MIC

remove CA4 chan ge QA1 , QA2 fr om SB501380020 <BSS138> to SB 00000EO10 <2N7 002>. Tock 201 1/02/24

Security Class ification

2010/11/ 09 2012/11/ 09

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/11/ 09 2012/11/ 09

3

Compal Secret Data

Deciphered Date

Add net INT_MIC 0 on JIO1 pin 2 Tock 2010/11/26

INT_MIC0<1 7>

+MIC1_VRE FO

MIC_PLUG#<17> COM_MIC<1 7>

HP_LEFT<17>

HP_RIGHT<17 >

USB_ON#<25,26>

USB_OC0 #<13>

USB20_P 0<1 3>

USB20_N 0<13> USB20_P 1<1 3>

USB20_N 1<13>

2

MIC1_L<17> MIC1_R<17>

INT_MIC0

MIC1_L

MIC1_R

MIC_PLUG#

COM_MIC

HP_LEFT HP_RIGHT

HP_SENS E

USB_ON#

USB_OC0 #

USB20_P 0

USB20_N 0 USB20_P 1

USB20_N 1

Size Document N umber Rev

B

Date: Sheet of

Date: Sheet

Title

+5VS

+5VALW

Compal Electronics, Inc.

KB Conn/TP/IO Conn

P1VE6 Schematics

JIO1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

G1

26

G2

ACES_85 202-24051

Add IO connecto r Michael 2010/11 /18

CONN@

24 37Thursday, March 17 , 2011

1

of

1.0

A

Dr-Bios.com

1 1

B

C

D

E

11/17 Move Left Side USB CONN. Circuit to IO board

2 2

+USB_VCCC1+5VALW

3 3

0.1U_0402_16V4Z

4 4

W=80mils W=80mils

USB_ON#<24,26>

C338

1

2

A

U11

1

GND

2

VIN

3

VIN

4

EN

SA00003XM00

8

VOUT

7

VOUT

6

VOUT

5

FLG

EPAD

AP2301MPG-13_MSOP8

9

USB_OC1# <13>

1

C339

1000P_0402_50V7K@

2

8/25 Change C340 from poly-cap to E-cap (SF000001500)

delete D17 for DFB issue 2011/02/25 Tock

B

SGA00002N80

Change C340 to SF000001500 2010/12/14 Tock

+USB_VCCC1

W=80mils

C340

220U_6.3V_M

1

+

2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

USB20_N2_1 USB20_P2_1

Issued Date

1

2

C

C341

470P_0402_50V7K

JUSB1

1 2

3 4

5 6

7 8

SUYIN_020173GB004M25MZL

CONN@

change JUSB1 to SP060004B00 2010/12/14 Tock

2010/11/09 2012/11/09

Right Side USB CONN.

VCC D-

D+ GND

GND GND

Compal Secret Data

Deciphered Date

9/28 Swap L28

R257

R257 0_0402_5%

0_0402_5%

@

1 2

L28

2

USB20_N2<13>

USB20_P2<13>

D

2

3

WCM-2012-900T_4P

@

1 2

R258 0_0402_5%

Title

Size Document Number Rev

B

Date: Sheet of

USB20_N2_1

1

USB20_P2_1

4

Compal Electronics, Inc.

USB PORTS

P1VE6 Schematics

25 37Thursday, March 17, 2011

E

1.0

5

Dr-Bios.com

SUSP#

1

C475

100P_0402_50V8J

D D

C C

+3VALW

2

Reserve C475,C476 for SUSP# Tock 2011/01/07

@

C349

@C349

22P_0402_50V8J

R267 47K_040 2_5%R267 47K_0402_5%

+3VALW

C350 0.1U_0402_16V4ZC350 0.1U_0402_16V4Z

+3VALW

10/1 ENE Recomm and

R269 47K_0402_5%R269 47K_0402_5%

1 2

R270 47K_0402_5%R270 47K_0402_5%

1 2

R271 1K_0402_5%@R271 1K_0402_5%@

1 2

R266 2.2K_0402_5%R266 2.2K_0402_5%

1 2

R272 2.2K_0402_5%R272 2.2K_0402_5%

1 2

C353

C353 10P_0402_50V8J

10P_0402_50V8J

+3VS

Reserve for EMI please close to U12

R276 2.2K_0402_5%@R276 2.2K_0402_5%@

1 2

R277 2.2K_0402_5%@R277 2.2K_0402_5%@

1 2

R279 10K_0402_5%@R279 10K_0402_5%@

1 2

place close to PU4 and PU7

1

C476

C476 100P_0402_50V8J

100P_0402_50V8J

2

@

@R265

33_0402_5%

12

R275

22_0402_5%

1 2

12

R265

LPC_CLK0_EC

12

1

EC_RST#

KSO1

KSO2

EC_SMI#

EC_SMB_DA1

EC_SMB_CK1

2

11/02 Change C353 to 10p R275 to 22 ohm

8/23 Change R271 R279 from mount to @

EC_SMB_CK2

EC_SMB_DA2

EC_SCI#

9/5 Change R276 R277 from mount to @

+3VALW

PLT_RST#

C420

C420 100P_0402_50V8J

100P_0402_50V8J

KSI[0..7]<24>

KSO[0..15]<24>

8/31 EC_SCI# Pull up to +3VALW

8/23 Delete R280

Reserve C436, C437 for SMB Michael 2010/11/18

EC_SMB_CK2 EC_SMB_DA2

@

1

C436

C436 100P_0402_50V8J

100P_0402_50V8J

2

B B

15P_0402_50V8J

A A

Ra

Rb

@

1

C437

100P_0402_50V8J

2

C407 100P_0402_50V8J

10/05 Add 100p(C407) on APU_ALERT#_EC

EC_XCLK0

EC_XCLK1

1

C354

2

X1

32.768KHZ_12.5PF_Q13MC14610002

8/23 Change R282 from mount to @ X1 C354 C355 from @ to mount

8/26 Change R282 from @ to mount X1 C354 C355 from mount @

+3VALW

1 2

Board ID

Analog Board ID definition, Please see page 3.

R283

R283 100K_0402_5%

100K_0402_5%

AD_BID0

R284

8.2K_0402_5%

1

2

1

C355

1

2

C355

4

15P_0402_50V8J

2

OSC

NC

3

10/11 Change C354,C355, X1 from @ to mount

change R284 from 0 ohm to 8.2K , 2011/01/28 Tock

change R283 from 0 ohm to 100K , 2011/02/11 Tock

C357

0.1U_0402_16V4Z

@

1 2

8/25 Delete KSO16 KSO17

Battery

APU

8/24 Delete Net FAN_SPEED1

SUSCLK<12>

8/31 Add 100k(R358) pull-down on SUSCLK

10/11 Change R282 R358 from mount to @

SLP_S3#

@

4

8/21 Change R262 from 0 ohm 0805 to 0 ohm 0603

R262

R262 0_0603_5%

0_0603_5%

1 2

Reserve C420 for PLT_RST# Michael 2010/11/18

GATEA20<13>

KB_RST#<13>

SERIRQ<12>

LPC_FRAME#<12>

LPC_CLK0_EC<12>

PLT_RST#<12,18,20,21>

EC_SCI#<13>

EC_SMB_CK1<29>

EC_SMB_DA1<29>

EC_SMB_CK2<4>

EC_SMB_DA2<4>

APU_ALERT#_EC<4>

INVT_PWM<9>

FAN_SPEED1<27>

EC_TX_P80_DATA<21>

EC_RX_P80_CLK<21>

ON/OFF#<23>

PWR_SUSP_LED#<22>

R358

@

100K_0402_5%

W=40mils W=20mils

C344

0.1U_0402_16V4Z

C344

C343

0.1U_0402_16V4Z

C343

0.1U_0402_16V4Z

1

2

GATEA20

KB_RST#

SERIRQ

LPC_FRAME#

LPC_AD3

LPC_AD2

LPC_AD1

LPC_AD0

LPC_CLK0_EC

PLT_RST#

EC_RST#

EC_SCI#

EC_SMB_CK1

EC_SMB_DA1

EC_SMB_CK2

EC_SMB_DA2

SLP_S3#

SLP_S5#

EC_SMI#

APU_ALERT#_EC

INVT_PWM

FAN_SPEED1

BT_ON#

EC_TX_P80_DATA

EC_RX_P80_CLK

ON/OFF#

PWR_SUSP_LED#

R282

@

1 2

0.1U_0402_16V4Z

1

2

KSI0

KSI1

KSI2

KSI3

KSI4

KSI5

KSI6

KSI7

KSO0

KSO1

KSO2

KSO3

KSO4

KSO5 KSO6

KSO7

KSO8

KSO9

KSO10

KSO11

KSO12

KSO13

KSO14

KSO15

0_0402_5%

EC_XCLK1

EC_XCLK0

C342

0.1U_0402_16V4Z

C342

0.1U_0402_16V4Z

1

2

LPC_AD3<12>

LPC_AD2<12>

LPC_AD1<12> LPC_AD0<12>

KSI[0..7]

KSO[0..15]

SLP_S3#<13>

SLP_S5#<13>

EC_SMI#<13>

BT_ON#<20,21>

12

C346

1000P_0402_50V7K

C346

1000P_0402_50V7K

C345

0.1U_0402_16V4Z

C345

0.1U_0402_16V4Z

2

1

2

U12

1

GATEA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ#

4

LPC_FRAME#/LFRAME#

5

LPC_AD3/LAD3

7

LPC_AD2/LAD2

8

LPC_AD1/LAD1

10

LPC_AD0/LAD0

12

CLK_PCI_EC/PCICLK

13

PCIRST#/GPIO05

37

EC_RST#/ECRST#

20

EC_SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

EC_SMB_CK1/SCL0/GPIO44

78

EC_SMB_DA1/SDA0/GPIO45

79

EC_SMB_CK2/SCL1/GPIO46

80

EC_SMB_DA2/SDA1/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

GPIO0A

17

GPIO0B

18

GPIO0C

19

SUS_PWR_DN_AC K/GPIO0D

25

INVT_PWM/PWM 2/GPIO11

28

FAN_SPEED1/FANFB0/GPIO14

29

FANFB1/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

ON_OFF/GPIO18

34

SUSP_LED#/GPIO19

36

NUM_LED#/GPIO1A

122

XCLK1

123

XCLK0

KB930QF-A1_LQFP128_14X14

SA00003QQ10

SLP_S5# ON/OFF#

1

C424

C424 100P_0402_50V8J

100P_0402_50V8J

2

Reserve C424, C425, for SLP_S3#, SLP_S5# Michael 2010/11/18

@

1

C425

C425 100P_0402_50V8J

100P_0402_50V8J

2

Reserve C428 for ON/OFF# Michael 2010/11/18

1

C428

C428 100P_0402_50V8J

100P_0402_50V8J

2

1

+3VALW_EC

C347

1000P_0402_50V7K

C347

1000P_0402_50V7K

LPC & MISC

Int. K/B

Matrix

5

4

3

8/23 Pull up 10k (R345) to +3VALW on USB_ON#

8/31 Change EC_MUTE# Pull-up to +3VS(@)

L29

L29 FBMA-L11-160808-800LMT_0603

FBMA-L11-160808-800LMT_0603

1 2

22

9

VCC

PS2 Interface

SM Bus

GND

11

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+EC_VCCA

1

C348

0.1U_0402_16V4Z

2

125

111

96

33

VCC

PWM Output

ACOFF/FANPWM1/GPIO13

AD Input

DA Output

EC_MUTE#/PSCLK1/GPIO4A

USB_EN#/PSDAT1/GPIO4B

CAP_INT#/PSCLK2/GPIO4C

TP_DATA/PSDAT3/GPIO4F

WOL_EN/SDICLK/GPXIOA01

ME_EN/SDIMOSI/GPXIOA02

SPI Device I/F

SPI Flash ROM

GPIO

GPO

GPI

GND

94

35

24

113

Reserve C430 for EC_PROCHOT# Michael 2010/11/18

3

ECAGND

67

AVCC

PWM0/GPIO0F

BEEP#/PWM1/GPIO10

FANPWM0/GPIO12

BATT_TEMP/AD0/GPI38

BATT_OVP/AD1/GPI39

ADP_I/AD2/GPI3A

AD3/GPI3B

AD4/GPI42

AD5/GPI43

DAC_BRIG/DA0/GPO3C

EN_DFAN1/DA1/GPO3D

IREF/DA2/GPO3E

DA3/GPO3F

PSDAT2/GPIO4D

TP_CLK/PSCLK3/GPIO4E

SDICS#/GPXIOA00

LID_SW#/GPXIOD00

SPIDI/MISO

SPIDO/MOSI

SPICLK/GPIO58

SPICS#

GPIO40

H_PECI/GPIO41

FSTCHG/GPIO50

BATT_CHG_LED#/GPIO52

CAPS_LED#/GPIO53

BATT_LOW_LED#/GPIO54

PWR_LED#/GPIO55

SYSON/GPIO56

VR_ON/XCLK32K/GPIO57

AC_IN/GPIO59

EC_RSMRST#/GPXIOA03

EC_LID_OUT#/GPXIOA04

EC_ON/GPXIOA05

EC_SWI#/GPXIOA06

ICH_PWROK/GPXIOA07

BKOFF#/GPXIOA08

RF_OFF#/GPXIOA09

GPXIOA10 GPXIOA11

PM_SLP_S4#/GPXIOD01

ENBKL/GPXIOD02

EAPD/GPXIOD03

EC_THERM#/GPXIOD04

SUSP#/GPXIOD05

PBTN_OUT#/GPXIOD06

EC_PME#/GPXIOD07

AGND

69

20mil

ECAGND

FBMA-L11-160808-800LMT_0603

EC_PROCHOT#

V18R

L30

2010/11/09 2012/11/09

@

@ C403

9/23 Update EC pin definition follow P5WE6

10/04 Add 100p(C399) on ACOFF

Delete EC_FAN_PWM Tock 2011/01/28

21

BEEP#

23

26

ACOFF

27

BATT_TEMP

63

64

ADP_I

65

AD_BID0

66

AD_PID0

75

76

68

EN_FAN1

70

IREF

71

CHGVADJ

72

EC_MUTE#

83

USB_ON#

84 85

PWR_LED1#

86

TP_CLK

87

TP_DATA

88

97

EN_WOL#

98

VLDT_EN#

99

LID_SW#

109

EC_SI_SPI_SO

119

EC_SO_SPI_SI

120

EC_SPICLK

126

EC_SPICS#/FSEL#

128

EDP_BIST DMIC_DATA

73

74

FSTCHG

89

BATT_BLUE_LED#

90 91

BATT_AMB_LED#

92

PWR_LED#

93

SYSON

95

VR_ON

121

EC_ACIN

127

EC_RSMRST#

100

EC_LID_OUT#

101

EC_ON

102

EC_PME#

103

ICH_POK_EC

104

BKOFF#

105

WL_OFF#

106

WXMIT_OFF#

107 108

VGATE

110

APU_ENBKL

112

EAPD

114

EC_PROCHOT#

115

SUSP#

116

PBTN_OUT#

117

WWAN_W AKEUP#

118

V18R

124

10/27 Change C356 from 10V_0805 to 6.3V_0603

12

1

C430

C430 100P_0402_50V8J

100P_0402_50V8J

2

Reserve C403, C443, C444 for ADP_I, TP_CLK, DATA Michael 2010/11/18

ADP_I

1

C403 100P_0402_50V8J

100P_0402_50V8J

2

C351 100P_0402_50V8J

2

9/25 Change VLDT_EN to VLDT_EN#

eDP@

R390

eDP@R390

1 2

0_0402_5%

1

C356

4.7U_0603_6.3V6K

2

LAN_WAKE# BKOFF#

1

C471

100P_0402_50V8J

2

Reserve C471,C472 for LAN_WAKE# , BKOFF# Tock 2011/01/07

Compal Secret Data

Deciphered Date

2

TP_CLK TP_DATA

1

@

C443

@ C443

100P_0402_50V8J

2

C399

ACOFF

BEEP# <17>

ACOFF <31>

1

EN_FAN1 <27>

IREF <31>

CHGVADJ <31>

EC_MUTE# <17>

USB_ON# < 24,25>

PWR_LED1# <23>

TP_CLK <24>

TP_DATA <24>

EN_WOL# <18>

VLDT_EN# <28>

LID_SW# <23>

EC_SI_SPI_SO <27>

EC_SO_SPI_SI <27> EC_SPICLK <27>

EC_SPICS#/FSEL# <27 >

FSTCHG <31>

BATT_BLUE_LED# <22>

BATT_AMB_LED# <22>

PWR_LED# <22> SYSON <28,33>

VR_ON < 36>

EC_RSMRST# <13>

EC_LID_OUT# <13>

EC_ON <23>

BKOFF# <9>

WL_OFF# <21> WXMIT_OFF# <20>

VGATE <13,36>

EAPD <17>

EC_PROCHOT# <4>

SUSP# <28,33,34>

PBTN_OUT# <13>

WWAN_W AKEUP# <20>

C399

12

100P_0402_50V8J

ECAGND

BATT_TEMP <29>

8/23 Delete DAC_BRIG 8/25 Delete CHG_ON#

8/31 Add EN_FAN1 on U12.70

VR_ONAPU_ALERT#_EC

@

1

C472

100P_0402_50V8J

2

1

@

C444

@ C444

100P_0402_50V8J

2

ADP_I <31>

LID_SW#

EDP_BIST

1

2

@

R285

@ R285

100K_0402_5%

1 2

DMIC_DATA <9,17>

C470

C470 220P_0402_50V7K

220P_0402_50V7K

place close to PU2

C400

12

100P_0402_50V8J

1

2

Reserve C477 for FSTCHG Tock 2011/01/07

VGATE

C423

C423 100P_0402_50V8J

100P_0402_50V8J

Reserve C423 for VGATE Michael 2010/11/18

R281

R281 100K_0402_5%

100K_0402_5%

1 2

EC_MUTE#

USB_ON#

TP_CLK

TP_DATA

8/26 Change D18 to SCS00002G00 Standard Part

9/23 Reserve R395 on ACIN

10/08 Change D18 to SCS00000Z00

R268 200K_0402_5%R 268 200K_0402_5%

D18

RB751V-40_SOD323-2

EC_ACIN

RB751V-40_SOD323-2

C352 100P_0402_50V8JC352 100P_0402_50V8J

@

1 2

R395 0_0402_5%

Follow PAWGC

ICH_POK_EC

R273 0_0402_5%R273 0_0402_5%

Reserve C470 for LID_SW# Tock 2011/01/07

Add EDP_BIST and Reserve C390 , R285 Tock 2010/12/30

LID_SW#

FSTCHG

1

C477

C477 100P_0402_50V8J

100P_0402_50V8J

2

APU_ENBKL <4>

1

C447

C447 100P_0402_50V8J

100P_0402_50V8J

2

Reserve C447 for APU_ENBK Tock 2011/01/07

LAN_WAKE#<18>

PCI_PME#<13>

+3VALW

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

EC ENE-KB930

P1VE6 Schematics

1

R259 10K_0402_5%@R259 10K_0402_5%@

R345 10K_0402_5%R345 10K_0402_5%

R263 4.7K_0402_5%R263 4.7K_0402_5%

R264 4.7K_0402_5%R264 4.7K_0402_5%

12

D19 RB751V-40_S OD323-2

1 2

R278 100K_0402_5%R278 100K_0402_5%

Ra

Rb

PME Follow PAWGC

1 2

R323 0_0402_5%

1 2

R324 0_0402_5%@R324 0_0402_5%@

S

1 2

@

+3VALW

R398

0_0402_5%

1 2

AD_PID0

12

R399

8.2K_0402_5%

@

D

13

Q29

G

SSM3K7002FU_SC70-3

2

@

1

12

+3VALW

@

1 2

R274 10K_0402_5%

12

@

1

@

@R399

2

+3VALW

R322

R322 10K_0402_5%

10K_0402_5%

1 2

26 37Thursday, March 17, 2011

+3VS

+5VS

ACIN <31>

ICH_POK <13>

+3VS

+3VALW

Project ID

@

C393

@C393

0.1U_0402_16V4Z

EC_PME#

+3VALW

1.0

3P2 x 3 (APU)

Dr-Bios.com

3P0N x 1

2P3 x 2

2P5 x 4

0P6X2P3 x 2

EC_SPICS#/FSEL#<26>

EC_SI_SPI_SO<26>

H1

H1 H_3P2

H_3P2

1

@

H4

H4 H_3P0N

H_3P0N

1

@

H8

H8 H_2P3

H_2P3

1

@

H6

H6 H_2P5

H_2P5

1

@

H12

H12 H_0P6X2P3

H_0P6X2P3

1

@

H2

H2 H_3P2

H_3P2

1

@

H9

H9 H_2P3

H_2P3

1

@

H7

H7 H_2P5

H_2P5

1

@

+3VALW

R201

1 2

R202

1 2

EC_SPICS#/FSEL#

EC_SI_SPI_SO EC_SPI_SO

H3

H3 H_3P2

H_3P2

1

@

H11

H10

H_2P5

1

@

H15

H15 H_0P6X2P3

H_0P6X2P3

1

@

SPI_WP#

3.3K_0402_5%

SPI_HOLD#

3.3K_0402_5%

R203

0_0402_5%

EC_SPICS#/FSEL#_R

1 2

33_0402_5%

R204

Layout Note: R204 close to U7

Update the Screw Hole 2010/12/16 Tock

Update the Screw Hole 2010/12/22 Tock

FM1

@

1

2MB SPI ROM Share ROM.

W=20mil

+3VALW

U7

1

CS#

2

SPI_WP#

DO(IO1)

3

WP#(IO2)

4

GND

W25Q16BVSSIG_SO8

SA00003FO00

9/15 Update the Screw Hole

9/20 Add H20 (H_3P4X3P2N)

10/07 Change H13 from GND to LANGND

10/07 Change H13 from LANGND to GND

FM3

FM4

FM2

@

1

FM4

@

1

VCC

HOLD#(IO3)

CLK

DI(IO0)

@

FIDUCIAL_C40M80

1

8 7

6 5

SPI_HOLD#

EC_SPICLK_R

EC_SPI_SI

8/31 Remove EC ROM , Add SPI ROM

C212

1 2

0.1U_0402_16V4Z

Layout Note: R203 R205 R206 close to U12

R2060_0402_5% R 2060_0402 _5%

EC_SPICLK

1 2

EC_SO_SPI_SI

1 2

33_0402_5%

R205

Delete U17,C382,C386,R355,D20,C383,C384,C385 for Fan control IC circuit 2010/12/15 Tock

FAN Conn.

EN_FAN1<26>

+5VS

8/24 Update JFAN1 Symbol from database (ACES_85205-03001_3P) & Update pin definition 8/24 Delete R290

8/25 Update JFAN1 Symbol from database (ACES_85205-04001_4P) & Update pin definition 8/25 Add R290 10k pull-up tp +3VS

8/31 Reserve U17,C382~C386, R355~R357, D20 (Fan Drive Circuit)

change JFAN1 footprint from ACES_85205-04001_4P to ACES_50273-0030N-001_3P , 2011/01/28 Tock ,

delete EC_FAN_PWM and R356,R357 , 2011/01/28 Tock ,

EC_SPICLK <26>

EC_SO_SPI_SI <26>

+VCC_FAN1

1 2

R355 330_0402_5%R355 330_0402_5%

1 2

R289 0_0603_5%

@

EN_FAN1_R

1

2

+5VS

1

C386

0.01U_0402_16V7K

2

C360

10U_0805_10V6K

9/2 Change EC_SPICLK to EC_SPICLK_R

EC_SPICLK_R

12

R200

33_0402_5%

@

C211

22P_0402_50V8J

@

EMI

Add U17,C382,C386,R355,D20,C383,C384,C385 for Fan control IC circuit 2011/01/19 Tock

C382 2.2U_0603_10V6KC382 2.2U_0 603_10V6K

1 2

U17

1

EN

2

VIN

3

VOUT

4

VSET

APL5607KI-TRG_SO8

FAN_SPEED1<26>

GND GND

8 7

6 5

+3VS

12

R290

10K_0402_5%

+VCC_FAN1+VCC_FAN1

40mil

+VCC_FAN1

+5VS

3

@

2

D20

D20 DAN217_SC59

DAN217_SC59

@

1

1 2

4.7U_0603_6.3V6K

@

1 2

4.7U_0603_6.3V6K

@

1 2

1000P_0402_50V7K

1 2

3

4

5

C383

C384

C385

JFAN1

1 2

3

GND

ACES_50273-0030N-001

CONN@

H14

H13

H13 H_3P0X4P0N

3P0X4P0N x 2

H_3P0X4P0N

@

H14 H_3P0X4P0N

H_3P0X4P0N

1

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

2010/11/09 2012/11/09

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

Screw / EC ROM /FAN

P1VE6 Schematics

27 37Thursday, March 17, 2011

of

1.0

A

Dr-Bios.com

B

C

D

E

10/27 Change R291 Q18 from @ to mount

+1.5VS

3

1

DGS

2

1

2

Remove C362 10U Michael 2010/11/18

1

C363

1U_0603_10V6K

2

Q18

SSM3K7002FU_SC70-3

10/29 Change R298 from 0 ohm to 100k

C373

0.1U_0402_16V4Z

Q18

10/31 Change C373 from 0603_25V to 0402_16V

100K_0402_5%

SYSON#

SYSON<26,33>

SYSON

SSM3K7002FU_SC70-3

10/31 Change C361 C362 from mount to @

Q31

@

R303

@

2

G

12

R291

R291 470_0603_5%

470_0603_5%

13

D

S

+5VALW

12

13

D

S

SUSP

2

G

+5VS

C370

0.1U_0603_25V7K

Remove C365 10U Michael 2010/11/18

1

C366

C366 1U_0603_10V6K

1U_0603_10V6K

2

12

R292

R292 470_0603_5%

470_0603_5%

@

13

D

SUSP

2

G

Q16

S

SSM3K7002FU_SC70-3

U14

+VSB

12

R294

R294 82K_0402_5%

82K_0402_5%

+5VS_GATE

13

D

SSM3K7002FU_SC70-3

Q19

S

+5VALW

AP4800BGM-HF_SO-8

8 7

6

5

SB548000210 SB548000210

R297

1

20K_0402_5%

Remove C364 10U Michael 2010/11/18

1 1

SUSP

2

G

4

+5VS_GATE_R

2

U14

1

2

3

1

2

Remove C367 10U Michael 2010/11/18

@

+3VALW TO +3VS+5VALW TO +5VS

+VSB

12

SUSP

13

2

G

Q20 SSM3K7002FU_SC70-3

U15

R350

U15

1

2

3

4

+3VALW

AP4800BGM-HF_SO-8

8 7

6

5

R295

R295 120K_0402_5%

120K_0402_5%

+3VS_GATE +3VS_GATE_R

1 2

D

0_0402_5%

S

Remove C368 10U

+3VS

Michael 2010/11/18

1

C369

1U_0603_10V6K

2

change R295 from 200K to 120K Tock 2011/01/03

1

C371

0.1U_0603_25V7K

2

9/27 Change Q21.2 from SUSP# to SUSP

12

R293

470_0603_5%

@

13

D

SUSP

2

G

Q17

S

SSM3K7002FU_SC70-3

@

+1.5V to +1.5VS

Remove C361 10U Michael 2010/11/18

+5VALW

12

R296

R296 200K_0402_5%

200K_0402_5%

+1.5VS_GATE +1.5VS_GATE_R

13

D

SUSP#

D

2

G

Q21 SSM3K7002FU_SC70-3

S

+1.5V

SB000006R10

R298

100K_0402_5%

Q15

AO3413L_SOT23-3

12

9/27 Change R296.1 from +5VALW to +VSB

+1.1ALW to +1.1VS

U16

Remove C374 10U Michael 2010/11/18

2 2

+VSB

+1.1VS_ON#

2

G

Q24

SSM3K7002FU_SC70-3

3 3

Q25A

4 4

9/27 Change R304.1 from +5VALW to +VSB

Change Q25 package to SOT363-6 Remove Q26 Michael 2010/11/18

+1.8VS +0.75VS

12

R306

R306 470_0603_5%

470_0603_5%

@

61

@

SUSP SYSON#

2

2N7002DW-T/R7_SOT363-6

+1.1VALW +1.1VS

AP4800BGM-HF_SO-8

8 7

6

5

SB548000210

12

R304

R304 47K_0402_5%

47K_0402_5%

+1.1VS_GATE +1.1VS_GATE_R

13

D

S

R351

0_0402_5%

Q25B

U16

4

12

Change Q27 package to SOT363-6 Remove Q28 Michael 2010/11/18

+1.05VS

12

R308

R308 470_0603_5%

470_0603_5%

@

3

@

SUSP

5

2N7002DW-T/R7_SOT363-6

4

Remove C375 10U Michael 2010/11/18

1

2

3

1

C378

0.1U_0603_25V7K

2

Q27A

1

2

+1.5V

12

R307

R307 470_0603_5%

470_0603_5%

@

61

@

2

2N7002DW-T/R7_SOT363-6

C376

1U_0603_10V6K

10/12 Change R402 from mount to @

10/12 Change R400 R403 from @ to mount

12

R300

R300 470_0603_5%

470_0603_5%

@

13

D

+1.1VS_ON#

2

G

Q22SSM3K7002FU_SC70-3 @

S

10/12 Change R294 to 100k

10/12 Change R295, R296 to 200k

10/12 Change R304 to 47k

10/12 Change R294 to 82k

10/12 Change R297 to 20k

12

R309

R309 470_0603_5%

470_0603_5%

@

3

@

Q27B

@Q27B

SUSP

5

4

2N7002DW-T/R7_SOT363-6

+1.1VS_ON# SUSP

C404 100P_0402_50V8J

2

1

@

1 2

R402 0_0402_5%

1 2

R403 0_0402_5%R403 0_0402_5%

VLDT_EN#

10/04 Add 100p(C404) on VLDT_EN#

10/06 Change C404 on +1.1VS_ON#

8/19 Change Q16~Q22 Q24~Q28 toSB000009610(SSM3K7002FU_SC70-3)

8/19 Change Q29 Q30 to Q23A Q23B (SB00000DH00 S TR DMN66D0LDW-7 2N SOT363-6)

8/21 Change U14~U16 to SB548000310 (SI4800BDY-T1-E3_SO8)

8/23 Remove R305 R299 Add R350 R351 for Sequence

8/24 Change Q23A Q23B to Q30 Q31(@) (SB000009610 SSM3K7002FU_SC70-3)

8/25 Change C363,C366,C369,C376 to SE080105K80 Standard Part

8/25 Change C361,C362,C364,C365,C367,C368,C374,C375 to SE000004880 Standard Part

8/26 Change U14, U15, U16 to SB00000GV00 Standard Part

9/3 Delete C377(DIS@)

9/23 Reserve R400~403, Q36 for VLDT_EN

9/25 Remove R401 Q36 on VLDT_EN

9/25 Add 10k(R404) PD on SUSP#

10/27 Add C408(100P) on SUSP# close to PR70

9/27 Change Q15 to U19(SB00000GV00)

9/28 Change Q21.2 from SUSP to SUSP#

+5VALW

9/28 Change R296.1 from +VSB to +5VALW

9/28 Change U19 to Q15(SB934130020)

9/28 Remove C372

12

R400

R400 100K_0402_5%

100K_0402_5%

VLDT_EN# <26>

SUSP#<26,33,34>

C408 100P_0402_50V8JC408 100P_0402_50V8J

SUSP<35>

1 2

SUSP

12

R404

R404 10K_0402_5%

10K_0402_5%

2011/02/11 Change Q15 to SB000006R10

+5VALW

12

R302

R302 100K_0402_5%

100K_0402_5%

10/04 Add 100p(C403) on SUSP

10/06 Remove C403

13

D

2

G

Q30

S

SSM3K7002FU_SC70-3

9/27 Change R302 from @ to mount, remove R301

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

2010/11/09 2012/11/09

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

DC Interface

P1VE6 Schematics

28 37Thursday, March 17, 2011

E

1.0

A

Dr-Bios.com

B

C

D

1 1

PJP2

1

2

3

4

5

6

7

8

9

GND

10

GND

@

SUYIN_200275MR008G15QZR

2 2

3 3

100K_0402_1%

POK<31,33>

VMB

B/I TS

EC_SMDA

PR12

100_0402_1%

PR18

1 2

EC_SMCA

PR13

100_0402_1%

VL

1 2

PR19

1 2

0_0402_5%

PC12

.1U_0402_16V7K

12

PR6

PR6 1K_0402_1%

1K_0402_1%

PR9

6.49K_0402_1%

12

PR14

1K_0402_1%

1 2

B+

12

PC10

PR16

@

100K_0402_1%

0.22U_0603_25V7K

PC12

PR17

1 2

22K_0402_1%

13

D

PQ3

2

SSM3K7002FU_SC70-3

G

S

12

VMB

12

PC7

1000P_0402_50V7K

+3VALW

BATT_TEMP <25>

EC_SMB_CK1 <25>

EC_SMB_DA1 <25>

PQ2

TP0610K-T1-E3_SOT23- 3

2

HCB2012KF-121T50_0805

1 2

13

12

PL2

@

PC11

@PC11

0.1U_0603_25V7K

+VSBP

12

PC8

0.01U_0402_25V7K

BATT+

PC9

0.1U_0402_10V7K

PH1 under CPU botten side :

CPU thermal protection at 92 degree C Recovery at 72 degree C

VL

12

VL

PU1

@

PR10

@PR1 0

100K_0402_1%

MAINPWO N<3 1>

1 2

PU1

1

TMSNS1

VCC

2

RHYST1

GND

3

TMSNS2

OT1

4

OT2

RHYST2

G718TM1U_SOT23-8

100K_0402_1%_NCP15W F104F03RC

8

7

6

5

PR7

10K_0402_1%

@

PR15

47K_0402_1%

PH2

PR7

12

PR8

22.1K_0402_1%

1 2

12

PR11

15K_0402_1%

12

@

@PH2

12

PH1

100K_0402_1%_NCP15W F104F03RC

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

A

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

2012/08/122010/08/12

Title

Size D ocument Number Rev

Date: Sheet of

Compal Electronics, Inc.

BATTERY CONN / OTP

29 37Thursday, March 17, 2011

D

29 37Thursday, March 17, 2011

1.0

A

Dr-Bios.com

B

C

D

VIN

PD1

RLS4148_LL34-2

PR1

68_1206_5%

13

1 2

12

PR2

PR2 68_1206_5%

68_1206_5%

12

PC5

0.1U_0603_25V7K

VS

1 1

PL1

HCB2012KF-121T50_0805

PR5

HCB2012KF-121T50_0805

1 2

12

PC2

100P_0402_50V8J

+3VLP

12

PC3

1000P_0402_50V7K

CONN@

ACES 88266-04001

1

2

5

3

GND

3

6

4

GND

4

PJP1

SP02000GC00

2 2

DC_IN_S1

+CHGRTC

12

PC1

1000P_0402_50V7K

0_0603_5%

1 2

VIN

PQ1

TP0610K-T1-E3_SOT23- 3

PD2

RLS4148_LL34-2

100K_0402_1%

1 2

22K_0402_1%

PR4

12

PR3

12

BATT+

12

PC4

100P_0402_50V8J

51_ON#<22>

TP0610K-T1-E3_SOT23- 3

N1

PC6

0.22U_0603_25V7K

2

@

PJ2

@

PJ1

2

+3VALWP

3 3

+5VALWP

4 4

+VSBP

+1.5VP

12

@

PC248

@PC2 48

.1U_0402_16V7K

12

@

PC252

@PC2 52

.1U_0402_16V7K

12

@

PC253

@PC2 53

.1U_0402_16V7K

12

@

PC257

@PC2 57

.1U_0402_16V7K

12

PC258

PC258 .1U_0402_16V7K

.1U_0402_16V7K

2

JUMP_43X118

@

PJ3

@ PJ3

2

JUMP_43X118

PJ5

@

2

JUMP_43X39

@

PJ7

@ PJ 7

2

JUMP_43X118

@

PJ9

2

JUMP_43X118

1

12

PC241

PC241 .1U_0402_16V7K

.1U_0402_16V7K

12

PC243

PC243 .1U_0402_16V7K

.1U_0402_16V7K

+VSB

12

PC245

PC245 .1U_0402_16V7K

.1U_0402_16V7K

12

PC247

PC247 .1U_0402_16V7K

.1U_0402_16V7K

12

PC249

PC249 .1U_0402_16V7K

.1U_0402_16V7K

+3VALW

+5VALW

+0.75VSP

+1.8VS+1.8VSP

+1.5V

A

12

@

PC254

@PC2 54

.1U_0402_16V7K

12

@

PC255

@PC2 55

.1U_0402_16V7K

12

@

PC256

@PC2 56

.1U_0402_16V7K

@ PJ 2

2

JUMP_43X118

@

PJ4

@ PJ 4

2

JUMP_43X118

@

PJ6

@ PJ6

2

JUMP_43X79

1

+1.1VALW+1.1VALW P

12

PC242

PC242 .1U_0402_16V7K

.1U_0402_16V7K

+1.05VS+1.05VSP

12

PC244

PC244 .1U_0402_16V7K

.1U_0402_16V7K

12

PC246

PC246 .1U_0402_16V7K

.1U_0402_16V7K

B

+0.75VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

C

2012/08/122010/08/12

Compal Electronics, Inc.

Title

Size D ocument Number Rev

Date: Sheet of

Compal Electronics, Inc.

DCIN/VIN DECTOR

30 37Thursday, March 17, 2011

D

30 37Thursday, March 17, 2011

1.0

5

Dr-Bios.com

4

3

2

1

Iada=0~2.105A(40W/19V=2.105A)

PL18

ADP_I = 19.9*Iadapter*Rsense

PD3

2 1

VIN

D D

12

PR22

PR22 200K_0402_1%

200K_0402_1%

13

BATT_ON ACPRN

C C

2

61

D

2

G

PQ9A

S

DMN66D0LDW -7_SOT363-6

PACIN

DTC115EUA_SC70-3

ACOFF<25>

ACOFF

SX34_SMA2

2

PQ8

PQ8 DTC115EUA_SC70-3

DTC115EUA_SC70-3

PR40

47K_0402_1%

1 2

PQ12

PQ6

1 3

DTA144EUA_SC70-3

DMN66D0LDW -7_SOT363-6

2

P2

1

2

3

12

PR23

PR23 200K_0402_1%

PC17

13

200K_0402_1%

0.1U_0603_25V7K

12

PR30

150K_0402_1%

PQ9B

34

D

5

G

S

IREF<25>

4

ADP_I<25>

62K_0402_1%

100K_0402_1%

AON7403L_DFN8-5

PQ4

5

FSTCHG<25>

0.01U_0402_25V7K

PR39

12

PR44

1 2

12

P3

PC13

PC13 5600P_0402_25V7K

5600P_0402_25V7K

10K_0402_1%

PC24

6251VREF

12

PC31

0.01U_0402_25V7K

1

2

ACSETIN

PR29

12

100K_0402_1%

PR35

1 2

10K_0402_1%

PC26

1 2

.1U_0402_16V7K

1 2

4.7K_0402_1%

PR20

0.05_1206_1%

PR31

PR43

B+

4

3

PC18

12

PC23

1 2

6800P_0402_25V7K

PR37

1 2

47K_0402_1%

6251VREF

6251ACLIM

12

PR46

6251VDD

RB751V-40_SOD323-2

12

2.2U_0603_6.3V6K

PU2

1

VDD

2

ACPRN

ACSET

6251_EN CSON

3

EN

4

CELLS

5

ICOMP

6

VCOMP

7

ICM

PHASE

8

VREF

UGATE

9

CHLIM

10

ACLIM

11

LGATE

VADJ

12

GND

ISL6251AHAZ-TR5283_QSOP 24

20K_0402_1%

12

@

PD4

PR26

10_1206_5%

DCIN

CSON

CSOP

CSIN

CSIP

BOOT

VDDP

PGND

12

PC250

PC237

@

10U_0805_25V6K

VIN

1 2

12

PC19

1000P_0402_25V8J

PC20

DCIN

24

0.1U_0603_25V7K

23

22

21

20

19

18

17

16

15

14

13

PC22

0.047U_0402_16V7K

1 2

PR33

PR34 20_0402_5%PR34 20_0402_5%

PC25

0.1U_0603_25V7K

1 2

LX_CHG

DH_CHG

BST_CHG

6251VDDP

DL_CHG

PC251

@

10U_0805_25V6K

12

PR24

PR24 191K_0402_1%

191K_0402_1%

12

PR28

14.3K_0402_1%

12

PR32 2 0_0402_5%PR32 20_0402_5%

1 2

PR36 2_0402_5%PR36 2_0402_5%

PR42

1 2

0_0603_5%

PC32

4.7U_0603_6.3V6M

1 2

CP = 85%*Iada ; CP = 1.789A

PL18

1.2UH_1231AS-H-1R2 N=P3_2.9A_30%

HCB2012KF-121T50_0805

CSIN

CSIP

ACSETIN

1 2

20_0402_5%

12

BST_CHGA

12

PD5

PD5 SD103AWS SOD323-2

SD103AWS SOD323-2

1 2

PR45 4.7_0603_5%PR45 4.7_0603_5%

@

PL3

@ PL3

PC27

0.1U_0603_25V7K

12

PC14

4.7U_0805_25V6-K

CSOP

12

6251VDD

12

PQ5

PR25

10K_0402_1%

2

CHGCH G

PQ5 AON7403L_DFN8-5

AON7403L_DFN8-5

1

2

3

4

PR27

PR27 100K_0402_1%

100K_0402_1%

1 2

12

@

PC21

PC21 2200P_0402_50V7K

2200P_0402_50V7K

PR38

1

2

0.05_1206_1%

5

PR21

1 2

47K_0402_1%

BATT_ON

4

3

VIN

BATT+

12

PC29

10U_0805_25V6K

12

PC30

PC205

PC204

@

10U_0805_25V6K

CHG_B+

12

PC15

PC16

4.7U_0805_25V6-K

1 2

13

PQ7

DTC115EUA_SC70-3

PQ10

PQ10 AON7408L_DFN8-5

AON7408L_DFN8-5

5

4

PL4

1 2

12

@

PR41

@ PR41

4.7_1206_5%

12

@

PC28

680P_0603_50V7K

PL4

10UH_VMPI0703AR-100M- Z01_3.5A_20%

3

2

1

5

4

PQ11

3

2

1

AON7408L_DFN8-5

B B

CHGVADJ<25>

BATT Type

Charging Voltage (0x15)

CV mode

CC=0.25~3.52A

IREF=0.7224*Icharge

Normal 3S LI-ON Cells

Ki Vchlim=Iref*(PR 39/(PR39+PR44)) =Iref*(100K/(80 .6K+100K)) =Iref*0.617 Ichanrge=(165mV/PR38)*(Vchlim/3.3V) =(165m/50m)*(1/ 3.3V)*Iref*0.61 7 =0.617*Iref Iref=1.62*Ichan rge =>Ki=1.62

Kv Rinternal ic=514K Rec=3K R1=PR379=15.4K R2=PR381=31.6K

A A

R=514K//31.6K// (15.4K+3k)=11.3 72K r=514K//514K//3 1.6K=28.14K Vcell=0.175*Vad j+3.99v

4.2V=0.175*Vadj +3.99V =>Vadj=1 .2V Vadj=Vref*(R/(R +514K))+CALIBRA TE*(r/(r=514K) )

1.1483=CALIBRAT E*0.6046 =>CALI BRATE=1.899

1.899=(4.2-(Vce ll+A*0.175))*Kv =(4.2-(4.2+A*0 .175))*Kv A=Vref*(R/(R+51 4K))=0.052 Kv=9.451

12600mV

12.60V

IREF=0.43V~3.24V

5

4

PR47

1 2

15.4K_0402_1%

ACPRN

PR48

31.6K_0402_1%

1 2

PR49

47K_0402_1%

6251VDD

Vth,rise(typical) = ((191K/14.3K)+1)*1.26

Vth,fall(typical) = ((191K/14.3K)+1)*1.26 -3.4uA*191K

PR51

12

PR50

PR50 10K_0402_1%

10K_0402_1%

13

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PR51

10K_0402_1%

1 2

PQ13

PQ13 DTC115EUA_SC70-3

DTC115EUA_SC70-3

12

PR52

14.3K_0402_1%

3

ACIN <25>

PACIN

Compal Secret Data

2010/08/12 2012/08/12

Compal Secret Data

Deciphered Date

2

= 18.089V

= 17.44V

Title

Size D ocument Number Rev

Date: Sheet of

Compal Electronics, Inc.

CHARGER

31 37Thursday, March 17, 2011

1

1.0

5

Dr-Bios.com

4

3

2

1

2VREF

D D

1U_0402 _6.3V6K

PC33

12

+5VALW Vo= (2*30K/19.1K)+2=5.141V+3VALW Vo= (2*13.7K/20K)+2=3.37V

PR54

PR53

13.7K_04 02_1%

1 2

PR55

BST_3V

UG_3V

LX_3V

LG_3V

PR55

20K_040 2_1%

1 2

PR57

130K_04 02_1%

1 2

PU3

25

P PAD

7

VO2

8

VREG3

9

BOOT2

10

UGATE2

11

PHASE2

12

LGATE2

12

PR64

100K_0402_5%

2VREF

ENTRIP2

6

ENTRIP2

EN

13

B++

5

4

3

FB2

REF

TONSEL

GND

VIN

SKIPSEL

15

16

14

12

B++

PL5

HCB2012 KF-121T50_080 5

1 2

B+

PQ14

PR61

4.7_1206 _5%

PC45

100K_04 02_1%

PR67

@

PR65

12

PQ14

@

PQ18A

5

4

3

2

1

5

12

3

2

1

61

D

S

12

PC50

42.2K_0402_1%

@

0.1U_0402_10V7K

0.1U_060 3_25V7K

4

PQ16

PQ16 FDMC769 2S_MLP8-5

FDMC769 2S_MLP8-5

ENTRIP1

2

G

13

2

B++

5

G

PQ19

PQ19 DTC115E UA_SC70-3

DTC115E UA_SC70-3

12

PC35

PC239

C C

PC239

4.7U_0805_25V6-K

+3VALWP

PC43

220U_6.3 V_M

B B

12

PC36

4.7U_0805_25V6-K

2200P_0402_50V7K

4.7UH_FD SD0630-H-4R7M-P 3_5.5A_20%

1

+

2

AON7408 L_DFN8-5

PL6

1 2

680P_06 03_50V7K

DMN66D0 LDW-7_SOT3 63-6

VL

MAINPW ON<29 >

PR66

VS

A A

1 2

100K_04 02_1%

12

PC38

4.7U_0603_6.3V6K

PC41

1 2

499K_04 02_1%

1 2

1U_0402 _6.3V6K

ENTRIP2

34

D

PQ18B

DMN66D0 LDW-7_SOT3 63-6

S

+3VLP

PR59

1 2

0_0603_ 5%

PR63

12

PC47

+3.3VALWP Imax=4.214A ; Ipeak=6.02A ; Iocp=1.2*Ipeak=7.224A f=375KHz, L=4.7UH,Rentrip2=130K ohm Rdson=14.5~17.9m ohm (IRFH3707) 1/2Delta I = 1/2 *(19-3.3)*(3.3/19)/(375KHz*4.7UH)=0.773A Vtrip2=(10*10^-6*150Kohm/9)-24mV=0.143V Ilimit=0.143/(17.9m*1.2)~0.143/(14.5m)=6.642A~9.839A Iocp=7.415A~10.613A (7.415A>7.224A -> OK)

PR54

30K_040 2_1%

1 2

PR56

19.1K_04 02_1%

1 2

ENTRIP1

PR58

143K_04 02_1%

1 2

1

2

FB1

ENTRIP1

VO1

PGOOD

BOOT1

UGATE1

PHASE1

LGATE1

VREG5

NC

RT8205E GQW_W QFN24_4X4

17

18

12

PC48

4.7U_060 3_6.3V6K

PC49

0.1U_060 3_25V7K

B++

12

PC40

PC39

2200P_0402_50V7K

24

23

22

21

20

19

BST_5V

UG_5V

LX_5V

LG_5V

PR60

1 2

0_0603_ 5%

1 2

4.7U_0805_25V6-K

POK <2 9,33>

PC42

0.1U_060 3_25V7K

FDMC769 2S_MLP8-5

PC240

12

PC37

0.1U_0603_25V7K

4.7U_0805_25V6-K

PQ17

4

PQ15

5

AON7408 L_DFN8-5

3

2

1

4.7UH_FD SD0630-H-4R7M-P 3_5.5A_20%

1 2

5

12

@

PR62

4.7_1206 _5%

12

@

PC46

2

1

PC46 680P_06 03_50V7K

680P_06 03_50V7K

3

PL7

+5VALWP

1

+

PC44

2

220U_6.3V_M

VL

TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP) (2)SMPS2=375KHZ (+3VALWP)

+5VALWP Imax=4.9A ; Ipeak=7A ; Iocp=1.2*Ipeak=8.4A f=300KHz, L=4.7UH,Rentrip1=143K ohm Rdson=14.5~17.9m ohm (IRFH3707) 1/2Delta I = 1/2 *(19-5)*(5/19)/(300KHz*4.7UH)=1.306A Vtrip1=(10*10^-6*162Kohm/9)-24mV=0.156V Ilimit=0.156/(17.9m*1.2)~0.156/(15m)=7.263~10.759A Iocp=8.569~12.065A (8.569>8.4 -> OK)

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

2010/08/ 12 2012/08/ 12

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Rev

Date: Sheet of

2

Date: Sheet

Compal Electronics, Inc.

3VALWP/5VALWP

Thursday, March 17, 2011

1

32 37

of

1.0

D

Dr-Bios.com

B+

+1.5VP

PR69

12

4

C

12

PR71

10K_0402_1%

5

3

2

1

5

3

2

1

+1.8VSP

12

PC52

12

68P_0402_50V8J

12

PC59

4.7U_0805_25V6-K

12

PC53

22U_0805_6.3VAM

12

PC61

PC60

0.1U_0603_25V7K

4.7U_0805_25V6-K

2.2UH_FDSD0630-H- 2R2M-P3_8.3A_20%

@

PR79

@PR7 9

4.7_1206_5%

@

PC66

@PC6 6

680P_0603_50V7K

<Vo=1.8V> VFB=0.6V Vo=VFB*(1+PR69/PR71)=0.6*(1+20.5K/10K)=1.83V

Ipeak=2A, Imax=1.4A

PC54

22U_0805_6.3VAM

PL9

HCB2012KF-121T50_0805

1 2

12

PC62

2200P_0402_50V7K

PL10

12

1

+

PC65

330U_2.5V_M

2

SY8033BDBC_DFN10_3X3

12

15

14

1

TP

EN_SKIP

VFB=0.75V

PGND

AGND

G5603RU1U_TQFN14_3P5X3 P5

8

7

B

12

PC56

0.22U_0402_10V6K

PR74

255K_0402_1%

1 2

BST_1.5V

BST

13

DH

12

LX

11

ILIM

10

VDD

9

DL

PU4

10

9

8

5

1 2

0_0603_5%

DH_1.5V

LX_1.5V

4

PVIN

SVIN

EN

TP

11

PR77

1 2

15K_0402_1%

PG

PR73

7

NC

LX

FB

NC

1

BST_1.5V-1

DL_1.5V

2

3

6

LX_1.8VS

FB=0.6Volt

1 2

0.1U_0603_25V7K

+5VALW

PC67

4.7U_0603_6.3V6K

1 2

PC64

PL8

1UH_FDV0630-1R0M-P 3_10.3A_20%

12

20.5K_0402_1%

4.7_0603_5%

12

680P_0603_50V7K

AON7408L_DFN8-5

FDMC7692S_MLP8-5

20.5K_0402_1%

FB_1.8VS

PQ20

PQ21

PR68

PC55

A

@

PJ10

@ PJ10

2

1

JUMP_43X39

@

PC63

.1U_0402_16V7K

1

12

PC51

PC51 22U_0805_6.3VAM

22U_0805_6.3VAM

PR70

1 2

200K_0402_1%

499K_0402_1%

EN_1.8VS

PR72

PU5

2

TON

3

OUT

4

VCC

5

FB

6

PGOOD

@

PR75

1 2

0_0402_5%

PR78

1 2

100_0603_5%

4.7U_0603_6.3V6K

+5VALW

30K_0402_5%

PC58

PR76

SUSP#<25,27,33>

12

1 1

2 2

SYSON<25, 27>

+5VALW

3 3

PR80

1 2

5.36K_0402_1%

12

PR81

5.1K_0402_1%

4 4

Temperature Compensated

Vtrip_min (SPEC)

Vtrip_max (SPEC)

G5603 TPS51117 RT8209MRT8209B

-1180ppm/

℃℃℃℃

1600ppm/

℃℃℃℃

4500ppm/

℃℃℃℃

4800ppm/

30mV 50mV 30mV 50mV

200mV 200mV 200mV 200mV

℃℃℃℃

A

<Vo=1.5V> VFB=0.75V V=0.75*(1+5.36K/5.1K)=1.538V

Cout ESR=25m ohm Rdson(max)=17.9 mohm Rdson(typ)=14.5 mohm. (IRFH3707) Ipeak=6.5A, Imax=4.55A, Iocp > 7.8A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/12 2012/08/12

Compal Secret Data

Deciphered Date

C

RT8209BG5603

6.821A 7.235A 8.000A 8.178AOCP setting

Title

Size D ocument Number Rev

Custom

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

1.8VSP/1.5VP

RT8209MTPS51117

33 37Thursday, March 17, 2011

D

33 37Thursday, March 17, 2011

1.0

of

C

Dr-Bios.com

PL11

HCB2012KF-121T50_0805

1.1VALW _B+

12

PC70

PC71

0.1U_0603_25V7K

2200P_0402_50V7K

12

B+

<Vo=1.1V> VFB=0.75V V=0.75*(1+4.99K/10K)=1.124V

Cout ESR=25m ohm Rdson(max)=17.9 mohm Rdson(typ)=14.5 mohm. (IRFH3707) Ipeak=4.02A, Imax=2.814A, Iocp > 4.824A

G5603 RT8209B TPS51117 RT8209M

+1.1VALW P

OCP setting 5.799A 6.183A 6.845A 6.976A

1

+

PC74

2

330U_2.5V_M

PL13

HCB2012KF-121T50_0805

1.05VALW _B+

12

B+

13

12

11

10

9

B

BST_1.1V ALW

DH_1.1VALW

LX_1.1VALW

1 2

PR88

13K_0402_1%

DL_1.1VALW

PC73

1 2

0.1U_0603_25V7K

+5VALW

12

PC76

4.7U_0603_6.3V6K

12

PQ22

1

AON7408L_DFN8-5

PQ23

FDMC7692S_MLP8-5

1

12

5

4

3

2

5

4

3

2

PC69

PC68

4.7U_0805_25V6-K

PL12

2.2UH_FDSD0630-H- 2R2M-P3_8.3A_20%

1 2

12

PR86

4.7_1206_5%

@

@ PR86

12

PC77

@

@ PC77

680P_0603_50V7K

A

PR82

PU6

TON

OUT

VCC

FB

PGOOD

PR82

255K_0402_1%

1 2

15

1

TP

EN_SKIP

VFB=0.75V

AGND

7

8

PR85

0_0603_5%

1 2

14

BST

DH

LX

ILIM

VDD

DL

PGND

G5603RU1U_TQFN14_3P5X3 P5

1 1

PR83

0_0402_5%

POK<29,31>

+5VALW

2 2

1 2

30K_0402_5%

PR87

100_0603_1%

1 2

PC75

4.7U_0603_6.3V6K

PR84

12

PC72

PC72 .1U_0402_16V7K

.1U_0402_16V7K

@

12

@

PR89

4.99K_0402_1%

1 2

12

PR90

PR90 10K_0402_1%

10K_0402_1%

2

3

4

5

6

D

12

PQ24

2

1

AON7408L_DFN8-5

PQ25

2

1

12

PC78

4.7U_0805_25V6-K

2.2UH_FDSD0630-H- 2R2M-P3_8.3A_20%

1 2

12

PR97

4.7_1206_5%

@

@ PR97

12

FDMC7692S_MLP8-5

PC87

@

@ PC87

680P_0603_50V7K

5

PR91

255K_0402_1%

PR92

200K_0402_1%

SUSP#<25,27,32>

3 3

+5VALW

4 4

1 2

30K_0402_5%

PR95

100_0603_1%

1 2

PC85

4.7U_0603_6.3V6K

PR94

12

PC82

PC82 .1U_0402_16V7K

.1U_0402_16V7K

@

12

PR98

3.57K_0402_1%

1 2

12

PR99

8.25K_0402_1%

1 2

1

PU7

2

TON

EN_SKIP

3

OUT

4

VFB=0.75V

VCC

5

FB

6

PGOOD

AGND

7

PR93

0_0603_5%

1 2

15

14

TP

BST

13

DH

12

LX

11

ILIM

10

VDD

9

DL

PGND

G5603RU1U_TQFN14_3P5X3 P5

8

BST_1.05V ALW

DH_1.05VALW

LX_1.05VALW

1 2

PR96

15K_0402_1%

DL_1.05VALW

PC83

1 2

0.1U_0603_25V7K

+5VALW

12

PC86

4.7U_0603_6.3V6K

4

3

5

4

3

12

PC79

4.7U_0805_25V6-K

PL14

PC81

PC80

0.1U_0603_25V7K

2200P_0402_50V7K

+1.05VSP

1

<Vo=1.05V> VFB=0.75V

+

PC84

V=0.75*(1+3.57K/8.25K)=1.074V

2

330U_2.5V_M

Cout ESR=25m ohm Rdson(max)=17.9m ohm Rdson(typ)=14.5 mohm.(IRFH3707) Ipeak=5.5A, Imax=3.85A, Iocp > 6.6A

G5603 RT8209B TPS51117 RT8209M

OCP setting

6.524A 7.003A 7.768A 7.881A

G5603 TPS51117 RT8209MRT8209B

Temperature Compensated

Vtrip_min (SPEC)

Vtrip_max (SPEC)

-1180ppm/

℃℃℃℃

1600ppm/

℃℃℃℃

4500ppm/

℃℃℃℃

4800ppm/

30mV 50mV 30mV 50mV

200mV 200mV 200mV 200mV

A

℃℃℃℃

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/12 2012/08/12

Compal Secret Data

Deciphered Date

C

Title

Size D ocument Number Rev

Custom

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

1.1VALWP/1.0VSP

34 37Thursday, March 17, 2011

D

34 37Thursday, March 17, 2011

1.0

of

5

Dr-Bios.com

D D

4

3

2

1

+1.5V

1

PJ11

1

JUMP_43X118

@

2

C C

4.7U_0603_6.3V6K

PR101

300K_0402_5%

SUSP<27>

1 2

PC92

.1U_0402_16V7K

2

G

12

2

PC88

1 2

13

D

S

PQ26

SSM3K7002FU_SC70-3

PR100

1K_0402_1%

PR102

1K_0402_1%

12

PC90

For shortage changed

PU8

1

VIN

2

GND

3

VREF

4

VOUT

APL5336KAI-TRL_SOP8P8

12

PC91

PC91 10U_0603_6.3V6M

10U_0603_6.3V6M

.1U_0402_16V7K

VCNTL

+0.75VSP

8

NC

7

NC

6

5

NC

9

TP

+3VALW

12

PC89

PC89 1U_0402_6.3V6K

1U_0402_6.3V6K

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

5

4

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/12 2012/08/12

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

0.75VSP

35 37Thursday, March 17, 2011

1

1.0

D

Dr-Bios.com

CPU_B+

12

PC96

4.7U_0805_25V6-K

2.2UH_FDSD0630-H-2R2M-P3_8.3A_20%

12

@

PR107

4.7_1206_5%

12

@

PC104

PC104 680P_0603_50V7K

680P_0603_50V7K

2

1

2

1

PQ30

PQ30 FDMC7692S_MLP8-5

FDMC7692S_MLP8-5

PC97

0.1U_0603_25V7K

PC98

2200P_0402_50V7K

PL16

1 2

12

PC106

4.7U_0805_25V6-K

D

12

PC107

4.7U_0805_25V6-K

HCB2012KF-121T50_0805

1

+

PC99

2

@

68U_25V_M_R0.44

1

+

2

12

PC108

PC109

0.1U_0603_25V7K

4.7U_0805_25V6-K

PL15

12

+APU_CORE_NB

PC103

220U_D2_2VY_R15M

CPU_B+

12

PC110

2200P_0402_50V7K

12

@

PR122

4.7_1206_5%

12

@

PC112

@PC112

680P_0603_50V7K

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

B+

PL17

2.2UH_FDSD0630-H-2R2M-P3_8.3A_20%

1 2

PR123

7.5K_0402_1%

1 2

PC113

0.1U_0603_16V7K

PR127

1.69K_0402_1%

ISP0

Compal Electronics, Inc.

+APU_CORE_NB

PHASE_NB

LGATE_NB

PHASE_NB

UGATE_NB

36

35

34

33

32

31

30

PVCC

29

28

27

26

25

TP

49

C

AON7408L_DFN8-5

UGATE_NB

PHASE_NB

PR105

2.2_0603_1%

BOOT_NB

1 2

0.22U_0603_10V7K

LGATE_NB

APU_VDDNB_RUN_FB_ H <4>

APU_VDDNB_RUN_FB_ L <4>

BOOT_NB

BOOT0

UGATE0

PHASE0

LGATE0

C

0.22U_0603_10V7K

UGATE0

PHASE0

BOOT0

+5VALW

12

2010/08/12 2012/08/12

PQ27

4

1 2

PC102

4

PR118

2.2_0603_1%

1 2

0.22U_0603_10V7K

PC114

PC114 1U_0603_16V6K

1U_0603_16V6K

5

3

5

3

AON7408L_DFN8-5

PC111

LGATE0

Compal Secret Data

PC95

2

1

2

1

PQ28

PQ28 FDMC7692S_MLP8-5

FDMC7692S_MLP8-5

PQ29

4

1 2

4

Deciphered Date

12

4.7U_0805_25V6-K

5

3

5

3

A

1 1

+5VS +3VS

PR126

12

@

PR116

PR116 10K_0402_1%

10K_0402_1%

12

10_0402_1%

1 2

PC117

1000P_0402_50V7K

PR137

6.81K_0402_1%

+3VS

12

PR115

105K_0402_1%

2 2

FCH_PWRGD< 12>

H_PWRGD_L<11>

APU_SVD<4>

APU_SVC <4>

@

12

PC123

100P_0402_50V8J

3 3

DIFF_0

PC115

PR134

4700P_0402_25V7K

255_0402_1%

12

4 4

PR135

1K_0402_5%

12

VR_ON<25>

12

VGATE<12,25>

@

PC124

@PC124

100P_0402_50V8J

PR125

90.9K_0402_1%

PR136

54.9K_0402_1%

12

@

PR138

@ PR138

36.5K_0402_1%

1 2

PR119 100K_0402_5%@ PR119 100K_0402_5%@

1 2

PR120 100K_0402_5%PR120 100K_0402_5%

12

26.1K_0402_1%

12

+APU_CORE

APU_VDD0_RUN_FB_H<4>

APU_VDD0_RUN_FB_L<4>

VW0

12

PC116

100P_0402_50V8J

PC118

12

1200P_0402_50V7K

COMP0

PR113

PR113 0_0402_5%

0_0402_5%

PR121

0_0402_5%

PR128

10_0402_1%

12

+5VALW

CPU_B+

12

@

PR114

@PR114

105K_0402_1%

12

@

PR117

@PR117

105K_0402_1%

ISL6265_PWROK

12

PR124

0_0402_5%

PR130

0_0402_5%

PR131

12

0.1U_0603_25V7K

12

A

B

PR104

2_0603_5%

1 2

PC101

0.1U_0603_16V7K

1 2

PR109

2_0603_5%

PC105

PU9

1

OFS/VFIXEN

2

PGOOD

3

PWROK

4

SVD

5

SVC

6

ENABLE

7

RBIAS

8

OCSET

9

VDIFF0

10

FB0

11

COMP0

12

VW0

VSEN1

ISP0 ISN0

PR129

PR129 0_0402_5%

0_0402_5%

1 2

12

@

PC119

@PC119

100P_0402_50V8J

12

@

PC120

@PC120

100P_0402_50V8J

0_0402_5%

PR132

+3VS

B

12

48

47

VIN

VCC

ISP0

ISN0

13

14

VSEN0

RTN0

12

7.87K_0402_1%

7.87K_0402_1% PR133

PR133

46

FB_NB

VSEN0

15

PC93

33P_0402_50V8J

12

PC94

1000P_0402_50V7K

PC100

1000P_0402_50V7K

12

PR106

22K_0402_1%

12

PR110

0_0402_5%

@

PC121

@PC121

100P_0402_50V8J

@

PC122

@PC122

100P_0402_50V8J

PR111

PR111 0_0402_5%

0_0402_5%

43

42

41

RTN_NB

VSEN_NB

OCSET_NB

VSEN1

FB1

VDIFF1

18

20

19

VSEN1

6.49K_0402_1%

6.49K_0402_1% PR140

PR140

12

PC94

40

PGND_NB

COMP1

21

PR103

44.2K_0402_1%

45

44

FSET_NB

COMP_NB

ISL6265CHRTZ-T_TQFN48_6X6

RTN0

RTN1

16

17

12

PR108

10_0402_5%

1 2

12

PR139

10_0402_5%

1 2

12

PR112

12

17.8K_0402_1%

39

38

37

BOOT_NB

LGATE_NB

PHASE_NB

UGATE_NB

BOOT0

UGATE0

PHASE0

PGND0

LGATE0

LGATE1

PGND1

PHASE1

UGATE1

BOOT1

ISN1

ISP1

VW1

24

23

22

ISN0

ISP0

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

E

12

ISN0

CPU_CORE

E

36 37Thursday, March 17, 2011

+APU_CORE

of

1.0

5

Dr-Bios.com

4

3

2

1

Version change list (P.I.R. List) Page 1 of 1 for PWR

Reason for change Rev. PG# Modify List Date PhaseFixed IssueItem

Add PC248 for +3VALWP PC252 for +5VALWP PC253 for +VSBP

D D

1

Modify DCIN/VIN DECTOR power sequence

2

3

4

5

6

7

C C

8

9

10

11

12

13

Modify 3VALWP/5VALWP power sequence

Modify charger power sequence

Modify 3VALWP/5VALWP power sequence 32

Modify 1.8VSP/1.5VP power sequence

Modify 1.1VALWP/1.05VSP power sequence 34

Modify CPU_CORE power sequence

Modify 1.8VSP/1.5VP power sequence DVT

Modify 1.1VALWP/1.05VSP power sequence 34

Modify 1.8VSP/1.5VP power sequence PVT

14

15

B B

16

Modify charger power sequence

Modify charger power sequence 20110226 PVT

17

1

2

3

PC254 for +1.1VALWP PC255 for +1.05VSP PC256 for +0.75VSP

30

PC257 for +1.8VSP

delete PC234

31

delete PC34

32

Chang PD5 from SCS00000Z00 (RB7 51V-40_SOD323-2

31

to SCS00005I00 (SD103AWS SOD323 -2)

Chang PD3 from SCS00001I80 ( B340A SMA ) to SCS00000W00 (SX34_SMA2)

31

Chang PQ4&PQ5 fromSB00000KI00(SI7121DN-T1-GE3 1P POWERPAK1212-8) to SB00000KZ00(AON7403L_DFN8-5)

Chang PL6 &PL7 from SH00000F900(4.7UH_FDVE0630-H-4R7M= P3_5.5A_20%) to SH00000MB00(4.7UH_FDSD0630-H-4R7M-P3_5.5A_20%)

Chang PL10 from SH00000F800(2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%)

33 20110110

to SH00000M700(2.2UH_FDSD0630-H-2R2M-P3_8.3A_20%)

Chang PL12 &PL14 from SH00000F800(2.2UH_FDVE0630-H-2R2M= P3_8.3A_20%) to SH00000M700(2.2UH_FDSD0630-H-2R2M-P3_8.3A_20%)

Chang PL16 &PL17 from SH00000F800(2.2UH_FDVE0630-H-2R2M= P3_8.3A_20%) to SH00000M700(2.2UH_FDSD0630-H-2R2M-P3_8.3A_20%)

36

Chang PR112 from SD034237280 (23.7k_0402_1%) to SD034178280 (17.8k_0402_1%) Chang PR123 from SD000002680 (6.98k_0402_1%) to SD034750180 (7.5k_0402_1%)

36

Chang PR127 from SD034187180 (1.87k_0402_1%) to SD00000JB80 (1.69k_0402_1%)

add PC258 to +1.5V output capacitor (co-lay higt from 4.5

33

to 2.5) for thermal issue

add PC259 to +1.1VALWP output capacitor (co-lay higt from 4.5 to 2.5) for thermal issue

delete co-lay PC258 for +1.5V output capacitor

33

delete co-lay PC259 for +1.1VALW output capacitor

delete co-lay PJ32

31

modify PQ4 PQ5 footprint from AON7403L_DFN8-5 to SIS412DN-T1-GE3_POWERPAK8-5

change charger IC from G5209 to ISL6251

31

change output choke from 8.2u to 10u

Add PC258 for +1.5V jump by RF test

30

20101228 EVT

20101228

20101228 EVT

20110104 EVT

20110106 EVT

20110110 EVT

20110110

20110110 EVT

20110208

20110225

20110225Modify 1.1VALWP/1.05VSP power sequence 34

20110226 PVT

2010302 PVTModify DCIN/VIN DECTOR power sequence

EVTModify charger power sequence

EVT

DVT

PVT

18

19

20

21

22

A A

23

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/12 2012/08/12

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PIR (PWR)

1

1.0

37 37Thursday, March 17, 2011

1.0