Acer ASPIRE A315-31 Schematic

5

TPM@ : TPM GS@ : G-SENSOR CB@ : Cloud book SKU EJ@ : EJ sereies SKU KBL@ : keyboard backlight NVL@ : none LED panel boost VL@ : LED panel boost EC@ : EMMC TPC@ : Type C function w/o GS@: stuff with none GS sku SSD@ : SATA interface SSD PSD@ : PCIE interfance SSD ODD@ : ODD function

P19

P20

D

C

B

A

D

C

B

A

Dual Channel DDR3L 1867 MHz MAX

SATA0

SATA1

EMMC

USB2-2

USB2-3

USB2-4

USB2-5

USB2-6

USB2-7

DDR3L-2GB Memory down CHA

P10

DDR3L-2GB Memory down CHB

P11

Apollo Lake - 6W (BROXTON-P)

MCP 1296 pins

EDP

eDP

DDI0

DP

SMB

eDP Conn.

HDMI Conn.

P12

P13

USB3.0 Port

Type C port

SATA - HDD

SATA SSD M.2

32GB/64GB

USB2.0 Port 1

USB2.0 Port 2

Blue Tooth

Touch Screen

CCD(Camera)

P16

P12

P19

P17

P12

SATA

EMMC5.0

USB2.0

PCIE-0/1

USB3-0 + USB2-0

USB3.0/2.0 USB3-1 + USB3-2

USB2-1

PCI-E

PCIE-3

PCIE-2

M.2 NGFF WLAN+BT

P17

RJ45

P15

Cardreader

RTL8411B-CG

10/100/1G

P15

X'TAL 25MHz

X'TAL

32.768KHz

X'TAL 19.2MHz

I2C_0 SPI

SPI ROM 8M

P3

P20

Integrated PCH

RTC

P2~P8

IHDA

LPC

EC

IT8987

ODD bridge

ASM1153

P16

P6

Azalia

D-MIC AUDIO CODEC

P14

ALC255

P15

P22

BATTERY

P14

TPM(NPCT650)

P16

+1.8V_S5 / +1.24VSUS/+1.5V

P28

Quanta Computer Inc.

Date: Tuesday, March 21, 2017 Sheet

3

2b

1

P28

G-sensor

BQ24737RGRR

Batery Charger

RT8231BGQW

+1.35VSUS

G5719CTB1U G5719CTB1U G9661MF11U

P25

SY8286 & SY8288

+3VPCU/+5VPCU

M5671RE1U

+1.05V

P23

P24

ISL95859HRTZ-T Thermal Protection

+VCCGI / +VNN

HP JACK Speaker K/B Con. SPI ROM 1M Touch PAD Fan module

(PWM signal)

P14

P18

P20

P18

P26~27

P29

Discharger

PROJECT :

Size Document Number

Block Diagram

ZAJ

Rev

3A

4

3

2

1

01

ZAJ/Z8P/Z8PA SYSTEM BLOCK DIAGRAM

BOM

5 4 3 2 1

Section 2 of 12

DDR3L_ CH1_CB0_LPD DR3_NC DDR3L_ CH1_CB1_LPD DR3_NC DDR3L_ CH1_CB2_LPD DR3_NC DDR3L_ CH1_CB3_LPD DR3_NC DDR3L_ CH1_CB4_LPD DR3_NC DDR3L_ CH1_CB5_LPD DR3_NC DDR3L_ CH1_CB6_LPD DR3_NC DDR3L_ CH1_CB7_LPD DR3_NC

DDR3L_CH1_DQSP8_LPDDR 3_NC DDR3L_ CH1_DQSN8_LP DDR3_N C

Section 1 of 12

DDR3L_CH0_CB0_ LPDDR3 _NC DDR3L_CH0_CB1_ LPDDR3 _NC DDR3L_CH0_CB2_ LPDDR3 _NC DDR3L_CH0_CB3_ LPDDR3 _NC DDR3L_CH0_CB4_ LPDDR3 _NC DDR3L_CH0_CB5_ LPDDR3 _NC DDR3L_CH0_CB6_ LPDDR3 _NC DDR3L_CH0_CB7_ LPDDR3 _NC

DDR3L_ CH0_DQ SP8_LPDDR3_NC DDR3L_ CH0_DQSN 8_LPDDR 3_NC

DDR3L_C H 1_DQSP0_LPDDR3 _CH1_DQS PA0 DDR3L_ CH1_D QSN0_L PDDR3_ CH1_DQS NA0 DDR3L_C H 1_DQSP1_LPDDR3 _CH1_DQS PA1 DDR3L_ CH1_D QSN1_L PDDR3_ CH1_DQS NA1 DDR3L_C H 1_DQSP2_LPDDR3 _CH1_DQS PA2 DDR3L_ CH1_D QSN2_L PDDR3_ CH1_DQS NA2 DDR3L_C H 1_DQSP3_LPDDR3 _CH1_DQS PA3 DDR3L_ CH1_D QSN3_L PDDR3_ CH1_DQS NA3 DDR3L_C H 1_DQSP4_LPDDR3 _CH1_DQS PB0 DDR3L_ CH1_D QSN4_L PDDR3_ CH1_DQS NB0 DDR3L_C H 1_DQSP5_LPDDR3 _CH1_DQS PB1 DDR3L_ CH1_D QSN5_L PDDR3_ CH1_DQS NB1 DDR3L_C H 1_DQSP6_LPDDR3 _CH1_DQS PB2 DDR3L_ CH1_D QSN6_L PDDR3_ CH1_DQS NB2 DDR3L_C H 1_DQSP7_LPDDR3 _CH1_DQS PB3 DDR3L_ CH1_D QSN7_L PDDR3_ CH1_DQS NB3

MB_DRAMRST# [1 1]

DDR3L_ CH0_DQSP0_L PD DR3_CH0 _DQSPA0 DDR3L_ CH0_DQSN 0_LPDD R3_CH 0_DQSNA0 DDR3L_ CH0_DQSP1_L PD DR3_CH0 _DQSPA1 DDR3L_ CH0_DQSN 1_LPDD R3_CH 0_DQSNA1 DDR3L_ CH0_DQSP2_L PD DR3_CH0 _DQSPA2 DDR3L_ CH0_DQSN 2_LPDD R3_CH 0_DQSNA2 DDR3L_ CH0_DQSP3_L PD DR3_CH0 _DQSPA3 DDR3L_ CH0_DQSN 3_LPDD R3_CH 0_DQSNA3 DDR3L_ CH0_DQSP4_L PD DR3_CH0 _DQSPB0 DDR3L_ CH0_DQSN 4_LPDD R3_CH 0_DQSNB0 DDR3L_ CH0_DQSP5_ L PDDR3_CH 0_DQSPB1 DDR3L_ CH0_DQSN 5_LPDD R3_CH 0_DQSNB1 DDR3L_ CH0_DQSP6_L PD DR3_CH0 _DQSPB2 DDR3L_ CH0_DQSN 6_LPDD R3_CH 0_DQSNB2 DDR3L_ CH0_DQSP7_L PD DR3_CH0 _DQSPB3 DDR3L_ CH0_DQSN 7_LPDD R3_CH 0_DQSNB3

Rev

3A

Size Document Num ber

BXTP (MEMORY)

Date: Tuesday, March 21, 201 7 Sheet 2 of 34

5 4 3 2 1

Quanta Computer Inc.

PROJECT : ZAJ

C103 C101

0.1u/1 6V _4 0.1u/1 6V _4

MB_DRAMRST#

MA_ DRAMRST#

MA_DRAMRST# [ 10 ]

DRAMRST-MA DRAMRST-MB

+1.3 5VSUS +1.35VSU S

R106 R105

CPU

1K_1 %_ 4 1K_1 %_ 4

02

M_B _DQ0 [11] M_B _DQ1 [11] M_B _DQ2 [11] M_B _DQ3 [11] M_B _DQ4 [11] M_B _DQ5 [11] M_B _DQ6 [11] M_B _DQ7 [11] M_B _DQ8 [11]

M_B _DQ9 [11] M_B _DQ10 [11 ] M_B _DQ11 [11 ] M_B _DQ12 [11 ] M_B _DQ13 [11 ] M_B _DQ14 [11 ] M_B _DQ15 [11 ] M_B _DQ16 [11 ] M_B _DQ17 [11 ] M_B _DQ18 [11 ] M_B _DQ19 [11 ] M_B _DQ20 [11 ] M_B _DQ2 1 [11] M_B _DQ22 [11 ] M_B _DQ23 [11 ] M_B _DQ24 [11 ] M_B _DQ25 [11 ] M_B _DQ26 [11 ] M_B _DQ27 [11 ] M_B _DQ28 [11 ] M_B _DQ29 [11 ] M_B _DQ30 [11 ] M_B _DQ31 [11 ] M_B _DQ32 [11 ] M_B _DQ33 [11 ] M_B _DQ34 [11 ] M_B _DQ35 [11 ] M_B _DQ36 [11 ] M_B _DQ37 [11 ] M_B _DQ38 [11 ] M_B _DQ39 [11 ] M_B _DQ40 [11 ] M_B _DQ41 [11 ] M_B _DQ42 [11 ] M_B _DQ43 [11 ] M_B _DQ44 [11 ] M_B _DQ45 [11 ] M_B _DQ46 [11 ] M_B _DQ47 [11 ] M_B _DQ48 [11 ] M_B _DQ49 [11 ] M_B _DQ50 [11 ] M_B _DQ51 [11 ] M_B _DQ52 [11 ] M_B _DQ53 [11 ] M_B _DQ54 [11 ] M_B _DQ55 [11 ] M_B _DQ56 [11 ] M_B _DQ57 [11 ] M_B _DQ58 [11 ] M_B _DQ59 [11 ] M_B _DQ60 [11 ] M_B _DQ61 [11 ] M_B _DQ62 [11 ] M_B _DQ63 [11 ]

M_B_ DQS0 [11 ] M_B_ DQS #0 [11] M_B_ DQS1 [11 ] M_B_ DQS #1 [11] M_B_ DQS2 [11 ] M_B_ DQS #2 [11] M_B_ DQS3 [11 ] M_B_ DQS #3 [11] M_B_ DQS4 [11 ] M_B_ DQS #4 [11] M_B_ DQS5 [11 ] M_B_ DQS #5 [11] M_B_ DQS6 [11 ] M_B_ DQS #6 [11] M_B_ DQS7 [11 ] M_B_ DQS #7 [11]

M A A 0 BG50 M_A_A1 BG51 M_A_A2 BH51 M_A_A3 BD41 M_A_A4 BE41 M A A5 BJ 52 M A A 6 BG53 M_A_A7 BG55 M_A_A8 BH53

M_A_A9 BG52 M A A 10 BH49 M A A 11 BH55 M_A_A12 BG54 M_A_A13 BG46 M_A_A14 BG56 M_A_A15 BG57

BJ48

BG49

BH57

BH47 BG47 BG48

AR43

AT43

BB41

BA41

BH61

BH60

BH58

BJ58

AW43 AW41

AT34

AR35

MEM CH0 RCO MP

AV34

BD45

BE45

BB48

BD48

MA_ DRAMRST#

AR34

C102

0.1 u/1 6V_ 4

R102

10_5 %_ 4

AW48 AW47

BB43 AW45

AV48

AV47

BD43

BA45

BD47

BB47

AY62 M A DQ0 AY61 M_A_DQ1 BE62 M_A_DQ2 BG62 M_A_DQ3 BD63 M_A_DQ4 AW62

M A

DQ5

AW63

M A

DQ6

BD62 M_A_DQ7 AV59 M_A_DQ8 AU63 M_A_DQ9 AU62 M A DQ10 AV58 M A DQ11 AV57 M_A_DQ12 AT55 M_A_DQ13 AT54 M_A_DQ14 AY59 M_A_DQ15 AY57 M A DQ16 BB57 M_A_DQ17 BD59 M_A_DQ18 BF59 M_A_D Q19 AV54 M_A_DQ20 AY55 M A D Q21 AV52 M_A_DQ22 BD58 M_A_DQ23 BE56 M_A_DQ24 BD54 M_A_DQ25 BF58 M_A_D Q26 BE50 M A DQ27 BD50 M_A_DQ28 BB50 M_A_DQ29 BA50 M_A_DQ30 BB54 M_A_DQ31 AR39 M A DQ32 AV37 M_A_DQ33 AW37

M_A_DQ34

AR37 M_A_DQ35 AT37 M_A_DQ36 AT41 M A DQ37 AR41 M A DQ38 AW35

M_A_DQ39

BJ44 M_ A_DQ40 BG39 M_A_DQ41 BG40 M A DQ42 BJ40 M A DQ43 BG43 M_A_DQ44 BG44 M_A_DQ45 BH45 M_A_DQ46 BH41 M_A_DQ47 BA34 M A DQ48 BE34 M A DQ49 BD34 M_A_DQ50 BD37 M_A_DQ51 BB37 M_A_DQ52 BE39 M A DQ53 BD39 M A DQ54 BB34 M_A_DQ55 BJ38 M_ A_DQ56 BG34 M_A_DQ57 BG33 M_A_DQ58 BH33 M A DQ59 BG38 M A DQ60 BH37 M_A_DQ61 BG37 M_A_DQ62 BJ34 M_ A_DQ63

BB63

M A DQ S0 BC62 M _A_DQS #0 AT59

M_A _D QS1 AT58 M_A _DQS#1 BB59

M_A _DQ S2 BB58 M A DQS #2 BD52

M A DQS 3 BB52 M_A_DQ S#3 AV39

M_A _DQ S4 AW39 M_A _DQS#4 BJ42

M A DQS5 BG42 M A DQS#5 BB35

M_A _DQ S6 BD35 M _A_DQS #6 BG36

M _A_ DQS 7 BH35 M _A_DQS #7

U21B APL B GA 1296P

DDR3L_C H 1_MA0_LPDDR3_CH 1_CAB7 DDR3L _CH1_DQ0_L PDDR3 _CH1_DQ A0 DDR3L_C H 1_MA1_LPDDR3_CH 1_CAB9 DDR3L _CH1_DQ1_L PDDR3 _CH1_DQ A1 DDR3L_C H 1_MA2_LPDDR3_CH 1_CAB5 DDR3L _CH1_DQ2_L PDDR3 _CH1_DQA2 DDR3L_CH1_MA3_LPDDR3 _NC

DDR3L_ CH1_DQ3_L PDDR3_C H1_DQA3

DDR3L_CH1_MA4_LPDDR3 _NC

DDR3L_ CH1_DQ4_L PDDR3_C H1_DQA4 DDR3L_C H 1_MA5_LPDDR3_CH 1_CAA2 DDR3L _CH1_DQ5_L PDDR3 _CH1_DQ A5 DDR3L_C H 1_MA6_LPDDR3_CH 1_CAA0 DDR3L _CH1_DQ6_L PDDR3 _CH1_DQ A6 DDR3L_C H 1_MA7_LPDDR3_CH 1_CAA3 DDR3L _CH1_DQ7_L PDDR3 _CH1_DQ A7 DDR3L_C H 1_MA8_LPDDR3_CH 1_CAA1 DDR3L _CH1_DQ8_L PDDR3 _CH1_DQ A8 DDR3L_C H 1_MA9_LPDDR3_CH 1_CAA4 DDR3L _CH1_DQ9_L PDDR3 _CH1_DQ A9 DDR3L_ CH1_MA10_LPDD R3_CH1 _CAB6 DDR3L _CH1_DQ10_LPD D R3_CH 1_DQA10 DDR3L_ CH1_MA11_LPDD R3_CH1 _CAA6 DDR3L_CH1_D Q 11_LPDDR3_CH 1_DQA11 DDR3L_ CH1_MA12_LPDD R3_CH1 _CAA5 DDR3L _CH1_DQ12_LPD D R3_CH 1_DQA12 DDR3L_ CH1_MA13_LPDD R3_CH1 _CAB0 DDR3L _CH1_DQ13_LPD D R3_CH 1_DQA13 DDR3L_ CH1_MA14_LPDD R3_CH1 _CAA8 DDR3L _CH1_DQ14_LPD D R3_CH 1_DQA14 DDR3L_ CH1_MA15_LPDD R3_CH1 _CAA9 DDR3L _CH1_DQ15_LPD D R3_CH 1_DQA15

DDR3L_ CH1_DQ16_LPD D R3_CH1_DQA16 DDR3L_C H 1_BA0_LPDDR3_CH 1_CAB2 DDR3L_ CH1_DQ17_LPD D R3_CH1_DQA17 DDR3L_C H 1_BA1_LPDDR3_CH 1_CAB8 DDR3L_ CH1_DQ18_LPD D R3_CH1_DQA18 DDR3L_C H 1_BA2_LPDDR3_CH 1_CAA7 DDR3L_ CH1_DQ19_LPD D R3_CH1_DQA19

DDR3L_ CH1_DQ20_LPD D R3_CH1_DQA20 DDR3L_ CH1_C AS_N_LPDD R3_CH 1_CAB1 DDR3L_ CH1_DQ21_LPD D R3_CH1_DQA21 DDR3L_ CH1_R AS_N_LPDD R3_CH 1_CAB3 DDR3L_ CH1_DQ22_LPD D R3_CH1_DQA22 DDR3L_ CH1_W E_N_ LPDDR3 _CH1_C AB4 DDR3L_ CH1_DQ23_LPD D R3_CH1_DQA23

DDR3L_ CH1_DQ24_LPD D R3_CH1_DQA24 DDR3L_ CH1_CS0_N_LPDD R3_CH1_ CS0A_N DDR3L_ CH1_DQ25_LPD D R3_CH1_DQA25 DDR3L_NC_LPDDR3_CH1 _CS1A_ N

DDR3L_ CH1_DQ26_LPD D R3_CH1_DQA26 DDR3L_NC_LPDDR3_CH1 _CS0B_ N

DDR3L_ CH1_DQ27_LPD D R3_CH1_DQA27 DDR3L_ CH1_CS1_N_LPDD R3_CH1_ CS1B_N DDR3L_ CH1_DQ28_LPD D R3_CH1_DQA28

DDR3L_ CH1_DQ29_LPD D R3_CH1_DQA29 DDR3L_ CH1_CKE0_LPDD R3_CH1_C KE0A DDR3L_ CH1_DQ30_LPD D R3_CH1_DQA30 DDR3L_ CH1_CKE1_LPDD R3_CH1_C KE1A DDR3L_ CH1_DQ31_LPD D R3_CH1_DQA31 DDR3L_NC_LPDDR3_CH1 _CKE0B

DDR3L_ CH1_DQ32_L PDDR3_ CH1_DQB 0

DDR3L_NC_LPDDR3_CH1 _CKE1B

DDR3L_ CH1_DQ33_L PDDR3_ CH1_DQB 1

DDR3L_CH1 _DQ34_LPDDR 3_CH1_D QB2 DDR3L_ CH1_ ODT0_L PDDR3_C H1_ODT A DDR3L_ CH1_DQ35_L PDDR3_ CH1_DQB 3 DDR3L_ CH1_ ODT1_L PDDR3_C H1_ODT B DDR3L_ CH1_DQ36_L PDDR3_ CH1_DQB 4

DDR3L_ CH1_DQ37_L PDDR3_ CH1_DQB 5 MEM_CH1_VRE FDQ

DDR3L _CH1_DQ38_LPD DR3_CH 1_DQB6 MEM_CH1_VRE FCA

DDR3L_ CH1_DQ39_L PDDR3_ CH1_DQB 7

DDR3L_ CH1_DQ40_L PDDR3_ CH1_DQB 8

DDR3L_ CH1_DQ41_L PDDR3_ CH1_DQB 9 MEM_CH1_RCOM P

DDR3L _CH1_DQ42_LPD D R3_CH 1_DQB10

DDR3L_ CH1_DQ43_LPD D R3_CH1_DQB11 DDR3L_ CH1_C LKP0_LPDDR3 _CH1_C LKP_B DDR3L_ CH1_DQ44_LPD D R3_CH1_DQB12 DDR3L_ CH1_CLKN0_LPDD R3_CH1_ CLKN_B DDR3L_ CH1_DQ45_LPD D R3_CH1_DQB13

DDR3L_ CH1_DQ46_LPD D R3_CH1_DQB14 DDR3L_ CH1_C LKP1_LPDDR3 _CH1_C LKP_A DDR3L_ CH1_DQ47_LPD D R3_CH1_DQB15 DDR3L_ CH1_CLKN1_LPDD R3_CH1_ CLKN_A DDR3L_ CH1_DQ48_LPD D R3_CH1_DQB16

DDR3L_ CH1_DQ49_LPD D R3_CH1_DQB17 DDR3L_ CH1_R ESET_N_LPDD R3_NC DDR3L _CH1_DQ50_LPD D R3_CH 1_DQB18

DDR3L_ CH1_DQ51_LPD D R3_CH1_DQB19

DDR3L_ CH1_DQ52_LPD D R3_CH1_DQB20

DDR3L_ CH1_DQ53_LPD D R3_CH1_DQB21

DDR3L_ CH1_DQ54_LPD D R3_CH1_DQB22

DDR3L_ CH1_DQ55_LPD D R3_CH1_DQB23

DDR3L_ CH1_DQ56_LPD D R3_CH1_DQB24

DDR3L_ CH1_DQ57_LPD D R3_CH1_DQB2 5

DDR3L_ CH1_DQ58_LPD D R3_CH1_DQB26

DDR3L_ CH1_DQ59_LPD D R3_CH1_DQB27

DDR3L_ CH1_DQ60_LPD D R3_CH1_DQB28

DDR3L_ CH1_DQ61_LPD D R3_CH1_DQB29

DDR3L_ CH1_DQ62_LPD D R3_CH1_DQB30

DDR3L_ CH1_DQ63_LPD D R3_CH1_DQB31

[10 ] M_ A_A 0 [10 ] M_ A_A 1 [10 ] M_ A_A 2 [10 ] M_ A_A 3 [10 ] M_ A_A 4 [10 ] M_ A_A 5 [10 ] M_ A_A 6 [10 ] M_ A_A 7 [10 ] M_ A_A 8 [10 ] M_ A_A 9 [10 ] M_A_A 10 [10 ] M_A_A 11 [10 ] M_A_A 12 [10 ] M_A_A 13 [10 ] M_A_A 14 [10 ] M_A_A 15

[10] M _A_ BS#0 [10] M _A_ BS#1 [10] M _A_ BS#2

[10] M_ A_C AS# [10] M_ A_R AS#

[10] M_A_W E#

[10] M _A_ CS#0

[10] M_ A_C KE0

R89 105 1% 4

[10 ] M_A_ CLK 0 [10] M _A_ CLK0 #

colsed to CPU pin within 100 mils

M_A_ DQ0 [10] M_A_ DQ1 [10] M_A_ DQ2 [10] M_A_ DQ3 [10] M_A_ DQ4 [10] M_A_ DQ5 [10] M_A_ DQ6 [10] M_A_ DQ7 [10] M_A_ DQ8 [10]

M_A_ DQ9 [10] M_A _DQ1 0 [10] M_A _DQ1 1 [10] M_A _DQ1 2 [10] M_A _DQ1 3 [10] M_A _DQ1 4 [10] M_A _DQ1 5 [10] M_A _DQ1 6 [10] M_A _DQ1 7 [10] M_A _DQ1 8 [10] M_A _DQ1 9 [10] M_A _DQ2 0 [10] M_A _DQ2 1 [10] M_A _DQ2 2 [10] M_A _DQ2 3 [10] M_A _DQ2 4 [10] M_A _DQ2 5 [10] M_A _DQ2 6 [10] M_A _DQ2 7 [10] M_A _DQ2 8 [10] M_A _DQ2 9 [10] M_A _DQ3 0 [10] M_A _DQ3 1 [10] M_A _DQ3 2 [10] M_A _DQ3 3 [10] M_A _DQ3 4 [10] M_A _DQ3 5 [10] M_A _DQ3 6 [10] M_A _DQ3 7 [10] M_A _DQ3 8 [10] M_A _DQ3 9 [10] M_A _DQ4 0 [10] M_A _DQ4 1 [10] M_A _DQ4 2 [10] M_A _DQ4 3 [10] M_A _DQ4 4 [10] M_A _DQ4 5 [10] M_A _DQ4 6 [10] M_A _DQ4 7 [10] M_A _DQ4 8 [10] M_A _DQ4 9 [10] M_A _DQ5 0 [10] M_A _DQ5 1 [10] M_A _DQ5 2 [10] M_A _DQ5 3 [10] M_A _DQ5 4 [10] M_A _DQ5 5 [10] M_A _DQ5 6 [10] M_A _DQ5 7 [10] M_A _DQ5 8 [10] M_A _DQ5 9 [10] M_A _DQ6 0 [10] M_A _DQ6 1 [10] M_A _DQ6 2 [10] M_A _DQ6 3 [10]

M_A _DQS0 [10] M_A _DQS #0 [10] M_A _DQS1 [10] M_A _DQS #1 [10] M_A _DQS2 [10] M_A _DQS #2 [10] M_A _DQS3 [10] M_A _DQS #3 [10] M_A _DQS4 [10] M_A _DQS #4 [10] M_A _DQS5 [10] M_A _DQS #5 [10] M_A _DQS6 [10] M_A _DQS #6 [10] M_A _DQS7 [10] M_A _DQS #7 [10]

DDR3L_ CH0_MA0_LPDD R3_CH0_ CAB7 DDR3L_ CH0_DQ0_LPD DR3_CH 0_DQA0 DDR3L_ CH0_MA1_LPDD R3_CH0_ CAB9 DDR3L_ CH0_DQ1_LPD DR3_CH 0_DQA1 DDR3L_ CH0_MA2_LPDD R3_CH0_ CAB5 DDR3L_ CH0_DQ2_LPD DR3_CH 0_DQA2 DDR3L_ CH0_MA3_LPDD R3_NC

DDR3L_ CH0_DQ3_LPD DR3_CH 0_DQA3

DDR3L_ CH0_MA4_LPDD R3_NC

DDR3L_ CH0_DQ4_LPD DR3_CH 0_DQA4 DDR3L_ CH0_MA5_LPDD R3_CH0_ CAA2 DDR3L_ CH0_DQ5_LPD DR3_CH 0_DQA5 DDR3L_ CH0_MA6_LPDD R3_CH0_ CAA0 DDR3L_ CH0_DQ6_LPD DR3_CH 0_DQA6 DDR3L_ CH0_MA7_LPDD R3_CH0_ CAA3 DDR3L_ CH0_DQ7_LPD DR3_CH 0_DQA7 DDR3L_ CH0_MA8_LPDD R3_CH0_ CAA1 DDR3L_ CH0_DQ8_LPD DR3_CH 0_DQA8 DDR3L_ CH0_MA9_LPDD R3_CH0_ CAA4 DDR3L_ CH0_DQ9_LPD DR3_CH 0_DQA9 DDR3L_ CH0_MA10_LPDDR 3_CH0_CAB6 DDR3L_ CH0_D Q10_LPDD R3_CH0 _DQA10 DDR3L_ CH0_MA11_LPDDR 3_CH0_CAA6 DDR3L_ CH0_D Q11_LPDD R3_CH0 _DQA11 DDR3L_ CH0_MA12_LPDDR 3_CH0_CAA5 DDR3L_ CH0_D Q12_LPDD R3_CH0 _DQA12 DDR3L_ CH0_MA13_LPDDR 3_CH0_CAB0 DDR3L_ CH0_D Q13_LPDD R3_CH0 _DQA13 DDR3L_ CH0_MA14_LPDDR 3_CH0_CAA8 DDR3L_ CH0_D Q14_LPDD R3_CH0 _DQA14 DDR3L_ CH0_MA15_LPDDR 3_CH0_CAA9 DDR3L_ CH0_D Q15_LPDD R3_CH0 _DQA15

DDR3L_ CH0_D Q16_LPDDR 3_CH0 _DQA16 DDR3L_ CH0_BA0_LPDD R3_CH0_C AB2 DDR3L_ CH0_D Q17_LPDD R3_CH0 _DQA17 DDR3L_ CH0_BA1_LPDD R3_CH0_C AB8 DDR3L_ CH0_D Q18_LPDD R3_CH0_DQA18 DDR3L_ CH0_BA2_LPDD R3_CH0_C AA7 DDR3L_ CH0_D Q19_LPDD R3_CH0 _DQA19

DDR3L_ CH0_D Q20_LPDDR 3_CH0 _DQA20 DDR3L_ CH0_CA S_N_LPDDR 3_CH0_ CAB1 DDR3L_ CH0_D Q21_LPDD R3_CH0 _DQA21 DDR3L_ CH0_RA S_N_LPDDR 3_CH0_ CAB3 DDR3L_ CH0_D Q22_LPDD R3_CH0 _DQA22 DDR3L_ CH0_W E_N_L PDDR3_ CH0_CAB 4 DDR3L_ CH0_D Q23_LPDD R3_CH0 _DQA23

DDR3L_ CH0_D Q24_LPDDR 3_CH0 _DQA24 DDR3L_ CH0_CS 0_N_LPD DR3_CH0 _CS0A_N DDR3L_ CH0_D Q25_LPDD R3_CH0 _DQA25 DDR3L_NC_LPDD R3_CH0_C S1A_N

DDR3L_ CH0_D Q26_LPDD R3_CH0 _DQA26 DDR3L_NC_LPDD R3_CH0_C S0B_N

DDR3L_ CH0_D Q27_LPDD R3_CH0 _DQA27 DDR3L_CH0_CS1_ N_LPDDR 3_CH0_C S1B_N DDR3L_ CH0_D Q28_LPDD R3_CH0 _DQA28

DDR3L_ CH0_D Q29_LPDDR 3_CH0 _DQA29 DDR3L_ CH0_CKE0_L PDDR3_C H0_CKE0A DDR3L_ CH0_D Q30_LPDD R3_CH0 _DQA30 DDR3L_ CH0_CKE1_L PDDR3_C H0_CKE1A DDR3L_ CH0_D Q31_LPDD R3_CH0 _DQA31 DDR3L_NC_LPDD R3_CH0_C KE0B

DDR3L_ CH0_DQ 32_LPDDR 3_CH0_DQB0

DDR3L_NC_LPDD R3_CH0_C KE1B

DDR3L_ CH0_DQ 33_LPDDR 3_CH0_DQB1

DDR3L_ CH0_DQ 34_LPDDR 3_CH0_DQB2 DDR3L_ CH0_ ODT0_L PDDR3 _CH0_OD TA DDR3L_ CH0_DQ 35_LPDDR 3_CH0_DQB3 DDR3L_ CH0_ ODT1_L PDDR3 _CH0_OD TB DDR3L_ CH0_DQ 36_LPDDR 3_CH0_DQB4

DDR3L_ CH0_DQ 37_LPDDR 3_CH0_DQB5 MEM_CH0_ VREFDQ

DDR3L _CH0_DQ 38_LPDD R3_CH0_ DQB6 MEM_CH0_ VREFCA

DDR3L_ CH0_DQ 39_LPDDR 3_CH0_DQB7

DDR3L_ CH0_DQ 40_LPDDR 3_CH0_DQB8

DDR3L_ CH0_DQ 41_LPDDR 3_CH0_DQB9 MEM_CH0_R COMP

DDR3L_ CH0_D Q42_LPDD R3_CH0 _DQB10

DDR3L_ CH0_D Q43_LPDDR 3_CH0 _DQB11 DDR3L_ CH0_CL KP0_LPDD R3_CH 0_CLKP_B DDR3L_ CH0_D Q44_LPDD R3_CH0 _DQB12 DDR3L_ CH0_CLKN 0_LPDDR3_CH 0_CLKN_ B DDR3L_ CH0_D Q45_LPDD R3_CH0 _DQB13

DDR3L_ CH0_D Q46_LPDDR 3_CH0 _DQB14 DDR3L_ CH0_CL KP1_LPDDR 3_CH0_ CLKP_A DDR3L_ CH0_D Q47_LPDD R3_CH0 _DQB15 DDR3L_ CH0_CLKN 1_LPDDR3_CH 0_CLKN_ A DDR3L_ CH0_D Q48_LPDD R3_CH0 _DQB16

DDR3L_ CH0_D Q49_LPDDR 3_CH0 _DQB17 DDR3L_ CH0_R ESET_N _LPDDR3 _NC DDR3L_ CH0_D Q50_LPDD R3_CH0 _DQB18

DDR3L_ CH0_D Q51_LPDDR 3_CH0 _DQB19

DDR3L_ CH0_D Q52_LPDDR 3_CH0 _DQB20

DDR3L_ CH0_D Q53_LPDDR 3_CH0 _DQB21

DDR3L_ CH0_D Q54_LPDDR 3_CH0 _DQB22

DDR3L_ CH0_DQ55_LPD DR3_CH 0_DQB23

DDR3L_ CH0_D Q56_LPDDR 3_CH0 _DQB24

DDR3L_ CH0_D Q57_LPDDR 3_CH0 _DQB25

DDR3L_ CH0_D Q58_LPDDR 3_CH0 _DQB26

DDR3L_ CH0_D Q59_LPDDR 3_CH0 _DQB27

DDR3L_ CH0_D Q60_LPDDR 3_CH0 _DQB28

DDR3L_ CH0_D Q61_LPDDR 3_CH0 _DQB29

DDR3L_ CH0_D Q62_LPDDR 3_CH0 _DQB30

DDR3L_ CH0_DQ63_LPD DR3_CH 0_DQB31

M_B_ A0 BG9 M_B_A1 BG10 M_B _A 2

BH9

M_B_A3 BD1 6 M B A4 BB16 M B A 5 BG11 M_B_A6 BJ12 M_B_A7 BG14 M_B_A8 BG12 M B A 9 BH11

M B A10 BG7 M_B_A11 BH13 M_B_A12 BG13 M_B_ A13

BH3

M_B_A14 BG15 M B A 15 BG16

BH6

BG8

BH15

BH4

BJ6

BH7

BD17 BB17 AV17

AW17

BG18 BG17 BH17

BJ16

AW16

AV16

AT30 AR29

MEM CH1 RCO MP

AV30

BD19 BE19

BB21 BD21

MB_ DRAMRST#

AR30

C97

0.1u/1 6V _4

R101

10_5% _4

AR21

AT21 AW23 AW21

BA19 AW19

BA23

BB23

BD23

BE23

BJ26 M_B_DQ0 BG30 M_B_DQ1 BH31 M_B_DQ2 BG31 M_B_DQ3 BH27 M B DQ4 BG27 M B DQ5 BG26 M_B_DQ6 BJ30 M_B_DQ7 BA30 M_B_DQ8 BB30 M B DQ9 BE30 M B DQ10 BD30 M_B_DQ11 BE25 M_B_DQ12 BB27 M_B_DQ13 BD25 M_B_DQ14 BD27 M B DQ15 BG24 M_B_DQ16 BJ20 M_B_DQ17 BH23 M_B_DQ18 BJ24 M_B_DQ19 BG20 M B DQ20 BG21 M_B_DQ21 BH19 M_B_DQ22 BG25 M_B_DQ23 AT27 M_B_DQ24 AW29

M_B_DQ25

AR27 M B DQ26 AT23 M_B_DQ27 AV27 M_B_DQ28 AR25 M_B_DQ29 AR23 M_B_DQ30 AW27

M B

DQ31

BF6

M_B _D Q32 BD10 M_B_DQ33 BE14 M_B_DQ34 BB10 M_B_DQ35 BA14 M B DQ36 BB14 M B DQ37 BD14 M_B_DQ38 BE8

M_B _DQ3 9 AV12 M_B_DQ40 BD6

M B DQ41 BD5

M B DQ42 BB7

M_B _DQ4 3 AV10 M_B_DQ44 AY9

M_B _DQ4 5 AY7

M_B _DQ4 6 BF5

M B D Q47 AU2

M B DQ48 AT10 M_B_DQ49 AT9

M_B _DQ5 0 AU1

M _B_ DQ51 AY5

M B DQ52 AV5

M B DQ53 AV6

M_B _DQ5 4 AV7

M_B _DQ5 5 AY2

M_B _DQ5 6 BD2

M _B_ DQ57 BD1

M B DQ58 BE2

M B DQ59 AW1 M_B_ DQ60 AW2 M_B_ DQ61 AY3

M_B _DQ6 2 BG2 M B DQ63

BG28

M_B_ DQS 0 BH29 M_B_DQS#0 BD29

M_B _DQ S1 BB29 M_B_ DQS#1 BJ22

M B DQS 2 BG22 M B DQS#2 AV25

M_ B_D QS3 AW25 M_B_ DQS#3 BB12

M_ B_D QS4 BD12 M B DQS# 4 BB5

M B DQ S5

BB6

M_B_ DQS #5

AT5

M_B _D QS6

AT6

M_B_ DQS #6

BC2

M_B_ DQS 7

BB1

M B DQS #7

D

C

B

A

D

C

B

A

[11] M _B_ A0 [11] M _B_ A1 [11] M _B_ A2 [11] M _B_ A3 [11] M _B_ A4 [11] M _B_ A5 [11] M _B_ A6 [11] M _B_ A7 [11] M _B_ A8 [11] M _B_ A9 [11] M_B _A1 0 [11] M_B _A1 1 [11] M_B _A1 2 [11] M_B _A1 3 [11] M_B _A1 4 [11] M_B _A1 5

[11] M _B_ BS#0 [11] M _B_ BS#1 [11] M _B_ BS#2

[11] M _B_ CAS# [11] M _B_ RAS#

[11] M_ B_WE #

[11] M_ B_CS #0

[11] M _B_ CKE0

R91 105 1% 4

[11 ] M _B_ CLK 0

[11] M_B_ CLK 0#

colsed to CPU pin within 100 mils

_ _

_ _ _ _

_ _

_ _ _ _ _ _ _ _

_ _ _ _ _ _

_ _ _ _

_ _ _ _ _ _

_ _

_ _ _ _ _ _

_ _

_ _ _ _

_ _

_ _ _ _

_ _

APL ULT (DDR3L)

U21A APL BGA 1296P

J1 J2 K9

K10

K3 K2 F2

G2

AC16

WND GGD

5

4

3

2

1

8M 8M

Quanta Computer Inc.

PROJECT :ZAJ

Vender

Size

Quanta P/N Vender P/N

SPI ROM

1.8V

SP@ socket P/N: DFHS08FS023 only for A-TEST

Rev

3A

Size Document Number

BXTP (PCIE/USB/SATA/SPI)

Date: Tuesday, March 21, 2017

Sheet

3 of 34

AKE5EG-0Q01 GD25LB64CSIGR

03

D

C

B

A

D

C

B

A

[19] USB3_0_TXP

[19] USB3_0_TXN [19] USB3_0_RXP [19] USB3_0_RXN

[20] USB3_1_TXP

[20] USB3_1_TXN [20] USB3_1_RXP [20] USB3_1_RXN

USB_SSIC_RCOMP

N62 P61

PCIE_LAN_WAKE#

PCIE_LAN_WAKE# [15]

PCIE_TX3+_WLAN [17]

PCIE_TX3-_WLAN

[17]

PCIE_RX3+_WLAN [17]

PCIE_RX3-_WLAN

[17]

USB3_2_TXP [20] USB3_2_TXN [20] USB3_2_RXP [20] USB3_2_RXN [20]

PCIE_TX0+_SSD [16]

PCIE_TX0-_SSD [16]

PCIE_RX0+_SSD [16]

PCIE_RX0-_SSD [16]

PCIE_TX1+_SSD [16]

PCIE_TX1-_SSD [16]

PCIE_RX1+_SSD [16]

PCIE_RX1-_SSD [16]

PCIE_TX2+_LAN [15]

PCIE_TX2-_LAN [15]

PCIE_RX2+_LAN

[15]

PCIE_RX2-_LAN

[15]

CLK_PCIE_SSD_REQ#

[16]

CLK_PCIE_LAN_REQ#

[15]

PCIE_CLKREQ_WLAN#

[17]

+1.8V_S5

MB USB3.0

MB TYPE C

USB2COMP：4-8mils trace width with <1000 mils

P62 R62

F6

PCIE_RCOMPP

F5

PCIE RCOMPN

R37 402_1%_4

0.1u/16V 4 C332

0.1u/16V 4 C333

0.1u/16V_4 C335

0.1u/16V 4 C334

10K 5% 4 10K 5% 4

10K 5% 4 *10K_5%_4

USB3_P0_TXP

PCIE_WAKE3_N

USB3_P0_TXN

PCIE_WAKE2_N

USB3_P0_RXP

PCIE_WAKE1_N

USB3_P0_RXN

PCIE_WAKE0_N USB3_P1_TXP USB3_P1_TXN PCIE2_USB3_SATA3_RCOMP_P USB3_P1_RXP USB3_P1_RXN

PCIE2_USB3_SATA3_RCOMP_N

USB2_VBUS_SNS

PCIE_P3_USB3_P4_TXP

USB_SSIC_RCOMP PCIE_P3_USB3_P4_TXN

PCIE_P3_USB3_P4_RXP

USB2_RCOMP

PCIE_P3_USB3_P4_RXN

P3 P2 P12 P10

N2 M2 H5 H6

L2 L1 K7 M7

V3 V2 P7 P6

R1 R2 T10 T12

T2 T3 M5 M6

AK62 AH62 AH61 AJ62

C11 B11 C10 A10 A7 B8 B7 B5

C1 F1 B4 A4

A18 C19

PCIE_TX3+

PCIE_TX3-

PCIE_TX2+

PCIE TX2-

R398 R391

R397 R392

R64 137 1% 4

AB15

WIFI

MB TYPE C

M.2 SSD

LAN

R75 R382

*10K 5% 4 10K 5% 4

10K 5% 4

113 1% 4

USBCOMP Y15

*0 5% 4

AC15 AH13

AH12 AG16 AG15

B55 C55

V12 V10 V16 V15

Y13

V13

V9 V7

Y9

Y10 AB6 AB7

AC12 AC10

V5 V6

W 1 W 2

T5 T6 Y3 Y2 T9 T7

USB2_OTG_ID USB_SSIC_0_TX_P

USB_SSIC_0_TX_N USB_SSIC_0_RX_P USB_SSIC_0_RX_N

USB2_OC0_N USB2_OC1_N

USB2_DP0 USB2_DN0 USB2_DP1 USB2_DN1 USB2_DP2 USB2_DN2 USB2_DP3 USB2_DN3

USB2_DP4 USB2_DN4 USB2_DP5 USB2_DN5 USB2_DP6 USB2_DN6 USB2_DP7 USB2_DN7

PCIE_P4_USB3_P3_TXP PCIE_P4_USB3_P3_TXN PCIE_P4_USB3_P3_RXP PCIE_P4_USB3_P3_RXN

PCIE_P5_USB3_P2_TXP PCIE_P5_USB3_P2_TXN PCIE_P5_USB3_P2_RXP PCIE_P5_USB3_P2_RXN

PCIE_P0_TXP PCIE_P0_TXN PCIE_P0_RXP

PCIE_P0_RXN

PCIE_P1_TXP PCIE_P1_TXN PCIE_P1_RXP

PCIE_P1_RXN

PCIE_P2_TXP PCIE_P2_TXN PCIE_P2_RXP

PCIE_P2_RXN

PCIE_CLKREQ0_N PCIE_CLKREQ1_N PCIE_CLKREQ2_N PCIE_CLKREQ3_N

+1.8V_S5

[20] USB_OC0# [19] USB_OC1#

R377 R328

R327

[19]

USBP0+

MB USB3.0 CONN

[19]

USBP0-

[20]

USBP1+

MB TYPE C

[20]

USBP1-

[19]

USBP2+

USB 2.0

[19]

USBP2-

[19]

USBP3+

USB 2.0

[19]

USBP3-

BT

[17]

USBP4-

Touch Screen

[12]

USBP5-

CCD

ODD bridge

[16]

USBP7-

AKE5EZN0N01

W25Q64FWSSIQ

SATA_P1_USB3_P5_TXP

PCIE_CLKOUT0P

SATA_P1_USB3_P5_TXN

PCIE_CLKOUT0N

SATA_P1_USB3_P5_RXP

PCIE_CLKOUT1P

SATA_P1_USB3_P5_RXN

PCIE_CLKOUT1N

SATA_P0_TXP

PCIE_CLKOUT2P

SATA_P0_TXN

PCIE_CLKOUT2N

SATA_P0_RXP

PCIE_CLKOUT3P

SATA_P0_RXN

PCIE_CLKOUT3N

M.2 SATA

HDD

PCH SPI SI PCH SPI SO PCH SPI IO3 PCH SPI IO2

PCH_SPI_CS0# PCH_SPI_CLK

R302 33 5% 4

A58 B58 B61 B60 C57 B57 C56

RSVD_C1

RSVD_F1 RSVD_B4 RSVD_A4

RSVD_A18 RSVD_C19

VSTBY_FSPI

R352 R326

3.3K_5%_4 *3.3K_5%_4 U1

C5

R354

0.1u/16V_4

3.3K_5%_4

PCH_SPI_IO3

PCH SPI CS0# PCH_SPI_CLK PCH_SPI_SI PCH_SPI_SO

PCH_SPI_IO2

1 6 5 2

3

8

7

4

CE# VCC SCLK SI SO

IO3

IO2 VSS

GD25LB64CSIGR

_ _ _ _

_ _ _

_ _

_ _ _ _

_ _

USB_OTG_ID

[17]

USBP4+

[12]

USBP5+

[12]

USBP6+

[12]

USBP6-

[16]

USBP7+

[16]

SATA_TXP1

[16] SATA_TXN1

[16]

SATA_RXP1

[16]

SATA_RXN1

[16]

SATA_TXP0

[16] SATA_TXN0

[16]

SATA_RXP0

[16]

SATA_RXN0

CLK_PCIE_SSDP

[16] CLK_PCIE_SSDN [16] CLK_PCIE_LANP

[15] CLK_PCIE_LANN [15] CLK_PCIE_WLANP

[17]

CLK_PCIE_WLANN

[17]

M.2 SSD LAN

WIFI

FST_SPI_MOSI_IO0 FST_SPI_MISO_IO1 FST_SPI_IO3 FST_SPI_IO2 FST_SPI_CS1_N FST_SPI_CS0_N FST_SPI_CLK

Section 3 of 12

VSTBY_FSPI

CLK_PCIE_LAN_REQ#

PCIE_CLKREQ_WLAN#

R485

*0 5% 4

R486

*0 5% 4

SPI_CLK_A

5

4

3

2

1

Apollo lake (SATA , ODD, CLK ,USB,PCIE)

+1.8V_S5

R366

U21C

APL BGA 1296P

10K_5%_4

Q27A Q27B

+3V

R298 R337

10K_5%_4 10K_5%_4

5

2

SSM6N43FU

Q28A Q28B

Rev

3A

Size Document Number

BXTP (HDMI/eDP)

Date: Tuesday, March 21, 2017 Sheet 4 of 34

5 4 3 2 1

C310 15p/50V 4

XTAL192_IN

19.2MHZ/20ppm 200K_1%_4

5 4 3 2 1

Apollolake (DISPLAY,eDP)

04

D

C

B

U21D

DDI1_TXP_0 DDI1_TXN_0 DDI1_TXP_1 DDI1_TXN_1 DDI1_TXP_2 DDI1_TXN_2 DDI1_TXP_3 DDI1_TXN_3

DDI1_AUXP DDI1_AUXN

APL BGA 1296P

MDSI_RCOMP

MDSI_C_DP_0 MDSI_C_DN_ 0 MDSI_C_DP_1 MDSI_C_DN_ 1 MDSI_C_DP_2 MDSI_C_DN_ 2 MDSI_C_DP_3 MDSI_C_DN_ 3

MDSI_C_C LKP

+3V

R297

10K_5%_4

5

2

AF2 AF3 AD3 AD2 AC1 AC2 AB3 AB2

AK16 AK15

AK3

AK2 AM3 AM2

AH3

AH2

AL2

AL1

AM16 AM15

B51

C51

DDI0_RCOMP_P

DDI0 RCOMP N AG2

D

C

B

R336 10K_5%_4

SSM6N43FU

EDP_VDD_EN [12]

PCH_BKLTEN

PCH_BRIGHT [12]

+3V

R299

10K_5%_4

5

2

[13] INT_HDMITX2P [13] INT_HDMITX2N [13] INT_HDMITX1P [13] INT_HDMITX1N [13] INT_HDMITX0P [13] INT_HDMITX0N

[13] INT_HDMICLK+

[13] INT_HDMICLK-

PCH_VDDEN

150 1% 4

PCH_BKLTCTL

PCH_VDDEN PCH_BKLTEN PCH_BKLTCTL

XTAL192 OUT

C52 B53 C53

C47 B47 C46

AG62

AF61 AG63 AE60

AF62

P29 R27

R332 10K_5%_4

PCH_BLON [12]

SSM6N43FU

F27

MCSI_DPHY1 .2_RCOM P

R40

M23 P23 L23 J23 J21 H21 M25 L25 F25 E25 H25 J25

H27

MCSI

DPHY1.1 RCOM P

R44

P17 M17 P21 R21 L17 J17 F17 E17

M19 L19 H19 F19

L37 P34 J34 H30 M37 F30 R35 L34 M34 M35 R34 E30

M45 M43

R385 402 1% 4 AG1

INT_HDMI_HPD#

C50 A50

[13] INT_HDMI_HPD# [20] TypeC_HPD#

EDP_TXP0 AG7 EDP_TXN0 AG9 EDP_TXP1 AG12 EDP TXN1 AG10 EDP_TXP2 AC6 EDP_TXN2 AC5 EDP_TXP3 AC7 EDP_TXN3 AC9

EDP_RCOMP_P AG6 EDP_RCOMP_N AG5

EDP_AUXP AH10

EDP AUXN AH9

C54

A54

Q26A Q26B

[12] EDP_TXP0

[12] EDP_TXN0

[12] EDP_TXP1

[12] EDP_TXN1

[12] EDP_TXP2

[12] EDP_TXN2

[12] EDP_TXP3

[12] EDP_TXN3

R74 402 1% 4

[12] EDP_AUXP [12] EDP_AUXN

eDP Panel

HDMI DDCDATA SW C49 HDMI_DDCCLK_SW B49

[13] HDMI_DDCDATA_SW

[13] HDMI_DDCCLK_SW

C309 15p/50V 4

Y3 R301

_ _ _

_ _ _ _ _ _ _

_

_ _ _ _ _ _ _ _ _ _ _ _

AP7 MDSI_RCOM P

AK7 AK6 AM5 AM6 AM12 AM10 AK13 AM13

AM9 AM7

AP12 AP10 AR2 AR1 AP15 AP13 AP6 AP5

AP2 AP3

R87 150 1% 4

DDI0_TXP_0 MDSI_C_CLKN DDI0_TXN_0 DDI0_TXP_1 MDSI_A_DP_0 DDI0_TXN_1 MDSI_A_DN_0 DDI0_TXP_2 MDSI_A_DP_1 DDI0_TXN_2 MDSI_A_DN_1 DDI0_TXP_3 MDSI_A_DP_2 DDI0_TXN_3 MDSI_A_DN_2

MDSI_A_DP_3 DDI0_AUXP MDSI_A_DN_3 DDI0_AUXN

MDSI_A_CLKP MIPI_I2C_SDA MDSI_A_CLKN MIPI_I2C_SCL

MCSI_DPHY1.2_RCOMP DDI0_RCOMP_P DDI0_RCOMP_N MCSI_RX_DATA0_P

MCSI_RX_DATA0_N GPIO_200 MCSI_RX_CLK0_P GPIO_199 MCSI_RX_CLK0_N

MCSI_RX_DATA1_P EDP_TXP_0 MCSI_RX_DAT A1_N EDP_TXN_0 MCSI_RX_DATA2_P EDP_TXP_1 MCSI_RX_DAT A2_N EDP_TXN_1 MCSI_RX_CLK1_P EDP_TXP_2 MCSI_RX_CLK1_N EDP_TXN_2 MCSI_RX_DATA3_P EDP_TXP_3 MCSI_RX_DAT A3_N EDP_TXN_3

MCSI_DPHY1.1_RCOMP EDP_RCOMP_P EDP_RCOMP_N MCSI_DP_0

MCSI_DN_0 EDP_AUXP MCSI_DP_1 EDP_AUXN MCSI_DN_1

MCSI_DP_2 DDI1_DDC_SDA MCSI_DN_2 DDI1_DDC_SCL MCSI_DP_3

MCSI_DN_3 DDI0_DDC_SDA DDI0_DDC_SCL MCSI_CLKP_0

MCSI_CLKN_0 PNL1_VDDEN MCSI_CLKP_2 PNL1_BKLTEN MCSI_CLKN_2 PNL1_BKLTCTL

GP_CAMERAS B0 PNL0_VDDEN GP_CAMERASB1 PNL0_BKLTEN GP_CAMERASB2 PNL0_BKLTCTL GP_CAMERASB3

GP_CAMERAS B4 OSC_CLK_OUT_0 GP_CAMERASB5 OSC_CLK_OUT_1 GP_CAMERASB6 OSC_CLK_OUT_2 GP_CAMERASB7 OSC_CLK_OUT_3 GP_CAMERASB8 OSC_CLK_OUT_4 GP_CAMERASB9

GP_CAMERAS B10

GP_CAMERAS B11 OSCOUT OSCIN MDSI_A_TE

MDSI_C_TE

Section 4 of 12

A

Quanta Computer Inc.

PROJECT :ZAJ

R488 R300

0

1

0

1

0

1

0

Quanta PN

Description

AKD5JGSTL08 IC SDRAM (96P)MT 41K256M 16HA-125:E STNBSQ

AKD59GSTL12 IC SDRAM (96P)MT 41K256M 16TW-107:P STNBSQ

AKD5PGSTW29 IC SDRAM(9 6P)H5TC 4G63EFR -PBA(F BGA)STN BSQ

AKD5JG0T504 IC SDRAM(9 6P)K4B4 G1646E -BYK0(F BGA)STNB SQ

Quanta Computer Inc.

PROJECT :ZAJ

Vender

Miron-2GB

Hynix-2GB

Samsung-2GB

5

4

3

2

1

Rev

3A

Size

Document Number

BXTP (EMMC/LPC/SMB/ISH)

Date: Tuesday, March 21, 2017

Sheet

5 of 34

2N7002K

Samsung 32/64GB

Hynix 32/64GB

Kingston 32/64GB

0

1

0

1

eMMC_ID1 eMMC_ID0

Vender

[21]

IRQ_SERIRQ

[21]

ME_WR#

2

SOC_OVRIDE

Flash Descriptor Override (SOC_OVRIDE)

0 = Normal Override(Normal operation)

1 = Override

R390 10K_5%_4

SOC_SERIRQ

+1.8V_S5

R381

2.2K_5%_4

*10K_5%_4 *10K 5% 4 *10K 5% 4

R293

5

4

3

2

1

05

SATA_DEVS LP0 [16]

Apollolake (EMMC/LPC/I2C)

U21E APL BGA 1296P

+1.8V_S5

R321 *GS@10K 5% 4

R308 *10K 5% 4

V58 T58 T59 V51 V52 Y49 V55 V57 V54 Y51 Y58

F54 F52 H52 H54

J52

F58 K55 F61 H57 H58

F62 D61 E56 D59 C62 E62

Y61

Y62 W62 W63

[12] EMMC_DAT A_0 [12] EMMC_DAT A_1 [12] EMMC_DAT A_2 [12] EMMC_DAT A_3 [12] EMMC_DAT A_4 [12] EMMC_DAT A_5 [12] EMMC_DAT A_6 [12] EMMC_DAT A_7 [12]

EMMC_RCLK [12] EMMC_CMD [12]

EMMC_CLK

[9]

GPIO_104

[9]

GPIO_105

[9]

GPIO_106

[9]

GPIO_110

[9]

GPIO_111

[9]

GPIO_112

[9]

GPIO_113

[9]

GPIO_117

[9]

GPIO_120

[9]

GPIO_121

[9]

GPIO_123

V49 E34

GPIO RCOMP

200 1% 4 200 1% 4

33 5% 4 33_5%_4

33 5% 4

V59

EMMC_RCOMP R58

PCH_TPD_ INT# R25

+3V

R22 R21

10K 5% 4

D

C

B

A

D

C

B

A

A38 B33 C39 B39 B35 A34 B31 H39 B29 A30 L39 C34 E39 C30 C38 F39 C36 C35 J39 C33 B27 C26 A26 B25 C25 C27 C31 C29 B37 H35 C37 H34 F35 F34

Board_ID0 Board_ID1 Board_ID2 Board_ID3 Board_ID4 Board_ID5

Board ID6 Board ID8 Board_ID7

GPIO_23 GPIO_2 4 GPIO_2 5 RAM_ID0 RAM_ID1 RAM ID2 RAM_ID3 RAM_ID4 eMMC_ID0 eMMC ID1 RAM_ID5

HDA BCLK R HDA_SYNC_R

HDA_SDO_R

GPIO_104 GPIO 105 GPIO 106

GPIO_110

GPIO_111 GPIO_112 GPIO_113

GPIO 117

SOC_OVRIDE

GPIO 120 GPIO_121

GPIO_123

LPC_LAD0_R

ACCEL_INTA

[18]

SIO_EXT_SCI#

[21]

PCH_TPD_INT#

[18]

HDA

10K_5%_4

GPIO_23

2 5

Q4B Q4 A

2N7002KDW

NGFF_ SATA_DET # [16]

+3V

EMI

LPC_CLKOUT1

C336 *10p/50V_4

R487 R289

*10K_5%_4

5 2

Q25A

Q25B

*SSM6N43FU

+3V

TP32

[16,17,21] LPC_LA D0 [16,17,21] LPC_LA D1 [16,17,21] LPC_LA D2 [16,17,21] LPC_LA D3

[21] CLK_PCI_E C [16]

PCLK_TPM

[17] CLK_P CI_LP C

[16,21] CLKRUN#

[16,17,21]

LPC_LFRAME#

[16] SOC_SERIRQ

R374 R375 R370 R372

R379 R376 R380 R371 R369 R386

20 1% 4 LPC_LAD1_R

GPIO_2 4

20_1%_4 LPC_LAD3_R

LPC_CLKOUT0

LPC CLKOUT 1

AZ_CODEC_BITCLK

[14] AZ_CODEC_ SY NC [14] AZ_CO DEC_ SDIN0 [14]

AZ_CO DEC_ SDOU T [14]

EMI

B45

C45

A46

C44

B43

C43

A42

C42 H41

J41 L41

M41

P51 T52 P57 T54 T55 T57 P58

AB55 AC49 AC48 AC51 AB51 AC52 AB58 AB54

AM51 AM49 AM57 AM55 AM52 AK57

AR62 AR63

AN62 AM61

AP59 AP58

AM62 AL62

AP52 I2C4 SDA AP54

I2C4_SCL

AP49

TP9 TP7 TP8 TP10

C245

*10p/50V_4

SPKR [14]

GPIO_25

*10K_5%_4

5 2

Q24A

I2C4_S DA I2C4_S CL

*10K_5%_4

Q24B

*SSM6N43FU

SATA_DEVSLP1

[16]

+1.8V_S5

LPSS_I2C2_SDA LPSS_I2C2_SCL

LPSS_I2C3_SDA LPSS_I2C3_SCL

LPSS_I2C4_SDA LPSS_I2C4_SCL

LPSS_I2C5_SDA LPSS_I2C5_SCL

LPSS_I2C6_SDA LPSS_I2C6_SCL

LPSS_I2C7_SDA LPSS_I2C7_SCL

SDIO_PWR_DW N_N SDIO_D0 SDIO_D1 SDIO_D2 SDIO_D3 SDIO_CMD SDIO_CLK

SDCARD_LVL_WP SDCARD_D0 SDCARD_D1 SDCARD_D2 SDCARD_D3 SDCARD_CMD SDCARD_CLK SDCARD_CD_N

HW strap ID

Board_ID0

Board_ID1

Board_ID2

Board_ID3

Board_ID4

Board_ID5

Board_ID6

Board_ID7

Board_ID8

RAM_ID0

RAM_ID1

RAM_ID2

I2C4_S DA [18] I2C4_S CL [18]

R90

2K_1%_4

R92 2K 1% 4

+1.8V_S5

Touch PAD

R339 R341 R348 R347 R349 R342 R288 R282 R491

R350 R285 R340 R284 R338 R286

R287 R283

RAM_ID5 RAM _ID4 RAM_ ID3

Strap pin Descrip tion

0 = w/o type C 1 = w/ type C

0 = with EMMC

1 = without EMMC <HDD only>

0 = SATA SSD

1 = PCIE SSD

0 = none G sensor

1 = G sensor

0 = none TPM

1 = TPM

0 = EJ HDD

1 = Cloud book SSD

0 = EJ SSD

1 = Cloud book N/A

0 = EJ se ries

1 = Clo ud book

0 = UMA

1 = GPU 0 = Si ngle cha nnel (A o nly)

1 = Dual cha nnel (A & B)

0 = Cha nnel A 2GB

1 = Cha nnel A 4GB

0 = Cha nnel B 2GB

1 = Cha nnel B 4GB

Board ID

RAM ID

eMMC ID

1

2

3

Q30

6

VCCA VCCB

5

GND EO

4

A B

G2129TL1U

_ _ _ _

_ _

_

_ _

_ _ _ _

_ _

_

_ _

_ _ _

_ _

_ _ _ _

_ _

_

_ _

_

_ _

_ _ _ _

_

_ _ _ _

_

_ _ _ _

_ _

_

_ _

_ _ _ _

_

_ _ _ _

_ _ _ _ _

EMMC _D0

RSVD_V49 EMMC _D1 EMMC _D2

GPIO_RCOMP EMMC _D3 EMMC _D4

EMMC_RCOMP EMMC _D5 EMMC _D6 EMMC _D7 GPIO _0 EMMC_RCLK

GPIO_1 EMMC _CMD GP IO_2 EMMC_CLK

GPIO_3

GPIO _4 GPIO _5

SIO_SPI_0_CLK

GPIO _6

SIO_SPI_0_FS0

G PIO_7

SIO_SPI_0_FS1

G PIO_8

SIO_SPI_0_RXD

GPIO_9

SIO_SPI_0_TXD

GPIO _10

GPIO _11

SIO_SPI_1_CLK

GPIO _12

SIO_SPI_1_FS0

GPIO_13

SIO_SPI_1_FS1

GPIO_14

SIO_SPI_1_RXD

GPIO_15

SIO_SPI_1_TXD

GPIO _16

GPIO _17

SIO_SPI_2_CLK

GPIO _18

SIO_SPI_2_FS0

GPIO_19

SIO_SPI_2_FS1

GPIO_20

SIO_SPI_2_FS2

GPIO_21

SIO_SPI_2_RXD

GPIO_22

SIO_SPI_2_TXD

GPIO _23

GPIO _24

GPIO _25 LPC_AD 0 GPIO_ 26 LPC_AD 1 GPIO_ 27 LPC_AD 2 GPIO_ 28 LPC_AD 3 GPIO_ 29

GPIO _30 LPC_CLKOUT0

GPIO_31

LPC_CLKOUT1

GPIO_32

GPIO _33 LPC_C LKRUN_N LPC_FRAME_N LPC_SERIRQ

ISH_G PIO _0

ISH_GPIO _1 ISH_GPIO _2

Section 5 of 12

LPSS_UART0_TXD

ISH_GPIO _3

LPSS_UART0_RXD

ISH_GPIO_4

LPSS_UART0_RTS_N

ISH_GPIO_5

LPSS_UART0_CTS_N

ISH_GPIO_6

ISH_GPIO _7

LPSS_UART1_TXD

ISH_GPIO _8

LPSS_UART1_RXD

ISH_GPIO_9 LPSS_UART1_RTS_N LPSS_UART1_CTS_N

LPSS_I2C0_SDA LPSS_UART2_TXD LPSS_I2C0_SCL LPSS_UART2_RXD LPSS_UART2_RTS_N

LPSS_I2C1_SD A

LPSS_UART2_CTS_N LPSS_I2C1_SCL

AM48 R98 AK58 R399 AK51 AM54 R95

20 1% 4

*10K 5% 4 R318 10K 5% 4 10K_5%_4 R294

*10K_5%_4

*10K 5% 4 R295 10K 5% 4 10K 5% 4 R291 *10K 5% 4

+1.8V_S5

10K 5% 4 R317 10K 5% 4 R292

10K_5%_4

ACCEL_INTA

SIO_E XT_S CI#

R34

LPC LAD2 R

20 1% 4

20 1% 4 AB61 TPM@20 1% 4 AA62 *DBG@20 1% 4 20 1% 4

CLKRUN#_R

V62

20 1% 4 V61 20 1% 4 AB62

LPC_LFRAME #_R SOC SERIRQ R

GPIO_39 GPIO_40

GPIO 43 GPIO_44

GPIO_47 GPIO_48

AP51 AL63

AK61

AP62 AP61

I2C st andard/fast mode： I2C tot al lengh t is about 45 00 mils = 4. 5inchs Cb = 4.5*5pF +7pF = 29.5pF PU resis tor = 2K ohm

Board ID0 Board_ID1 Board_ID2 Board_ID3 Board ID4 Board_ID5 Board_ID6 Board_ID7 Board ID8

RAM ID0 RAM_ID1 RAM_ID2 RAM_ID3 RAM ID4 RAM_ID5

eMMC_ID0 eMMC ID1

10K 5% 4 R316 *10K 5% 4 10K_5%_4 R320

*10K_5%_4 10K 5% 4 R315 *10K 5% 4 10K 5% 4 R314 *10K 5% 4 10K 5% 4 R319 *10K 5% 4 10K_5%_4 R309

*10K_5%_4 10K 5% 4 R296 *10K 5% 4 10K 5% 4 R290 *10K 5% 4 10K 5% 4 R492 *10K 5% 4

*10K 5% 4 R330 10K 5% 4

[9]

GPIO_39

[9]

GPIO_40

[9]

GPIO_43

[9]

GPIO_44

[9]

SERIRQ IS 1.8V_S5 AT EC SIDE BUT 3V_S5 AT CPU/TPM SIDE

+1.8V_S5 +3V_S5

GPIO_47 GPIO_48

TP1

TP2

[9]

U22

TRST_N PIN

ML1220 Coin type AHL03001031 [VDE] 17mAH AHL03001057 [DBV] 17mAH

A A

R469

EJ@150K_ 1%_4

Quanta Computer Inc.

PROJECT :ZAJ

EC reset RTC

[21] CLR_ CMOS

R88 *S 4 ACP RESENT R475

CN13 Q34 E J@PMS T3904

3

4

EJ@530 14-00201-V 09

3

V CCRTC 3

VCCRTC 2

1

RTC_TES T# RTC_RS T#

5

2

Q11A Q1 1B

2N7002KDW

20K_1 %_4

C253

BAT54CW

R463 1K 1% 4

1

Trace width = 20 mils

Q29A

3

4

Q29B

6

1

2N7002KDW

+3VPC U

+3V RTC 1

RTC Circuitry (RTC)

CN7

1 2

R45 R38

4.7K_5 %_4 4.7K _5%_4

CLK_S DATA [18]

CLK_S CLK [18]

DDR_GS/S0

R365

1K_1%_4

PCH_MB DAT0_R

PCH MBC LK0 R

APL S5

R368

1K_1%_4

[21,22] SB _ACDC

B B

Size Docum ent Number

BXTP (PMU/PMIC/HDA/RTC)

Date: Tuesday March 21 2017 Sheet 6 of 34

5 4 3 2 1

Rev

3A

+3V_S5 +3V

CB@cabl e RTC 1u/6.3V _4

R246

20K_1 %_4

C254

1u/6.3V _4

20MIL

J1 *JUMP

RTC TEST#

+5V_S5

RTC Clock 32.768KHz (CPU)

C47 15p/50V 4

Trace length < 1000 mils

C34 15p/50V 4

5 4 3 2 1

Apollolake (PMU/PMIC/HDA)

colsed to CPU pin within 100 mils

C50 0.1u/16V 4 R61 10 5% 4

06

U21F APL BGA 1296P

RTC_TEST#

PMU_WA KE#

AH49 AC57

E47

AG55

RTC_RS T_N

SUSPWR DNACK

SUS_ST AT_N

AVS_I2S1_ WS_SYNC

AVS_I2S1_SDO

AVS_I2S1_SDI

AVS_I2S1_MCLK

AVS_I2S1_BCL K

AVS_I2S2_SDO

AVS_I2S2_SDI

AVS_I2S2_MCLK

AVS_I2S2_BCL K

AVS_I2S2_ WS_SYNC

AVS_I2S3_ WS_SYNC

AVS_I2S3_SDO

AVS_I2S3_SDI

AVS_I2S3_BCL K

AVS_DMIC_DAT A_2 AVS_DMIC_DAT A_1 AVS_DMIC_CL K_B1

AVS_DMIC_ CLK_AB2

AVS_DMIC_CL K_A1

VCC_RT C_EXT PAD

RTC_X2 RTC_X1

JTAG_PR EQ_N JTAG_PR DY_N

JTAG_P MODE

JTAG_T RST_N

JTAG_TMS JTAG_T DO

JTAG_TDI

JTAG_ TCK

GPIO_219 GPIO_218 GPIO_217 GPIO_216

PCIE_REF_CLK_RCO MP

SVID0_DATA

SVID0_CLK

SVID0_AL ERT_N

AC55 AC63 AG58

J62 K62 K61 G62 H63

M58 K59 K58 H59 M57

M61 L63 L62 M62

M52 M54 P52 M55 P54

_

PCH_S USPWR DNA CK

TP6

GPIO 78

GPIO_88

HDA_RST#_ R

GPIO_92

GPIO_82

RTC_TE ST_N RSM_RST_N PROCH OT_N PMU_WA KE_N PMU_SUSCLK PMU_SLP_S4_N PMU_SLP_S3_N PMU_SLP_S0_N PMU_RS TBTN_N PMU_RCOMP PMU_PW RBTN_ N PMU_PLT RST_N PMU_BATL OW_N PMU_AC_PR ESENT

SOC_P WROK

PMIC_TH ERMTRIP_N PMIC_STDBY PMIC_SD WN_B_G PIO_213 PMIC_RESET_ N PMIC_PW RGOO D PMIC_I2C_SD A PMIC_I2C_SCL GPIO_214 GPIO_215

PMC_SPI_TXD PMC_SPI_RXD PMC_SPI_FS 2 PMC_SPI_FS 1 PMC_SPI_FS 0 PMC_SPI_CLK

PWM0 PWM1 PWM2 PWM3

JTAGX INTRUDER

SMB_DATA SMB_CLK SMB_ALERT_N

RSVD_H43 RSVD_AG52 RSVD_J4 3 RSVD_AG54

[21] RSMRST#

[21,22,26] H _PROCHO T#

[21] SUSC#

[21] SUSB#

[21] DNBSW ON#

[21] EC_PWROK

PCH_S USPWR DNA CK H_PRO CHOT# THERM TRIP# SOC

PCH_SUSPW RDNA CK [21]

GPIO_ 78 [9]

PMU SUS CLK

AE62 AK54 AC62

PMU_S LP_S0 #

AD61

PMU_RSTBTN# AD62

PMU_RCOM P

AK55

TP37

TP38 TP36

D C D

C

GPIO_ 88 [9]

R52 33_5%_4

PCI_PLTRS T# PCH_BAT LOW# ACPRESEN T

THER MTRI P#_S OC

C79

0.1u/16 V_4

R83

10_5%_4

colsed to PU pin within 100 mils

AG57 AH51 AK49

AG49

J47 J45

M47

F48

H48

F47

H45

L47 P47

H50

J50

M48

P48 L48 E52

B41

C41

F41 E41

AZ_CO DEC_ RST # [14]

+1.8V_ S5

R384 R17 R23

+3V_S5

R82 R71 R85 R389 R67 R81

GPIO_ 92 [9]

GPIO_ 82 [9]

FOLLLOW AP L MOW31： UN-STUFF 51 OHM PULL DOWN RESISTOR ON

*10K 5% 4 1K 1% 4 *10K 5% 4

*100K 5% 4

AG51 AC58

RTC_X2

AC59

RTC_X1

C58 0.1u/16V 4

INT_ED P_HPD#

GPIO_ 34 GPIO_ 35 GPIO_ 36

[12] INT_EDP_HPD #

[9] GPI O_34 [9] GPI O_35 [9] GPI O_36

100 1% 4 100 1% 4

*51 5% 4 51 5% 4 100 1% 4 51 5% 4 51 5% 4

60.4 1% 4

220 5% 4

B21

R62 330K 5% 4 INTRUDER #

AC54

+3V_R TC

PCH MBD AT0 R PCH_MB CLK0_ R

PLTRST# [12,15,16,17,21]

T61 T62

R63

H43

AG52

J43

AG54

PLTRST# Buffer

PCI_PLTRS T#

Section 6 of 12

THERMALTRIP#

THER MTRI P#_S OC

R66

Q5 10K_5 %_4

3 1

2N7002K

colsed to CPU pin within 100 mils

C70

0.1u/16 V_4

R72

10_5%_4

SMBus(PCH)

R24 *S 4

_ _ _

_ _

RTC RST# _ _

_ _

_

_ _

_ _ _

C

_ _

_ _ _ _ _ _ _

_ _

_ _ _ _

_ _

_

_ _ _ _ _ _

_ _

_

_ _

. _ _4

_

, ,

VCCR TC_4

EJ@4. 7K_5% _4

R474 EJ@4 7K 5%

R468

EJ@68. 1K_1% _4

+3V_RTC Trace width = 20 mils

+3V_RTC

D26

2

R245

3

RTC R ST#

1K 1% 4 10K 5% 4 ACPRESE N T 10K 5% 4 *100K _5%_4 RS MRST# 20K 1% 4

R73 200 1% 4

AG59

PCH_BAT LOW# PMU_WAKE#

PMU_RS TBTN#

EC PWROK

+3V

+1.8V_S 5

XDP_P REQ# XDP_P RDY#

XDP_ TRST# XDP_ TMS XDP_ TDO XDP_ TDI XDP_ TCK

CLKDR V_RCOMP

C20

R307

C21

R306 B19 C24

R322 C23

R303 A22

R30 4 C22

R305 B23

R33 5

L30 M30 M29 P30

E21

R42

C18 C17 B17

SVID_ALERT#_R

R329

+1.05V

R323 R324 C313

169_1%_ 4 68_1%_4 1000p /50V_4

H CPU SVIDDAT VR_SV ID_AL ERT#_VC ORE

H_CPU_SVIDDAT [26] H_CPU_SVIDCLK [26] VR_SV ID_ALE RT#_VCORE [26]

THERM TRIP# [21]

CH01006JB08 -> 10p CH01506JB06 -> 15p CH-6806TB01 -> 6.8p

RTC X1

Y1 R60

32.768KHZ/20 ppm

10M_5%_4

RTC_X2

Quanta Computer Inc.

PROJECT :ZAJ

Rev

3A

Size Docum ent Num ber

BXTP (POWER)

Date: Tuesday , March 21, 2017 Sheet 7 of 34

5 4 3 2 1

Apollolake (POWER)

+VCC_VCCGI

07

+VNN

C304 C302 C29 3 C297 C3 01 C292 C298 47u/6.3 V_8 47u/6.3V _8 47u/6.3V _8 47 u/6.3V _8 4 7u/6.3 V_8 47u/6. 3V_8 47u/ 6.3V_8

U21H APL BGA 1296P

RSVD_AJ 44

VCC_VCGI_1 VCC_VCGI_2

VNN_SVID_1

VCC_VCGI_3

VNN_SVID_2

VCC_VCGI_4

VNN_SVID_3

VCC_VCGI_5

VNN_SVID_4

VCC_VCGI_6

VNN_SVID_6

VCC_VCGI_8

VNN_SVID_7

VCC_VCGI_9

VNN_SVID_8

VCC_VCG I_10

VNN_SVID_9

VCC_VCG I_11

VNN_SVID_10

VCC_VCG I_12

VNN_SVID_11

VCC_VCG I_13

VNN_SVID_12

VCC_VCG I_14 VCC_VCG I_15

VNN_SEN SE

VCC_VCG I_16

AJ44

AJ37 AJ39 AJ41 AJ42

AJ46 AK37 AK39 AK41 AK42 AK44 AK46 AM44

AG48

BG63

AC41 AA42

Y44 V44 V46

AJ25 AK25

AC22

AC20

AG20

AJ20

AJ22

AE18 AE20 AE22 AG22

AM20 AM28 AM37 AK20

AA18 AA20

AA36 AA37 AA39 AC36 AC37 AE36 AE37 AG36 E43 E45 E48 E50 R45 R47 U36 U37 U39 U41 U42 U44 U46 U47 U48 V36 V37 V39 V41 Y36 Y37 Y39 Y41 AA28 AA30 AA32 AC28 AC30 AC32 AE28 AE30 AE32 AG28 AG30 AG32 AJ28 AJ30 AJ32 AK28 AK30 AK32 AK34 AM30 E29 E35 E37 F29 U28 U30 U32 V28 V30 V32 Y28 Y30 Y32

AA25 AC25 AE25 U22 U23 V22 V23 V25 Y23 Y25 U25 U20

C4 C296 C 300 47u/6.3 V_8 47u/6.3 V_8 4 7u/6.3V _8

C8 C33 C41 22u/6.3 V_6 22u/6.3 V_6 2 2u/6.3V _6

C24 C14 C13 1u/6.3V _4 1u/6 .3V_ 4 1u/6.3V_ 4

+

C3

330u/2V _7343 H1.9

C66 C81 C46 C7 C6 22u/6.3 V_6 22u/6.3V_6 22u/6 .3V_6 22u/6 .3V_6 22u/6.3 V_6

C27 C23 C12 C39 C 31 C16 C 15 C11 C2 9 1u/6.3V_ 4 1u/6.3 V_4 1u/6.3 V_4 1u/6. 3V_4 1u/6.3V_4 1u/6.3 V_4 1u/6 .3V_4 1u/6 .3V_4 1u/6.3V_4

D

C

B

A

D

C

B

A

C65 C87 C85 22u/6.3V_6 22u/6. 3V_6 22u/6.3 V_6

+1.35VS US

C64 22u/6.3V_ 6

C84 22u/6.3V_ 6

C73 1u/6.3V_ 4

C77 1u/6.3V_ 4

C78 C76 1u/6.3V_4 1u/6. 3V_4

[26] VNN_SE NSE

+VCC_3.3V

+3V_S5

R84 *S 6

C38 1u/6.3V_ 4

+1.24V _S5

R395 *S 4

R394 *S 6

C72 1u/6.3V_ 4

R387 *S 6

C56 1u/6.3V_ 4

R396 *S 6

C86 1u/6.3V_ 4

R388 *0 5% 6

+1.8V_S 5

R86 *S 6

C62 1u/6.3V_ 4

+1.05V

R373 *S 8 R378 *S 8

C21 1u/6.3V_ 4

C37 C48 1u/6.3V_4 1u/6. 3V_4

C92 22u/6.3 V_6

C67 1u/6.3V_ 4

+VCC_ 1.24V _USB2

+VCC_ 1.24V _AUD_ ISH_ PLL

C74 C3 48 1u/6.3V_ 4 22u/6.3V_6

C71 C49 1u/6.3V_ 4 1u/6.3 V_4

C82 C83 1u/6.3V_ 4 1u/6.3 V_4

C57 C60 *1u/6. 3V_4 *1u /6.3V _4

+VCC 1.8V

C59 C63 1u/6.3V_ 4 1u/6.3 V_4

C17 C44 1u/6.3V_ 4 1u/6.3 V_4

+1.05V

+VCC_1.24V_ MPH Y

C68 22u/6.3V_ 6

+VCC 1.24V GLM

C80 C351 1u/6.3V_ 4 22u/6.3V_ 6

RSVD_AM32

+VCC 1.24V D SI CSI +VCC 1.24V AU D ISH PLL

AK22

V48

AA46 AC46 AE44 AE42 AC42 AC44

C69 *22u/6 .3V_6

C61 C91 1u/6.3V_ 4 22u/6.3 V_6

+3V_RTC

C45 1u/6.3V 4

+VCC_1.05V_ IO

C20 C40 1u/6.3V_ 4 22u/6.3 V_6

+VCC_ 1.05V _INT

R383 *S_6

AE46 AG25

BJ3

BJ61

AA44

D1

AA22 AC23

V18 Y18 Y20

AA23

P16 T15 T13

AN18 AN20 AN22 AN23 AN41 AN42 AN44 AN46 AR17 AR47 AT13 AT17 AT47 AT51 AV14 AV50

AM32

VCCRTC _3P3V

RSVD_D1

VCC_1P05V_IO_ 1 VCC_1P05V_IO_ 2 VCC_1P05V_IO_ 3 VCC_1P05V_IO_ 4 VCC_1P05V_IO_ 5

VCC_1P05V_3PH ASEI

VCC_1P05V_FUSE VCC_1P05V_FHV1 VCC_1P05V_FHV0

2.7A

Section 8 of 12

VCC_1P05V_1 VCC_1P05V_2 VCC_1P05V_3 VCC_1P05V_4 VCC_1P05V_5 VCC_1P05V_6 VCC_1P05V_7 VCC_1P05V_8

VCC_1P05V_9 VCC_1P05V_10 VCC_1P05V_11 VCC_1P05V_12

U21I APL BGA 1296P

RSVD_BJ62

BJ62

R41

R43

AM23 AM25 AM41 AM42

AN32

VCC_VCGI_SE NSE_P

VCC_VCGI_SENSE_N

2.8A

VCCIOA_1 VCCIOA_2 VCCIOA_3 VCCIOA_4

C99 C88 C94 C 95 C 89 C98 C100 22u/6.3 V_6 22u/6.3V _6 22u/6.3V _6 22 u/6.3V _6 2 2u/6.3 V_6 22u/6. 3V_6 22u/ 6.3V_6

C104 C96 1u/6.3V_4 1u/6. 3V_4

_ _

_ _ _ _ _ _ _ _ _ _

_ _

_ _ _ _

_ _ _

_ _ O

_ _

VNN_SVID_5

4.8A

VCC_VCGI_7

_17

21A

VCC_VCGI

RSVD_BG63

VCC_VC GI_18 VCC_VCG I_19

VCC_3P3V_A _1

VCC_VCG I_20

VCC_3P3V_A _2

VCC_VCG I_21

VCC_3P3V_A _4

VCC_VCG I_23

VCC_3P3V_A _5

VCC_VCG I_24

VCC_3P3V_A_USB_1

VCC_VCG I_25

VCC_3P3V_A_USB_2

VCC_VCG I_26 VCC_VCG I_27

RSVD_AC 22

VCC_VC GI_28 VCC_VCG I_29

RSVD_AC 20

VCC_VC GI_30 VCC_VCG I_31

VCC_1P24V_1P35V_A_ USB2

VCC_VC GI_32 VCC_VCG I_33

VCC_1P24V_1P35V_ A_PLL_1

VCC_VCG I_34

VCC_1P24V_1P35V_ A_PLL_2

VCC_VCG I_35 VCC_VCG I_36

VCC_1P24V_1P35V_A _MPHY_1

VCC_VC GI_37

VCC_1P24V_1P35V_A _MPHY_2

VCC_VC GI_38

VCC_1P24V_1P35V_A _MPHY_3

VCC_VCGI_39

VCC_1P24V_1P35V_A _MPHY_4

VCC_VC GI_40 VCC_VCG I_41

VCC_1P24V_1P35V_ A_GLML2LDO_1

VCC_VC GI_42

VCC_1P24V_1P35V_ A_GLML2LDO_2

VCC_VC GI_43

VCC_1P24V_1P35V_ A_GLML2LDO_3

VCC_VC GI_44

VCC_1P24V_1P35V_A _GLML2

VCC_VC GI_45 VCC_VCG I_46

VDD2_1P24_DSI_CSI# 1

VCC_VC GI_47

VDD2_1P24_DSI_CSI# 2

VCC_VC GI_48 VCC_VCG I_49

VCC_1P24V_1P35V_ A_AUD_ISH

VCC_VCG I_50 VCC_VCG I_51

RSVD_V48

VCC_VCG I_52 VCC_VCG I_53 VCC_VCG I_54

VCC_1P8V_A _1

VCC_VCG I_55

VCC_1P8V_A _2

VCC_VCG I_56

VCC_1P8V_A _3

VCC_VCG I_57

VCC_1P8V_A _4

VCC_VCG I_58

VCC_1P8V_A _5

VCC_VCG I_59

VCC_1P8V_A _6

VCC_VCG I_60

VCC_1P8V_A _7

VCC_VCG I_61

VCC_1P8V_A _8

VCC_VCG I_62 VCC_VCG I_63

VCC_VCG I_64 RSVD_BJ3 RSVD_BJ 61

VCC_3P3V_A _3

0.15A

VCC_VCG I_22

1.3A

0.4A

RSVD_AN3 2

Section 9 of 12

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 VDDQ_16

+VCC_ 1.05V _IO

C35 C32 C 25 C19 C 30 C26 22u/6.3 V_6 22u/6. 3V_6 1u/6.3V _4 1u/6.3V _4 1u/6.3V_ 4 1u/6.3V _4

VCCGI_SE NSE [26]

VCCGI SS_SE NSE [26]

C305 C303 C93 C90 22u/6.3V_ 6 22u/6 .3V_6 1u/6 .3V_4 1 u/6.3V _4

+VNN

5

R29 A12 A16 A20 A24 A28 A32 A36 A40 A44 A48

A5 A52 A56 A62

A9

AA1

AA2 AA27 AA34 AA41 AA63 AB10 AB12 AB16 AB48

AB5 AB52 AB57 AB59

AB9

AC18 AC27 AC34 AC39

AE1 AE10 AE11 AE13 AE14 AE16 AE17

AE2 AE23 AE27 AE34 AE39

AE4 AE41 AE47 AE48

AE5 AE50 AE51 AE53 AE54 AE56 AE57 AE59 AE63

AE7

AE8

AG13 AG18 AG23 AG27 AG34 AG37 AG39 AG41 AG42 AG44 AG46 AH15 AH16 AH48

AH5

AH52 AH54 AH55 AH57

5

4

Apollolake ULT (GND)

U21J APL_BGA_1296P U21K APL_BGA_1296P

3

L43 L45

L50 M14 M21 M27

M3 M32 M50 M59

M9

N1

N32 N63 P13 P19 P35 P37 P41 P43 P45

P5 P55 P59

P9 R23 R32 T49

U1 U10 U11 U13 U14 U16 U17 U18

3 2 2

1

08

M12 C15 F16 J16 D8 E8 H16 C9 F8 E10 E16 F14 F12 H10 H14 H12 A14 C14 M39 P39 R39 R37 C2 J29 P25 R30 C63 E63 D2 AP57

VSS_163 VSS_244 VSS_164 VSS_245 VSS_165 VSS_246 VSS_166 VSS_247 VSS_167 VSS_248 VSS_168 VSS_249 VSS_169 VSS_250 VSS_170 VSS_251 VSS_171 VSS_252 VSS_172 VSS_253 VSS_173 VSS_254 VSS_174 VSS_255 VSS_175 VSS_256 VSS_176 VSS_257 VSS_177 VSS_258 VSS_178 VSS_259 VSS_179 VSS_260 VSS_180 VSS_261 VSS_181 VSS_262 VSS_182 VSS_263 VSS_183 VSS_264 VSS_184 VSS_265 VSS_185 VSS_266 VSS_186 VSS_267 VSS_187 VSS_268 VSS_188 VSS_269 VSS_189 VSS_270 VSS_190 VSS_271 VSS_191 VSS_272 VSS_192 VSS_273 VSS_193 VSS_274 VSS_194 VSS_275 VSS_195 VSS_276 VSS_196 VSS_277 VSS_197 VSS_278 VSS_198 VSS_279 VSS_199 VSS_280 VSS_200 VSS_281 VSS_201 VSS_282 VSS_202 VSS_283 VSS_203 VSS_284 VSS_204 VSS_285 VSS_205 VSS_286 VSS_206 VSS_287 VSS_207 VSS_288 VSS_208 VSS_289 VSS_209 VSS_290 VSS_210 VSS_291 VSS_211 VSS_292 VSS_212 VSS_293 VSS_213 VSS_294 VSS_214 VSS_295 VSS_215 VSS_296 VSS_216 VSS_297 VSS_217 VSS_298 VSS_218 VSS_299 VSS_219 VSS_300 VSS_220 VSS_301 VSS_221 VSS_302 VSS_222 VSS_303 VSS_223 VSS_304 VSS_224 VSS_305 VSS_225 VSS_306 VSS_226 VSS_307 VSS_227 VSS_308 VSS_228 VSS_309 VSS_229 VSS_310 VSS_230 VSS_311 VSS_231 VSS_312 VSS_232 VSS_313 VSS_233 VSS_314 VSS_234 VSS_315 VSS_235 VSS_316 VSS_236 VSS_317 VSS_237 VSS_318 VSS_238 VSS_319 VSS_239 VSS_320 VSS_240 VSS_321 VSS_241 VSS_322 VSS_242 VSS_323 VSS_243 VSS_324

Section 11 of 12

U21G APL BGA 1296P

SPARE_9

NOCONNECT_16

SPARE_8

NOCONNECT_17

SPARE_7

NOCONNECT_18

SPARE_6

NOCONNECT_19

SPARE_5

NOCONNECT_20

SPARE_4

NOCONNECT_21

SPARE_3

NOCONNECT_22

SPARE_2

NOCONNECT_23

SPARE_11

NOCONNECT_24

SPARE_10

NOCONNECT_25

SPARE_1

NOCONNECT_26

SPARE_0

NOCONNECT_27

NOCONNECT_28 NOCONNECT_1 NOCONNECT_29 NOCONNECT_2 NOCONNECT_30 NOCONNECT_3 NOCONNECT_31 NOCONNECT_4 NOCONNECT_32 NOCONNECT_5 NOCONNECT_33 NOCONNECT_6 NOCONNECT_34 NOCONNECT_7 NOCONNECT_35 NOCONNECT_8 NOCONNECT_36 NOCONNECT_9 NOCONNECT_37 NOCONNECT_10 NOCONNECT_38 NOCONNECT_11 NOCONNECT_39 NOCONNECT_12 NOCONNECT_40 NOCONNECT_13 NOCONNECT_41 NOCONNECT_14 NOCONNECT_42 NOCONNECT_15 NOCONNECT_43

B13 C13

L16

M16

E23

F23

R25

AB49

AC13

AB13 AM59 AM58

T51

L14

R19

E6

R17

E3

D4 A60 A61 BJ2

BG1

P27

A3

M10

B15

D

C

B

A

D

C

B

A

Rev

3A

Quanta Computer Inc.

PROJECT :ZAJ

Size Document Number

BXTP (GND)

Date: Tuesday, March 21, 2017 Sheet 8 of 34

1

_ _

VSS_1 VSS_82 VSS_2 VSS_83 VSS_3 VSS_84 VSS_4 VSS_85 VSS_5 VSS_86 VSS_6 VSS_87 VSS_7 VSS_88 VSS_8 VSS_89 VSS_9 VSS_90 VSS_10 VSS_91 VSS_11 VSS_92 VSS_12 VSS_93 VSS_13 VSS_94 VSS_14 VSS_95 VSS_15 VSS_96 VSS_16 VSS_97 VSS_17 VSS_98 VSS_18 VSS_99 VSS_19 VSS_100 VSS_20 VSS_101 VSS_21 VSS_102 VSS_22 VSS_103 VSS_23 VSS_104 VSS_24 VSS_105 VSS_25 VSS_106 VSS_26 VSS_107 VSS_27 VSS_108 VSS_28 VSS_109 VSS_29 VSS_110 VSS_30 VSS_111 VSS_31 VSS_112 VSS_32 VSS_113 VSS_33 VSS_114 VSS_34 VSS_115 VSS_35 VSS_116 VSS_36 VSS_117 VSS_37 VSS_118 VSS_38 VSS_119 VSS_39 VSS_120 VSS_40 VSS_121 VSS_41 VSS_122 VSS_42 VSS_123 VSS_43 VSS_124 VSS_44 VSS_125 VSS_45 VSS_126 VSS_46 VSS_127 VSS_47 VSS_128 VSS_48 VSS_129 VSS_49 VSS_130 VSS_50 VSS_131 VSS_51 VSS_132 VSS_52 VSS_133 VSS_53 VSS_134 VSS_54 VSS_135 VSS_55 VSS_136 VSS_56 VSS_137 VSS_57 VSS_138 VSS_58 VSS_139 VSS_59 VSS_140 VSS_60 VSS_141 VSS_61 VSS_142 VSS_62 VSS_143 VSS_63 VSS_144 VSS_64 VSS_145 VSS_65 VSS_146 VSS_66 VSS_147 VSS_67 VSS_148 VSS_68 VSS_149 VSS_69 VSS_150 VSS_70 VSS_151 VSS_71 VSS_152 VSS_72 VSS_153 VSS_73 VSS_154 VSS_74 VSS_155 VSS_75 VSS_156 VSS_76 VSS_157 VSS_77 VSS_158 VSS_78 VSS_159 VSS_79 VSS_160 VSS_80 VSS_161 VSS_81 VSS_162

Section 10 of 12

BG29 BG32 BG35 BG41 BG45 BH1 BH2 BH21 BH25 BH39 BH43 BH62 BH63 BJ10 BJ14 BJ18 BJ28 BJ32 BJ36 BJ4 BJ46 BJ50 BJ54 BJ56 BJ60 BJ8 C12 C16 C28 C32 C40 C48 D32 D58 D6 E12 E14 E19 E27 E4 E54 F10 F21 F3 F32 F37 F43 F45 F50 F56 F59 F63 G1 G32 H17 H23 H29 H3 H37 H47 H61 H7 J12 J14 J19 J27 J30 J32 J35 J37 J48 J63 K32 K5 K54 K57 K6 L21 L27 L29 L35

U21L APL_BGA_1296P

U2 U27 U34 U5 U50 U51 U53 U54 U56 U57 U59 U62 U63 U7 U8 V20 V27 V34 V42 Y12 Y16 Y22 Y27 Y34 Y42 Y46 Y48 Y5 Y52 Y54 Y55 Y57 Y59 Y6 Y7

VSS_325 VSS_361 VSS_326 VSS_362 VSS_327 VSS_363 VSS_328 VSS_364 VSS_329 VSS_365 VSS_330 VSS_366 VSS_331 VSS_367 VSS_332 VSS_368 VSS_333 VSS_369 VSS_334 VSS_370 VSS_335 VSS_371 VSS_336 VSS_372 VSS_337 VSS_373 VSS_338 VSS_374 VSS_339 VSS_375 VSS_340 VSS_376 VSS_341 VSS_377 VSS_342 VSS_378 VSS_343 VSS_379 VSS_344 VSS_380 VSS_345 VSS_381 VSS_346 VSS_382 VSS_347 VSS_383 VSS_348 VSS_384 VSS_349 VSS_385 VSS_350 VSS_386 VSS_351 VSS_387 VSS_352 VSS_388 VSS_353 VSS_389 VSS_354 VSS_390 VSS_355 VSS_391 VSS_356 VSS_392 VSS_357 VSS_393 VSS_358 VSS_394 VSS_359 VSS_395

VSS_360

Sect 12/12

NOCONNECT_44 NOCONNECT_45

Section 7 of 12

AH58 AH59 AH6 AH7 AJ1 AJ18 AJ2 AJ23 AJ27 AJ34 AJ36 AJ63 AK10 AK12 AK18 AK23 AK27 AK36 AK48 AK5 AK52 AK59 AK9 AM18 AM22 AM27 AM34 AM36 AM39 AM46 AN1 AN10 AN11 AN13 AN14 AN16 AN17 AN2 AN25 AN27 AN28 AN30 AN34 AN36 AN37 AN39 AN47 AN48 AN5 AN50 AN51 AN53 AN54 AN56 AN57 AN59 AN63 AN7 AN8 AP55 AP9 AR19 AR32 AR45 AT12 AT16 AT19 AT2 AT25 AT29 AT3 AT35 AT39 AT45 AT48 AT52 AT57 AT61 AT62 AT7 AU32

4

AV19

AV2 AV21 AV23 AV29

AV3 AV32 AV35 AV41 AV43 AV45 AV55 AV61 AV62

AV9

AW14 AW30 AW34 AW50

AY10 AY32 AY54 AY58

AY6

B2

B3 B62 B63

B9

BA1 BA12 BA16 BA17

BA2 BA21 BA25 BA27 BA29 BA32 BA35 BA37 BA39 BA43 BA47 BA48 BA52 BA62 BA63 BB19 BB25

BB3 BB39 BB45 BB61 BC32

BD3 BD32 BD56 BD61

BD8

BE1 BE10 BE12 BE16 BE17 BE21 BE27 BE29 BE35 BE37 BE43 BE47 BE48 BE52 BE54 BE63

BF3 BF32 BF61 BG19

BG23

GPIO_36

Rev

3A

Size Document Number

HARDWARE STRAPS

Date: Tuesday, March 21, 2017 Sheet 9 of 34

5 4 3 2 1

HARDWARE STRAPS

09

D

C

Hardware Strap Strap Descr iption

VCC_1P24V_1P35V_A voltage select

GPIO_36 0 = 1.24V

1 = 1.35V

Enable CSE(TXE3.0) ROM Bypass

GPIO_39 0 = Disable bypass

1 = Enable Bypass

Allow eMMC as a boot source

GPIO_43 0 = Disable

1 = Enable

Allow SPI as a boot source

GPIO_44 0 = Disable

1 = Enable

Force DNX FW Load

GPIO_47 0 = Do not force

1 = Force

SMBus 1.8V/3.3V mode select

GPIO_78 0=buffers set to 3.3V

1=buffers set to 1.8V

PMU 1.8V/3.3V mode select

GPIO_88 0=buffers set to 3.3V mod e

1=buffers set to 1.8V mod e

SMBus No Re-Boot

GPIO_92 0 = Disable (default)

1 = Enable

LPC 1.8V/3.3V mode select

GPIO_110 0=buffers set to 3.3V mod e

1=buffers set to 1.8V mod e

Boot BIOS Strap

GPIO_111 0 = Boot from SPI

1 = Do not boot from SPI

Top swap override

GPIO_120 0 = Disable

1 = Enable

FOLLLOW APL WOW36： ENABLE BOOT FROM SPI GPIO_43=0;GPIO_44=1

+1.8V_S5

R27 R310 R311 R312 R28 R360 R19 R363 R16 R26 R18 *4.7K_5%_4 *4.7K_5%_4 *4.7K_5%_4 4.7K_5%_4 *4.7K_5%_4 *10K_5%_4 *10K_5%_4 *4.7K_5%_4 *4.7K_5%_4 *10K_5%_4 *4.7K_5%_4

D

C

GPIO_36 [6] GPIO_39 [5] GPIO_43 [5] GPIO_44 [5] GPIO_47 [5] GPIO_78 [6] GPIO_88 [6] GPIO_92 [6] GPIO_110 [5] GPIO_111 [5]

GPIO_120 [5]

A

Quanta Computer Inc.

PROJECT : ZAJ

B B

+1.8V_S5

GPIO_34 GPIO 35 GPIO_40 GPIO 48 GPIO_82 GPIO 104 GPIO_105 GPIO 117 GPIO_112 GPIO 113 GPIO_121

[6] GPIO_34 [6] GPIO_35 [5] GPIO_40 [5] GPIO_48 [6] GPIO_82 [5] GPIO_104 [5] GPIO_105 [5] GPIO_117 [5] GPIO_112 [5] GPIO_113 [5] GPIO_121

R346 10K 5% 4 R313 10K 5% 4 R334 4.7K 5% 4 R54 10K 5% 4 R59 10K 5% 4 R41 10K 5% 4 R43 10K 5% 4 R55 10K 5% 4 R57 4.7K 5% 4 R39 4.7K 5% 4 R35 10K 5% 4

R20 4.7K 5% 4 R356 10K 5% 4

[5] GPIO_106 [5] GPIO_123

A

_ _ _ _ _ _ _

_ _ _ _ _ _ _ _ _ _ _ _

_ _ _ _ _

_ _ _ _ _ _ _

_

GPIO 39 GPIO_43 GPIO_44 GPIO_47 GPIO_78 GPIO_88 GPIO_92 GPIO_110 GPIO_111

GPIO_120

R33 R343 R344 R345 R32 R364 R31 R367 R36 R29 R30 10K_5%_4 10K_5%_4 10K_5%_4 *10K_5%_4 10K_5%_4 10K_5%_4 10K_5%_4 10K_5%_4 4.7K_5%_4 4.7K_5%_4 10K_5%_4

[2] M_A_ A[15:0]

+1.35VS US

Distributed around all DRAM devices (CHA)

C362 C160 C16 2 C134 C12 0 C133 10u/6.3V _4 10u/6.3V _4 1 0u/6.3V _4 10u/6.3V_4 10u/6.3V_4 10 u/6.3V_ 4

Place these Caps near each X16 Memory Down

C148 C 366 C37 7 C157 C143 C153 1u/6.3V _4 1u/6. 3V_4 1u/6.3V_ 4 1u/6. 3V_4 1u /6.3V_4 1u/6.3 V_4

C365 C 361 C35 6 C357 C354 C369

Rev

3A

ize Documen t Num ber

DDR3L SODIMM-STD CHA

Date: Tuesday, Mar ch 21, 2017 hee t 10 of 34

5

4

3

2 1

FOLLLOW APL WOW37：MEMORY DOWN ODT SINGLE ON DRAM SIDE IS PULLED UP TO VDDQ

+1.35VSUS

C140 C142 C147

3.65K_ 1%_4 470p/5 0V_4 0.1u/16V _4 2. 2u/10V _4

Quanta Computer Inc.

PROJECT :ZAJ

C367 C 373 C36 0 C379

M_A_ ODT0

1u/6.3V _4 1u/6. 3V_4 1u/6.3V_ 4 1u/6. 3V_4

A

1u/6.3V _4 1u/6. 3V_4 1u/6.3V_ 4 1u/6. 3V_4 1u /6.3V_4 1u/6.3 V_4 3.65K_ 1%_4

R147

M_A_C LK0#

VREF_DQ trace at least 20mils wide and space

+SMDD R_VRE F_D Q_A

A

+1.35VS US

R145

5

4

3

2 1

DDR3L MEMORY CHANNEL A

10

BYTE4_32-39

BYTE6_48-55

M_A_D Q38 [ 2] M_A_D Q35 [ 2] M_A_D Q37 [ 2] M_A_D Q32 [ 2] M_A_D Q39 [ 2] M_A_D Q33 [ 2] M_A_D Q36 [ 2] M_A_D Q34 [ 2]

M_A_D Q55 [ 2] M_A_D Q51 [ 2] M_A_D Q50 [ 2] M_A_D Q52 [ 2] M_A_D Q48 [ 2] M_A_D Q54 [ 2] M_A_D Q49 [ 2] M_A_D Q53 [ 2]

+1.35VS US

On board memory(OBM)

+SMDDR_VREF _CA_A M8 +SMDDR VREF DQ A H1

BYTE0_0-7 BYTE1_8-15

U24 U8

BYTE2_16-23

BYTE3_24-31

M_A_D Q19 [ 2] M_A_D Q18 [ 2] M_A_D Q23 [ 2] M_A_D Q17 [ 2] M_A_D Q21 [ 2] M_A_D Q20 [ 2] M_A_D Q22 [ 2] M_A_D Q16 [ 2]

M_A_D Q28 [ 2] M_A_D Q31 [ 2] M_A_D Q30 [ 2] M_A_D Q24 [ 2] M_A_D Q27 [ 2] M_A_D Q26 [ 2] M_A_D Q29 [ 2] M_A_D Q25 [ 2]

+1.35VS US

[2] M_A_DQ S7 [2] M_A_DQ S5

[2] M_A _DQS# 7 [2] M_A_ DQS#5

BYTE7_56-63

BYTE5_40-47

M_A_D Q62 [ 2] M_A_D Q60 [ 2] M_A_D Q56 [ 2] M_A_D Q61 [ 2] M_A_D Q57 [ 2] M_A_D Q59 [ 2] M_A_D Q58 [ 2] M_A_D Q63 [ 2]

M_A_D Q40 [ 2] M_A_D Q43 [ 2] M_A_D Q46 [ 2] M_A_D Q41 [ 2] M_A_D Q44 [ 2] M_A_D Q47 [ 2] M_A_D Q45 [ 2] M_A_D Q42 [ 2]

+1.35VS US

[2] M_A_DQS4 [2] M_A_DQ S6

[2] M_A _DQS# 4 [2] M_A _DQS# 6

U25

VREFCA DQL 0/DQ0 VREFD Q DQL1/DQ1

DQL2/D Q2 A0 DQL 3/DQ3 A1 DQL 4/DQ4 A2 DQL 5/DQ5 A3 DQL 6/DQ6 A4 DQL 7/DQ7 A5 A6 A7 DQU0/D Q8 A8 DQU1/D Q9 A9 DQU2/ DQ10 A10/AP D QU3/D Q11 A11 DQU 4/DQ1 2 A12/BC DQU5/D Q13 A13 DQU 6/DQ14 A14 DQU 7/DQ1 5 A15/NC

BA0 VD D#B2 BA1 VDD# D9 BA2 VDD#G 7

VDD#K2 VDD#K8

VDD#N1 CK VDD#N9 CK VDD#R1 CKE VDD# R9

ODT VDDQ#A1 CS VDDQ# A8 RAS VD DQ#C1 CAS VDDQ#C9 W E VD DQ#D2

VDDQ#E 9

VDDQ# F1 DQSL VDDQ#H 2 DQSU VDD Q#H9

DML VSS#A9 DMU VSS# B3

VSS#E1

VSS#G8 DQSL VS S#J2 DQSU VSS#J8

VSS#M1

VSS#M9

VSS#P1

RESET VSS#P9

VSS#T1

ZQ VSS#T9

VSSQ#B 1 VSSQ#B 9 VSSQ#D1 VSSQ#D8

VSSQ#E 2 NC#J1 VSSQ #E8 NC#L1 VSSQ# F9 NC#J9 V SSQ#G1 NC#L9 VSSQ#G9

96-BALL SDRAM D DR3L

U9

VREFCA DQL 0/DQ0 VREFD Q DQL1/DQ1

DQL2/D Q2 A0 DQL 3/DQ3 A1 DQL 4/DQ4 A2 DQL 5/DQ5 A3 DQL 6/DQ6 A4 DQL 7/DQ7 A5 A6 A7 DQU0/D Q8 A8 DQU1/D Q9 A9 DQU2/ DQ10 A10/AP D QU3/D Q11 A11 DQU 4/DQ1 2 A12/BC DQU5/D Q13 A13 DQU 6/DQ1 4 A14 DQU 7/DQ1 5 A15/NC

BA0 VD D#B2 BA1 VDD# D9 BA2 VDD#G 7

VDD#K2 VDD#K8

VDD#N1 CK VDD#N9 CK VDD#R1 CKE VDD# R9

ODT VDDQ#A1 CS VDDQ# A8 RAS VD DQ#C1 CAS VDDQ#C9 W E VD DQ#D2

VDDQ#E 9

VDDQ# F1 DQSL VDDQ#H 2 DQSU VDD Q#H9

DML VSS#A9 DMU VSS# B3

VSS#E1

VSS#G8 DQSL VS S#J2 DQSU VSS#J8

VSS#M1

VSS#M9

VSS#P1

RESET VSS#P9

VSS#T1

ZQ VSS#T9

VSSQ#B 1 VSSQ#B 9 VSSQ#D1 VSSQ#D8

VSSQ#E 2 NC#J1 VSSQ #E8 NC#L1 VSSQ# F9 NC#J9 V SSQ#G1 NC#L9 VSSQ#G9

96-BALL SDRAM D DR3L

+SMDDR_VREF _CA_A M8 +SMDDR VREF DQ A H1

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

M_A_D Q7 [2] M_A_D Q3 [2] M_A_D Q2 [2] M_A_D Q4 [2] M_A_D Q6 [2] M_A_D Q0 [2] M_A_D Q1 [2] M_A_D Q5 [2]

M_A_D Q10 [ 2] M_A_D Q12 [ 2] M_A_D Q9 [2] M_A_D Q8 [2] M_A_D Q13 [ 2] M_A_D Q11 [ 2] M_A_D Q14 [ 2] M_A_D Q15 [ 2]

+1.35VS US

[2] M_A_DQ S2 [2] M_A_DQ S3

[2] M_A _DQS# 2 [2] M_A _DQS# 3

VREFCA DQL 0/DQ0 VREFD Q DQL1/DQ1

DQL2/D Q2 A0 DQL 3/DQ3 A1 DQL 4/DQ4 A2 DQL 5/DQ5 A3 DQL 6/DQ6 A4 DQL 7/DQ7 A5 A6 A7 DQU0/D Q8 A8 DQU1/D Q9 A9 DQU2/ DQ10 A10/AP D QU3/D Q11 A11 DQU 4/DQ1 2 A12/BC DQU5/D Q13 A13 DQU 6/DQ1 4 A14 DQU 7/DQ1 5 A15/NC

BA0 VD D#B2 BA1 VDD# D9 BA2 VDD#G 7

VDD#K2 VDD#K8

VDD#N1 CK VDD#N9 CK VDD#R1 CKE VDD# R9

ODT VDDQ#A1 CS VDDQ# A8 RAS VD DQ#C1 CAS VDDQ#C9 W E VD DQ#D2

VDDQ#E 9

VDDQ# F1 DQSL VDDQ#H 2 DQSU VDD Q#H9

DML VSS#A9 DMU VSS# B3

VSS#E1

VSS#G8 DQSL VS S#J2 DQSU VSS#J8

VSS#M1 VSS#M9

VSS#P1 RESET VSS#P9

VSS#T1 ZQ VSS#T9

VSSQ#B 1 VSSQ#B 9 VSSQ#D1 VSSQ#D8

VSSQ#E 2 NC#J1 VSSQ #E8 NC#L1 VSSQ# F9 NC#J9 V SSQ#G1 NC#L9 VSSQ#G9

96-BALL SDRAM D DR3L

VREFCA DQL 0/DQ0 VREFD Q DQL1/DQ1

DQL2/D Q2 A0 DQL3/D Q3 A1 DQL 4/DQ4 A2 DQL 5/DQ5 A3 DQL 6/DQ6 A4 DQL 7/DQ7 A5 A6 A7 DQU0/D Q8 A8 DQU1/D Q9 A9 DQU2/ DQ10 A10/AP D QU3/D Q11 A11 DQU 4/DQ1 2 A12/BC DQU5/D Q13 A13 DQU 6/DQ1 4 A14 DQU 7/DQ1 5 A15/NC

BA0 VD D#B2 BA1 VDD# D9 BA2 VDD#G 7

VDD#K2 VDD#K8

VDD#N1 CK VDD#N9 CK VDD#R1 CKE VDD# R9

ODT VDDQ#A1 CS VDDQ# A8 RAS VD DQ#C1 CAS VDDQ#C9 W E VD DQ#D2

VDDQ#E 9

VDDQ# F1 DQSL VDDQ#H 2 DQSU VDD Q#H9

DML VSS#A9 DMU VSS# B3

VSS#E1

VSS#G8 DQSL VS S#J2 DQSU VSS#J8

VSS#M1 VSS#M9

VSS#P1 RESET VSS#P9

VSS#T1 ZQ VSS#T9

VSSQ#B 1 VSSQ#B 9 VSSQ#D1 VSSQ#D8

VSSQ#E2 NC#J1 VSSQ #E8 NC#L1 VSSQ# F9 NC#J9 V SSQ#G1 NC#L9 VSSQ#G9

96-BALL SDRAM D DR3L

M_A_A 0 M_A_A 1 M_A_A 2 M A A3 M_A_A 4 M_A_A 5 M_A_A 6 M_A_A 7 M A A8 M_A_A 9 M_A_A 10 M_A_A 11 M_A_A 12 M A A 13 M_A_A 14 M_A_A 15

M A BS#0 M_A_B S#1 M_A_B S#2

M_A_C LK0 M_A_C LK0# M_A_C KE0

M_A_ ODT0 M_A_C S#0 M_A_R AS# M_A_C AS# M A W E#

M_A_D QS0 M_A_D QS1

M_A_D QS#0 M_A_D QS#1

MA_DRA MRST#

M_A_Z Q1

R414

240_1%_4

N3

P7 P3

N2

P8

P2 R8 R2

T8 R3

L7 R7 N7

T3

T7 M7

M2 N8 M3

J7 K7 K9

K1

L2

J3 K3

L3

F3 C7

E7 D3

G3 B7

T2

L8

J1

L1

J9

L9

M_A_A 0 M_A_A 1 M_A_A 2 M A A3 M_A_A 4 M_A_A 5 M_A_A 6 M_A_A 7 M A A8 M_A_A 9 M_A_A 10 M_A_A 11 M_A_A 12 M A A 13 M_A_A 14 M_A_A 15

M A BS#0 M_A_B S#1 M_A_B S#2

M_A_C LK0 M_A_C LK0# M_A_C KE0

M_A_ ODT0 M_A_C S#0 M_A_R AS# M_A_C AS# M A W E#

M_A_D QS2 M_A_D QS3

M_A_D QS#2 M_A_D QS#3

N3

P7

P3 N2

P8

P2 R8 R2

T8 R3

L7 R7 N7

T3

T7 M7

M2 N8 M3

J7 K7 K9

K1

L2

J3 K3

L3

F3 C7

E7 D3

G3 B7

M_A_A 0 M_A_A 1 M_A_A 2 M A A3 M_A_A 4 M_A_A 5 M_A_A 6 M_A_A 7 M A A8 M_A_A 9 M_A_A 10 M_A_A 11 M_A_A 12 M A A 13 M_A_A 14 M_A_A 15

M A BS#0 M_A_B S#1 M_A_B S#2

M_A_C LK0 M_A_C LK0# M_A_C KE0

M_A_ ODT0 M_A_C S#0 M_A_R AS# M_A_C AS# M A W E#

M_A_D QS7 M_A_D QS5

M_A_D QS#7 M_A_D QS#5

N3

P7

P3 N2

P8

P2 R8 R2

T8 R3

L7 R7 N7

T3

T7 M7

M2 N8 M3

J7 K7 K9

K1

L2

J3 K3

L3

F3 C7

E7 D3

G3 B7

M_A_A 0 M_A_A 1 M_A_A 2 M A A3 M_A_A 4 M_A_A 5 M_A_A 6 M_A_A 7 M A A8 M_A_A 9 M_A_A 10 M_A_A 11 M_A_A 12 M A A 13 M_A_A 14 M_A_A 15

M A BS#0 M_A_B S#1 M_A_B S#2

M_A_C LK0 M_A_C LK0# M_A_C KE0

M_A_ ODT0 M_A_C S#0 M_A_R AS# M_A_C AS# M A W E#

M_A_D QS4 M_A_D QS6

M_A_D QS#4 M_A_D QS#6

N3

P7

P3 N2

P8

P2 R8 R2

T8 R3

L7 R7 N7

T3

T7 M7

M2 N8 M3

J7 K7 K9

K1

L2

J3 K3

L3

F3 C7

E7 D3

G3 B7

D

C

L8

J1 L1 J9 L9

+1.35VS US

VREF_CA trace at least 20mils wide and space

R144

+SMDDR_VRE F_CA _A

3.65K_ 1%_4

R146

C139 C141 C146

3.65K_ 1%_4 470p/5 0V_4 0.1u/16V _4 2. 2u/10V _4

MA_DRA MRST# T2

M_A_Z Q2

R149 240_1%_4

M_A_Z Q3

R412 240_1%_4

L8

J1 L1 J9 L9

M_A_Z Q4

R162 240_1%_4

L8

J1 L1 J9 L9

H5TC4 G63EFR-PBA H5 TC4G6 3EFR-PBA H5TC4 G63EFR-PBA H5TC4 G63EFR-PBA

VTT TERMINATIONS

DE-CAPS FOR MEMORY CHANNEL A

VREF_CA-DQ CIRCUIT

B

+VDDQ_ VTT

_ _ _ _ _ _ _ _ _ _ _ _

_ _ _ _ _ _ _ _

_ _

. _ _

_ _

. _ _

_ _

. _ _

_ _

. _ _

_ _

. _ _

_ _

. _ _

_ _

. _ _

_ _

. _ _

_ _

. _ _

_ _

S

R152 1K 1% 4

M_A_C LK0

R154 80.6 1% 4

M_A_R AS# M_A_C AS# M_A_W E# M_A_B S#0 M_A_B S#1 M_A_B S#2 M_A_C KE0 M_A_C S#0

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8

M_A_A9 M_A_A 10 M_A_A 11 M_A_A 12 M_A_A 13 M_A_A 14 M_A_A 15

R423 80.6 1% 4 R426 80.6 1% 4 R429 80 6 1% 4 R428 80.6 1% 4 R187 80 6 1% 4 R422 80.6 1% 4 R419 80.6 1% 4 R420 80 6 1% 4 R427 80.6 1% 4 R188 80 6 1% 4 R189 80.6 1% 4 R425 80.6 1% 4 R185 80 6 1% 4 R184 80.6 1% 4 R183 80 6 1% 4 R182 80.6 1% 4 R424 80.6 1% 4 R180 80 6 1% 4 R430 80.6 1% 4 R179 80 6 1% 4 R178 80.6 1% 4 R186 80.6 1% 4 R181 80 6 1% 4 R421 80.6 1% 4

D

[2] M _A_BS# [2:0]

[2] M_A_CL K0 [2] M_A_CL K0# [2] M_A_CK E0

[2] M_A_CS #0 [2] M_A_RA S# [2] M_A_CA S# [2] M_A_W E#

[2] M_A_DQ S0

C

[2] M_A_DQ S1

[2] M_A _DQS# 0 [2] M_A _DQS# 1

[2] MA_DRA MRST#

[2] M_B_ A[15:0]

+1.35VS US

Distributed around all DRAM devices (CHB)

C164 C371 C15 0 C132 C15 8 C151 10u/6.3V _4 10u/6.3V _4 1 0u/6.3V _4 10u/6.3V_4 10u/6.3V_4 10 u/6.3V_ 4

Place these Caps near each X16 Memory Down

C374 C 166 C35 5 C372 C368 C364 1u/6.3V _4 1u/6. 3V_4 1u/6.3V_ 4 1u/6. 3V_4 1u /6.3V_4 1u/6.3 V_4

C376 C 175 C17 1 C136 C121 C168

Rev

3A

ize Documen t Num ber

DDR3L MEMORY DOWNx16 CHB

Date: Tuesday, Mar ch 21, 2017 hee t 11 of 34

5

4

3

2 1

FOLLLOW APL WOW37：MEMORY DOWN ODT SINGLE ON DRAM SIDE IS PULLED UP TO VDDQ

+1.35VSUS

C149 C152 C156

3.65K_ 1%_4 470p/5 0V_4 0.1u/16V _4 2. 2u/10V _4

Quanta Computer Inc.

PROJECT : ZAJ

C358 C 363 C37 8 C375

M_B_ ODT0

1u/6.3V _4 1u/6. 3V_4 1u/6.3V_ 4 1u/6. 3V_4

A

1u/6.3V _4 1u/6. 3V_4 1u/6.3V_ 4 1u/6. 3V_4 1u /6.3V_4 1u/6.3 V_4 3.65K_ 1%_4

R150

M_B_C LK0#

+1.35VS US

VREF_CA trace at least 20mils wide and space

R166

+SMDDR_VRE F_CA _B

3.65K_ 1%_4

R164

C167 C165 C163

3.65K_ 1%_4 470p/5 0V_4 0.1u/16V _4 2. 2u/10V _4

+VDDQ_ VTT

VREF_DQ trace at least 20mils wide and space

+SMDD R_VRE F_D Q_B

A

+1.35VS US

R148

DE-CAPS FOR MEMORY CHANNEL B

5

4

3

2 1

DDR3L MEMORY CHANNEL B

11

BYTE6_48-55

BYTE4_32-39

On board memory(OBM)

+SMDDR_VREF _CA_B M8 +SMDDR VREF DQ B H1

BYTE0_0-7

BYTE2_16-23

BYTE1_8-15

BYTE3_24-31

BYTE5_40-47

BYTE7_56-63

U26

VREFCA DQL 0/DQ0 VREFD Q DQL1/DQ1

DQL2/D Q2 A0 DQL 3/DQ3 A1 DQL 4/DQ4 A2 DQL 5/DQ5 A3 DQL 6/DQ6 A4 DQL 7/DQ7 A5 A6 A7 DQU0/D Q8 A8 DQU1/D Q9 A9 DQU2/ DQ10 A10/AP D QU3/D Q11 A11 DQU 4/DQ1 2 A12/BC DQU5/D Q13 A13 DQU 6/DQ1 4 A14 DQU 7/DQ1 5 A15/NC

BA0 VDD#B 2 BA1 VDD# D9 BA2 VDD#G 7

VDD#K2 VDD#K8

VDD#N1 CK VDD#N9 CK VDD#R1 CKE VDD# R9

ODT VDDQ#A1 CS VDDQ# A8 RAS VD DQ#C1 CAS VDDQ#C9 W E VD DQ#D2

VDDQ#E 9

VDDQ# F1 DQSL VDDQ#H 2 DQSU VDD Q#H9

DML VSS#A9 DMU VSS# B3

VSS#E1

VSS#G8 DQSL VS S#J2 DQSU VSS#J8

VSS#M1

VSS#M9

VSS#P1

RESET VSS#P9

VSS#T1

ZQ VSS#T9

VSSQ#B 1 VSSQ#B 9 VSSQ#D1 VSSQ#D8

VSSQ#E 2 NC#J1 VSSQ #E8 NC#L1 VSSQ# F9 NC#J9 V SSQ#G1 NC#L9 VSSQ#G9

96-BALL SDRAM D DR3L

U10

VREFCA DQL 0/DQ0 VREFD Q DQL1/DQ1

DQL2/D Q2 A0 DQL 3/DQ3 A1 DQL 4/DQ4 A2 DQL 5/DQ5 A3 DQL 6/DQ6 A4 DQL 7/DQ7 A5 A6 A7 DQU0/D Q8 A8 DQU1/D Q9 A9 DQU2/ DQ10 A10/AP D QU3/D Q11 A11 DQU 4/DQ1 2 A12/BC DQU5/D Q13 A13 DQU 6/DQ1 4 A14 DQU 7/DQ1 5 A15/NC

U11

VREFCA DQL 0/DQ0 VREFD Q DQL1/DQ1

DQL2/D Q2 A0 DQL 3/DQ3 A1 DQL 4/DQ4 A2 DQL 5/DQ5 A3 DQL 6/DQ6 A4 DQL 7/DQ7 A5 A6 A7 DQU0/D Q8 A8 DQU1/D Q9 A9 DQU2/ DQ10 A10/AP D QU3/D Q11 A11 DQU 4/DQ1 2 A12/BC DQU5/D Q13 A13 DQU 6/DQ1 4 A14 DQU 7/DQ1 5 A15/NC

U27

VREFCA DQL 0/DQ0 VREFD Q DQL1/DQ1

DQL2/D Q2 A0 DQL 3/DQ3 A1 DQL 4/DQ4 A2 DQL 5/DQ5 A3 DQL 6/DQ6 A4 DQL 7/DQ7 A5 A6 A7 DQU0/D Q8 A8 DQU1/D Q9 A9 DQU2/ DQ10 A10/AP D QU3/D Q11 A11 DQU 4/DQ1 2 A12/BC DQU5/D Q13 A13 DQU 6/DQ1 4 A14 DQU 7/DQ1 5 A15/NC

M_B_D Q0 M B DQ4 M_B_D Q5 M_B_D Q6

+SMDDR_VREF _CA_B M8 +SMDDR VREF DQ B H1

E3 F7 F2 F8

M_B_DQ0 [2] M_B_D Q4 [2] M_B_D Q5 [2] M_B_D Q6 [2] M_B_D Q1 [2] M_B_D Q3 [2] M_B_D Q2 [2] M_B_D Q7 [2]

M_B_D Q16 [2] M_B_D Q22 [2] M_B_D Q23 [2] M_B_D Q21 [2] M_B_D Q18 [2] M_B_D Q17 [2] M_B_D Q19 [2] M_B_D Q20 [2]

+1.35VS US

[2] M_B_DQ S1 [2] M_B_DQ S3

[2] M_B _DQS# 1 [2] M_B _DQS# 3

M_B_D Q12 [ 2] M_B_D Q15 [ 2] M_B_D Q13 [ 2] M_B_D Q14 [ 2] M_B_D Q9 [2] M_B_D Q11 [ 2] M_B_D Q10 [ 2] M_B_D Q8 [2]

M_B_D Q27 [2] M_B_D Q28 [2] M_B_D Q30 [2] M_B_D Q25 [2] M_B_D Q26 [2] M_B_D Q31 [2] M_B_D Q29 [2] M_B_D Q24 [2]

+1.35VS US

[2] M_B_DQ S5 [2] M_B_DQ S7

[2] M_B _DQS# 5 [2] M_B _DQS# 7

M_B_D Q47 [2] M_B_D Q43 [2] M_B_D Q42 [2] M_B_D Q41 [2] M_B_D Q40 [2] M_B_D Q44 [2] M_B_D Q46 [2] M_B_D Q45 [2]

M_B_D Q56 [2] M_B_D Q58 [2] M_B_D Q60 [2] M_B_D Q63 [2] M_B_D Q62 [2] M_B_D Q59 [2] M_B_D Q61 [2] M_B_D Q57 [2]

+1.35VS US

[2] M_B_D QS6 [2] M_B_D QS4

[2] M_ B_DQS# 6 [2] M_ B_DQS# 4

M_B_D Q53 [2] M_B_D Q48 [2] M_B_D Q51 [2] M_B_D Q52 [2] M_B_D Q50 [2] M_B_D Q55 [2] M_B_D Q54 [2] M_B_D Q49 [2]

M_B_D Q34 [2] M_B_D Q39 [2] M_B_D Q36 [2] M_B_D Q33 [2] M_B_D Q38 [2] M_B_D Q32 [2] M_B_D Q37 [2] M_B_D Q35 [2]

+1.35VS US

E3 M_B _DQ12 F7 M_B _DQ15 F2 M_B _DQ13 F8 M_B _DQ14 H3 M_B_ DQ9 H8 M_B_ DQ11 G2 M B DQ10 H7 M_B_ DQ8

D7 M_B_ DQ27 C3 M_B_ DQ28 C8 M_B_ DQ30 C2 M_B_ DQ25 A7 M_B _DQ26 A2 M_B _DQ31 B8 M_B _DQ29 A3 M_B _DQ24

E3 M_B _DQ53 F7 M_B _DQ48 F2 M_B _DQ51 F8 M_B _DQ52 H3 M_B_ DQ50 H8 M_B_ DQ55 G2 M B DQ54 H7 M_B_ DQ49

D7 M_B_ DQ34 C3 M_B_ DQ39 C8 M_B_ DQ36 C2 M_B_ DQ33 A7 M_B _DQ38 A2 M_B _DQ32 B8 M_B _DQ37 A3 M_B _DQ35

M_B_A 0 M_B_A 1 M_B_A 2 M B A3 M_B_A 4 M_B_A 5 M_B_A 6 M_B_A 7 M B A8 M_B_A 9 M_B_A 10 M_B_A 11 M_B_A 12 M B A 13 M_B_A 14 M_B_A 15

M B BS#0 M_B_B S#1 M_B_B S#2

M_B_C LK0 M_B_C LK0# M_B_C KE0

M_B_ ODT0 M_B_C S#0 M_B_R AS# M_B_C AS# M B W E#

M_B_D QS0 M_B_D QS2

M_B_D QS#0 M_B_D QS#2

MB_DRA MRST#

M_B_Z Q1

R413 240_1%_4

N3

P7 P3

N2

P8 P2

R8 R2

T8

R3

L7

R7 N7

T3 T7

M7

M2 N8 M3

J7

K7 K9

K1

L2 J3

K3

L3

F3

C7

E7 D3

G3 B7

T2 L8

J1 L1 J9 L9

M_B_A 0 M_B_A 1 M_B_A 2 M B A3 M_B_A 4 M_B_A 5 M_B_A 6 M_B_A 7 M B A8 M_B_A 9

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3

M_B_A 0 M_B_A 1 M_B_A 2 M B A3 M_B_A 4 M_B_A 5 M_B_A 6 M_B_A 7 M B A8 M_B_A 9

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3

M_B_A 0 M_B_A 1 M_B_A 2 M B A3 M_B_A 4 M_B_A 5 M_B_A 6 M_B_A 7 M B A8 M_B_A 9

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3

E3 M_B _DQ47 F7 M_B _DQ43 F2 M_B _DQ42 F8 M_B _DQ41 H3 M_B_ DQ40 H8 M_B_ DQ44 G2 M_B_DQ4 6 H7 M_B_ DQ45

D7 M_B_ DQ56 C3 M_B_ DQ58 C8 M_B_ DQ60 C2 M_B_ DQ63 A7 M_B _DQ62 A2 M_B _DQ59 B8 M_B _DQ61 A3 M_B _DQ57

H3 M_B_ DQ1 H8 M_B_ DQ3 G2 M B DQ2 H7 M_B_ DQ7

D7 M_B_ DQ16 C3 M B DQ22 C8 M_B_ DQ23 C2 M_B_ DQ21 A7 M_B _DQ18 A2 M_B _DQ17 B8 M B DQ19

D

C

M_B_A 10 L 7 M_B_A 11 R7 M_B_A 12 N7 M B A 13 T3 M_B_A 14 T7 M_B_A 15 M 7

A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

M_B_D Q20

M B BS#0 M_B_B S#1 M_B_B S#2

M_B_C LK0 M_B_C LK0# M_B_C KE0

M_B_ ODT0 M_B_C S#0 M_B_R AS# M_B_C AS# M B W E#

M_B_D QS1 M_B_D QS3

M_B_D QS#1 M_B_D QS#3

M2 B2

M B BS#0 M_B_B S#1 M_B_B S#2

M_B_C LK0 M_B_C LK0# M_B_C KE0

M_B_ ODT0 M_B_C S#0 M_B_R AS# M_B_C AS# M B W E#

M_B_D QS5 M_B_D QS7

M_B_D QS#5 M_B_D QS#7

M2 B2

M B BS#0 M_B_B S#1 M_B_B S#2

M_B_C LK0 M_B_C LK0# M_B_C KE0

M_B_ ODT0 M_B_C S#0 M_B_R AS# M_B_C AS# M B W E#

M_B_D QS6 M_B_D QS4

M_B_D QS#6 M_B_D QS#4

M2 B2

BA0 VD D#B2 BA1 VDD# D9 BA2 VDD#G 7

VDD#K2 VDD#K8

VDD#N1 CK VDD#N9 CK VDD#R1 CKE VDD# R9

ODT VDDQ#A1 CS VDDQ# A8 RAS VD DQ#C1 CAS VDDQ#C9 W E VD DQ#D2

VDDQ#E 9

VDDQ# F1 DQSL VDDQ#H 2 DQSU VDD Q#H9

DML VSS#A9 DMU VSS# B3

VSS#E1

VSS#G8 DQSL VS S#J2 DQSU VSS#J8

VSS#M1 VSS#M9

VSS#P1 RESET VSS#P9

VSS#T1 ZQ VSS#T9

VSSQ#B 1 VSSQ#B 9 VSSQ#D1 VSSQ#D8

VSSQ#E 2 NC#J1 VSSQ #E8 NC#L1 VSSQ# F9 NC#J9 V SSQ#G1 NC#L9 VSSQ#G9

96-BALL SDRAM D DR3L

BA0 VD D#B2 BA1 VDD# D9 BA2 VDD#G 7

VDD#K2 VDD#K8

VDD#N1 CK VDD#N9 CK VDD#R1 CKE VDD# R9

ODT VDDQ#A1 CS VDDQ# A8 RAS VD DQ#C1 CAS VDDQ#C9 W E VD DQ#D2

VDDQ#E 9

VDDQ# F1 DQSL VDDQ#H 2 DQSU VDD Q#H9

DML VSS#A9 DMU VSS# B3

VSS#E1

VSS#G8 DQSL VS S#J2 DQSU VSS#J8

VSS#M1 VSS#M9

VSS#P1 RESET VSS#P9

VSS#T1 ZQ VSS#T9

VSSQ#B 1 VSSQ#B 9 VSSQ#D1 VSSQ#D8

VSSQ#E 2 NC#J1 VSSQ #E8 NC#L1 VSSQ# F9 NC#J9 V SSQ#G1 NC#L9 VSSQ#G9

96-BALL SDRAM D DR3L

BA0 VD D#B2 BA1 VDD# D9 BA2 VDD#G 7

VDD#K2 VDD#K8

VDD#N1 CK VDD#N9 CK VDD#R1 CKE VDD# R9

ODT VDDQ#A1 CS VDDQ# A8 RAS VD DQ#C1 CAS VDDQ#C9 W E VD DQ#D2

VDDQ#E 9

VDDQ# F1 DQSL VDDQ#H 2 DQSU VDD Q#H9

DML VSS#A9 DMU VSS# B3

VSS#E1

VSS#G8 DQSL VS S#J2 DQSU VSS#J8

VSS#M1 VSS#M9

VSS#P1 RESET VSS#P9

VSS#T1 ZQ VSS#T9

VSSQ#B 1 VSSQ#B9 VSSQ#D1 VSSQ#D8

VSSQ#E 2 NC#J1 VSSQ #E8 NC#L1 VSSQ# F9 NC#J9 V SSQ#G1 NC#L9 VSSQ#G9

96-BALL SDRAM D DR3L

N8 M3

J7 K7 K9

K1

L2

J3 K3

L3

F3 C7

E7 D3

G3 B7

D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

N8 M3

J7 K7 K9

K1

L2

J3 K3

L3

F3 C7

E7 D3

G3 B7

D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

N8 M3

J7 K7 K9

K1

L2

J3 K3

L3

F3 C7

E7 D3

G3 B7

D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

VREF_CA-DQ CIRCUIT

B

H5TC4 G63EFR-PBA H5 TC4G6 3EFR-PBA H5TC4 G63EFR-PBA H5TC4 G63EFR-PBA

VTT TERMINATIONS

MB_DRA MRST# T2

M_B_Z Q2

R155 240_1%_4

L8

J1 L1 J9 L9

M_B_Z Q3

R159 240_1%_4

L8

J1 L1 J9 L9

M_B_Z Q4

R411 240_1%_4

L8

J1 L1 J9 L9

_ _ _ _ _ _ _ _ _ _ _ _ _ _

_ _ _ _ _ _ _ _ _ _

_ _ _ _ _ _ _ _

_ _

. _ _

_ _

. _ _

_ _

. _ _

_ _

. _ _

_ _

. _ _

_ _

. _ _

_ _

. _ _

_ _

. _ _

_ _

. _ _

_ _

S

R160 1K 1% 4

M_B_C LK0

R156 80.6 1% 4

M_B_R AS# M_B_C AS# M_B_W E# M_B_B S#0 M_B_B S#1 M_B_B S#2 M_B_C KE0 M_B_C S#0 M_B_A 0 M_B_A 1 M_B_A 2 M_B_A 3 M_B_A 4 M_B_A 5 M_B_A 6 M_B_A 7 M_B_A 8 M_B_A 9 M_B_A 10 M_B_A 11 M_B_A 12 M_B_A 13 M_B_A 14 M_B_A 15

R435 80.6 1% 4 R438 80.6 1% 4 R441 80 6 1% 4 R440 80.6 1% 4 R199 80 6 1% 4 R434 80.6 1% 4 R431 80.6 1% 4 R432 80 6 1% 4 R439 80.6 1% 4 R200 80 6 1% 4 R201 80.6 1% 4 R436 80.6 1% 4 R197 80 6 1% 4 R196 80.6 1% 4 R195 80 6 1% 4 R194 80.6 1% 4 R437 80.6 1% 4 R192 80 6 1% 4 R442 80.6 1% 4 R191 80 6 1% 4 R190 80.6 1% 4 R198 80.6 1% 4 R193 80 6 1% 4 R433 80.6 1% 4

D

[2] M _B_BS# [2:0]

[2] M_B_CL K0 [2] M_B_CL K0# [2] M_B_CK E0

[2] M_B_CS #0 [2] M_B_RA S# [2] M_B_CA S# [2] M_B_W E#

[2] M_B_DQ S0

C

[2] M_B_DQ S2

[2] M_B _DQS# 0 [2] M_B _DQS# 2

[2] MB_DRA MRST#

C322

Rev

3A

Size

Document Number

eDP/ CCD/eMMC

Date:

Tuesday, March 21, 2017

Sheet 12 of 34

5 4

3

2 1

D14 D13

*AZ5725-01F.R7G *AZ5725-01F.R7G

D12

*AZ5725-01F.R7G

196538-40041-3 2N7002KDW

D11 *AZ5725-01F.R7G

Q2 DDTC144EUA-7-F

5 2

Q3A

Q3B

EC_FPBACK#

[21]

Quanta Computer Inc.

PROJECT : ZAJ

[3] USBP6+

CCD-USB

[3] USBP6[3] USBP5+

Touch P anel-USB

[3] USBP5-

[14] DMIC_D AT [14]

DMIC_CLK

[4] PCH_BL ON

[21] PCH_BL ON_E C

R10

*S 4

R9

*S 4

BL#

1N4 148WS

BL_ON

PCH_BL ON_R

R8

2

100K_5%_4

[4]

EDP_TXP1

[4] EDP_TXN1 [4]

EDP_TXP2

[4] EDP_TXN2 [4]

EDP_TXP3

[4] EDP_TXN3

LID# [13,21]

LID59 1#,E C i ntrn al PU

D1

eDP FHD

EDP TXP1 C

EDP TXP2 C EDP TXN2 C

EDP TXP3 C EDP_TXN3_C

+3V

R7 10K_5%_4

+3VPC U

R11

10K_5%_4

Q1

PJA138K

R2

C1

100K_5%_4 180p/50V_4

Prevent ESD/EO S Layout near connector

[4]

EDP_AUXP

[4] EDP_A UXN

[4]

EDP_TXP0

[4] EDP_TXN0

R275

*S 6

R276

*S 4

R277

*S 4

[21]

TS_EN

[4] PCH_BRIG HT

5 4

3

2 1

eMMC (MMC)

12

D

C

B

A

+1.8V

+3V

15 mils

+1.8V_E MMC

R325 *S_4

C331

C321 C317

C319

C316

EC@1u/6. 3V_4

[email protected]/16V_4 EC@1u/6.3V_4 [email protected]/16V_4 [email protected]/16V_4

U2

VCCQ_1 VCCQ_2 VCCQ_3 VCCQ_4 VCCQ_5

VCC_1 VCC_2 VCC_3 VCC_4

VDDI

VSS_1 VSS_2 VSS_3 VSS_4

NC#L4 NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 NC_23 NC_24 NC_25 NC_26 NC_27 NC_28 NC_29 NC_30 NC_31 NC_32 NC_33 NC_34 NC_35 NC_36 NC_37 NC_38 NC_39 NC_40 NC_41 NC_42 NC_43 NC_44 NC_45 NC_46 NC_47 NC_48 NC_49 RFU#3 RFU#4 RFU#2 NC_53 NC_54 NC_55 NC_56 NC_57 NC_58 RFU#5 NC_60 NC_61 NC_62 NC_63 NC_64 NC_65 RFU#6 NC_67 NC_68 NC_69

+3V

+1.8V

R355

*EC@20K_1%_4

EMMC CLK R

EMMC_CMD [5]

TP5

K6

AA5

W4

Y4

AA3 T10

U9

M6

N5

+VDDI_ EMMC

K2

R10

U8

M7

P5

L4 A4 A6 A9

A11

B2

B13

D1

D14

H1 H2 H6 H7 H8

H9 H10 H11 H12 H13 H14

J1

J7

J8

9 J10 J11 J12 J13 J14

K1 K3 K5 K7 K8

K9 K10 K11 K12 K13 K14

L1

L2

L3

L12 L13 L14 M1 M2 M3 M5 M8

M9 M10 M12 M13 M14

N1 N2

N3 N10 N12 N13 N14

P1

P2

P3 P10 P12 P13 P14

W6 W5

H3 EMMC DATA 0 H4

EMMC_ DATA_ 1

H5

EMMC_ DATA_ 2

J2

EMMC_D ATA_3

J3

EMMC_D ATA_4

J4

EMMC_D ATA_5

J5

EMMC_D ATA_6

J6

EMMC_D ATA_7

U5 AA6

Y5 K4 AA4 Y2

R331

*S 4

C318 *[email protected]/50V_4

EMI request

EMMC_ CLK [5]

CLK

CMD

DAT0 DAT1 DAT2 DAT3 DAT4 DAT5 DAT6 DAT7

RESET

VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5

NC_70 NC_71 NC_72 NC_73 NC_74 NC_75 NC_76 NC_77 NC_78 NC_79 NC_80 NC_81 NC_82 NC_83 NC_84 NC_85 NC_86

NC_87 NC_88 RFU#7 NC_90 NC_91 NC_92 NC_93 NC_94 NC_95 NC_96 NC_97 NC_98

NC_99 NC_100 NC_101 NC_102 NC_103 NC_104 NC_105 NC_106 NC_107 NC_108 NC_109 NC_110 NC_111 NC_112 NC_113 NC_114 NC_115 NC_116 NC_117 NC_118 NC_119 NC_120 NC_121 NC_122 NC_123 NC_124 NC_125

RFU#1 NC_127 NC_128 NC_129 NC_130 NC_131 NC_132 NC_133 NC_134 NC_135 NC_136 NC_137 NC_138

15 mils

+3V_EMMC

D

C

B

A

Power Signals

GND

NC

co-layout

R353 *S_4

LCDVC C

+3V

+5V

R1 R2 R3 R5 R12 R13 R14 T1 T2 T3 T5 T12 T13 T14 U1 U2 U3

U6 U7 U10 U12 U13

14

V1 V2 V3 V12 V13 V14 W1 W2 W3 W7 W8 W9 W10 W11 W12 W13 W14 Y1 Y3 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 AA1 AA2 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AE1 AE14 AG2 AG13 AH4 AH6 AH9 AH11

PLTRST#

[6,15,16,17,21]

LCDVC C 1 2

C306 C308 C311

0.1u/16V_ 4

0.01u/50V_4

22u/6.3V_6

2

EMMC RCLK

EDP HPD R

EDP HPD

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

100K_5%_4

eDP Backlight (LDS)

R1

33 5%

DualDMIC PWR

MAX 1.5A

VOUT_ BACKL IGHT

EC@Hy nix 32 GB

eDP Power (LDS)

+3V

C315

1u/6.3V_4

[4] EDP_VDD_EN

VOUT_ BACKL IGHT

TP_PWR

CCD+D MIC_PWR

C9 C2

C284 C283

C282

C281

100p/50V_4 0.1u/25V_4

0.1u/16V_4

1000p/50V_4 0.1u/16V_4 1000p/50V_4

+VIN

[6] INT_EDP_HPD#

+12V_Panel

OUT GND

3

0 5% 4

4

*0 5% 4

5

IN#2

4

IN#1

3

EN

co-layout

R5

NVL@0 5% 6

R6

VL@0 5% 6

G5245AT11U

Enable: High Active /2 A GMT:AL0 05245000 NVT:AL003522001

CN3

R281

_ _

_

_ _

_ _ J U

_ R _ _ R _ _

_ _ _

_

_ _

_

_ _4

_

_ _

EDP TXN EDP TXN

_

_ _

. _ EDP_TXN1 EDP_TXN1_C

C

.

_

_ _

.

_

_ _

.

_

_ _

. _ .

_ _ _

M C D I C_ LK_C

R280

*S_4

EDP_TXP0_C

_

0_C

EDP_AUXP EDP_AUXN

EDP_TXP0

_ 0

EDP TXP1

EDP TXP2 EDP TXN2

EDP TXP3 EDP_TXN3

C285

0.1u/16V 4

C286

0.1u/16V 4

+3V

C287

0.1u/16V 4

C288 0.1u/16V _4 C289

0 1u/16V 4

290

0 1u/16V 4

C291

0 1u/16V 4

C294

0 1u/16V 4

C295

0 1u/16V 4

C299

0 1u/16V 4

R278

*100K_5%_4

R279

*100K 5% 4

EDP_AUXP_C EDP_AUXN_C

Reserve for 4K2K pa nel

R274

*0_5%_6

LCDVCC R

CCD+D MIC_P WR

TP_PWR

DualDMIC_PWR

BL_ON EDP_HPD_R

EMMC_ DATA_0 [5] EMMC_ DATA_1 [5] EMMC_ DATA_2 [5] EMMC_ DATA_3 [5] EMMC_ DATA_4 [5] EMMC_ DATA_5 [5] EMMC_ DATA_6 [5] EMMC_ DATA_7 [5]

EMMC RST#

EMMC_RCLK [5]

R357 EC@100K_5%_4

+1.8V

R63 EC@20K_1%_4

D2

2

1

EC@RB500V-40

U19

C320 C328

[email protected]/16V_4 EC@1u/6.3V_4 EC@1u/6.3V_4 [email protected]/16V_4 [email protected]/16V_4

C329

eDP CONNECTOR (LDS)

C327

C330

[email protected]/16V_4

C

+1.8V HDMI_5 V

R103 R110

HDMI_HPD

R400 D2 9

100K_5%_4 *VARISTOR

Size

Document Number

R401 *0 5% 4 R402 *S 4

co-layout

C138

4.7u/6.3V_4

*AZ5725-01F.R7G

*AZ5725-01F.R 7G

HDMI HPD ROUT

2 HDMI_HPD_NOR-

2.2_5%_6

SSM6N43FU

LID#

[12,21]

Q14

YB8251ST23

*PJA13 8K

Q9

4 3

Q10A

R112

*2.2K_5%_4

Q10B

1 6

R107 *0 5% R108 *S 4

co-layout

R114 *0 5% R115 *S 4

R120 *0 5 % R104 *S 4

co-layout

R121 *0 5 % R113 *S 4

DDCCLK ROUT DDCCLK NOR-1

DDCDATA_ROU DDCDATA_NOR

R410 *S 4 R409 *S 4

R408 *S 4 R407 *S 4

R406 *S 4 R405 *S 4

R404 *S 4 R403 *S 4

[4]

INT_HDMI_HPD#

[4]

INT_HDMITX0P

[4]

INT_HDMITX0N

[4]

INT_HDMITX1P

[4]

INT_HDMITX1N

[4]

INT_HDMITX2P

[4]

INT_HDMITX2N

[4]

INT_HDMICLK+

[4]

INT_HDMICLK-

1st:AL008251000 -- YBT 2nd:AL008132004 -- ANC

R142 *0 5% 4 R140 *0 5% 4 R137 *0_5%_4 R135 *0 5% 4 R132 *0 5% 4 R130 *0 5% 4 R125 *0 5% 4 R123 *0 5% 4

C125 0.1u/1 6V 4 C123 0.1u/1 6V 4

C119 0 1u/1 6V 4 C117 0.1u/1 6V 4

C115 0.1u/1 6V 4 C113 0.1u/1 6V 4

C111 0 1u/1 6V 4 C108 0.1u/1 6V 4

+3V

[4]

HDMI_DDCCLK_SW

[4]

HDMI_DDCDATA_SW

INT_HDMITX0P_NOR INT_HDMITX0N_NOR

INT HDMITX1 P NO R INT HDMITX1 N NOR

INT_HDMITX2P_NOR INT_HDMIT 2N_NOR

INT HDMIC K+ NOR INT_HDMIC K-_NOR

R122 R126 R12 9 R 133 R1 34 R138 R139 R1 43

470_1%_4 470_1%_4 470_1%_4 470_1%_4 470_1%_4 470_1%_4 470_1%_4 470_1%_4

2

Q13 2N70 02K

+1.8V

10 INT HDMITX0P C

9

INT_HDMITX0N_C

7

INT_HDMITX1P_C

6

INT_HDMITX1N_C

10 INT HDMITX2P C

9

INT_HDMITX2N_C

7 INT HDMICLK + C

6

INT_HDMICLK-_C

EMI

Quanta Computer Inc.

PROJECT : ZAJ

1

Line-1 NC#4

2

Line-2 NC#3

3

GND#1

4

Line-3 NC#2

5

Line-4 NC#1

*AZ1045-04F.R7G

ESD6

1

Line-1 NC#4

2

Line-2 NC#3

3

GND#1

4

Line-3 NC#2

5

Line-4 NC#1

*AZ1045-04F.R7G

INT_HDMITX0P_C INT_HDMITX0N_C INT_HDMITX1P_C INT HDMITX1N C INT_HDMITX2P_C INT_HDMITX2N_C INT_HDMICLK+_C INT_HDMICLK-_C

INT_HDMITX0P_C INT_HDMITX0N_C

INT HDMITX1P C INT HDMITX1N C

INT_HDMITX2P_C INT_HDMITX2N_C

INT HDMICL K+ C INT_HDMICLK-_C

R100 *0 5% 4

R99 *S 4

co-layout

C106

*0.1u/1 6 V_4

D30

HMRBL-AK120C

*VARISTOR

ESD7

C

B

A

2.2K_5%_4

HDMI DDCCLK

R116

2.2K_5%_4

HDMI_DDCDATA

D4 D5

*2.2K_5%_4

DDCCLK RIN DDCCLK NOR

DDCDATA_RIN DDCDATA_NOR

HDMI_5 V

C353 *220p/50V_4

INT HDMITX0P C

INT_HDMITX0N_C

INT_HDMITX1P_C

INT_HDMITX1N_C

INT HDMITX2P C

INT_HDMITX2N_C

INT HDMICLK + C

INT_HDMICLK-_C

IN_D1-

OUT_D 1-

IN_D1+

OUT_D 1+

IN_D2-

OUT_D 2-

IN_D2+

OUT_D 2+

IN_D3-

OUT_D 3-

IN_D3+

OUT_D 3+

IN_D4-

OUT_D 4-

IN_D4+

OUT_D 4+

GND#1

GND#5 GND#4 GND#3 GND#2

*PTN3366BS

+5V

U5

1

OUT

3

IN

2

GND

G5250Q1T73U

GMT:AL005250003 BCD:AL002802002

HDMI_HPD_RIN

Q12

3 1

HDMI/Hall sensor

Date:

Tuesday, March 21, 20 17

Sheet

13 of 34

5 4 3 2 1

16 15 14 13 12 11 10 9

37 36 35 34

5 4 3 2 1

HDMI (HDM)

+3V +3V

INT_HDMITX0P INT_HDMITX0N INT_HDMITX1P INT HDMITX1N INT_HDMITX2P INT_HDMITX2N INT_HDMICLK+ INT_HDMICLK-

INT_HDMITX0P INT_HDMITX0N

INT HDMITX1P INT HDMITX1N

INT_HDMITX2P INT_HDMITX2N

INT HDMICLK+ INT_HDMICLK-

INT_HDMITX0P_C_ROUT

INT_HDMITX0N_C_ROUT

INT_HDMITX1P_C_ROUT

INT HDMITX1N C ROUT

INT_HDMITX2P_C_ROUT INT_HDMITX2N_C_ROUT INT_HDMICLK+_C_ROUT

INT_HDMICLK-_C_ROUT

13

C124 *0.1u/16V 4 C122 *0.1u/16V 4 C118 *0.1u /16V_ 4 C116 *0 1u/16 V 4 C114 *0.1u/16V 4 C112 *0.1u/16V 4 C110 *0.1u/16V 4 C107 *0.1u/16V 4

PJA138K

Rev

3A

HDMI_EQ1

HDMI_EQ0

C105

*0.1u/1 6 V_4

INT_HDMITX0P_C_RIN 25 INT_HDMITX0N_C_RIN 26 INT_HDMITX1P_C_RIN 27 INT HDMITX1N C RIN

28

INT_HDMITX2P_C_RIN 29 INT_HDMITX2N_C_RIN 30 NT_HDMICLK+_C_RIN 31 INT_HDMICLK-_C_RIN 32

33

+3V

R118

*10K_5%_4

R109 *0 5% 4

R119

*10K_5%_4

R111 *0 5% 4

+3V

D D

HDMI_HPD_ROUT DDCDATA_ROUT DDCCLK ROUT

+3V

C109

*0.1u/1 6V _4

U6

C131 C129 C127 C126 C128 C137 C130

*0.1u/16V_4 *0.1u/16V_4

*0.1u /16V_ 4

*0.1u/16V_4

*0.1u /16V_ 4 * 0.1u/ 1 6V_ 4 *0.1 u/16 V_4

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19

INT_HDMITX2P_C

INT_HDMITX2N_C INT HDMITX1P C

INT_HDMITX1N_C INT_HDMITX0P_C

INT_HDMITX0N_C INT HDMICL K+ C

INT_HDMICLK-_C

HDMI DDCCLK HDMI_DDCDATA

HDMI_HPD

CN6

D2+

D2_shield

D2-

D1+

D1_shield

D1-

D0+

D0_shield

D0-

CLK+

CLK_shield

CLK-

CEC

NC

DDC CLK

DDC DATA

GND

+5V

HP DET

_ _ _ _

_

_ _

_ _ _

_ _ _ _ _ _ _ _ _ _ _

. _ _ _

_ _ _

I

_ _ _

_

_ _ _ _

_ _

_ _ _ _ _

. _ _

_ _ _ _ _

_ _

X

_ _

_ _ _ _

_ _ L _ _ _

. _ _

L

_ _

_ _ _ _

_ _ _ _ _

_ _

1 _ _ _

_ _4 _ _4

_ _ _

_ _

T

_ _4 _ _4

-1

_ _

HDMI_HPD_RIN_Q

HDMI_HPD_NOR

B

Hall Sensor (HSR)

A

+3VP CU

R151

Analog

Digital

1 2

D25 1N4148W S

1 2

D23 1N4148W S

C261 10u/6.3V_4

200K 1% 4 100K 1% 4

R255 20K 1% 4

HP_JD# [ 1

trace width of SLEEVE & RING2 are required at least 40mil and its length should be asshort as possible

Placement near Audio Codec

C213

0.1u/16V _4

Rev

3A

Size Docum ent N umber

Audio Codec/HP/SPK/AMIC

Date: Tuesday M arch 21 2017 Sheet 14 of 34

3

2

1

C435 C434 C 432 C433 1000p/5 0V_4 1000 p/50V_4 10 00p/50V _4 1000p/ 50V_4

40mil for each signal

R SPK+

_ L_SPKL_SPK+

+1.5V

CN19 C397

1u/6.3V _4

50278-00401- 01

Tied at one point only under the codec or near t he codec

R479 *S 4 R473 *S 4 R460 *S 4 R227 *S 4 R239 *S 4 R235 *S 4

C436 * 1000p/ 50V 4 C260 *0. 1u/16V 4

ADOGND

Cap need ne ar AVDD1 and AVDD2 power source input

2 1

PBY16 8 8T-600Y-N

Quanta Computer Inc.

PROJECT : ZAJ

C442 C441 C417 C243 100p/50V _4 100p/50V _4 100p/50V_ 4 100p/50V_4

L_SPK+

L SPKR_SPK- R_SPK+

+3VPCU

C443 10u/ 6.3V_4

L9

1 2

PBY1608 08T-600Y-

C412

10u/6.3V_4

C411

10u/6.3V_4

LINE1-L LINE1-R

SLEEVE RING2

SENSEA

24

LINE2-L

23

LINE2-R

22

LINE1-L

21

LINE1-R

20

VD33 STB

19

MIC-CAP

18

MIC2 R/SLEEV E

17

MI 2 -L/RING2

16

ONO-OUT

15

SPD IFO/ FRON

JD/GPIO3

14

MI 2/LIN2 JD

13

HP/LINE1 JD

37

CBP

38

AVSS2

39

LDO2-C P

40

AVDD2

41

PVDD1

42

SPK- L+

43

SPK- L-

44

SPK- R-

45

SPK-R+

46

PVDD2

47

PDB

48

SPDIF-OUT

49

DGND

+AZA_VD D

ADOGND

C223 10u/6.3V 4

+5V_PVDD

+3V

[12] D MIC_DAT [12] D MIC_CLK

+AZA_V DD

_4

D

C

B

A

D

C

B

A

ADOGND

+5VA

C259 C428

0.1u/16V _4 10u /6.3V_ 4

Place next to pin 26

ADOGN D

C249 2 2u/10V 4 C255 10u/6.3V 4

R251 100K 5% 4

U15

Codec PWR 1.5V(ADO)

+1.5VA

DIGITAL ANALOG

*PJA138 K

*RB500 V-40

D22

2 1

RB500V -40

+5VA

MIC2-V REFO

SLEEVE

RING2

HP-L2 HP-R2

LINE1-L

D21 Q32

1 3

2

PD#

R228

C219

*10K_5 %_4 *1u/6.3V_4

Internal Speaker

Codec PWR 5V(ADO)

DIGITAL ANALOG

+5V

11

1 2

PB 1 0808T-600Y-N

40mil

5

HP-R2 HP-L2

LINE1-V REFO-L LINE1-V REFO- R MIC2-VRE FO

CODEC _VREF

INT_AM IC-VRE FO

3

2

1

C444 4 7u/6 3V 4 ADOGND

4

LINE1-R

Mute(ADO)

+AZA_V DD +1.5V

R232 1K_1%_4

5

Codec(ADO)

+1.5VA

C401 C220 10u/6.3V_4 0.1u/ 16

ADOGND

Place next to pin 40

Analog

R257 R256

BEEP_1

LINE1-V REFO- L R465

LINE1-V REFO- R R 476

4.7K 5% 4

R262 10K_5%_

AZ_CO DEC_R ST# [6]

AZ_CO DEC_S YNC [5]

DVDD IO

AZ_CO DEC_SD IN0 [5]

AZ_CO DEC_BIT CLK [5]

AZ_CO DEC_S DOUT [5]

PCBEEP C264

C268

100p/50V _4

R249 33 5% 4

C247 *22p/50V 4

C229 C230

0.1u/16V _4 10u/6.3V_4

9]

R238 *S 4

DMIC_ DAT DMIC CLK

Close to Codec

ALC255-CG

1.6Vrms

Place next to pin 9

Low is power down amplifier output

PD#

+3V

+1.5V

R240 *S 4

R243 22 5% 4

C241

10p/50V _4

SLEEVE [ 19]

RING2 [ 19] HP-L3 [19]

HP-R3 [19 ]

2 *AZ572 5-01F.R7G 2 *AZ572 5-01F.R7G

HP-L3 HP-R3

R478 2 2K 5% 4 R477 2. 2K 5% 4

D10 1 D9 1

R466 62 1% 4 R244 62 1% 4

C423 4 7u/6 3V 4

. _ _ _ _ V _ A N _ - C M T C

_ _

_ _ _ _ _ _

4

_

_ _

. _ _

_ _ _ _ _

_ _ _

_ _

_

_ _ _

. . _

_ _

. . _

_ _ L Y 6

L8

0 0

_

R SPK

V

, ,

C214

0.1u/16V _4

TP19

ADOGND

Digital

+5V

AZ CODEC RST#

AMP_M UTE# [21]

1 2 3 4

1

0.1u/16V 4

C257

0.1u/16V _4

AZ_SDIN0_R

14

SPKR [5]

PCBEEP _EC [21]

Universal Audio Jack HEADPHONE/MIC/LINE combo (ADO)

SP3=SD_CLK=MS_D0

4 3

R226

Q15B

10K_5%_4

1 6

SSM6N43FU

PCIE_LAN_WAKE#_R

For RTL8411B Place 0.1uF,CAP close to each VDD33 pin -- 11,32,

CLK_LAN_REQ#

60 MILS

+3V_S5

R 9

Descripiton

LAN_MX1+ LAN MX1LAN_MCT2 LAN_MX2+ LAN MX2LAN_MCT3 LAN_MX3+ LAN_MX3-

TF height limit = 2.4mm

Cloudbook Vend er

FCE

PSK

BOT

DB0LL1LAN00

DB0X81LAN01

DB0Z06LAN00

LANVCC

C178

C210 C189 C177 C386

C403 C407

0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 1u/6.3V_4 0.1u/16V_4

Descripiton

TRANSFORMER LL1 LAN 24P(NS892407)

TRANSFORMER X81 GIGA LAN (A-8300G)

TRANSFORMER Z06 LAN 24P(GST5009B LF)

TF height limit = 4mm

EJ series Vender

LANVCC

LAN_MX1+ LAN MX2+ LAN_MX2LAN_MX1LAN MX3+ LAN_MX3-

C307 EJ@1000p/3KV_1808

_

_ 0-

Close to Pin20

C10

VDD10

0.01u/50V_4

LAN MX0+

MDI_0+ MDI 0-

MDI_1+ MDI 1-

MDI_2+ MDI 2-

MDI_3+ MDI_3-

B B

[3] PCIE_LAN_WAKE#

[3] CLK_PCI E_LAN_REQ#

A

close to each VDD10 pin-- 3, 8, 33, 46

40 mils (Iout=1A)

*S 6

RTL8411B (LDO mode)

REGOUT

40 mils (Iout=1A)

R174

24 23 22 21 20 19 18 17 16 15 14 13

1 2 3 4 5 6 7 8

9 10 11 12

4

Size Document Number

LAN/CRD COMBO - RTL8411B

Date: Tuesday, March 21, 2017

Sheet 15 of 34

5 4 3 2 1

Rev

3A

C188 C203 C204 C187 10u/6.3V_4 0.1u/16V_4 *0.1u/16V_4 *0.1u/16V_4

+1.8V_S5

DB0Z8PLAN00

TRANSFORMER Z8P LAN (A-8300G-SLIM)

Quanta Computer Inc.

PROJECT :ZAJ

PSK

LANVCC

10 MILS

VDD33/18

C226 C227 *4.7u/6.3V_4 0.1u/16V_4

60 MILS

R168

C215 C176 C202

C200 C186

0.1u/16V_4 0.1u/16V_4 0.1u/16V_4

4.7u/6.3V_4 0.1u/16V

Q15A

10K_5%_4

Closed to Pin35 Pl ace close to pin 27

15

D

TAI - SOL

C

LAN & Card reader Combo (LAN)

C180

C179

VDD10

LANVCC

VDD10

C232

C238

5 4 3 2 1

*10p/50V 4

*10p/50V_4

*10p/50V 4

*10p/50V_4

CN2

C

ARD READER

(CRD)

SP8=SD_CD#

LAN_XTALI

Y2 25MHZ/30ppm

LAN_XTAL2

10p/50V_4

10p/50 4

SP1=SD_D1

SP2=SD_D0=MS_D1

C448 0.1u/16V 4

SP1=SD_D1 SP2=SD_D0=MS_D1 SP3=SD_CLK=MS_D0 SP4=SD_CMD=MS_D2 SP5=SD_D3=MS_D3 SP6=SD_D2=MS_CLK

VDD10

WAKE#/REQ# circuit(LAN)

U20

TCT1

NC #4 TD1+ MX1+ TD1- MX1TCT2

NC #3 TD2+ MX2+ TD2- MX2TCT3

NC #2 TD3+ MX3+ TD3- MX3TCT4

NC #1 TD4+ MX4+ TD4- MX4-

NS892407

1

CN4

1 2 3 4 5 6 7 8

MP1H01-R3401-7H

A

Layout :All term inati on signal shou ld have 30 mil t race

LAN_MCT0 LAN_MX0+ LAN MX0-

LANVCC

R234

+3V

25

PCIE R X2+ LAN C C224

PCIE_RX2-_LAN [3] PCIE_RX2+_LAN [3]

0.1u/16V 4

C225

27

VDD33/18

26

PCIE_RX2-_LAN_C

SP6=SD_D2=MS_CLK

15K_1%_4

SP8=SD C D#

SP7=SD_WP=MS_BS

EMI

SP7=SD WP=MS BS

PCIE LA N W AKE# R

SP4=SD CMD=MS D2 C445

ISOLATEB

CLK_LAN_REQ#

31 30 29 28

VCC_XD

SD_CLK_R

D

C

0 R247 *S_4

reserve for EMI

SP3=SD_CLK=MS_

SP2=SD D0=MS D1

SP1=SD_D1

MDIP0 REGOUT MDIN0 VDDREG AVDD10#1 ENSWREG_H MDIP1

DVDD10

MDIN1

DVDD33 MDIP2 ISOLATEB MDIN2 PERSTB AVDD10#2 CLKREQB MDIP3 D_WP/MS_BS MDIN3 VDD33/18 AVDD33#1 HSON DVDD33_CR

HSOP

RTL8411B-CG

VCC_XD

REGOUT LANVCC

VDD10 LANVCC

36 35 34

ENSWREG

33 32

SP5=SD_D3=MS_D3

SP6=SD_D2=MS_CLK

VCC_XD

+3V

C262 C263

4.7u/6.3V_4 0.1u/16V_4

R224

1K_1%_4

PLTRST# [6 ,12,16,17,21 ]

C212 1000p/50V 4

R225

1 2 3 4 5 6 7 8 9

10 11

MDI_0+ MDI_0-

MDI_1+ MDI_1MDI 2+

_2-

MDI 3+

_3-

+3V CR

C446

C447

R173 2.49K 1% 4 RSET

10 mils

U13

49

E_PAD

1

CD/DAT3

2

CMD

3

VSS

4

VDD

5

CLK

6

VSS#2

7

DAT0

8

DAT1

9

DAT2

10

CD

11

WP

SP5=SD_D3=MS_D3

SP4=SD CMD=MS D2

TP12

TP14

_

V_

_ _ _

_ _

_

_ _

_

_ _

D _

_ _

MDI _

_ _

_

S

MDI _ _

_

_ _ _

_

0

_4 _

_

LAN MCT1

LAN MX

_

8

_

J

_ 20

*S_6

*S 6

12

C246

CLK_PCIE_LANN [3] CLK_PCIE_LANP [3]

PCIE_TX2-_LAN [3] PCIE_TX2+_LAN [3]

10p/50V_4

156-1001902602

Tramsformer

5

6

5 R93

4

1

VCCA VCCB

2

GND EO

3

A B

PSD@N TS0101 GW

C217 TPM @10u/ 6.3V 4 C234 TPM @0.1u /16V 4 C201 TPM @0 1 u/16V 4 C222 TPM @0.1u /16V 4

U14

R236 *S 4

C190 TPM @10u/ 6.3V 4 C196 TPM @0 1u/1 6V 4

+3V_S5

*10K 5% 4

ODD@1u /6 3V 4 [email protected] 5% 4

PGND

PGND C413

+1.8V_S5 +3V_M2

U4

C426

R470

U32

VCCIN

VDD#2

I2C_DATA

GPIO7

I2C_CLK

VCCS

VCC#1

STXP

GPIO5

STXN

GPIO4

GNDA#2

VDD#1

SRXN

GPIO3

SRXP

GPIO2

VDDS VBU S VCCTXL VBUS_LDO

XO

VCCO

XI

+3V

20mil

R393 *S_4

CN5

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

ODD@4 . 7K_5% _4

CLKREQ SSD#

TPM NPCT650 (TPM)

[5,17,21] LP C_LAD 3 [5,17,21] LP C_LAD 2 [5,17,21] LP C_LAD 1 [5,17,21] LP C_LAD 0

[5,17,21] LPC_LFR AME#

[5] SOC_SER IRQ

[5] PC LK_TPM

[5,21] CLKRUN#

[6,12,15,16,17 ,21] PL TRST#

A

3/4 EMI request add 33p near T M IC

CLKRUN #

C233 TPM @33p/ 50V_4

C430

[email protected]/5 0V_4

[email protected]/5 0V_4 [email protected]/5 0V_4

+3V_M2

C339 10u/6.3V 4 C337 0.1u/16V 4 C338 0 1u/16V 4 C345 0.1u/16V 4 C346 0.1u/16V 4

TP35

[3] CL K_PCIE _SSD _REQ#

+1.2V_A SM

R471

+3V_ASM ODD TXP ODD_TX N

ODD RXN ODD_RXP +1.2V_A SM +3V ASM ASM_XO UT ASM_X IN

C409 C244 C239 C235 C248 C399

0.01u/50 V_4 0. 01u/50 V_4 0.1 u/16V_ 4 0.1 u/16V_ 4 10u /6.3V_ 4 *1 00u/6.3 V_12

R242 w/o GS@0 5% 4

ACCEL_ INT2 [ 18]

B

M.2 PCPIE & SATA SSD (NGF)

+601_V CC

SW7 - EN H - Enabled L - Standby Mode

DEW1 H - Long Duration X - NC (Long) L - Short Duration

Rev

3A

SATA_ TXP0_RD SATA TXN0 RD

SATA_R XN0_RD SATA RXP0 RD

Size Docum ent N umber

HDD/ODD/TPM NPCT650/Hole

Date: Tuesday March 21 2017 Sheet 16 of 34

5

4

3

2

1

RX1P RX1N GND#1 TX2N TX2P

DEW 2 EN DE2 DE1 VCC#1

SN75LV CP601RTJR

*0_5%_4 NASM0 -S6701 -TS40

[3] S ATA_ TXP0 [3] S ATA_TXN 0

[3] S ATA_R XN0 [3] S ATA_R XP0

1 2 3 4 5

6 7 8 9

10

Quanta Computer Inc.

PROJECT : ZAJ

C183 0 01u/50V 4 C185 0.01u/50V 4

C193 0 01u/50V 4 C197 0.01u/50V 4

ODD@25 MHZ/3 0ppm

PPAD

TX1P TX1N

GND#2

RX2N RX2P

GND#4 GND#5 GND#6 GND#7 GND#8

21 15

14 13 12 11

22 23 24 25 26

R449

ODD@ 12.1 K_1%_4

C395 ODD@10 p/50V _4

ASM XOUT

R461 *S 8

ODD@W 25X 10CLS NIG

WP

GND

EQ2

DE1 H - 14dB H - -2dB X - 0dB X - -4dB L - 7dB L - 0dB

EQ1

DE2 H - 14dB H - -2dB X - 0dB X - -4dB L - 7dB L - 0dB

DEW2 H - Long Duration X - NC (Long) L - Short Duration

68 70 72 74

VCC

HOL D

C405 C390

ODD@2. 2u/10 V_4 ODD@1u/6.3V _4

ODD @ASM1153

+3V ASM

ASM_X IN

C400

Y4 O [email protected] u/16V _4

8

7 4

1 6 5 2

3

67 69 71 73 75

SPI CS0 SPI_CL K SPI_DO SPI DI

+3V_ASM

U31

CS CLK DI DO

CB@132F 10-000000-A2-R

36 35 34 33 32 31 30 29 28 27 26 25

1 2 3 4 5 6 7

+3V ASM SPI_DI SPI_CLK +3V ASM SPI_DO SPI_CS0 +1.2V ASM

C381 C383 C382 C211 C182 10u/6.3V _4 1u/6.3 V_4 1u/6. 3V_4 0. 1u/16V _4 0 .1u/16V _4

+601_V CC

U12

+3V_ASM

C438 C429 C418

ODD@0. 1u/16V_4 ODD@10u/6 .3V_4 *OD D@100 u/6.3V _12

ODD_RXP ODD_RXN

ODD_TXN ODD_TXP

Close to ASM 1153

R241

VCC1. O

+5V

+3V_ASM

R472

TPM@NP CT650A BBYX

+5V_OD D

CLKREQ SSD#

TP34 TP33

+3V_M2

SATA_R XP0_C N SATA_R XN0_C N

SATA TXN0 CN SATA_ TXP0_CN

SATA_ TXP0_M2 SATA_ TXN0_M2

SATA_R XN0_M 2 SATA_R XP0_M2

SATA_D EVSLP0

HDD+M2 PWR

BADD SELECTION

0

EEh - EFh

1

7Eh - 7Fh

'1' - pin is left open. '0' - pin is pulled down.

60mil

2 5

Q36B Q36A

*PSD@S SM6N4 3FU

PLTRST# [6,12,15,16,17, 21]

+3V +6 1_VCC

R416 *S 4

C439

ODD@0. 01u/5 0V_4

SATA_DEVSLP0 [5]

HDD+M2 _PW R

ODD@4. 7u/6. 3V_4

11 12

NC1

LRESET/SPI_RST/SRESET

NC2

LPCPD NC3

NC4

NC7

Reserved

NC8 NC 6

R458 OD [email protected] 5% 4 8

9

R456 OD D@4 7K 5% 4 10

19 13

17 28

26 31

PCLK_TP M

C199 EJ@0 01u/50 _4 C191 [email protected]/50 _4

C184 EJ@0 01u/50 _4 C181 [email protected]/50 _4

co-layout

175 CB@0 5% 4 203 CB@0 5% 4

C192 CB@ 0.01u/50 4 C198 CB@ 0.01u/50 4

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20

GS1220 1-1011 -7H

CN11

10

9 8 7 6 5 4 3 2

1

+3V

+5V

+601_V CC

D

C

R172 4 .7K_5% _4 EQ2 R171 *4 7K 5% 4 R169 * 4.7K_5%_ 4 EQ1 R170 *4.7K 5% 4 R444 4. 7K_5%_4 DEW1 R447 *4.7K 5% 4

R220 * 4.7K_ 5%_4 DE1 R452 *4.7K 5% 4 R219 * 4.7K_ 5%_4 DE2 R453 *4 7K 5% 4 R217 4. 7K_5%_4 DEW2 R218 *4 7K 5% 4

R216 * 4.7K_ 5%_4 EN R 451 4.7K 5% 4

LPC_LFRAME # 20 SOC SERIRQ 27

R351 PSD@0 5% 4 R333 PSD@0 5% 4

C314 PSD @0 0 1u/50V 4 C312 PSD @0.01 u/50V 4

R361 SSD@ 5% 4 R362 SSD@ 5% 4

C325 SSD @0 1u/50V 4 C326 SSD @0. 1u/ 50V 4

R358 PSD@ 5% 4 R359 PSD@ 5% 4

C323 PSD@0 1u/50V 4 C324 PSD@0. 1u/50V 4

co-layout

[5] NGFF_S ATA_DE T#

[3] PCIE_RX1-_ SSD

[3] PC IE_RX1 +_SS D [3] PC IE_TX1 -_SSD

[3] P CIE_TX 1+_SS D

[3] S ATA_R XP1

[3] SATA_RXN1

[3] SA TA_TXN1

[3] SATA_TXP1

[3] P CIE_RX 0-_SS D [3] P CIE_RX 0+_SS D

[3] PCIE_TX0-_ SSD [3] P CIE_TX 0+_SS D

*S_4

LAD3 LAD2/SPI_IRQ LAD1/MOSI LAD0/MISO LFRAME/SCS SERIRQ LCLK/SCLK

CLKRUN/GPIO04/SI NT

CN16

18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

ODD@ 18 pi n conn

+3V_ASM

TP16

PP

GPX/GPIO2

GPIO1/SCL

SDA/GPIO0 GPIO3/BADD

TEST

4 TPM_PP 3 30

29

TPM_BA DD

5 2

7 10 11 12 25

15 18 21 24

LPC_LA D3 LPC_LA D2 LPC LAD1 LPC_LA D0

S5 S0

+3V_M2

R70 * 10K 5% 4

R490 R484

SATA_D EVSLP 1 [5]

*PSD@1 0K_5% _4 *PSD@10 K_5%_ 4

CLK_P CIE_SS D_RE Q#

C391 ODD @0.1u/16V 4 C419 ODD @0.1u/16V 4 C389 ODD @0 1u/1 6V 4 C398 ODD @0.1u/16V 4 C414 ODD @0.1u/16V 4

+1.2V_A SM

C388 ODD @0.1u/16V 4 C406 ODD @0.1u/16V 4 C404 ODD @0 1u/1 6V 4 C422 ODD @0.1u/16V 4 C387 ODD @0.1u/16V 4 C392 ODD @0 1u/1 6V 4

+5V_OD D

co-layout

R252 CB@0 5% 8

R260 EJ@0 5% 8

16

D

C

+3V_ASM

C385 [email protected]/1 6V_4

Close to pin 10/20 of IC

_ _

_ _ _

_ _

. V V _ _

. V V 2

. _

R _ _

R _ _ _ _

V_

V_ _ _ _ . _

_

_ _

_ _ 0 _ _

. _ _ . _

_ _ _ _ _

_ _ _

_

_ . _ . _ _

_ _

. _ _

_

_ _

_

. _ _ _ _ _

. _ _ _ _ _ _

. _

_ _

_

_ _

. _ . _

_

_ _

_ _ _ _

_

_ _

. _

_

0_ _

.0 _

0 _

_ _

0_ _

.0 _

P 0 _

, ,

PSD@10 K_5%_ 4

CLKREQ_ SSD#

+1.8V_S 5

A

Close to ASM 1153

SATA_ TXP0_C SATA_ TXN0_C

SATA_R XN0_C SATA_R XP0_C

DEW 2 EN DE2 DE1

6 R221

Internal 1.2V voltage (Switching)

>40mil

1 2

L10 ODD @4.7u H_3.2 x2.5x1. 55 ODD@100 K_5%_ 4

+1.2V_A SM

C421

ODD@10 u/6.3 V_4

SATA_R XP0_R D SATA_R XN0_RD

SATA_ TXN0_RD SATA_ TXP0_RD

SATA_ TXP0_RD SATA_ TXN0_RD

SATA_R XN0_RD SATA_R XP0_R D

PCIE_R X1-_S SD_R PCIE_RX1+ _SSD _R

PCIE_ TX1-_SS D_C PCIE_ TX1+_SS D_C

SATA_R XP1_R SATA_R XN1_R

SATA_TXN1_C SATA_TXP1_C

[3] CLK_P CIE_SSDN [3] CLK_P CIE_SSDP

R47

ODD_RX P_C ODD_RX N_C

ODD_TX N_C ODD_TXP _C

C424 C427

C431 C437

4

3

2.5" SATA HDD (HDD) USB ODD Bridge (ODD)

CN12

2

1

C172 C173 C174 C236 C240 10u/6.3V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4

Rev

3A

Size Document Number

NGFF WiFi & BT

Date: Tuesday March 21 2017 Sheet 17 of 34

5

4

3

2

1

5

4

3

2

1

+1.8V_S5 +WL_VDD

17

NGFF_M.2 WiFi & BT (NGF)

+WL_VDD

U29

1

VCCA VCCB

2

GND EO

3

A B

NTS0101GW

6

5

4

+1.8V_S5

S0

R418 10K 5% 4

CLKREQ_WLAN#

+WL_VDD

D

C

B

A

D

C

B

A

PCIE_CLKREQ_WLAN#

[3] PCIE_CLKREQ_WLAN#

S5

C221 180p/50V 4

CN9

2 4 6

8 10 12 14 16 18 20 22

32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74

1 3 5 7 9

11 13 15 17 19 21 23

33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75

2 4 6 8 10 12 14 16 18 20 22

32 34 36 38 40 42 44 46 48 50 52 54 BT_EN 56 RF_EN 58 60 62 64 66 68 70 72 74

1 3 5 7 9 11 13 15 17 19 21 23

33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75

USBP4+ USBP4-

PCIE_TX3+_WLAN PCIE_TX3-_WLAN

PCIE_RX3+_WLAN PCIE_RX3-_W LA N

CLK_PCIE_WLANP CLK_PCIE_WLANN

R464 *DBG@0 5% 4

[3] USBP4+

[3] USBP4-

[3] PCIE_TX3+_WLAN [3] PCIE_TX3-_WLAN

[3] PCIE_RX3+_WLAN [3] PCIE_RX3-_WLAN

[3] CLK_PCIE_WLANP [3] CLK_PCIE_WLANN

[5] CLK_PCI_LPC

[5,16,21] LPC_LFRAME#

R489 R483

*10K_5%_4 *10K_5%_4

APCI0076-P001A

2 5

Q35B Q35A

*SSM6N43FU

PLTRST# [6,12,15,16,21] BT_EN [21] RF_EN [21]

LPC_LAD0 [5,16,21] LPC_LAD1 [5,16,21] LPC_LAD2 [5,16,21] LPC_LAD3 [5,16,21]

+3V

CLKREQ_WLAN#

CLK PCI LPC LPC_LFRAME#_C

+WL_VDD

30mil

R163 *S 6

_ _ _ _ _

_ _

_

,

CLKREQ_WLAN#

Quanta Computer Inc.

PROJECT : ZAJ

NBSW ON# [21]

5 4

Rev

3A

Size Doc ument Number

KB/TP/FAN/G-sensor

Date: T uesday, M arch 21, 201 7 Sheet 18 of 34

5

4

3

2 1

Quanta Computer Inc.

PROJECT :

ZAJ

4 3 2 1

[21] KB_BL_ LED

CN18

2

5

Q19B Q19A

GS@2N7002KDW

KBL@50591-00401 0 01

5

4

3

2 1

KEYBOARD (KBC)

CN14

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

50584 -0280N-V02

TOUCHPAD (T PD I2C/PS2 co-lay)

18

6

I2C4_ SCL_C

TPD->100kHz,TS=400Khz Intel design guide suggestion MCP PIN 10u. Per inch 3u TS=3x5inch 400kHz10~100u =2.4~0.4k. 100Khz 10~100u=9k~1k.

[21] TPCL K

[21] TPDATA

+3V_ S5

R258

10K_5%_4

+3V_S5

R259

10K_ 5%_4

R263 *S 4

C266 C270 C269

0.1u/16 V_4 0.22u/1 0V_ 4 0.1u/16V_4

10 mils

+TPVDD TPCLK TPDATA

I2C4 SDA C I2C4_SC L_C

MX0 MX1 MX2 MX3 MX4 MX5 MX6

MX7 MY17 MY16 MY15 MY14 MY13 MY12 MY11 MY10 MY9 MY8 MY7 MY6 MY5 MY4 MY3 MY2 MY1 MY0

MX0 [21] MX1 [21] MX2 [21] MX3 [21] MX4 [21] MX5 [21] MX6 [21]

MX7 [21] MY17 [21] MY16 [21] MY15 [21] MY14 [21] MY13 [21] MY12 [21] MY11 [21] MY10 [21] MY9 [21] MY8 [21] MY7 [21] MY6 [21] MY5 [21] MY4 [21] MY3 [21] MY2 [21] MY1 [21] MY0 [21]

D

C

B

A

D

C

B

A

CN15

1 2 3 4 5 6 7 8

51653 -0080N-001

+3V_ S5

ESD4

1 6 GND VDD 3 4

I2C4 SDA C

TPD_INT#

1 2 3

+TPVDD TPD_EN

2 3

10 15

5 12 13 16

D28

*AZ5725- 01F.R 7G

Touch PAD level shift I2C(TPD)

+1.8V_S5

*TVL ST23 04 AD0

U17

Vdd_IO NC#1 VDD

NC#2

R267

R268 R264 10K_5%_4

R261

10K_5%_4

TPD_INT#

R 53 3 3_5% _4

C25 180p

Q21A 2 K_1%_4 2 K_1 %_4

[5] PCH_TPD_ INT#

+3V

4

3

Q21B

1

6

SSM6N43F U

+3V

I2C4_SCL_C

I2C4_SDA_ C

+5V

[5] I2C4_SC L

[5] I2C4_SDA

Prevent ESD/EOS Layout near connector

CPU T

HERMAL SENSOR

(THM)

+3V

2

5

Q20B Q20A

2N7002K DW

+5V

20mil

R230

*S_4

R222 R229

R223

EJ@1 K_1%_4 EJ @10 K_5%_4

EJ@10K_ 5%_4

4 CN10

U23

+Vs Q16

[21] FAN1_RPM

FAN_PW M_Q

For EMI

+5V_FAN1

1 2 3 4

EJ@50278-00401-V01 C218 C216 *EJ@2 20p/50 V 4*EJ@220p/50 V_4

+3V

C280 C277

[email protected] u/16V_4 GS@10u/6. 3V_4

1 3

EJ@M ETR39 04- G

[21] FAN_PW M

TP39

G-sensor(ACS)

+3V

R231

2ND MBDATA

[21] 2ND_MBDATA

2ND_ MBC LK

[21] 2ND_MBCLK

5

1

SMBDATA

ALERT#

SMBC LK

GND

3

ALERT#

CB@G753T11U

2

Keyboard backlight (KBL)

+5V + 5V

C265 [email protected]/10 V_4

1

14

INT1 INT2

R266 GS@10K_ 5%_4

KBL@ 10K_5% _4

2

Q23

2

KBL@DDTC144 EUA- 7-F

ACCE L_INT1

[5] ACCEL_INTA

Q22

RES

ADC2

D7 1 GS@RB50 0V-40 ACCEL INT1 R

11

20mil

+5V KB

C273 C 279 KBL@ 4.7 u/6.3 V_4 K BL@0 .01 u/50 V_4

1

ACCEL_INT2_R

+3V

9

7 6 4

8

KBL@ PJA34 13 C242

*GS@2 2p/50V_4

D8 GS@RB 500V-4 0

SDO/SA0 SDA/SDI/SDO GND #1 SCL/SPC GND#2

ADC3

CS

ADC1

GS@L IS3D HTR

_

_ _ _ _

2

8 / _ _ _ _

_

-

D27 *AZ5725- 01F.R7G

+3V_S5

[21] TPD_INT#

[21] TPD_EN

2 2

ACCEL_INT1

[16] ACCEL_INT2

[6] CLK_SDATA [6] CLK_SCLK

to CPU to SATA HDD

50V_4

C352 [email protected] 1u/50V _4

CPU FAN (THM)

USBP0-_R

HOLE6 HOLE10

*O-EJ-KBL-1 *H-C122D122N

Rev

3A

+3VPCU

PWRLED # [21] SUSLED# [21] BATLED0# [21] BATLED1# [21]

USBP3+_R USBP3-_R

USBP2+_R USBP2-_R

HP_JD# [14]

SLEEVE [14]

RING2 [14]

HP-L3 [14] HP-R3 [14]

ADOGND

Size Document Number

USB/CARDREADER/LED

Date: T uesday, March 21, 2 017 Sheet 19 of 34

5 4

3

2 1

OCB

OUT

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

196332-34041-3

USB3_0_RXP_R 5

5 4

3

2 1

R167 * S 4

USB 3.0 (UB3)

[21] USBON #

19

10

USB3_0_TXN_R

9 8 7 USBP0+_R 6 USB3_0_RXN_R

C170 *1.6p/50V 4

C169 *1 6p/50 V 4

C159 0.1u/16V 4 C154 0.1u/16V 4

L3

3 4 2 1

*MCM2012B900 GBE

R165 *S_4

R161 0 5% 4

L2

3 4 2 1

*MCM2012B9 00GBE R158 0_ 5%_4

R157 * S 4

L1

3 4 2 1

*MCM2012B9 00GBE R153 *S_4

USB3_0_RXN_R USB3_0_RXP_R

USBP0+_R USBP0-_R

USBPWR1

USB3_0_TXN_R USB3_0_TXP_R

C161 C155 *1.6p/50V_4 *1.6p/50V_4

[3] USB3_0_RXN [3] USB3_0_RXP

[3] USBP0+

[3] USBP0-

[3] USB3_0_T XN [3] USB3_0_T XP

CN8

Shield

2UB4008-39 0101F

5 4 6 3 7 2 8 1 9

USBPWR1

USB3_0_TXP_R 1

2 3

Shield

StdA_S SRX-

GND

StdA_S SRX+

D+

GND_Dr ain

D-

StdA_SST X-

VBUS

StdA_SST X+

Shield

ESD3

I/O-1

I/O-6

VDD

GND#1

NC#1

NC#2

I/O-2

I/O-5

I/O-3

I/O-4

AZ1065-06F.R7G

+5V_S5

5

4

D

C

B

A

trace midth：100 mils

U7

D

C

B

A

C135 1u/6.3V_4

USBON#

C370

0.1u/16V_4

4

3

1

USB_OC1# [3]

USBPWR1

C145 C144 C359 470p/50V_4 0.1u/16V_4 100u/6.3V_12

IN

EN GND

2

5 8 5 8 5 8 5 8 5 8 5 8 5 8 5 4 9 4 9 4 9 4 9 4 9 4 9 4 9 4

SPAD1 S PAD3 SPAD2 SPAD4 SPAD5 SPAD6

*SPAD-C315NP *SPAD-C236N P *SPAD-C 236NP *SPAD-C236NP *SPAD-C177NP *SPAD-C177NP

HOLE3 HOLE4 CPU nut CPU nut CPU nut

G524B2T11U

USB PROTECTION DIODES FOR ESD. AS CLOSE AS POSSIBLE TO USB CONNECTOR PINS.

Quanta Computer Inc.

PROJECT : ZAJ

USBP3+_R USBP3-_R

ESD5

1 6 GN VDD 3 4

2 1 3 4

*MCM2012B900GBE

R271 *S_4

1 2 3

R272 *S 4

L7

2 1 3 4

[3] USBP3+

[3] USBP3-

[3] USBP2+

[3] USBP2-

+5V_S5

trace midth：100 mils

U18

C278 1u/6.3V_4

5

3 USB_OC1#

1

IN

EN GND

2

OCB

OUT

USBPWR2

C275 C274 C271 470p/50V_4 0.1u/16V_4 *100u/6.3V_12

USBPWR2 6 5 4

USBON# 4

G524B2T11U

*TVL ST23 0 4 AD0

USBP2+_R USBP2-_R

Enable: Low Active /2.5A GMT:AL000524007 EMS:AL005203001

USB 2.0/LED/AUDIO JACK DB (UB2)

USBPWR2

CN17

*MCM2012B900GBE

R273 *S_4

HOLE(OTH)

HOLE2 HOLE12 HOLE11 HOLE8 HOLE5 HOLE15 HOLE14 HOLE13

*HG-EJ-AP-1 *HG-C354D220P2 *HG-C 354D220P2 *H G-C315D165P2 *HG-Z8P-1 *HG-C354D126P2 *HG-C3 15D165 P2 * HG-TC315BC236D95P2

7 6 7 6 7 6 7 6 7 6 7 6 7 6 7 6

8 9

HOLE1

*H-C236D94P2

HOLE9

WLAN nut

_

. _

_ _ _ _ _ _ D _

HOLE7

USB3_0_TXN_C USB3_0_TXP_C

Enable: Low Active /2.5A GMT:AL000524007 EMS:AL005203001

USB 2.0 (UB2)

R270 *S 4

L6

Stitch cap (EMC)

+TYPEC_VBUS_C

+5V_S5

R96

R49

*S 4

TYPEC_CHG_HI

8

LINE-1 LINE-2 LINE-3 LINE-4

GND LINE-6 LINE-5

LINE-8 LINE-7

ESD1

1 6 GND VDD 3 4

9 8

7 6

1 2

3 4

5

USBP125810 CC2

6 5 4 Rev

3A

Size Document Number

USB_Type C_25810

Date: Tuesday, March 21, 2017

Sheet

20 of 34

1

*TPC@AUSB0181-P101A

[email protected]

Amazing：BC104508Z00 PJT

：

BC605S8QZ00 INPAQ

：

BC38109LZ00

5 4 3

TPC@TVL ST23 04 AD0

5 4 3

USB TYPE-C (UB3)

trace midth：150 mils

2

+5V_S5

TYPEC CHG

Vendor suggest input cap 120u

C394 TPC@100u/6.3V 12 C53 TPC@10u/6.3V 4

C52 TPC@10u/6.3V 4

[21] EC_TypeC_EN

+TYPEC_VBUS_C

U3

IN1#1 IN1#2 IN2 AUX

EN CHG

CHG_HI REF

REF_RTN GND#1

TPC@TPS25810RVCR

D

C

B

A

2 3 4 5

6 7

15 14

11 13

1 20 19 18 17 16

21

C42 TPC@10u/6.3V 4 C54 TPC@100p/50V 4

C43 TPC@1000p/50V 4

MI

R68

*S 4

R78

*S 4

OUT#2 OUT#1

CC1 CC2

FAULT

LD_DET

UFP POL

AUDIO

DEBUG

PwPd

25810_CC1 25810 CC2

25810_FAULT# 25810_LD_DET# 25810_UFP# 25810_POL# 25810_AUO# 25810_DBG#

+TYPEC_VBUS

25810_FAULT# 25810 LD DET# 25810_UFP# 25810_POL# 25810 AUO# 25810_DBG# TYPEC CHG TYPEC_CHG_HI EC_TypeC_EN

+3V_S5

R69

*TPC@100K 5% 4

R80

TPC@100K 5% 4

R79

*TPC@100K 5% 4

R77

TPC@100K 5% 4

R76

TPC@100K 5% 4

R65

TPC@100K 5% 4

R51

TPC@100K 5% 4

R50

TPC@100K 5% 4

R56

TPC@10K 5% 4

Close to connector

USB_OC0# [3] TypeC_HPD#

[4]

TPC@AON7401

R97 TPC@10K_5%_4

1 2 3

25810_REF

10

25810 REF RTN 9

R48 TPC@100K_1%_4 12

trace midth：150 mils

+TYPEC_VBUS

C28 [email protected]/16V 4 C36 [email protected]/16V 4

C55 [email protected]/16V 4 C51 [email protected]/16V 4

+5V_S5

C343 [email protected]/25V 4 C344 [email protected]/25V 4

C350 TPC@100p/50V 4 C342 TPC@1000p/50V 4

EMI

+TYPEC_VBUS

D3

[email protected]

Q7

3

5 2

1

25810_UFP#

2

USB3_1_TXP_CN USB3 1 RXN

USB3_2_TXP_CN USB3 2 RXN

25810_UFP#_G2

R94

Q8 TPC@PJA138K

USB3_1_TXN_CN USB3 1 RXP

USB3_2_TXN_CN USB3 2 RXP

TPC@100K 5%_4

C75

[email protected]/25V_4

USBP1+

25810 CC1

CN1

SSTXp1 SSTXn1 SSRXp1 SSRXn1

SSTXp2 SSTXn2 SSRXp2 SSRXn2

Dp1 Dn1 Dp2 Dn2

CC1 CC2

SBU1 SBU2

TPC@10K_5%_4

25810_UFP#_G12

Q6 TPC@PJA138K

ESD2

[3] USB3_1_TXP [3] USB3_1_TXN [3] USB3_1_RXP [3] USB3_1_RXN

[3] USB3_2_TXP [3] USB3_2_TXN [3] USB3_2_RXP [3] USB3_2_RXN

[3] USBP1+

[3] USBP1-

_

_ _

_ _ _ _ _

_ _ _

_ _ E _ _

_ _ _

_ _

_ _ _ _

_

_ _

_ _ _ _ _ _ _ _ _ _

_

_ _

_ _ _ _ _ _

_ _ _

_

_ _ _ _

_ _

_ _ _ _

[21]

EC_TypeC_CHG_HI

USB3 1 TXP CN USB3_1_TXN_CN USB3 1 RXP USB3_1_RXN

USB3_2_TXP_CN USB3 2 TXN CN USB3_2_RXP USB3_2_RXN

USBP1+ USBP1USBP1+ USBP1-

25810_CC1 25810 CC2

TP4 TP3

A2

A3 B11 B10

B2

B3 A11 A10

A6

A7

B6

B7

A5

B5

A8

B8

A4 B4 A9 B9

A1 A12 B1 B12 1 2 3 4 5 6

VBUS#1 VBUS#3 VBUS#2 VBUS#4

GND#1 GND#2 GND#3 GND#4 GND#5 GND#6 GND#7 GND#8

NC#1 NC#2

+TYPEC_VBUS

C340 [email protected]/25V 6 C349 [email protected]/25V 6 C347 [email protected]/25V 6 C341 [email protected]/25V 6

1

D

C

B

A

Quanta Computer Inc.

PROJECT :ZAJ

VccD SW

BT_EN

PCH SLP SUS#

GPIO

2

Quanta Computer Inc.

PROJECT : ZA J

SPIVCC ON

SP@ socket P/N: DFHS08FS023 only for A-TEST

5 2

Q33A Q33B

*SSM6N43FU

+3V

R443

10K_5%_4

HWPG

5 4 3 2 1

5

6

2

RB500V-40

2

*RB500V-40

2

*RB500V-40

2

*RB500V-40

2

*RB500V-40

2

*RB500V-40

CIR

CRX0/GPC0 CTX0/TMA0/GPB2(3)

DAC4/DCD0#/GPJ4(3) DSR0#/GPG6 GINT/CTS0#/GPD5 PS2DAT1/RTS0#/GPF3 DAC5/RIG0#/GPJ5(3) PS2CLK1/DTR0#/GPF2 TXD/SOUT0/GPB1 RXD/SIN0/GPB0

*TME-532W-Q-T/R

W25Q80BW SSIG

VIN VO UT

GND

EN NC

WP G ND

4 1

2

R233

2N7002K

100K_5%_4

Battery Disable (FSW)

[22] BI#

6

SW 2

5

20

MILS

5

4

C393 1u/6.3V_4

Rev

3A

PWM0/GPA0 PWM1/GPA1 PWM2/GPA2 PWM3/GPA3 PWM4/GPA4 PWM5/GPA5

TACH0A/GPD6(3)

TACH1A/TMA1/GPD7(3)

TMRI0/GPC4(3) TMRI1/GPC6(3)

PWRSW/GPE 4

RI1#/ GPD 0(3 )

RI2#/GPD1

Size

Document Number

KBC IT8987E_CX

Date: Tuesday March 21 201 7 Sheet 2 1 of 34

20

MILS

W25Q80EW SSIG GD25LQ80BSIGR

3 2 4 1

TP20 TP24

KBRST# 4

16

113 123

80

119

33

AKE5GGN0N00 AKE5GZN0Q00

1M 1M

NBSWON#

WND GGD

R459 2.2 5% 6

CS CLK SI DO

66 67 68 69 70

76 77 78 79

44

0.1u/16V_4

R493 10 5% 4

colsed to EC pin within 100 mils

D24

100K_5%_4 RB500V-40

C416 1u/6.3V_4

1 6 5 2

SPI W P# 3

SPI_CS0#_UR_M PCH SPI CLK E PCH SPI SI EC PCH_SPI_SO_EC

EXTERNAL SERIAL FLASH

+3V_RTC +3VPCU

R455 R454

*0_5%_4 *0_5%_4

R457

*10K_5%_4

RING#/PWRFAIL#/CK32 KOUT/LPCRST#/GPB7

ADC0/GPI0(3) ADC1/GPI1(3) ADC2/GPI2(3) ADC3/GPI3(3) ADC4/GPI4(3)

A/D D/A

TACH2/GPJ0(3)

GPJ1 (3) DAC2/TACH0B/GPJ2(3) DAC3/TACH1B/GPJ3(3)

R445 R 415

3.3K_5%_4 3.3K_5%_4 U28

R448 *S 4

1.8V_LDO

TP23

TP25

SM BUS

1.8V_LDO

U30

Reserve power on switch for test (MP remove)

SW 3

VSTBY_FSPI

680_LDO

R417

C380

3.3K_5%_4

0.1u/16V_4

8

VCC

7

SPI_HOLD#

HOLD

15

MILS

R450 *S 4

680_LDO

+3V_LDO_EC

R462

SPI ROM(KBC)

Power_Auto_Recovery

VSTBY_FSPI

IT8987E/CX

LQFP

PWM

UART port

WAKE UP

PROCHOT_EC

TP17

WRST#

[18]

MX0

[18]

MX1

[18]

MX2

[18]

MX3

[18]

MX4

[18]

MX5

[18]

MX6

[18]

MX7

Battery

Thermal sensor

20

MILS

SM Bus 1

SM Bus 2

SM Bus 3

SM Bus 4

ADC5/DCD1#/GPI 5(3) ADC6/DSR1#/GPI6(3) ADC7/CTS1#/GPI 7(3) RTS1#/GPE5 PWM7/RIG1#/ GPA7 DTR1#/SBUSY/GPG1/ID7 CTX1/SOUT1/GPH2/SMDAT3/ID2 CRX1/SIN1/SMCLK3/ GPH1/ID1

[email protected] 5% 4 CB@4 7K 5% 4

H_PROCHOT#

[6,22,26 ]

Q17

C410 C20 9 C440 C4 15 C40 8 C20 5 C20

0.1u/16V_4 0.1u/16V_ 4 0.1u/16V_4 0.1u/16V _4 0.1u/16V_4 0.1u/16V_4

0.1u/16 V

GPJ7 GPJ6

IT8987E/CX

KSO0/PD0 KSO1/PD1 KSO2/PD2 KSO3/PD3 KSO4/PD4 KSO5/PD5 KSO6/PD6 KSO7/PD7 KSO8/ACK# KSO9/BUSY KSO10/PE KSO11/ERR# KSO12/SLCT KSO13 KSO14 KSO15

Vender Size Quanta P/N Vender P/N

SPI ROM

1.8V

KBMX

CLOCK

C252

0.1u/16V_ 4

2 1

L5

BLM15AG121 SN1D

C425 1 80p/50 V 4

[6,12,15,16,17] PLTRST#

[5] CL K_P CI_EC

[5,16,17] LPC_L FRAME#

D

C

B

A

+3V_S5

[5,16,17] LP C_LA D0 [5,16,17] LP C_LA D1 [5,16,17] LP C_LA D2 [5,16,17] LP C_LA D3

[18]

KB_BL_LED

[6] DNBSWO N#

Output for type-c Apling ridge

reset timming"Low " Active

[20]

EC_TypeC_EN

[6]

SUSB#

[6]

EC_PWROK

[12] PCH_BL ON_ EC

TP22

[5]

ME_WR#

[14]

AMP_MUTE#

TP26

[22] ACIN

[22]

TEMP_MBAT#

TP43

[14]

PCBEEP_EC

[6]

THERMTRIP#

[22] AC_Prot ect

MBCLK [22] MBDA TA [22]

2ND_MB CLK [18] 2ND_MBDATA

[18 ]

TP15

LID# [ 12,13]

Prevent ESD/EOS Layout near EC

EC_FPB ACK# [ 12]

TPCLK [18] TPDATA

[18]

PWRLED#

[19]

BATLED1#

[1 9]

SUSLED#

[19]

BATLED0#

[1 9]

MAINON

[23,24,2 5,28,29]

FAN1_RPM [18]

SUSON [25 ]

R269 33 5 _4

C276 180p/50V_4

LAD0/GPM0(3) LAD1/GPM1(3) LAD2/GPM2(3) LAD3/GPM3(3) LPCRST#/GPD2 LPCCLK/GPM4(3) LFRAME#/GPM5(3)

LPCPD#/GPE6

GA20/GPB5(3) SERIRQ/GPM6(3) ECSMI#/GPD4(3) ECSCI#/GPD3 WRST# KBRST#/GPB6(3)

MBCL K MBDA TA 2ND_MB CLK 2ND MBDATA

SLP _S0 IX#

R204 33 5% 4

C195

180p/50V

D6

VARISTOR

TP21

TP28

GPC6

WRS T#

R250 33 5 % 4

C256 180p/50V 4

110 111 115 116 117 118

85 86 89 90

24 25 28 29 30 31

47 48

120 124

10

9 8

7 22 13

6

17

126

5 15 23 14

C402 * 0 1u/16 V 4

BI_GATE

FSCK/GPG7 FSCE#/GPG3 FMOSI/GPG4 FMISO/GPG5

TS EN C

AC_Protect

SPI ENABLE

[12] TS_E N

88 81 87

109 108

71 72 73 35 34

122

95 94

105 101 102 103

56 57 32

100 125

36 37 38 39 40 41 42 43 44 45 46 51 52 53 54 55

Prevent ESD/EO Layout near EC

JTE1CQR

Q31

PJA138K

HWPG(KBC)

[28] HWPG_ 1.5V [28] HW PG_1.8 V_S5

[25] HWPG_ 1.35VSUS

[24] HW PG_1.0 5V

[26]

IMVP_PWRGD

[28] HW PG_1 .24V_ S5

G9090-180T11U

C396

2.2u/10V_4

R248 2. 2 5% 6

4

LPC

+3V_RTC

R446

100K_5%_4

2

C384

*0.1u/1 6V _4

SW 1

TME-532W-Q-T/

1

D20

1

D18

1

D15

1

D17

1

D16

1

D19

Prevent ESD/EOS Layout near EC

D

C

B

A

CLK_PCI_EC

R467

*22_5%_4

C420 *10p/50V_4

R214 33 %_4

C194 180p/50 V 4

+3V_E C

C251

0.1u/16V_4

Prevent ESD/EOS Layout near EC

KSO16/SMOSI/GPC3 (3) KSO17/SMISO/GPC5 (3) PWM6/SSCK/ GPA6

SSCE0#/GPG2 SSCE1#/GPG0

1 2

L12

BLM15AG121SN1D

C267

0.1u/16V_4

ECAGND

12

MILS

+3V_LDO_EC

10K 5% 4

4.7K 5 % 4 4 7K 5% 4 *10K 5 % 4

CB@10K 5% 4

100K 5 % 4

100K_5%_4

100K 5 % 4

10K 5% 4

+3V

VSTBY_FSPI_R

VSTBY_FSPI

R205 2.2_ 5%_6

+3VPCU_EC

+A3VPCU

+3VPCU_ECPLL

1

3

5 4 3 2 1

PU/PD (KBC)

SPIVCC_ON

NBSWON#

MBCL K MBDA TA

GPC6

MAINON

SUSON

RSMRST# EC PW ROK

CLR_CMOS

S5 ON

2ND_MB CLK 2ND MBDATA

PROCHOT_EC

EC(KBC)

+3VPCU_EC and +3V_RTC minimum trace width 12mils.

21

+3VPCU_EC

SB_ACDC

[6,22]

BT_EN [17]

D/C# [22] USBON# [19 ]

EC_TypeC_CHG_HI

[ 20]

CLKR UN# [5,16 ]

U16

L4

BLM15AG121 SN1D

(For PLL Power)

C208

0.1u/16V_4

R213

R212

R206 R211 R202

R207

R480

R215

R210

R481

R254

R265

R177 R176

2

_ _

. _ _

_ _ _ _

_ _

6

_ _ _

_5

_ _ _ _

_

_ _ _ _ _ _ _ _ _ _

_ _

_ _ _ _4 . _ _

_ _

C 9 _ _

S

_ _ _ %

_ _ _

_

]

. _

R

_ _

E

_ _ _ C

_ _ _

_ _ , ,

ICMN T

ICMNT

[22]

C272 10u/6.3V 4

ECAGND

S5_ON [2 3,28

TP27

VNN_ON [26]

SYS_HWPG [23]

PANEL_LED_EN

[30]

CLR_CMOS

[6]

[5] IRQ_ SERIRQ

[6]

PCH_SUSPWRDNACK

[5] SIO_EXT_SCI#

PWUREQ#/BBO/SMCLK2 ALT/GPC7(3)

VSTBY_FSPI

Pin124 is a board ID for Cloud book (PD) , EC has internal PU for EJ series

107

NBSWON#

18 21 HWP G

112

NBSWON# [18 ]

SUS C# [6]

RSMRST#

[6]

SYS_SHDN#_R

2 R23 7 *S_4 128 R208

33_5%_4

SYS_SHDN# [23,29]

TPD_INT#

[18]

Prevent ESD/EOS Layout near device

C207

180p/50V_4

SM BUS ARRANGEMENT TABLE

RF_EN [17]

SMCLK0/GPB3 SMDAT0/GPB4 SMCLK1/GPC1 SMDAT1/GPC2

PECI/SMCLK2/GPF6( 3)

SMDAT2/PECIRQT#/GPF7(3)

PS/2

PS2CLK0/CEC/TMB0/GPF0

PS2DAT0/TMB1/GPF1

PS2CLK2/GPF4 PS2DAT2/GPF5

TPD_EN [18]

MY0 MY1 MY2 MY3 MY4 MY5 MY6 MY7 MY8 MY9

TP18

PCH_SPI_CLK_E C SPI_CS0#_UR_ME PCH SPI SI EC PCH_SPI_SO_EC

SPIVCC_ON

TS_EN_C

[18] MY16 [18] MY17

[18] FAN_PW M

[18] [18] [18] [18] [18] [18] [18] [18] [18]

[18] [18] MY10 [18] MY11 [18] MY12 [18] MY13 [18] MY14 [18] MY15

*0_5%_ 4 PR80

316K_1 %_4

PR77

PR73

PJ5

8 7 6 5 4 3 2 1

50458-00801-V02

24737_ILIM

PR202 10_5%_6

24737

PR203 7.5_5 %_6

24737_ C MPIN

4

CMPIN

SRN

12

PR55 *S_4

10

24737_ SRP

2473 7_SR N

SRP／SRN

PC44 PC20 4 PC201 PC214

2200p/50V_4 10u /25V_8 10u/25V_8 *1 0u/25 V_8

24737

PC43 *100p/50

24737 BM#

_4

11

TEMP_MBAT# [21]

+3VPCU

Date: T uesday, M arch 21, 201 7 Sheet 22 of 36

5

4

3

2 1

Check PU High with HW side

+1.8V_S5

PR50

*100K _5% _4

H_PROCH OT# [6,2 1,26]

2

PQ8 2N7002K

For BATT Only

R1

R2

UMA-45W 51K 100K

[21]

PR201 PR61

*100K _5% _4 00K_5% _4

PC57 PC56 PC53 *47p/50V_4 *47p/50V_4 100p/50V_4

PD6 PD5 PDZ5.6 B PDZ5.6B

PC200

0.1u/50 V_6

PR69 *4.7_5 %_6

PC52 *680p/ 50V_ 6

24737 BM#

2

PR66 *0_5%_ 4

24737_ CMP OUT

AC_Pro tect

MBCL K [21]

PQ10

MBDATA [21 ] *2N7002K

[21] ICM NT

24737_ CMPO UT

3

PR54 51K_1 %_4

R2

R1

PR75 PR74

PR20 0 PC58

100_1 %_4 100_1%_ 4 100K_1%_4 0.01u/50V_4

4-Cells Others

bq24707A 0／0 10／7.5

bq24737 10／7.5 10／7.5

REGN MAX voltage 6.5V V_ILIM=20*(VSRP-VSRN)=20*Ichg*Rsr =0.793V for 3.965A current limit

Pin10 ILIM=0.793V Rsr = 0.0 1ohm

Quanta Computer Inc.

PR45 *S_4

24737_A CN

24737 ACP

PR46

3

4

*S_4

PR78

0.01_ 1%_061 2

PR83 PR82 *S_4 *S_4

5

6

PL10

6.8uH_7x7x3

1

2

5

PQ9B PQ9A 2N7002KDW 2 N70 02K DW

+3VPCU

PR81 10K_5 %_4

PR62 10K_5 %_4

BAT-V

BI# [21]

PHASE

LODRV

GND#1

SRP

5

4

3

2 1

22

PQ17 TPCA8109

+VIN

3 2

5

PC213 PR51 *10u/25 V_8 10K_5%_4

PQ7 2N7002 K

BAT-V

1

2

1

D

C

B

A

D

C

B

A

PC19 0 PR1 87

0.1u/ 50V_6 220K_1%_4

PC55 PD2

0.1u/5 0V_6 P4SMAF J20 A

PD4 1N4148WS

recommend 200mA at least.

PR71 *S_6

PC206 PC49 PR49

0.1u/50V_6 2200p/50V_4 33K_1%_4

2

+VIN

PU2

BQ2473 7RG RR

SDA

SCL

BM

CMPOUT

ILIM

PR188 220K_1%_4

2

1

PQ16 IMD2 AT10 8

24737_ACP

24737_ACN

PC46 PC50 PC45

0.1u/5 0V_ 6 0.1u/50V_6 0.1u/5 0V_6

D/C# [21]

PR189 *S_4

16

24737_REG N

PR72 *S_6

17 24737_ BST

18

24737 DH

19

24707_LX

15

24737_DL

14

13

24737_ACDET 6

24737 VCC

20

PC51

0.47u/2 5V_ 6

5

8

9

PR67

63.4K_1%_4

PR68 PC59 11K_1%_4 1u/16V_6

ACDET

REGN

VCC

BTST

HIDRV

ACOK

PD7 PC48 PC209 RB50 0V-40 2200p/5 0V_4 10u/25V_8

PQ20

AON7410

PR58 20_5%_1 2

PR70 *S_4

MBDATA

MBCLK

PR76 *S_4

PC54

0.047u/50V_6

4

PQ21

AON7410

4

PC61

0.1u/25V_4

SRP

PC60

0.1u/25 V_4

SRN

PC62

0.1u/25V_4

D

G

S

D

G

S

C

_

V

_

_ _

1

_

TEMP_MBAT#

PR79 1M _5%_4

100 1% 4

PROJECT :

Size Doc umen t Number

Charger(BQ24737RGRR)

ZAJ

Rev

3A

PQ6

VA1 TPCA8109

3 2

VA2

PD3 PR44 SV1040 0.02_1%_061 2

1

5

3

CB@50278-006T 1-001

[6,21 ] SB_A CDC

Double Check ADP-IN Connector with ME

PJ1

4 3 2 1

EJ@ I2504P1H02-RB- NH

PC37 PC38

0.1u/50 V_6 2200p/50 V_6

PJ2

[21] ACIN

VA1

6 5 4 3 2 1

PR57 *0_5% _4

+3VPCU

5

4

3

2

1

23

[12,22,25,26,27,29,30] +VIN [12, 13,14,16,18,29] +5V

[6,12,13,14,19 ,21,22,24,28] +3VP CU [6,19,20,25,26,2 7,30] +5 V_S5

[28] +5VPCU [4,5,6, 12,13,14, 15,16,17,18,21,24,25, 26,28,29] + 3V [29] VL [5,6, 7,15,16,18, 20,21,28] +3V_S5

+5VPCU +5VPCU

Do Not add test pad on LDO pin

PC85

4.7u/6.3 V_4

PU5

+VIN

PR125 *S_4

+VIN

+

PR171 *S_4

JP1 *S 3720

3VPCU_VIN

PR102 PC88

SY8286 BBST_S

2 3 4 5

7

1 S Y8286B BST

D

C

B

A

D

C

B

A

10K 1% 4

IN#1

LDO IN#2

IN#3 IN#4

GND#1

LDO=3.3V/100mA

10K_1%_ 4

SY8286BPG 9

11

Vih=0.8V

PR98 150K_1 %_4

SY8286 BEN 12

PC2 *0.1u/1 6V_4

*S 4 100K 1% 4

PR93 499K_1 %_4

PR4 *S_4

SY8286 BLDO

TDC : 5.25A TDC : 2.25A PEAK : 7A PEAK : 3A Width : 220mil Width : 100mil

PC177 PC178 1u/25V_4 1u /25V_4

+5V_S5 +5V

PG

EN2

EN1

NC#2

PU11 SY8288 CRAC

BS

LX#1 LX#2 LX#3

NC#1 NC#3

OUT

FF

+VIN

SYS S HDN#

[21,29] SYS_SHDN#

680_LD O

PR15 *S_6

680_LD O

[21] 680_LDO

PL3

*S_6 0.1u/25V _4 2.2uH_7 x7x3

6 S Y8286B SW 1 2 19 20

PR17

13

PC179 PC181 14 10u/6.3V _6 0.1u/1 6V_4

4

PC174

0.1u/16V _4

3

VOUT1#1 VOUT1#2

8 9

11 15

5

PC182 PC180

0.1u/16V _4 10u/6.3 V_6

PR174 *S_4

MAINON

OUT2#1 OUT2#2

PU13

AOZ1331DI

VBIAS

GND#1

GND#2

ON1 ON2

+5VPCU

[21,28] S 5_ON

PR173 *S_4

S5_ON

5

4

3

2

1

Do Not add test pad on VCC & LDO pin

Rev

3A

Size Docum ent N umber

SYSTEM 5V/3V (NB680 & NB679)

Date: Tuesday March 21 2017 heet 23 of 34

15

MAINON [21, 24,25,28, 29]

PR99 PC84 1K_1%_4 470p/ 50V_4

Freq=600KHZ

JP7 *S 3720

5VPCU_VIN

PR169 PC164

SY8288 CBST_S

PR168 PC34 1K_1%_4 470p/ 50V_4

Freq=600KHZ

PR172 *S_4

PC176 PC175 *0.1u/16V_ 4 *0. 1u/16 V_4

PC183 PC1 4

1000p/ 0V_4 100 /50 V_4

Soft-Start

+3VPCU +3VPCU

SY8286 BRAC

TDC : 0.28A TDC : 3.345A PEAK : 0.21A PEAK : 4.46A Width : 20mil Width : 140mil

PC116 PC136 1u/25V_4 1u /25V_4

+3V_S5 +3V

LDO=5V/100mA

VL

PC162

4.7u/6.3V _4

2 3 4 5

7

1 S Y8288C BST

IN#1

LDO IN#2

IN#3 IN#4

GND#1

PC117 PC125 *0.1u/1 6V_4 *0.1u/ 16V_4

P 119 PC1 4

1000p/ 0V_4 10 00 /5 0V_4

Soft-Start

Quanta Computer Inc.

PROJECT : ZAJ

S5 ON

PR136 *S_4

0.1u/16V _4

3

13 14

4

SYS_HW PG

PR157 *S_4

+VIN

PR158 499K_1 %_4

SYS_SH DN#

PR164 *S_4

SY8288CPG

9

PG

Vih=0.8V

11

EN2

PR162 150K_1 %_4

SY8288 CEN

12

EN1

PC32 *0.1u/1 6V_4

17

VCC

PC163

2.2u/10V _4

8

VCC=3.3V

PC111 PC115 10u/6.3V _6 0.1u/1 6V_4

+5VPCU

PR137 *S_ 4 PC1 20

8 9

11 15

5

PC135 PC139

0.1u/16V _4 10u/6.3 V_6

PR138 *S_4

MAINON

BS

LX#1 LX#2 LX#3

NC#1 NC#2

OUT

FF

1821

VOUT1#1 VOUT1#2 OUT2#1

OUT2#2

PU7

AOZ1331DI

VBIAS

GND#1

GND#2

ON1 ON2

PL8

*S_6 0.1 u/25V_ 1.5uH_7 x7x3

6 S Y8288C SW 1 2 19 20

PR40

_

_ _ _ _ _ _ 8

5 0p

_

4 _ _

C 2

5 p

, , S

SYS_SH DN#

+3VPCU

SYS_HW PG

[21] SYS_ HWPG

PR109

PR88 PR87 PR3

17

SY8286 BLDO

*4.7_5 %_6

10 16

PC13 *680p/5 0V_6

14 SY82 86BVO UT

13 S Y8286B FB

Idc=8A

*4.7_5 %_6

10 16

PC33 *680p/5 0V_6

14 SY828 8CV OUT

13 S Y8288 CFB

Idc=9A

3.3 Volt +/- 5% TDC : 5.73A PEAK : 7.64A Width : 240mil

+3VPCU

JP4 *S_3720

+3VPCU _SRC

+5VPCU 5 Volt +/- 5%

+5VPCU SRC

TDC : 7.5A PEAK : 10A Width : 300mil

+5VPCU

JP8 *S_3720

PC148 PR148

1

POK NC#1

2

VIN#1 SW#1

3

VIN#2 SW#2

7

NC#2

6

VCC FB

5

GND EN

Rev

3A

Size Document Number

+1.05V (M5671RE1U)

Date: Tuesday, March 21, 2017 Sheet 24 of 34

5

4

3

2

1

M5671RE1U PC140

*0.1u/16V_4

B

A

PR142 *S_4

PR141

7.5K_1%_4

PR143

Vo=0.6*(R1+R2)/R2

8068FB_1.05V_S

PR146 *S_4

PU8 PL5

1uH_7x7x3

806 LX_1.05V 2

PC137

*22p/50V_4

8068NC_ .05V

8068PG_1.05V

4 9

10

PR147 10_5%_6

8068SVIN_1.05V 8

11

PC149 PC142 10u/6.3V_6 1u/6.3V_4

[21] HWPG_1.05V

+3VPCU

JP6 *S_3720

B

A

*68p/50V_4

8068FB_1.05V 8068EN 1.05V

5

4

3

2

1

[6,12,13,14,19,21,22,23,28] +3VPCU

[6,7,26] +1.05V

[4,5,6,12,13,14,15,16,17,18,21,23,25,26,28,29] +3V

+3V

PR144

100K_1%_4

D

C

PR145 JP5 *S_4 *2200p/50V_4 *2.2_5%_6 *S_3720

R1

R2

ZP HNE 15_

15

H CAG+.VST+.V

0 5O 0

8 1 _

10K_1%_4

=1.05V

MAINON [21,23,25,28,29]

Quanta Computer Inc.

PROJECT :

PC141

1

24

D

+1.05V

1.05Volt +/- 5% TDC : 2.025A PEAK : 2.7A Width : 100mil

+1.05V

A

Size Document Number

DDR3L (RT8231BGQW)

Date:

Tuesday March 21 2017

Sheet

25 of

34

4 5

Rev

3A

1 2

+3V

PR197 100K_1%_4

3

S0

1

S3 (mainon off)

0

S4/S5

0

OCP=13A L ripple current =(19-1.35)*1.35/(1u*500k*19) =2.508A Vtrip=13-(2.508/2)*14.5mohm =170.317mV Rlimit=170.317mV/5uA*10=340.63Kohm

4 5

+VIN

[12,22,23,26,27,29,30]

+1.35VSUS [2,7,10,11]

+VDDQ_VTT [10,11]

+5V_S5 [6,19,20,23,26,27,30]

+3V

[4,5,6,12,13,14,15,16,17,18,21,23,24,26,28,29]

25

PR196 *S_4

PR59 *S_4

A

B

C

D

[21]

HWPG_1.35VSUS

[2

SUSON

[21,23,24,28,29] MAINON

PC47 *0.1u/16V_4

Ilimit=13A

PR193

PR199

*S_4

340K_1%_4

+VIN

JP9 *S 3720

PR190 *S_4

PC41 *0.1u/16V_4

+VDDQ_VTT

PC197 10u/6.3V_6

1P35V TON

UGATE

BOOT

PHASE LGATE

VDD

1P35V_VDDQ

R1

PR191 10K_1%_4

1.35VSUS VIN

PL9

1uH_7x7x3

1 2

PR52 *4.7_5%_6

PC40 *680p/50V_6

TDC : 0.75A PEAK : 1A Width : 40mil

+VDDQ

PQ18 AON7410

D

G

4

S

D

G

4

S

PQ19 AON7752

20

2

1

4

19

VTT VTTSNS

VTTGND

PU15

RT8231BGQ W

VTTREF VLDOIN

Fsw=500KHz

PR194

499K_1%_4

17

1P35V_UGATE

PR195 PC207

18

1P35V_BOOT

2.2_5% _6

16

1P35V_PHASE

15

1P35V_LGATE

12 1P35V VDD

PR64 *S_4

PC210

1u/6.3V_4

0.1u/50V_6

+5V_S5

S3

R2

PR192 10K_1%_4

DDR=1.35V R1=10K/F_4 R2=10K/F_4

PR48 100_1%_4

PC39

PC195

0.1u/16V_4

0.033u/16V_4

+1.35VSUS

TDC : 0.375A PEAK : 0.5A Width : 20mil

Rds(on)=14.5mohm

S5

VDDQ

VTTREF VTT

1

ON

1

ON

OFF

0

OFF

PR47 *S_4

PR53

PR65

*0_5%_4

*S_4

1P35V_S3

1P35V_S5

+5V_S5

PR198 *0_5%_4

VID

Ref. Voltage

High

0.675V

Low

0.75V

1] _ _ _

_

, ,

+1.35VSUS

1.35 Volt +/- 5% TDC : 7.875A PEAK : 10.5A OCP : 13A Width : 320mil

+1.35VSUS

+1.35VSUS_SR C

JP10 *S_3720

Quanta Computer Inc.

PROJECT :

B

C

D

+VCC_VC CGI

PC19

*0.01u/50 V_4

PR30 100_1%_4

4 27

COMP_B ISUMP_C

PU6

ISL95859AH RTZ-T

26

ISL9585 7_RTN_C

RTN_C

5 6 7 8 9

10

25

ISL95857_FB_C

FB_B FB_C

RTN_B ISUMP_B ISUMN_B ISEN _B ISEN _B

Close to VCCGI MOS

[27]

PR112 *S_4

PWM_C

PR108 *S_4

FCCM_C

Rail A

PR104 *S_4

PWM_A

PR103 *S_4

FCCM_A

PR115

1K_1%_4

1

PSYS

2

IMON_B

3

NTC_B

30

ISL95857 PW M C

PWM_C

29

ISL95857 _FCCM_C

FCCM_C

28

ISL95857_ISUMN_C

ISUMN_C

24

ISL95857 _COMP_C

COMP_C

23

ISL95857_IMON_ C

IMON_C

22

ISL9585 7 PW M A

PWM_A

21

ISL95857 _FCCM_A

FCCM_A

PC91

2200p/50V_ 4

PR124

*S 4

VCCGI_SENSE

PR119

*S 4

VCCGISS_SENS E

PR12

*S 4

PR97

*S 4

PC98 *0.01u/50V_4

+3V

ISL95857 PSYS

Rev

3A

Size Docume nt Number

CPU_CORE (ISL95859)

Date: Tuesday, M arch 21, 2017

Sheet 26 of 34

5 4 3 2 1

Quanta Computer Inc.

PROJECT :

PC17

PR21 100_1%_4

0.01u/50V_ 4

Close to VNN Choke

ISUMN_C [27]

PR110

0K_NTC _4_1%

PC86

PR100

0.047u/16 V_4 11K_1%_4

PR6

2.61K_1%_4

ISUMP_C [27]

+VNN

PC3

PR95

*0.01u/50V_4 100_1%_4

PC87 PR101

2200p/50V_ 4 1K_1%_4

PR14

332 1% 4

Close to VCCGI Choke

PR116

0K_NTC_4_1 %

PC12

PR19

0.022u/50V _4 11K_1%_4

PR22

2.61K_1%_4

[6] H_CPU_S VIDCLK

Check PU High with HW

PR129 10K_1%_4

[6,21,22] H_PROC HOT#

[21] I MVP_PW RGD

[21] VNN_ON

PR33 *S_4

Check VR Sequence

TP30

PC4 *0.01u/50V_ 4

PC5

PR96 *S_4

*0.01u/50V_4

ISUMN_A [27]

ISUMP_A [27]

[7]

PR111 182_1%_4

PR23 499_1%_4

PC15 1000p/50V_4

D

C

B

A

PR24

20 1% 4

PR123 95.3_1%_4

+3V

：

+VCCGI

：

+VNN

Rail C

Rail A（1 phase

）

Rail C（1 phase

）

5 4 3 2 1

+5V_S5

+VIN

ISL95857_SDA

ISL95857_SCLK

IMVP8 VR Controller

+1.05V

PR122

PR27

86.6_1%_4 169_1%_4

SVID_CLK : UP:85 ohm Series:95 ohm SVID_ALERT : UP:68 ohm Series:220 ohm SVID_DATA : UP:170 ohm Series:20 ohm

[6] H_CPU_SVI DDAT

[6] VR_SVID _ALERT#_VCOR E

26

D

C

VNN_SEN SE [7]

TP29

B

A

_

_ _

1

_ _ _

1

_ _

2

_

1

_

ISL95857_VR_HOT

ISL95857_VR_READ Y

ISL95857_VR_EN

PR127 *S_4

PR130 *S_4

PR133 *S_4

PR131 *10K_1%_ 4

Double Check Rail B Non-Usage Pin

+5V_S5

PR132 *S_4

APL VR (1+1 Phase)

+VCCGI

Icc Max：21A Icc TDC：18A Vboot：0V OCP：25A Fsw：750KHZ

VCCGI L/L

R_DC_LL：6mV/A R_AC_LL：6mV/A

：

+VNN

Icc Max：4.8A

Icc TDC：N/A

Vboot：1.05V OCP：8A Fsw：750KHZ

VCCGI

G

4

G

4

[26] ISUMP_A [26] ISUMN_A

D

PQ11 AON7410

S

D

PQ12 AON7752

S

[26] ISUMP_C

[26] ISUMN_C

PU3 ISL95808 HRZ- T P R92

*S_6

2

VCC BOO T

1

PWM UGATE

8

FCCM PH ASE

5

GND#1

LGATE

D

G

4

S

D

G

4

S

PU4

VCC

PWM

FCCM

PR121

PR126

PHASE_C

PR16

2.2_5%_ 6

PC14 1000p/5 0V_4

PR91

PR94

6

3

7

4

6

3

7

4

GND#1

LGATE

PL4

0.15uH_ 7x7x4

1 2

3 65K 1% 6

*S_6

PL2

0.47uH_ 7x7x3

1 2

3 65K 1% 6

*S_6

30

+VCCGI

Icc Max：21A Icc TDC：18A Vboot：0V OCP：25A Fsw：750KHZ

VCCGI L/L

：

R_DC_LL：6mV/A R_AC_LL：6mV/A

+VNN

Icc Max：4.8A Icc TDC：N/A Vboot：1.05V OCP：8A Fsw：750KHZ

D

C

B

A

D

C

B

A

PR1 *S_6

+5V_S5

Rail A

[26] PWM_A

[26] FCCM_A

VNN

PR2 *S_6

+5V_S5

Rail C

[26] PW M_C

[26] FCCM _C

+VIN

+

DCR=0.66mOhm

17x22uF for VCCGI

JP2 *S 3720

+VIN

DCR=4.2mOhm

7x22uF for VNN

+VCC_V CCGI

+VCC VCCGI

+

+VCC_VCCG I

+VNN

ISL958 08HRZ -T PR86

*S_6

2

BOOT

PR84 *S 4

PR90 *S 4

PR85 *S 4

PR89 *S 4

PQ13 AON641 4AL

PHASE A

PR5

2.2_5%_ 6 PQ14 AON6752

PC1 1000p/5 0V_4

1

8

5

UGATE

PHASE

Rev

3A

Size Docum ent N umber

+VCCGI / +VNN (ISL95859)

Date: Tuesday March 21 2017 heet 27 of 34

5

4

3 2 1

Quanta Computer Inc.

PROJECT :

PC75

0.1u/50V _6

PC79

0.1u/50V _6

_ _ _ _

_

. _ _

_

. _ _

, , S

5

4

3 2 1

+VIN [12,22,23,25,26,29,3 0]

+VCC_V CCGI [7 ,26]

+VNN [7, 26] +5V_S5 [6,19,20 ,23,25,26,30]

JP3 *S 3720

Size Document Number

+1.8V_S5 / +1.24V_S5 / +1.5V

Date: Tuesday, March 21, 2017 Sheet 28 of 34

1

4

3

Rev

3A

P 158 *0 1u/16V_4

PR150 *S_6

PR166

30K_1%_4 PR167 15K_1%_4

PC150

4.7u/6.3 V_4

R2

5

NC

6

VO

8

GND# 1

9

GND# 2

R1

0.8V

R2

PU14 G9661MF11U

VIN

VEN VPP

POK

GND

[21]

EN

PR41 *S_6

5

PG LX

PU12

G5719CT B1U

1

EN GND

PC1 7

0.1u 6V_4

Check RC delay time with HW (follow ZHP RC dealy time)

PR180 *S_8

3

PR182 *S_4

2 4

1

Check RC delay time with HW (follow ZHP RC dealy time)

5

PG LX

PU10

G5719CT B1U

+3V_S5

PR160 100K_1%_4

HWPG_1.8V_S5

[21,23] S5_ON

+3VPCU

PR165 *S_4

PR170 100K_5%_4

R1

PR154

16K_1%_4 PR155 15K_1%_4

PR151 *S_4

Vo=(0.6(R1+R2)/R2) =1.24V

PR181 *S_8

PC186 10u/6.3V_6

PR183 30K_1%_4

Vo =0.8(1+R1/R2)

=1.506V

PR185 34K_1%_4

+3V_S5

PR149 100K_1%_4

+1.8V_S5

1.8Volt +/- 5% TDC : 0.514A PEAK : 0.685A Width : 40mil

+1.8V_S 5

[29]

MAIND

+1.24V_S5

1.24Volt +/- 5% TDC : 0.975A PEAK : 1.3A Width : 40mil

+1.24V_ S5

[5,6,7,15,16,18,20,21,23] +3V_S5

[23]

+5VPCU

[4,5,6,12,13,14,15,16,17,18,21,23,24,25,26,29] +3V

PC161

4.7u/6.3 V_4

PL7

3 G5719LX1.8V 1 2

2.2uH_2 .5x2.0x1.2

2

PR161 *S_4

R1

[6,12,13,14,19,21,22,23,24] +3VPCU

[3,5,6,7,9,15,16,17,18,22]

+1.8V_ S5 [7]

+1.24V_S5

[12,13,29]

+1.8V

[14]

+1.5V

ZHP CHANGE +1.8V_S5 PG PULL UP TO +3V_S5

1 2

2

JP11 *S 3720

JP12 *S 3720

+1.5V

1.5Volt +/- 5% TDC : 0.39A PEAK : 0.52A Width : 20mil

+1.5V

2

4

3

5

D

C

B

[21,23,24,25,29]

A

5

Vo=(0.6(R1+R2)/R2) =1.8V

PL6

R2

+3VPCU

PR152 *S_4

PR163 *S_4

_ 6 /1 _ C

.

HWPG_1.5V

+3V

PR186 100K_5%_4

PC185 [21] 1u/25V_4

[21]

MAINON

+5VPCU

HWPG_1.24V_S5

HWPG_1.8V_ S5

+3VPCU

MAINON

PR179 *S_4

3 G5719LX1.24V 2

2.2uH_2 .5x2.0x1.2

1

28

+1.8V_S 5

MAIND 2 PQ4

TDC : 0.173A PEAK : 0.23A Width : 20mil

D

AO3404

+1.8V

C

B

A

Quanta Computer Inc.

PROJECT :

5 4 3 2 1

Rset(Kohm)=0.0 012T*T -0.930 8T+96.147 =25.69 K ohm

Rev

3A

Size Document Number

Thermal / Discharge

Date: Tuesday, March 21, 2017 Sheet 29 of 34

5 4 3 2 1

A A

Quanta Computer Inc.

PROJECT :

29

D

(1) Need fine tune

for thermal protect point

(2) Note placement position

TEMP=85C

SYS_SHDN#

SYS_SHDN# [21,23]

PR159 150 1% 4

PR153 24K_1%_4

VL

PC160

0.1u/16V_4

3

OT

PR42 22_5%_8

2

PQ5 2N7002K

PU9 PR156

TMP708AIDBVR *S_4

1

SET

C C

HYST=VCC for 10 degree Hys. HYST=GND for 30 degree Hys.

+5V PU High R= 220 ohm for Bo-Bo sound issue.

+VIN

PR35 1M_5%_6

MAIND

2

PQ1 2N7002K

+3V +5V +1.8V

+VIN

PR36 1M_5%_6

MAINON_ON_G

PR37 1M_5%_6

PQ2

DDTC144EUA-7-F

PR43 *220_5

PR39 22_5%_8

PQ3 2N7002K

_8

B

2

[21,23,24,25,28] MAINON

PR38

*100K_1%_6

B

MAIND [28]

PC31 *2200p/50V_4

2 2

PQ15 *2N7002K

_ _

%

[4,5,6,12,13,14,15,16,17,18,21,23,24,25,26,28] +3V

[12,22,23,25,26,27,30] +VIN

[12,13,14,16,18,23] +5V

[23] VL

[12,13,28] +1.8V

Thermal Protection

Size Document Number

LED Panel (TPS61087)

Date: Tuesday, March 21, 2017 Sheet 30 of 34

3 2 1

PR212

*VL@100K_1%_6

10 61087SS

PC16

[email protected]/25V_4

PR29

PR8

R2

VL@20K_1%_4

PR10

PR28 *VL@0 5% 4

PR7 VL@0 5% 4

PC7

[email protected]/16V_4

R1

PR9

VL@174K_1%_4

VFB=1.238V

6 2

1

VL@DFLS240-7

2

61087SW

61087FB

61087COMP

6

7

2

1

8

IN SW #1

61087EN

3

EN SW#2

61087FREQ

9

FREQ FB

[21] PANEL_LED_EN

PQ23 VL@2N7002K

PR211 VL@1M_5%

4

AGND COMP

5

PGND SS

PL1

1

2

[email protected]_5x5x1.8

40V, 2A

PU1 V L@TPS61087DRCR

PD1

D

C

B

A

D

C

B

A

PR206

VL@10K_5%_4

PR207 VL@0_5%_4

2

VL@0_ %_4

PR25 *VL@0_5%_4

PQ24

VL@DDTC144EUA

2

PANEL_LED_EN

5

+VIN

PR209 VL@1M_5%_6

7-F

BL Discharge Circuit

PR208 VL@0_5%_4

PANEL LED EN

Rev

3A

5

+5V_S5

PR204 VL@0_5%_8

PC216 PR205

*[email protected]/25V_4 VL@100K_1%_4

VL@100K_5%_4

PC8 VL@820p/50V_4

+12V_Panel

PR210 VL@22_5%_8

PQ25 VL@2N7002K

4

PANEL_LED_EN

4

3 2 1

30

Panel Spec (TFT-LCD 14'') VLED : 6V~21V (Tpy:12V) Power Consumption : 3W (MAX)

+12V_Panel 12 Volt +/- 5% PEAK : 0.35A Width : 20mil

+12V_Panel

PC138 PC127 PC145 PC146 *VL@22u/25V_8 *VL@22u/25V_8 VL@22u/25V_8 VL@22u/25V_8

_ _ 5 _ _ - _ _

_

PQ22

S

D

1

3

G

VGS=-4.5V

VL@AO3415

Vo =1.238*(1+R1/R 2) =12V

Quanta Computer Inc.

PROJECT : ZAJ

2

20MIL

CN5

EMMC

15MIL U2

+1.8V

20MIL

PQ4

CODEC

PANEL BOOST +5V_FAN1 HDD+M2_PWR +5V_ODD TP_PWR

5

Apollo Power Tree

4

PU4

PU3

PU15

PU5

PU11

4

3

30

D

C

B

A

Quanta Computer Inc.

PROJECT :

ZAJ

+VCC_VCCGI

840 MIL

+VNN

200 MIL

+1.35VSUS

420 MIL

110MIL

25MIL

55MIL

D

C

VIN

600MIL

B

A

5

RTC

20MIL CN13

LED

10MIL

+3V_S5

70MIL

PU7

+3V

190MIL

PU7

+1.8V_S5

105MIL +3VPCU

310MIL

305MIL +5VPCU

590MIL

35MIL

LCDVCC

60MIL

M.2 SSD

U13

U19

40MIL

USBPWR1

100MIL

U15

U7

40MIL

+1.05V

110MIL

+1.24V_S5

55MIL

+1.5V

20MIL

+5V

240MIL

+5V_S5

350MIL

PU12

PU8

PU10

PU14

PU13

40MIL PU1 20MIL CN10 60MIL CN12 60MIL CN16 10MIL CN3

USBPWR2 +TYPEC_VBUS_C

100MIL U18 150MIL U3

ize Document Number

POWER TREE

ate:

Tuesday March 21 2017

Sheet 31 of 34

2

1

Rev

3A S D , ,

1

LAN RTL8411B-CG

40MIL

U13

TPM

5MIL U14

TOUCH PAD

10MIL

CN15

EC

12MIL U16

AUDIO CODEC

10MIL

U15

WIFI

30MIL CN9

CRD RTL8411B-CG

5

4

3

VCCRTC

2

1

31

D

C

B

A

Quanta Computer Inc.

PROJECT : ZAJ

RTC_RST#

VCC_RTC_3P3V power to RTC_TEST# > 9 ms

RTC_TEST#

+3VPCU/+5VPCU

SYS_HWPG

NBSWON#

S5 ON

+5V S5/+3V S5

VNN ON

+VNN

+1.8V S5

+1.24V S5

RSMRST#

DNBSWON#

SUSB#/SUSC#

SUSON

+1.35VSUS

MAINON

+1.05V/+1.5V

HWPG

MAIND

+1.8V

EC PWROK

+VCC VCCGI

PLTRST#

30ms

120ms

10ms

>100ms

boot up by SVID

5

4

3

Size Document Number

Power on Sequence

Date: Tuesday, March 21, 2017

Sheet 32 of 34

1

Rev

3A

_

_ _ _ _ _ _ _

D

Adaptor in

From PWM to EC

POWER BUTTON

From EC to PWM

Delay S5_ON (6.34ms)

C

HWPG_1.8V_S5

From EC to SOC

From SOC to EC

From EC to PWM

B

From PW to MOS

HWPG_1.5V

From EC to SOC

A

1

7

8

32

A

B

C

D

Quanta Computer Inc.

Date:

Tuesday, March 21, 2017

Sheet

33 of 34

7

8

PROJECT :

Size Document Number

Power status table

ZAJ

Rev

3A

A

2

3

4

5

6

B

C

D

1

2

3

4

5

6

5 4 3 2

1

D

C

B

A

1

CHANGE LIST

1.Change 0 ohm to shortpad： R403,R404,R405,R406,R407,R408,R409,R410,R104,R113,R108,R115,R99,R402,R167,R165,R161,R158,R157,R153,R270,R271,R272,R273,R247

2.Un-stuff R380/R464 (debug card circuit)

1.Unstuff SW3

2.Update SW2 FP to "sw-ds-a40e-4p-smt " by SMT request

3.Update CN2 FP to "sdcard-156-1001902602-11p-smt" by SMT request

4.Update CN9 FP to "ngff-apci0076-p001a-75p-ke-smt" by SMT request

Quanta Computer Inc.

PROJECT : ZAJ

Size Document Numb er

Change li st

Date: Tuesday, March 21, 2017 Sheet 34 of 34

ZAJ

PROJECT MODEL :

APPROVED BY:

DATE:

DOC NO.

ev

3A

PART NU MBER:

DRAWING BY:

REVISON:

5 4 3 2

R

ZAJ REV.D

M

ODEL

D

ATE

02/10

D

C

02/18

B

A

Acer Aspire A315-31 Schematic