Acer Aspire 8940, Aspire 8940G Schematics
5
+3V
BKP1608HS181T_6_1.5A
BKP1608HS181T_6_1.5A
L28
D D
C C
XTAL_IN XTAL_OUT
C283
C283
33P
33P
4/23 Chagne +3V to +1.05V
B B
at B-test
A A
CPU_SEL
L28
Y3
Y3
21
14.318MHZ
14.318MHZ
01
CPU0/1=133MHz
(default)
C303
C303
4.7U/10V_8
4.7U/10V_8
4.7U/10V_8
4.7U/10V_8
Place the 33 ohm
resistors close to the CK 505
+1.05V
R184
R184
*10K_4
*10K_4
R189
R189
10K_4
10K_4
CLK_ICH_14M10
C284
C284
33P
33P
CPU_SEL
C264
C264
*10p/50V/COG_4
*10p/50V/COG_4
CPU0/1=100MHz
5
C293
C293
150mA(20mil)
C299
C299
C297
C297
.1u/16V_4
.1u/16V_4
.1u/16V_4
.1u/16V_4
C298
C298
.1u/16V_4
.1u/16V_4
ICH_SMBDATA10,16,20,21,25
ICH_SMBCLK10,16,20,21,25
C285
C285
.1u/16V_4
.1u/16V_4
4
+3V_CLK
C302
C302
.1u/16V_4
.1u/16V_4
R199 33_4R199 33_4
Q26
Q26
R183 0_4R183 0_4
Q28
Q28
R203 0_4R203 0_4
4
XTAL_OUT
XTAL_IN
CPU_SEL
CLK_SDATA
CLK_SCLK
+3V
2
3 1
+3V
2
R198
R198
*10K_4
*10K_4
*2N7002W-7-F
*2N7002W-7-F
31
*2N7002W-7-F
*2N7002W-7-F
U21
U21
1
VDD_DOT
5
VDD_27
17
VDD_SRC
24
VDD_CPU
29
VDD_REF
27
XTAL_OUT
28
XTAL_IN
30
REF_0/CPU_SEL
31
SDA
32
SCL
2
VSS_DOT
8
VSS_27
9
VSS_SATA
12
VSS_SRC
21
VSS_CPU
26
VSS_REF
33
GND
SLG8SP585V
SLG8SP585V
CLK_SDATA
CLK_SCLK
R202
R202
*10K_4
*10K_4
3
VDD_SRC_I/O
VDD_CPU_I/O
DOT_96
DOT_96#
27M_SS
SRC_1/SATA
SRC_1#/SATA#
SRC_2
SRC_2#
*CPU_STOP#
CPU_1
CPU_1#
CPU_0
CPU_0#
CKPWRGD/PD#
CLK_SDATA 14,15
CLK_SCLK 14,15
3
27M
15
18
CLK_BUF_DREFCLK_R
3
CLK_BUF_DREFCLK#_R
4
6
7
CLK_BUF_PCIE_3GPLL_R
10
CLK_BUF_PCIE_3GPLL#_R
11
CLK_BUF_DREFSSCLK_R
13
CLK_BUF_DREFSSCLK#_R
14
R206 10K_4R206 10K_4
16
20
19
CLK_BUF_BCLK_R
23
CLK_BUF_BCLK#_R
22
CK_PWRGD_R
25
CLK Enable
VR_PWRGD_CK505#33
+VDDIO_CLK
TP54TP54
TP56TP56
+3V
TP53TP53
TP55TP55
80mA(20mil)
2
2
CLK_BUF_DREFCLK_R
CLK_BUF_DREFCLK#_R
CLK_BUF_PCIE_3GPLL_R
CLK_BUF_PCIE_3GPLL#_R
CLK_BUF_DREFSSCLK_R
CLK_BUF_DREFSSCLK#_R
CLK_BUF_BCLK_R
CLK_BUF_BCLK#_R
+3V
R197
R197
1K/F_4
1K/F_4
CK_PWRGD_R
3
Q25
Q25
2N7002E_200MA
2N7002E_200MA
1
2
1
+VDDIO_CLK
+3V
+1.05V
L29 *BLM18AG601SN1D_6L29 *BLM18AG601SN1D_6
L30 BLM18AG601SN1D_6L30 BLM18AG601SN1D_6
Place each 0.1uF cap as close as
possible to each VDD IO pin. Place
the 10uF caps on the VDD_IO plane.
43
1 2
RN3 0_4P2RRN3 0_4P2R
RN5 0_4P2RRN5 0_4P2R
RN6 0_4P2RRN6 0_4P2R
RN4 0_4P2RRN4 0_4P2R
R200
R200
100K/F_4
100K/F_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
43
1 2
43
1 2
1 2
43
Clock Generator
Clock Generator
Clock Generator
C300
C300
C305
C305
.1u/16V_4
.1u/16V_4
.1u/16V_4
.1u/16V_4
CLK_BUF_DREFCLK 10
CLK_BUF_DREFCLK# 10
CLK_BUF_PCIE_3GPLL 10
CLK_BUF_PCIE_3GPLL# 10
CLK_BUF_DREFSSCLK 10
CLK_BUF_DREFSSCLK# 10
CLK_BUF_BCLK 10
CLK_BUF_BCLK# 10
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
ZY9
ZY9
ZY9
1
C301
C301
10u/Y5V_8
10u/Y5V_8
342Thursday, August 27, 2009
342Thursday, August 27, 2009
342Thursday, August 27, 2009
of
of
of
C308
C308
10u/Y5V_8
10u/Y5V_8
3A
3A
3A
5
4
AUBURNDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI)
3
2
1
AUBURNDALE/CLARKSFIELD PROCESSOR (CLK,MISC,JTAG)
U37A
U37A
DMI_TXN08
DMI_TXN18
DMI_TXN28
D D
C C
B B
DMI_TXN38
DMI_TXP08
DMI_TXP18
DMI_TXP28
DMI_TXP38
DMI_RXN08
DMI_RXN18
DMI_RXN28
DMI_RXN38
DMI_RXP08
DMI_RXP18
DMI_RXP28
DMI_RXP38
FDI_FSYNC0_R
FDI_FSYNC1_R
FDI_INT_R
FDI_LSYNC0_R
FDI_LSYNC1_R
A24
DMI_RX#[0]
C23
DMI_RX#[1]
B22
DMI_RX#[2]
A21
DMI_RX#[3]
B24
DMI_RX[0]
D23
DMI_RX[1]
B23
DMI_RX[2]
A22
DMI_RX[3]
D24
DMI_TX#[0]
G24
DMI_TX#[1]
F23
DMI_TX#[2]
H23
DMI_TX#[3]
D25
DMI_TX[0]
F24
DMI_TX[1]
E23
DMI_TX[2]
G23
DMI_TX[3]
E22
FDI_TX#[0]
D21
FDI_TX#[1]
D19
FDI_TX#[2]
D18
FDI_TX#[3]
G21
FDI_TX#[4]
E19
FDI_TX#[5]
F21
FDI_TX#[6]
G18
FDI_TX#[7]
D22
FDI_TX[0]
C21
FDI_TX[1]
D20
FDI_TX[2]
C18
FDI_TX[3]
G22
FDI_TX[4]
E20
FDI_TX[5]
F20
FDI_TX[6]
G19
FDI_TX[7]
F17
FDI_FSYNC[0]
E17
FDI_FSYNC[1]
C17
FDI_INT
F18
FDI_LSYNC[0]
D17
FDI_LSYNC[1]
Clarksfield/Auburndale
Clarksfield/Auburndale
DMI Intel(R) FDI
DMI Intel(R) FDI
PCI EXPRESS -- GRAPHICS
PCI EXPRESS -- GRAPHICS
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RBIAS
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
B26
A26
B27
A25
K35
J34
J33
G35
G32
F34
F31
D35
E33
C33
D32
B32
C31
B28
B30
A31
J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30
L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26
L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25
R446 49.9/F_4R446 49.9/F_4
R445 750/F_4R445 750/F_4
PCIE_MRX_GTX_N0 H_COMP1
PCIE_MRX_GTX_N1
PCIE_MRX_GTX_N2
PCIE_MRX_GTX_N3
PCIE_MRX_GTX_N4
PCIE_MRX_GTX_N5
PCIE_MRX_GTX_N6
PCIE_MRX_GTX_N7
PCIE_MRX_GTX_N8
PCIE_MRX_GTX_N9
PCIE_MRX_GTX_N10
PCIE_MRX_GTX_N11
PCIE_MRX_GTX_N12
PCIE_MRX_GTX_N13
PCIE_MRX_GTX_N14
PCIE_MRX_GTX_N15
PCIE_MRX_GTX_P0
PCIE_MRX_GTX_P1
PCIE_MRX_GTX_P2
PCIE_MRX_GTX_P3
PCIE_MRX_GTX_P4
PCIE_MRX_GTX_P5
PCIE_MRX_GTX_P6
PCIE_MRX_GTX_P7
PCIE_MRX_GTX_P8
PCIE_MRX_GTX_P9
PCIE_MRX_GTX_P10
PCIE_MRX_GTX_P11
PCIE_MRX_GTX_P12
PCIE_MRX_GTX_P13
PCIE_MRX_GTX_P14
PCIE_MRX_GTX_P15
PCIE_MTX_GRX_C_N0
PCIE_MTX_GRX_C_N1
PCIE_MTX_GRX_C_N2
PCIE_MTX_GRX_C_N3
PCIE_MTX_GRX_C_N4
PCIE_MTX_GRX_C_N5
PCIE_MTX_GRX_C_N6
PCIE_MTX_GRX_C_N7
PCIE_MTX_GRX_C_N8
PCIE_MTX_GRX_C_N9
PCIE_MTX_GRX_C_N10
PCIE_MTX_GRX_C_N11
PCIE_MTX_GRX_C_N12
PCIE_MTX_GRX_C_N13
PCIE_MTX_GRX_C_N14
PCIE_MTX_GRX_C_N15
PCIE_MTX_GRX_C_P0
PCIE_MTX_GRX_C_P1
PCIE_MTX_GRX_C_P2
PCIE_MTX_GRX_C_P3
PCIE_MTX_GRX_C_P4
PCIE_MTX_GRX_C_P5
PCIE_MTX_GRX_C_P6
PCIE_MTX_GRX_C_P7
PCIE_MTX_GRX_C_P8
PCIE_MTX_GRX_C_P9
PCIE_MTX_GRX_C_P10
PCIE_MTX_GRX_C_P11
PCIE_MTX_GRX_C_P12
PCIE_MTX_GRX_C_P13
PCIE_MTX_GRX_C_P14
PCIE_MTX_GRX_C_P15
PCIE_MRX_GTX_N[0..15] 17
PCIE_MRX_GTX_P[0..15] 17
7/3 Change R470 connect to S3 circuit of P.37 at C-test
Processor Compensation Signals
R467 20/F_4R467 20/F_4
R464 20/F_4R464 20/F_4
R113 49.9/F_4R113 49.9/F_4
R481 49.9/F_4R481 49.9/F_4
R135 *1K_4R135 *1K_4
R480
R480
H_PECI11
H_PROCHOT#33
PM_THRMTRIP#11
H_CPURST#16
PM_SYNC8
H_PWRGOOD11,16
PM_DRAM_PWRGD8
H_PWRGD_XDP16
PLTRST#10,16,17,20,21,25,26,30
*SHORT_4
*SHORT_4
R493
R493
*SHORT_4
*SHORT_4
R514 *SHORT_4R514 *SHORT_4
R496
R496
*SHORT_4
*SHORT_4
R513
R513
*SHORT_4
*SHORT_4
R475 *SHORT_4R475 *SHORT_4
R470
R470
0_4
0_4
R483 *SHORT_4R483 *SHORT_4
R471 1.5K/F_4R471 1.5K/F_4
750/F_4
750/F_4
SI 2/5 Modified
H_COMP3
H_COMP2
H_COMP0
TP_SKT0CC#
H_CATERR#
H_PECI_ISO
H_PROCHOT#_R
TP52TP52
TP12TP12
H_CPURST#_R
H_PM_SYNC_R
VDDPWRGOOD_R
H_VTTPWRGD
CPU_PLTRST#
R472
R472
U37B
U37B
AT23
COMP3
AT24
COMP2
G16
COMP1
AT26
COMP0
AH24
SKTOCC#
AK14
CATERR#
AT15
PECI
AN26
PROCHOT#
AK15
THERMTRIP#
AP26
RESET_OBS#
AL15
PM_SYNC
AN14
VCCPWRGOOD_1
AN27
VCCPWRGOOD_0
AK13
SM_DRAMPWROK
AM15
VTTPWRGOOD
AM26
TAPPWRGOOD
AL14
RSTIN#
Clarksfield/Auburndale
Clarksfield/Auburndale
MISC THERMAL
MISC THERMAL
CLOCKS
CLOCKS
DDR3
MISC
DDR3
MISC
PWR MANAGEMENT
PWR MANAGEMENT
JTAG & BPM
JTAG & BPM
BCLK
BCLK#
BCLK_ITP
BCLK_ITP#
PEG_CLK
PEG_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
PM_EXT_TS#[0]
PM_EXT_TS#[1]
PRDY#
PREQ#
TRST#
TDI_M
TDO_M
DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
TCK
TMS
TDI
TDO
CLK_CPU_BCLK_R
A16
CLK_CPU_BCLK#_R
B16
BCLK_ITP_P_R
AR30
BCLK_ITP_N_R
AT30
CLK_PCIE_3GPLL_R
E16
CLK_PCIE_3GPLL#_R
D16
DPLL_REF_SSCLK_R
A18
DPLL_REF_SSCLK#_R
A17
F6
SM_RCOMP_0
AL1
SM_RCOMP_1
AM1
SM_RCOMP_2
AN1
AN15
AP15
AT28
AP27
AN28
AP28
AT27
XDP_TDI_R
AT29
XDP_TDO_R
AR27
XDP_TDI_M
AR29
XDP_TDO_M
AP29
H_DBR#_R
AN25
XDP_OBS0_R
AJ22
XDP_OBS1_R
AK22
XDP_OBS2_R
AK24
AJ24
XDP_OBS4_R
AJ25
XDP_OBS5_R
AH22
XDP_OBS6_R
AK23
XDP_OBS7_R
AH23
R213 *100K_4R213 *100K_4
R155 100/F_4R155 100/F_4
R157 24.9/F_4R157 24.9/F_4
R159 130/F_4R159 130/F_4
R482 *SHORT_4R482 *SHORT_4
R500 *SHORT_4R500 *SHORT_4
R501 *SHORT_4R501 *SHORT_4
R504 *SHORT_4R504 *SHORT_4
R503 *SHORT_4R503 *SHORT_4
R499 *SHORT_4R499 *SHORT_4
R498 *SHORT_4R498 *SHORT_4
R502 *SHORT_4R502 *SHORT_4
R497 *SHORT_4R497 *SHORT_4
R440 33_4R440 33_4
R439 33_4R439 33_4
R485 33_4R485 33_4
R484 33_4R484 33_4
R111 33_4R111 33_4
R112 33_4R112 33_4
CPU_DDR3_DRAMRST# 37
R477 10K_4R477 10K_4
R478 10K_4R478 10K_4
R476 *SHORT_4R476 *SHORT_4
R479 *SHORT_4R479 *SHORT_4
XDP_PRDY# 16
XDP_PREQ# 16
XDP_TCLK 16
XDP_TMS 16
XDP_TRST# 16
XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3XDP_OBS3_R
XDP_OBS4
XDP_OBS5
XDP_OBS6
XDP_OBS7
CLK_CPU_BCLK 11
CLK_CPU_BCLK# 11
BCLK_ITP_P 16
BCLK_ITP_N 16
CLK_PCIE_3GPLL 10
CLK_PCIE_3GPLL# 10
8/14 Reserve R213 by intel
S3 at Ramp.
Layout Note: Place
these resistors
near Processor
+1.1V_VTT
PM_EXTTS#0 14
PM_EXTTS#1 15
XDP_DBRESET# 8,16
XDP_OBS[0:7] 16
PCIE_MTX_GRX_C_N0
PCIE_MTX_GRX_C_N1
PCIE_MTX_GRX_C_N2
PCIE_MTX_GRX_C_N3
PCIE_MTX_GRX_C_N4
PCIE_MTX_GRX_C_N5
PCIE_MTX_GRX_C_N6
PCIE_MTX_GRX_C_N7
PCIE_MTX_GRX_C_N8
PCIE_MTX_GRX_C_N9
PCIE_MTX_GRX_C_N10
PCIE_MTX_GRX_C_N11
PCIE_MTX_GRX_C_N12
PCIE_MTX_GRX_C_N13
PCIE_MTX_GRX_C_N14
PCIE_MTX_GRX_C_N15
[VGA]
A A
FDI_FSYNC0_R
FDI_FSYNC1_R
FDI_INT_R
FDI_LSYNC0_R
FDI_LSYNC1_R
C168 0.1U/X7R_4C168 0.1U/X7R_4
C162 0.1U/X7R_4C162 0.1U/X7R_4
C154 0.1U/X7R_4C154 0.1U/X7R_4
C144 0.1U/X7R_4C144 0.1U/X7R_4
C149 0.1U/X7R_4C149 0.1U/X7R_4
C143 0.1U/X7R_4C143 0.1U/X7R_4
C137 0.1U/X7R_4C137 0.1U/X7R_4
C136 0.1U/X7R_4C136 0.1U/X7R_4
C133 0.1U/X7R_4C133 0.1U/X7R_4
C130 0.1U/X7R_4C130 0.1U/X7R_4
C125 0.1U/X7R_4C125 0.1U/X7R_4
C116 0.1U/X7R_4C116 0.1U/X7R_4
C118 0.1U/X7R_4C118 0.1U/X7R_4
C112 0.1U/X7R_4C112 0.1U/X7R_4
C99 0.1U/X7R_4C99 0.1U/X7R_4
C114 0.1U/X7R_4C114 0.1U/X7R_4
R106 EV@1K_4R106 EV@1K_4
R109 EV@1K_4R109 EV@1K_4
R107 EV@1K_4R107 EV@1K_4
R110 EV@1K_4R110 EV@1K_4
R108 EV@1K_4R108 EV@1K_4
5
PCIE_MTX_GRX_N0
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_N15
PCIE_MTX_GRX_N[0..15] 17 PCIE_MTX_GRX_P[0..15] 17
Auburndale Graphics Disabled Guideline
(Checklist 1.0 P52 Auburndale Graphics Disable Guidelines)
DPLL_REF_SSCLK_R
DPLL_REF_SSCLK#_R
Layout Note: Place these resistors
near Processor ball less than 500mil.
PCIE_MTX_GRX_C_P0
PCIE_MTX_GRX_C_P1
PCIE_MTX_GRX_C_P2
PCIE_MTX_GRX_C_P3
PCIE_MTX_GRX_C_P4
PCIE_MTX_GRX_C_P5
PCIE_MTX_GRX_C_P6
PCIE_MTX_GRX_C_P7
PCIE_MTX_GRX_C_P8
PCIE_MTX_GRX_C_P9
PCIE_MTX_GRX_C_P10
PCIE_MTX_GRX_C_P11
PCIE_MTX_GRX_C_P12
PCIE_MTX_GRX_C_P13
PCIE_MTX_GRX_C_P14
PCIE_MTX_GRX_C_P15
R442 *EV@0_4R442 *EV@0_4
R441 *EV@0_4R441 *EV@0_4
4
C160 0.1U/X7R_4C160 0.1U/X7R_4
C155 0.1U/X7R_4C155 0.1U/X7R_4
C148 0.1U/X7R_4C148 0.1U/X7R_4
C142 0.1U/X7R_4C142 0.1U/X7R_4
C145 0.1U/X7R_4C145 0.1U/X7R_4
C139 0.1U/X7R_4C139 0.1U/X7R_4
C135 0.1U/X7R_4C135 0.1U/X7R_4
C134 0.1U/X7R_4C134 0.1U/X7R_4
C129 0.1U/X7R_4C129 0.1U/X7R_4
C127 0.1U/X7R_4C127 0.1U/X7R_4
C122 0.1U/X7R_4C122 0.1U/X7R_4
C117 0.1U/X7R_4C117 0.1U/X7R_4
C119 0.1U/X7R_4C119 0.1U/X7R_4
C113 0.1U/X7R_4C113 0.1U/X7R_4
C100 0.1U/X7R_4C100 0.1U/X7R_4
C115 0.1U/X7R_4C115 0.1U/X7R_4
MPWROK16,30
PCIE_MTX_GRX_P0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_P15
MPWROK
2
1
+3V
3 5
4
U20
U20
TC7SH08FU
TC7SH08FU
C286
C286
.1u/16V_4
.1u/16V_4
R192
R192
2K/F_4
2K/F_4
3
H_VTTPWRGD
R191
R191
1K_4
1K_4
Processor
Pullups
XDP_TDO
H_CATERR#
H_PROCHOT#_R
H_CPURST#_R
7/3 Reserve S3 circuit of P.37 connect to VDDPWRGOOD_R at C-test
4/9 REV:B MODIFY BY DG1.52
+1.5VSUS
R468
R468
1.1K/F_4
1.1K/F_4
R488
R488
3K/F_4
3K/F_4
R508 51/F_4R508 51/F_4
R137 49.9/F_4R137 49.9/F_4
R494 68_4R494 68_4
R495 *68_4R495 *68_4
XDP_TMS
R511 *51_4R511 *51_4
XDP_TDI_R
R486 *51_4R486 *51_4
XDP_PREQ#
R509 *51_4R509 *51_4
XDP_TCLK
R510 *51_4R510 *51_4
XDP_TRST#
R512 51/F_4R512 51/F_4
VDDPWRGOOD_R
Use a voltage divider with VDDQ
(1.5V) rail (ON in S3) and
resistor combination of 4.75K (to
VDDQ)/12K(to GND) to generate the
required voltage.
Note: CRB uses a 3.3V (always ON)
rail with 2K and 1K combination.
+1.1V_VTT
VDDPWRGOOD_R 37
2
JTAG MAPPING
XDP_TDI_R
XDP_TDO_M
XDP_TDI_M
XDP_TDO_R
Scan Chain
(Default)
CPU Only
GMCH Only
R491 0_4R491 0_4
R490 *0_4R490 *0_4
R469
R469
0_4
0_4
R489 *0_4R489 *0_4
R507 0_4R507 0_4
STUFF -> R469, R491, R507
NO STUFF -> R489, R490
STUFF -> R490, R491
NO STUFF -> R469, R489, R507
STUFF -> R489, R507
NO STUFF -> R491, R490, R469
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
AUBURNDA 1/4
AUBURNDA 1/4
AUBURNDA 1/4
Date: Sheet
Date: Sheet
Date: Sheet
PROJECT :
1
XDP_TDI 16
XDP_TDO 16
ZY9
ZY9
ZY9
442Thursday, August 27, 2009
442Thursday, August 27, 2009
442Thursday, August 27, 2009
3A
3A
3A
of
of
of
5
AUBURNDALE/CLARKSFIELD PROCESSOR (DDR3)
U37C
U37C
M_A_DQ[63:0]14
D D
C C
B B
M_A_BS#014
M_A_BS#114
M_A_BS#214
M_A_CAS#14
M_A_RAS#14
M_A_WE#14
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
AG5
AJ10
AL10
AK12
AK8
AK11
AN8
AM10
AR11
AL11
AM9
AN9
AT11
AP12
AM12
AN12
AM13
AT14
AT12
AL13
AR14
AP14
A10
SA_DQ[0]
C10
SA_DQ[1]
C7
SA_DQ[2]
A7
SA_DQ[3]
B10
SA_DQ[4]
D10
SA_DQ[5]
E10
SA_DQ[6]
A8
SA_DQ[7]
D8
SA_DQ[8]
F10
SA_DQ[9]
E6
SA_DQ[10]
F7
SA_DQ[11]
E9
SA_DQ[12]
B7
SA_DQ[13]
E7
SA_DQ[14]
C6
SA_DQ[15]
H10
SA_DQ[16]
G8
SA_DQ[17]
K7
SA_DQ[18]
J8
SA_DQ[19]
G7
SA_DQ[20]
G10
SA_DQ[21]
J7
SA_DQ[22]
J10
SA_DQ[23]
L7
SA_DQ[24]
M6
SA_DQ[25]
M8
SA_DQ[26]
L9
SA_DQ[27]
L6
SA_DQ[28]
K8
SA_DQ[29]
N8
SA_DQ[30]
P9
SA_DQ[31]
AH5
SA_DQ[32]
AF5
SA_DQ[33]
AK6
SA_DQ[34]
AK7
SA_DQ[35]
AF6
SA_DQ[36]
SA_DQ[37]
AJ7
SA_DQ[38]
AJ6
SA_DQ[39]
SA_DQ[40]
AJ9
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
AL7
SA_DQ[45]
SA_DQ[46]
AL8
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
AC3
SA_BS[0]
AB2
SA_BS[1]
U7
SA_BS[2]
AE1
SA_CAS#
AB3
SA_RAS#
AE9
SA_WE#
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
4
SA_CK[0]
SA_CK#[0]
SA_CKE[0]
SA_CK[1]
SA_CK#[1]
SA_CKE[1]
SA_CS#[0]
SA_CS#[1]
SA_ODT[0]
SA_ODT[1]
SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AA6
AA7
P7
Y6
Y5
P6
AE2
AE8
AD8
AF9
B9
D7
H7
M7
AG6
AM7
AN10
AN13
C9
F8
J9
N9
AH7
AK9
AP11
AT13
C8
F9
H9
M9
AH8
AK10
AN11
AR13
Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_CLK0 14
M_A_CLK0# 14
M_A_CKE0 14
M_A_CLK1 14
M_A_CLK1# 14
M_A_CKE1 14
M_A_CS#0 14
M_A_CS#1 14
M_A_ODT0 14
M_A_ODT1 14
M_A_DM[7:0] 14
M_A_DQS#[7:0] 14
M_A_DQS[7:0] 14
M_A_A[15:0] 14
3
M_B_DQ[63:0]15
M_B_BS#015
M_B_BS#115
M_B_BS#215
M_B_CAS#15
M_B_RAS#15
M_B_WE#15
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
AG1
AK1
AG4
AG3
AH4
AK3
AK4
AM6
AN2
AK5
AK2
AM4
AM3
AP3
AN5
AT4
AN6
AN4
AN3
AT5
AT6
AN7
AP6
AP8
AT9
AT7
AP9
AR10
AT10
AB1
AC5
AC6
M1
M4
AF3
AJ3
AJ4
W5
B5
A5
C3
B3
E4
A6
A4
C4
D1
D2
F2
F1
C2
F5
F3
G4
H6
G2
J6
J3
G1
G5
J2
J1
J5
K2
L3
K5
K4
N5
R7
Y7
U37D
U37D
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_RAS#
SB_WE#
2
W8
SB_CK[0]
W9
SB_CK#[0]
M3
SB_CKE[0]
V7
SB_CK[1]
V6
SB_CK#[1]
M2
SB_CKE[1]
AB8
SB_CS#[0]
AD6
SB_CS#[1]
AC7
SB_ODT[0]
AD1
SB_ODT[1]
M_B_DM0
D4
SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
DDR SYSTEM MEMORY - B
DDR SYSTEM MEMORY - B
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
E1
H3
K1
AH1
AL2
AR4
AT8
D5
F4
J4
L4
AH2
AL4
AR5
AR8
C5
E3
H4
M5
AG2
AL5
AP5
AR7
U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
1
M_B_CLK0 15
M_B_CLK0# 15
M_B_CKE0 15
M_B_CLK1 15
M_B_CLK1# 15
M_B_CKE1 15
M_B_CS#0 15
M_B_CS#1 15
M_B_ODT0 15
M_B_ODT1 15
M_B_DM[7:0] 15
M_B_DQS#[7:0] 15
M_B_DQS[7:0] 15
M_B_A[15:0] 15
Clarksfield/Auburndale
Clarksfield/Auburndale
Channel A DQ[15,32,48,54], DM[5]
Requires minimum 12mils spacing
with all other signals, including data signals.
A A
5
4
DM signals are not present on Clarkfield
processor. All DM signal can br left as
NC on Clarkfield and connect directly to
GND on So-DIMM side for Clarkfield
design only
3
Channel B DQ[16,18,36,42,56,57,60,61,62]
Requires minimum 12mils spacing
with all other signals, including data signals.
Clarksfield/Auburndale
Clarksfield/Auburndale
2
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
AUBURNDA 2/4
AUBURNDA 2/4
AUBURNDA 2/4
Date: Sheet
Date: Sheet
Date: Sheet
PROJECT :
ZY9
ZY9
ZY9
of
of
of
542Thursday, August 27, 2009
542Thursday, August 27, 2009
542Thursday, August 27, 2009
1
3A
3A
3A
CPU Core Power
+VCC_CORE
U37F
U37F
5
4
3
2
1
+1.1V_VTT4,7,11,12,16,34,37
+VCC_CORE33
+1.8V11,12,37
AUBURNDALE/CLARKSFIELD PROCESSOR (GRAPHICS POWER)
AG35
VCC1
AG34
VCC2
AG33
VCC3
AG32
VCC4
AG31
VCC5
AG30
D D
48A
C C
B B
A A
VCC6
AG29
VCC7
AG28
VCC8
AG27
VCC9
AG26
VCC10
AF35
VCC11
AF34
VCC12
AF33
VCC13
AF32
VCC14
AF31
VCC15
AF30
VCC16
AF29
VCC17
AF28
VCC18
AF27
VCC19
AF26
VCC20
AD35
VCC21
AD34
VCC22
AD33
VCC23
AD32
VCC24
AD31
VCC25
AD30
VCC26
AD29
VCC27
AD28
VCC28
AD27
VCC29
AD26
VCC30
AC35
VCC31
AC34
VCC32
AC33
VCC33
AC32
VCC34
AC31
VCC35
AC30
VCC36
AC29
VCC37
AC28
VCC38
AC27
VCC39
AC26
VCC40
AA35
VCC41
AA34
VCC42
AA33
VCC43
AA32
VCC44
AA31
VCC45
AA30
VCC46
AA29
VCC47
AA28
VCC48
AA27
VCC49
AA26
VCC50
Y35
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55
Y30
VCC56
Y29
VCC57
Y28
VCC58
Y27
VCC59
Y26
VCC60
V35
VCC61
V34
VCC62
V33
VCC63
V32
VCC64
V31
VCC65
V30
VCC66
V29
VCC67
V28
VCC68
V27
VCC69
V26
VCC70
U35
VCC71
U34
VCC72
U33
VCC73
U32
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
U28
VCC78
U27
VCC79
U26
VCC80
R35
VCC81
R34
VCC82
R33
VCC83
R32
VCC84
R31
VCC85
R30
VCC86
R29
VCC87
R28
VCC88
R27
VCC89
R26
VCC90
P35
VCC91
P34
VCC92
P33
VCC93
P32
VCC94
P31
VCC95
P30
VCC96
P29
VCC97
P28
VCC98
P27
VCC99
P26
VCC100
Clarksfield/Auburndale
Clarksfield/Auburndale
1.1V RAIL POWER
1.1V RAIL POWER
CPU CORE SUPPLY
CPU CORE SUPPLY
POWER
POWER
PROC_DPRSLPVR
CPU VIDS
CPU VIDS
VSS_SENSE_VTT
SENSE LINES
SENSE LINES
AUBURNDALE/CLARKSFIELD PROCESSOR (POWER)
5
VTT0_1
VTT0_2
VTT0_3
VTT0_4
VTT0_5
VTT0_6
VTT0_7
VTT0_8
VTT0_9
VTT0_10
VTT0_11
VTT0_12
VTT0_13
VTT0_14
VTT0_15
VTT0_16
VTT0_17
VTT0_18
VTT0_19
VTT0_20
VTT0_21
VTT0_22
VTT0_23
VTT0_24
VTT0_25
VTT0_26
VTT0_27
VTT0_28
VTT0_29
VTT0_30
VTT0_31
VTT0_32
VTT0_33
VTT0_34
VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42
VTT0_43
VTT0_44
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VTT_SELECT
ISENSE
VCC_SENSE
VSS_SENSE
VTT_SENSE
AH14
AH12
AH11
AH10
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15
AN33
PSI#
AK35
AK33
AK34
AL35
AL33
AM33
AM35
AM34
G15
AN35
AJ34
AJ35
B15
A15
C501 10U_8C501 10U_8
C506 10U_8C506 10U_8
C525 10U_8C525 10U_8
C531 10U_8C531 10U_8
C519 10U_8C519 10U_8
C523 10U_8C523 10U_8
C504 10U_8C504 10U_8
C214 22U_8C214 22U_8
C205 22U_8C205 22U_8
C511 22U_8C511 22U_8
+
+
C500 *330u/2V_7343
C500 *330u/2V_7343
VTT Rail Values are
Auburndal VTT=1.05V
Clarksfield VTT=1.1V
C223
C223
22U_8
22U_8
TP9TP9
+VTT_43
R122 *SHORT_4R122 *SHORT_4
+VTT_44
R123 *SHORT_4R123 *SHORT_4
(15mils)
TP10TP10
C98
C98
1u/10V_4
1u/10V_4
For CRB use
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6
H_VTTVID1
H_VTTVID1=Low, 1.1V
H_VTTVID1=High, 1.05V
VTT_SENSE
TP_VSS_SENSE_VTT
+1.1V_VTT
18A
+1.1V_VTT
C237
C237
22U_8
22U_8
H_PSI# 33
H_VID0 33
H_VID1 33
H_VID2 33
H_VID3 33
H_VID4 33
H_VID5 33
H_VID6 33
ICH_DPRSLPVR 33
TP8TP8
I_MON 33
R150 100_4R150 100_4
R146 100_4R146 100_4
TP6TP6
TP7TP7
4
+VCC_CORE
VCCSENSE 33
VSSSENSE 33
R448
R448
R450
R450
R452
1K_4
1K_4
R449
R449
*1K_4
*1K_4
R452
1K_4
1K_4
R451
R451
*1K_4
*1K_4
3
1K_4
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6
ICH_DPRSLPVR
H_PSI#
1K_4
R447
R447
*1K_4
*1K_4
Note:
For Validating IMVP VR R6451 should be STUFF
and R2N1 NO_STUFF
+1.1V_VTT
+1.1V_VTT
+1.1V_VTT
R454
R454
*1K_4
*1K_4
R453
R453
1K_4
1K_4
C180 22U_8C180 22U_8
C509 22U_8C509 22U_8
C181 22U_8C181 22U_8
C182 22U_8C182 22U_8
C197 22U_8C197 22U_8
C517 22U_8C517 22U_8
R456
R456
R459
R459
*1K_4
*1K_4
1K_4
1K_4
R458
R458
R455
R455
*1K_4
*1K_4
1K_4
1K_4
HFM_VID : Max 1.4V
LFM_VID : Min 0.65V
R461
R461
*1K_4
*1K_4
R460
R460
1K_4
1K_4
R466
R466
1K_4
1K_4
R465
R465
*1K_4
*1K_4
U37G
U37G
AT21
VAXG1
AT19
VAXG2
AT18
VAXG3
AT16
VAXG4
AR21
VAXG5
AR19
VAXG6
AR18
VAXG7
AR16
VAXG8
AP21
VAXG9
AP19
VAXG10
AP18
VAXG11
AP16
VAXG12
AN21
VAXG13
AN19
VAXG14
AN18
VAXG15
AN16
VAXG16
AM21
VAXG17
AM19
VAXG18
AM18
VAXG19
AM16
VAXG20
AL21
VAXG21
AL19
VAXG22
AL18
VAXG23
AL16
VAXG24
AK21
VAXG25
AK19
VAXG26
AK18
VAXG27
AK16
VAXG28
AJ21
VAXG29
AJ19
VAXG30
AJ18
VAXG31
AJ16
VAXG32
AH21
VAXG33
AH19
VAXG34
AH18
VAXG35
AH16
VAXG36
J24
VTT1_45
J23
VTT1_46
H25
VTT1_47
K26
VTT1_48
J27
VTT1_49
J26
VTT1_50
J25
VTT1_51
H27
VTT1_52
G28
VTT1_53
G27
VTT1_54
G26
VTT1_55
F26
VTT1_56
E26
VTT1_57
E25
VTT1_58
Clarksfield/Auburndale
Clarksfield/Auburndale
R463
R463
*1K_4
*1K_4
R462
R462
1K_4
1K_4
+VCC_CORE
GRAPHICS
GRAPHICS
FDI PEG & DMI
FDI PEG & DMI
POWER
POWER
C199
C199
22U_8
22U_8
C183
C183
22U_8
22U_8
C198
C198
10u/6.3V_6
10u/6.3V_6
C515
C515
10u/6.3V_6
10u/6.3V_6
C498
C498
+
+
*330u/2V_7343
*330u/2V_7343
VAXG_SENSE
VSSAXG_SENSE
SENSE
LINES
SENSE
LINES
GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]
GFX_VR_EN
GFX_DPRSLPVR
GFX_IMON
GRAPHICS VIDs
GRAPHICS VIDs
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
DDR3 - 1.5V RAILS
DDR3 - 1.5V RAILS
VTT0_59
VTT0_60
VTT0_61
VTT0_62
VTT1_63
VTT1_64
VTT1_65
1.1V1.8V
1.1V1.8V
VTT1_66
VTT1_67
VTT1_68
VCCPLL1
VCCPLL2
VCCPLL3
C530
C530
C526
C526
C512
C234
C234
C513
C513
2
22U_8
22U_8
C529
C529
22U_8
22U_8
C520
C520
10u/6.3V_6
10u/6.3V_6
C521
C521
10u/6.3V_6
10u/6.3V_6
C480
C480
+
+
330u/2V_7343
330u/2V_7343
C512
22U_8
22U_8
C243
C243
22U_8
22U_8
C209
C209
10u/6.3V_6
10u/6.3V_6
C518
C518
10u/6.3V_6
10u/6.3V_6
22U_8
22U_8
C226
C226
22U_8
22U_8
10u/6.3V_6
10u/6.3V_6
10u/6.3V_6
10u/6.3V_6
AR22
AT22
AM22
AP22
AN22
AP23
AM23
AP24
AN24
AR25
AT25
AM24
AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1
P10
N10
L10
K10
J22
J20
J18
H21
H20
H19
L26
L27
M26
C222
C222
22U_8
22U_8
C236
C236
22U_8
22U_8
C208
C208
+
+
*330u/2V_7343
*330u/2V_7343
C238
C238
22U_8
22U_8
C190
C190
22U_8
22U_8
C516
C516
10u/6.3V_6
10u/6.3V_6
C510
C510
10u/6.3V_6
10u/6.3V_6
IMON
C188
C188
1u/10V_4
1u/10V_4
C203
C203
22U_8
22U_8
C184
C184
10u/6.3V_6
10u/6.3V_6
C507
C507
22U_8
22U_8
C178
C178
1u/10V_4
1u/10V_4
C174
C174
22U_8
22U_8
C527
C527
22U_8
22U_8
C514
C514
10u/6.3V_6
10u/6.3V_6
C232
C232
10u/6.3V_6
10u/6.3V_6
C522
C522
+
+
330u/2V_7343
330u/2V_7343
R193 EV@1K_4R193 EV@1K_4
3A
+1.5V_CPUVDDQ
C221
C221
C228
C228
C241
C241
C194
C194
1u/10V_4
1u/10V_4
C213
C213
22U_8
22U_8
1u/10V_4
1u/10V_4
+
+
C163
C163
*330u/2V_7343
*330u/2V_7343
1u/10V_4
1u/10V_4
1u/10V_4
1u/10V_4
7/2 Change CPU VDDQ from +1.5V_S3
to +1.5V_CPUVDDQ at C test.
6/5 No stuff at RevC by DG1.6
+1.1V_VTT
C176
C176
10u/6.3V_6
10u/6.3V_6
C508
C508
22U_8
22U_8
C503
C503
C502
C179
C179
1u/10V_4
1u/10V_4
C191
C191
22U_8
22U_8
C528
C528
22U_8
22U_8
C195
C195
10u/6.3V_6
10u/6.3V_6
C524
C524
10u/6.3V_6
10u/6.3V_6
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
C502
2.2U_6_H0.5
2.2U_6_H0.5
4.7u_6
4.7u_6
C217
C217
10u/6.3V_6
10u/6.3V_6
C196
C196
10u/6.3V_6
10u/6.3V_6
AUBURNDA 3/4
AUBURNDA 3/4
AUBURNDA 3/4
+1.8V
C505
C505
22U_8
22U_8
0.6A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
1
ZY9
ZY9
ZY9
3A
3A
3A
of
of
of
642Thursday, August 27, 2009
642Thursday, August 27, 2009
642Thursday, August 27, 2009
5
4
3
2
1
AUBURNDALE/CLARKSFIELD PROCESSOR (GND) AUBURNDALE/CLARKSFIELD PROCESSOR( RESERVED, CFG)
U37H
U37H
AT20
VSS1
AT17
VSS2
AR31
VSS3
AR28
VSS4
AR26
VSS5
AR24
VSS6
AR23
VSS7
AR20
VSS8
AR17
D D
C C
B B
VSS9
AR15
VSS10
AR12
VSS11
AR9
VSS12
AR6
VSS13
AR3
VSS14
AP20
VSS15
AP17
VSS16
AP13
VSS17
AP10
VSS18
AP7
VSS19
AP4
VSS20
AP2
VSS21
AN34
VSS22
AN31
VSS23
AN23
VSS24
AN20
VSS25
AN17
VSS26
AM29
VSS27
AM27
VSS28
AM25
VSS29
AM20
VSS30
AM17
VSS31
AM14
VSS32
AM11
VSS33
AM8
VSS34
AM5
VSS35
AM2
VSS36
AL34
VSS37
AL31
VSS38
AL23
VSS39
AL20
VSS40
AL17
VSS41
AL12
VSS42
AL9
VSS43
AL6
VSS44
AL3
VSS45
AK29
VSS46
AK27
VSS47
AK25
VSS48
AK20
VSS49
AK17
VSS50
AJ31
VSS51
AJ23
VSS52
AJ20
VSS53
AJ17
VSS54
AJ14
VSS55
AJ11
VSS56
AJ8
VSS57
AJ5
VSS58
AJ2
VSS59
AH35
VSS60
AH34
VSS61
AH33
VSS62
AH32
VSS63
AH31
VSS64
AH30
VSS65
AH29
VSS66
AH28
VSS67
AH27
VSS68
AH26
VSS69
AH20
VSS70
AH17
VSS71
AH13
VSS72
AH9
VSS73
AH6
VSS74
AH3
VSS75
AG10
VSS76
AF8
VSS77
AF4
VSS78
AF2
VSS79
AE35
VSS80
Clarksfield/Auburndale
Clarksfield/Auburndale
VSS
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30
U37I
U37I
K27
VSS161
K9
VSS162
K6
VSS163
K3
VSS164
J32
VSS165
J30
VSS166
J21
VSS167
J19
VSS168
H35
VSS169
H32
VSS170
H28
VSS171
H26
VSS172
H24
VSS173
H22
VSS174
H18
VSS175
H15
VSS176
H13
VSS177
H11
VSS178
H8
VSS179
H5
VSS180
H2
VSS181
G34
VSS182
G31
VSS183
G20
VSS184
G9
VSS185
G6
VSS186
G3
VSS187
F30
VSS188
F27
VSS189
F25
VSS190
F22
VSS191
F19
VSS192
F16
VSS193
E35
VSS194
E32
VSS195
E29
VSS196
E24
VSS197
E21
VSS198
E18
VSS199
E13
VSS200
E11
VSS201
E8
VSS202
E5
VSS203
E2
VSS204
D33
VSS205
D30
VSS206
D26
VSS207
D9
VSS208
D6
VSS209
D3
VSS210
C34
VSS211
C32
VSS212
C29
VSS213
C28
VSS214
C24
VSS215
C22
VSS216
C20
VSS217
C19
VSS218
C16
VSS219
B31
VSS220
B25
VSS221
B21
VSS222
B18
VSS223
B17
VSS224
B13
VSS225
B11
VSS226
B8
VSS227
B6
VSS228
B4
VSS229
A29
VSS230
A27
VSS231
A23
VSS232
A9
VSS233
Clarksfield/Auburndale
Clarksfield/Auburndale
VSS
VSS
NCTF
NCTF
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
AT35
AT1
AR34
B34
B2
B1
A35
9/9
M_VREF_DQ_DIMM014,37
M_VREF_DQ_DIMM115,37
CFG0
CFG3
CFG4
CFG7
R443 *SHORT_4R443 *SHORT_4
R444 *SHORT_4R444 *SHORT_4
TP_RSVD17_R
TP_RSVD18_R
U37E
U37E
AP25
RSVD1
AL25
RSVD2
AL24
RSVD3
AL22
RSVD4
AJ33
RSVD5
AG9
RSVD6
M27
RSVD7
L28
RSVD8
J17
SA_DIMM_VREF
H17
SB_DIMM_VREF
G25
RSVD11
G17
RSVD12
E31
RSVD13
E30
RSVD14
AM30
CFG[0]
AM28
CFG[1]
AP31
CFG[2]
AL32
CFG[3]
AL30
CFG[4]
AM31
CFG[5]
AN29
CFG[6]
AM32
CFG[7]
AK32
CFG[8]
AK31
CFG[9]
AK28
CFG[10]
AJ28
CFG[11]
AN30
CFG[12]
AN32
CFG[13]
AJ32
CFG[14]
AJ29
CFG[15]
AJ30
CFG[16]
AK30
CFG[17]
H16
RSVD_TP_86
B19
RSVD15
A19
RSVD16
A20
RSVD17
B20
RSVD18
U9
RSVD19
T9
RSVD20
AC9
RSVD21
AB9
RSVD22
C1
RSVD_NCTF_23
A3
RSVD_NCTF_24
J29
RSVD26
J28
RSVD27
A34
RSVD_NCTF_28
A33
RSVD_NCTF_29
C35
RSVD_NCTF_30
B35
RSVD_NCTF_31
Clarksfield/Auburndale
Clarksfield/Auburndale
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
RSVD_NCTF_37
RSVD38
RSVD39
RSVD_NCTF_40
RSVD_NCTF_41
RSVD_NCTF_42
RSVD_NCTF_43
RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
RSVD53
RSVD_NCTF_54
RSVD_NCTF_55
RSVD_NCTF_56
RSVD_NCTF_57
RSVD58
RSVD_TP_59
RSVD_TP_60
RESERVED
RESERVED
RSVD62
RSVD63
RSVD64
RSVD65
RSVD_TP_66
RSVD_TP_67
RSVD_TP_68
RSVD_TP_69
RSVD_TP_70
RSVD_TP_71
RSVD_TP_72
RSVD_TP_73
RSVD_TP_74
RSVD_TP_75
RSVD_TP_76
RSVD_TP_77
RSVD_TP_78
RSVD_TP_79
RSVD_TP_80
RSVD_TP_81
RSVD_TP_82
RSVD_TP_83
RSVD_TP_84
RSVD_TP_85
KEY
VSS
AJ13
AJ12
AH25
AK26
AL26
AR2
AJ26
AJ27
AP1
AT2
AT3
AR1
AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33
AT33
AT34
AP35
AR35
AR32
E15
F15
A2
D15
C15
AJ15
AH15
AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3
V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9
AP34
RSVD64_R
RSVD65_R
R474 *SHORT_4R474 *SHORT_4
R473 *SHORT_4R473 *SHORT_4
TP11TP11
Processor Strapping
10
A A
The Clarkfield processor's PCI Express interface
may not meet PCI Express 2.0 jitter specifications.
Intel recommends placing a 3.01K +/- 5% pull down
resistor to VSS on CFG[7] pin for both rPGA and BGA
components. This pull down resistor should be
removed when this issue is fixed.
5
+1.1V_VTT
R487 3.01K/F_4R487 3.01K/F_4
R138 3.01K/F_4R138 3.01K/F_4
R142 3.01K/F_4R142 3.01K/F_4
CFG4
R492 *3.01K/F_4R492 *3.01K/F_4
CFG0
R139 *3.01K/F_4R139 *3.01K/F_4
CFG3
R143 *3.01K/F_4R143 *3.01K/F_4
CFG7
R154 3.01K/F_4R154 3.01K/F_4
4
CFG4
(Display Port
Presence)
CFG0
(PCI-Epress
Configuration Select)
CFG3
(PCI-Epress Static
Lane Reversal)
3
Disabled; No Physical Display Port
attached to Embedded Diplay Port
Single PEG
Normal Operation Lane Numbers Reversed
Enabled; An external Display port
device is connected to the Embedded
Display port
Bifurcation enabled
2
CFG[ 1:0 ] - PCI_Epress Configuration Select
* 11= 1 x 16 PEG
* 10= 2 x 8 PEG
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
AUBURNDA 4/4
AUBURNDA 4/4
AUBURNDA 4/4
Date: Sheet
Date: Sheet
Date: Sheet
PROJECT :
ZY9
ZY9
ZY9
of
of
of
742Thursday, August 27, 2009
742Thursday, August 27, 2009
1
742Thursday, August 27, 2009
3A
3A
3A
5
4
3
2
1
IBEX PEAK-M (DMI,FDI,GPIO)
U46C
U46C
DMI_RXN04
D D
C C
B B
A A
DMI_RXN14
DMI_RXN24
DMI_RXN34
DMI_RXP04
DMI_RXP14
DMI_RXP24
DMI_RXP34
DMI_TXN04
DMI_TXN14
DMI_TXN24
DMI_TXN34
DMI_TXP04
DMI_TXP14
DMI_TXP24
DMI_TXP34
+V1.1LAN_VCC_EXP
XDP_DBRESET#4,16
PM_DRAM_PWRGD4
ICH_RSMRST#30
DNBSWON#30
PM_PWRBTN#_R16
PCH_ACIN30
SYS_PWROK
R564 49.9/F_4R564 49.9/F_4
R279 *SHORT_4R279 *SHORT_4
R353 *SHORT_4R353 *SHORT_4
R356 *SHORT_4R356 *SHORT_4
R579 *SHORT_4R579 *SHORT_4
R265 *SHORT_4R265 *SHORT_4
R274 *0_4R274 *0_4
CLKRUN#
XDP_DBRESET#_R
ICH_RSMRST#
RSV_ICH_LAN_RST#
SYS_PWROK
XDP_DBRESET#_R
SYS_PWROK_R
PCHPWROK
MEPWROK
RSV_ICH_LAN_RST#
SUS_PWR_ACK_R
ACIN_R
PM_BATLOW#
PM_RI#
BC24
DMI0RXN
BJ22
DMI1RXN
AW20
DMI2RXN
BJ20
DMI3RXN
BD24
DMI0RXP
BG22
DMI1RXP
BA20
DMI2RXP
BG20
DMI3RXP
BE22
DMI0TXN
BF21
DMI1TXN
BD20
DMI2TXN
BE18
DMI3TXN
BD22
DMI0TXP
BH21
DMI1TXP
BC20
DMI2TXP
BD18
DMI3TXP
BH25
DMI_ZCOMP
BF25
DMI_IRCOMP
T6
SYS_RESET#
M6
SYS_PWROK
B17
PWROK
K5
MEPWROK
A10
LAN_RST#
D9
DRAMPWROK
C16
RSMRST#
M1
SUS_PWR_DN_ACK / GPIO30
P5
PWRBTN#
P7
ACPRESENT / GPIO31
A6
BATLOW# / GPIO72
F14
RI#
IbexPeak-M_R1P0
IbexPeak-M_R1P0
R620 8.2K_4R620 8.2K_4
R370 1K_4R370 1K_4
R242 10K_4R242 10K_4
R578 10K_4R578 10K_4
R365 10K_4R365 10K_4
DMI
FDI
DMI
FDI
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
System Power Management
System Power Management
SLP_LAN# / GPIO29
+3V +3V_S5
PM_RI#
PM_BATLOW#
PCIE_WAKE#
PM_SLP_LAN#
SUS_PWR_ACK_R
ACIN_R
4/9 REV:B MODIFY
5
4
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
WAKE#
SLP_S4#
SLP_S3#
SLP_M#
TP23
PMSYNCH
R246 10K_4R246 10K_4
R599 8.2K_4R599 8.2K_4
R250 1K_4R250 1K_4
R613 *10K_4R613 *10K_4
R368 10K_4R368 10K_4
R373 10K_4R373 10K_4
BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12
BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12
BJ14
BF13
BH13
BJ12
BG14
J12
Y1
P8
F3
E4
H7
P12
K8
N2
BJ10
F6
6/5 No stuff at RevC by DG1.6
FDI_INT
R658 *1K_4R658 *1K_4
FDI_FSYNC0
R659 *1K_4R659 *1K_4
FDI_FSYNC1
R660 *1K_4R660 *1K_4
FDI_LSYNC0
R661 *1K_4R661 *1K_4
FDI_LSYNC1
R662 *1K_4R662 *1K_4
SUS_STAT#
ICH_SUSCLK
SLP_S5#_R
SLP_S4#_R
R260 *SHORT_4R260 *SHORT_4
SLP_S3#_R
R266 *SHORT_4R266 *SHORT_4
SLP_M#
R261 *0_4R261 *0_4
PM_SLP_LAN#
PCIE_WAKE# 20,21
CLKRUN# 30
TP42TP42
ICH_SUSCLK 30
6/22 Del R260,R266 at C test.
TP45TP45
SUSC# 14,30
SUSB# 30
TO LED
TP48TP48
PM_SYNC 4
TP46TP46
C388 *.1u_4C388 *.1u_4
SYS_PWROK
TC7SH08FU
TC7SH08FU
DAC_IREF_R
R217
R217
1K/F_4
1K/F_4
+3V_S5
DELAY_VR_PWRGOOD need PU 2K to +3V.
PU at power side
53
1
4
2
U25
U25
R295 100K_4R295 100K_4
3
DELAY_VR_PWRGOOD 11,33
PWROK_EC 30
IBEX PEAK-M (LVDS,DDI)
U46D
U46D
AB48
AB46
AP39
AP41
AT43
AT42
AV53
AV51
BB47
BA52
AY48
AV47
BB48
BA50
AY49
AV48
AP48
AP47
AY53
AT49
AU52
AT53
AY51
AT48
AU50
AT51
AA52
AB53
AD53
AD48
AB51
T48
T47
Y48
Y45
V48
V51
V53
Y53
Y51
L_BKLTEN
L_VDD_EN
L_BKLTCTL
L_DDC_CLK
L_DDC_DATA
L_CTRL_CLK
L_CTRL_DATA
LVD_IBG
LVD_VBG
LVD_VREFH
LVD_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_CLK#
LVDSB_CLK
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
CRT_BLUE
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN
IbexPeak-M_R1P0
IbexPeak-M_R1P0
2
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_STALLN
SDVO_STALLP
SDVO_CTRLCLK
SDVO_CTRLDATA
LVDS
LVDS
DDPC_CTRLCLK
DDPC_CTRLDATA
Digital Display Interface
Digital Display Interface
DDPD_CTRLCLK
DDPD_CTRLDATA
CRT
CRT
BJ46
BG46
BJ48
BG48
BF45
SDVO_INTN
BH45
SDVO_INTP
T51
T53
BG44
DDPB_AUXN
BJ44
DDPB_AUXP
AU38
DDPB_HPD
BD42
DDPB_0N
BC42
DDPB_0P
BJ42
DDPB_1N
BG42
DDPB_1P
BB40
DDPB_2N
BA40
DDPB_2P
AW38
DDPB_3N
BA38
DDPB_3P
Y49
AB49
BE44
DDPC_AUXN
BD44
DDPC_AUXP
AV40
DDPC_HPD
BE40
DDPC_0N
BD40
DDPC_0P
BF41
DDPC_1N
BH41
DDPC_1P
BD38
DDPC_2N
BC38
DDPC_2P
BB36
DDPC_3N
BA36
DDPC_3P
U50
U52
BC46
DDPD_AUXN
BD46
DDPD_AUXP
AT38
DDPD_HPD
BJ40
DDPD_0N
BG40
DDPD_0P
BJ38
DDPD_1N
BG38
DDPD_1P
BF37
DDPD_2N
BH37
DDPD_2P
BE36
DDPD_3N
BD36
DDPD_3P
DP_HPD_INT#_R
6/25 No stuff R366 at C-test.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
SDVO_CTRL_CLK
SDVO_CTRL_DATA
DP_HPD_INT#_R
DPB_LANE0_N
DPB_LANE0_P
DPB_LANE1_N
DPB_LANE1_P
DPB_LANE2_N
DPB_LANE2_P
DPB_LANE3_N
DPB_LANE3_P
R366 *IV@0_4R366 *IV@0_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
IBEX PEAK-M 1/6
IBEX PEAK-M 1/6
IBEX PEAK-M 1/6
TP61TP61
TP59TP59
TP63TP63
TP64TP64
TP23TP23
TP24TP24
TP65TP65
TP66TP66
TP26TP26
TP33TP33
TP30TP30
TP19TP19
DP_HPD_INT# 19,30
1
ZY9
ZY9
ZY9
SDVO
HDMI port BDisplay port CDisplay port D
3A
3A
842Thursday, August 27, 2009
842Thursday, August 27, 2009
842Thursday, August 27, 2009
3A
of
of
of
5
4
3
2
1
+RTC_CELL
CR2
CR2
20mils
+3VPCU
D D
+3VRTC_2
R220
R220
1K_4
1K_4
20MIL
VCCRTC_2
12
CN30
CN30
RTC_ML2032
RTC_ML2032
C C
PCH_AZ_CODEC_SYNC23
MXM_SYNC_HDMI17
PCH_AZ_CODEC_RST#23
MXM_RST#_HDMI17
PCH_AZ_CODEC_SDOUT23
B B
MXM_SDOUT_HDMI17
MXM_BIT_CLK_HDMI17
PCH_AZ_CODEC_BITCLK23
Place all series terms close to PCH except for SDIN input
lines,which should be close to source.Placement of R773, R775,
R776 & R777 should equal distance to the T split trace point.
Basically, keep the same distance from T for all series
termination resistors.
VCCRTC_2
RB500V-40
RB500V-40
RB500V-40
RB500V-40
20MIL
RTC Circuitry
CR1
CR1
30mils20mils
30mils
R225
R225
1M_4
1M_4
TPM Settings J4
Clear ME RTC registers 1-2
Save ME RTC registers
20MIL
RTC_N01
1 3
Q44
Q44
MMBT3904
MMBT3904
2
RTC_N03
R558 33_4R558 33_4
R362 33_4R362 33_4
R553 33_4R553 33_4
R364 33_4R364 33_4
R560 33_4R560 33_4
R374 33_4R374 33_4
R367 33_4R367 33_4
R554 33_4R554 33_4
C408
C408
*27P_4
*27P_4
50
50
R218 16K_6R218 16K_6
C602
C602
*27P_4
*27P_4
50
50
R241 20K/F_4R241 20K/F_4
R219
R219
68.1K/F_4
68.1K/F_4
R337
R337
150K/F_6
150K/F_6
ACZ_SYNCACZ_SYNC
ACZ_RST#
ACZ_SDOUT
ACZ_SDOUT
ACZ_BIT_CLK
ACZ_BIT_CLK
C310 1u/10V_4C310 1u/10V_4
C355
C355
1u/10V_4
1u/10V_4
+5V_S5
CMOS Settings J5
Clear CMOS 1-2
C363
C363
1u/10V_4
1u/10V_4
1-X
(Default)
12
J2
J2
*SHORT_ PAD1
*SHORT_ PAD1
7/1 change from +3V_S5 to +3V by intel.
R233 *1K_4R233 *1K_4
Save CMOS
R253 20K/F_4R253 20K/F_4
12
J1
J1
*SHORT_ PAD1
*SHORT_ PAD1
1-X
(Default)
INTVRMEN - Integrated SUS 1.1V VRM Enable
High - Enable Internal VRs
HDA_DOCK_EN#
6/21 Non stuff R233 by Intel at C-test.
C632
C632
15p_4
15p_4
32.768KHZY632.768KHZ
C636
C636
15p_4
15p_4
Cap values depend on Xtal
+RTC_CELL
+3V
R626 *10K_4R626 *10K_4
SPKR23
Place near connector
PCH_AZ_CODEC_SDIN023
MXM_SDIN_HDMI17
R235 *10K_4R235 *10K_4
+3V
R234 10K_4R234 10K_4
+3V_S5
PCH_JTAG_TCK_BUF16
PCH_JTAG_TMS16
PCH_JTAG_TDI16
PCH_JTAG_TDO16
PCH_JTAG_RST#16
23
Y6
4 1
R255 330K_4R255 330K_4
ACZ_BIT_CLK
ACZ_SYNC
R615
R615
ACZ_RST#
ACZ_SDOUT
TP5TP5
TP4TP4
TP3TP3
TP2TP2
TP1TP1
R591 10K_4R591 10K_4
+3VPCU
R571
R571
10M_4
10M_4
RTC_X1
RTC_X2
RTC_RST#
SRTC_RST#
SM_INTRUDER#
PCH_INVRMEN
PCH_HDA_SPKR
*SHORT_4
*SHORT_4
HDA_DOCK_EN#
GPIO13
PCH_JTAG_TCK_BUF
PCH_JTAG_TCK_BUF
PCH_JTAG_TMS
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TDO
PCH_JTAG_RST#
PCH_JTAG_RST#
IBEX PEAK-M (HDA,JTAG,SATA)
U46A
U46A
TP39TP39
TP37TP37
SPI_CLK_R
SPI_CS0#_R
SPI_CS1#
SPI_SI_R
SPI_SO
B13
RTCX1
D13
RTCX2
C14
RTCRST#
D17
SRTCRST#
A16
INTRUDER#
A14
INTVRMEN
A30
HDA_BCLK
D29
HDA_SYNC
P1
SPKR
C30
HDA_RST#
G30
HDA_SDIN0
F30
HDA_SDIN1
E32
HDA_SDIN2
F32
HDA_SDIN3
B29
HDA_SDO
H32
HDA_DOCK_EN# / GPIO33
J30
HDA_DOCK_RST# / GPIO13
M3
JTAG_TCK
K3
JTAG_TMS
K1
JTAG_TDI
J2
JTAG_TDO
J4
TRST#
BA2
SPI_CLK
AV3
SPI_CS0#
AY3
SPI_CS1#
AY1
SPI_MOSI
AV1
SPI_MISO
IbexPeak-M_R1P0
IbexPeak-M_R1P0
RTCIHDA
RTCIHDA
SPI JTAG
SPI JTAG
FWH4 / LFRAME#
LDRQ1# / GPIO23
LPC
LPC
SATA
SATA
SATAICOMPO
SATA0GP / GPIO21
SATA1GP / GPIO19
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
LDRQ0#
SERIRQ
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATAICOMPI
SATALED#
D33
B33
C32
A32
C34
A34
F34
AB9
AK7
AK6
AK11
AK9
AH6
AH5
AH9
AH8
AF11
AF9
AF7
AF6
AH3
AH1
AF3
AF1
AD9
AD8
AD6
AD5
AD3
AD1
AB3
AB1
AF16
AF15
T3
Y9
V1
PCH_DRQ#0
PCH_DRQ#1
SATA_TXN0_C
SATA_TXP0_C
SATA_TXN1_C
SATA_TXP1_C
SATA_RX2N_C
SATA_RX2P_C
SATA_TXN2_C
SATA_TXP2_C
SATA_TXN3_C
SATA_TXP3_C
R273 43K/F_4R273 43K/F_4
R619 43K/F_4R619 43K/F_4
TP38TP38
TP36TP36
C389 0.01u/16V_4C389 0.01u/16V_4
C390 0.01u/16V_4C390 0.01u/16V_4
C392 0.01u/16V_4C392 0.01u/16V_4
C391 0.01u/16V_4C391 0.01u/16V_4
C405 0.01u/16V_4C405 0.01u/16V_4
C404 0.01u/16V_4C404 0.01u/16V_4
C372 0.01u/16V_4C372 0.01u/16V_4
C371 0.01u/16V_4C371 0.01u/16V_4
C379 0.01u/16V_4C379 0.01u/16V_4
C378 0.01u/16V_4C378 0.01u/16V_4
Distance between the PCH and
cap on the "P" signal should be
identical distace between the
PCH and cap on the "N" signal
for the same pair.
R244 37.4/F_4R244 37.4/F_4
+3V
SATA_DET0# 16
SATA_DET1# 16
R263 10K_4R263 10K_4
+V1.1LAN_VCC_SATA
LPC_LAD0 21,30
LPC_LAD1 21,30
LPC_LAD2 21,30
LPC_LAD3 21,30
LPC_LFRAME# 21,30
+3V
IRQ_SERIRQ 30
SATA_RX0- 22
SATA_RX0+ 22
SATA_TX0- 22
SATA_TX0+ 22
SATA_RX1- 22
SATA_RX1+ 22
SATA_TX1- 22
SATA_TX1+ 22
SATA_RX2- 28
SATA_RX2+ 28
SATA_TX2- 28
SATA_TX2+ 28
SATA_RX3- 22
SATA_RX3+ 22
SATA_TX3- 22
SATA_TX3+ 22
SATA_ACT# 27
SATA HDD
SATA ODD
E-SATA
2ND SATA HDD
For PCH
A A
16Mbit (2M Byte), SPI/
32Mbit (4M Byte), SPI
SPI_CS0#_R
R344 *SHORT_4R344 *SHORT_4
SPI_CLK_R
R638 *SHORT_4R638 *SHORT_4
SPI_SI_R
R352 *SHORT_4R352 *SHORT_4
SPI_SO
R350 *SHORT_4R350 *SHORT_4
5
SPI_CS0#
SPI_CLK
SPI_SI
SPI_SO_R
C406
C406
22P_4
22P_4
50
50
R363
R363
3.3K/F_4
3.3K/F_4
1
6
5
2
3
U27
U27
CE#
VDD
SCK
SI
SO
HOLD#
WP#
VSS
W25X16AVSSIG
W25X16AVSSIG
+3V+3V
R361
R361
3.3K/F_4
C407
C407
0.1U/X7R_4
0.1U/X7R_4
10
10
3.3K/F_4
3
8
7
4
4
iTPM ENABLE/DISABLE
+3V
R358 *1K_4R358 *1K_4
SPI_SI_R
TPM Function R591
Enable Mount
Disable NC
2
(Default)
SATA_DET1#
R369 *0_4R369 *0_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
IBEX PEAK-M 2/6
IBEX PEAK-M 2/6
IBEX PEAK-M 2/6
Date: Sheet
Date: Sheet
Date: Sheet
dGPU_EDIDSEL# 19
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
ZY9
ZY9
ZY9
942Thursday, August 27, 2009
942Thursday, August 27, 2009
1
942Thursday, August 27, 2009
3A
3A
3A
of
of
of
5
IBEX PEAK-M (PCI,USB,NVRAM)
U46E
U46E
H40
AD0
N34
AD1
C44
AD2
A38
AD3
C36
AD4
J34
AD5
A40
AD6
D45
D D
PCI_PIRQA#
TP16TP16
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
TP18TP18
C C
PCI_RST#21
CLK_LPC_DEBUG21
B B
CLK_PCI_77530
CLK_PCI_FB CLK_PCI_FB_C
TP17TP17
TP47TP47
TP62TP62
TP57TP57
TP35TP35
TP15TP15
PCI_RST#
TP25TP25
TP34TP34
TP27TP27
TP29TP29
TP21TP21
TP22TP22
TP20TP20
TP31TP31
TP28TP28
TP67TP67
R540 22_4R540 22_4
T12T12
R221 22_4R221 22_4
R223 22_4R223 22_4
PCI_REQ0#
PCI_REQ1#
dGPU_SELECT#
PCI_REQ3#
PCI_GNT0#
PCI_GNT1#
PCI_GNT2#
PCI_GNT3#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
PCI_SERR#
PCI_PERR#
PCI_IRDY#
PCI_PAR
PCI_DEVSEL#
PCI_FRAME#
PCI_PLOCK#
PCI_STOP#
PCI_TRDY#
ICH_PME#
PCI_PLTRST#
CLK_PCI_PCCARD_C
CLK_PCI_775_CCLK_PCI_775_C
5/21 Change R540,R221 to 22ohm at B-test.
Non-iAMT
A A
PCI_PLTRST#
Add Buffers as needed for
+3V_S5
Loading and fanout concerns.
C595
C595
.1u_4
.1u_4
2
1
U24
U24
3 5
TC7SH08FU
TC7SH08FU
4
5
R357
R357
100K_4
100K_4
PLTRST# 4,16,17,20,21,25,26,30
AD7
E36
AD8
H48
AD9
E40
AD10
C40
AD11
M48
AD12
M45
AD13
F53
AD14
M40
AD15
M43
AD16
J36
AD17
K48
AD18
F40
AD19
C42
AD20
K46
AD21
M51
AD22
J52
AD23
K51
AD24
L34
AD25
F42
AD26
J40
AD27
G46
AD28
F44
AD29
M47
AD30
H36
AD31
J50
C/BE0#
G42
C/BE1#
H47
C/BE2#
G34
C/BE3#
G38
PIRQA#
H51
PIRQB#
B37
PIRQC#
A44
PIRQD#
F51
REQ0#
A46
REQ1# / GPIO50
B45
REQ2# / GPIO52
M53
REQ3# / GPIO54
F48
GNT0#
K45
GNT1# / GPIO51
F36
GNT2# / GPIO53
H53
GNT3# / GPIO55
B41
PIRQE# / GPIO2
K53
PIRQF# / GPIO3
A36
PIRQG# / GPIO4
A48
PIRQH# / GPIO5
K6
PCIRST#
E44
SERR#
E50
PERR#
A42
IRDY#
H44
PAR
F46
DEVSEL#
C46
FRAME#
D49
PLOCK#
D41
STOP#
C48
TRDY#
M7
PME#
D5
PLTRST#
N52
CLKOUT_PCI0
P53
CLKOUT_PCI1
P46
CLKOUT_PCI2
P51
CLKOUT_PCI3
P48
CLKOUT_PCI4
IbexPeak-M_R1P0
IbexPeak-M_R1P0
+3V
USB_OC7#
USB_OC6#
USB_OC5#
USB_OC4#
+3V_S5
PCI_REQ0#
PCI_PIRQB#
PCI_REQ3#
PCI_PIRQD#
PCI_PLOCK#
PCI_SERR#
PCI_DEVSEL#
PCI_STOP#
R227 *1K_4R227 *1K_4
R257 *1K_4R257 *1K_4
R539 10K_4R539 10K_4
R548 8.2K_4R548 8.2K_4
R536 8.2K_4R536 8.2K_4
R230 8.2K_4R230 8.2K_4
+3V
+3V
PCI
PCI
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11
NVRAM
NVRAM
NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15
USB
USB
PCI_GNT0#
PCI_GNT1#
dGPU_SELECT#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
RP10
RP10
6
7
8
9
10
8.2K_10P8R
8.2K_10P8R
RP3
RP3
6
7
8
9
10
8.2K_10P8R
8.2K_10P8R
RP4
RP4
6
7
8
9
10
8.2K_10P8R
8.2K_10P8R
NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3
NV_DQS0
NV_DQS1
NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9
NV_ALE
NV_CLE
NV_RCOMP
NV_RB#
NV_WR#0_RE#
NV_WR#1_RE#
NV_WE#_CK0
NV_WE#_CK1
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USBRBIAS#
USBRBIAS
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
5
4
3
2
1
5
4
3
2
1
5
4
3
2
1
4
AY9
BD1
AP15
BD8
AV9
BG8
AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6
BD3
AY6
AU2
AV7
AY8
AY5
AV11
BF5
H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24
B25
D25
N16
J16
F16
L16
E14
G16
F12
T15
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
PCI_PIRQH#
PCI_TRDY#
PCI_FRAME#
PCI_REQ1#
PCI_PERR#
PCI_PIRQC#
PCI_IRDY#
PCI_PIRQA#
4
NV_ALE 11
NV_CLE 11
USBP0- 28
USBP0+ 28
USBP1- 28
USBP1+ 28
USBP2- 29
USBP2+ 29
USBP3ÂUSBP3+
USBP4- 29
USBP4+ 29
USBP5- 28
USBP5+ 28
USBP6- 28
USBP6+ 28
USBP7- 25
USBP7+ 25
USBP8- 18
USBP8+ 18
USBP9- 21
USBP9+ 21
USBP10ÂUSBP10+
USBP11- 28
USBP11+ 28
USBP12- 28
USBP12+ 28
USBP13- 21
USBP13+ 21
USB_BIAS
R568
R568
22.6/F_4
22.6/F_4
USB_OC0#
R567 0_4R567 0_4
USB_OC1#
USB_OC2#
USB_OC3#CLK_LPC_DEBUG_C
R612 0_4R612 0_4
USB_OC4#
USB_OC5#
R565 0_4R565 0_4
USB_OC6#
R238 0_4R238 0_4
USB_OC7#
+3V_S5
7/1 stuff R614 by intel.
R607 10K_4R607 10K_4
R614 10K_4R614 10K_4
+3V
R222 1K_4R222 1K_4
R224 1K_4R224 1K_4
R533 *10K_4R533 *10K_4
4/9 Stuff R227, R257; remove R222,R224
Boot BIOS Strap
+3V
GNT0# GNT1#
0
0
1
1
3
5/14 Change PCIE sequence beween CN21 and CN23 by BIOS at B-test.
PCIE_RX1-21
PCIE_RX1+21
PCIE_TX1-21
PCIE_TX1+21
PCIE_RX2-21
PCIE_RX2+21
PCIE_TX2-21
PCIE_TX2+21
PCIE_RX4-25
PCIE_RX4+25
PCIE_TX4-25
PCIE_TX4+25
PCIE_RX6-20
PCIE_RX6+20
LAN
PCIE_TX6-20
PCIE_TX6+20
PCIE_RX8-26
PCIE_RX8+26
JMB380
PCIE_TX8-26
PCIE_TX8+26
CLK_PCH_SRC1#21
CLK_PCH_SRC121
CLK_PCIE_REQ1#21
CLK_PCIE_REQ1#_R16
CLK_PCH_SRC2#26
CLK_PCH_SRC226
CLK_PCH_SRC3#21
CLK_PCH_SRC321
CLK_PCIE_REQ3#21
CLK_PCH_SRC4#25
CLK_PCH_SRC425
CLK_PCIE_REQ4#25
CLK_PCIE_REQ4#_R16
CLK_PCIE_LOM#20
LAN
CLK_PCIE_LOM20
CLK_PCIE_LAN_REQ#20
SMBUS
CLK_PCIE_REQ0#
CLK_PCIE_REQ3#
CLK_PCIE_REQ4#
CLK_PCIE_REQ5#
CLK_PCIE_LAN_REQ#
PEG_CLKREQ#_R
CLK_PCIE_REQ1#
Low = A16 swap
override/Top-Block
Swap Override enabled
High = Default
+3V_S5
R58410K_4 R58410K_4
R24710K_4 R24710K_4
R26710K_4 R26710K_4
R2492.2K_4 R2492.2K_4
R5922.2K_4 R5922.2K_4
R5952.2K_4 R5952.2K_4
R2592.2K_4 R2592.2K_4
M/B USB2.0
ESATA USB
Finger Printer
BLUETOOTH
Touch Screen
EXT-USB2
Express Card
Camera
Mini Card (WWAN)
EXT-USB1-1
EXT-USB1-2
Mini Card (WLAN)
Note : place these
resistors near to PCIe
Slots
OC0_1#
CLK_PCIE_REQ2#
PEG_CLKREQ#_R
Boot BIOS Location
LPC
0
Reserved (NAND)
1
PCI
0
SPI
1
OC0_1# 28
OC3# 28
OC5_6# 28
PCI_GNT0#
PCI_GNT1#
PCI_GNT3#
MiniWLAN
Mini TV
Express Card
EHCI1
Mini TV
JMB380
MiniWLAN
EHCI2
Express Card
RSV_SMBALERT#
RSV_SML0ALERT#
RSV_SML1ALERT#
ICH_SMBCLK
ICH_SMBDATA
SMB_CLK_ME0
SMB_DATA_ME0
+3V_S5
R280 10K_4R280 10K_4
R587 10K_4R587 10K_4
R254 10K_4R254 10K_4
R610 10K_4R610 10K_4
R354 10K_4R354 10K_4
R372 *10K_4R372 *10K_4
+3V
R618 10K_4R618 10K_4
A16 swap override Strap/Top-Block
Swap Override jumper
PCI_GNT3#
3
2
IBEX PEAK-M (PCI-E,SMBUS,CLK)
BG30
R538
R538
*1M_4
*1M_4
BJ30
BF29
BH29
AW30
BA30
BC30
BD30
AU30
AT30
AU32
AV32
BA32
BB32
BD32
BE32
BF33
BH33
BG32
BJ32
BA34
AW34
BC34
BD34
AT34
AU34
AU36
AV36
BG34
BJ34
BG36
BJ36
AK48
AK47
P9
AM43
AM45
U4
AM47
AM48
N4
AH42
AH41
A8
AM51
AM53
M9
AJ50
AJ52
H6
AK53
AK51
P13
C563
C563
*18P_4
*18P_4
21
Y5
*25MHzY5*25MHz
C564
C564
*18P_4
*18P_4
2
C600 .1u_4C600 .1u_4
C599 .1u_4C599 .1u_4
C336 .1u_4C336 .1u_4
C337 .1u_4C337 .1u_4
C348 .1u_4C348 .1u_4
C342 .1u_4C342 .1u_4
C334 .1u_4C334 .1u_4
C331 .1u_4C331 .1u_4
C324 .1u_4C324 .1u_4
C325 .1u_4C325 .1u_4
R349 33_4R349 33_4
R346 33_4R346 33_4
R602
R602
R359 33_4R359 33_4
R343 33_4R343 33_4
R335 33_4R335 33_4
R325 33_4R325 33_4
R589
R589
R329 33_4R329 33_4
R333 33_4R333 33_4
R256
R256
R355 33_4R355 33_4
R340 33_4R340 33_4
PCIE_TXN1_C
PCIE_TXP1_C
PCIE_TXN2_C
PCIE_TXP2_C
PCIE_TXN4_C
PCIE_TXP4_C
PCIE_TXN6_C
PCIE_TXP6_C
PCIE_TXN8_C
PCIE_TXP8_C
CLK_PCIE_REQ0#
CLK_PCH_SRC1N
CLK_PCH_SRC1P
CLK_PCIE_REQ1#_R
*SHORT_4
*SHORT_4
CLK_PCH_SRC2N
CLK_PCH_SRC2P
CLK_PCIE_REQ2#
CLK_PCH_SRC3N
CLK_PCH_SRC3P
CLK_PCIE_REQ3#_R
*SHORT_4
*SHORT_4
CLK_PCH_SRC4N
CLK_PCH_SRC4P
CLK_PCIE_REQ4#_R
CLK_PCIE_REQ4#_R
*SHORT_4
*SHORT_4
CLK_PCIE_REQ5#
CLK_PCH_SRC6N
CLK_PCH_SRC6P
XTAL25_IN
XTAL25_OUT
No stuff XTAL25_IN and XTAL25_OUT circuitry
until integrated CG becomes PCH POR.
U46B
U46B
PERN1
PERP1
PETN1
PETP1
PERN2
PERP2
PETN2
PETP2
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4
PERN5
PERP5
PETN5
PETP5
PERN6
PERP6
PETN6
PETP6
PERN7
PERP7
PETN7
PETP7
PERN8
PERP8
PETN8
PETP8
CLKOUT_PCIE0N
CLKOUT_PCIE0P
PCIECLKRQ0# / GPIO73
CLKOUT_PCIE1N
CLKOUT_PCIE1P
PCIECLKRQ1# / GPIO18
CLKOUT_PCIE2N
CLKOUT_PCIE2P
PCIECLKRQ2# / GPIO20
CLKOUT_PCIE3N
CLKOUT_PCIE3P
PCIECLKRQ3# / GPIO25
CLKOUT_PCIE4N
CLKOUT_PCIE4P
PCIECLKRQ4# / GPIO26
CLKOUT_PCIE5N
CLKOUT_PCIE5P
PCIECLKRQ5# / GPIO44
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
PEG_B_CLKRQ# / GPIO56
IbexPeak-M_R1P0
IbexPeak-M_R1P0
2ND_MBCLK30
For EC
2ND_MBDATA30
SML0ALERT# / GPIO60
SML1ALERT# / GPIO74
SMBus
SMBus
PCI-E*
PCI-E*
Link
Link
Controller
Controller
PEG_A_CLKRQ# / GPIO47
PEG
PEG
CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P
From CLK BUFFER
From CLK BUFFER
CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P
CLKIN_PCILOOPBACK
CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67
Clock Flex
Clock Flex
+3V_S5
2
Q31 2N7002DQ31 2N7002D
3
+3V_S5
2
Q59
Q59
3
SMBALERT# / GPIO11
SMBCLK
SMBDATA
SML0CLK
SML0DATA
SML1CLK / GPIO58
SML1DATA / GPIO75
CL_CLK1
CL_DATA1
CL_RST1#
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_BCLK_N
CLKIN_BCLK_P
CLKIN_DOT_96N
CLKIN_DOT_96P
REFCLK14IN
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
R348
R348
2.2K_4
2.2K_4
1
2N7002D
2N7002D
1
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
1
RSV_SMBALERT#
B9
H14
C8
RSV_SML0ALERT#
J14
SMB_CLK_ME0
C6
SMB_DATA_ME0
G8
RSV_SML1ALERT#
M14
SMB_CLK_ME1
E10
SMB_DATA_ME1
G12
CL_CLK1
T13
CL_DATA1
T11
CL_RST1#
T9
PEG_CLKREQ#_R
H1
CLK_PCH_PEGA_N
AD43
CLK_PCH_PEGA_P
AD45
AN4
AN2
AT1
AT3
AW24
BA24
AP3
AP1
F18
E18
AH13
AH12
P41
CLK_PCI_FB
J42
XTAL25_IN
AH51
XTAL25_OUT
AH53
XCLK_RCOMP
AF38
T45
P43
T42
N50
SMB_CLK_ME1
R347
R347
2.2K_4
2.2K_4
SMB_DATA_ME1
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
R228 90.9/F_4R228 90.9/F_4
CLK_FLEX0
CLK_FLEX1
CLK_FLEX2
CLK_FLEX3
USB_OC0# 16
USB_OC1# 16
USB_OC2# 16
USB_OC3# 16
USB_OC4# 16
USB_OC5# 16
USB_OC6# 16
USB_OC7# 16
IBEX PEAK-M 3/6
IBEX PEAK-M 3/6
IBEX PEAK-M 3/6
9/15
T19T19
ICH_SMBCLK 3,16,20,21,25
ICH_SMBDATA 3,16,20,21,25
T15T15
For LAN
R341 *0_4R341 *0_4
SML1ALERT# 11,29,30
For EC
CL_CLK1 21
CL_DATA1 21
CL_RST1# 21
R360 *0_4R360 *0_4
SMB_CLK_ME1
SMB_DATA_ME1
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
1
PEG_CLKREQ# 17
CLK_PCH_PEGA_N 17
CLK_PCH_PEGA_P 17
CLK_PCIE_3GPLL# 4
CLK_PCIE_3GPLL 4
CLK_BUF_PCIE_3GPLL# 3
CLK_BUF_PCIE_3GPLL 3
CLK_BUF_BCLK# 3
CLK_BUF_BCLK 3
CLK_BUF_DREFCLK# 3
CLK_BUF_DREFCLK 3
CLK_BUF_DREFSSCLK# 3
CLK_BUF_DREFSSCLK 3
CLK_ICH_14M 3
+1.05V
T16T16
T13T13
T14T14
T18T18
ZY9
ZY9
ZY9
10 42Thursday, August 27, 2009
10 42Thursday, August 27, 2009
10 42Thursday, August 27, 2009
of
of
of
3A
3A
3A
5
4
3
2
1
IBEX PEAK-M (GPIO,VSS_NCTF,RSVD)
U46F
NV_ALE10
NV_CLE10
NV_ALE
NV_CLE
U46F
Y3
BMBUSY# / GPIO0
C38
TACH1 / GPIO1
D37
TACH2 / GPIO6
J32
TACH3 / GPIO7
F10
GPIO8
K9
LAN_PHY_PWR_CTRL / GPIO12
T7
GPIO15
AA2
SATA4GP / GPIO16
F38
TACH0 / GPIO17
Y7
SCLOCK / GPIO22
H10
GPIO24
AB12
GPIO27
V13
GPIO28
M11
STP_PCI# / GPIO34
V6
SATACLKREQ# / GPIO35
AB7
SATA2GP / GPIO36
AB13
SATA3GP / GPIO37
V3
SLOAD / GPIO38
P3
SDATAOUT0 / GPIO39
H3
PCIECLKRQ6# / GPIO45
F1
PCIECLKRQ7# / GPIO46
AB6
SDATAOUT1 / GPIO48
AA4
SATA5GP / GPIO49
F8
GPIO57
A4
VSS_NCTF_1
A49
VSS_NCTF_2
A5
VSS_NCTF_3
A50
VSS_NCTF_4
A52
VSS_NCTF_5
A53
VSS_NCTF_6
B2
VSS_NCTF_7
B4
VSS_NCTF_8
B52
VSS_NCTF_9
B53
VSS_NCTF_10
BE1
VSS_NCTF_11
BE53
VSS_NCTF_12
BF1
VSS_NCTF_13
BF53
VSS_NCTF_14
BH1
VSS_NCTF_15
BH2
VSS_NCTF_16
BH52
VSS_NCTF_17
BH53
VSS_NCTF_18
BJ1
VSS_NCTF_19
BJ2
VSS_NCTF_20
BJ4
VSS_NCTF_21
BJ49
VSS_NCTF_22
BJ5
VSS_NCTF_23
BJ50
VSS_NCTF_24
BJ52
VSS_NCTF_25
BJ53
VSS_NCTF_26
D1
VSS_NCTF_27
D2
VSS_NCTF_28
D53
VSS_NCTF_29
E1
VSS_NCTF_30
E53
VSS_NCTF_31
IbexPeak-M_R1P0
IbexPeak-M_R1P0
R586 *1K_4R586 *1K_4
R606 *1K_4R606 *1K_4
High = Enable
Low = Disable
Set to Vcc when LOW
Set to Vcc/2 when HIGH
4
MISC
MISC
CLKOUT_BCLK0_N / CLKOUT_PCIE8N
CLKOUT_BCLK0_P / CLKOUT_PCIE8P
GPIO
GPIO
CPU
CPU
NCTF
NCTF
RSVD
RSVD
+1.8V
CLKOUT_PCIE6N
CLKOUT_PCIE6P
CLKOUT_PCIE7N
CLKOUT_PCIE7P
A20GATE
PECI
RCIN#
PROCPWRGD
THRMTRIP#
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
NC_1
NC_2
NC_3
NC_4
NC_5
INIT3_3V#
TP24
5/12 Reverse Q12,Q11 connect to t SYS_SHDN# at B-test
BMBUSY#16
SIO_EXT_SMI#30
SIO_EXT_SCI#30
7/1 change board_id0 to GPIO7 at C-test
D D
TP60TP60
CR_WAKE#26
dGPU_HOLD_RST#16,17
SATA5GP16
SML1ALERT#10,29,30
BOARD_ID0
GPIO27
RSV_GPIO8
GPIO57
R229 *SHORT_4R229 *SHORT_4
TP69TP69
TP58TP58
TP_PCH_GPIO2816
SAVE_LED#28
dGPU_PWR_EN#16
dGPU_PRSNT#16,17
R428 *0_4R428 *0_4
R351 0_4R351 0_4
R640 10K_4R640 10K_4
R669 *10K_4R669 *10K_4
R670 *1K_4R670 *1K_4
R671 10K_4R671 10K_4
dGPU_RUNPWROK17
7/1 GPIO24 NC for Intel
suggestion at C-test.
8/8 Reserve R428 from GPIO46 by
intel S3 suggestion at Ramp.
C C
DDR3_DRAMRST#_EC30,37
5/12 Reverse R351 connect to EC for Temp Alert at B-test
SATA5GP / GPIO49 / TEMP_ALERT# is used to
alert for EC when CPU or Graph/Memory
controllers' temperature go out of limit.
So connecting GPIO49 to EC and avoid this
pin to be used for other purpose
B B
R641 *10K_4R641 *10K_4
+3V_S5
4/9 Reserve GPIO8 by ww14 MoW
A A
7/1 Add R671 for GPIO57 PD and not PU for Intel
suggestion at C-test.
BMBUSY#
SIO_EXT_SMI#
SIO_EXT_SCI#
BOARD_ID0
RSV_GPIO8
LAN_DISABLE#
CR_WAKE#
dGPU_HOLD_RST#
dGPU_RUNPWROK_R
GPIO22
GPIO24
GPIO27
STP_PCI#
SAVE_LED#
dGPU_PWR_EN#
dGPU_PRSNT#
GPIO38
GPIO39
GPIO45
GPIO46
SV_SET_UP
SATA5GP
GPIO57
Danbury Technology Enabled
Integrated Clock Chip Enable
RSV_GPIO8
BOARD_ID0
High = Disable
Low = Enable
High = Touch Screen
Low = Discrete
5
DMI Termination Voltage
AH45
AH46
AF48
AF47
U2
AM3
AM1
PCH_PECI_R
BG10
T1
BE10
PCH_THRMTRIP#_R
BD10
BA22
AW22
BB22
AY45
AY46
AV43
AV45
AF13
M18
N18
AJ24
AK41
AK42
M32
N32
M30
N30
H12
AA23
AB45
AB38
AB42
AB41
T39
P6
C10
DELAY_VR_PWRGOOD8,33
3
TP_PCH_PCIE6N
TP_PCH_PCIE6P
TP_PCH_PCIE7N
TP_PCH_PCIE7P
TP1_PCH
TP2_PCH
TP_INT3_3V
TP49TP49
TP50TP50
TP51TP51
TP44TP44
R581 *SHORT_4R581 *SHORT_4
R252 56/F_4R252 56/F_4
TP41TP41
TP40TP40
TP68TP68
2
PM_THRMTRIP#
+1.1V_VTT
3
1
2
1 3
SIO_A20GATE 30
CLK_CPU_BCLK# 4
CLK_CPU_BCLK 4
H_PECI 4
SIO_RCIN# 30
H_PWRGOOD 4,16
Q12
Q12
*2N7002D
*2N7002D
Q11
Q11
*MMBT3904
*MMBT3904
+1.1V_VTT
R251
R251
56/F_4
56/F_4
SYS_SHDN# 32,41
2
PM_THRMTRIP# 4
Del R231 at C-test.
CR_WAKE#
RSV_GPIO8
TP_PCH_GPIO28
GPIO45
GPIO46
GPIO57
LAN_DISABLE#
SIO_EXT_SMI#
SIO_EXT_SCI#
dGPU_PWR_EN#
dGPU_RUNPWROK_R
SIO_RCIN#
SIO_A20GATE
dGPU_HOLD_RST#
SATA5GP
GPIO22
dGPU_PRSNT#
SAVE_LED#
STP_PCI#
GPIO39
GPIO38
BMBUSY#
SV_SET_UP
R275 1K_4R275 1K_4
R258 10K_4R258 10K_4
R634 10K_4R634 10K_4
R625 10K_4R625 10K_4
R624 10K_4R624 10K_4
R621 *10K_4R621 *10K_4
R285 10K_4R285 10K_4
R551 10K_4R551 10K_4
R278 10K_4R278 10K_4
R631 10K_4R631 10K_4
R330 10K_4R330 10K_4
R601 10K_4R601 10K_4
R616 10K_4R616 10K_4
R282 10K_4R282 10K_4
R605 10K_4R605 10K_4
R276 10K_4R276 10K_4
R604 10K_4R604 10K_4
R277 10K_4R277 10K_4
R623 10K_4R623 10K_4
R600 10K_4R600 10K_4
R603 10K_4R603 10K_4
+1.1V_VTT4,6,7,12,16,34,37
+1.05V3,10,12,16,22,35,37
+3V3,4,8,9,10,12,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,32,33,34,35,37
+3V_S58,9,10,12,14,15,16,20,25,27,29,30,32,37
+1.8V6,12,37
R371 8.2K_4R371 8.2K_4
R283 10K_4R283 10K_4
SV_SET_UP 1-X High = Strong (Default)
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
IBEX PEAK-M 4/6
IBEX PEAK-M 4/6
IBEX PEAK-M 4/6
Date: Sheet
Date: Sheet
Date: Sheet
PROJECT :
ZY9
ZY9
ZY9
11 42Thursday, August 27, 2009
11 42Thursday, August 27, 2009
11 42Thursday, August 27, 2009
of
of
1
of
+3V_S5
+3V
+3V
+3V
3A
3A
3A
IBEX PEAK-M (POWER)
VCCCORE = 1.432A(80mils)
D D
40mA(15mils)
R552 0_2512R552 0_2512
+1.05V
VCCIO = 3.062A(150mils)
C C
B B
5
+1.05V
+1.05V
+1.05V
SMR2512
37mA(15mils)
R226 *SHORT_8R226 *SHORT_8
R546 *SHORT_8R546 *SHORT_8
R239 *SHORT_6R239 *SHORT_6
L48 *1uH_6L48 *1uH_6
C613 *10u/6.3V_6C613 *10u/6.3V_6
+V1.1LAN_VCC_EXP
L59 *1uH_6L59 *1uH_6
+1.05V_VCCCORE_ICH
C335 1u/10V_4C335 1u/10V_4
C338 10u/6.3V_6C338 10u/6.3V_6
+1.05V_PCH_VCCDPLL_EXP
+V1.1LAN_VCCAPLL_EXP
C339 1u/10V_4C339 1u/10V_4
C343 1u/10V_4C343 1u/10V_4
C344 1u/10V_4C344 1u/10V_4
C346 1u/10V_4C346 1u/10V_4
C609 10u/6.3V_6C609 10u/6.3V_6
+V1.1LAN_VCCAPLL_FDI
C627
C627
*10u/6.3V_6
*10u/6.3V_6
+V1.5S_1.8S
+1.05V
U46G
U46G
AB24
VCCCORE[1]
AB26
VCCCORE[2]
AB28
VCCCORE[3]
AD26
VCCCORE[4]
AD28
VCCCORE[5]
AF26
VCCCORE[6]
AF28
VCCCORE[7]
AF30
VCCCORE[8]
AF31
VCCCORE[9]
AH26
VCCCORE[10]
AH28
VCCCORE[11]
AH30
VCCCORE[12]
AH31
VCCCORE[13]
AJ30
VCCCORE[14]
AJ31
VCCCORE[15]
AK24
VCCIO[24]
BJ24
VCCAPLLEXP
AN20
VCCIO[25]
AN22
VCCIO[26]
AN23
VCCIO[27]
AN24
VCCIO[28]
AN26
VCCIO[29]
AN28
VCCIO[30]
BJ26
VCCIO[31]
BJ28
VCCIO[32]
AT26
VCCIO[33]
AT28
VCCIO[34]
AU26
VCCIO[35]
AU28
VCCIO[36]
AV26
VCCIO[37]
AV28
VCCIO[38]
AW26
VCCIO[39]
AW28
VCCIO[40]
BA26
VCCIO[41]
BA28
VCCIO[42]
BB26
VCCIO[43]
BB28
VCCIO[44]
BC26
VCCIO[45]
BC28
VCCIO[46]
BD26
VCCIO[47]
BD28
VCCIO[48]
BE26
VCCIO[49]
BE28
VCCIO[50]
BG26
VCCIO[51]
BG28
VCCIO[52]
BH27
VCCIO[53]
AN30
VCCIO[54]
AN31
VCCIO[55]
AN35
+3V
+1.05V
+1.8V
AT22
BJ18
AM23
+3V
VCC3_3[1]
VCCVRM[1]
VCCFDIPLL
VCCIO[1]
IbexPeak-M_R1P0
IbexPeak-M_R1P0
R240 *0_4R240 *0_4
R574 *0_4R574 *0_4
R573 0_4R573 0_4
R264 0_8R264 0_8
R281 *0_8R281 *0_8
9/5
L39 10uHL39 10uH
+1.05V
L40 10uHL40 10uH
A A
C304
C304
220U
220U
+V1.1LAN_VCCA_B_DPL
C309
C309
220U
220U
4
POWER
POWER
VCC CORE
VCC CORE
DMI
DMI
PCI E*
PCI E*
NAND / SPI
NAND / SPI
FDI
FDI
+V1.1LAN_VCCA_A_DPL
+
+
C568
C568
1u/10V_4
1u/10V_4
+
+
C573
C573
1u/10V_4
1u/10V_4
VCCADAC[1]
VCCADAC[2]
VSSA_DAC[1]
CRTLVDS
CRTLVDS
VSSA_DAC[2]
VCCALVDS
VSSA_LVDS
VCCTX_LVDS[1]
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]
VCC3_3[2]
VCC3_3[3]
VCC3_3[4]
HVCMOS
HVCMOS
VCCVRM[2]
VCCDMI[1]
VCCDMI[2]
VCCPNAND[1]
VCCPNAND[2]
VCCPNAND[3]
VCCPNAND[4]
VCCPNAND[5]
VCCPNAND[6]
VCCPNAND[7]
VCCPNAND[8]
VCCPNAND[9]
VCCME3_3[1]
VCCME3_3[2]
VCCME3_3[3]
VCCME3_3[4]
196mA(15mils)
+V1.5S_1.8S+1.5V
+V_NVRAM_VCCQ
156mA(15mils)
68mA(15mils)
69mA(15mils)
+VCCA_DAC_1_2
AE50
AE52
AF53
AF51
AH38
AH39
AP43
AP45
AT46
AT45
AB34
AB35
AD35
AT24
AT16
AU16
AM16
AK16
AK20
AK19
AK15
AK13
AM12
AM13
AM15
AM8
AM9
AP11
AP9
C569
C569
0.01u/16V_4
0.01u/16V_4
+3V_VCC_GIO
C327
C327
.1u/16V_4
.1u/16V_4
VCCVRM= 196mA(15mils)
+VCCVRM
R334 *SHORT_6R334 *SHORT_6
+VCCDM
C364
C364
1u/10V_4
1u/10V_4
C353
C353
.1u/16V_4
.1u/16V_4
+3V_VCCME_SPI
C367
C367
.1u/16V_4
.1u/16V_4
L31
L31
BKP1608HS181T_6_1.5A
BKP1608HS181T_6_1.5A
C565
C565
C561
C561
10u/6.3V_6
10u/6.3V_6
.1u/16V_4
.1u/16V_4
VCCALVDS= 59mA(15mils)
R332 *SHORT_6R332 *SHORT_6
VCC3_3 = 0.357A(30mils)
R245 0_4R245 0_4
R248 *0_4R248 *0_4
+V1.5S_1.8S
+3V
+1.1V_VTT
+1.05V
VCCPNAND= 156mA(15mils)
+V_NVRAM_VCCQ
VCCME3_3= 85mA(15mils)
R326 *SHORT_6R326 *SHORT_6
+3V
3
VCCADAC= 69mA(15mils)
+3V
VCCLAN = 0.32A(30mils)
VCCME = 1.849A(100mils)
R531 *SHORT_8R531 *SHORT_8
+1.05V
R208 *SHORT_8R208 *SHORT_8
VCCDMI= 61mA(15mils)
VCCIO = 3.062A(150mils)
VCCSUS3_3 = 0.163A(20mils)
VCC3_3 = 0.357A(30mils)
V_CPU >1mA(15mils)
VCCRTC= 2mA(15mils)
VCCACLK= 52mA(15mils)
L37 *10uHL37 *10uH
+1.05V
R327 *SHORT_6R327 *SHORT_6
+1.05V
C350
C350
1u/10V_4
1u/10V_4
+V1.5S_1.8S
R339 *SHORT_6R339 *SHORT_6
+1.05V
R243 *SHORT_6R243 *SHORT_6
+3V_S5
R345 *SHORT_6R345 *SHORT_6
+3V
R342 *SHORT_6R342 *SHORT_6
+1.1V_VTT
+RTC_CELL
+V1.1LAN_VCCA_CLK
C558 *10u/6.3V_6C558 *10u/6.3V_6
C559 *1u/6.3V_4C559 *1u/6.3V_4
TP_PCH_VCCDSW
C351
C351
.1u/16V_4
.1u/16V_4
+1.05V_VCCEPW
C306 22U_8C306 22U_8
C307 22U_8C307 22U_8
C321 1u/10V_4C321 1u/10V_4
C329 1u/10V_4C329 1u/10V_4
C369 .1u/16V_4C369 .1u/16V_4
+V1.1LAN_VCCA_A_DPL
+V1.1LAN_VCCA_B_DPL
C330 1u/10V_4C330 1u/10V_4
C332 1u/10V_4C332 1u/10V_4
C328 1u/10V_4C328 1u/10V_4
C365 .1u/16V_4C365 .1u/16V_4
+V1.1LAN_INT_VCCSUS
C358 4.7U/10V_8C358 4.7U/10V_8
C359 .1u/16V_4C359 .1u/16V_4
C368 .1u/16V_4C368 .1u/16V_4
+VCCRTCEXT
+1.05V_SSCVCC
+VCCSST
+3V_S5_VCCPSUS
.1u/16V_4C354 .1u/16V_4C354
+3V_VCCPCORE
C356
C356
.1u/16V_4
.1u/16V_4
+VTT_VCCPCPU
C637
C637
.1u/16V_4
.1u/16V_4
2
AP51
AP53
AF23
AF24
Y20
AD38
AD39
AD41
AF43
AF41
AF42
V39
V41
V42
Y39
Y41
Y42
AU24
BB51
BB53
BD51
BD53
AH23
AJ35
AH35
AF34
AH34
AF32
V12
Y22
P18
U19
U20
U22
V15
V16
Y16
AT18
AU18
A12
C360
C360
.1u/16V_4
.1u/16V_4
U46J
U46J
VCCACLK[1]
VCCACLK[2]
VCCLAN[1]
VCCLAN[2]
DCPSUSBYP
VCCME[1]
VCCME[2]
VCCME[3]
VCCME[4]
VCCME[5]
VCCME[6]
VCCME[7]
VCCME[8]
VCCME[9]
VCCME[10]
VCCME[11]
VCCME[12]
V9
DCPRTC
VCCVRM[3]
VCCADPLLA[1]
VCCADPLLA[2]
VCCADPLLB[1]
VCCADPLLB[2]
VCCIO[21]
VCCIO[22]
VCCIO[23]
VCCIO[2]
VCCIO[3]
VCCIO[4]
DCPSST
DCPSUS
VCCSUS3_3[29]
VCCSUS3_3[30]
VCCSUS3_3[31]
VCCSUS3_3[32]
VCC3_3[5]
VCC3_3[6]
VCC3_3[7]
V_CPU_IO[1]
V_CPU_IO[2]
VCCRTC
IbexPeak-M_R1P0
IbexPeak-M_R1P0
POWER
POWER
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
USB
USB
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
VCCSUS3_3[21]
VCCSUS3_3[22]
VCCSUS3_3[23]
VCCSUS3_3[24]
VCCSUS3_3[25]
VCCSUS3_3[26]
VCCSUS3_3[27]
VCCSUS3_3[28]
Clock and Miscellaneous
Clock and Miscellaneous
PCI/GPIO/LPC
PCI/GPIO/LPC
VCCSATAPLL[1]
VCCSATAPLL[2]
SATA
SATA
PCI/GPIO/LPC
PCI/GPIO/LPC
CPU
CPU
RTC
RTC
HDA
HDA
VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]
VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCCSUS3_3[6]
VCCSUS3_3[7]
VCCSUS3_3[8]
VCCSUS3_3[9]
VCCIO[56]
V5REF_SUS
V5REF
VCC3_3[8]
VCC3_3[9]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
VCC3_3[14]
VCCIO[9]
VCCVRM[4]
VCCIO[10]
VCCIO[11]
VCCIO[12]
VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]
VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]
VCCME[13]
VCCME[14]
VCCME[15]
VCCME[16]
VCCSUSHDA
V24
V26
Y24
Y26
V28
U28
U26
U24
P28
P26
N28
N26
M28
M26
L28
L26
J28
J26
H28
H26
G28
G26
F28
F26
E28
E26
C28
C26
B27
A28
A26
U23
V23
F24
K49
J38
L38
M36
N36
P36
U35
AD13
AK3
AK1
AH22
AT20
AH19
AD20
AF22
AD19
AF20
AF19
AH20
AB19
AB20
AB22
AD22
AA34
Y34
Y35
AA35
L30
1
VCCIO = 3.062A(150mils)
+1.05V_VCCUSBCORE
C340 1u/10V_4C340 1u/10V_4
+3V_S5_VCCPUSB+1.05V_VCCAUX
C610
C610
0.022U
0.022U
R331 *SHORT_6R331 *SHORT_6
C349
C349
.1u/16V_4
.1u/16V_4
VCCSUS3_3 = 0.163A(20mils)
V5REF_SUS< 1mA
R237 100/F_4R237 100/F_4
D20 RB500V-40D20 RB500V-40
R209 100/F_4R209 100/F_4
D19 RB500V-40D19 RB500V-40
R336 *SHORT_6R336 *SHORT_6
VCC3_3 = 0.357A(30mils)
+3V+1.05V
+V1.1LAN_VCCAPLL
C660
C660
+V1.1LAN_VCC_SATA
*10u/6.3V_6
*10u/6.3V_6
+3V_VCCPPCI
C659
C659
*1u/6.3V_4
*1u/6.3V_4
+1.05V
C347
C347
1u/16V_6
1u/16V_6
C317
C317
1u/16V_6
1u/16V_6
C333
C333
.1u/16V_4
.1u/16V_4
C326
C326
.1u/16V_4
.1u/16V_4
+V1.5S_1.8S
VCCIO = 3.062A(150mils)
VCCME = 1.849A(100mils)
+1.05V_VCCEPW
+V3.3A_1.5A_HDA_IO
C341
C341
1u/10V_4
1u/10V_4
VCCSUSHDA= 6mA(15mils)
+1.05V
R328 *SHORT_6R328 *SHORT_6
C612
C612
.1u/16V_4
.1u/16V_4
V5REF< 1mA
+3V
31mA(15mils)
L58 *10uHL58 *10uH
R622 *SHORT_12R622 *SHORT_12C352 .1u/16V_4C352 .1u/16V_4
C357
C357
1u/10V_4
1u/10V_4
R232*0_4 R232*0_4
R2360_4 R2360_4
+3V_S5
+5V_S5
+3V_S5
+5V
+3V
+1.5VSUS
+3V_S5
+1.05V
+1.05V
+1.1V_VTT4,6,7,11,16,34,37
+1.5VSUS4,14,15,22,36,37
+5V_S59,22,28,32,33,34,35,36
+1.05V3,10,16,22,35,37
+3V3,4,8,9,10,11,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,32,33,34,35,37
+3V_S58,9,10,11,14,15,16,20,25,27,29,30,32,37
5
+1.8V6,11,37
4
3
2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
IBEX PEAK-M 5/6
IBEX PEAK-M 5/6
IBEX PEAK-M 5/6
Date: Sheet
Date: Sheet
Date: Sheet
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
1
ZY9
ZY9
ZY9
of
of
of
12 42Thursday, August 27, 2009
12 42Thursday, August 27, 2009
12 42Thursday, August 27, 2009
3A
3A
3A
5
IBEX PEAK-M (GND)
D D
U46H
U46H
AB16
VSS[0]
AA19
VSS[1]
AA20
VSS[2]
AA22
VSS[3]
AM19
VSS[4]
AA24
VSS[5]
AA26
VSS[6]
AA28
VSS[7]
AA30
VSS[8]
AA31
VSS[9]
AA32
VSS[10]
AB11
VSS[11]
AB15
VSS[12]
AB23
VSS[13]
AB30
VSS[14]
AB31
VSS[15]
AB32
VSS[16]
AB39
VSS[17]
AB43
VSS[18]
AB47
AC52
AD11
AD12
AD16
AD23
AD30
AD31
AD32
AD34
AU22
AD42
AD46
AD49
AF12
AH49
AF35
AP13
AN34
AF45
AF46
AF49
AG52
AH11
AH15
AH16
AH24
AH32
AV18
AH43
AH47
AJ19
AJ20
AJ22
AJ23
AJ26
AJ28
AJ32
AJ34
AK12
AM41
AN19
AK26
AK22
AK23
AK28
AB5
AB8
AC2
AD7
AE2
AE4
Y13
AU4
AF5
AF8
AG2
AH7
AJ2
AT5
AJ4
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
IbexPeak-M_R1P0
IbexPeak-M_R1P0
C C
B B
A A
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
4
AK30
AK31
AK32
AK34
AK35
AK38
AK43
AK46
AK49
AK5
AK8
AL2
AL52
AM11
BB44
AD24
AM20
AM22
AM24
AM26
AM28
BA42
AM30
AM31
AM32
AM34
AM35
AM38
AM39
AM42
AU20
AM46
AV22
AM49
AM7
AA50
BB10
AN32
AN50
AN52
AP12
AP42
AP46
AP49
AP5
AP8
AR2
AR52
AT11
BA12
AH48
AT32
AT36
AT41
AT47
AT7
AV12
AV16
AV20
AV24
AV30
AV34
AV38
AV42
AV46
AV49
AV5
AV8
AW14
AW18
AW2
BF9
AW32
AW36
AW40
AW52
AY11
AY43
AY47
BG12
BB12
BB16
BB20
BB24
BB30
BB34
BB38
BB42
BB49
BC10
BC14
BC18
BC22
BC32
BC36
BC40
BC44
BC52
BD48
BD49
BE12
BE16
BE20
BE24
BE30
BE34
BE38
BE42
BE46
BE48
BE50
BF49
BF51
BG18
BG24
BG50
BH11
BH15
BH19
BH23
BH31
BH35
BH39
BH43
BH47
AF39
AY7
B11
B15
B19
B23
B31
B35
B39
B43
B47
BB5
BC2
BH9
BD5
BE6
BE8
BF3
BG4
BH7
C12
C50
D51
E12
E16
E20
E24
E30
E34
E38
E42
E46
E48
F49
G10
G14
G18
G22
G32
G36
G40
G44
G52
H16
H20
H30
H34
H38
H42
3
U46I
U46I
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
B7
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
E6
VSS[238]
E8
VSS[239]
VSS[240]
F5
VSS[241]
VSS[242]
VSS[243]
VSS[244]
G2
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[326]
VSS[327]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[332]
VSS[333]
VSS[334]
VSS[335]
VSS[336]
VSS[337]
VSS[338]
VSS[339]
VSS[340]
VSS[341]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
VSS[353]
VSS[354]
VSS[355]
VSS[356]
VSS[366]
H49
H5
J24
K11
K43
K47
K7
L14
L18
L2
L22
L32
L36
L40
L52
M12
M16
M20
N38
M34
M38
M42
M46
M49
M5
M8
N24
P11
AD15
P22
P30
P32
P34
P42
P45
P47
R2
R52
T12
T41
T46
T49
T5
T8
U30
U31
U32
U34
P38
V11
P16
V19
V20
V22
V30
V31
V32
V34
V35
V38
V43
V45
V46
V47
V49
V5
V7
V8
W2
W52
Y11
Y12
Y15
Y19
Y23
Y28
Y30
Y31
Y32
Y38
Y43
Y46
P49
Y5
Y6
Y8
P24
T43
AD51
AT8
AD47
Y47
AT12
AM6
AT13
AM5
AK45
AK39
AV14
2
1
IbexPeak-M_R1P0
IbexPeak-M_R1P0
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
IBEX PEAK-M 6/6
IBEX PEAK-M 6/6
IBEX PEAK-M 6/6
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
ZY9
ZY9
ZY9
of
of
of
13 42Thursday, August 27, 2009
13 42Thursday, August 27, 2009
13 42Thursday, August 27, 2009
1
3A
3A
3A
Loading...