Acer Aspire 5741 Schematics

A

B

C

D

E

www.rosefix.com

1 1

Compal Confidential

2 2

NEW70 / 80 / 90 / 50 <LA-5892P> M/B Schematics Document

PEW51 <LA-5892P> M/B Schematics Document

Intel Arrandale Processor with DDRIII + Ibex Peak-M

3 3

2010-06-09

REV:1.0

4 4

A

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/5/12 2010/04/15

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A5892

401826

of

149Tuesday, June 22, 2010

E

C

A

Compal Confidential

Model Name NEW70 / 80 / 90 / 50

www.rosefix.com

File Name : LA-5892P

1 1

B

ZZZ

ZZZ DAZ0C900200

DAZ0C900200

PCB NEW70 LA-5892P

ZZZ1

ZZZ1 RO0000003HM46@

RO0000003HM46@

HDMI+HDCP LOGO

C

D

E

Fan Control

page 26

Intel

Arrandale (UMA)

Processor rPGA988A

page 4,5,6,7,8,9

(UMA)

100MHz

2.7GT/s

2 2

LVDS Conn.

page 22

CRT Conn.

HDMI Conn.

page 24

3 3

Level Shift

page 24

page 23

PCI-Express x 8 (ABD PCIE1 2.5GT/S CKD PCIE1/2 2.5/5GT/S)

port 2,4 port 1

MINI Card x2

WLAN, 3G

page 26

RTC CKT. LS-5891P

LVDS(UMA)

CRT(UMA)

HDMI(UMA)

LAN(GbE)

BCM57780

page 27

RJ45

page 28

100MHz

Intel

Ibex Peak-M

PCH

page 13,14,15,16,17 18,19,20,21

LPC BUS

ENE KB926

DMI x4FDI x8

100MHz 1GB/s x4

33MHz

page 30

Memory BUS(DDRIII)

Dual Channel

1.5V DDRIII 800/1066/1333

6.4G/8.5G/10.6G 100M/133M/166M(CFD)

USB conn x3

USB port 0 (sub board) USB Port 1 Left side USB port 2 (sub board)

USBx14

HD Audio

3.3V 48MHz

3.3V 24MHz

SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S)

SPI

SPI ROM x2

page 13

SATA HDD Conn.

page 25

Bluetooth Conn

port 0

204pin DDRIII-SO-DIMM X2

BANK 0, 1, 2, 3

CMOS Camera

page 29page 39 page 22

100MHz

USB port 8USB port 11

page 10,11

Mini card

USB port 12 USB port 13

page 39

HDA Codec

port 1

SATA ODD Conn.

page 25

Audio AMP

Int. Speaker

ALC888

page 33

APA2051

page 34

Card Reader

USB port 9

page 39

Power ON/Off CKT.

DC/DC Interface CKT.

Power Circuit DC/DC CKT.

4 4

A

LS-5892P

LS-5893P

LS-5894P

LS-5895P

Touch Pad

page 31

Int.KBD

page 31

Clock Generator

IDT: 9LRS3199AKLFT SILEGO: SLG8SP587

BIOS ROM

page 31

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/5/12 2010/04/15

Compal Secret Data

133/120/100/96/14.318MHZ to PCH 48MHZ to CardReader

Deciphered Date

page 12

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A5892

401826

C

of

249Tuesday, June 22, 2010

E

A

Voltage Rails

Power Plane Description

VIN

1 1

2 2

B+ +CPU_CORE +0.75VS 0.75V switched power rail for DDR terminator +1.05VS +1.05VS_VTT 1.05V switched power rail (1.05 for AUB CPU) ON OFF OFF +1.5V 1.5V power rail for DDRIII ON ON OFF +1.5VS +1.8VS 1.8V switched power rail +3VALW 3.3V always on power rail

+3V_LAN 3.3V power rail for LAN ON ON +3VS +5VALW +5VS +5V 5V power rail for PCH +VSB VSB always on power rail ON ON* +RTCVCC RTC power

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

www.rosefix.com

Adapter power supply (19V) AC or battery power rail for power circuit. Core voltage for CPU

1.05V switched power rail for PCH

1.5V switched power rail

3.3V switched power rail 5V always on power rail 5V switched power rail

B

S1

S3 S5

N/A N/A N/A

ON ON ON OFF OFF

ON OFF OFF ON ON

ON ON

ON ON ON ON ON

N/AN/AN/A OFF

ON

OFF

OFF ON ON*

ON* OFF

OFF ON

ON* OFFON

OFF

ONON

C

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

SLP_S1# SLP_S3#

HIGH HIGH HIGH HIGH

LOW

LOW LOW LOW LOW

SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH

LOW

D

HIGHHIGHHIGH

HIGH

LOWLOWLOW

Project ID / Board ID Table for EC-AD channel

Vcc 3.3V +/- 5%

0 1 2 3 4 5 6 7NC

BTO Option Table

100K +/- 5%Ra/Rc

Rb / Rd V min

0

8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

AD_BID

V typ

0 V 0 V

0.503 V

0.819 V

1.185 V 1.264 V

2.200 V

3.300 V

BOM Config

ON

V

AD_BID

0.538 V

0.875 V

2.341 V

3.300 V

ON

OFF

max

ON ON

ON

OFF

0.1

0.2

0.3

1.0

E

LOW

OFF

Project IDBoard ID

NEWX0 PEW51

BTO Item BOM Structure

External PCI Devices

Device IDSEL# REQ#/GNT# Interrupts

EC SM Bus1 address

Device

Smart Battery

Address Address

0001 011X b

EC SM Bus2 address

Device

HDMI 3G 9050@ 7080@ For NEWX0 ID For PEW51 ID

HDMI@ 3G@ NEW90 / NEW50 NEW70 / NEW80 NEWX0@ PEW51@

Ibex SM Bus address

3 3

Device Address

Clock Generator (9LRS3199AKLFT, SLG8SP587)

DDR DIMM0 DDR DIMM2

1101 0010b

1001 000Xb 1001 010Xb

USB Port Table

USB 2.0 USB 1.1 Port

UHCI0

0 1 2

4 External USB Port

Ext1 USB

Ext2 USB

3 External USB Port

Ext1 USB Ext3 HS USBExt3 HS USB Ext2 USB

UHCI1

EHCI1

UHCI2

3 4 5 6

UHCI3

UHCI4

EHCI2

4 4

A

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

UHCI5

UHCI6

2009/08/01 2010/08/01

C

7

8

Camera

9

Card Reader

10

SIM CARD SIM CARD

11

Blue Tooth Blue Tooth

12

1st Min-Card

13

2st Min-Card

Compal Secret Data

Deciphered Date

Camera Card Reader

1st Min-Card 2st Min-Card

D

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A5892

401826

of

349Tuesday, June 22, 2010

E

C

5

JCPU1A

www.rosefix.com

DMI_PTX_HRX_N0 DMI_PTX_HRX_N1 DMI_PTX_HRX_N2 DMI_PTX_HRX_N3

DMI_PTX_HRX_P0 DMI_PTX_HRX_P1 DMI_PTX_HRX_P2

H_FDI_INT<15>

DMI_PTX_HRX_P3 DMI_HTX_PRX_N0

DMI_HTX_PRX_N1 DMI_HTX_PRX_N2 DMI_HTX_PRX_N3

DMI_HTX_PRX_P0 DMI_HTX_PRX_P1 DMI_HTX_PRX_P2 DMI_HTX_PRX_P3

H_FDI_TXN0 H_FDI_TXN1 H_FDI_TXN2 H_FDI_TXN3 H_FDI_TXN4 H_FDI_TXN5 H_FDI_TXN6 H_FDI_TXN7

H_FDI_TXP0 H_FDI_TXP1 H_FDI_TXP2 H_FDI_TXP3 H_FDI_TXP4 H_FDI_TXP5 H_FDI_TXP6 H_FDI_TXP7

D D

C C

H_FDI_FSYNC0<15> H_FDI_FSYNC1<15>

H_FDI_LSYNC0<15> H_FDI_LSYNC1<15>

B B

A24

DMI_RX#[0]

C23

DMI_RX#[1]

B22

DMI_RX#[2]

A21

DMI_RX#[3]

B24

DMI_RX[0]

D23

DMI_RX[1]

B23

DMI_RX[2]

A22

DMI_RX[3]

D24

DMI_TX#[0]

G24

DMI_TX#[1]

F23

DMI_TX#[2]

H23

DMI_TX#[3]

D25

DMI_TX[0]

F24

DMI_TX[1]

E23

DMI_TX[2]

G23

DMI_TX[3]

E22

FDI_TX#[0]

D21

FDI_TX#[1]

D19

FDI_TX#[2]

D18

FDI_TX#[3]

G21

FDI_TX#[4]

E19

FDI_TX#[5]

F21

FDI_TX#[6]

G18

FDI_TX#[7]

D22

FDI_TX[0]

C21

FDI_TX[1]

D20

FDI_TX[2]

C18

FDI_TX[3]

G22

FDI_TX[4]

E20

FDI_TX[5]

F20

FDI_TX[6]

G19

FDI_TX[7]

F17

FDI_FSYNC[0]

E17

FDI_FSYNC[1]

C17

FDI_INT

F18

FDI_LSYNC[0]

D17

FDI_LSYNC[1]

IC,AUB_CFD_rPGA,R1P0

IC,AUB_CFD_rPGA,R1P0 CONN@

CONN@

DMI Intel(R) FDI

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RBIAS PEG_RX#[0]

PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]

PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14]

PCI EXPRESS -- GRAPHICS

PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

B26 A26 B27 A25

K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31

J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30

L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26

L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25

4

PEG_IRCOMP

EXP_RBIAS

1 2

R1 49.9_0402_1%R1 49.9_0402_1%

1 2

R3 750_0402_1%R3 750_0402_1%

3

WW41 Recommend not pull down PCIE2.0 Jitter is over on ES1

R5

3.01K_0402_1% @

3.01K_0402_1% @ R6

R6

3.01K_0402_1% @

3.01K_0402_1% @ R7

3.01K_0402_1%

3.01K_0402_1% R8

3.01K_0402_1%

1 2

1 2 1 2

1 2

R11

R11 0_0402_5%

0_0402_5%

1 2 1 2

R12

R12 0_0402_5%

0_0402_5%

DMI_PTX_HRX_N[0..3] <15> DMI_PTX_HRX_P[0..3] <15>

DMI_HTX_PRX_N[0..3] <15> DMI_HTX_PRX_P[0..3] <15>

H_FDI_TXN[0..7] <15>

H_FDI_TXP[0..7] <15>

2

JCPU1E

RSVD32

AP25

RSVD1

AL25

RSVD2

AL24

RSVD3

AL22

RSVD4

AJ33

RSVD5

AG9

RSVD6

M27

RSVD7

L28

RSVD8

J17

SA_DIMM_VREF

H17

SB_DIMM_VREF

G25

RSVD11

G17

RSVD12

E31

RSVD13

E30

RSVD14

CFG0

AM30

CFG[0]

AM28

CFG[1]

AP31

CFG3

@R7

@

@R8

@

CFG4

CFG7

H_RSVD17_R

@

H_RSVD18_R

@

AL32

AL30 AM31 AN29 AM32 AK32 AK31 AK28

AJ28 AN30 AN32

AJ32

AJ29

AJ30 AK30

H16

B19 A19

A20 B20

AC9 AB9

A34 A33

C35 B35

U9 T9

C1 A3

J29 J28

CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] RSVD_TP_86

RSVD15 RSVD16

RSVD17 RSVD18

RSVD19 RSVD20

RSVD21 RSVD22

RSVD_NCTF_23 RSVD_NCTF_24

RSVD26 RSVD27

RSVD_NCTF_28 RSVD_NCTF_29

RSVD_NCTF_30 RSVD_NCTF_31

(CFD Only) (CFD Only)

RESERVED

RSVD33

RSVD34 RSVD35

RSVD36

RSVD_NCTF_37

RSVD38 RSVD39

RSVD_NCTF_40 RSVD_NCTF_41

RSVD_NCTF_42 RSVD_NCTF_43

RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52

RSVD53 RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57

RSVD58

RSVD_TP_59 RSVD_TP_60

RSVD62

RSVD63

RSVD64

RSVD65

RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75

RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85

KEY

VSS

AJ13 AJ12

AH25 AK26

AL26 AR2

AJ26 AJ27

AP1 AT2

AT3 AR1

AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32

E15 F15 A2 D15 C15 AJ15 AH15

AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3

V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9

AP34

1

RSVD64_R RSVD65_R

R9

R9 0_0402_5%

0_0402_5%

R10

R10 0_0402_5%

0_0402_5%

@

12

@

12

IC,AUB_CFD_rPGA,R1P0

IC,AUB_CFD_rPGA,R1P0 CONN@

CONN@

eDP Signals Mapping eDP Singal

eDP_TX0

PEG Singals

PEG_HTX_C_GRX_P15 eDP_TX#0 PEG_HTX_C_GRX_N15 eDP_TX1 PEG_HTX_C_GRX_P14 eDP_TX#1

A A

eDP_TX2 eDP_TX#2 eDP_TX3 eDP_TX#3 eDP_AUX eDP_AUX# eDP_HPD#

PEG_HTX_C_GRX_N14

PEG_HTX_C_GRX_P13

PEG_HTX_C_GRX_N13

PEG_HTX_C_GRX_P12

PEG_HTX_C_GRX_N12

PEG_GTX_C_HRX_P13

PEG_GTX_C_HRX_N13

PEG_GTX_C_HRX_P12

5

Lane Reversal

PEG_HTX_C_GRX_P0 PEG_HTX_C_GRX_N0 PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_N1 PEG_HTX_C_GRX_P2 PEG_HTX_C_GRX_N2 PEG_HTX_C_GRX_P3 PEG_HTX_C_GRX_N3 PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_N2 PEG_GTX_C_HRX_P3

Security Classification

2009/08/01 2010/08/01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/08/01 2010/08/01

3

Compal Secret Data

CFG0 - PCI-Express Configuration Select

*1:Single PEG 0:Bifurcation enabled

CFG3 - PCI-Express Static Lane Reversal

*1 :Normal Operation 0 :Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

Deciphered Date

Title

Size Document Number Rev

B

Date: Sheet

2

Date: Sheet

CFG4 - Display Port Presence

*1:Disabled; No Physical Display Port attached to Embedded Display Port 0:Enabled; An external Display Port device is connected to the Embedded Display Port

*:Default

Compal Electronics, Inc.

SCHEMATICS,MB A5892

SCHEMATICS,MB A5892 401826

401826

1

C

449Tuesday, June 22, 2010

of

5

JCPU1B

R18 20_0402_1%R18 20_0402_1% R19 20_0402_1%R19 20_0402_1% R20 49.9_0402_1%R20 49.9_0402_1% R21 49.9_0402_1%R21 49.9_0402_1%

D D

H_PECI<18>

H_PROCHOT#<45>

H_THERMTRIP#<18>

H_PM_SYNC<15>

C C

B B

A A

H_CPUPWRGD<18>

PM_DRAM_PWRGD<15>

H_PWRGD_XDP H_PWRGD_XDP_R

PLT_RST#<17,21,27,30>

2009/2/4 #414044 DG

Update Rev1.11

+1.05VS_VTT

R58 49.9_0402_1% R58 49.9_0402_1%

R59 68_0402_5% R59 68_0402_5%

R60 68_0402_5%@R60 68_0402_5%@

H_VTTPWRGD<43>

U1 / U2 change to SA00000OH00

#425302 CP_S3PowerReduction WhitePaper_Rev0.7

PM_DRAM_PWRGD_R

H_VTTPWRGD

NC7SZ08P5X_NL_SC70-5

1.1K_0402_1%

3.01K_0402_1%

R68

R68 @

@

R71

R71 @

@

+1.5V_1

5

12

www.rosefix.com

12 12 12

PAD

T24

R26

1 2

0_0402_5%

R36

1 2

0_0402_5%

R42

1 2

0_0402_5%

0_0402_5% R44

R44

1 2

0_0402_5%

0_0402_5% R47

R47

1 2

0_0402_5%

R50

1 2

0_0402_5%

H_VTTPWRGD

R56

1.5K_0402_1%

12

@

1 2

R52 0_0402_5%

R55

1 2

0_0402_5%

R56

1 2

12 12 12

+3VALW

5

U1

2

P

B

1

A

G

3

12

R69

1.5K_0402_1%

12

R72

R72 750_0402_1%

750_0402_1%

Y

4

H_COMP3 H_COMP2 H_COMP1 H_COMP0

SKTOCC#_R

@

H_CATERR#

H_PECI_R

H_PROCHOT#

H_THERMTRIP#_R

H_CPURST#

H_PM_SYNC_R

H_CPUPWRGD_1

H_CPUPWRGD_0

PM_DRAM_PWRGD_R

H_VTTPWRGD_R

PLT_RST#_R

12

R57

R57 750_0402_1%

750_0402_1%

H_CATERR# H_PROCHOT# H_CPURST#

R61

2K_0402_1%

1 2

4

+3VALW

Need to check Voltage Level

5

U2

2

P

B

Y

1

A

G

NC7SZ08P5X_NL_SC70-5

3

2009/04/23 Intel CRB 1.55 Update Change R292 to 1.1K_1%, R302 to 3.01K_1%

JCPU1B

AT23 AT24

G16

AT26

AH24

AK14

AT15

AN26

AK15

AP26

AL15

AN14

AN27

AK13

AM15

AM26

AL14

IC,AUB_CFD_rPGA,R1P0

IC,AUB_CFD_rPGA,R1P0 CONN@

CONN@

2009/8/14 change back to 2K

H_VTTPWRGD_R

12

R62

R62 1K_0402_1%

1K_0402_1%

H_VTTPWRGD

4

COMP3 COMP2 COMP1 COMP0

SKTOCC#

CATERR#

PECI

PROCHOT#

THERMTRIP#

RESET_OBS#

PM_SYNC

VCCPWRGOOD_1

VCCPWRGOOD_0

SM_DRAMPWROK

VTTPWRGOOD

TAPPWRGOOD

RSTIN#

4

MISC THERMAL

DPLL_REF_SSCLK#

CLOCKS

DDR3

MISC

DDR3

MISC

PWR MANAGEMENT

JTAG & BPM

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

BCLK

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

DPLL_REF_SSCLK

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

PM_EXT_TS#[0] PM_EXT_TS#[1]

PRDY# PREQ#

TCK TMS

TRST#

TDO

TDI_M

TDO_M

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

+1.05VS_VTT

Issued Date

TDI

C65

0.1U_0402_16V4Z

0.1U_0402_16V4Z @

@

3

A16 B16

AR30 AT30

E16 D16

A18 A17

F6

SM_RCOMP_0

AL1

SM_RCOMP_1

AM1

SM_RCOMP_2

AN1

PM_EXTTS#0

AN15

PM_EXTTS#1_R

AP15

XDP_PRDY#

AT28

XDP_PREQ#

AP27

XDP_TCLK

AN28

XDP_TMS

AP28

XDP_TRST#

AT27

XDP_TDI_R

AT29

XDP_TDO_R

AR27

XDP_TDI_M

AR29

XDP_TDO_M

AP29

XDP_DBR#_R

AN25

AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23

2009/2/4 Delete dampling resistor for

power noise and Layout space issue

H_CPUPWRGD

PBTN_OUT#<15,21,30>

1

2

2009/08/01 2010/08/01

3

CLK_CPU_XDP CLK_CPU_XDP#

1 2

R28 100K_0402_5%

R46 0_0402_5% R46 0_0402_5%

1 2

XDP_OBS0 XDP_OBS1 XDP_OBS2 XDP_OBS3 XDP_OBS4 XDP_OBS5 XDP_OBS6 XDP_OBS7

R65

R65 1K_0402_5%

1K_0402_5%

1 2 1 2

R66 0_0402_5%R66 0_0402_5%

SMB_DATA_S3<21> SMB_CLK_S3<21>

Compal Secret Data

CLK_CPU_BCLK <18> CLK_CPU_BCLK# <18>

CLK_CPU_DMI <14> CLK_CPU_DMI# <14>

CLK_CPU_DP <14> CLK_CPU_DP# <14>

SM_DRAMRST# <10>

R32 10K_0402_5% R32 10K_0402_5%

1 2

R34 10K_0402_5% R34 10K_0402_5%

1 2

R35 0_0402_5% R35 0_0402_5%

1 2

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

XDP_PREQ# XDP_PRDY#

XDP_OBS0 XDP_OBS1

XDP_OBS2 XDP_OBS3

XDP_OBS4 XDP_OBS5

XDP_OBS6 XDP_OBS7

H_PWRGOOD_R PBTN_OUT#_XDP

H_PWRGD_XDP

XDP_TCLK

Deciphered Date

R38 100_0402_1% R38 100_0402_1%

1 2

R39 24.9_0402_1% R39 24.9_0402_1%

1 2

R40 130_0402_1%<BOM Structure>R40 130_0402_1%<BOM Structure>

1 2

XDP_DBRESET#

1 3 5 7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59

2

2009/08/14 #425302 CP_S3PowerReduction WhitePaper_Rev0.9

+1.05VS_VTT

PM_EXTTS#0_1 <10,11>

XDP_DBRESET# <15,21>

XDP Connector

JP5

GND0 OBSFN_A0 OBSFN_A1 GND2 OBSDATA_A0 OBSDATA_A1 GND4 OBSDATA_A2 OBSDATA_A3 GND6 OBSFN_B0 OBSFN_B1 GND8 OBSDATA_B0 OBSDATA_B1 GND10 OBSDATA_B2 OBSDATA_B3 GND12 PWRGOOD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 GND14 SDA SCL TCK1 TCK0 GND16

2

SAMTE_BSH-030-01-L-D-ACONN@

OBSFN_C0 OBSFN_C1

OBSDATA_C0 OBSDATA_C1

OBSDATA_C2 OBSDATA_C3

OBSFN_D0 OBSFN_D1

OBSDATA_D0 OBSDATA_D1

OBSDATA_D2 OBSDATA_D3

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

1

+1.05VS_VTT

XDP_PRDY# XDP_TMS XDP_TDI_R XDP_PREQ# XDP_TCLK

XDP_TRST#

XDP_TDI_R XDP_TDI

XDP_TDI_M XDP_TDO_R

R27 51_0402_5%@R27 51_0402_5%@

1 2

R29 51_0402_5%@R29 51_0402_5%@

1 2

R30 51_0402_5%@R30 51_0402_5%@

1 2

R31 51_0402_5%@R31 51_0402_5%@

1 2

R33 51_0402_5%@R33 51_0402_5%@

1 2

R37 51_0402_5% R37 51_0402_5%

1 2

R41 0_0402_5% R41 0_0402_5%

1 2

R43 0_0402_5%@R43 0_0402_5%@

1 2

12

R45

R45 0_0402_5%

0_0402_5%

@

1 2

R48 0_0402_5%

1 2

R49 0_0402_5%

JTAG MAPPING

Scan Chain (Default)

CPU Only

GMCH Only

2

GND1

4 6 8

GND3

10 12 14

GND5

16 18 20

GND7

22 24 26

GND9

28 30 32

GND11

34 36 38

GND13

GND15

TD0

TRST#

TDI

TMS

GND17

Title

Size Document Number Rev

B

Date: Sheet

CLK_CPU_XDP

40

CLK_CPU_XDP#

42 44

H_RESET#_R

46

XDP_DBRESET#

48 50

XDP_TDO

52

XDP_TRST#

54

XDP_TDI

56

XDP_TMS

58 60

SCHEMATICS,MB A5892

SCHEMATICS,MB A5892 401826

401826

STUFF -> R653, R657, R662 NO STUFF -> R655, R660

STUFF -> R653, R655 NO STUFF -> R657, R660, R662

STUFF -> R660, R662 NO STUFF -> R653, R655, R657

R63

R63 1K_0402_5%

1K_0402_5%

1 2 1 2

R64 0_0402_5%@R64 0_0402_5%@

1 2

R67 1K_0402_5%R67 1K_0402_5%

1 2

R70 51_0402_5%R70 51_0402_5%

Compal Electronics, Inc.

H_CPURST# PLT_RST#H_RESET#_R

549Tuesday, June 22, 2010

1

XDP_TDOXDP_TDO_M

+1.05VS_VTT +3VS +1.05VS_VTT

of

C

5

JCPU1C

A10 C10

B10 D10 E10

F10

H10

G10

J10

AH5

AF5 AK6 AK7 AF6

AG5

AJ7 AJ6

AJ10

AJ9

AL10

AK12

AK8 AL7

AK11

AL8

AN8 AM10 AR11

AL11

AM9

AN9

AT11 AP12 AM12 AN12 AM13

AT14

AT12

AL13 AR14 AP14

AC3

AB2

AE1 AB3 AE9

C7 A7

A8 D8

E6 F7 E9 B7 E7 C6

G8

K7

J8

G7

J7

L7 M6 M8

L9

L6

K8 N8 P9

U7

JCPU1C

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

DDR SYSTEM MEMORY A

DDR_A_D[0..63]<10> DDR_A_DM[0..7]<10>

DDR_A_DQS#[0..7]<10>

DDR_A_DQS[0..7]<10>

DDR_A_MA[0..15]<10>

D D

C C

B B

DDR_A_BS0<10> DDR_A_BS1<10> DDR_A_BS2<10>

DDR_A_CAS#<10> DDR_A_RAS#<10>

DDR_A_WE#<10>

www.rosefix.com

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

DDR_A_CAS# DDR_A_RAS# DDR_A_WE#

SA_CK[0] SA_CK#[0] SA_CKE[0]

SA_CK[1] SA_CK#[1] SA_CKE[1]

SA_CS#[0] SA_CS#[1]

SA_ODT[0] SA_ODT[1]

SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

4

AA6 AA7 P7

Y6 Y5 P6

AE2 AE8

AD8 AF9

B9 D7 H7 M7 AG6 AM7 AN10 AN13

C9 F8 J9 N9 AH7 AK9 AP11 AT13

C8 F9 H9 M9 AH8 AK10 AN11 AR13

Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

DDR_A_CLK0 <10> DDR_A_CLK0# <10> DDR_A_CKE0 <10>

DDR_A_CLK1 <10> DDR_A_CLK1# <10> DDR_A_CKE1 <10>

DDR_A_CS0# <10> DDR_A_CS1# <10>

DDR_A_ODT0 <10> DDR_A_ODT1 <10>

3

DDR_B_D[0..63]<11>

DDR_B_DM[0..7]<11>

DDR_B_DQS#[0..7]<11>

DDR_B_DQS[0..7]<11>

DDR_B_MA[0..15]<11>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

DDR_B_BS0<11> DDR_B_BS1<11> DDR_B_BS2<11>

DDR_B_CAS#<11> DDR_B_RAS#<11>

DDR_B_WE#<11>

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

DDR_B_CAS# DDR_B_RAS# DDR_B_WE#

AF3

AG1

AK1 AG4 AG3

AH4

AK3

AK4 AM6 AN2

AK5

AK2 AM4 AM3

AP3 AN5

AT4 AN6 AN4 AN3

AT5

AT6 AN7

AP6

AP8

AT9

AT7

AP9

AR10 AT10

AB1

AC5 AC6

B5 A5 C3 B3 E4 A6 A4 C4 D1 D2 F2 F1 C2 F5 F3

G4

H6

G2

J6

J3 G1 G5

J2

J1

J5

K2

L3 M1

K5 K4

M4

N5

AJ3

AJ4

W5

R7

Y7

JCPU1D

SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

SB_BS[0] SB_BS[1] SB_BS[2]

SB_CAS# SB_RAS# SB_WE#

2

SB_CK[0]

SB_CK#[0]

SB_CKE[0]

SB_CK[1]

SB_CK#[1]

SB_CKE[1]

SB_CS#[0] SB_CS#[1]

SB_ODT[0] SB_ODT[1]

SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

DDR SYSTEM MEMORY - B

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

W8 W9 M3

V7 V6 M2

AB8 AD6

AC7 AD1

D4 E1 H3 K1 AH1 AL2 AR4 AT8

D5 F4 J4 L4 AH2 AL4 AR5 AR8

C5 E3 H4 M5 AG2 AL5 AP5 AR7

U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1

DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

1

DDR_B_CLK0 <11> DDR_B_CLK0# <11> DDR_B_CKE0 <11>

DDR_B_CLK1 <11> DDR_B_CLK1# <11> DDR_B_CKE1 <11>

DDR_B_CS0# <11> DDR_B_CS1# <11>

DDR_B_ODT0 <11> DDR_B_ODT1 <11>

IC,AUB_CFD_rPGA,R1P0

IC,AUB_CFD_rPGA,R1P0 CONN@

CONN@

A A

5

4

Security Classification

2009/08/01 2010/08/01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/08/01 2010/08/01

3

Compal Secret Data

Deciphered Date

IC,AUB_CFD_rPGA,R1P0

IC,AUB_CFD_rPGA,R1P0 CONN@

CONN@

2

Compal Electronics, Inc.

Title

SCHEMATICS,MB A5892

Size Document Number Rev

B

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

401826

649Tuesday, June 22, 2010

of

1

of

C

5

JCPU1F

www.rosefix.com

+CPU_CORE

D D

C C

B B

A A

48A Continuous 18A

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

WW15 MOW

1.1V RAIL POWER

CPU CORE SUPPLY

POWER

CPU VIDS

SENSE LINES

IC,AUB_CFD_rPGA,R1P0

IC,AUB_CFD_rPGA,R1P0 CONN@

CONN@

5

Peak 21A

VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8

VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32

VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44

PSI#

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

PROC_DPRSLPVR

VTT_SELECT

ISENSE

VCC_SENSE

VSS_SENSE

VTT_SENSE

VSS_SENSE_VTT

4

AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15

AN33

AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34

H_VTTVID1

G15

H_VTTVID1 = low, 1.1V H_VTTVID1 = high, 1.05V

AN35

VCCSENSE_R

AJ34

VSSSENSE_R

AJ35

B15

VSS_SENSE_VTT

A15

4

10U_0805_6.3V6M

1

C66

2

10U_0805_6.3V6M

1

C82

2

330U_D2E_2.5VM_R6M

22U_0805_6.3V6M

1

C91

C92

2

22U_0805_6.3V6M

@

PAD

IMVP_IMON <45>

R92 0_0402_5% R92 0_0402_5%

1 2

R93 0_0402_5% R93 0_0402_5%

1 2

R95 0_0402_5% R95 0_0402_5%

1

C67

2

10U_0805_6.3V6M

+1.05VS_VTT

+

1

2

20090915 Modify

T14

1 2

3

+1.05VS_VTT

10U_0805_6.3V6M

1

C68

2

1

+

C83

C83 330U_D2E_2.5VM_R6M

330U_D2E_2.5VM_R6M

2

+1.05VS_VTT

10U_0805_6.3V6M

1

C69

C70

2

10U_0805_6.3V6M

H_PSI# <45>

CPU_VID0 <45> CPU_VID1 <45> CPU_VID2 <45> CPU_VID3 <45> CPU_VID4 <45> CPU_VID5 <45> CPU_VID6 <45> H_DPRSLPVR <45>

1

C71

C72

2

10U_0805_6.3V6M

CSC (Current Sense Configuration) 8/25

CPU_VID0

CPU_VID1

CPU_VID2

CPU_VID3

CPU_VID4

CPU_VID5

CPU_VID6

H_DPRSLPVR

H_PSI#

R73 1K_0402_1% R73 1K_0402_1%

1 2

R74 1K_0402_1%@R74 1K_0402_1%@

1 2

R75 1K_0402_1% R75 1K_0402_1%

1 2

R76 1K_0402_1%@R76 1K_0402_1%@

1 2

R77 1K_0402_1% R77 1K_0402_1%

1 2

R78 1K_0402_1%@R78 1K_0402_1%@

1 2

R79 1K_0402_1%@R79 1K_0402_1%@

1 2

R80 1K_0402_1% R80 1K_0402_1%

1 2

R81 1K_0402_1%@R81 1K_0402_1%@

1 2

R82 1K_0402_1% R82 1K_0402_1%

1 2

R83 1K_0402_1% R83 1K_0402_1%

1 2

R84 1K_0402_1%@R84 1K_0402_1%@

1 2

R85 1K_0402_1%@R85 1K_0402_1%@

1 2

R86 1K_0402_1% R86 1K_0402_1%

1 2

R87 1K_0402_1% R87 1K_0402_1%

1 2

R88 1K_0402_1%@R88 1K_0402_1%@

1 2

R89 1K_0402_1%@R89 1K_0402_1%@

1 2

R90 1K_0402_1% R90 1K_0402_1%

1 2

+CPU_CORE

10U_0805_6.3V6M

1

C73

2

1

C74

2

10U_0805_6.3V6M

+1.05VS_VTT

C74

VTT Rail Auburndale +1.1VS_VTT=1.05V

Clarksfield +1.1VS_VTT=1.1V

1 2

R91 100_0402_1%

VCCSENSE VSSSENSE

1 2

R94 100_0402_1%

VTT_SENSE <43>

R94 100_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+CPU_CORE

VCCSENSE <45> VSSSENSE <45>

Compal Secret Data

2009/08/01 2010/08/01

Compal Secret Data

+CPU_CORE

1

C105

330U_D2E_2.5VM_R6M

Deciphered Date

2

+

TOP side (under inductor)

2

10U_0805_6.3V6M

1

C78

2

1

C87

2

1

C96

2

1

2

10U_0805_6.3V6M

C78

C79

C87

C88

10U_0805_6.3V6M

22U_0805_6.3V6M

1

C96

2

22U_0805_6.3V6M

1

C102

2

1

C79

2

1

C88

2

C97

22U_0805_6.3V6M

C103

22U_0805_6.3V6M

10U_0805_6.3V6M

1

C75

2

10U_0805_6.3V6M

(Place these capacitors between inductor and socket on Bottom)

10U_0805_6.3V6M

+CPU_CORE

10U_0805_6.3V6M

1

C84

2

(Place these capacitors under CPU socket, top layer)

+CPU_CORE

C98

22U_0805_6.3V6M

+CPU_CORE

C99

22U_0805_6.3V6M

10U_0805_6.3V6M

1

C76

2

1

C85

2

22U_0805_6.3V6M

1

C94

2

(Place these capacitors on CPU cavity, Bottom Layer)

22U_0805_6.3V6M

1

2

1

C76

C85

C94

C100

(Place these capacitors on CPU cavity, Bottom Layer)

C77

2

1

C86

2

10U_0805_6.3V6M

1

C95

2

22U_0805_6.3V6M

1

C101

2

22U_0805_6.3V6M

10U_0805_6.3V6M

4 x 470uF(4.5mohm@100kHz; 4.0mohm@SRF)

1

+

C106

@

2

330U_D2E_2.5VM_R6M

+CPU-CORE Decoupling SPCAP,Polymer

MLCC 0805 X5R

2

1

+

C272

2

330U_D2E_2.5VM_R6M

C,uF 4X470uF 4m ohm/4

16X22uF 16X10uF 3m ohm/16

Title

SCHEMATICS,MB A5892

Size Document Number Rev

Custom

401826

Date: Sheet

1

+

C273

2

330U_D2E_2.5VM_R6M

C275

330U_D2E_2.5VM_R6M

ESR, mohm

3m ohm/12

Compal Electronics, Inc.

1

C80

2

10U_0805_6.3V6M

1

C89

2

1

2

22U_0805_6.3V6M

1

C104

2

1

+

2

Stuffing Option

2X470uF

749Tuesday, June 22, 2010

1

10U_0805_6.3V6M

1

C81

2

1

2

of

C

5

4

3

2

1

www.rosefix.com

D D

330U_D2E_2.5VM_R6M

C C

B B

+VGFX_CORE

1

+

C107

2

22U_0805_6.3V6M

1

C111

C110

2

22U_0805_6.3V6M

+1.05VS_VTT

C122

+1.05VS_VTT

C125

1

C112

2

10U_0805_6.3V6M

1

C123

C123 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

C126

C126 22U_0805_6.3V6M

22U_0805_6.3V6M

2

10U_0805_6.3V6M

1

C113

2

JCPU1G

AT21

VAXG1

AT19

VAXG2

AT18

VAXG3

AT16

VAXG4

AR21

VAXG5

AR19

VAXG6

AR18

VAXG7

AR16

VAXG8

AP21

VAXG9

AP19

VAXG10

AP18

VAXG11

AP16

VAXG12

AN21

VAXG13

AN19

VAXG14

AN18

VAXG15

AN16

VAXG16

AM21

VAXG17

AM19

VAXG18

AM18

VAXG19

AM16

VAXG20

AL21

VAXG21

AL19

VAXG22

AL18

VAXG23

AL16

VAXG24

AK21

VAXG25

AK19

VAXG26

AK18

VAXG27

AK16

VAXG28

AJ21

VAXG29

AJ19

VAXG30

AJ18

VAXG31

AJ16

VAXG32

AH21

VAXG33

AH19

VAXG34

AH18

VAXG35

AH16

VAXG36

J24

VTT1_45

J23

VTT1_46

H25

VTT1_47

K26

VTT1_48

J27

VTT1_49

J26

VTT1_50

J25

VTT1_51

H27

VTT1_52

G28

VTT1_53

G27

VTT1_54

G26

VTT1_55

F26

VTT1_56

E26

VTT1_57

E25

VTT1_58

IC,AUB_CFD_rPGA,R1P0

IC,AUB_CFD_rPGA,R1P0 CONN@

CONN@

15A

GRAPHICS

FDI PEG & DMI

VAXG_SENSE

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6]

GFX_VR_EN

GFX_DPRSLPVR

GFX_IMON

GRAPHICS VIDs

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6

3A

POWER

0.6A

VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18

DDR3 - 1.5V RAILS

VTT0_59 VTT0_60 VTT0_61 VTT0_62

VTT1_63 VTT1_64 VTT1_65

1.1V1.8V

VTT1_66 VTT1_67 VTT1_68

VCCPLL1 VCCPLL2 VCCPLL3

AR22 AT22

AM22 AP22 AN22 AP23 AM23 AP24 AN24

GFXVR_EN

AR25

GFXVR_DPRSLPVR_R

AT25 AM24

AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1

P10 N10 L10 K10

J22 J20 J18 H21 H20 H19

L26 L27 M26

1U_0402_6.3V4Z

1

C114

2

1U_0402_6.3V4Z

+1.05VS_VTT

1

C127

22U_0805_6.3V6M

2

+1.8VS_VCCSFR

1

C128

2

VCC_AXG_SENSE <44> VSS_AXG_SENSE <44>

GFXVR_VID_0 <44> GFXVR_VID_1 <44> GFXVR_VID_2 <44> GFXVR_VID_3 <44> GFXVR_VID_4 <44> GFXVR_VID_5 <44> GFXVR_VID_6 <44>

R97 0_0402_5% R97 0_0402_5%

1 2

1U_0402_6.3V4Z

1

C115

+1.05VS_VTT

C129

1U_0402_6.3V4Z

1

C116

2

1U_0402_6.3V4Z

1

C124

C124 10U_0805_6.3V6M

10U_0805_6.3V6M

2

2.2U_0603_6.3V4Z

1

C130

2

1U_0402_6.3V4Z

1

C118

C117

2

1U_0402_6.3V4Z

1

C131

2

4.7U_0805_10V4Z

GFXVR_EN <44> GFXVR_DPRSLPVR <44> GFXVR_IMON <44>

22U_0805_6.3V6M

1

C120

C119

2

22U_0805_6.3V6M

1

C132

2

22U_0805_6.3V6M

GFXVR_EN

PD 470ohm 20091105

1

+

C121

C121 330U_D2E_2.5VM_R6M

330U_D2E_2.5VM_R6M

2

Reserved for +1.5VS to +1.5V_1

11/03 add four 0.1u 0402 Intel suggest

R99

R99 0_0805_5%

0_0805_5%

1 2

R167 470_0402_5%

+1.5V+1.5V_1

Reserved for +1.5V to +1.5V_1

C670 0.1U_0402_16V4ZC670 0.1U_0402_16V4Z C671 0.1U_0402_16V4ZC671 0.1U_0402_16V4Z C672 0.1U_0402_16V4ZC672 0.1U_0402_16V4Z C673 0.1U_0402_16V4ZC673 0.1U_0402_16V4Z

+1.8VS

1 2 1 2 1 2 1 2

J1

2

112

JUMP_43X118@J1JUMP_43X118@

J3

2

JUMP_43X118@J3JUMP_43X118@

+1.5VS

112

+1.5V+1.5V_1

A A

5

4

Security Classification

2009/08/01 2010/08/01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/08/01 2010/08/01

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

SCHEMATICS,MB A5892

Size Document Number Rev

Custom

401826

Date: Sheet

Compal Electronics, Inc.

849Tuesday, June 22, 2010

of

1

of

C

5

4

3

2

1

www.rosefix.com

JCPU1H

D D

C C

B B

AT20 AT17 AR31 AR28 AR26 AR24 AR23 AR20 AR17 AR15 AR12

AR9 AR6

AR3 AP20 AP17 AP13 AP10

AP7

AP4

AP2 AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11

AM8

AM5

AM2

AL34 AL31 AL23 AL20 AL17 AL12

AL9 AL6

AL3 AK29 AK27 AK25 AK20 AK17

AJ31 AJ23 AJ20 AJ17 AJ14 AJ11

AJ8

AJ5

AJ2 AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13

AH9 AH6 AH3

AG10

AF8 AF4 AF2

AE35

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80

VSS

VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30

G34 G31 G20

K27

H35 H32 H28 H26 H24 H22 H18 H15 H13 H11

F30 F27 F25 F22 F19 F16 E35 E32 E29 E24 E21 E18 E13 E11

D33 D30 D26

C34 C32 C29 C28 C24 C22 C20 C19 C16 B31 B25 B21 B18 B17 B13 B11

A29 A27 A23

JCPU1I

VSS161

K9

VSS162

K6

VSS163

K3

VSS164

J32

VSS165

J30

VSS166

J21

VSS167

J19

VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178

H8

VSS179

H5

VSS180

H2

VSS181 VSS182 VSS183 VSS184

G9

VSS185

G6

VSS186

G3

VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201

E8

VSS202

E5

VSS203

E2

VSS204 VSS205 VSS206 VSS207

D9

VSS208

D6

VSS209

D3

VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226

B8

VSS227

B6

VSS228

B4

VSS229 VSS230 VSS231 VSS232

A9

VSS233

VSS

NCTF

VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7

AT35 AT1 AR34 B34 B2 B1 A35

H_NCTF1 H_NCTF2

H_NCTF6 H_NCTF7

@

PAD

T2

@

PAD

T3

@

PAD

T4

@

PAD

T5

IC,AUB_CFD_rPGA,R1P0

IC,AUB_CFD_rPGA,R1P0 CONN@

CONN@

A A

5

4

Security Classification

2009/08/01 2010/08/01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/08/01 2010/08/01

3

Compal Secret Data

IC,AUB_CFD_rPGA,R1P0

IC,AUB_CFD_rPGA,R1P0 CONN@

CONN@

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A5892

SCHEMATICS,MB A5892 401826

401826

1

C

949Tuesday, June 22, 2010

of

5

DIMMA VREFDQ M1 Circuit

+1.5V

12

R101

1K_0402_1%

12

R104

D D

1K_0402_1%

www.rosefix.com

+DIMM_VREFDQA

DDR_A_DQS#[0..7]<6>

DDR_A_D[0..63]<6>

DDR_A_DM[0..7]<6> DDR_A_DQS[0..7]<6> DDR_A_MA[0..15]<6>

DIMMA & DIMMB VREFCA circuit

+1.5V

12

R106

1K_0402_1%

12

R107

R107 1K_0402_1%

1K_0402_1%

C C

Layout Note: Place near JDIMM1

B B

+1.5V

10U_0805_6.3V6M

1

C150

C138

2

+0.75VS

1U_0402_6.3V4Z

1

C151

2

1

2

C137

10U_0805_6.3V6M

Layout Note: Place near JDIMM1.203 & JDIMM1.204

A A

1U_0402_6.3V4Z

+DIMM_VREFCA

#425302 CP_S3PowerReduction WhitePaper_Rev1.0

SM_DRAMRST#<5>

Layout Note: Place these 4 Caps near Command and Control signals of DIMMA

10U_0805_6.3V6M

1

C139

2

10U_0805_6.3V6M

1U_0402_6.3V4Z

1

C152

C153

2

1U_0402_6.3V4Z

5

C140

1

2

1

C141

2

10U_0805_6.3V6M

1

C154

C154 10U_0805_6.3V6M

10U_0805_6.3V6M

2

10U_0805_6.3V6M

1

C142

2

0.1U_0402_16V4Z

RST_GATE<18>

1

C143

2

0.1U_0402_16V4Z

1

C144

2

0.1U_0402_16V4Z

RST_GATE

R102

R102 0_0402_5%

0_0402_5%

1 2

0.1U_0402_16V4Z

1

C145

2

4

@

D

S

D

S

13

G

2

1

C146

2

4

+DIMM_VREFDQA

+1.5V

12

R103

R103 1K_0402_1%

1K_0402_1%

DIMM_DRAMRST#

Q2

Q2 BSS138LT1G_SOT23-3

BSS138LT1G_SOT23-3

C617

1 2

0.047U_0402_16V7K

12

+

C147

@+C147

@ 330U_2.5V_M_R15

330U_2.5V_M_R15

M1 Circuit

0.1U_0402_16V4Z

DIMM_DRAMRST# <11>

3

+DIMM_VREFDQA

DDR_A_D0 DDR_A_D1

DDR_A_DM0 DDR_A_D2

DDR_A_D3 DDR_A_D8

DDR_A_D9 DDR_A_DQS#1

1

2

2.2U_0603_6.3V4Z

Issued Date

1

C133

2.2U_0805_16V4Z

2

DDR_A_CKE0<6>

DDR_A_BS2<6>

DDR_A_CLK0<6> DDR_A_CLK0#<6>

DDR_A_BS0<6>

DDR_A_WE#<6>

DDR_A_CAS#<6> DDR_A_ODT0 <6>

DDR_A_CS1#<6>

+3VS

1

C148

2

2009/08/01 2010/08/01

3

C134

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDR_A_DQS1 DDR_A_D10

DDR_A_D11 DDR_A_D16

DDR_A_D17 DDR_A_DQS#2

DDR_A_DQS2 DDR_A_D18

DDR_A_D19 DDR_A_D24

DDR_A_D25 DDR_A_DM3 DDR_A_D26

DDR_A_D27

DDR_A_CKE0

DDR_A_BS2 DDR_A_MA12

DDR_A_MA9 DDR_A_MA8

DDR_A_MA5 DDR_A_MA3

DDR_A_MA1 DDR_A_CLK0

DDR_A_CLK0# DDR_A_MA10

DDR_A_BS0 DDR_A_WE#

DDR_A_CAS# DDR_A_ODT0 DDR_A_MA13

DDR_A_CS1#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5 DDR_A_D42

DDR_A_D43 DDR_A_D48

DDR_A_D49 DDR_A_DQS#6

DDR_A_DQS6 DDR_A_D50

DDR_A_D51 DDR_A_D56

DDR_A_D57 DDR_A_DM7 DDR_A_D58

DDR_A_D59

R109 10K_0402_5% R109 10K_0402_5%

1 2

1

C149

R110

0.1U_0402_16V4Z

2

+1.5V +1.5V

11 13 15 17 19 21 23 25 27

33 35

39 41

45 47 49 51 53 55 57 59

63 67

69

73 75 77 79 81 83 85 87 89 91 93 95 97

99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201

12

R110 10K_0402_5%

10K_0402_5%

Compal Secret Data

203 205

Deciphered Date

2

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS129RESET# VSS1131VSS12 DQ10 DQ11 VSS1337VSS14 DQ16 DQ17 VSS1543VSS16 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS2261DQS#3 DM3 VSS2365VSS24 DQ26 DQ27 VSS2571VSS26

CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1

G1

FOX_AS0A626-U8RN-7F

2

DQ4 DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6 DQ7

VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3 DQ30

DQ31

CKE1

VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

VTT2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78

A15

80

A14

82 84

A11

86

A7

88 90

A6

92

A4

94 96

A2

98

A0

100 102

CK1

104 106 108

BA1

110 112 114

S0#

116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202

SCL

204 206

G2

1

DDR_A_D4 DDR_A_D5

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D6 DDR_A_D7

DDR_A_D12 DDR_A_D13

DDR_A_DM1 DIMM_DRAMRST#

DDR_A_D14 DDR_A_D15

DDR_A_D20 DDR_A_D21

DDR_A_DM2 DDR_A_D22

DDR_A_D23 DDR_A_D28

DDR_A_D29 DDR_A_DQS#3

DDR_A_DQS3 DDR_A_D30

DDR_A_D31

DDR_A_CKE1

DDR_A_MA15 DDR_A_MA14

DDR_A_MA11 DDR_A_MA7

DDR_A_MA6 DDR_A_MA4

DDR_A_MA2 DDR_A_MA0

DDR_A_CLK1 DDR_A_CLK1#

DDR_A_BS1 DDR_A_RAS#

DDR_A_CS0#

DDR_A_ODT1

DDR_VREF_CA_DIMMA DDR_A_D36

DDR_A_D37 DDR_A_DM4 DDR_A_D38

DDR_A_D39 DDR_A_D44DDR_A_D44

DDR_A_D45 DDR_A_DQS#5

DDR_A_DQS5 DDR_A_D46

DDR_A_D47 DDR_A_D52

DDR_A_D53 DDR_A_DM6 DDR_A_D54

DDR_A_D55 DDR_A_D60

DDR_A_D61 DDR_A_DQS#7

DDR_A_DQS7 DDR_A_D62

DDR_A_D63 PM_EXTTS#0_1

D_CK_SDATA D_CK_SCLK

+0.75VS

DDR_A_CKE1 <6>

DDR_A_CLK1 <6> DDR_A_CLK1# <6>

DDR_A_BS1 <6> DDR_A_RAS# <6>

DDR_A_CS0# <6>

DDR_A_ODT1 <6>

R108 0_0402_5% R108 0_0402_5%

1 2

2.2U_0603_6.3V4Z

PM_EXTTS#0_1 <5,11>

D_CK_SDATA <11,12> D_CK_SCLK <11,12>

C135

+DIMM_VREFCA

1

2

DDR3 SO-DIMM A

Change to Reverse Type

8mm High

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A5892

401826

1

C136

0.1U_0402_16V4Z

2

of

10 49Tuesday, June 22, 2010

C

5

DDR_B_DQS#[0..7]<6>

DDR_B_D[0..63]<6>

DDR_B_DM[0..7]<6>

DDR_B_DQS[0..7]<6>

DDR_B_MA[0..15]<6>

D D

DIMMB VREFDQ M1 Circuit

+1.5V

12

R113

1K_0402_1%

12

R114

R114 1K_0402_1%

1K_0402_1%

C C

Layout Note: Place near JDIMM2

+1.5V

1

B B

A A

C159

10U_0805_6.3V6M

1U_0402_6.3V4Z

1

C160

2

10U_0805_6.3V6M

Layout Note: Place near JDIMM2.203 & JDIMM2.204

+0.75VS

1

C170

C171

2

1U_0402_6.3V4Z

www.rosefix.com

+DIMM_VREFDQB

10U_0805_6.3V6M

1

C162

2

10U_0805_6.3V6M

1

C173

2

1U_0402_6.3V4Z

10U_0805_6.3V6M

1

C163

2

1

2

1

C164

2

10U_0805_6.3V6M

C174

10U_0805_6.3V6M

C161

1U_0402_6.3V4Z

1

C172

2

2008/9/8 #400755 Calpella Clarksfield DDR3 SO-DIMM VREFDQ Platform Design Guide Change Details

Layout Note: Place these 4 Caps near Command and Control signals of DIMMB

0.1U_0402_16V4Z

C165

1

C166

2

0.1U_0402_16V4Z

1

2

C167

4

1

C168

2

0.1U_0402_16V4Z

1

2

12

+

C169

C169 330U_2.5V_M_R15

330U_2.5V_M_R15

+DIMM_VREFDQB

M1 Circuit

C155

2.2U_0805_16V4Z

+3VS

C175

2.2U_0603_6.3V4Z

3

1

2

0.1U_0402_16V4Z

DDR_B_CKE0<6>

DDR_B_BS2<6>

DDR_B_CLK0<6> DDR_B_CLK0#<6>

DDR_B_BS0<6>

DDR_B_WE#<6>

DDR_B_CAS#<6>

DDR_B_CS1#<6>

1

2

+DIMM_VREFDQB

1

C156

2

R116 10K_0402_5%R116 10K_0402_5%

1 2 1 2

R117 10K_0402_5%R117 10K_0402_5%

1

C176

0.1U_0402_16V4Z

2

DDR_B_D0 DDR_B_D1

DDR_B_DM0 DDR_B_D2

DDR_B_D3 DDR_B_D8

DDR_B_D9 DDR_B_DQS#1

DDR_B_DQS1 DDR_B_D10

DDR_B_D11 DDR_B_D16

DDR_B_D17 DDR_B_DQS#2

DDR_B_DQS2

DDR_B_D19 DDR_B_D24

DDR_B_D25 DDR_B_DM3 DDR_B_D26

DDR_B_D27

DDR_B_CKE0

DDR_B_BS2 DDR_B_MA12

DDR_B_MA9 DDR_B_MA8

DDR_B_MA5 DDR_B_MA3

DDR_B_MA1 DDR_B_CLK0

DDR_B_CLK0# DDR_B_MA10

DDR_B_BS0 DDR_B_WE#

DDR_B_CAS# DDR_B_MA13

DDR_B_CS1#

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_DM5 DDR_B_D42

DDR_B_D43 DDR_B_D48

DDR_B_D49 DDR_B_DQS#6

DDR_B_DQS6 DDR_B_D50

DDR_B_D51 DDR_B_D56

DDR_B_D57 DDR_B_DM7 DDR_B_D58

DDR_B_D59

+1.5V

JDIMM2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-U4RN-7F

FOX_AS0A626-U4RN-7F CONN@

CONN@

2

DQ4 DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6 DQ7

VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3 DQ30

DQ31

CKE1

VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

VTT2

1

+1.5V

2

DDR_B_D4

4

DDR_B_D5

6 8

DDR_B_DQS#0

10

DDR_B_DQS0

12 14

DDR_B_D6

16

DDR_B_D7

18 20

DDR_B_D12

22

DDR_B_D13

24 26

DDR_B_DM1

28

DIMM_DRAMRST#

30 32

DDR_B_D14

34

DDR_B_D15

36 38

DDR_B_D20

40

DDR_B_D21

42 44

DDR_B_DM2

46 48

DDR_B_D22

50

DDR_B_D23DDR_B_D18

52 54

DDR_B_D28

56

DDR_B_D29

58 60

DDR_B_DQS#3

62

DDR_B_DQS3

64 66

DDR_B_D30

68

DDR_B_D31

70 72

DDR_B_CKE1

74 76 78

A15

80

A14

82 84

A11

86

A7

88 90

A6

92

A4

94 96

A2

98

A0

100 102

CK1

104 106 108

BA1

110 112 114

S0#

116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202

SCL

204 206

G2

DDR_B_MA15 DDR_B_MA14

DDR_B_MA11 DDR_B_MA7

DDR_B_MA6 DDR_B_MA4

DDR_B_MA2 DDR_B_MA0

DDR_B_CLK1 DDR_B_CLK1#

DDR_B_BS1 DDR_B_RAS#

DDR_B_CS0# DDR_B_ODT0

DDR_B_ODT1

DDR_VREF_CA_DIMMB

DDR_B_D36 DDR_B_D37

DDR_B_DM4 DDR_B_D38

DDR_B_D39 DDR_B_D44

DDR_B_D45 DDR_B_DQS#5

DDR_B_DQS5 DDR_B_D46

DDR_B_D47 DDR_B_D52

DDR_B_D53 DDR_B_DM6 DDR_B_D54

DDR_B_D55 DDR_B_D60

DDR_B_D61 DDR_B_DQS#7

DDR_B_DQS7 DDR_B_D62

DDR_B_D63 PM_EXTTS#0_1

D_CK_SDATA D_CK_SCLK

DIMM_DRAMRST# <10>

DDR_B_CKE1 <6>

R115 0_0402_5%R115 0_0402_5%

+0.75VS

DDR_B_CLK1 <6> DDR_B_CLK1# <6>

DDR_B_BS1 <6> DDR_B_RAS# <6>

DDR_B_CS0# <6> DDR_B_ODT0 <6>

DDR_B_ODT1 <6>

1 2

2.2U_0603_6.3V4Z

PM_EXTTS#0_1 <5,10>

D_CK_SDATA <10,12> D_CK_SCLK <10,12>

C157

+DIMM_VREFCA

1

2

DDR3 SO-DIMM B

1

C158

0.1U_0402_16V4Z

2

Reverse Type 4mm High

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/08/01 2010/08/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A5892

401826

11 49Tuesday, June 22, 2010

1

of

C

A

B

C

D

E

F

G

H

www.rosefix.com

+CLK_1.05VS

L1

+1.05VS_VTT

1 1

L1 FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

1

C177

C177 10U_0805_10V4Z

10U_0805_10V4Z

2

12

10U_0805_10V4Z

C178

1

2

2 2

CLK_BUF_DREF_96M

CLK_BUF_DREF_96M#<14>

CLK_BUF_PCIE_SATA<14> CLK_BUF_PCIE_SATA#<14>

CLK_BUF_CPU_DMI<14> CLK_BUF_CPU_DMI#<14>

3 3

+3VS

Silego Have Internal Pull-Up

R121 10K_0402_5% R121 10K_0402_5%

1 2

IDT Have Internal Pull-Down

R124 10K_0402_5% R124 10K_0402_5%

1 2

(Default)

4 4

0 133MHz

1

A

B

CLK_BUF_DREF_96M#

CLK_BUF_PCIE_SATA CLK_BUF_PCIE_SATA#

CLK_BUF_CPU_DMI CLK_BUF_CPU_DMI#

H_STP_CPU#

REF_0/CPU_SEL

100MHz 100MHz

0.1U_0402_16V4Z

1

C179

2

0.1U_0402_16V4Z

+CLK_1.05VS

CPU_1PIN 30 CPU_0 133MHz

L2

47P_0402_50V8J

1

C180

2

47P_0402_50V8J

+CLK_3VS

H_STP_CPU#

1

@

C35

C36

2

+CLK_1.5VS

C36

U3

1

VDD_USB_48

2

VSS_48M

3

DOT_96

4

DOT_96#

5

VDD_27

6

27MHZ

7

27MHZ_SS

8

USB_48

9

VSS_27M

10

SATA

11

SATA#

12

VSS_SRC

13

SRC_1

14

SRC_1#

15

VDD_SRC_IO

16

CPU_STOP#

33

TGND

SLG8SP587VTR_QFN32_5X5

Clock Generator

IDT SA00003HR00

2

20090915 Add for 3G team 20090915 Add for 3G team

+3VS

C181

10U_0805_10V4Z

+1.5VS

REF_0/CPU_SEL

XTAL_OUT

CKPWRGD/PD#

VDD_CPU_IO

L2

FBMA-L11-201209-221LMA30T_0805

1

2

L3

FBMA-L11-201209-221LMA30T_0805

@

L4

FBMA-L11-201209-221LMA30T_0805

1

C185

C185 10U_0805_10V4Z

10U_0805_10V4Z

2

+CLK_3VS

32

SCL

31

SDA

30 29

VDD_REF

28

XTAL_IN

27 26

VSS_REF

25 24

VDD_CPU

23

CPU_0

22

CPU_0#

21

VSS_CPU

20

CPU_1

19

CPU_1#

18 17

VDD_SRC

12

D_CK_SCLK D_CK_SDATA REF_0/CPU_SEL

CLK_XTAL_IN CLK_XTAL_OUT

CK505_PWRGD

CLK_BUF_CPU_BCLK CLK_BUF_CPU_BCLK#

IDT: 9LRS3199AKLFT, SA000030P00 SILEGO: SLG8SP587V(WF), SA00002XY10

Low Power:

IDT: 9LVS3199AKLFT, SA00003HR00 Realtek: RTM890N-631-GRT, SA00003HQ00

+3VS

R123

4.7K_0402_5%

2

G

1 2

PCH_SMBDATA<14,21,26>

PCH_SMBCLK<14,21,26>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

1 3

D

1 3

D

D_CK_SDATA

S

Q4

Q4 2N7002_SOT23

2N7002_SOT23

+3VS

R125

4.7K_0402_5%

2

G

1 2

S

Q6

Q6 2N7002_SOT23

2N7002_SOT23

2009/08/01 2010/08/01

+3VS

D_CK_SCLK

Compal Secret Data

E

Deciphered Date

C182

10U_0805_10V4Z

+CLK_1.5VS

C186

10U_0805_10V4Z

+CLK_1.05VS +CLK_1.5VS

Change to 5x3.2

+CLK_3VS

0.1U_0402_16V4Z

1

2

1

2

R118 33_0402_5% R118 33_0402_5%

F

C183

2

0.1U_0402_16V4Z

1

C187

2

0.1U_0402_16V4Z

1 2

CLK_BUF_CPU_BCLK <14> CLK_BUF_CPU_BCLK# <14>

+3VS

R120

R120 10K_0402_5%

10K_0402_5%

1 2

CK505_PWRGD

13

D

2

G

Q5

S

2N7002_SOT23

14.31818MHZ 20PF 7A14300003

47P_0402_50V8J

1

C184

2

1

C188

2

0.1U_0402_16V4Z

CLK_ENABLE# <45>

CLK_XTAL_IN

CLK_XTAL_OUT

1

@

@ C30

C30

C31

2

1

2

R122

R122 0_0402_5%

0_0402_5%

1 2

Y1

Title

Size Document Number Rev

Custom

Date: Sheet

C31

2

47P_0402_50V8J

1

@

C189

C32

2

47P_0402_50V8J

20090915 Add for 3G team

D_CK_SCLK <10,11>

D_CK_SDATA <10,11> CLK_BUF_ICH_14M <14>CLK_BUF_DREF_96M<14>

@

C190

12

27P_0402_50V8J

C191

27P_0402_50V8J

12

Compal Electronics, Inc.

SCHEMATICS,MB A5892

401826

G

47P_0402_50V8J

1

@

C33

C34

2

VGATE <15,45>

C34

2

Y1 Change to SJ100009R00 20091117

12 49Tuesday, June 22, 2010

of

H

C

5

+RTCVCC

1 2

R126

R126 20K_0402_1%

20K_0402_1%

PCH_RTCRST#

www.rosefix.com

RC Delay 18~25mS

18P_0402_50V8J

close to RAM door

1 2

R127

@R127

@

10K_0603_5%

C193

1U_0603_10V6K

D D

+RTCVCC

close to RAM door

1 2

R132

R132 20K_0402_1%

20K_0402_1%

1 2

R130 10K_0603_5%

10K_0603_5%

C194

1U_0603_10V6K

1 2

@R130

@

HDA for AUDIO

+3VS

R137

R137 1K_0402_5%

1K_0402_5%

1 2

R138

C C

B B

A A

R138 10K_0402_5%

10K_0402_5%

If GPIO33 pull down, ME will not working. For factory update ME, pull down resistor pull under door.

ME_OVERRIDE<30>

GPIO33 has a weak internal pull-up NOTE: Asserting the GPIO33 low on the rising edge of PWROK will also halt Intel Management Engine after chipset bringup and disable runtime Intel Management Engine features. This is a debug mode and must not be asserted after manfacturing/ debug.

PCH_JTAG_TMS

PCH_JTAG_TDO

PCH_JTAG_TDI

PCH_JTAG_RST#

@

100K_0402_5%

PCH_SPKR

Have internal PD

SERIRQ

PCH_GPIO33#

R140

5

32.768KHZ_12.5PF_Q13MC14610002

PCH_SRTCRST#

RC Delay 18~25mS

modify to 330K

INTVRMEN - Integrated SUS

1.1V VRM Enable High - Enable Internal VRs

HDA_BITCLK_AUDIO<33>

HDA_SYNC_AUDIO<33>

HDA_RST_AUDIO#<33>

HDA_SDOUT_AUDIO<33>

13

D

2

G

Q7

G

12

R151 51_0402_5%@R151 51_0402_5%@ R478 200_0402_1%R478 200_0402_1% R479 100_0402_5% R479 100_0402_5%

R152 51_0402_5%@R152 51_0402_5%@ R480 200_0402_1%R480 200_0402_1% R481 100_0402_5% R481 100_0402_5%

R153 51_0402_5%@R153 51_0402_5%@ R482 200_0402_1%R482 200_0402_1% R483 100_0402_5% R483 100_0402_5%

R154 51_0402_5%@R154 51_0402_5%@ R484 20K_0402_5% R484 20K_0402_5% R485 10K_0402_5% R485 10K_0402_5%

Q7

S

2N7002_SOT23

1 2 1 2 1 2

PCH_SPI_CLK_1 PCH_SPI_CS0#

PCH_SPI_MISO_1 PCH_SPI_MISO

+RTCVCC

+3VALW

3 2

18P_0402_50V8J

R133 1M_0402_5% R133 1M_0402_5% R134 330K_0402_1% R134 330K_0402_1%

+1.05VS

4

C192

4 1

PCH_RTCX1

10M_0402_5%

PCH_RTCX2

@

R128

12

X1

OSC

NC

OSC

NC

C195

12

1 2 1 2

1 2

R135 33_0402_5%

1 2

R131 33_0402_5%

PCH_SPKR<33>

1 2

R136 33_0402_5%

HDA_SDIN0<33>

1 2

R139 33_0402_5%

GPIO33 can not pull down (manufacturing environments)

PCH_JTAG_TCK<21> PCH_JTAG_TMS<21>

PCH_JTAG_TDI<21>

PCH_JTAG_TDO<21>

PCH_JTAG_RST#<21>

R142 0_0402_5% R142 0_0402_5%

1 2

R143 15_0402_5% R143 15_0402_5%

1 2

PAD

T6

R145 15_0402_5% R145 15_0402_5%

1 2

R147 33_0402_5% R147 33_0402_5%

1 2

20090923 Update

2008 Intel MOW36/MOW50 TDO:

Reserved on ES1 Sample Mount R516, R517 on ES2 Sample

MP mount R689, R690, R691, R692 and remove others

4

X1 Change to mini type 20091102

12

PCH_RTCRST# PCH_SRTCRST# SM_INTRUDER# PCH_INTVRMEN

HDA_BITCLK_PCH HDA_SYNC_PCH PCH_SPKR HDA_RST_PCH#

HDA_SDOUT_PCH

PCH_GPIO33#

PCH_JTAG_TCK

PCH_SPI_CLKPCH_SPI_CLK PCH_SPI_CS0#_R PCH_SPI_CS1#

PCH_SPI_MOSIPCH_SPI_MOSI_1

PCH_SPI_MOSI

PCH_JTAG_TCK

+3VS

3

U4A

REV1.0

B13 D13

C14 D17 A16 A14

A30 D29

P1

C30

G30

F30

E32

F32

B29

H32

J30

M3

K3 K1

J2 J4

BA2 AV3 AY3

AY1 AV1

enable iTPM: SPI_MOSI High

CRB 1.0 Change to 4.7K

R155 3.3K_0402_5% R155 3.3K_0402_5%

1 2

R156 3.3K_0402_5% R156 3.3K_0402_5%

1 2

REV1.0

RTCX1 RTCX2

RTCRST# SRTCRST# INTRUDER# INTVRMEN

HDA_BCLK HDA_SYNC SPKR HDA_RST#

HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3

HDA_SDO

HDA_DOCK_EN# / GPIO33 HDA_DOCK_RST# / GPIO13

JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO TRST#

SPI_CLK SPI_CS0# SPI_CS1#

SPI_MOSI SPI_MISO

IBEXPEAK-M_FCBGA107

IBEXPEAK-M_FCBGA107 <BOM Structure>

R157 1K_0402_5%@R157 1K_0402_5%@

1 2

R158 4.7K_0402_5% R158 4.7K_0402_5%

1 2

LPC

RTCIHDA

SATA

SATA0GP / GPIO21 SATA1GP / GPIO19

SPI JTAG

PCH_SPI_CS0# SPI_WP1# SPI_HOLD1#

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

SERIRQ

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN SATA1RXP SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATAICOMPO

SATAICOMPI

SATALED#

+3VS

1 3 7 4

SPI ROM Footprint 200mil

Security Classification

2009/08/01 2010/08/01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/08/01 2010/08/01

3

Compal Secret Data

LPC_AD0

D33

LPC_AD1

B33

LPC_AD2

C32

LPC_AD3

A32

LPC_FRAME#

C34 A34

F34

SERIRQ

AB9

SATA_DTX_C_PRX_N0

AK7

SATA_DTX_C_PRX_P0

AK6

SATA_PTX_DRX_N0

AK11

SATA_PTX_DRX_P0

AK9

SATA_DTX_C_PRX_N1

AH6

SATA_DTX_C_PRX_P1

AH5

SATA_PTX_DRX_N1

AH9

SATA_PTX_DRX_P1

AH8 AF11

AF9 AF7 AF6

AH3 AH1 AF3 AF1

AD9 AD8 AD6 AD5

AD3 AD1 AB3 AB1

AF16 AF15

T3

Y9 V1

U18

CS# WP# HOLD# GND

MX25L1605DM2I-12G SOP 8P

MX25L1605DM2I-12G SOP 8P SA000021A00

SA000021A00

Deciphered Date

2/10 SATA2, SATA3 not support on HM55

SATA_COMP

SATA_LED#

8

VCC

6

SCLK

5

SI

2

SO

R141 37.4_0402_1% R141 37.4_0402_1%

R144 10K_0402_5% R144 10K_0402_5%

PCH_GPIO21 <21> PCH_GPIO19 <21>

+3VS

PCH_SPI_CLK_1 PCH_SPI_MOSI_1 PCH_SPI_MISO_1

2

LPC_AD0 <30> LPC_AD1 <30> LPC_AD2 <30> LPC_AD3 <30>

LPC_FRAME# <30>

SERIRQ <30>

SATA_DTX_C_PRX_N0 <25>

SATA_DTX_C_PRX_P0 <25> SATA_PTX_DRX_N0 <25> SATA_PTX_DRX_P0 <25>

SATA_DTX_C_PRX_N1 <25>

SATA_DTX_C_PRX_P1 <25> SATA_PTX_DRX_N1 <25> SATA_PTX_DRX_P1 <25>

1 2

SATA_LED# <32>

10K_0402_5%

2

R149

SATA for HDD1

SATA for ODD

+1.05VS

+3VS

1 2

R146 10K_0402_5%@R146 10K_0402_5%@

1 2

R148 10K_0402_5%@R148 10K_0402_5%@

12

R150

R150 10K_0402_5%

10K_0402_5%

@

PCH_SPI_CLK_1

For 3G team Close to U5 20090915

@

1 2

R340 10_0402_5%

Title

SCHEMATICS,MB A5892

Size Document Number Rev

Custom

401826

Date: Sheet

1

+RTCBATT

R129

R129 1K_0402_5%

1K_0402_5%

1 2 1

D1

D1 BAS40-04_SOT23-3

+RTCVCC

1

2

3

C196

0.1U_0402_16V4Z

+3VS

BAS40-04_SOT23-3

2

+CHGRTC

GPIO21 Project

0

NEW70/90

1

NEW71/91

@

1 2

C557 10P_0402_50V8J

Compal Electronics, Inc.

13 49Tuesday, June 22, 2010

of

1

of

C

5

www.rosefix.com

PCIE_DTX_C_PRX_N1<27> PCIE_DTX_C_PRX_P1<27>

For PCIE LAN

For Wireless LAN

D D

PCIE_PTX_C_DRX_N1<27> PCIE_PTX_C_DRX_P1<27>

PCIE_DTX_C_PRX_N2<26> PCIE_DTX_C_PRX_P2<26> PCIE_PTX_C_DRX_N2<26> PCIE_PTX_C_DRX_P2<26>

C197 0.1U_0402_16V7KC197 0.1U_0402_16V7K C198 0.1U_0402_16V7KC198 0.1U_0402_16V7K

12 12

C199 0.1U_0402_16V7KC199 0.1U_0402_16V7K

12

C200 0.1U_0402_16V7KC200 0.1U_0402_16V7K

12

2/10 PCIE7, PCIE8 not support on HM55

C C

For PCIE LAN

LAN_CLKREQ#<27>

For Wireless LAN

MINI1_CLKREQ#<26>

PCH_GPIO18<21>

PCH_GPIO20<21>

B B

+3VS

MINI1_CLKREQ# PCH_GPIO20

A A

PCH_GPIO26

PCH_GPIO25

R177 10K_0402_5% R177 10K_0402_5%

1 2

R178 10K_0402_5% R178 10K_0402_5%

1 2

2009/09/23:Change to +3VALW

R166 10K_0402_5%R166 10K_0402_5%

1 2

R186 10K_0402_5% R186 10K_0402_5%

2009/08/13: Change back to +3VALW

1 2

5

+3VALW

R164 0_0402_5% R164 0_0402_5%

1 2

R165 0_0402_5% R165 0_0402_5%

1 2

EC_LID_OUT# PCH_SMBCLK PCH_SMBDATA

PCH_GPIO60 PCH_SML1CLK

PCH_SML1DAT PCH_GPIO74

PCH_GPIO44 PCH_GPIO56 PCH_GPIO73

4

PCIE_DTX_C_PRX_N1 PCIE_DTX_C_PRX_P1

PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1

PCIE_DTX_C_PRX_N2 PCIE_DTX_C_PRX_P2

PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2

CLK_PCIE_LAN#<27>

CLK_PCIE_LAN<27>

CLK_PCIE_MINI1#<26> CLK_PCIE_MINI1<26>

R179 10K_0402_5%

R179 10K_0402_5% R180 2.2K_0402_5%

R180 2.2K_0402_5% R181 2.2K_0402_5% R181 2.2K_0402_5%

R182 10K_0402_5% R182 10K_0402_5% R183 2.2K_0402_5%

R183 2.2K_0402_5% R184 2.2K_0402_5% R184 2.2K_0402_5%

R185 10K_0402_5% R185 10K_0402_5%

R187 10K_0402_5% R187 10K_0402_5% R188 10K_0402_5% R188 10K_0402_5% R189 10K_0402_5% R189 10K_0402_5%

PCH_GPIO73

PCH_GPIO26

PCH_GPIO44

PCH_GPIO56

1 2 1 2 1 2

1 2 1 2

1 2 1 2 1 2

4

PCH_GPIO18

PCH_GPIO20

PCH_GPIO25

3

U4B

REV1.0

BG30

PERN1

BJ30

PERP1

BF29

PETN1

BH29

PETP1

AW30

PERN2

BA30

PERP2

BC30

PETN2

BD30

PETP2

AU30

PERN3

AT30

PERP3

AU32

PETN3

AV32

PETP3

BA32

PERN4

BB32

PERP4

BD32

PETN4

BE32

PETP4

BF33

PERN5

BH33

PERP5

BG32

PETN5

BJ32

PETP5

BA34

PERN6

AW34

PERP6

BC34

PETN6

BD34

PETP6

AT34

PERN7

AU34

PERP7

AU36

PETN7

AV36

PETP7

BG34

PERN8

BJ34

PERP8

BG36

PETN8

BJ36

PETP8

AK48

CLKOUT_PCIE0N

AK47

CLKOUT_PCIE0P

P9

PCIECLKRQ0# / GPIO73

AM43

CLKOUT_PCIE1N

AM45

CLKOUT_PCIE1P

U4

PCIECLKRQ1# / GPIO18

AM47

CLKOUT_PCIE2N

AM48

CLKOUT_PCIE2P

N4

PCIECLKRQ2# / GPIO20

AH42

CLKOUT_PCIE3N

AH41

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

AM51

CLKOUT_PCIE4N

AM53

CLKOUT_PCIE4P

M9

PCIECLKRQ4# / GPIO26

AJ50

CLKOUT_PCIE5N

AJ52

CLKOUT_PCIE5P

H6

PCIECLKRQ5# / GPIO44

AK53

CLKOUT_PEG_B_N

AK51

CLKOUT_PEG_B_P

P13

PEG_B_CLKRQ# / GPIO56

IBEXPEAK-M_FCBGA107

+3VALW

REV1.0

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML1ALERT# / GPIO74

SMBus

SML1DATA / GPIO75

PCI-E*

Link

Controller

PEG_A_CLKRQ# / GPIO47

PEG

CLKOUT_DP_N / CLKOUT_BCLK1_N

CLKOUT_DP_P / CLKOUT_BCLK1_P

From CLK BUFFER

CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_P

CLKIN_PCILOOPBACK

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

Clock Flex

CLKOUTFLEX3 / GPIO67

Board ID

ID1 GPIO65

A & B test

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK / GPIO58

CL_CLK1

CL_DATA1

CL_RST1#

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKIN_DMI_N

CLKIN_DMI_P

CLKIN_BCLK_N

CLKIN_BCLK_P

CLKIN_DOT_96N CLKIN_DOT_96P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

HIGHLOW

C test

B9 H14 C8

J14 C6 G8

M14 E10 G12

T13 T11 T9

H1

AD43 AD45

AN4 AN2

AT1 AT3

AW24 BA24

AP3 AP1

F18 E18

AH13 AH12

P41

J42

AH51 AH53

AF38

T45

P43

T42

N50

PROJECT_ID1

PROJECT_ID0

EC_LID_OUT# PCH_SMBCLK PCH_SMBDATA

PCH_GPIO60

PCH_GPIO74 PCH_SML1CLK PCH_SML1DAT

PEG_CLKREQ#

1 2

R338 10_0402_5%R338 10_0402_5%

XTAL25_IN XTAL25_OUT

XCLK_RCOMP

R169 90.9_0402_1% R169 90.9_0402_1%

Project Port ID

PROJECT ID

ID1

ID2

GPIO65

GPIO21

00

0

00

100 101

100

Security Classification

2009/08/01 2010/08/01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/08/01 2010/08/01

3

Compal Secret Data

Deciphered Date

2

EC_LID_OUT# <30> PCH_SMBCLK <12,21,26> PCH_SMBDATA <12,21,26>

+3VALW

R159

R159 10K_0402_5%

10K_0402_5%

1 2

20090915 Add

CLK_CPU_DMI# <5> CLK_CPU_DMI <5>

CLK_CPU_DP# <5> CLK_CPU_DP <5>

CLK_BUF_CPU_DMI# <12> CLK_BUF_CPU_DMI <12>

CLK_BUF_CPU_BCLK# <12> CLK_BUF_CPU_BCLK <12>

CLK_BUF_DREF_96M# <12> CLK_BUF_DREF_96M <12>

CLK_BUF_PCIE_SATA# <12> CLK_BUF_PCIE_SATA <12>

1 2

C555 10P_0402_50V8JC555 10P_0402_50V8J

CLK_BUF_ICH_14M <12> CLK_PCI_FB <17>

1 2

R171 10K_0402_5%R171 10K_0402_5%

1 2 1 2

R174 10K_0402_5%@R174 10K_0402_5%@

1 2 1 2

R175 10K_0402_5%R175 10K_0402_5%

ID0 GPIO66

10K_0402_5%R172@ 10K_0402_5%R172@

PROJECT

NEW70

NEW80

1

NEW90

2

1

1. Connect Directly EXPRESS CARD, MINI1, MINI2

2. Level Shift1, Pull-Up to +3VS CLOCK GEN, DIMM1, DIMM2

3. Level Shift2, Pull-Up to +3VS LAN

4. Level Shift3, Pull-Up to +3VS CPU & PCH XDP

6/9 MOW23 Request add 25MHz crystal supporting Integrated Graphics

C203

C203 27P_0402_50V8J

27P_0402_50V8J

1 2

12

R170

+1.05VS

+3VS

PCH_SML1CLK EC_SMB_CK2

PCH_SML1DAT EC_SMB_DA2

Title

Size Document Number Rev

Custom

Date: Sheet

R170

1M_0402_5%

6 1

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6 Q9A

Q9A

3

2N7002DW-T/R7_SOT363-6

SCHEMATICS,MB A5892

SCHEMATICS,MB A5892 401826

401826

12

Y2

Y2 25MHZ_20PF_7A25000012

25MHZ_20PF_7A25000012

1 2

C204

C204 27P_0402_50V8J

27P_0402_50V8J

+3VS

2

+3VS

Pull high +3VS at KB926 side

5

4

Q9B

Compal Electronics, Inc.

1

Change to 5x3.2

EC_SMB_CK2 <30>

EC_SMB_DA2 <30>

14 49Tuesday, June 22, 2010

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5

DMI_HTX_PRX_N[0..3]<4>

DMI_HTX_PRX_P[0..3]<4> DMI_PTX_HRX_N[0..3]<4> DMI_PTX_HRX_P[0..3]<4>

www.rosefix.com

DMI_HTX_PRX_N[0..3] DMI_HTX_PRX_P[0..3] DMI_PTX_HRX_N[0..3] DMI_PTX_HRX_P[0..3]

4

3

2

1

D D

+3VS

R190 8.2K_0402_5%R190 8.2K_0402_5%

+3VALW

R191 10K_0402_5%R191 10K_0402_5% R193 8.2K_0402_5%R193 8.2K_0402_5%

C C

B B

R194 10K_0402_5%R194 10K_0402_5% R195 10K_0402_5%R195 10K_0402_5% R196 10K_0402_5%

R196 10K_0402_5%

H_FDI_TXN[0..7]<4> H_FDI_TXP[0..7]<4>

1 2

1 2 1 2 1 2 1 2

@

1 2

10/2 Intel suggestion change to 10K

SYS_PWROK<21>

PM_CLKRUN#

SUS_PWR_ACK PCH_GPIO72 EC_SWI# PCH_PCIE_WAKE# PM_SLP_LAN#

+3VALW

EC_ACIN<30>

SYS_PWROK

U6 change to SA00000OH00

A A

5

H_FDI_TXN[0..7] H_FDI_TXP[0..7]

+1.05VS

R192

49.9_0402_1%

1 2

R195 Change to 10K for WW37 20090916

XDP_DBRESET#<5,21>

SYS_PWROK VGATE

SYS_PWROK

EC_PWROK

LAN_RST#

R197 0_0402_5% R197 0_0402_5% R198 0_0402_5%@R198 0_0402_5%@

1 2

R199 10K_0402_5%

CH751H-40PT_SOD323-2

R203 0_0402_5%@R203 0_0402_5%@

+3VS

4

Y

1 2

R205 10K_0402_5%

1 2

R206 10K_0402_5%

1 2

R207 10K_0402_5%

No used Integrated LAN, connecting LAN_RST# to GND

12 12

PM_DRAM_PWRGD<5>

SUS_PWR_ACK<30>

PBTN_OUT#<5,21,30>

21

D2

EC_SWI#<30>

12

5

U6

2

P

B

1

A

G

NC7SZ08P5X_NL_SC70-5

3

EC_PWROK VGATE

DMI_HTX_PRX_N0 DMI_HTX_PRX_N1 DMI_HTX_PRX_N2 DMI_HTX_PRX_N3

DMI_HTX_PRX_P0 DMI_HTX_PRX_P1 DMI_HTX_PRX_P2 DMI_HTX_PRX_P3

DMI_PTX_HRX_N0 DMI_PTX_HRX_N1 DMI_PTX_HRX_N2 DMI_PTX_HRX_N3

DMI_PTX_HRX_P0 DMI_PTX_HRX_P1 DMI_PTX_HRX_P2 DMI_PTX_HRX_P3

DMI_COMP

XDP_DBRESET#

SYS_PWROK_R

SYS_PWROK

LAN_RST#

PCH_RSMRST#

SUS_PWR_ACK

PBTN_OUT#

PCH_ACIN

PCH_GPIO72

EC_SWI#

EC_PWROK <30> VGATE <12,45>

4

U4C

BC24

DMI0RXN

BJ22

DMI1RXN

AW20

DMI2RXN

BJ20

DMI3RXN

BD24

DMI0RXP

BG22

DMI1RXP

BA20

DMI2RXP

BG20

DMI3RXP

BE22

DMI0TXN

BF21

DMI1TXN

BD20

DMI2TXN

BE18

DMI3TXN

BD22

DMI0TXP

BH21

DMI1TXP

BC20

DMI2TXP

BD18

DMI3TXP

BH25

DMI_ZCOMP

BF25

DMI_IRCOMP

T6

SYS_RESET#

M6

SYS_PWROK

B17

PWROK

K5

MEPWROK

A10

LAN_RST#

D9

DRAMPWROK

C16

RSMRST#

M1

SUS_PWR_DN_ACK / GPIO30

P5

PWRBTN#

P7

ACPRESENT / GPIO31

A6

BATLOW# / GPIO72

F14

RI#

IBEXPEAK-M_FCBGA107

IBEXPEAK-M_FCBGA107 <BOM Structure>

REV1.0

FDI_FSYNC0

DMI

FDI

DMI

FDI

FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

System Power Management

SLP_LAN# / GPIO29

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

FDI_INT

WAKE#

SLP_S4#

SLP_S3#

SLP_M#

TP23

PMSYNCH

BA18 BH17 BD16 BJ16 BA16 BE14 BA14 BC12

BB18 BF17 BC16 BG16 AW16 BD14 BB14 BD12

BJ14 BF13 BH13 BJ12 BG14

PCH_PCIE_WAKE#

J12

PM_CLKRUN#

Y1

PCH_GPIO61

P8

F3

E4

H7

P12

PM_SLP_M#

K8

PM_SLP_DSW#

N2

BJ10

PM_SLP_LAN#

F6

2009/08/01 2010/08/01

3

H_FDI_TXN0 H_FDI_TXN1 H_FDI_TXN2 H_FDI_TXN3 H_FDI_TXN4 H_FDI_TXN5 H_FDI_TXN6 H_FDI_TXN7

H_FDI_TXP0 H_FDI_TXP1 H_FDI_TXP2 H_FDI_TXP3 H_FDI_TXP4 H_FDI_TXP5 H_FDI_TXP6 H_FDI_TXP7

PCH_PCIE_WAKE# <26,27>

PM_CLKRUN# <30>

@

PAD

T7

PCH_SUSCLK <30>

PM_SLP_S5# <30>

PM_SLP_S4# <30>

PM_SLP_S3# <30>

@

PAD

T9

@

PAD

T10

H_PM_SYNC <5>

Compal Secret Data

Deciphered Date

H_FDI_INT <4> H_FDI_FSYNC0 <4> H_FDI_FSYNC1 <4> H_FDI_LSYNC0 <4> H_FDI_LSYNC1 <4>

32.768KHZ ouput for remove EC crystal 20091103

2

@

R200 0_0402_5%

Q11

Q11 MMBT3906_SOT23-3

PCH_RSMRST#

R201

R201 10K_0402_5%

10K_0402_5%

Title

Size Document Number Rev

Custom

Date: Sheet

MMBT3906_SOT23-3

12

Compal Electronics, Inc.

SCHEMATICS,MB A5892

SCHEMATICS,MB A5892 401826

401826

@

12

123

C

E

B

1 2

R202 4.7K_0402_5%R202 4.7K_0402_5%

D3A

1 2

BAV99DW-7_SOT363

D3B

4 5

BAV99DW-7_SOT363

6

3

1

EC_RSMRST# <30>

+3VALW

12

R204

2.2K_0402_5%

15 49Tuesday, June 22, 2010

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