Acer Aspire 5020 Schematics

5

4

3

2

1

See 'TEXT' in 0MEMO or 1MEMO property in component

Dummy when 'USE EZ4'

Dummy when 'NO EZ4'

Dummy when use '10/100'

Dummy when use 'GIGA'

D D

Dummy when use 'UMA'

Dummy when use 'DIS'

Dummy when use 'SATA'

Dummy when use 'IDE'

Dummy when use ''M26'

Dummy when use ''M24'

CLK GEN

IDT CV137

LEDs RTC BAT. BUTTONs

Bolsena Block Diagram

AMD CPU

3

17 18 35

35W/25W

4,5,6,7

HyperTransport

6.4GB/S 16b/8b

DDR 333/400

91.4C501.001 (04243)

200-PIN DDR SODIMM

DDR x2

SVIDEO/COMP

8,9,10

TVOUT

16

PWR SW

TSP2220A

PCMCIA SLOT

Support TypeII

C C

28

1394 4pin Conn

28

PCMCIA I/F

MS/xD SM/MMC/SD

5 in 1

28

TI

PCI 7411

1* Slot Cardbus 1* 1394 CardReader

26,27

ATI

RS480M

AGTL+ CPU I/F + UMA

11,12,13,14

PCI-Express x2

PCI Express x16

VRAM x4

ATI

M26/M24

50,51,52

53,54(M26/M24 diff.)

CH7301C

LVDS

RGB CRT

15

TMDS

ATI

PCI

25

SB400

ACPI 2.0

ATA 133

18,19,20,21,22

PIDE

HDD

25

6xUSB 2.0

6-CH AC97 2.2

LPC I/F

SIDE

DVD/ CD-RW

USB x 4

24

AC97

MODEM MDC Card

NS SIO

PC87392

25

FIR

RJ11 CONN

37

LPC Bus / 33MHz

Thermal & Fan

G792

CODEC

ALC655

32

OP AMP

30

G1421

3324

KBC

23

KB3910

Touch Pad

35 35

34

Int. KB

Mini-PCI

PCI Bus / 33MHz

802.11a/b/g

31

RJ45

TXFM

30

1000Mb

PCI LAN

Realtek RTL8110SBL

B B

TXFM

10/100Mb

30

1000/100/10 RTL8100C 100/10

29

SATA

LCD

CRT

DVI-D

(EZ4 only )

BlueTooth miniUSB

Line In MIC In

Line Out

Int. SPKR

XBUS

17

16

15

24

33

ISA ROM

Power Block Diag -> Page 40

36

A A

Port Replicator 4 (124 PIN)

AC IN

RJ45-11

SEARIAL PORT

5

CRT

PRINTER

PS2

4

MIC

LINE IN

LINE OUT

TV OUT

DVI PCIeX2 SMBUS

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

BLOCK DIAGRAM

Size Document Number Rev

A3

Bolsena

Date: Sheet

Date: Sheet of

158Tuesday, April 12, 2005

of

1

-1

5

4

3

2

1

PCI Routing

IRQ

MiniPCI

LAN

D D

21 23 2 22 17411 E (CardBus)

F H

22 17411 G (1394) 22 17411 E (FlashMedia)

C C

REQ/GNTIDSEL

0

B B

Ref. function schematic BOM

------------------------U81 cpu socket 62.10055.091 (DON'T CHANGE) (3mm high) U80 north bridge 71.RS48M.00U 71.RS48M.B0U (ver A22) U43 south bridge 71.SB400.B0U 71.SB400.D0U (ver A32) U32 clock gen. 71.00137.A0W 71.00137.B0W

--U70 VGA M24 71.0M26P.00U 71.00M24.C0U U64 VRAM FOR M24 72.55732.B0U 72.52832.E05 U65 VRAM FOR M24 72.55732.B0U 72.52832.E05 U69 VRAM FOR M24 72.55732.B0U 72.52832.E05 U71 VRAM FOR M24 72.55732.B0U 72.52832.E05

--U70 VGA M26 71.0M26P.00U (DON'T CHANGE) U64 VRAM FOR M26 72.55732.B0U (DON'T CHANGE) U65 VRAM FOR M26 72.55732.B0U (DON'T CHANGE) U69 VRAM FOR M26 72.55732.B0U (DON'T CHANGE) U71 VRAM FOR M26 72.55732.B0U (DON'T CHANGE)

--U66 BIOS SOCKET 72.39040.G03 62.10002.032 (NO NEED WHEN PD) U66 BIOS IC 72.39040.G03 72.39040.H03 (DIP STAGE IN LAB, SMT IN PD)

---

A A

LOUT1 AUDIO 22.10257.001 22.10147.031 (NO SPDIF)

--U75 GIGA LAN 71.08110.00G 71.08110.A0G U75 10/100 LAN 71.08110.00G 71.08100.C0G

--HDD1 20.80175.044 20.80592.044 SATA1 20.F0614.022 20.F0665.022 EZ4 20.80579.120 20.80591.120 (AFTER SB)

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CHANGE HISTORY

Size Document Number Rev

Bolsena -1

A3

Bolsena -1

A3

Bolsena -1

A3

Date: Sheet

258Thursday, March 31, 2005

of

1

of

A

3D3V_S0

L14

1 2

0R0603-PAD

SC 0308

4 4

12

C421

C421 SCD1U16V

SCD1U16V

C416

C416 SCD1U16V

SCD1U16V

12

C423

C423 SCD1U16V

SCD1U16V

C417

C417 SCD1U16V

SCD1U16V

Dummy when 'NO EZ4'

SMBC_SB_EZ457 SMBD_SB_EZ457

RN120

SRN33-2-U2

SMBC_SB8,21

3 3

SMBD_SB8,21

SC 0309

SB_OSC_CLK21

CLK14_AUDIO32

1

23

4

12

C397

C397 SCD1U16V

SCD1U16V

12

C420

C420 SCD1U16V

SCD1U16V

R279

1 2

R280

1 2

CLK48_CARDBUS26

CLK48_USB21

R261 33R2R261 33R2

1 2 1 2

R260 33R2R260 33R2

33R2

12

1 2

C398

C398 SCD1U16V

SCD1U16V

C419

C419 SCD1U16V

SCD1U16V

C400

SC33P50V2JN

X-14D318MHZ-1-U1

1 2

C422

SC33P50V2JN

CLK14_NB13

CLK14_SIO37

B

12

C415

C415 SC10U10V5ZY

SC10U10V5ZY

3D3V_CLK_VDDA

3D3V_S0 3D3V_CLK_VDD

12

R264 22R2R264 22R2

1 2

R263 22R2R263 22R2

1 2

SB 0219

3D3VDD48_S0

12

C399

C399 SC2D2U16V5ZY

SC2D2U16V5ZY

R278

R278 DUMMY-R3

DUMMY-R3

R277

1 2

R274

1 2

R273

1 2

12

R298

R298 100R2F

100R2F

75R2F

USB_48M SMBC_CLK SMBD_CLK

33R2

IREF_CLKGEN

12

FS2 FS1 FS0

CLK_REF2 CLK_HTT66

R272

R272 475R2F

475R2F

X2

SC 0309

HTREF_CLK13

1 2

0R0603-PAD

SC 0308

XI_CLK

XO_CLK

L13

U32

3

VDD_48

39

VDDA

32

VDD_SRC

21

VDD_SRC

14

VDD_SRC

35

VDD_SRC

56

VDD_REF

51

VDD_PC1

43

VDD_CPU

48

VDD_HTT

1

XIN

2

XOUT

4

USB_48

7

SCL

8

SDA

10

CLKREQ0#

11

CLKREQ1#

9

SEL24/24_48#

53

REF1

54

REF0

52

REF2

47

HTT66

50

PCI0

37

IREF

6

NC#6

IDTCV137PAG

CHANGE TO 71.00137.B0W

C

SRCC0 SRCT0 SRCC3 SRCT3 SRCC4 SRCT4 SRCC5 SRCT5 SRCC6 SRCT6 SRCC7 SRCT7

CPUC1 CPUT1 CPUC0 CPUT0

SRCC1 SRCT1 SRCC2 SRCT2

VSS_SRC VSS_SRC

RESET#

TURBO1

VSS_CPU

VSS_PCI

VSS_HTT

VSS_SRC

VSS_48

VSS_REF

VSSA

33 34 25 24 23 22 19 18 17 16 13 12

40 41 44 45

29 30 28 27

36 20 15 26

42 49 46 31 38 5 55

3D3V_CLK_VDDA3D3V_CLK_VDD

12

C418

C418 SCD1U16V

SCD1U16V

SRC_CLK0# SRC_CLK0 SRC_CLK3# SRC_CLK3 SRC_CLK4# SRC_CLK4 SRC_CLK5# SRC_CLK5

CPUCLKJ_CY CPUCLK_CY

ATI_CLK0# ATI_CLK0 ATI_CLK1# ATI_CLK1

3D3V_S0

L12

1 2

0R0603-PAD

12

C414

C414 SC10U10V5ZY

SC10U10V5ZY

R296 15R2JR296 15R2J

1 2

R297 15R2JR297 15R2J

1 2

RN55

2 3 1

SRN33-2-U2

RN44

1 2 3

SRN33-2-U2

SC 0308

2 3 1

1 2 3

RN46

1 2 3

SRN33-2-U2

SRN33-2-U2 RN47

RN47

1 2 3

SRN33-2-U2

Dummy when no EZ4

4

Dummy when use UMA

D

RN56

SRN33-2-U2

4

RN45

4

SRN33-2-U2

4

CPUCLK# 6 CPUCLK 6

NBSRC_CLK# 13 NBSRC_CLK 13

GFX_CLK# 49 GFX_CLK 49

SBLINK_CLK# 13 SBLINK_CLK 13

SBSRC_CLK# 18 SBSRC_CLK 18

CLK_PCIE_DOCK1# 57 CLK_PCIE_DOCK1 57

CLK_PCIE_DOCK2# 57 CLK_PCIE_DOCK2 57

CLK_PCIE_DOCK1# CLK_PCIE_DOCK1 CLK_PCIE_DOCK2# CLK_PCIE_DOCK2

SBLINK_CLK# SBLINK_CLK SBSRC_CLK# SBSRC_CLK GFX_CLK# GFX_CLK

E

R253

1 2

49D9R2F

R254

1 2

49D9R2F

R255

1 2

49D9R2F

R256

1 2

49D9R2F

Dummy when no EZ4

R294

1 2

R295

1 2

R251

1 2

R252

1 2

R249

1 2

R250

1 2

49D9R2F

49D9R2F 49D9R2F

49D9R2F

Dummy when use UMA

2 2

NBSRC_CLK# NBSRC_CLK

3D3V_CLK_VDD

DY

R281

1 2

2K2R2

1 2

DUMMY-R2

R299

R275

1 2

1 1

R257

1 2 1 2

R276

R258

2K2R2

DY

DUMMY-R2

DY

2K2R2

2K2R2 DUMMY-R2

DUMMY-R2

for ICS

A

FS0

FS1

FS2

Title

Size Document Number Rev

A3

Date: Sheet

B

C

D

Date: Sheet

CLKGEN_IDTCV137

Bolsena

R292

1 2

49D9R2F

R293

1 2

49D9R2F

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

358Thursday, March 31, 2005

of

E

of

-1

A

4 4

B

C

D

E

HTT for CPU sideA Transmit power and NB sideA Receive power

1D2V_S0

12

3 3

C244

C244 SCD22U16V3ZY

SCD22U16V3ZY

12

C245

C245 SCD22U16V3ZY

SCD22U16V3ZY

12

NB0CADOUT[15..0]11 NB0CADOUTJ[15..0]11

C246

C246 SCD22U16V3ZY

SCD22U16V3ZY

Used SideB Power Plane

2 2

1D2V_HT0B_S0

1 1

12

C247

C247 SCD22U16V3ZY

SCD22U16V3ZY

NB0HTTCLKOUT111 NB0HTTCLKOUTJ111 NB0HTTCLKOUT011 NB0HTTCLKOUTJ011

1 2 1 2

NB0HTTCTLOUT11 NB0HTTCTLOUTJ11

R176 49D9R2FR176 49D9R2F R177 49D9R2FR177 49D9R2F

NB0CADOUT15 NB0CADOUTJ15 NB0CADOUT14 NB0CADOUTJ14 NB0CADOUT13 NB0CADOUTJ13 NB0CADOUT12 NB0CADOUTJ12 NB0CADOUT11 NB0CADOUTJ11 NB0CADOUT10 NB0CADOUTJ10 NB0CADOUT9 NB0CADOUTJ9 NB0CADOUT8 NB0CADOUTJ8 NB0CADOUT7 NB0CADOUTJ7 NB0CADOUT6 NB0CADOUTJ6 NB0CADOUT5 NB0CADOUTJ5 NB0CADOUT4 NB0CADOUTJ4 NB0CADOUT3 NB0CADOUTJ3 NB0CADOUT2 NB0CADOUTJ2 NB0CADOUT1 NB0CADOUTJ1 NB0CADOUT0 NB0CADOUTJ0

NB0HTTCLKOUT1 NB0HTTCLKOUTJ1 NB0HTTCLKOUT0 NB0HTTCLKOUTJ0

CPUHTTCTLIN1 CPUHTTCTLINJ1 NB0HTTCTLOUT NB0HTTCTLOUTJ

U81A

D29

VLDT0_A

D27

VLDT0_A

D25

VLDT0_A

C28

VLDT0_A

C26

VLDT0_A

B29

VLDT0_A

B27

VLDT0_A

T25

L0_CADIN_H15

R25

L0_CADIN_L15

U27

L0_CADIN_H14

U26

L0_CADIN_L14

V25

L0_CADIN_H13

U25

L0_CADIN_L13

W27

L0_CADIN_H12

W26

L0_CADIN_L12

AA27

L0_CADIN_H11

AA26

L0_CADIN_L11

AB25

L0_CADIN_H10

AA25

L0_CADIN_L10

AC27

L0_CADIN_H9

AC26

L0_CADIN_L9

AD25

L0_CADIN_H8

AC25

L0_CADIN_L8

T27

L0_CADIN_H7

T28

L0_CADIN_L7

V29

L0_CADIN_H6

U29

L0_CADIN_L6

V27

L0_CADIN_H5

V28

L0_CADIN_L5

Y29

L0_CADIN_H4

W29

L0_CADIN_L4

AB29

L0_CADIN_H3

AA29

L0_CADIN_L3

AB27

L0_CADIN_H2

AB28

L0_CADIN_L2

AD29

L0_CADIN_H1

AC29

L0_CADIN_L1

AD27

L0_CADIN_H0

AD28

L0_CADIN_L0

Y25

L0_CLKIN_H1

W25

L0_CLKIN_L1

Y27

L0_CLKIN_H0

Y28

L0_CLKIN_L0

R27

L0_CTLIN_H1

R26

L0_CTLIN_L1

T29

L0_CTLIN_H0

R29

L0_CTLIN_L0

62.10055.091

SB 0127

ME : 60.10055.091 (3MM HEIGHT)

VLDT0_B VLDT0_B VLDT0_B VLDT0_B VLDT0_B VLDT0_B VLDT0_B

L0_CADOUT_H15

L0_CADOUT_L15

L0_CADOUT_H14

L0_CADOUT_L14

L0_CADOUT_H13

L0_CADOUT_L13

L0_CADOUT_H12

L0_CADOUT_L12

L0_CADOUT_H11

L0_CADOUT_L11

L0_CADOUT_H10

L0_CADOUT_L10

L0_CADOUT_H9

L0_CADOUT_L9

L0_CADOUT_H8

L0_CADOUT_L8

L0_CADOUT_H7

L0_CADOUT_L7

L0_CADOUT_H6

L0_CADOUT_L6

L0_CADOUT_H5

L0_CADOUT_L5

L0_CADOUT_H4

L0_CADOUT_L4

L0_CADOUT_H3

L0_CADOUT_L3

L0_CADOUT_H2

L0_CADOUT_L2

L0_CADOUT_H1

L0_CADOUT_L1

L0_CADOUT_H0

L0_CADOUT_L0 L0_CLKOUT_H1

L0_CLKOUT_L1

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CTLOUT_H1

L0_CTLOUT_L1

L0_CTLOUT_H0

L0_CTLOUT_L0

AH29 AH27 AG28 AG26 AF29 AE28 AF25

N26 N27 L25 M25 L26 L27 J25 K25 G25 H25 G26 G27 E25 F25 E26 E27 N29 P29 M28 M27 L29 M29 K28 K27 H28 H27 G29 H29 F28 F27 E29 F29

J26 J27 J29 K29

N25 P25 P28 P27

CPUCADOUT15 CPUCADOUTJ15 CPUCADOUT14 CPUCADOUTJ14 CPUCADOUT13 CPUCADOUTJ13 CPUCADOUT12 CPUCADOUTJ12 CPUCADOUT11 CPUCADOUTJ11 CPUCADOUT10 CPUCADOUTJ10 CPUCADOUT9 CPUCADOUTJ9 CPUCADOUT8 CPUCADOUTJ8 CPUCADOUT7 CPUCADOUTJ7 CPUCADOUT6 CPUCADOUTJ6 CPUCADOUT5 CPUCADOUTJ5 CPUCADOUT4 CPUCADOUTJ4 CPUCADOUT3 CPUCADOUTJ3 CPUCADOUT2 CPUCADOUTJ2 CPUCADOUT1 CPUCADOUTJ1 CPUCADOUT0 CPUCADOUTJ0

CPUHTTCLKOUT1 CPUHTTCLKOUTJ1 CPUHTTCLKOUT0 CPUHTTCLKOUTJ0

CPUHTTCTLOUT0 CPUHTTCTLOUTJ0

HTT for CPU sideB Receive power and NB sideA Transmit power

1D2V_HT0B_S0

12

Used SideA Power Plane

CPUHTTCLKOUT1 11 CPUHTTCLKOUTJ1 11 CPUHTTCLKOUT0 11 CPUHTTCLKOUTJ0 11

CPUHTTCTLOUT0 11 CPUHTTCTLOUTJ0 11

C242

C242 SC4D7U10V5ZY

SC4D7U10V5ZY

LAYOUT: Place bypass cap on topside of board near HTT power pins that are not connected directly to downstream HTT device, but connected internally to other HTT power pins.

CPUCADOUT[15..0] 11 CPUCADOUTJ[15..0] 11

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

A

B

C

D

Date: Sheet

CPU(1/4)_HyperTransport I/F

Bolsena

458Thursday, March 31, 2005

of

E

of

-1

A

VREF_DDR_MEM

B

C

D

E

NOTE: Test with passive probes only. NOTE: Install to bypass op-amp

2D5V_S3

4 4

12

R291

R291 100R2F

100R2F

R290

R290 100R2F

100R2F

12

C441

C441 SCD1U

SCD1U

12

VREF_DDR_MEM

C440

C440 SCD1U

SCD1U

12

C439

C439 SC1000P50V2KX

SC1000P50V2KX

2D5V_S3

M_DATA[63..0]9

1 2 1 2

LAYOUT: Locate close to DIMMs.

NOTE: Remove to bypass op-amp

3 3

VREF_DDR_CLAW

2D5V_S3

12

2 2

Place it near CPU

1 1

12

R197

R197 100R2F

100R2F

R198

R198 100R2F

100R2F

C309

C309 SCD1U

SCD1U

12

C311

C311 SCD1U

SCD1U

VREF_DDR_CLAW

LAYOUT: Locate close to CPU.

R203

1 2

R204

1 2

R199

1 2

R200

1 2

121R2F

A

M_CLK7 M_CLK#7

M_CLK6 M_CLK#6

M_CLK5 M_CLK#5

M_CLK4 M_CLK#4

12

C312

C312 SC1000P50V2KX

SC1000P50V2KX

M_ADM[7..0]9

M_DQS[7..0]9

B

TP47TPAD30 TP47TPAD30

VREF_DDR_CLAW

R206 34D8R2FR206 34D8R2F R205 34D8R2FR205 34D8R2F

DDRVTT_SENSE

MEMZN MEMZP

M_DATA63 M_DATA62 M_DATA61 M_DATA60 M_DATA59 M_DATA58 M_DATA57 M_DATA56 M_DATA55 M_DATA54 M_DATA53 M_DATA52 M_DATA51 M_DATA50 M_DATA49 M_DATA48 M_DATA47 M_DATA46 M_DATA45 M_DATA44 M_DATA43 M_DATA42 M_DATA41 M_DATA40 M_DATA39 M_DATA38 M_DATA37 M_DATA36 M_DATA35 M_DATA34 M_DATA33 M_DATA32 M_DATA31 M_DATA30 M_DATA29 M_DATA28 M_DATA27 M_DATA26 M_DATA25 M_DATA24 M_DATA23 M_DATA22 M_DATA21 M_DATA20 M_DATA19 M_DATA18 M_DATA17 M_DATA16 M_DATA15 M_DATA14 M_DATA13 M_DATA12 M_DATA11 M_DATA10 M_DATA9 M_DATA8 M_DATA7 M_DATA6 M_DATA5 M_DATA4 M_DATA3 M_DATA2 M_DATA1 M_DATA0

M_ADM8 M_ADM7 M_ADM6 M_ADM5 M_ADM4 M_ADM3 M_ADM2 M_ADM1 M_ADM0 M_DQS8 M_DQS7 M_DQS6 M_DQS5 M_DQS4 M_DQS3 M_DQS2 M_DQS1 M_DQS0

AE13

AG12

D14 C14

A16 B15 A12 B11 A17 A15 C13 A11 A10

C11

AC1 AC3

AC2 AD1 AE1 AE3

AG3

AJ4

AE2

AF1

AH3

AJ3 AJ5 AJ6

AJ7 AH9 AG5 AH5

AJ9

AJ10

AH11

AJ11

AH15

AJ15

AG11

AJ12 AJ14 AJ16

A13

AA1 AG1 AH7

AH13

A14

AB1

AJ2

AJ8

AJ13

B9 C7 A6

A9 A5 B5 C5 A4 E2 E1 A3 B3 E3

F1 G2 G1

L3

L1 G3

J2

L2 M1 W1 W3

W2

Y1

R1

A7

C2

H1

T1

A8

D1

J1

VTT_SENSE

MEMVREF1 MEMZN

MEMZP

MEMDATA63 MEMDATA62 MEMDATA61 MEMDATA60 MEMDATA59 MEMDATA58 MEMDATA57 MEMDATA56 MEMDATA55 MEMDATA54 MEMDATA53 MEMDATA52 MEMDATA51 MEMDATA50 MEMDATA49 MEMDATA48 MEMDATA47 MEMDATA46 MEMDATA45 MEMDATA44 MEMDATA43 MEMDATA42 MEMDATA41 MEMDATA40 MEMDATA39 MEMDATA38 MEMDATA37 MEMDATA36 MEMDATA35 MEMDATA34 MEMDATA33 MEMDATA32 MEMDATA31 MEMDATA30 MEMDATA29 MEMDATA28 MEMDATA27 MEMDATA26 MEMDATA25 MEMDATA24 MEMDATA23 MEMDATA22 MEMDATA21 MEMDATA20 MEMDATA19 MEMDATA18 MEMDATA17 MEMDATA16 MEMDATA15 MEMDATA14 MEMDATA13 MEMDATA12 MEMDATA11 MEMDATA10 MEMDATA9 MEMDATA8 MEMDATA7 MEMDATA6 MEMDATA5 MEMDATA4 MEMDATA3 MEMDATA2 MEMDATA1 MEMDATA0

MEMDQS17 MEMDQS16 MEMDQS15 MEMDQS14 MEMDQS13 MEMDQS12 MEMDQS11 MEMDQS10 MEMDQS9 MEMDQS8 MEMDQS7 MEMDQS6 MEMDQS5 MEMDQS4 MEMDQS3 MEMDQS2 MEMDQS1 MEMDQS0

U81BU81B

MEMRESET_L

MEMCLK_H7 MEMCLK_L7 MEMCLK_H6 MEMCLK_L6 MEMCLK_H5 MEMCLK_L5 MEMCLK_H4 MEMCLK_L4 MEMCLK_H3 MEMCLK_L3 MEMCLK_H2 MEMCLK_L2 MEMCLK_H1 MEMCLK_L1 MEMCLK_H0 MEMCLK_L0

MEMCS_L7 MEMCS_L6 MEMCS_L5 MEMCS_L4 MEMCS_L3 MEMCS_L2 MEMCS_L1 MEMCS_L0

MEMRASA_L MEMCASA_L

MEMWEA_L

MEMBANKA1 MEMBANKA0

MEMADDA13 MEMADDA12 MEMADDA11 MEMADDA10

MEMADDA9 MEMADDA8 MEMADDA7 MEMADDA6 MEMADDA5 MEMADDA4 MEMADDA3 MEMADDA2 MEMADDA1 MEMADDA0

MEMRASB_L MEMCASB_L

MEMWEB_L

MEMBANKB1 MEMBANKB0

MEMADDB13 MEMADDB12 MEMADDB11 MEMADDB10

MEMADDB9 MEMADDB8 MEMADDB7 MEMADDB6 MEMADDB5 MEMADDB4 MEMADDB3 MEMADDB2 MEMADDB1 MEMADDB0

MEMCHECK7 MEMCHECK6 MEMCHECK5 MEMCHECK4 MEMCHECK3 MEMCHECK2 MEMCHECK1 MEMCHECK0

C

VTT_A VTT_A VTT_A VTT_A VTT_B VTT_B VTT_B VTT_B

MEMCKEA MEMCKEB

NC_E13 NC_C12

NC_E14 NC_D12

D17 A18 B17 C17 AF16 AG16 AH16 AJ17

AG10 AE8

AE7 D10

C10 E12 E11 AF8 AG8 AF10 AE10 V3 V4 K5 K4 R5 P5 P3 P4

D8 C8 E8 E7 D6 E6 C4 E5

H5 D4 G5

K3 H3

E13 C12 E10 AE6 AF3 M5 AE5 AB5 AD3 Y5 AB4 Y3 V5 T5 T3 N5

H4 F5 F4

L5 J5

E14 D12 E9 AF6 AF4 M4 AD5 AC5 AD4 AA5 AB3 Y4 W5 U5 T4 M3

N3 N1 U3 V1 N2 P1 U1 U2

1D25V_S3

MEMRESET# M_CKE#0

M_CKE#1 M_CLK7

M_CLK#7 M_CLK6 M_CLK#6 M_CLK5 M_CLK#5 M_CLK4 M_CLK#4

M_CLK1 M_CLK#1 M_CLK0 M_CLK#0

M_CS#7 M_CS#6 M_CS#5 M_CS#4 M_CS#3 M_CS#2 M_CS#1 M_CS#0

M_ARAS# M_ACAS# M_AWE#

M_ABS#1 M_ABS#0

RSVD_M_AA15 RSVD_M_AA14 M_AA13 M_AA12 M_AA11 M_AA10 M_AA9 M_AA8 M_AA7 M_AA6 M_AA5 M_AA4 M_AA3 M_AA2 M_AA1 M_AA0

M_BRAS# M_BCAS# M_BWE#

M_BBS#1 M_BBS#0

RSVD_M_BA15 RSVD_M_BA14 M_BA13 M_BA12 M_BA11 M_BA10 M_BA9 M_BA8 M_BA7 M_BA6 M_BA5 M_BA4 M_BA3 M_BA2 M_BA1 M_BA0

CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0

12

For REGISTED DIMM Only UNBUFFER DIMM NC

12

C267

M_CKE#0 8,9 M_CKE#1 8,9

M_CLK7 8 M_CLK#7 8 M_CLK6 8 M_CLK#6 8 M_CLK5 8 M_CLK#5 8 M_CLK4 8 M_CLK#4 8

M_CS#3 8,9 M_CS#2 8,9 M_CS#1 8,9 M_CS#0 8,9

M_ARAS# 8,9 M_ACAS# 8,9 M_AWE# 8,9

M_ABS#1 8,9 M_ABS#0 8,9

M_BRAS# 8,9 M_BCAS# 8,9 M_BWE# 8,9

M_BBS#1 8,9 M_BBS#0 8,9

TP60

TPAD30

TP90

TPAD30

TP59

TPAD30

TP83

TPAD30

TP89

TPAD30

TP88

TPAD30

TP84

TPAD30

TP85

TPAD30

C267 SC1000P50V2KX

SC1000P50V2KX

M_CLK#1 M_CLK#0 M_CLK1 M_CLK0

M_AA[13..0] 8,9

M_BA[13..0] 8,9

Title

Size Document Number Rev

A3

Date: Sheet

Date: Sheet of

C266

C266 SCD1U

SCD1U

AMD suggested M_AA13 connect to DIMM pin123

AMD suggested M_BA13 connect to DIMM pin123

D

2D5V_S3

RN36

1

8

2

7

3

6

45

SRN10K-2

M_DQS8 M_ADM8

MEMRESET# M_CS#7 M_CS#6 M_CS#5 M_CS#4 RSVD_M_AA15 RSVD_M_AA14 RSVD_M_BA15 RSVD_M_BA14

TP86 TPAD30TP86 TPAD30 TP87 TPAD30TP87 TPAD30

TP44 TPAD30TP44 TPAD30 TP53 TPAD30TP53 TPAD30 TP54 TPAD30TP54 TPAD30 TP49 TPAD30TP49 TPAD30 TP61 TPAD30TP61 TPAD30 TP50 TPAD30TP50 TPAD30 TP55 TPAD30TP55 TPAD30 TP51 TPAD30TP51 TPAD30 TP52 TPAD30TP52 TPAD30

NOT SUPPORT ECC CHECK AMD suggested remove PULL-HI resistor.

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU(2/4)_DDR

Bolsena

558Thursday, March 31, 2005

E

-1

of

-1

A

2D5V_VDDA_S0

2D5V_S0

1 2

0R0603-PAD

12

C239

C239 SC10U10V5ZY

SC10U10V5ZY

SC 0308

R173

R174

1 2

DY

0R3-U

2D5V_CPUR_S0

1 2

0R0805-PAD

12

TC3

ST100U4VBM-U

4 4

2D5V_CPUA_S0

AMD SUGGEST TO USE 2D5V_CPUA_S0

KEMET,NT:5.7, B2 size ST100U4VBM-1 (80.10716.321)

3 3

2D5V_S0

2 2

DY

DBREQJ DBRDY TCK TMS TDI TRST_L TDO

2D5V_S3

CHANGE FROM 1KR3 TO 680R2 FOR AMD CHECK LIST

NC_AG17 NC_AJ18 NC_D18

NC_B19

1 1

NC_C19 NC_D20 NC_C21

Iripple=1.1A,ESR=70mohm

SANYO, NT$:6.1 Iripple=1.1A,ESR=70mohm

3.5/2.8/2.0

77.21071.031

678

RN28

12

C160

C160 SCD1U

SCD1U

R207

1 2

1 2 3 4 5

RN28

123

4 5

680R3F

DY

RN31 SRN680-URN31 SRN680-U

8 7 6

RN33

SRN680-U

A

DY

SRN680-U

AMD SUGGEST TO USE 100 ~ 300UH

Change L270H

R175

SC 0308

2D5V_VDDA_S0

12

LAYOUT: Route trace 50 mils wide and 500 to 750 mils long between these caps.

12

C240

C240 SC4D7U10V5ZY

SC4D7U10V5ZY

1D2V_HT0B_S0

12

R155

R156

680R3F

DY

R153 44D2R2FR153 44D2R2F

1 2

R154 44D2R2FR154 44D2R2F

1 2

AMD suggest voltege from 2D5V_S0 to 2D5V_S3

differentially impedance 100

B

3D3V_S0

12

C210

C210 SC1U10V3KX

SC1U10V3KX

DY

2D5V_S0

DY

LDT_RST#13,18 SB_CPUPWRGD18 LDT_STP#13,18

1 2

1D25V_S3

2D5V_S0

SRN680-U

LDT_RST# SB_CPUPWRGD LDT_STP#

12

C243

C243 SC3300P50V2KX

SC3300P50V2KX

12

C211

C211 SC1000P50V2KX

SC1000P50V2KX

2D5V_S3

R616 820R3R616 820R3

1 2

R605 820R3R605 820R3

1 2

R189 680R3FR189 680R3F R190 680R3FR190 680R3F R606 680R3FR606 680R3F

LAYOUT: Route VDDA trace approx. 50 mils wide (use 2x25 mil traces to exit ball field) and 500 mils long.

12

C241

C241 SCD22U16V3ZY

SCD22U16V3ZY

12

C212

C212 SC1000P50V2KX

SC1000P50V2KX

CPUCLK3

CPUCLK#3

1 2 1 2 1 2

Validation Test Points

NC_C15 NC_AE23 NC_AF23 NC_AF22 NC_AF21

B

LAYOUT: Place close to the CPU.

TP56

TPAD30

TP42

TPAD30

TP39

TPAD30

TP41

TPAD30

TP40

TPAD30

LDT_RST# CLKIN CLKIN# CORE_SENSE VDDIOFB VDDIOFBJ VDDIOSENSE NC_AE24 NC_AF24

C

Iomax=120mA

U73

1

SHDN#

2

GND

3

IN

G913C-U

DY

COREFB41

COREFB#41

C790

C790 SC3900P50V3KX

SC3900P50V3KX

C789

C789 SC3900P50V3KX

SC3900P50V3KX

1 2 1 2

RN32

C

R193

R193 R194

R194

123

12

680R3F

680R3F 680R3F

680R3F

678

TP38

TP38 TP34

TP34 TP35

TP35 TP43

TP43 TP46

TP46 TP45

TP45 TP48

TP48 TP27

TP27 TP26

TP26

4 5

5

SET

4

OUT

L0_REF1 L0_REF0

COREFB COREFB# CORE_SENSE

VDDIOFB VDDIOFBJ VDDIOSENSE

CLKIN

R618

R618 169R2F

169R2F

CLKIN# NC_AJ23 NC_AH23 NC_AE24 NC_AF24

DBRDY NC_C15 TMS

TCK TRST_L TDI

NC_C18 NC_A19

NC_AE23 NC_AF23 NC_AF22 NC_AF21

DY

TPAD30

TPAD30 TPAD30

TPAD30

2D5V_CPUA_S0

2D5V_VDDA_VREF

DY

12

C734

C734 SC1U10V3KX

SC1U10V3KX

DY

AH25

AJ25 AF20

AE18

AJ27

AF27 AE26

A23 A24 B23

AE12 AF12 AE11

AJ21

AH21

AJ23

AH23

AE24 AF24

C16

AG15 AH17

C15 E20

E17 B21 A21

C18 A19 A28

AJ28

AE23 AF23 AF22 AF21

C1

J3

R3

AA2

D3

AG2

B18

AH1

AE21

C20

AG4

C6 AG6 AE9 AG9

12

C733

C733 SC22P50V2JN-1

SC22P50V2JN-1

U81CU81C

VDDA1 VDDA2

RESET_L PWROK LDTSTOP_L

L0_REF1 L0_REF0

COREFB_H COREFB_L CORE_SENSE

VDDIOFB_H VDDIOFB_L VDDIO_SENSE

CLKIN_H CLKIN_L

NC_AJ23 NC_AH23

NC_AE24 NC_AF24

VTT_A VTT_B

DBRDY NC_C15 TMS

TCK TRST_L TDI

NC_C18 NC_A19 KEY1

KEY0 NC_AE23

NC_AF23 NC_AF22 NC_AF21

NC_C1 NC_J3 NC_R3 NC_AA2 NC_D3 NC_AG2 NC_B18 NC_AH1 NC_AE21 NC_C20 NC_AG4 NC_C6 NC_AG6 NC_AE9 NC_AG9

D

12

DY

R604

R1

20KR2F

12

R152

R152 20KR2F

20KR2F

DY

Vout = 1.25*(1+ R1/R2)

R2

THERMTRIP#

THERMDA THERMDC

VID4 VID3 VID2 VID1 VID0

NC_AG18 NC_AH18 NC_AG17

NC_AJ18

A20 A26

A27 AG13

AF14 AG14 AF15 AE15

AG18 AH18 AG17 AJ18

VID4 VID3 VID2 VID1 VID0

NC_AG18 NC_AH18 NC_AG17 NC_AJ18

THERMTRIP_L

THERMDP 23 THERMDN 23

TP37 TPAD30TP37 TPAD30 TP36 TPAD30TP36 TPAD30

VID[4..0] 41

E

LAYOUT: Route FBCLKOUT_H/L

differentially impedance 80

12

R617

R617 80D6R2F

80D6R2F

R191

1 2

DUMMY-R3

2D5V_S3

THERMTRIP#Level shift to SB400

2D5V_S0

12

R192

R192 680R3F

680R3F

THERMTRIP#

Title

Size Document Number Rev

A3

Date: Sheet

Date: Sheet of

CPU(3/4)_Control & Debug

2

1

NS3

Bolsena

3

Q10

Q10 MMBT3904-U1

MMBT3904-U1

R195

1 2

SB 0201

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1KR2

E

2D5V_S0

658Thursday, March 31, 2005

CPU_THERMTRIP# 23

of

-1

FBCLKOUT_H

FBCLKOUT_L

DBREQ_L

NC_D20 NC_C21 NC_D18 NC_C19 NC_B19

TDO

NC_AF18

NC_D22 NC_C22

NC_B13

NC_B7 NC_C3 NC_K1 NC_R2

NC_AA3

NC_F3 NC_C23 NC_AG7

NC_AE22

NC_C24 NC_A25

NC_C9

FBCLKOUT

AH19 AJ19

FBCLKOUTJ

DBREQJ

AE19

NC_D20

D20

NC_C21

C21

NC_D18

D18

NC_C19

C19

NC_B19

B19

TDO

A22

AF18

Connect to VDDIO for AMD suggest.

D22 C22

B13 B7 C3 K1 R2 AA3 F3 C23 AG7 AE22 C24 A25 C9

D

U81EU81E

Y17

VSS

K17

VSS

H17

VSS

F17

VSS

E18

VSS

AJ26

VSS

AE29

VSS

AC16

VSS

AA16

VSS

J16

VSS

G16

VSS

E16

VSS

AH14

4 4

3 3

2 2

1 1

AD15 AB15

K15 E15

D16 AE14 AC14 AA14

G14

AF17 AD13 AB13

Y13 K13 H13

F13 AH12 AC12 AA12

G12

B12 AD11 AB11

Y11

K11

H11

F11 AH10 AC10

W10

U10

R10

N10

G10

B10

AD9

AH8 AC8

AD7

AB7

AH6 AC6

AA6

AH4 AH2

AD2

AB2

C29 AH28

AF28

AC28

W28

R28

VSS VSS VSS VSS VSS VSS VSS VSS VSS

J14

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

L10

VSS

J10

VSS VSS VSS VSS

Y9

VSS

V9

VSS

T9

VSS

P9

VSS

M9

VSS

K9

VSS

H9

VSS

F9

VSS VSS VSS

W8

VSS

U8

VSS

R8

VSS

N8

VSS

L8

VSS

J8

VSS

G8

VSS

B8

VSS VSS VSS

V7

VSS

T7

VSS

P7

VSS

M7

VSS

K7

VSS

H7

VSS

F7

VSS VSS VSS VSS

U6

VSS

R6

VSS

N6

VSS

L6

VSS

J6

VSS

G6

VSS

B6

VSS VSS

B4

VSS VSS VSS VSS

Y2

VSS

V2

VSS

T2

VSS

P2

VSS

M2

VSS

K2

VSS

H2

VSS

F2

VSS VSS VSS VSS VSS VSS VSS

L28

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

A

VCC_CORE_S0 2D5V_S3

N20 L20 J20 AF19 AD19 AB19 Y19 K19 H19 F19 D19 AC18 AA18 G18 B16 AD17 AB17 H15 F15 G28 D28 B28 C27 AH26 AF26 AD26 Y26 T26 M26 H26 D26 B26 C25 B25 AJ24 AG24 AC24 AA24 W24 U24 R24 N24 J24 G24 E24 AG23 AD23 AB23 Y23 V23 T23 P23 K23 H23 F23 D23 AJ22 AH22 AG22 AC22 AA22 AG29 U22 R22 N22 L22 J22 G22 E22 B22 AG21 AD21 Y21 V21 T21 P21 M21 K21 H21 F21 D21 AJ20 AG20 AE20 AC20 AA20 W20 U20 R20 G20 J18 AE16 Y15 B14 J12 AA10 AB9 AA8 Y7 W6 AF2 D2 AG27 AG25 L24 M23 W22 AB21 AH20 B2

A

AC15

H18 B20 E21 H22

H24 F26

V10 G13 K14 Y14

AB14

G15

AA15

H16 K16 Y16

AB16

G17

AA17 AC17 AE17

F18 K18

Y18 AB18 AD18 AG19

E19

G19 AC19 AA19

F20

H20

K20

M20

P20

T20

V20

Y20 AB20 AD20

G21

N21

R21

U21

W21 AA21 AC21

F22 K22 M22 P22 T22 V22

Y22 AB22 AD22

E23

G23

N23

R23

U23

W23 AA23 AC23

B24 D24 F24 K24 M24 P24 T24 V24

Y24 AB24 AD24 AH24 AE25

K26

P26

V26

U81DU81D

L7

VDD VDD VDD VDD VDD VDD

J23

VDD VDD VDD

N7

VDD

L9

VDD VDD VDD VDD VDD VDD VDD

J15

VDD VDD VDD VDD VDD VDD VDD

J17

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

J19

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

J21

VDD

L21

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

L23

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

E4 G4 J4 L4 N4 U4 W4 AA4 AC4 AE4 D5 AF5 F6 H6 K6 M6 P6 T6 V6 Y6 AB6 AD6 D7 G7 J7 AA7 AC7 AF7 F8 H8 AB8 AD8 D9 G9 AC9 AF9 F10 AD10 D11 AF11 F12 AD12 D13 AF13 F14 AD14 F16 AD16 D15 R4

N28 U28 AA28 AE27 R7 U7 W7 K8 M8 P8 T8 V8 Y8 J9 N9 R9 U9 W9 AA9 H10 K10 M10 P10 T10 Y10 AB10 G11 J11 AA11 AC11 H12 K12 Y12 AB12 J13 AA13 AC13 H14 AB26 E28 J28

B

VCC_CORE_S0

B

VCC_CORE_S0

1 2

0.22u x 4

DY

2D5V_S3

12

1D25V_S3

12

0.22u x 2

C

LAYOUT: Place in uPGA socket cavity.

0.22u x 6

12

1 2

SCD22U16V3ZY

DY

12

SCD22U16V3ZY

C274

SCD22U16V3ZY

C269

SCD22U16V3ZY

C794

DY

SCD22U16V3ZY

C339

SCD22U16V3ZY

1D25V_S3

4.7u x 2

12

C791

C316

SCD22U16V3ZY

12

C814

C815

1 2

SC10U10V5ZY

SCD22U16V3ZY

10u x 2

12

SCD22U16V3ZY

SC4D7U10V5ZY

C

12

C319

SCD22U16V3ZY

12

C265

SC4D7U10V5ZY

12

C273

12

C276

12

C792

SC10U10V5ZY

C341

SCD22U16V3ZY

C318

SCD22U16V3ZY

12

C271

SCD22U16V3ZY

LAYOUT: Place on backside of processor.

C816

C813

1 2

SCD22U16V3ZY

DY

12

C268

C340

SCD22U16V3ZY

12

C275

SCD22U16V3ZY

D

10u x 4

12

C315

C818

SCD22U16V3ZY

2D5V_S3

12

C320

10u x 1 4.7u x 6

SC10U10V5ZY

12

C313

C272

SC4D7U10V5ZY

SC10U10V5ZY

12

C314

SC4D7U10V5ZY

C817

SC10U10V5ZY

12

C365

SC4D7U10V5ZY

D

C793

SC10U10V5ZY

12

C317

SC4D7U10V5ZY

E

12

C367

C366

SC4D7U10V5ZY

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

CPU(4/4)_Power

Bolsena

758Thursday, March 31, 2005

E

-1

of

-1

A

M_AA0 M_AA1 M_AA2 M_AA3 M_AA4 M_AA5 M_AA6 M_AA7 M_AA8 M_AA9 M_AA10 M_AA11

4 4

3 3

2 2

1 1

M_ARAS#5,9 M_ACAS#5,9 M_AWE#5,9

VREF_DDR_MEM VREF_DDR_MEM

Layout trace 20 mil Layout trace 20 mil

M_AA12 M_ABS#0

M_ABS#1 M_DATA_R_0

M_DATA_R_1 M_DATA_R_2 M_DATA_R_3 M_DATA_R_4 M_DATA_R_5 M_DATA_R_6 M_DATA_R_7 M_DATA_R_8 M_DATA_R_9 M_DATA_R_10 M_DATA_R_11 M_DATA_R_12 M_DATA_R_13 M_DATA_R_14 M_DATA_R_15 M_DATA_R_16 M_DATA_R_17 M_DATA_R_18 M_DATA_R_19 M_DATA_R_20 M_DATA_R_21 M_DATA_R_22 M_DATA_R_23 M_DATA_R_24 M_DATA_R_25 M_DATA_R_26 M_DATA_R_27 M_DATA_R_28 M_DATA_R_29 M_DATA_R_30 M_DATA_R_31 M_DATA_R_32 M_DATA_R_33 M_DATA_R_34 M_DATA_R_35 M_DATA_R_36 M_DATA_R_37 M_DATA_R_38 M_DATA_R_39 M_DATA_R_40 M_DATA_R_41 M_DATA_R_42 M_DATA_R_43 M_DATA_R_44 M_DATA_R_45 M_DATA_R_46 M_DATA_R_47 M_DATA_R_48 M_DATA_R_49 M_DATA_R_50 M_DATA_R_51 M_DATA_R_52 M_DATA_R_53 M_DATA_R_54 M_DATA_R_55 M_DATA_R_56 M_DATA_R_57 M_DATA_R_58 M_DATA_R_59 M_DATA_R_60 M_DATA_R_61 M_DATA_R_62 M_DATA_R_63

12

C458

C458 SCD1U

SCD1U

A

3D3V_S0

C456

C456 SCD1U

SCD1U

TP62

TP62 TPAD30

TPAD30

DDR1

112

A0

111

A1

110

A2

109

A3

108

A4

107

A5

106

A6

105

A7

102

A8

101

A9

115

A10 / AP

100

A11

99

A12

117

BA0

116

BA1

5

DQ0

7

DQ1

13

DQ2

17

DQ3

6

DQ4

8

DQ5

14

DQ6

18

DQ7

19

DQ8

23

DQ9

29

DQ10

31

DQ11

20

DQ12

24

DQ13

30

DQ14

32

DQ15

41

DQ16

43

DQ17

49

DQ18

53

DQ19

42

DQ20

44

DQ21

50

DQ22

54

DQ23

55

DQ24

59

DQ25

65

DQ26

67

DQ27

56

DQ28

60

DQ29

66

DQ30

68

DQ31

127

DQ32

129

DQ33

135

DQ34

139

DQ35

128

DQ36

130

DQ37

136

DQ38

140

DQ39

141

DQ40

145

DQ41

151

DQ42

153

DQ43

142

DQ44

146

DQ45

152

DQ46

154

DQ47

163

DQ48

165

DQ49

171

DQ50

175

DQ51

164

DQ52

166

DQ53

172

DQ54

176

DQ55

177

DQ56

181

DQ57

187

DQ58

189

DQ59

178

DQ60

182

DQ61

188

DQ62

190

DQ63

71

CB0

73

CB1

79

CB2

83

CB3

72

CB4

74

CB5

80

CB6

84

CB7

85

NC#85

86

NC#86/(RESET#)

97

NC#97/A13

98

NC#98/BA2

123

NC#123

124

NC#124

200

NC#200

118

/RAS

120

/CAS

119

/WE

1

VREF

2

VREF

197

VDDSPD

199

VDDID

201

GND

/CS0 /CS1

CKE0 CKE1

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8

CK0

/CK0

CK1

/CK1

CK2

/CK2

SCL SDA

SA0 SA1 SA2

VDD VDD VDD VDD VDD VDD VDD

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS

REVERSE TYPE 5.2MM

VSS

VSS GND

121 122

96 95

11 25 47 61 133 147 169 183 77

12 26 48 62 134 148 170 184 78

35 37 160 158 89 91

195 193

194 196 198

9 10 21 22 33 34 36 45 46 57 58 69 70 81 82 92 93 94 113 114 131 132 143 144 155 156 157 167 168 179 180 191 192

3 4 15 16 27 28 38 39 40 51 52 63 64 75 76 87 88 90 103 104 125 126 137 138 149 150 159 161 162 173 174 185 186

202

B

M_CS#0 5,9

M_CKE#0

M_DQS_R0 M_DQS_R1 M_DQS_R2 M_DQS_R3 M_DQS_R4 M_DQS_R5 M_DQS_R6 M_DQS_R7

M_ADM_R0 M_ADM_R1 M_ADM_R2 M_ADM_R3

M_ADM_R5 M_ADM_R6 M_ADM_R7

DDR_CLK0 DDR_CLK#0

SMBC_SB SMBD_SB

NOT SUPPORT ECC CHECK AMD suggested pull-low

1ST 62.10017.701 - 2ND 62.10017.201

Part Number = 62.10017.201

DDR-SODIMM-R-U2

ME : 62.10017.201 2nd :62.10017.701

B

M_CS#1 5,9 M_CKE#0 5,9 M_CKE#1 5,9

M_ADM#0 M_ADM#1 M_ADM#2 M_ADM#3 M_ADM#4 M_ADM#5 M_ADM#6 M_ADM#7

M_CLK5 5 M_CLK#5 5 M_CLK7 5 M_CLK#7 5

2D5V_S3

C

DDR2

M_BA0 M_BA1 M_BA2 M_BA3 M_BA4 M_BA5 M_BA6 M_BA7 M_BA8 M_BA9 M_BA10 M_BA11 M_BA12

M_BBS#0 M_BBS#1

M_DATA_R_0 M_DATA_R_1 M_DATA_R_2 M_DATA_R_3 M_DATA_R_4 M_DATA_R_5 M_DATA_R_6 M_DATA_R_7 M_DATA_R_8 M_DATA_R_9 M_DATA_R_10 M_DATA_R_11 M_DATA_R_12 M_DATA_R_13 M_DATA_R_14 M_DATA_R_15 M_DATA_R_16 M_DATA_R_17 M_DATA_R_18 M_DATA_R_19 M_DATA_R_20 M_DATA_R_21 M_DATA_R_22 M_DATA_R_23 M_DATA_R_24 M_DATA_R_25 M_DATA_R_26 M_DATA_R_27 M_DATA_R_28 M_DATA_R_29 M_DATA_R_30 M_DATA_R_31 M_DATA_R_32 M_DATA_R_33 M_DATA_R_34 M_DATA_R_35 M_DATA_R_36 M_DATA_R_37 M_DATA_R_38 M_DATA_R_39 M_DATA_R_40 M_DATA_R_41 M_DATA_R_42 M_DATA_R_43 M_DATA_R_44 M_DATA_R_45 M_DATA_R_46 M_DATA_R_47 M_DATA_R_48 M_DATA_R_49 M_DATA_R_50 M_DATA_R_51 M_DATA_R_52 M_DATA_R_53 M_DATA_R_54 M_DATA_R_55 M_DATA_R_56 M_DATA_R_57 M_DATA_R_58 M_DATA_R_59 M_DATA_R_60 M_DATA_R_61 M_DATA_R_62 M_DATA_R_63

M_BA13M_AA13

M_BRAS#5,9 M_BCAS#5,9 M_BWE#5,9

12

3D3V_S0

C497

C498

SCD1U

TP63

TP63 TPAD30

TPAD30

DDR2

112

A0

111

A1

110

A2

109

A3

108

A4

107

A5

106

A6

105

A7

102

A8

101

A9

115

A10 / AP

100

A11

99

A12

117

BA0

116

BA1

5

DQ0

7

DQ1

13

DQ2

17

DQ3

6

DQ4

8

DQ5

14

DQ6

18

DQ7

19

DQ8

23

DQ9

29

DQ10

31

DQ11

20

DQ12

24

DQ13

30

DQ14

32

DQ15

41

DQ16

43

DQ17

49

DQ18

53

DQ19

42

DQ20

44

DQ21

50

DQ22

54

DQ23

55

DQ24

59

DQ25

65

DQ26

67

DQ27

56

DQ28

60

DQ29

66

DQ30

68

DQ31

127

DQ32

129

DQ33

135

DQ34

139

DQ35

128

DQ36

130

DQ37

136

DQ38

140

DQ39

141

DQ40

145

DQ41

151

DQ42

153

DQ43

142

DQ44

146

DQ45

152

DQ46

154

DQ47

163

DQ48

165

DQ49

171

DQ50

175

DQ51

164

DQ52

166

DQ53

172

DQ54

176

DQ55

177

DQ56

181

DQ57

187

DQ58

189

DQ59

178

DQ60

182

DQ61

188

DQ62

190

DQ63

71

CB0

73

CB1

79

CB2

83

CB3

72

CB4

74

CB5

80

CB6

84

CB7

85

NC#85

86

NC#86/(RESET#)

97

NC#97/A13

98

NC#98/BA2

123

NC#123

124

NC#124

200

NC#200

118

/RAS

120

/CAS

119

/WE

1

VREF

2

VREF

197

VDDSPD

199

VDDID

201

GND

SKT-SODIMM2006U1

C

121

/CS0

122

/CS1

96

CKE0

95

CKE1

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8

CK0

/CK0

CK1

/CK1

CK2

/CK2

SCL SDA

SA0 SA1 SA2

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

REVERSE TYPE 9.2MM

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

GND

M_DQS_R0

11

M_DQS_R1

25

M_DQS_R2

47

M_DQS_R3

61

M_DQS_R4

133

M_DQS_R5

147

M_DQS_R6

169

M_DQS_R7

183 77

M_ADM_R0

12

M_ADM_R1

26

M_ADM_R2

48

M_ADM_R3

62

M_ADM_R4M_ADM_R4

134

M_ADM_R5

148

M_ADM_R6

170

M_ADM_R7

184 78

35 37 160 158

DDR_CLK1

89

DDR_CLK#1

91 195

193 194

196 198

9 10 21 22 33 34 36 45 46 57 58 69 70 81 82 92 93 94 113 114 131 132 143 144 155 156 157 167 168 179 180 191 192

3 4 15 16 27 28 38 39 40 51 52 63 64 75 76 87 88 90 103 104 125 126 137 138 149 150 159 161 162 173 174 185 186

202

DM_SA0

2D5V_S3

62.10017.391

ME : 62.10017.391

D

M_CS#2 5,9 M_CS#3 5,9

! NOT THIS LIBRARY

M_ADM#0 M_ADM#1 M_ADM#2 M_ADM#3 M_ADM#4 M_ADM#5 M_ADM#6 M_ADM#7

M_CLK4 5 M_CLK#4 5 M_CLK6 5 M_CLK#6 5

SMBC_SB 3,21 SMBD_SB 3,21

1 2

R312

R312 4K7R2

4K7R2

DDR1(Reverse 5.2mm)

DDR2(Reverse 9.2mm)

D

E

M_ADM_R[7..0] 9 M_DATA_R_[63..0] 9 M_DQS_R[7..0] 9

M_AA[13..0] 5,9 M_ABS#[1..0] 5,9 M_BA[13..0] 5,9 M_BBS#[1..0] 5,9

3D3V_S0

2D5V_S3

RN62

DDR_CLK#1 DDR_CLK#0 DDR_CLK1 DDR_CLK0

8 7 6

RN62

SRN10K-2

1 2 3 45

SB 0203

AMD CPU

MD63

Title

Size Document Number Rev

A3

Date: Sheet

DDR SO-DIMM SKT

SMA10

SMA11

SMA0 SMA12

SMA14

Pin 199

Pin 200 Pin 2

Pin 199 Pin 1

Pin 200 Pin 2

(Bottom view)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena

E

Pin 1

MD0

858Thursday, March 31, 2005

-1

of

-1

A

SERIES DAMPING PARALLEL TERMINATION

PLACE RNs CLOSE TO FIRST DIMM, < 0.75" STRICT EQUAL LENGTH LIMITATION WITH DQS, CB PINS

SRN10J-3

M_DATA4 M_ADM0

M_DATA6 M_DATA7 M_DATA13 M_DATA12

4 4

M_ADM1

M_DATA1 M_DATA0 M_DQS0 M_DATA2 M_DATA3 M_DATA8 M_DATA9 M_DQS1

M_DATA14 M_DATA_R_14 M_DATA15 M_DATA21 M_DATA20 M_ADM2 M_DATA23 M_DATA_R_23 M_DATA22 M_DATA28 M_DATA_R_28

3 3

M_DATA11 M_DATA10 M_DATA17 M_DATA16 M_DQS2 M_DQS_R2 M_DATA19 M_DATA_R_19 M_DATA18

M_DATA31 M_DATA_R_31

M_DATA24 M_DATA_R_24 M_DATA_R_27 M_DQS3 M_DQS_R3 M_DATA26 M_DATA_R_26 M_DATA27 M_DATA_R_27

2 2

SRN10J-3

8 9 7 6 5 4 3 2 1

RN49

RN49 SRN10J-3

SRN10J-3

8 9 7 6 5 4 3 2 1

RN38

RN38 SRN10J-3

SRN10J-3

8 9 7 6 5 4 3 2 1

RN50

RN50 SRN10J-3

SRN10J-3

8 9 7 6 5 4 3 2 1

RN39

RN51

4 5 3 2 1

RN40

SRN10-1

10 11 12 13 14 15 16

SRN10-1

6 7 8

M_DATA_R_4 M_DATA_R_5M_DATA5 M_ADM_R0 M_DATA_R_6 M_DATA_R_7 M_DATA_R_13 M_DATA_R_12 M_ADM_R1

M_DATA_R_1 M_DATA_R_0 M_DQS_R0 M_DATA_R_2 M_DATA_R_3 M_DATA_R_8 M_DATA_R_9 M_DQS_R1

M_DATA_R_15 M_DATA_R_21 M_DATA_R_20 M_ADM_R2

M_DATA_R_22

M_DATA_R_11 M_DATA_R_10 M_DATA_R_17 M_DATA_R_16

M_DATA_R_18 M_DATA_R_25M_DATA25

M_DATA_R_29M_DATA29 M_ADM_R3M_ADM3

M_DATA_R_30M_DATA30

M_ADM4 M_ADM_R4 M_DATA39 M_DATA_R_39

M_DATA33 M_DATA_R_33 M_DATA34 M_DATA_R_34

M_DATA35 M_DATA41 M_DATA40 M_DQS5 M_DATA42 M_DATA43 M_DATA49 M_DATA48

M_DATA38 M_DATA45 M_DATA44 M_ADM5 M_DATA47 M_DATA46 M_DATA53 M_DATA52

M_DQS6 M_DATA50 M_DATA51 M_DATA56 M_DATA57 M_DQS7 M_DATA58 M_DATA59

M_ADM6 M_DATA54 M_DATA55 M_DATA61 M_DATA60 M_ADM7 M_DATA62 M_DATA63

4 5 3 2 1

RN41

8 9 7 6 5 4 3 2 1

SRN10-1

RN52

SRN10-1

SRN10-1 SRN10J-3

SRN10J-3

RN42

RN42 SRN10J-3

SRN10J-3

RN53

RN53 SRN10J-3

SRN10J-3

RN43

RN43 SRN10J-3

SRN10J-3

RN54

B

6 7 8

10 11 12 13 14 15 16

M_DATA_R_37M_DATA37 M_DATA_R_36M_DATA36

M_DATA_R_32M_DATA32 M_DQS_R4M_DQS4

M_DATA_R_35 M_DATA_R_41 M_DATA_R_40 M_DQS_R5 M_DATA_R_42 M_DATA_R_43 M_DATA_R_49 M_DATA_R_48

M_DATA_R_38

M_DATA_R_45

M_DATA_R_44 M_ADM_R5 M_DATA_R_47 M_DATA_R_46 M_DATA_R_53 M_DATA_R_52

M_DQS_R6 M_DATA_R_50 M_DATA_R_51 M_DATA_R_56 M_DATA_R_57 M_DQS_R7 M_DATA_R_58 M_DATA_R_59

M_ADM_R6 M_DATA_R_54 M_DATA_R_55 M_DATA_R_61 M_DATA_R_60 M_ADM_R7 M_DATA_R_62 M_DATA_R_63

C

PULL HIGH STUBS < 0.8", PLACE RPs CLOSE TO SECOND DM ( DM2 )

SRN68J-1

M_ADM_R1 M_DATA_R_13 M_DATA_R_12 M_DATA_R_7 M_DATA_R_6 M_ADM_R0 M_DATA_R_5 M_DATA_R_4

M_DATA_R_1 M_DATA_R_0 M_DQS_R0 M_DATA_R_2 M_DATA_R_3 M_DATA_R_8 M_DATA_R_9 M_DQS_R1

M_DATA_R_28 M_DATA_R_23 M_DATA_R_22 M_ADM_R2 M_ADM_R5 M_DATA_R_21 M_DATA_R_20 M_DATA_R_15 M_DATA_R_14

M_DATA_R_11 M_DATA_R_10 M_DATA_R_16 M_DATA_R_17 M_DQS_R2 M_DATA_R_19 M_DATA_R_18 M_DATA_R_24

M_DATA_R_26 M_DQS_R3 M_DATA_R_25

M_DATA_R_31 M_DATA_R_30 M_ADM_R3 M_DATA_R_29

SRN68J-1

8 9 7 6 5 4 3 2 1

RN113

SRN68J-1

8 9 7 6 5 4 3 2 1

RN59

RN59 SRN68J-1

SRN68J-1

8 9 7 6 5 4 3 2 1

RN114

RN114 SRN68J-1

SRN68J-1

8 9 7 6 5 4 3 2 1

RN60

RN60 RN61

RN61

1 2 3 4 5

4 5 3 2 1

RN115

1D25V_S3 1D25V_S3

4 5 10 11 12 13 14 15 16

10 11 12 13 14 15 16

SRN68-1

8 7 6

6 7 8

SRN68-1

3

2

1

RN66

4 5

3

2

1

RN110

SRN68J-1

8 9 7 6 5 4 3 2 1

RN68

RN68 SRN68J-1

SRN68J-1

8 9 7 6 5 4 3 2 1

RN111

RN111 SRN68J-1

SRN68J-1

8 9 7 6 5 4 3 2 1

RN69

RN69 SRN68J-1

SRN68J-1

8 9 7 6 5 4 3 2 1

RN112

NO EQUAL LENGTH LIMITATION

M_DATA_R_32 M_DATA_R_33

6

M_DQS_R4

7

M_DATA_R_35

8

SRN68-1

M_DATA_R_36 M_DATA_R_37

6

M_ADM_R4

7

M_DATA_R_38

8

SRN68-1

M_DATA_R_48 M_DATA_R_49

10

M_DATA_R_43

11

M_DATA_R_42

12

M_DQS_R5

13

M_DATA_R_41

14

M_DATA_R_40

15

M_DATA_R_34

16

M_DATA_R_39 M_DATA_R_44

10

M_DATA_R_45

11 12

M_DATA_R_46

13

M_DATA_R_47

14

M_DATA_R_52

15

M_DATA_R_53

16

M_DATA_R_59 M_DATA_R_58

10

M_DQS_R7

11

M_DATA_R_57

12

M_DATA_R_56

13

M_DATA_R_51

14

M_DATA_R_50

15

M_DQS_R6

16

M_ADM_R6 M_DATA_R_54

10

M_DATA_R_55

11

M_DATA_R_60

12

M_DATA_R_61

13

M_ADM_R7

14

M_DATA_R_62

15

M_DATA_R_63

16

D

M_CKE#0 M_AA12

M_BA12 M_BA5

M_AA11 M_AA9 M_AA7 M_AA5 M_AA4 M_AA8 M_AA6 M_AA3

M_AWE# M_ABS#0

M_BA3 M_BA7

M_AA1 M_AA10 M_AA2 M_AA0 M_ABS#1 M_ARAS# M_CS#2 M_BA13

M_BA9 M_BA6 M_BA10 M_BA1 M_BA2 M_BA0 M_BBS#0 M_BWE#

M_BA4 M_BA8 M_BA11 M_CKE#1

M_AA13 M_CS#0 M_CS#1 M_ACAS#

M_CS#3 M_BCAS# M_BRAS# M_BBS#1

SRN47J

1 4 2

RN57

RN57 SRN47J

SRN47J

1 4 2

RN63

RN63 SRN47J-1-U

SRN47J-1-U

8 9 7 6 5 4 3 2 1

RN64

4 5 3 2 1

RN67 SRN47JRN67 SRN47J

1 4 2

RN70

1 4 2

SRN47J-1-U

8 9 7 6 5 4 3 2 1

RN65

RN65 SRN47J-1-U

SRN47J-1-U

8 9 7 6 5 4 3 2 1

RN71

SRN47-1

4 5 3 2 1

RN108

SRN47-1

4 5 3 2 1

RN58

SRN47-1

RN109

6 7 8

3

10 11 12 13 14 15 16

3

SRN47J

3

10 11 12 13 14 15 16

E

M_ADM_R[7..0] 8

M_ADM[7..0] 5 M_DATA[63..0] 5 M_DATA_R_[63..0] 8 M_DQS[7..0] 5 M_DQS_R[7..0] 8

M_AA[13..0] 5,8

M_ABS#[1..0] 5,8

M_BA[13..0] 5,8

M_BBS#[1..0] 5,8

M_AWE# 5,8

M_ACAS# 5,8

6 7 8

M_CKE#05,8

M_CKE#15,8

M_ARAS# 5,8

M_BWE# 5,8

M_BCAS# 5,8

M_BRAS# 5,8

M_CS#0 5,8

M_CS#1 5,8

M_CS#2 5,8

M_CS#3 5,8

M_CKE#0 M_CKE#1

1 1

05/10 Remove the damping resistor for AMD suggest.

A

B

C

D

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Date: Sheet of

DDR DAMPING & TERMINATION

Bolsena

958Thursday, March 31, 2005

of

E

of

-1

A

B

C

D

E

4 4

2D5V_S3

1D25V_S3

3 3

2D5V_S3

1D25V_S3

2 2

12

C873

C873 SCD1U

SCD1U

DY

12

C868

C868 SCD1U

SCD1U

DY

12

C879

C879 SCD1U

SCD1U

DY

12

C882

C882 SCD1U

SCD1U

DY

12

C875

C877

SCD1U

12

C870

C872

SCD1U

12

C881

C881 SCD1U

SCD1U

C886

C886 SCD1U

SCD1U

C883

C883 SCD1U

SCD1U

12

C888

C888 SCD1U

SCD1U

LAYOUT:Place altemating caps to GND and 2D5_S3

12

C867

C867 SCD1U

SCD1U

DY

12

C874

C874 SCD1U

SCD1U

DY

12

C885

C885 SCD1U

SCD1U

DY

12

C890

C890 SCD1U

SCD1U

DY

12

C869

C869 SCD1U

SCD1U

12

C876

C876 SCD1U

SCD1U

12

C887

C887 SCD1U

SCD1U

12

C880

C880 SCD1U

SCD1U

12

C871

C363

SCD1U

DY

12

C878

C878 SCD1U

SCD1U

C889

C889 SCD1U

SCD1U

C884

C884 SCD1U

SCD1U

C496

C496 SCD1U

SCD1U

DY

12

C503

C503 SCD1U

SCD1U

DY

12

C504

C504 SCD1U

SCD1U

DY

12

C364

C364 SCD1U

SCD1U

C436

C436 SCD1U

SCD1U

C368

C368 SCD1U

SCD1U

C370

C370 SCD1U

SCD1U

C388

C388 SCD1U

SCD1U

12

C437

C437 SCD1U

SCD1U

12

C409

C409 SCD1U

SCD1U

12

C411

C411 SCD1U

SCD1U

12

C407

C407 SCD1U

SCD1U

DY

12

C405

C405 SCD1U

SCD1U

DY

12

C321

C321 SCD1U

SCD1U

DY

12

C322

C322 SCD1U

SCD1U

DY

12

C406

C406 SCD1U

SCD1U

C404

C404 SCD1U

SCD1U

C342

C342 SCD1U

SCD1U

C343

C343 SCD1U

SCD1U

C438

C438 SCD1U

SCD1U

12

C386

C386 SCD1U

SCD1U

12

C369

C369 SCD1U

SCD1U

12

C371

C371 SCD1U

SCD1U

12

C338

C454

SCD1U

DY

12

C385

C361

SCD1U

DY

12

C389

C389 SCD1U

SCD1U

C390

C390 SCD1U

SCD1U

C408

C408 SCD1U

SCD1U

DY

12

C412

C412 SCD1U

SCD1U

DY

12

C387

C387 SCD1U

SCD1U

12

C362

C362 SCD1U

SCD1U

12

C410

C410 SCD1U

SCD1U

12

C449

C449 SCD1U

SCD1U

12

C310

C455

SCD1U

DY

12

C337

C308

SCD1U

DY

12

C447

C447 SCD1U

SCD1U

C448

C448 SCD1U

SCD1U

C466

C466 SCD1U

SCD1U

DY

12

C467

C467 SCD1U

SCD1U

DY

1D25V_S3

12

DY

C460

C460 SCD1U

SCD1U

12

C459

C459 SCD1U

SCD1U

DY

C462

C462 SCD1U

SCD1U

12

C463

C463 SCD1U

SCD1U

DY

C457

C457 SCD1U

SCD1U

12

C502

C465

SCD1U

DY

LAYOUT:Place close to Power Pin of DDR socket.

LAYOUT:Place at end of the DIMMs

1D25V_S3

12

DY

TC17

TC17 ST100U4VBM-U

ST100U4VBM-U

12

TC26

SE100U10VM

79.10711.4C1

SB

12

C892

C892 SC10U10V5ZY

SC10U10V5ZY

12

C865

C865 SC10U10V5ZY

SC10U10V5ZY

12

C891

C891 SC10U10V5ZY

SC10U10V5ZY

12

C866

C866 SC10U10V5ZY

SC10U10V5ZY

2D5V_S3 2D5V_S3

C445

1 2

SCD22U16V3ZY

SCD22U16V3ZY C443

C443

1 2

SCD22U16V3ZY

SCD22U16V3ZY C446

C446

1 2

DY

SCD22U16V3ZY

DY

C444

C444 SCD22U16V3ZY

SCD22U16V3ZY C442

C442 SCD22U16V3ZY

SCD22U16V3ZY

1 2

C464

C464 SCD22U16V3ZY

SCD22U16V3ZY C501

C501 SCD22U16V3ZY

SCD22U16V3ZY

DY

C500

C500 SCD22U16V3ZY

SCD22U16V3ZY

DY

C461

C461 SCD22U16V3ZY

SCD22U16V3ZY C499

C499 SCD22U16V3ZY

SCD22U16V3ZY

0.22u x 10

1 1

A

B

C

D

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Date: Sheet of

DDR DECOUPLING

Bolsena

E

10 58Thursday, March 31, 2005

of

-1

A

4 4

B

C

D

E

CLAW HAMMER TO NB NB TO CLAW HAMMER

CPUCADOUT[15..0]4 CPUCADOUTJ[15..0]4

3 3

1D2V_S0

12

2 2

AROUND NB

C221

C221 SCD1U16V

SCD1U16V

DY

12

C222

C222 SCD1U16V

SCD1U16V

1D2V_S0

CPUHTTCLKOUT14 CPUHTTCLKOUTJ14

CPUHTTCLKOUT04 CPUHTTCLKOUTJ04

CPUHTTCTLOUT04 CPUHTTCTLOUTJ04

R162 49D9R2FR162 49D9R2F

1 2

R161 49D9R2FR161 49D9R2F

1 2

CPUCADOUT15 CPUCADOUTJ15 CPUCADOUT14 CPUCADOUTJ14 CPUCADOUT13 CPUCADOUTJ13 CPUCADOUT12 CPUCADOUTJ12 CPUCADOUT11 CPUCADOUTJ11 CPUCADOUT10 CPUCADOUTJ10 CPUCADOUT9 CPUCADOUTJ9 CPUCADOUT8 CPUCADOUTJ8

CPUCADOUT7 CPUCADOUTJ7 CPUCADOUT6 CPUCADOUTJ6 CPUCADOUT5 CPUCADOUTJ5 CPUCADOUT4 CPUCADOUTJ4 CPUCADOUT3 CPUCADOUTJ3 CPUCADOUT2 CPUCADOUTJ2 CPUCADOUT1 CPUCADOUTJ1 CPUCADOUT0 CPUCADOUTJ0

CPUHTTCLKOUT1 CPUHTTCLKOUTJ1

CPUHTTCLKOUT0 CPUHTTCLKOUTJ0

CPUHTTCTLOUT0 CPUHTTCTLOUTJ0

HT_RXCALN HT_RXCALP

W25

W24 AA25 AA24 AB26 AA26 AC25 AC24 AD26 AC26

W30

AB29 AA29 AC29 AC28

W26

W29

W28

T26 R26 U25 U24 V26 U26

R29 R28 T30 R30 T28 T29 V29 U29 Y30

Y28 Y29

Y26

P29 N29

D27 E27

U80A

HT_RXCAD15P HT_RXCAD15N HT_RXCAD14P HT_RXCAD14N HT_RXCAD13P HT_RXCAD13N HT_RXCAD12P HT_RXCAD12N HT_RXCAD11P HT_RXCAD11N HT_RXCAD10P HT_RXCAD10N HT_RXCAD9P HT_RXCAD9N HT_RXCAD8P HT_RXCAD8N

HT_RXCAD7P HT_RXCAD7N HT_RXCAD6P HT_RXCAD6N HT_RXCAD5P HT_RXCAD5N HT_RXCAD4P HT_RXCAD4N HT_RXCAD3P HT_RXCAD3N HT_RXCAD2P HT_RXCAD2N HT_RXCAD1P HT_RXCAD1N HT_RXCAD0P HT_RXCAD0N

HT_RXCLK1P HT_RXCLK1N

HT_RXCLK0P HT_RXCLK0N

HT_RXCTLP HT_RXCTLN

HT_RXCALN HT_RXCALP

PART 1OF6

HT_TXCAD15P HT_TXCAD15N HT_TXCAD14P HT_TXCAD14N HT_TXCAD13P HT_TXCAD13N HT_TXCAD12P HT_TXCAD12N HT_TXCAD11P HT_TXCAD11N HT_TXCAD10P HT_TXCAD10N

HT_TXCAD9P HT_TXCAD9N HT_TXCAD8P HT_TXCAD8N

HT_TXCAD7P HT_TXCAD7N HT_TXCAD6P HT_TXCAD6N HT_TXCAD5P HT_TXCAD5N HT_TXCAD4P HT_TXCAD4N HT_TXCAD3P HT_TXCAD3N HT_TXCAD2P HT_TXCAD2N HT_TXCAD1P HT_TXCAD1N HT_TXCAD0P HT_TXCAD0N

HT_TXCLK1P HT_TXCLK1N

HT_TXCLK0P HT_TXCLK0N

HT_TXCTLP

HT_TXCTLN HT_TXCALP

HT_TXCALN

R24 R25 N26 P26 N24 N25 L26 M26 J26 K26 J24 J25 G26 H26 G24 G25

L30 M30 L28 L29 J29 K29 H30 H29 E29 E28 D30 E30 D28 D29 B29 C29

L24 L25

F29 G29

M29 M28

B28 A28

NB0CADOUT15 NB0CADOUTJ15 NB0CADOUT14 NB0CADOUTJ14 NB0CADOUT13 NB0CADOUTJ13 NB0CADOUT12 NB0CADOUTJ12 NB0CADOUT11 NB0CADOUTJ11 NB0CADOUT10 NB0CADOUTJ10 NB0CADOUT9 NB0CADOUTJ9 NB0CADOUT8 NB0CADOUTJ8

NB0CADOUT7 NB0CADOUTJ7 NB0CADOUT6 NB0CADOUTJ6 NB0CADOUT5 NB0CADOUTJ5 NB0CADOUT4 NB0CADOUTJ4 NB0CADOUT3 NB0CADOUTJ3 NB0CADOUT2 NB0CADOUTJ2 NB0CADOUT1 NB0CADOUTJ1 NB0CADOUT0 NB0CADOUTJ0

NB0HTTCLKOUT1 NB0HTTCLKOUTJ1

NB0HTTCLKOUT0 NB0HTTCLKOUTJ0

NB0HTTCTLOUT NB0HTTCTLOUTJ

HT_TXCALP HT_TXCALN

R583

1 2

NB0CADOUT[15..0] 4 NB0CADOUTJ[15..0] 4

NB0HTTCLKOUT1 4 NB0HTTCLKOUTJ1 4

NB0HTTCLKOUT0 4 NB0HTTCLKOUTJ0 4

NB0HTTCTLOUT 4 NB0HTTCTLOUTJ 4

100R2F

CHANGE TO 71.RS48M.B0U (VER A22)

HYPER TRANSPORT CPU I/F

1 1

A

B

C

CHANGE TO 71.RS48M.B0U (VER A22)

D

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

ATI-RS480M (1 of 4) HT

Bolsena

11 58Thursday, March 31, 2005

E

of

-1

A

4 4

3 3

IDCKP_1

R634

1 2

IDCKP15

IDCKN15

R636

1 2

33R2

IDCKN_1

Dummy when 'USE DVO'

R217

1 2

0R0603-PAD

SC 0308

2 2

1D8V_S0

12

R208

R208 1KR2F

1KR2F

MEM_VREF

12

1 1

R214

R214 1KR2F

1KR2F

C823 SCD47U16V3ZYC823 SCD47U16V3ZY

MEM_CAP1

1 2

MEM_CAP2

1 2

C832 SCD47U16V3ZYC832 SCD47U16V3ZY

RS480_MEM_VMODE

MEM_VREF MPVDD_PLL

12

C324

C324 SC1U10V3KX

SC1U10V3KX

NO DVO: MEM_COMPP = NC MEM_COMPN = NC MEM_CAP1 = 470nF MEM_CAP2 = 470nF MEM_VMODE = GND (IF VDD_MEM = 2.5V) MEM_VREF = VDD_MEM / 2

A

U80C

AF17

MEM_A0

AK17 AH16

AF16 AJ22

AJ21 AH20 AH21 AK19 AH19

AJ17 AG16 AG17 AH17

AJ18 AG26

AJ29 AE21 AH24 AH12 AG13

AH8 AE8

AF25 AH30 AG20

AJ25 AH13

AF14

AG8

AG25 AH29

AF21 AK25

AJ12

AF13

AK7 AF9

AE17 AH18 AE18

AJ19

AF18 AK16

AJ16

AE28

AJ20

AK20

AJ15

AJ14

AJ7

AJ4

PART 3 OF 6

MEM_A1 MEM_A2 MEM_A3 MEM_A4 MEM_A5 MEM_A6 MEM_A7 MEM_A8 MEM_A9 MEM_A10 MEM_A11 MEM_A12 MEM_A13 MEM_A14

MEM_DM0 MEM_DM1 MEM_DM2 MEM_DM3 MEM_DM4 MEM_DM5 MEM_DM6 MEM_DM7

MEM_DQS0P MEM_DQS1P MEM_DQS2P MEM_DQS3P MEM_DQS4P MEM_DQS5P MEM_DQS6P MEM_DQS7P

MEM_DQS0N MEM_DQS1N MEM_DQS2N MEM_DQS3N MEM_DQS4N MEM_DQS5N MEM_DQS6N MEM_DQS7N

MEM_RAS# MEM_CAS# MEM_WE# MEM_CS# MEM_CKE

MEM_CKP MEM_CKN

MEM_CAP1 MEM_CAP2

MEM_VMODE

MEM_VREF MPVDD

MPVSS

CHANGE TO 71.RS48M.B0U (VER A22)

B

AF28

MEM_DQ0

AF27

MEM_DQ1

AG28

MEM_DQ2

AF26

MEM_DQ3

AE25

MEM_DQ4

AE24

MEM_DQ5

AF24

MEM_DQ6

AG23

MEM_DQ7

AE29

MEM_DQ8

AF29

MEM_DQ9 MEM_DQ10 MEM_DQ11 MEM_DQ12 MEM_DQ13 MEM_DQ14 MEM_DQ15 MEM_DQ16 MEM_DQ17 MEM_DQ18 MEM_DQ19 MEM_DQ20 MEM_DQ21 MEM_DQ22 MEM_DQ23 MEM_DQ24 MEM_DQ25 MEM_DQ26 MEM_DQ27 MEM_DQ28 MEM_DQ29 MEM_DQ30 MEM_DQ31 MEM_DQ32 MEM_DQ33 MEM_DQ34 MEM_DQ35 MEM_DQ36 MEM_DQ37 MEM_DQ38 MEM_DQ39 MEM_DQ40 MEM_DQ41 MEM_DQ42 MEM_DQ43

MEM_A I/F

MEM_DQ44 MEM_DQ45 MEM_DQ46 MEM_DQ47 MEM_DQ48 MEM_DQ49 MEM_DQ50 MEM_DQ51 MEM_DQ52 MEM_DQ53 MEM_DQ54 MEM_DQ55 MEM_DQ56 MEM_DQ57 MEM_DQ58 MEM_DQ59 MEM_DQ60 MEM_DQ61 MEM_DQ62 MEM_DQ63

MEM_COMPP MEM_COMPN

AG30 AG29 AH28 AJ28 AH27 AJ27 AE23 AG22 AF23 AF22 AE20 AG19 AF20 AF19 AH26 AJ26 AK26 AH25 AJ24 AH23 AJ23 AH22 AK14 AH14 AK13 AJ13 AJ11 AH11 AJ10 AH10 AE15 AF15 AG14 AE14 AE12 AF12 AG11 AE11 AJ9 AH9 AJ8 AK8 AH7 AJ6 AH6 AJ5 AG10 AF11 AF10 AE9 AG7 AF8 AF7 AE7

AH5 AD30

WITH DVO: MEM_COMPP = 61.9 OHM TO GND MEM_COMPN = 61.9 OHM TO VDD_MEM MEM_CAP1 = NC MEM_CAP2 = NC MEM_VMODE = 1.8V(IF VDD_MEM = 1.8V) MEM_VREF = VDD_MEM / 2

B

DVO_MDA33 DVO_MDA34 DVO_MDA35 DVO_MDA36 DVO_MDA37 DVO_MDA38 DVO_MDA39

DVO_MDA48 DVO_MDA49 DVO_MDA50 DVO_MDA51 DVO_MDA52 DVO_MDA53 DVO_MDA54 DVO_MDA55

MEM_COMPP MEM_COMPN

PEG_TXP15 PEG_TXN15 PEG_TXP14 PEG_TXN14 PEG_TXP13 PEG_TXN13 PEG_TXP12 PEG_TXN12 PEG_TXP11 PEG_TXN11 PEG_TXP10 PEG_TXN10 PEG_TXP9 PEG_TXN9 PEG_TXP8 PEG_TXN8 PEG_TXP7 PEG_TXN7 PEG_TXP6 PEG_TXN6 PEG_TXP5 PEG_TXN5

LANE REVERSE

PEG_TXP4 PEG_TXN4 PEG_TXP3 PEG_TXN3 PEG_TXP2 PEG_TXN2 PEG_TXP1 PEG_TXN1 PEG_TXP0 PEG_TXN0

PCIE_RXP057

PCIE_RXN057

PCIE_RXP157

PCIE_RXN157

PCIE_RX0P_SB18 PCIE_RX0N_SB18

PCIE_RX1P_SB18 PCIE_RX1N_SB18

R620 10KR2R620 10KR2

1 2 1 2

8K25R3F

R633

1D8V_S0

R211 61D9R2FR211 61D9R2F

1 2

R630 61D9R2FR630 61D9R2F

1 2

Dummy when 'NO DVO'

SC 0308

RS480_MEM_VMODE

C

PCE_TXISET

C

PCE_ISET

PEG_TXP[15..0]49 PEG_TXN[15..0]49

PEG_RXP[15..0]49 PEG_RXN[15..0]49

U80B

D8

GFX_RX0P

D7

GFX_RX0N

D5

GFX_RX1P

D4

GFX_RX1N

E4

GFX_RX2P

F4

GFX_RX2N

G5

GFX_RX3P

G4

GFX_RX3N

H4

GFX_RX4P

J4

GFX_RX4N

H5

GFX_RX5P

H6

GFX_RX5N

G1

GFX_RX6P

G2

GFX_RX6N

K5

GFX_RX7P

K4

GFX_RX7N

L4

GFX_RX8P

M4

GFX_RX8N

N5

GFX_RX9P

N4

GFX_RX9N

P4

GFX_RX10P

R4

GFX_RX10N

P5

GFX_RX11P

P6

GFX_RX11N

P2

GFX_RX12P

R2

GFX_RX12N

T5

GFX_RX13P

T4

GFX_RX13N

U4

GFX_RX14P

V4

GFX_RX14N

W1

GFX_RX15P

W2

GFX_RX15N

AE1

GPP_RX0P/SB_RX2P

AE2

GPP_RX0N/SB_RX2N

AB2

GPP_RX1P/SB_RX3P

AC2

GPP_RX1N/SB_RX3N

AB5

GPP_RX2P

AB4

GPP_RX2N

Y4

GPP_RX3P

AA4

GPP_RX3N

AG1

SB_RX0P

AH1

SB_RX0N

AC5

SB_RX1P

AC6

SB_RX1N

AH3

PCE_ISET

AJ3

PCE_TXISET

1D8V_S0

12

R209

R209 1KR2

1KR2

PART 2 OF 6

PCIE I/F TO SLOT

PCIE I/F TO SB

Dummy when 'NO DVO'

R210

R210 1KR2

1KR2

1 2

Dummy when 'USE DVO'

A7

GFX_TX0P

B7

GFX_TX0N

B6

GFX_TX1P

B5

GFX_TX1N

A5

GFX_TX2P

A4

GFX_TX2N

B3

GFX_TX3P

B2

GFX_TX3N

C1

GFX_TX4P

D1

GFX_TX4N

D2

GFX_TX5P

E2

GFX_TX5N

F2

GFX_TX6P

F1

GFX_TX6N

H2

GFX_TX7P

J2

GFX_TX7N

J1

GFX_TX8P

K1

GFX_TX8N

K2

GFX_TX9P

L2

GFX_TX9N

GPP_TX2P GPP_TX2N

GPP_TX3P GPP_TX3N

SB_TX0P SB_TX0N

SB_TX1P SB_TX1N

PCE_PCAL PCE_NCAL

DVO_MDA33 DVO_MDA34 DVO_MDA35 DVO_MDA36 DVO_MDA37 DVO_MDA38 DVO_MDA39

DVO_MDA48 DVO_MDA49 DVO_MDA50 DVO_MDA51 DVO_MDA52 DVO_MDA53 DVO_MDA54 DVO_MDA55

M2 M1 N1 N2 R1 T1 T2 U2 V2 V1 Y2 AA2

AD2 AD1

AA1 AB1

Y5 Y6

W5 W4

AF2 AG2

AC4 AD4

AH2 AJ2

GFX_TX10P GFX_TX10N GFX_TX11P GFX_TX11N GFX_TX12P GFX_TX12N GFX_TX13P GFX_TX13N GFX_TX14P GFX_TX14N GFX_TX15P GFX_TX15N

GPP_TX0P/SB_TX2P GPP_TX0N/SB_TX2N

GPP_TX1P/SB_TX3P GPP_TX1N/SB_TX3N

PCIE I/F TO VIDEO

SC 0308

D

PEG_RXP15_NB PEG_RXP15 PEG_RXP14_NB PEG_RXP13_NB

PEG_RXN13_NB PEG_RXP12_NB PEG_RXN12_NB PEG_RXP11_NB PEG_RXN11_NB PEG_RXP10_NB PEG_RXN10_NB PEG_RXP9_NB PEG_RXN9_NB PEG_RXP8_NB PEG_RXN8_NB PEG_RXP7_NB PEG_RXN7_NB PEG_RXP6_NB PEG_RXN6_NB PEG_RXP5_NB PEG_RXN5_NB PEG_RXP4_NB PEG_RXN4_NB PEG_RXP3_NB PEG_RXN3_NB PEG_RXP2_NB PEG_RXN2_NB PEG_RXP1_NB PEG_RXN1_NB PEG_RXP0_NB PEG_RXN0_NB

PCIE_TXP0_NB PCIE_TXN0_NB

PCIE_TXP1_NB PCIE_TXN1_NB

SB_TX0P SB_TX0N

SB_TX1P SB_TX1N

PCE_PCAL PCE_NCAL

CHANGE TO 71.RS48M.B0U (VER A22)

DVO_MDA33 15 DVO_MDA34 15 DVO_MDA35 15 DVO_MDA36 15 DVO_MDA37 15 DVO_MDA38 15 DVO_MDA39 15

DVO_MDA48 15 DVO_MDA49 15 DVO_MDA50 15 DVO_MDA51 15 DVO_MDA52 15 DVO_MDA53 15 DVO_MDA54 15 DVO_MDA55 15

D

C742

1 2

SCD1U16V

C743

C743 C744

C744 C745

C745 C746

C746 C747

C747 C748

C748 C749

C749 C751

C751 C750

C750 C774

C774 C772

C772 C777

C777 C776

C776 C770

C770 C773

C773 C781

C781 C780

C780 C775

C775 C771

C771 C779

C779 C778

C778 C799

C799 C801

C801 C807

C807 C803

C803 C797

C797 C800

C800 C805

C805 C806

C806 C802

C802 C798

C798

C826

C826 C827

C827 C804

C804 C808

C808

C829

1 2

C828

1 2

C830

1 2

C831

1 2

1 2 1 2

Title

Size Document Number Rev

Date: Sheet

SCD1U16V

1 2

SCD1U16V

1 2

SCD1U16V

1 2

SCD1U16V

1 2

SCD1U16V

1 2

SCD1U16V

1 2

SCD1U16V

1 2

SCD1U16V

1 2

SCD1U16V

1 2

SCD1U16V

1 2

SCD1U16V

1 2

SCD1U16V

1 2

SCD1U16V

1 2

SCD1U16V

1 2

SCD1U16V

1 2

SCD1U16V

1 2

SCD1U16V

1 2

SCD1U16V

1 2

SCD1U16V

1 2

SCD1U16V

1 2

SCD1U16V

1 2

SCD1U16V

1 2

SCD1U16V

1 2

SCD1U16V

1 2

SCD1U16V

1 2

SCD1U16V

1 2

SCD1U16V

1 2

SCD1U16V

1 2

SCD1U16V

1 2

SCD1U16V

1 2

SCD1U16V

1 2

SCD1U16V

1 2

SCD1U16V

1 2

SCD1U16V

1 2

SCD1U16V

1 2

SCD1U16V

SCD1U16V SCD1U16V

SCD1U16V R632 150R2FR632 150R2F R631 100R2FR631 100R2F

ATI-RS480M (2 of 4) PCIE

A3

Dummy when no EZ4

E

PEG_RXN15PEG_RXN15_NB PEG_RXP14 PEG_RXN14PEG_RXN14_NB PEG_RXP13 PEG_RXN13 PEG_RXP12 PEG_RXN12 PEG_RXP11 PEG_RXN11 PEG_RXP10 PEG_RXN10 PEG_RXP9 PEG_RXN9 PEG_RXP8 PEG_RXN8 PEG_RXP7 PEG_RXN7 PEG_RXP6 PEG_RXN6 PEG_RXP5 PEG_RXN5 PEG_RXP4 PEG_RXN4 PEG_RXP3 PEG_RXN3 PEG_RXP2 PEG_RXN2 PEG_RXP1 PEG_RXN1 PEG_RXP0 PEG_RXN0

Dummy when use UMA

PCIE_TXP0 57 PCIE_TXN0 57

PCIE_TXP1 57 PCIE_TXN1 57

PCIE_TX0P_SB 18 PCIE_TX0N_SB 18

PCIE_TX1P_SB 18 PCIE_TX1N_SB 18

1D2V_S0

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena

12 58Thursday, March 31, 2005

E

LANE REVERSE

-1

of

-1

A

12

DY

1 2

150R5F

SC 0308

12

LPC_RST#18,34,37

AVDDQ

12

C766

C769

SCD1U16V

SC10U10V5ZY

Dummy when use Discrete

UMA_CRMA57

UMA_LUMA57

UMA_COMP57

UMA_R57 UMA_G57

1D8V_S0

12

R635

R635 4K7R2

4K7R2

NB_SUS_STAT#

UMA_B57

R593

1 2

BLM11A121S

HTPVDD

12

C768

12

C767

SCD1U16V

SC10U10V5ZY

DO NOT SUPPORT SIDEPORT MEMORY DO NOT SUPPORT SERIAL STRAP ROM DUMMY IT

1 2

3D3V_S5

C968

12

SCD1U16V

SC 0310

1 2

A

C765

R183

12

147

PLVDD

C740

SC10U10V5ZY

SCD1U16V

3D3V_S01D8V_S0

DY

0R2-0

1 2

SC 0301

R585 102R2FR585 102R2F

R165 102R2FR165 102R2F

R586 102R2FR586 102R2F

12

C717

C741

SCD1U16V

SC2D2U16V5ZY

R188

1 2

0R0603-PAD

SC 0308

EDID_CLK17,49 EDID_DAT17,49

12

C259

C259 SC1U10V3ZY

SC1U10V3ZY

3 4

Dummy when use Discrete

U22A

R760

33R2

R760

1 2

RS480_RST#

33R2

3

TSLCX08MTC-U

R159

1D8V_S0

3D3VDDR_S0

RN107

RN107 SRN0-2-U

SRN0-2-U

R759

R759 0R2-0

0R2-0

DY

1 2

1D8V_S0

R610

1 2

0R0603-PAD

SC 0308

4 4

3 3

1D8V_S0

R609

2 2

LDT_RST#6,18

ALL_PWROK39

1 1

B

AVDD3D3V_S0

R584

1 2

0R0603-PAD

SC 0308

R164

1 2

0R0603-PAD

R588

150R2F

1 2

3D3V_S0

2 1

0R0603-PAD

SC 0308

12

R589

R587

150R2F

UMA_VS16 UMA_HS16

UMA_CRT_DDC_C16 UMA_CRT_DDC_D16

CLK14_NB3 SB_OSC_INT21

RS480_CLK15

RN106

3

12

C220

C220 SC2D2U16V5ZY

SC2D2U16V5ZY

AVDDQ

12

C254

C254 SC1U10V3ZY

SC1U10V3ZY

ALLOW_LDTSTOP18

14 2

SRN10KJ

GMODULE_RST# 34

Place close the two resistor

AG_RST# 49

SC 0307

12

C251

C251 DUMMY-C3

DUMMY-C3

B

C735

C735 SC2D2U16V5ZY

SC2D2U16V5ZY

1D8VAVDDD1_S0

R163

1 2

634R3F

NB_PWRGD39

LDT_STP#6,18

TP32TPAD30 TP32TPAD30 TP24TPAD30 TP24TPAD30 TP23TPAD30 TP23TPAD30

R594

1 2

DY

BMREQ#18

SC 0228

22R2

RS480_RST#

NB_SUS_STAT#

NB_OSC_OUT

R595 10KR2R595 10KR2

1 2

DFT_GPIO0 DFT_GPIO2

RS480_CLK RS480_DAT

LVDS_DIGON

NB_PWRGD

LVDS_BLON

IRSET_NB

3D3V_S5

4 5

12

R608

R608 1KR2

1KR2

C

U80D

B27

AVDD1

C27

AVDD2

D26

AVSSN1

D25

AVSSN2

C24

AVDDDI

B24

AVSSDI

E24

AVDDQ

D24

AVSSQ

B25

C

A25

Y

A24

COMP

C25

RED

A26

GREEN

B26

BLUE

A11

DAC_VSYNC

B11

DAC_HSYNC

C26

RSET

E11

DAC_SCL

F11

DAC_SDA

A14

PLLVDD

B14

PLLVSS

M23

HTPVDD

L23

HTPVSS

D14

SYSRESET#

B15

POWERGOOD

B12

LDTSTOP#

C12

ALLOW_LDTSTOP

AH4

SUS_STAT#

H13

VDDR3_1

H12

VDDR3_2

A13

OSCIN

B13

OSCOUT

B9

TVCLKIN

F12

DFT_GPIO0/RSV

E13

DFT_GPIO1/RSV

D13

DFT_GPIO2/RSV

F10

BMREQb

C10

I2C_CLK

C11

I2C_DATA

AF4

THERMALDIODE_P

AE4

THERMALDIODE_N

CHANGE TO 71.RS48M.B0U (VER A22)

R185

1 2

DY

U22B

147

TSLCX08MTC-U

6

3D3V_S5

147

12 13

C

PART 4 OF 6

CRT/TVOUT

PLL PWR

PM

CLOCKs

MIS.

0R2-0

U22D

R607

11

1 2

TSLCX08MTC-U

Dummy when use Discrete

DFT_GPIO3/RSV DFT_GPIO4/RSV DFT_GPIO5/RSV

LCDVDD_ON

0R2-0

TXOUT_U0P TXOUT_U0N TXOUT_U1P TXOUT_U1N TXOUT_U2P TXOUT_U2N TXOUT_U3P TXOUT_U3N

TXOUT_L0P TXOUT_L0N TXOUT_L1P TXOUT_L1N TXOUT_L2P TXOUT_L2N TXOUT_L3P TXOUT_L3N

TXCLK_UP TXCLK_UN

TXCLK_LP

LVDS

TXCLK_LN

LPVDD LPVSS

LVDDR18D LVDDR18A_1 LVDDR18A_2

LVSSR1 LVSSR2 LVSSR3 LVSSR4 LVSSR5 LVSSR6 LVSSR7 LVSSR8

LVDS_DIGON

LVDS_BLON LVDS_BLEN

GFX_CLKP

GFX_CLKN

HTTSTCLK

HTREFCLK

SB_CLKP SB_CLKN

TMDS_HPD

STRP_DATA

DDC_DATA TESTMODE

VCC_CORE_S0

12

D18 C18 B19 A19 D19 C19 D20 C20

B16 A16 D16 C16 B17 A17 E17 D17

B20 A20 B18 C17

E18 F17 E19 G20 H20

G19 E20 F20 H18 G18 F19 H19 F18

E14 F14 F13

B8 A8

P23 N23

E8 E7

C13 C14 C15

A10 E10 B10 E12

R186

R186 DUMMY-R2

DUMMY-R2

R187

R187 4K7R2

4K7R2

R739

R739 10KR2

10KR2

1 2

D

TXBOUT0+ TXBOUT0TXBOUT1+ TXBOUT1TXBOUT2+

TXBOUT2TXBOUT3+ TXBOUT3-

TXAOUT0+

TXAOUT0-

TXAOUT1+

TXAOUT1-

TXAOUT2+

TXAOUT2TXAOUT3+ TXAOUT3-

TXBCLK+

TXBCLK-

TXACLK+

TXACLK-

LVDS_DIGON LVDS_BLON LVDS_BLEN_NB

HTTST_CLK

DFT_GPIO3

DFT_GPIO4DFT_GPIO1

DFT_GPIO5

DDC_DATA TESTMODE_NB

BL_ON 34,49

SB 0201

D

TP28TP28 TP22TP22

R196

1 2

DDC_DATA 15

E

TXACLK+ TXACLKTXAOUT2+ TXAOUT2-

TXAOUT1+ TXAOUT1TXAOUT0+ TXAOUT0-

TXBOUT1+ TXBOUT1TXBOUT0+ TXBOUT0-

TXBCLK+ TXBCLKTXBOUT2+ TXBOUT2-

LCDVDD_ON

6 7 8

R184

RN90

RN89

RN95

RN94

12

0R2-0

45 3 2 1

SRN0-1-U

45 3 2 1

SRN0-1-U

45 3 2 1

SRN0-1-U

45 3 2 1

SRN0-1-U

LCD_TXACLK+ 17,54

LCD_TXACLK- 17,54

LCD_TXAOUT2+ 17,54

LCD_TXAOUT2- 17,54

LCD_TXAOUT1+ 17,54

LCD_TXAOUT1- 17,54

LCD_TXAOUT0+ 17,54

LCD_TXAOUT0- 17,54

LCD_TXBOUT1+ 17,54

LCD_TXBOUT1- 17,54

LCD_TXBOUT0+ 17,54

LCD_TXBOUT0- 17,54

LCD_TXBCLK+ 17,54

LCD_TXBCLK- 17,54

LCD_TXBOUT2+ 17,54

LCD_TXBOUT2- 17,54

LCD_VDD_ON 17,54

Dummy when use Discrete

R592 TP30TP30 TP29TP29

1D8VLPVDD_S0

LVDDR18D_S0

LVDDR18A_S0

TP31 TPAD30TP31 TPAD30

NBSRC_CLK 3 NBSRC_CLK# 3

10KR2

HTREF_CLK 3 SBLINK_CLK 3

SBLINK_CLK# 3

TP81 TPAD30TP81 TPAD30 TP80 TPAD30TP80 TPAD30 TP79 TPAD30TP79 TPAD30

TMDS_UMA_HPD 15

TP33 TPAD28TP33 TPAD28

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

ATI-RS480M (3 of 4) LVDS CRT

A3

12

C739

SC1U10V3ZY

12

C738

12

SC1U10V3ZY

C226

C737

SC1U10V3ZY

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena

E

12

SCD1U16V

C227

SC2D2U16V5ZY

C225

SCD1U16V

13 58Thursday, March 31, 2005

R592

1 2

R591

1 2

R590

1 2

of

1D8V_S0

BLM11A121S

-1

A

B

C

D

E

VSS89

H17

H10

H16

H14

E16

D10

E15

F15

U15

V14

R15

T14

N15

V12

N13

P14

U17

T16

R17

P12

T12

R13

W13

W17

P18

V18

M18

U13

N17

W15

V16

T18

M14

M12

M16

P16

U19

AC16

AG18

AC23

AD8

AD11

AD13

AD16

AD19

AD23

AG5

AG6

AG21

AD17

AG15

AG12

AF30

AG24

AG9

AC19

AG27

AC11

AD7

AJ30

AC21

AK5

AK10

AC13

AD21

AK22

AK29

W19

AE26

AE27

T27

R27

AD28

F24

F27

G28

U80F

4 4

3 3

12

C253

C253 SCD1U16V

SCD1U16V

C280

C280 SCD1U16V

SCD1U16V

C825

C825 SCD1U16V

SCD1U16V

C293

C293 SCD1U16V

SCD1U16V

12

C252

C252 SCD1U16V

SCD1U16V

12

C281

C281 SCD1U16V

SCD1U16V

DY

12

C285

C285 SCD1U16V

SCD1U16V

12

C329

C329 SCD1U16V

SCD1U16V

DY

L11

1 2

BLM11A121S

DY

1 2

U25

U25 BAV99-1

BAV99-1

DY

A

0R2-0

3

12

R216

C257

C257 SCD1U16V

SCD1U16V

DY

C282

C282 SCD1U16V

SCD1U16V

C330

C330 SCD1U16V

SCD1U16V

C325

C325 SCD1U16V

SCD1U16V

12

C284

C284 SC10U10V5ZY

SC10U10V5ZY

DY

12

C278

C278 SCD1U16V

SCD1U16V

2 2

12

C821

C821 SC10U10V5ZY

SC10U10V5ZY

12

C326

C326 SCD1U16V

SCD1U16V

1D8V_S0

1 1

3D3V_S0

3

1 2

U24

U24 BAV99-1

BAV99-1

DY

12

DY

R215

0R2-0

C255

C255 SCD1U16V

SCD1U16V

C283

C283 SCD1U16V

SCD1U16V

C287

C287 SCD1U16V

SCD1U16V

C331

C331 SCD1U16V

SCD1U16V

DY

12

C346

12

SCD1U16V

C223

C223 SCD1U16V

SCD1U16V

C279

C279 SCD1U16V

SCD1U16V

C323

C323 SCD1U16V

SCD1U16V

C344

C344 SCD1U16V

SCD1U16V

1D8VDD_S0

12

C258

SCD1U16V

12

VSS111

VSS112

C224

C224 SCD1U16V

SCD1U16V

C277

C277 SCD1U16V

SCD1U16V

C328

C328 SCD1U16V

SCD1U16V

C327

C327 SCD1U16V

SCD1U16V

C291

SCD1U16V

VSS108

VSS109

VSS110

1D8V_S0

12

C288

VSS107

C345

C333

C333 SCD1U16V

SCD1U16V

1D2V_S0

SC1U10V3KX

VSS102

VSS103

VSS104

VSS105

VSS106

1D2V_S0

VDDHT30 VDDHT31

SCD1U16V

VSS95

VSS96

VSS97

VSS98

VSS99

VSS100

VSS101

U80E

N27

VDD_HT1

U27

VDD_HT2

V27

VDD_HT3

G27

VDD_HT4

V24

VDD_HT5

H27

VDD_HT6

K24

VDD_HT7

AB24

VDD_HT8

P27

VDD_HT9

J27

VDD_HT10

AA27

VDD_HT11

K27

VDD_HT12

P24

VDD_HT13

AB27

VDD_HT14

AB23

VDD_HT15

V23

VDD_HT16

G23

VDD_HT17

E23

VDD_HT18

W23

VDD_HT19

K23

VDD_HT20

J23

VDD_HT21

H23

VDD_HT22

U23

VDD_HT23

AA23

VDD_HT24

D23

VDD_HT25

F23

VDD_HT26

C23

VDD_HT27

B23

VDD_HT28

A23

VDD_HT29

A29

VDD_HT30

AC30

VDD_HT31

AK23

VDD_MEM1

AK28

VDD_MEM2

AK11

VDD_MEM3

AK4

VDD_MEM4

AE30

VDD_MEM5

AC14

VDD_MEM6

AD12

VDD_MEM7

AC18

VDD_MEM8

AC20

VDD_MEM9

AD10

VDD_MEM10

AD14

VDD_MEM11

AD15

VDD_MEM12

AD20

VDD_MEM13

AC10

VDD_MEM14

AD18

VDD_MEM15

AC12

VDD_MEM16

AD22

VDD_MEM17

AC22

VDD_MEM18

AH15

VDD_MEMCK

H15

VDD_18_1

AC17

VDD_18_2

AC15

VDD_18_3

B21

VDD_CORE47

C21

VDD_CORE46

A22

VDD_CORE45

B22

VDD_CORE44

C22

VDD_CORE43

F21

VDD_CORE42

F22

VDD_CORE41

E21

VDD_CORE40

G21

VDD_CORE39

B

VSS93

VSS94

VSS89

VSS90

VSS91

VSS92

PART 5 OF 6

VSS85

VSS86

VSS87

VSS88

VSS129

VSS130

VSS131

VSS132

K25

V25

V28

U28

R23

POWER

VSS83

VSS84

VSS127

VSS128

E26

VDDA_12_14

VDDA_12_1 VDDA_12_2 VDDA_12_3 VDDA_12_4 VDDA_12_5 VDDA_12_6 VDDA_12_7 VDDA_12_8

VDDA_12_9 VDDA_12_10 VDDA_12_11 VDDA_12_12 VDDA_12_13

VDDA_18_1

VDDA_18_2

VDDA_18_3

VDDA_18_4

VDDA_18_5

VDDA_18_6

VDDA_18_7

VDDA_18_8

VDDA_18_9 VDDA_18_10 VDDA_18_11 VDDA_18_12 VDDA_18_13 VDD_CORE1 VDD_CORE2 VDD_CORE3 VDD_CORE4 VDD_CORE5 VDD_CORE6 VDD_CORE7 VDD_CORE8 VDD_CORE9

VDD_CORE10 VDD_CORE11 VDD_CORE12 VDD_CORE13 VDD_CORE14 VDD_CORE15 VDD_CORE16 VDD_CORE17 VDD_CORE18 VDD_CORE19 VDD_CORE20 VDD_CORE21 VDD_CORE22 VDD_CORE23 VDD_CORE24 VDD_CORE25 VDD_CORE26 VDD_CORE27 VDD_CORE28 VDD_CORE29 VDD_CORE30 VDD_CORE31 VDD_CORE32 VDD_CORE33 VDD_CORE34 VDD_CORE35 VDD_CORE36 VDD_CORE37 VDD_CORE38

VSS77

VSS78

VSS79

VSS80

VSS81

VSS82

VSS122

VSS123

VSS124

VSS125

VSS126

L27

P25

P28

H24

N28

M27

H9 AA7 G9 U8 N7 N8 U7 F9 AA8 G8 G7 J8 J7 B1 AG4 R8 AC8 AC7 AF6 AE6 L8 W8 W7 L7 R7 AF5 AK2 N16 M13 M15 W16 N18 P19 N12 P15 N14 M17 T19 G22 R12 P13 R14 V19 R18 U16 U12 T13 U14 T17 U18 E22 R16 V13 T15 P17 W18 D22 W12 V15 W14 V17 M19 H22 H21 D21

VSS72

VSS73

VSS74

VSS75

VSS76

VSS114

VSS115

VSS116

VSS117

VSS118

VSS119

VSS120

J28

T23

K28

H28

N19

M24

VDDA12_13

VDDA18_13

CHANGE TO 71.RS48M.B0U (VER A22)

VSS66

VSS67

VSS68

VSS69

VSS70

VSS71

GROUND

VSS113

T8

F28

12

1D8V_VDDA

12

1D2V_S0

C

VSS62

VSS63

VSS64

VSS65

12

C261

C261 SC1U10V3KX

SC1U10V3KX

12

C332

C332 SC1U10V3KX

SC1U10V3KX

12

C289

C289 SC10U10V5ZY

SC10U10V5ZY

12

C292

C292 SC10U10V5ZY

SC10U10V5ZY

VSS60

VSS61

C263

C263 SCD1U16V

SCD1U16V

C302

C302 SCD1U16V

SCD1U16V

DY

VSS59

VSS58

VSSA60M7VSSA61V7VSSA62F6VSSA63E6VSSA64U5VSSA65U6VSSA66E5VSSA67L5VSSA68

AJ1

VSSA59

12

VSS55

VSS56

VSS57

VSSA58L6VSSA59

AG3

C304

C304 SCD1U16V

SCD1U16V

C303

C303 SCD1U16V

SCD1U16V

C294

C294 SCD1U16V

SCD1U16V

C290

C290 SCD1U16V

SCD1U16V

VSS54

VSS53

12

VSS50

VSS51

VSS52

C301

C301 SCD1U16V

SCD1U16V

C262

C262 SCD1U16V

SCD1U16V

C295

C295 SCD1U16V

SCD1U16V

C286

C286 SCD1U16V

SCD1U16V

VSS48

VSS49

VSSA51K7VSSA52H7VSSA53M3VSSA54V6VSSA55H8VSSA56C2VSSA57

AD6

12

DY

12

VSS44

VSS45

VSS46

VSS47

VSSA44D6VSSA45C4VSSA46K3VSSA47

VSSA48T7VSSA49Y7VSSA50

AB8

AD5

1D2V_VDDA_RS480_S0

12

C299

C299 SCD1U16V

SCD1U16V

C300

C300 SCD1U16V

SCD1U16V

C256

C256 SCD1U16V

SCD1U16V

DY

C297

C297 SCD1U16V

SCD1U16V

12

C260

C260 SCD1U16V

SCD1U16V

C298

C298 SCD1U16V

SCD1U16V

VSS40

VSS41

VSS42

VSS43

C305

C305 SC10U10V5ZY

SC10U10V5ZY

12

VSS37

VSS38

VSS39

VSSA38C9VSSA39C7VSSA40J5VSSA41R6VSSA42J3VSSA43

AA5

TC10

TC10 ST100U6D3VDM-5

ST100U6D3VDM-5

DY

12

D

F26

W27

D11

H11

AD25

VSS33

VSS34

VSS35

VSS36

VSSA34G3VSSA35B4VSSA36P7VSSA37

AB7

12

DY

1 2

C296

C296 SCD1U16V

SCD1U16V

VSS30

D15

AD9

G11

F16

G30

AB28

AB25

D12

AD24

AA28

G17

Y23

AC9

R19

Y27

C28

G16

F25

B30

T24

VSS12D9VSS13

VSS14

VSS15

VSS16

VSS17

VSS18

VSS19

VSS20

VSS21

VSS22

VSS23

VSS24

VSS25

VSS26

VSS27

VSS28

VSS29

VSS30

VSS31

VSS32

VSSA22A2VSSA23

VSSA24P8VSSA25J6VSSA26C8VSSA27

VSSA28V8VSSA29F3VSSA30

VSSA31

VSSA32M5VSSA33

AF3

AE3

1 2

TC9

TC9 ST100U6D3VDM-5

ST100U6D3VDM-5

1D8V_S0

L9

L9 MLB-201209-11

MLB-201209-11

AA3

AB3

AD3

VSSA22

1D2V_S0

L10

L10 MLB-201209-11

MLB-201209-11

SB 0127

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

ATI-RS480M (4 of 4) PWR, GND

A3

Bolsena

AC27

G15

G14

Y24

G13

VSS5

VSS6

VSS7

VSS8

VSS9

VSS10E9VSS11

VSSA7R3VSSA8

VSSA9T3VSSA10M6VSSA11C5VSSA12F8VSSA13M8VSSA14Y8VSSA15V3VSSA16C3VSSA17W3VSSA18K8VSSA19D3VSSA20C6VSSA21

F5

AA6

VDDA12_13

VSSA22

VDDA18_13

VSSA59

VDDHT30

VSS30

VDDHT31

VSS89

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

E

AD27

VSS4

VSSA4N3VSSA5F7VSSA6

AD29

VSS3

VSSA3

V5

G10

G12

VSS2

PAR 6 OF 6

VSSA2

R5

AE5

14 58Thursday, March 31, 2005

VSS1

VSSA1

12

C264

C264 SC4D7U10V5ZY

SC4D7U10V5ZY

C334

C334 SC4D7U10V5ZY

SC4D7U10V5ZY

C736

C736 SC4D7U10V5ZY

SC4D7U10V5ZY

C796

C796 SC4D7U10V5ZY

SC4D7U10V5ZY

of

-1

A

B

C

D

E

3D3V_S0

2

14

RN16

SRN10KJ

4 4

To Discrete

RN20

DIS_DVI_DDC_D49

DIS_DVI_DDC_C49

3 4

SRN0-2-U

Dummy when use UMA

To UMA

DDC_DATA13

RS480_CLK13

3 3

2 2

2 1

3 4

3D3V_S0

12

DVI_D_1

DVI_C_1

RN21

SRN0-2-U

R720

R720 10KR2

10KR2

DY

R723

R723 330R2

330R2

SRN10KJ

3

5 6

2 1

PCIRST_BUF#18,26,28,29,31,57

1 2

34 2 1

R733 0R2-0R733 0R2-0

12

U11

U11 2N7002DW

2N7002DW

C955

3D3V_S0

DUMMY-C2

1D8V_S0

To Discrete

R42

DVI_HPD49

TMDS_UMA_HPD13

1 2

To UMA & CH7301

1 1

A

B

5V_S0

2

14

RN15

SRN10KJ

3

DVO_MDA3312 DVO_MDA3412 DVO_MDA3512 DVO_MDA3612 DVO_MDA3712 DVO_MDA3812 DVO_MDA4812 DVO_MDA3912 DVO_MDA5112 DVO_MDA5012 DVO_MDA4912 DVO_MDA5212

DVO_MDA5312

DVO_MDA5412 DVO_MDA5512

RN118 SRN0-2-URN118 SRN0-2-U

DVI_D_1

3

DVI_C_1

4

R721 0R2-0

1 2

R722 0R2-0

1 2

R724 140R2F-GPR724 140R2F-GP

1 2

R725

1 2

2K4R2F

0R2-0

IDCKN12 IDCKP12

DY

DY DY

DY

R361KR2 R361KR2 R351KR2 R351KR2

12

To EZ4 (5V level)

EZ4_DVI_DDC_D 57

EZ4_DVI_DDC_C 57

DVO_MDA33 DVO_MDA34 DVO_MDA35 DVO_MDA36 DVO_MDA37 DVO_MDA38 DVO_MDA48 DVO_MDA39 DVO_MDA51DVO_MDA51 DVO_MDA50 DVO_MDA49 DVO_MDA52

DVO_MDA53

DVO_MDA54 DVO_MDA55

CH7301_DATA

2

CH7301_CLK

1

DVI_GIPO0 DVI_GIPO1

DVI_AS

DVI_VSWING VREF_DVI

12 12

C25SCD1U10V2MX C25SCD1U10V2MX

TMDS_HPD

DVI_ISET

Dummy when use UMA

R41

0R2-0

Dummy when use Discrete

SB 0128

CHT2222A

50

D11

51

D10

52

D9

53

D8

54

D7

55

D6

58

D5

59

D4

60

D3

61

D2

62

D1

63

D0

56

XCLK#

57

XCLK

2

DE

46

P-OUT/TLDET#

4

H

5

V

13

RESET#

14

SPD

15

SPC

8

GPIO0

7

GPIO1/TLDET#

10

AS

35

ISET

19

VSWING

3

VREF

Q3

12

10KR2

3

2

C

R43

1

TMDS_EZ4_TX0-

TMDS_EZ4_TX0+

TMDS_EZ4_TX1-

21

24

22

TDC0

TDC0#

TDC1#

XI/FIN

42

Q4

CHT2222A

TMDS_EZ4_TX2-

TMDS_EZ4_TX2+

TMDS_EZ4_TXC+

TMDS_EZ4_TX1+

27

25

28

TDC1

TDC2

TDC2#

3D3V_S0

12

3

2

30

TLC

TMDS_EZ4_TXC-

31

TLC#

R56

R56 10KR2

10KR2

1

C/HSYNC

XO

CH7301C-T

43

HPDET

BCO

CVBS

CVBS/B

DVDD DVDD DVDD

DGND DGND DGND

DVDDV

TVDD

TVDD TGND TGND TGND

AVDD

AVDD AGND AGND AGND

VDD GND GND

SB 0202

U10

Y/G C/R

SB 0127

9 47 48 36 37 38 39 1

12 49

6 11 64

45 23

29 20 26 32

18 44 16 17 41 33 34 40

TMDS_UMA_HPD

R726 75R2F

1 2

DY

R728 75R2F

1 2

DY

R727 75R2F

1 2

DY

3D3V_DVI_DVDD_S0

1D8V_DVI_DVDDV_S0

3D3V_DVI_TVDD_S0

3D3V_DVI_AVDD_S0

3D3V_DVI_VDD_S0

TMDS_EZ4_TX2- 49,57

TMDS_EZ4_TX2+ 49,57

TMDS_EZ4_TX1- 49,57

TMDS_EZ4_TX1+ 49,57

TMDS_EZ4_TX0- 49,57

TMDS_EZ4_TX0+ 49,57

TMDS_EZ4_TXC+ 49,57

TMDS_EZ4_TXC- 49,57

12

C954

C953

SC10U10V5ZY

1 2

SCD1U10V2MX

12

C26

C27

1 2

SCD1U10V2MX

12

R3

SB 0127

100KR2R3100KR2

Place Near Dock

D

SB change much in this page 0127

3D3V_S0

R34

12

BLM11A121S

12

C51

C52

R54

12

BLM11A121S

R4

SC2200P50V2KX

1 2

10KR2R410KR2

1D8V_S0

3D3V_S0

R39

12

Title

Size Document Number Rev

A3

Date: Sheet

Date: Sheet of

1 2

SC2200P50V2KX

12

C57

C56

1 2

SC2200P50V2KX

12

C29

C30

1 2

SC2200P50V2KX

Dummy when use Discrete

DVI_EZ4_HPD 57

Dummy when no EZ4

UMA DVI - CH7301C

BLM11A121S

12

C24

SC10U10V5ZY

SCD1U10V2MX

D51

12

C55

12

C28

Bolsena

21

SSM5817S

R40

SC10U10V5ZY

12

BLM11A121S

SC10U10V5ZY

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

E

-1

15 58Thursday, March 31, 2005

of

-1

A

CRT CONN

200mA Rating/Spec 500mA

5V_S0

4 4

RN6

2

UMA_HS13 UMA_VS13

Dummy when use Discrete

DIS_HS49 DIS_VS49

3 4

Dummy when use UMA

SRN0-2-U

RN7

SRN0-2-U

VSYNC_5_1

1

2 1

HSYNC_5_1

14

4

5 6

7

2 3

U2B

TSAHCT125

U2A

14

1

HSYNC_5

TSAHCT125

7

VSYNC_5

C3

DUMMY-C2C3DUMMY-C2

B

To SYS and EZ4 CRT Both

R1

1 2

10R3R110R3

R2

1 2

10R3R210R3

12

SC 0308

C2

DUMMY-C2C2DUMMY-C2

SYS_HS

SYS_VS

RN5

3 4

SRN0-2-U

Dummy when no EZ4

2 1

UMA_CRT_DDC_D13

UMA_CRT_DDC_C13

EZ4_HS 57

EZ4_VS 57

C

RN3

3 4

SRN0-2-U

Dummy when use Discrete

DIS_CRT_DDC_D49

DIS_CRT_DDC_C49

2

14

RN82

SRN10KJ

3

CRT_DDC_D_1

2

CRT_DDC_C_1

1

RN4

SRN0-2-U

2 1

3 4

Dummy when use UMA

D

3D3V_S0

5V_CRT_S0

2

5V_S0

12

14

C657

C657 SCD01U50V2ZY

SCD01U50V2ZY

U1

U1 2N7002DW

2N7002DW

34 5 6

2

1

To SYS and EZ4 CRT Both

RN1

SRN10KJ

3

SYS_CRT_DDC_D5 SYS_CRT_DDC_C5

RN2

SRN0-2-U

5V_CRT_S0

2 1

D28

1 2

RB751V-40-U

3 4

E

EZ4_CRT_DDC_D 57 EZ4_CRT_DDC_C 57

Dummy when no EZ4

3 3

CRT_R_SYS57

CRT_G_SYS57

CRT_B_SYS57

2 2

1 1

12

DY

TV_LUMA_SYS57

TV_COMP_SYS57

TV_CRMA_SYS57

C666

A

12

SC47P50V2JN

DY

C667

12

C668

SC47P50V2JN

DY

12

R505150R2FR505150R2F

R504150R2FR504150R2F

SC 0228

R171

R172

R151

150R2F

1 2

SC 0302

12

R506150R2FR506150R2F

L22

1 2

L23

1 2

L24

1 2

12

C236

C236 SC100P50V2JN

SC100P50V2JN

1 2

12

C237

C237 SC100P50V2JN

SC100P50V2JN

1 2

12

C238

SC100P50V2JN

BLM18BB750SN1D

C232

C232 SC47P50V2JN

SC47P50V2JN

L6

IND-1D2UH

C233

C233 SC47P50V2JN

SC47P50V2JN

L7

IND-1D2UH

C231

C231 SC47P50V2JN

SC47P50V2JN

L8

IND-1D2UH

B

C652

SC8D2P50V2CC

TV_LUMA_CON

12

C235

C235 SC270P50V

SC270P50V

TV_COMP_CON

12

C234

C234 SC270P50V

SC270P50V

TV_CRMA_CON

12

C209

SC270P50V

CRT_R

CRT_G

CRT_B

12

C653

SC8D2P50V2CC

SC 0228

12

C654

SC 0228

3

2

1 4

2 5 7 6 3

MINDIN7-11

22.10021.D81

ME : 22.10021.D81

TV1

3

SC8D2P50V2CC

D34

BAV99-2

D35

BAV99-2

D36

BAV99-2

SC 0302

DY

D27

BAV99-2

DY

2

1

2

1

2

1

3

2

3D3V_S0

D26

1

BAV99-2

DY

3

2

TV_LUMA_CON

TV_COMP_CON

TV_CRMA_CON

C

D25

1

BAV99-2

DY

SYS_HS

SYS_VS

C655

SC100P50V2JN

5V_S0

8

9

SYS_CRT_DDC_D5

SYS_CRT_DDC_C5

C659

12

C656

SC100P50V2JN

SC10P50V2JN-1

TV CONN

COMPOSIT

D

CRT_R

CRT_G CRT_B

5V_CRT_S0

12

C658

SC10P50V2JN-1

456

123

7

Title

Size Document Number Rev

A3

Date: Sheet

Date: Sheet of

CRT / TV

CRT / TV Bolsena

Bolsena

CRT1

17

6 1

11

7 2 8 3 9 4

10

5

20.20378.015

VIDEO-15-42

12 13 14 15 16

SYS_CRT_DDC_D5 SYS_HS SYS_VS SYS_CRT_DDC_C5

ME : 20.20378.015

LUMACHROMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

16 58Thursday, March 31, 2005

E

-1

of

-1

A

B

C

D

E

LEDs

4 4

Dummy when use IDE

R22

C663

1 2

0R2-0

2

1

SC 0310

DCBATOUT

C651

12

SC10U35V0ZY-U

D8

MEDIA_LED#

3

BAW56D8BAW56

NUM_LED#34 CAP_LED#34 MAIL_LED#34 BLT_LED#34

STDBY_LED#34 CHARGE_LED#34 DC_BATFULL#34

FRONT_PWRLED#34

LCD CONN

LCD1

42

2 4

6 8

3D3V_S0

C664

12

SCD1U

10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 41

JST-CONN40A-2

20.F0439.040

1ST 20.F0687.040 - 2ND 20.F0439.040

NUM_LED#

CAP_LED# MAIL_LED# MEDIA_LED#

WLAN_LED#

STDBY_LED# BLT_LED#

CHARGE_LED#

DC_BATFULL#

FRONT_PWRLED#

LCDPOWER_S0

12

C39

C37

SC10U10V5ZY

C37

1 3

5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

SB 0202

B

DY

LCD_TXBCLK+ 13,54 LCD_TXBCLK- 13,54 LCD_TXBOUT2+ 13,54 LCD_TXBOUT2- 13,54 LCD_TXBOUT1+ 13,54 LCD_TXBOUT1- 13,54 LCD_TXBOUT0+ 13,54 LCD_TXBOUT0- 13,54 LCD_TXACLK+ 13,54 LCD_TXACLK- 13,54 LCD_TXAOUT2+ 13,54 LCD_TXAOUT2- 13,54 LCD_TXAOUT1+ 13,54 LCD_TXAOUT1- 13,54 LCD_TXAOUT0+ 13,54 LCD_TXAOUT0- 13,54

1 2 3 4 5

C644SC100P50V2JNC644SC100P50V2JN

1 2

C229SC100P50V2JNC229SC100P50V2JN

1 2

12

C38

SCD1U

DY

SCD1U

EVEN CHANNEL

ODD CHANNEL

R21

1 2

0R2-0

WLAN_LED#31

EDID_CLK13,49

EDID_DAT13,49

C665

1 2

SC100P50V2JN

A

SATA_LED#19

HDD_LED#_525

Dummy when use SATA

CDROM_LED#_525

3 3

2 2

BRIGHTNESS34

FPBACK34

1 1

?modify R ?half light

SRC100P50V-U

RC2

8 7 6

SRC100P50V-U

RC9

8 7 6

on KB cover

LED ButtonVV

POWER1 E-MAIL INTERNET e-BTN PROGRAM

Front panel

LED ButtonVV

BlutToothWireless Charger Power2

LCD_VDD_ON13,54

C

NUM_LED#

CAP_LED#

MAIL_LED#

MEDIA_LED#

WLAN_LED#

SC 0302

FRONT_PWRLED#

DC_BATFULL#

BLT_LED#

STDBY_LED#

CHARGE_LED#

V

R17

1 2

R16

1 2

R14

1 2

R19

1 2

R483

1 2

R10

1 2

R497

1 2

R495

1 2

R480

1 2

R496

1 2

R494

1 2

SC 0302

330R2

VVVV

V

VV

V

(Please See M.E. drawing LED position)

LCD POWER

Layout 40 mil

1KR2

LCDVDD_ON_1

12

C40

SC1U10V3KX

12

C42

C42 SCD1U

SCD1U

R50

1 2

D6 LED-G-31D6 LED-G-31

1 2

D5 LED-G-31D5 LED-G-31

1 2

D4 LED-G-31D4 LED-G-31

1 2

D7 LED-G-31D7 LED-G-31

1 2

D24 LED-Y-22D24 LED-Y-22

1 2

D3 LED-G-31D3 LED-G-31

1 2

D50 LED-G-31D50 LED-G-31

1 2

D48 LED-G-31D48 LED-G-31

1 2

D23

LED-B-27-U-GP

D49 LED-Y-22D49 LED-Y-22

1 2

D47 LED-Y-22D47 LED-Y-22

1 2

CAPS NUM HDD

Charger: Green : DC only or Battery full with DC Orange : Charging Orange Blink : Battery low

U13

1

OUT

2

GND ON/OFF#3IN

AAT4280IGU-3-T1

D

GND

IN

5V_S0

5V_S5

SC 0308

5V_S0

12

5V_S5

VVV

6 5 4

Title

Size Document Number Rev

A3

Date: Sheet

SC 0302

on KB Cover on KB Cover on KB Cover on KB Cover

on Front Panel

on KB Cover

on Front Panel

SC 0302

on Front Panel on Front Panel

3D3V_S0LCDPOWER_S0

12

C43

C43 SC1U10V3KX

SC1U10V3KX

LCD / LEDs

Power2: Green : S0 Orange : S3 Orange Blinking : Enter S4

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena

E

-1

17 58Thursday, March 31, 2005

of

-1

A

?3.9p need app PN

PCIE_RX0P_SB12 PCIE_RX0N_SB12 PCIE_RX1P_SB12 PCIE_RX1N_SB12

PCIE_VDDR

RSTDRV#_5 25

SC 0228

SBSRC_CLK3 SBSRC_CLK#3

PCIE_TX0P_SB12 PCIE_TX0N_SB12 PCIE_TX1P_SB12 PCIE_TX1N_SB12

12

C486

DY

SCD1U16V

10

INT_PIRQG#

9

INT_PIRQD#INT_PIRQC#

8

INT_PIRQE#

7

INT_PIRQF#

LPC_RST# 13,34,37

ALLOW_LDTSTOP13 SB_CPUPWRGD6

BMREQ#13 LDT_RST#6,13

CHANGE TO - 3.9P -> 78.3R974.1F1

C579

1 2

SC12P50V2JN-1

4 4

XTAL-32D768K-4P

1D8V_S0

3 3

2 2

A_RST# RSTDRV#_R

A_RST#

12

1 1

SC12P50V2JN-1

X5

2 3

C566

1 2

SC12P50V2JN-1

CHANGE TO - 3.9P -> 78.3R974.1F1

SB

L16

1 2

MLB-201209-11

R367

R367 8K2R2

8K2R2

PCIRST#

12

5V_S0

14

12 11

7

1 2

3D3V_S5

4 5

41

C479

SC10U10V5ZY

13

3D3V_S5

147

R381

R382

20MR3

32K_X1 32K_X2

MAIN SOURCE: 82.30001.031 EPSON

PCIE_PVDD

2ND SOURCE: 82.30001.341 KDS

12

1D8V_S0 PCIE_VDDR

1 2

U2D

TSAHCT125

C480

SC1U10V3KX

L15

0R0603-PAD

SC 0308

INT_PIRQA# INT_PIRQB#

INT_PIRQH#

3D3V_S0

C485

SCD1U16V

12

DY

R13

1 2

C475

SC10U10V5ZY

RP4

1 2 3 4 5 6

SRP10K

33R2

PCIRST# 3V to 5V level shift for HDD & CDROM

SB400 asserts PLTRST# to reset devices on the platform.

U51A

3

TSLCX08-U

U51B

PCI_RST#

6

TSLCX08-U

PLT_RST#_R

R368

1 2

R366

1 2

33R2

10R3

12

Secondary PCI Bus reset signal.

A

B

A_RST#

C478 SCD01U16V2KXC478 SCD01U16V2KX

1 2

C481 SCD01U16V2KXC481 SCD01U16V2KX

1 2

C476 SCD01U16V2KXC476 SCD01U16V2KX

1 2

C477 SCD01U16V2KXC477 SCD01U16V2KX

1 2

R304 150R2FR304 150R2F

1 2

R305 150R2FR305 150R2F

1 2

R303 4K12R2FR303 4K12R2F

1 2

A11, A12 4K53 1% A21, A22 5K5 1% A23 4K12 1% PA_IXP400AC10.PDF

12

C450

3D3V_S0

12

C483

DY

SCD1U16V

TP72TP72 TP71TP71

INT_PIRQE#26 INT_PIRQF#26,31 INT_PIRQG#26 INT_PIRQH#29

TP66TP66 TP64TP64 TP94TP94 TP65TP65 TP68TP68

LDT_STP#6,13

TP67TP67 TP93TP93 TP92TP92

TP91TP91

CHANGE TO 71.SB400.D0U (VER A32)

B

12

PCIRST_BUF# 15,26,28,29,31,57

SC 0307

PCIE_PVDD

C482

SCD1U16V

12

PCIE_CALRP PCIE_CALRN

PCIE_CALI

SB_CPUSTP#

SB_PCISTP# INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#

INT_PIRQE#

INT_PIRQF#

INT_PIRQG#

INT_PIRQH#

SB_C29 SB_A28 H_NMI FWH_INIT# SB_D29

SB_B30

H_A20M# H_FERR#

H_DPRSLP#

R365

R365 8K2R2

8K2R2

TX0P TX0N TX1P TX1N

32K_X1

32K_X2

U43A

AH8

A_RST#

L27

PCIE_RCLKP

M27

PCIE_RCLKN

M30

PCIE_TX0P

N30

PCIE_TX0N

K30

PCIE_TX1P

L30

PCIE_TX1N

H30

PCIE_TX2P

J30

PCIE_TX2N

F30

PCIE_TX3P

G30

PCIE_TX3N

M29

PCIE_RX0P

N29

PCIE_RX0N

M28

PCIE_RX1P

N28

PCIE_RX1N

J29

PCIE_RX2P

K29

PCIE_RX2N

J28

PCIE_RX3P

K28

PCIE_RX3N

G27

PCIE_CALRP

H27

PCIE_CALRN

G28

PCIE_CALI

R30

PCIE_PVDD

F26

PCIE_VDDR_1

R29

PCIE_VDDR_2

G26

PCIE_VDDR_3

P26

PCIE_VDDR_4

K26

PCIE_VDDR_5

L26

PCIE_VDDR_6

P28

PCIE_VDDR_7

N26

PCIE_VDDR_8

P27

PCIE_VDDR_9

H28

PCIE_VSS_1

F29

PCIE_VSS_2

H29

PCIE_VSS_3

H26

PCIE_VSS_4

F27

PCIE_VSS_5

G29

PCIE_VSS_6

L29

PCIE_VSS_7

J26

PCIE_VSS_8

L28

PCIE_VSS_9

J27

PCIE_VSS_10

N27

PCIE_VSS_11

M26

PCIE_VSS_12

K27

PCIE_VSS_13

P29

PCIE_VSS_14

P30

PCIE_VSS_15

AJ8

CPU_STP#/DPSLP#

AK7

PCI_STP#

AG5

INTA#

AH5

INTB#

AJ5

INTC#

AH6

INTD#

AJ6

INTE#/GPIO33

AK6

INTF#/GPIO34

AG7

INTG#/GPIO35

AH7

INTH#/GPIO36

B2

X1

B1

X2

C29

CPU_PG

A28

INTR/LINT0

C28

NMI/LINT1

B29

INIT#

D29

SMI#

E4

SLP#/LDT_STP#

B30

IGNNE#

F28

A20M#

E28

FERR#

E29

STPCLK#/ALLOW_LDTSTP

D25

LDT_PG/SSMUXSEL/GPIO0

E27

DPRSLPVR

D27

BMREQ#

D28

LDT_RST#

SB400-1

5

C

SB400 SB

Part 1 of 4

PCI EXPRESS INTERFACE

PCI INTERFACE

REQ4#/PLL_BP33/PDMA_REQ1#

GNT3#/PLL_BP66/PDMA_GNT0# GNT4#/PLL_BP50/PDMA_GNT1#

LPC

CPU XTAL

RTC_IRQ#/ACPWR_STRAP

RTC

RTC_AUX_S5_1

123

4

RTC2

SCON3

21.D0010.103

C

PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5 PCICLK6 PCICLK7 PCICLK8 PCICLK9

PCICLK_FB

PCI CLKS

PCIRST# AD0/ROMA18 AD1/ROMA17 AD2/ROMA16 AD3/ROMA15 AD4/ROMA14 AD5/ROMA13 AD6/ROMA12 AD7/ROMA11

AD8/ROMA9

AD9/ROMA8 AD10/ROMA7 AD11/ROMA6 AD12/ROMA5 AD13/ROMA4 AD14/ROMA3 AD15/ROMA2 AD16/ROMD0 AD17/ROMD1 AD18/ROMD2 AD19/ROMD3 AD20/ROMD4 AD21/ROMD5 AD22/ROMD6 AD23/ROMD7

AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

CBE0#/ROMA10

CBE1#/ROMA1

CBE2#/ROMWE#

CBE3#

FRAME#

DEVSEL#/ROMA0

IRDY#

TRDY#/ROMOE#

PAR/ROMA19

STOP# PERR# SERR#

REQ0#

REQ1#

REQ5#/GPIO13 REQ6#/GPIO31

GNT5#/GPIO14 GNT6#/GPIO32

CLKRUN#

LFRAME#

LDRQ0# LDRQ1#

SERIRQ

RTCCLK

RTC_GND

EC91

EC91 SC470P50V2KX

SC470P50V2KX

REQ2#

GNT0#

GNT1#

GNT2#

LOCK#

LAD0 LAD1 LAD2 LAD3

VBAT

SC 0310

REQ3#/PDMA_REQ0#

12

L4 L3 L2 L1 M4 M3 M2 M1 N4 N3 N2

AJ7 W3 Y2 W4 Y3 V1 Y4 V2 W2 AA4 V4 AA3 U1 AA2 U2 AA1 U3 T4 AC1 R2 AD4 R3 AD3 R4 AD2 P2 AE3 P3 AE2 P4 AF2 N1 AF1 V3 AB4 AC2 AE4 T3 AC4 AC3 T2 U4 T1 AB2 AB3 AF4 AF3 AG2 AG3 AH1 AH2 AH3 AJ2 AK2 AJ3 AK3 AG4 AH4 AJ4 AG1 AB1

AG25 AH25 AJ25 AH24 AG24 AH26 AG26

AK27

C2 F3

A2 A1

PCI_CLK1_R PCI_CLK2_R PCI_CLK3_R PCI_CLK4_R PCI_CLK5_R PCI_CLK6_R

PCI_CLK9_R PCI_CLK9_FB

PCIRST# PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31

PCI_REQ#4

PCI_REQ#5 PCI_REQ#6

PCI_GNT#3 PCI_GNT#4 PCI_GNT#5 PCI_GNT#6

PCI_LOCK#

LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3

LPC_LDRQ1#

VBAT

12

C565

1 2

22R2

1 2

22R2

1 2

22R2

1 2

22R2

1 2

22R2

1 2

PCI_REQ#3

TP105TP105 TP104TP104 TP106TP106 TP107TP107

P_SERIRQ 26,34,37

RTC_CLK 22 AUTO_ON# 22

12

C561

SC1U10V3KX

RTC_AUX_S5

SCD1U16V

D

32K suspend clock output

PM_SLP_S3#21,34,38,39,43,44,55,57 RTC_CLK22

CLK33_CBUS

R40022R2 R40022R2

CLK33_LAN

R397

CLK33_MINI

R396

CLK33_KBC

R402

CLK33_SIO

R401

CLK33_LPCROM

R398

R399

22R2

1 2

PCI_AD[31..0] 22,26,29,31

12

C591

C591 DUMMY-C2

DUMMY-C2

3D3V_S0

RN78

123

SRN10K-2

LPC_LAD[0..3] 34,37

LPC_LFRAME# 34,37 LPC_LDRQ0# 37

3D3V_AUX_S5

3

1 2

D

RN80

678

4 5

123

SRN10K-2

Close to chip

U47

U47 BAT54C-U

BAT54C-U

5V_S5

U44A

147

1 2

PCI_CLK7 22 PCI_CLK8 22

C588

C588 SC100P50V2JN

SC100P50V2JN

DY

12

C585

C585 DUMMY-C2

DUMMY-C2

RN77

678

123

4 5

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet of

4 5

SRN10K-2

PM_CLKRUN# 26,29,31,34,37

RTC_AUX_S5

R362

R362 1KR2

1KR2

1 2

RTC_AUX_S5_1

123

5

RTC1 SCON3

ME : 21.D0010.103

21.D0010.103

ATI-SB400 (1 of 5) PCI, PCIE

3

TSAHCT08-U

CLK33_CBUS CLK33_LAN CLK33_MINI CLK33_KBC CLK33_SIO CLK33_LPCROM

12

C584

C593

DUMMY-C2

RN79

678

R4038K2R2 R4038K2R2

12

123

4 5

SRN10K-2

DY

12

EC61

EC61 SC470P50V2KX

SC470P50V2KX

SC 0308

4

DY

SC 0310

Bolsena -1

E

R349

1 2

10R3

CLK33_CBUS 26 CLK33_LAN 22,29 CLK33_MINI 22,31 CLK33_KBC 22,34 CLK33_SIO 22,37 CLK33_LPCROM 22

12

C592

C587

DUMMY-C2

RN74

LPC_LAD0 LPC_LAD3 LPC_LAD2 LPC_LAD1

RN74

1 2 3 4 5

SRN10K-2

PCI_CBE#0 26,29,31

PCI_CBE#1 26,29,31

PCI_CBE#2 26,29,31

PCI_CBE#3 26,29,31

PCI_FRAME# 26,29,31

PCI_DEVSEL# 26,29,31

PCI_IRDY# 26,29,31

PCI_TRDY# 26,29,31

PCI_PAR 26,29,31

PCI_STOP# 26,29,31

PCI_PERR# 26,29,31

PCI_SERR# 26,29,31

PCI_REQ#0 31 PCI_REQ#1 26 PCI_REQ#2 29

PCI_GNT#0 31 PCI_GNT#1 26 PCI_GNT#2 29

SC 0310

8 7 6

Pull up 100k to 3D3V_S0

P_SERIRQ LPC_LDRQ1# LPC_LDRQ0#

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

E

1 2 1 2 1 2

18 58Thursday, March 31, 2005

R326

R326 R306

R306 R327

R327

of

CLK32_G791 23

3D3V_S0

10KR2

10KR2 10KR2

10KR2