Acer Aspire 3100, Aspire 5100, Aspire 5110 Schematics
A
1 1
B
C
D
E
2 2
Compal Confidential
HCW51 Schematics Document
AMD/Sempron/ATI RS485MC/SB460
2006 / 04 / 27 FOR MP
3 3
4 4
Rev:1.0
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/05/09 2006/03/08
C
Compal Secret Data
Deciphered Date
Compal Electronics, inc.
Title
SCHEMATIC, M/B LA-3121P
Size Document Number Rev
Custom
401411
Date: Sheet
星期一
08, 2006
D
五月
151,
E
D
of
5
4
3
2
1
Compal confidential
Project Code: HCW51
File Name : LA-3121P
D D
Thermal Sensor
ADM1032ARM
page 8 page 17
Clock Generator
ICS951462
AMD Turion/Sempron CPU
Socket S1 638P
H_A#(3..31)
page 6,7,8,9
DDRII DDRII-SO-DIMM X2
Dual Channel
H_D#(0..63)
HT 16x16 800MHZ
533/667
page 10,11
CRT & TV-OUT
page 24
LCD CONN
page 25
ATI-RS485MC
465 BGA
page 12,13,14,15,16
A-Link Express
2 x PCIE
C C
USB 2.0
PCI BUS
ATI-SB460
549 BGA
AC-LINK
USB 2.0
Mini PCI Socket
Mini card RTL8110SCL
page 31
Realtek
RTL8100CL
page 26
ENE Controller
CB714
page 32
1394 Controller
VT6311S
page 35
page 18,19,20,21,22
SATA
B B
page 27
RJ45 CONN
Slot 0
page 33
6in1 CardReader
Slot
page 33
1394
Conn.
page 35
LPC BUS
PATA
One Channel
USB conn x 2 / New card
BT Conn
page 38
Audio CKT
ALC883
page 39
MDC Conn.
page 41
page 34
AMP & Audio Jack
SATA HDD Conn.
page 23
HDD Conn.
page 40
CDROM Conn.
page 23
Power On/Off C KT / LID switch / Power OK CKT
DC/DC Interface CKT.
page 41
CIR/LED
page 38
page 37
RTC CKT.
page 18
SMsC LPC47N207
page 36
ENE KB910
page 28
Power Circuit DC/DC
page 42~48
A A
5
4
FIR module
page 36
Security Classification
Issued Date
THIS SHEET OF ENG INEE RIN G DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY O R DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
Touch Pad
CONN.
2005/05/09 2006/03/08
page 29
Compal Secret Data
Deciphered Date
Int. KBD
page 29
BIOS
page 30
2
Compal Electronics, inc.
Title
SCHEMATIC, M/B LA-3121P
Size Document Number R ev
Custom
401411
Date: Sheet
星期一 五
08, 2006
月
251,
1
of
D
5
Voltage Rails
Power Plane Description
D D
C C
VIN
B+
+CPU_CORE
+0.9V 0.9V switched power rail for DDR terminator
+1.2VS
+1.5VS
+1.8VALW 1.8V always on power rail O N ON ON*
+1.8V 1.8V power rail for DDR
+1.8VS 1.8V switched power rail
+2.5VS
+3VALW
+3VS
+5VALW
+5VS
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
1.05V switched power rail
1.5V switched power rail
2.5V switched power rail
3.3V always on power rail
3.3V switched power rail
5V always on power rail
5V switched power rail
4
S1 S3 S5
N/A N/A N/A
ON OFF
ON ON
ON OFF OFF
ON OFF OFF
ON
ON OFF
ON
ON
ON
ON
ON OFF
ON
ON+RTCVCC
ON
OFF
OFF
ON
OFF
ON
OFF
ONRTC power
N/AN/AN/A
OFF
OFF
OFF
OFF
ON*
OFF
ON*
ON*ONVSB always on power rail+VSB
ON
3
SIGNAL
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
SLP_S1# SLP_S3#
HIGH HIGH HIGH
LOW
LOW
LOW LOW LOW LOW
SLP_S4# SLP_S5# +VA LW +V +VS Clock
HIGH
LOW
Board ID / SKU ID Table for AD channel
Vcc 3.3V +/- 5%
Board ID
0
1
2
3
4
5
6
7 NC
100K +/- 5%Ra/Rc/Re
Rb / Rd / Rf V min
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
AD_BID
0 V
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
2
LOWLOWLOW
ON
HIGH
HIGHHIGHHIGH
HIGH
HIGH
ON
ON
ON
ON
ON
V typ
AD_BID
ON
ON
OFF
OFF
V
AD_BID
0 V 0 V
0.503 V
0.819 V
1.185 V 1.264 V
2.200 V
3.300 V
ON ON
ON
OFF
OFF
OFF
max
0.538 V
0.875 V
2.341 V
3.300 V
1
LOW
OFF
OFF
OFF
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
External PCI Devices
Device IDSEL# REQ#/GNT# Interrupts
CardBus(SD)
1394
LAN(10/100)
Mini-PCI(WLAN/TV-Tuner)
B B
EC SM Bus1 address
Device
Smart Battery
EEPROM(24C16/02)
(24C04)
AD20
AD16 0
AD17
AD18
2
3
1
PIRQE/PIRQH
PIRQE
PIRQF
PIRQG/PORQH
EC SM Bus2 address
Address Address
1010 000X b
1011 000X b
Device
ADM1032
1001 100X b0001 011X b
SB460 SM Bus address
Device
Clock Generator
A A
(ICS951462)
DDR DIMM0
DDR DIMM2
5
Address
1101 001Xb
1001 000Xb
1001 001Xb
Security Classification
Issued Date
THIS SHEET OF ENG INEE RIN G DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY O R DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BOARD ID Table
Board ID
0
1
2
3
4
5
6
7
SKU ID Table
SKU ID
0
1
2
3
4
5
6
7
2005/05/09 2006/03/08
3
PCB Revision
UMA
DISCRETE
SKU
W / O SATA
WITH SATA
Compal Secret Data
Deciphered Date
BTO Option Table
BTO Item BOM Structure
WITH TV-OUT
WITH FIR
WITH CARD READER
WITH 1394
WITH EXPRESS CARD EXPRESS@
WITH CIR CIR@
WITH LAN(10/100)
WITH GIGA LAN(8110SBL)
WITH GIGA LAN(8110SCL)
WITH PATA HDD
WITH SATA HDD
WITH BLUETOOTH
WITH USBx2
WITH LPC47N207
WITH SIO1036
WITH SIO BOTH
WITH SSC
W/O SSC
Compal Electronics inc
Title
SCHEMATIC, M/B LA-3121P
Size Document Number R ev
Custom
401411
Date: Sheet
星期一 五
08, 2006
2
月
TV@
FIR@
61@
1394@
100@
GIGA@WITH LAN(10/100/1000)
8110SB@
8110SC@
PATA@
SATA@
BT@
USB2@
SIO1@
SIO2@
SIOALL@
SPREAD@
NOSPREAD@
45@DIP CAP
351,
1
D
of
5
D D
4
3
2
1
PCI CLK0
33MHZ
PCI CLK1
33MHZ
HTREFCLK
66MHZ
NB-OSC
C C
B B
NEAR SO-DIMM REV SO-DIMM
2 PAIR MEM CLK
2 PAIR MEM CLK
ATHLON64 S1 CPU
LGA638 PACKAGE
1 PAIR CP U CLK
200MHZ
EXTERNAL
CLK GEN.
14.318MHZ
NB PCIE CLK
100MHZ
SB PCIE CLK
100MHZ
SB-OSCIN
14.318MHZ
PCIE CLK
100MHZ
PCIE CLK
100MHZ
SD CLK
48MHZ
SIO CLK
14.318MHZ
ATI NB - RS485MC
SB-OSCIN
14.318MHZ
PCI EXPRESS CARD - 1 LANE
MINI CARD - 1 LANE
SB-OSCIN
14.318MHZ
PCIE CLK
100MHZ
USB CLK
48MHZ
ATI SB
SB460
AZALIA_BITCLK
PCI CLK5
33MHZ
SIO CLK
14.318MHZ
25M Hz
PCI CLK2
33MHZ
PCI CLK3
33MHZ
SD CLK
48MHZ
PCI CLK4
33MHZ
LAN RTL8100CL
EC-CB714
MINI PCI SLOT
Cardbus
CB714
1394
VT6311S
SUPER IO
AZALIA CODEC
TP_CLK
TOUCH PAD
32.768K Hz
14.31818MHz
A A
Security Classification
Issued Date
THIS SHEET OF ENG INEE RIN G DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY O R DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/05/09 2006/10/10
Compal Secret Data
Deciphered Date
Compal Electronics inc
Title
SCHEMATIC, M/B LA-3121P
Size Document Number R ev
Custom
401411
Date: Sheet
星期一 五
08, 2006
2
月
451,
1
D
of
5
D D
C C
4
3
2
1
B B
A A
Security Classification
Issued Date
THIS SHEET OF ENG INEE RIN G DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY O R DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/05/09 2006/10/10
Compal Secret Data
Deciphered Date
Title
Size Document Number R ev
2
Date: Sheet
Compal Electronics inc
SCHEMATIC, M/B LA-3121P
401411
星期一 五
08, 2006
月
1
551,
DCustom
of
5
4
3
2
1
PROCESSOR HYPERTRANSPORT INTERFACE
D D
H_CADIP15(12) H_CADOP15 (12)
H_CADIN15(12)
H_CADIP14(12)
H_CADIN14(12)
H_CADIP13(12)
H_CADIN13(12)
H_CADIP12(12)
H_CADIN12(12)
H_CADIP11(12)
H_CADIN11(12)
H_CADIP10(12)
H_CADIN10(12)
H_CADIP9(12)
H_CADIN9(12)
H_CADIP8(12)
C C
+1.2V_HT
B B
H_CADIN8(12)
H_CADIP7(12)
H_CADIN7(12)
H_CADIP6(12)
H_CADIN6(12)
H_CADIP5(12)
H_CADIN5(12)
H_CADIP4(12)
H_CADIN4(12)
H_CADIP3(12)
H_CADIN3(12)
H_CADIP2(12)
H_CADIN2(12)
H_CADIP1(12)
H_CADIN1(12)
H_CADIP0(12)
H_CADIN0(12)
H_CLKIP1(12)
H_CLKIN1(12)
H_CLKIP0(12)
H_CLKIN0(12)
R38 51_0402_1%
1 2
R37 51_0402_1%
1 2
H_CTLIP0(12)
H_CTLIN0(12)
VLDT_A x AND VLDT _B x ARE CONNEC T E D TO T HE LDT_RUN POWER
SUPPLY THRO UGH T HE PA CKA GE OR ON T HE DIE. IT IS ONLY CONNECTED
ON THE BOA RD T O DEC OUPLING NEA R THE CPU PACKA GE
+1.2V_HT
JP23A
H_CADIP15
H_CADIP14
H_CADIN14
H_CADIP13
H_CADIN13
H_CADIP12
H_CADIN12
H_CADIP11
H_CADIN11
H_CADIP10
H_CADIN10
H_CADIP9
H_CADIN9
H_CADIP8
H_CADIN8
H_CADIP7
H_CADIN7
H_CADIP6
H_CADIN6
H_CADIP5
H_CADIN5
H_CADIP4
H_CADIN4
H_CADIP3
H_CADIN3
H_CADIP2
H_CADIN2
H_CADIP1
H_CADIN1
H_CADIP0
H_CADIN0
H_CLKIP1
H_CLKIN1
H_CLKIP0
H_CLKIN0
H_CTLIP1
H_CTLIN1
H_CTLIP0
H_CTLIN0
D4
VLDT_A3
D3
VLDT_A2
D2
VLDT_A1
D1
VLDT_A0
N5
L0_CADIN_H15
P5
L0_CADIN_L15
M3
L0_CADIN_H14
M4
L0_CADIN_L14
L5
L0_CADIN_H13
M5
L0_CADIN_L13
K3
L0_CADIN_H12
K4
L0_CADIN_L12
H3
L0_CADIN_H11
H4
L0_CADIN_L11
G5
L0_CADIN_H10
H5
L0_CADIN_L10
F3
L0_CADIN_H9
F4
L0_CADIN_L9
E5
L0_CADIN_H8
F5
L0_CADIN_L8
N3
L0_CADIN_H7
N2
L0_CADIN_L7
L1
L0_CADIN_H6
M1
L0_CADIN_L6
L3
L0_CADIN_H5
L2
L0_CADIN_L5
J1
L0_CADIN_H4
K1
L0_CADIN_L4
G1
L0_CADIN_H3
H1
L0_CADIN_L3
G3
L0_CADIN_H2
G2
L0_CADIN_L2
E1
L0_CADIN_H1
F1
L0_CADIN_L1
E3
L0_CADIN_H0
E2
L0_CADIN_L0
J5
L0_CLKIN_H1
K5
L0_CLKIN_L1
J3
L0_CLKIN_H0
J2
L0_CLKIN_L0
P3
L0_CTLIN_H1
P4
L0_CTLIN_L1
N1
L0_CTLIN_H0
P1
L0_CTLIN_L0
FOX_PZ63823-284S-41F
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
HTT Interface
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
Athlon 64 S1
Processor Socket
VLDT_B3
VLDT_B2
VLDT_B1
VLDT_B0
AE5
AE4
AE3
AE2
T4
T3
V5
U5
V4
V3
Y5
W5
AB5
AA5
AB4
AB3
AD5
AC5
AD4
AD3
T1
R1
U2
U3
V1
U1
W2
W3
AA2
AA3
AB1
AA1
AC2
AC3
AD1
AC1
Y4
Y3
Y1
W1
T5
R5
R2
R3
1 2
H_CADOP15
H_CADON15H_CADIN15
H_CADOP14
H_CADON14
H_CADOP13
H_CADON13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADOP10
H_CADON10
H_CADOP9
H_CADON9
H_CADOP8
H_CADON8
H_CADOP7
H_CADON7
H_CADOP6
H_CADON6
H_CADOP5
H_CADON5
H_CADOP4
H_CADON4
H_CADOP3
H_CADON3
H_CADOP2
H_CADON2
H_CADOP1
H_CADON1
H_CADOP0
H_CADON0
H_CLKOP1
H_CLKON1
H_CLKOP0
H_CLKON0
H_CTLOP0
H_CTLON0
C455
4.7U_0805_10V4Z
H_CADON15 (12)
H_CADOP14 (12)
H_CADON14 (12)
H_CADOP13 (12)
H_CADON13 (12)
H_CADOP12 (12)
H_CADON12 (12)
H_CADOP11 (12)
H_CADON11 (12)
H_CADOP10 (12)
H_CADON10 (12)
H_CADOP9 (12)
H_CADON9 (12)
H_CADOP8 (12)
H_CADON8 (12)
H_CADOP7 (12)
H_CADON7 (12)
H_CADOP6 (12)
H_CADON6 (12)
H_CADOP5 (12)
H_CADON5 (12)
H_CADOP4 (12)
H_CADON4 (12)
H_CADOP3 (12)
H_CADON3 (12)
H_CADOP2 (12)
H_CADON2 (12)
H_CADOP1 (12)
H_CADON1 (12)
H_CADOP0 (12)
H_CADON0 (12)
H_CLKOP1 (12)
H_CLKON1 (12)
H_CLKOP0 (12)
H_CLKON0 (12)
H_CTLOP0 (12)
H_CTLON0 (12)
EN_DFAN1(28)
+5VS
+VCC_FAN1
EN_DFAN1
1
C47
10U_0805_10V4Z
2
U1
1
VEN
2
VIN
3
VO
4
VSET
G993P1U_SOP8L
FAN_SPEED1(28)
FAN Conn
8
GND
7
GND
6
GND
5
GND
+3VS
12
R34
10K_0402_5%
+5VS
12
12
D3
CH355PT_SOD323
FAN1
D4
1N4148_SOT23
1
C92
1000P_0402_50V7K
2
W=40mils
+VCC_FAN1
1 2
C83 10U_0805_10V4Z
1 2
C90 1000P_0402_50V7K
JP20
1
1
2
2
3
3
4
GND
5
GND
ACES_85205-03001
+1.2V_HT
1
C164
2
4.7U_0805_10V4Z
LAYOUT: Place bypass cap on topside of board
A A
5
1
C156
2
4.7U_0805_10V4Z
NEAR HT POWER PINS T HA T A RE NOT CONNECTED DIRECTLY
TO DOWNSTREAM HT DEVICE, BUT CONNECTED INTERNA LLY
TO OTHER HT POWER PINS
PLACE CLOSE TO VLDT0 POWER PINS
C158
0.22U_0402_10V4Z
1
2
1
C163
2
0.22U_0402_10V4Z
C145
180P_0402_50V8J
1
2
1
2
4
C152
180P_0402_50V8J
Security Classification
Issued Date
THIS SHEET OF ENG INEE RIN G DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY O R DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/05/09 2006/10/11
Compal Secret Data
Deciphered Date
2
Compal Electronics inc
Title
SCHEMATIC, M/B LA-3121P
Size Document Number R ev
Custom
401411
Date: Sheet
星期一 五
08, 2006
月
651,
1
of
D
A
B
C
D
E
VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER
SUPPLY THROUGH TH E P ACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE
+1.8V
4 4
3 3
2 2
12
R13
39.2_0402_1%~D
R22
12
39.2_0402_1%~D
PLACE THEM CLOSE TO
CPU WITHIN 1"
DDR_CS3_DIMMA#(10)
DDR_CS2_DIMMA#(10)
DDR_CS1_DIMMA#(10)
DDR_CS0_DIMMA#(10)
DDR_CS3_DIMMB#(11)
DDR_CS2_DIMMB#(11)
DDR_CS1_DIMMB#(11)
DDR_CS0_DIMMB#(11)
DDR_CKE1_DIMMB(11)
DDR_CKE0_DIMMB(11)
DDR_CKE1_DIMMA(10)
DDR_CKE0_DIMMA(10)
DDR_A_MA[15..0](10)
DDR_A_BS#2(10)
DDR_A_BS#1(10)
DDR_A_BS#0(10)
DDR_A_RAS#(10)
DDR_A_CAS#(10)
DDR_A_WE#(10)
DDR_A_CLK2
DDR_A_CLK#2
DDR_A_CLK1
DDR_A_CLK#1
PLACE CLOSE TO PRO CESSOR
WITHIN 1.2 INCH
+0.9VREF_CPU
TP3PAD
M_ZN
M_ZP
10:8:10:8:10
DDR_CS3_DIMMA#
DDR_CS2_DIMMA#
DDR_CS1_DIMMA#
DDR_CS0_DIMMA#
DDR_CS3_DIMMB#
DDR_CS2_DIMMB#
DDR_CS1_DIMMB#
DDR_CS0_DIMMB#
DDR_CKE1_DIMMB
DDR_CKE0_DIMMB
DDR_CKE1_DIMMA
DDR_CKE0_DIMMA
DDR_A_MA15
DDR_A_MA14
DDR_A_MA13
DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0
DDR_A_BS#2
DDR_A_BS#1
DDR_A_BS#0
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
1
C66
1.5P_0402_50V8C
2
1
C132
1.5P_0402_50V8C
2
VTT_SENSE
JP23B
W17
M_VREF
Y10
VTT_SENSE
AE10
M_ZN
AF10
M_ZP
V19
MA0_CS_L3
J22
MA0_CS_L2
V22
MA0_CS_L1
T19
MA0_CS_L0
Y26
MB0_CS_L3
J24
MB0_CS_L2
W24
MB0_CS_L1
U23
MB0_CS_L0
H26
MB_CKE1
J23
MB_CKE0
J20
MA_CKE1
J21
MA_CKE0
K19
MA_ADD15
K20
MA_ADD14
V24
MA_ADD13
K24
MA_ADD12
L20
MA_ADD11
R19
MA_ADD10
L19
MA_ADD9
L22
MA_ADD8
L21
MA_ADD7
M19
MA_ADD6
M20
MA_ADD5
M24
MA_ADD4
M22
MA_ADD3
N22
MA_ADD2
N21
MA_ADD1
R21
MA_ADD0
K22
MA_BANK2
R20
MA_BANK1
T22
MA_BANK0
T20
MA_RAS_L
U20
MA_CAS_L
U21
MA_WE_L
FOX_PZ63823-284S-41F
Athlon 64 S1
Processor
Socket
D10
VTT1
C10
VTT2
B10
VTT3
AD10
VTT4
W10
VTT5
AC10
VTT6
AB10
VTT7
AA10
VTT8
A10
VTT9
Y16
MA0_CLK_H2
AA16
MA0_CLK_L2
E16
MA0_CLK_H1
F16
MA0_CLK_L1
AF18
MB0_CLK_H2
AF17
MB0_CLK_L2
A17
MB0_CLK_H1
A18
MB0_CLK_L1
W23
MB0_ODT1
W26
MB0_ODT0
V20
MA0_ODT1
U19
MA0_ODT0
J25
MB_ADD15
J26
MB_ADD14
W25
MB_ADD13
L23
MB_ADD12
L25
MB_ADD11
U25
MB_ADD10
L24
MB_ADD9
M26
MB_ADD8
DDRII Cmd/Ctrl//Clk
L26
MB_ADD7
N23
MB_ADD6
N24
MB_ADD5
N25
MB_ADD4
N26
MB_ADD3
P24
MB_ADD2
P26
MB_ADD1
T24
MB_ADD0
K26
MB_BANK2
T26
MB_BANK1
U26
MB_BANK0
U24
MB_RAS_L
V26
MB_CAS_L
U22
MB_WE_L
DDR_B_CLK2
DDR_B_CLK#2
DDR_B_CLK1
DDR_B_CLK#1
PLACE CLOSE TO PRO CESSOR
WITHIN 1.2 INCH
+0.9V
DDR_A_CLK2
DDR_A_CLK#2
DDR_A_CLK1
DDR_A_CLK#1
DDR_B_CLK2
DDR_B_CLK#2
DDR_B_CLK1
DDR_B_CLK#1
DDR_B_ODT1
DDR_B_ODT0
DDR_A_ODT1
DDR_A_ODT0
DDR_B_MA15
DDR_B_MA14
DDR_B_MA13
DDR_B_MA12
DDR_B_MA11
DDR_B_MA10
DDR_B_MA9
DDR_B_MA8
DDR_B_MA7
DDR_B_MA6
DDR_B_MA5
DDR_B_MA4
DDR_B_MA3
DDR_B_MA2
DDR_B_MA1
DDR_B_MA0
DDR_B_BS#2
DDR_B_BS#1
DDR_B_BS#0
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
1
2
1
2
C35
1.5P_0402_50V8C
C173
1.5P_0402_50V8C
DDR_A_CLK2 (10)
DDR_A_CLK#2 (10)
DDR_A_CLK1 (10)
DDR_A_CLK#1 (10)
DDR_B_CLK2 (11)
DDR_B_CLK#2 (11)
DDR_B_CLK1 (11)
DDR_B_CLK#1 (11)
DDR_B_ODT1 (11)
DDR_B_ODT0 (11)
DDR_A_ODT1 (10)
DDR_A_ODT0 (10)
DDR_B_ MA[15..0] (11)
DDR_B_BS# 2 (11)
DDR_B_BS# 1 (11)
DDR_B_BS# 0 (11)
DDR_B_RAS# (11)
DDR_B_CAS# (11)
DDR_B_W E# (11)
DDR_B_D[63..0](11)
Processor DDR2 Memory Interface
DDR_B_D63
DDR_B_D62
DDR_B_D61
DDR_B_D60
DDR_B_D59
DDR_B_D58
DDR_B_D57
DDR_B_D56
DDR_B_D55
DDR_B_D54
DDR_B_D53
DDR_B_D52
DDR_B_D51
DDR_B_D50
DDR_B_D49
DDR_B_D48
DDR_B_D47
DDR_B_D46
DDR_B_D45
DDR_B_D44
DDR_B_D43
DDR_B_D42
DDR_B_D41
DDR_B_D40
DDR_B_D39
DDR_B_D38
DDR_B_D37
DDR_B_D36
DDR_B_D35
DDR_B_D34
DDR_B_D33
DDR_B_D32
DDR_B_D31
DDR_B_D30
DDR_B_D29
DDR_B_D28
DDR_B_D27
DDR_B_D26
DDR_B_D25
DDR_B_D24
DDR_B_D23
DDR_B_D22
DDR_B_D21
DDR_B_D20
DDR_B_D19
DDR_B_D18
DDR_B_D17
DDR_B_D16
DDR_B_D15
DDR_B_D14
DDR_B_D13
DDR_B_D12
DDR_B_D11
DDR_B_D10
DDR_B_D9
DDR_B_D8
DDR_B_D7
DDR_B_D6
To reverse SODIMM socket
DDR_B_DM[7..0](11) DDR_A_ DM[7..0] (10)
DDR_B_DQS7(11)
DDR_B_DQS#7(11)
DDR_B_DQS6(11)
DDR_B_DQS#6(11)
DDR_B_DQS5(11)
DDR_B_DQS#5(11)
DDR_B_DQS4(11)
DDR_B_DQS#4(11)
DDR_B_DQS3(11)
DDR_B_DQS#3(11)
DDR_B_DQS2(11)
DDR_B_DQS#2(11)
DDR_B_DQS1(11)
DDR_B_DQS#1(11)
DDR_B_DQS0(11)
DDR_B_DQS#0(11)
DDR_B_D5
DDR_B_D4
DDR_B_D3
DDR_B_D2
DDR_B_D1
DDR_B_D0
DDR_B_DM7
DDR_B_DM6
DDR_B_DM5
DDR_B_DM4
DDR_B_DM3
DDR_B_DM2
DDR_B_DM1
DDR_B_DM0
DDR_B_DQS7
DDR_B_DQS#7
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS0
DDR_B_DQS#0
JP23C
AD11
MB_DATA63
AF11
MB_DATA62
AF14
MB_DATA61
AE14
MB_DATA60
Y11
MB_DATA59
AB11
MB_DATA58
AC12
MB_DATA57
AF13
MB_DATA56
AF15
MB_DATA55
AF16
MB_DATA54
AC18
MB_DATA53
AF19
MB_DATA52
AD14
MB_DATA51
AC14
MB_DATA50
AE18
MB_DATA49
AD18
MB_DATA48
AD20
MB_DATA47
AC20
MB_DATA46
AF23
MB_DATA45
AF24
MB_DATA44
AF20
MB_DATA43
AE20
MB_DATA42
AD22
MB_DATA41
AC22
MB_DATA40
AE25
MB_DATA39
AD26
MB_DATA38
AA25
MB_DATA37
AA26
MB_DATA36
AE24
MB_DATA35
AD24
MB_DATA34
AA23
MB_DATA33
AA24
MB_DATA32
G24
MB_DATA31
G23
MB_DATA30
D26
MB_DATA29
C26
MB_DATA28
G26
MB_DATA27
G25
MB_DATA26
E24
MB_DATA25
E23
MB_DATA24
C24
MB_DATA23
B24
MB_DATA22
C20
MB_DATA21
B20
MB_DATA20
C25
MB_DATA19
D24
MB_DATA18
A21
MB_DATA17
D20
MB_DATA16
D18
MB_DATA15
C18
MB_DATA14
D14
MB_DATA13
C14
MB_DATA12
A20
MB_DATA11
A19
MB_DATA10
A16
MB_DATA9
A15
MB_DATA8
A13
MB_DATA7
D12
MB_DATA6
E11
MB_DATA5
G11
MB_DATA4
B14
MB_DATA3
A14
MB_DATA2
A11
MB_DATA1
C11
MB_DATA0
AD12
MB_DM7
AC16
MB_DM6
AE22
MB_DM5
AB26
MB_DM4
E25
MB_DM3
A22
MB_DM2
B16
MB_DM1
A12
MB_DM0
AF12
MB_DQS_H7
AE12
MB_DQS_L7
AE16
MB_DQS_H6
AD16
MB_DQS_L6
AF21
MB_DQS_H5
AF22
MB_DQS_L5
AC25
MB_DQS_H4
AC26
MB_DQS_L4
F26
MB_DQS_H3
E26
MB_DQS_L3
A24
MB_DQS_H2
A23
MB_DQS_L2
D16
MB_DQS_H1
C16
MB_DQS_L1
C12
MB_DQS_H0
B12
MB_DQS_L0
FOX_PZ63823-284S-41F
DDRII Data
Athlon 64 S1
Processor Socket
MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14
MA_DATA13
MA_DATA12
MA_DATA11
MA_DATA10
MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0
MA_DM7
MA_DM6
MA_DM5
MA_DM4
MA_DM3
MA_DM2
MA_DM1
MA_DM0
MA_DQS_H7
MA_DQS_L7
MA_DQS_H6
MA_DQS_L6
MA_DQS_H5
MA_DQS_L5
MA_DQS_H4
MA_DQS_L4
MA_DQS_H3
MA_DQS_L3
MA_DQS_H2
MA_DQS_L2
MA_DQS_H1
MA_DQS_L1
MA_DQS_H0
MA_DQS_L0
AA12
AB12
AA14
AB14
W11
Y12
AD13
AB13
AD15
AB15
AB17
Y17
Y14
W14
W16
AD17
Y18
AD19
AD21
AB21
AB18
AA18
AA20
Y20
AA22
Y22
W21
W22
AA21
AB22
AB24
Y24
H22
H20
E22
E21
J19
H24
F22
F20
C23
B22
F18
E18
E20
D22
C19
G18
G17
C17
F14
E14
H17
E17
E15
H15
E13
C13
H12
H11
G14
H14
F12
G12
Y13
AB16
Y19
AC24
F24
E19
C15
E12
W12
W13
Y15
W15
AB19
AB20
AD23
AC23
G22
G21
C22
C21
G16
G15
G13
H13
DDR_A_D63
DDR_A_D62
DDR_A_D61
DDR_A_D60
DDR_A_D59
DDR_A_D58
DDR_A_D57
DDR_A_D56
DDR_A_D55
DDR_A_D54
DDR_A_D53
DDR_A_D52
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
DDR_A_D47
DDR_A_D46
DDR_A_D45
DDR_A_D44
DDR_A_D43
DDR_A_D42
DDR_A_D41
DDR_A_D40
DDR_A_D39
DDR_A_D38
DDR_A_D37
DDR_A_D36
DDR_A_D35
DDR_A_D34
DDR_A_D33
DDR_A_D32
DDR_A_D31
DDR_A_D30
DDR_A_D29
DDR_A_D28
DDR_A_D27
DDR_A_D26
DDR_A_D25
DDR_A_D24
DDR_A_D23
DDR_A_D22
DDR_A_D21
DDR_A_D20
DDR_A_D19
DDR_A_D18
DDR_A_D17
DDR_A_D16
DDR_A_D15
DDR_A_D14
DDR_A_D13
DDR_A_D12
DDR_A_D11
DDR_A_D10
DDR_A_D9
DDR_A_D8
DDR_A_D7
DDR_A_D6
DDR_A_D5
DDR_A_D4
DDR_A_D3
DDR_A_D2
DDR_A_D1
DDR_A_D0
DDR_A_DM7
DDR_A_DM6
DDR_A_DM5
DDR_A_DM4
DDR_A_DM3
DDR_A_DM2
DDR_A_DM1
DDR_A_DM0
DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_D[63..0] (10)
DDR_A_ DQS7 (10)
DDR_A_DQS#7 (10)
DDR_A_ DQS6 (10)
DDR_A_DQS#6 (10)
DDR_A_ DQS5 (10)
DDR_A_DQS#5 (10)
DDR_A_ DQS4 (10)
DDR_A_DQS#4 (10)
DDR_A_ DQS3 (10)
DDR_A_DQS#3 (10)
DDR_A_ DQS2 (10)
DDR_A_DQS#2 (10)
DDR_A_ DQS1 (10)
DDR_A_DQS#1 (10)
DDR_A_ DQS0 (10)
DDR_A_DQS#0 (10)
To normal SODIMM socket
A1
+1.8V
12
R33
1K_0402_1%
1 1
1K_0402_1%
12
R23
1000P_0402_50V7K
1
C32
2
A
CPU_VREF_REF
1
C33
1000P_0402_50V7K
2
VDD_VREF_SUS_CPU
LAYOUT:PLACE CLOSE TO CPU
0.1U_0402_16V4Z
1
C34
2
1000P_0402_50V7K
1
2
C29
+0.9VREF_CPU
1
C28
1U_0402_6.3V4Z
2
Security Classification
Issued Date
THIS SHEET OF ENG INEE RING D RAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY CO MPAL ELECTRONICS, IN C. NEITHER THIS SHE ET NOR THE INFORMATI ON IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PART Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/05/09 2006/10/11
Compal Secret Data
Deciphered Date
D
Compal Electronics inc
Title
SCHEMATIC, M/B LA-3121P
Size Document Number Rev
Custom
401411
星期一 五月
Date: Sheet
AF1
Athlon 64 S1g1
uPGA638
Top View
006
E
A26
751, 08, 2
D
of
5
+2.5VS
1
C506
+
FCM2012C-800_0805
150U_D2_6.3VM
CPU_PWRGD(18,19)
LDT_STOP#(14,19)
2
300_0402_5%
300_0402_5%
300_0402_5%
1 2
R82 0_0402_5%
R63
R88
R71
D D
C C
SB_PWROK(19,37)
LDT_RST#(18)
1 2
+1.8VS
12
+1.8VS
12
+1.8VS
12
SB_PWROK_R
LDT_RST#
+1.8V
L4
1
2
4.7U_0805_10V4Z
+1.8V+3VS
12
R64
4.7K_0402_5%@
5
2
B
1
A
3
R543 0_0402_5% @
1 2
+1.8V
5
2
B
1
A
3
R544 0_0402_5% @
1 2
+1.8V
5
2
B
1
A
NC7SZ08P5 X_NL_SC70-5
3
R545 0_0402_5% @
1 2
1
C189
2
C147 0.1U_0402_16V4Z
1 2
U5
P
R70
4
1 2
Y
G
NC7SZ08P5 X_NL_SC70-5
C155 0.1U_0402_16V4Z
1 2
U8
P
R79
4
1 2
Y
G
NC7SZ08P5 X_NL_SC70-5
C282 0.1U_0402_16V4Z
1 2
U6
P
R65
4
1 2
Y
G
C187
0.22U_0603_16V7K
0_0402_5%
0_0402_5%
0_0402_5%
4
1
C136
3300P_0402_50V7K
2
CPU_ALL_PWROK
CPU_LDTSTOP#
CPU_HT_RESET#
W=50mils
R372 300_0402_5%
1 2
+1.8VS
+1.2V_HT
R584 0_0402_5%@
R585 0_0402_5%@
CPU_SIC(18)
CPU_SID(18)
place them to CPU within 1"
LAYOUT: ROUTE VDDA TRACE APPROX.
50 mils WIDE (USE 2x25 mil TRACES TO
EXIT BALL FIE L D) AND 500 mils LONG.
R582 300_0402_5%@
1 2
R583 300_0402_5%@
1 2
1 2
1 2
R36 44.2_0603_1%
1 2
R35 44.2_0603_1%
1 2
CPUCLK(17)
CPUCLK#(17)
3
2
ATHLON Control and Debug
JP23D
F8
VDDA2
12/22 Modify
CPU_SIC_R
CPU_SID_R
CPU_HTREF1
CPU_HTREF0 VID0
5:10
CPU_VCC_SENSE(48)
CPU_VSS_SENSE(48)
C501
1 2
3900P_0402_50V7K
169_0402_1%
C502
1 2
3900P_0402_50V7K
R389
CPU_CLKIN_SC_P
CPU_CLKIN_SC_N
12
CPU_HT_RESET#
CPU_ALL_PWROK
CPU_LDTSTOP#
CPU_VCC_SENSE
CPU_VSS_SENSE
TP2PAD
TP1PAD
CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI
CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1
CPU_THERMDC
CPU_THERMDA
10:10
F9
B7
A7
F10
AF4
AF5
P6
R6
F6
E6
W9
Y9
A9
A8
G10
AA9
AC9
AD9
AF9
E8
G9
H10
AA7
C2
D7
E7
F7
C7
AC8
C3
AA6
W7
W8
Y6
AB6
P20
P19
N20
N19
R26
R25
P22
R22
THERMTRIP_L
VDDA1
PROCHOT_L
RESET_L
PWROK
LDTSTOP_L
SIC
SID
HTREF1
HTREF0
CPU_PRESENT_L
VDD_FB_H
VDD_FB_L
VDDIO_FB_H
VDDIO_FB_L
CLKIN_H
CLKIN_L
DBRDY
TMS
TCK
TRST_L
TDI
TEST25_HE9TEST29_H
TEST25_L
TEST19
TEST18
TEST13
TEST9
TEST17
TEST16
TEST15
TEST14
TEST12
TEST7
TEST6
THERMDC
THERMDA
TEST3
TEST2
RSVD0
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
FOX_PZ63823-284S-41F
MISC
AMD NPT S1 SOCKET
Processor Socket
DBREQ_L
TEST29_L
TEST24
TEST23
TEST22
TEST21
TEST20
TEST28_H
TEST28_L
TEST27
TEST26
TEST10
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
PSI_L
TEST8
VID5
VID4
VID3
VID2
VID1
VID0
TDO
H_THERMTRIP_S#
AF6
CPU_PROCHOT#_1.8
AC7
VID5
A5
VID4
C6
VID3
A6
VID2
A4
VID1
C5
B5
CPU_PRESENT#
AC6
PSI#
A3
CPU_DBREQ#
E10
CPU_TDO
AE9
CPU_TEST29_H_FBCLKOUT_P
C9
CPU_TEST29_L_FBCLKOUT_N
C8
5:5:5
AE7
AD7
AE8
CPU_TEST21_SCANEN
AB8
AF7
J7
H8
AF8
CPU_TEST26_BURNIN#
AE6
K8
C4
H16
B18
B3
C1
H6
G6
D5
R24
W18
R23
AA8
H18
H19
R7
300_0402_5%
+1.8V
12
PSI# (48)
80.6_0402_1%
12
R78
300_0402_5%
VID5 (48)
VID4 (48)
VID3 (48)
VID2 (48)
VID1 (48)
VID0 (48)
R68
1 2
ROUTE AS 80 Ohm DIFFERENTIAL PAIR
PLACE IT CLOSE TO CPU WITHIN 1"
1
HDT Connector
12
+1.8V
12
R4
1K_0402_5%
2
Q3
3 1
MMBT3904_SOT23
10K_0402_5%
+3VALW
+1.8V
12
R8
CPU_PH_G
B
2
Q4
E
3 1
C
MMBT3904_SOT23
Title
Size Document Number Rev
C
Date: Sheet
12
12
12
12
B B
NOTE: HDT TERMINATION IS REQUIRED
FOR REV. Ax SILICON ONLY.
C451
A A
2200P_0402_50V7K
EC_SMB_CK2(28)
EC_SMB_DA2(28)
5
CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO
1
2
R361 220_0402_5%@
EC_SMB_CK2
EC_SMB_DA2
12
+1.8V
R364 220_0402_5%@
R362 220_0402_5%@
R363 220_0402_5%@
R365 220_0402_5%@
CPU_THERMDA
CPU_THERMDC
2
3
8
7
U4524 CLOSE CPU,
CPU_THERMDA&CPU_THERMDC PLACE
CLOSE TO PROCESSOR WITHIN 1" INCH
+3VS
U38
D+
ALERT#
D-
THERM#
SCLK
SDATA
ADM1032ARM_RM8
JP4
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
2423
26
SAMTEC_ASP-68200-07
@
1
C454
0.1U_0402_16V4Z
2
1
VDD1
6
4
5
GND
12
R572
220_0402_5%
@
3V_LDT_RST# CPU_HT_RESET#
12
R374
10K_0402_5%@
4
1 3
+3VALW+3VS
2
G
D
S
Q33
2N7002_SOT23@
CPU_TEST26_BURNIN#
CPU_PRESENT#
CPU_TEST25_H_BYPASSCLK_H
CPU_TEST21_SCANEN
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1
3
R366 300_0402_5%
1 2
R369 1K_0402_5%
1 2
R47 510_0402_5%
1 2
R368 300_0402_5%
1 2
R54 510_0402_5%
1 2
R92 300_0402_5%
1 2
R91 300_0402_5%
1 2
Security Classification
Issued Date
THIS SHEET OF ENG INEE RING D RAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY CO MPAL ELECTRONICS, IN C. NEITHER THIS SHE ET NOR THE INFORMATI ON IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PART Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+1.8V
2005/05/09 2006/03/08
Compal Secret Data
Deciphered Date
2
+1.8V
R5
300_0402_5%
H_THERMTRIP_S# H_THERMTRIP#
CPU_PROCHOT#_1.8
+3VALW
12
3 1
H_THERMTRIP# (19)
+3VS
12
R6
4.7K_0402_5%
@
R2
1K_0402_5%@
2
Q2
MMBT3904_SOT23@
EC_THERM# (19,28)
MAINPW ON (4 2,43,45)
12
R3
10K_0402_5%
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3121P
401411
星期三 五月
006
1
851, 10, 2
D
of
5
D D
4
3
+CPU_CORE
1
+
C505
@
330U_D2E_2.5VM_R9
2
+CPU_CORE
1
C195
2
10U_0805_10V6M
10U_0805_10V6M
1
C17
2
10U_0805_10V6M
1
+
C504
@
330U_D2E_2.5VM_R9
2
10U_0805_10V6M
1
C194
2
1
C193
2
10U_0805_10V6M
1
+
C453
330U_D2E_2.5VM_R9
2
10U_0805_10V6M
1
C192
2
2
1
+
C452
330U_D2E_2.5VM_R9
2
+CPU_CORE
1
1
C16
C97
10U_0805_10V6M
2
2
1
+
C450
820U_E9_2.5V_M_R7
45@
2
1
+
C449
820U_E9_2.5V_M_R7
45@
2
1
JP23F
AA4
VSS1
AA11
VSS2
AA13
VSS3
AA15
VSS4
AA17
VSS5
AA19
VSS6
AB2
VSS7
AB7
VSS8
AB9
VSS9
AB23
VSS10
AB25
VSS11
AC11
VSS12
AC13
VSS13
AC15
VSS14
AC17
VSS15
AC19
VSS16
AC21
VSS17
AD6
VSS18
AD8
VSS19
AD25
VSS20
AE11
VSS21
AE13
VSS22
AE15
VSS23
AE17
VSS24
AE19
VSS25
AE21
VSS26
AE23
VSS27
B4
VSS28
B6
VSS29
B8
VSS30
B9
VSS31
B11
VSS32
B13
VSS33
B15
VSS34
B17
VSS35
B19
VSS36
B21
VSS37
B23
VSS38
B25
VSS39
D6
VSS40
D8
VSS41
D9
VSS42
D11
VSS43
D13
VSS44
D15
VSS45
D17
VSS46
D19
VSS47
D21
VSS48
D23
VSS49
D25
VSS50
E4
VSS51
F2
VSS52
F11
VSS53
F13
VSS54
F15
VSS55
F17
VSS56
F19
VSS57
F21
VSS58
F23
VSS59
F25
VSS60
H7
VSS61
H9
VSS62
H21
VSS63
H23
VSS64
J4
VSS65
FOX_PZ63823-284S-41F
Athlon 64 S1
Processor Socket
JP23E
AC4
VDD1
AD2
VDD2
G4
VDD3
H2
VDD4
J9
VDD5
J11
VDD6
J13
VDD7
K6
VDD8
K10
VDD9
K12
VDD10
K14
VDD11
L4
VDD12
L7
VDD13
L9
VDD14
L11
VDD15
L13
VDD16
M2
C C
B B
VDD17
M6
VDD18
M8
VDD19
M10
VDD20
N7
VDD21
N9
VDD22
N11
VDD23
P8
VDD24
P10
VDD25
R4
VDD26
R7
VDD27
R9
VDD28
R11
VDD29
T2
VDD30
T6
VDD31
T8
VDD32
T10
VDD33
T12
VDD34
T14
VDD35
U7
VDD36
U9
VDD37
U11
VDD38
U13
VDD39
V6
VDD40
V8
VDD41
V10
VDD42
FOX_PZ63823-284S-41F
Athlon 64 S1
Processor Socket
Power
VDD43
VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
+CPU_CORE+CPU_CORE
V12
V14
W4
Y2
J15
K16
L15
M16
P16
T16
U15
V16
+1.8V
H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
P18
P21
P23
P25
R17
T18
T21
T23
T25
U17
V18
V21
V23
V25
Y25
J6
VSS66
J8
VSS67
J10
VSS68
J12
VSS69
J14
VSS70
J16
VSS71
J18
VSS72
K2
VSS73
K7
VSS74
K9
VSS75
K11
VSS76
K13
VSS77
K15
VSS78
K17
VSS79
L6
VSS80
L8
VSS81
L10
VSS82
L12
VSS83
L14
VSS84
L16
VSS85
L18
VSS86
M7
VSS87
M9
VSS88
M11
VSS89
M17
VSS90
N4
VSS91
N8
VSS92
N10
VSS93
N16
VSS94
N18
VSS95
P2
VSS96
P7
VSS97
P9
VSS98
P11
VSS99
P17
VSS100
R8
VSS101
R10
Ground
VSS102
R16
VSS103
R18
VSS104
T7
VSS105
T9
VSS106
T11
VSS107
T13
VSS108
T15
VSS109
T17
VSS110
U4
VSS111
U6
VSS112
U8
VSS113
U10
VSS114
U12
VSS115
U14
VSS116
U16
VSS117
U18
VSS118
V2
VSS119
V7
VSS120
V9
VSS121
V11
VSS122
V13
VSS123
V15
VSS124
V17
VSS125
W6
VSS126
Y21
VSS127
Y23
VSS128
N6
VSS129
+CPU_CORE
1
C73
22U_0805_6.3V6M
2
+CPU_CORE +1.8V
1
C70
0.22U_0402_10V4Z
2
+1.8V
1
C472
4.7U_0805_10V4Z
2
1
C127
0.22U_0402_10V4Z
2
+0.9V
1
C188
4.7U_0805_10V4Z
2
CPU SOCKET S1 DECOUPLING
1
C76
22U_0805_6.3V6M
2
1
C120
0.22U_0402_10V4Z
2
1
C86
10U_0805_10V6M
2
1
C100
180P_0402_50V8J
2
1
C118
22U_0805_6.3V6M
2
1
C91
0.01U_0402_16V7K
2
1
C109
10U_0805_10V6M
2
1
C96
10U_0805_10V6M
2
1
C82
10U_0805_10V6M
2
1
2
DECOUPLING BETWEEN PROCESSOR AND DIMMs
PLACE CLOSE TO PROCESSOR AS POSSIBLE
1
C471
4.7U_0805_10V4Z
2
1
C128
0.01U_0402_16V7K
2
1
C30
4.7U_0805_10V4Z
2
1
C479
4.7U_0805_10V4Z
2
1
C85
0.01U_0402_16V7K
2
1
C36
4.7U_0805_10V4Z
2
1
C480
4.7U_0805_10V4Z
2
1
C181
4.7U_0805_10V4Z
2
1
C68
180P_0402_50V8J
2
1
C104
0.22U_0402_10V4Z
2
1
C105
180P_0402_50V8J
2
1
C184
0.22U_0402_10V4Z
2
1
C84
0.22U_0402_10V4Z
2
1
C185
0.22U_0402_10V4Z
2
1
C89
10U_0805_10V6M
2
C102
10U_0805_10V6M
1
2
1
2
1
C113
10U_0805_10V6M
2
1
C72
0.22U_0402_10V4Z
2
C129
0.22U_0402_10V4Z
C27
0.22U_0402_10V4Z
1
C124
22U_0805_6.3V6M
2
1
C116
0.22U_0402_10V4Z
2
1
C23
0.22U_0402_10V4Z
2
1
C39
1000P_0402_50V7K
2
A1
A26
1
C41
1000P_0402_50V7K
2
1
C178
1000P_0402_50V7K
2
1
C22
1000P_0402_50V7K
2
1
C179
180P_0402_50V8J
2
1
C26
180P_0402_50V8J
2
1
C175
180P_0402_50V8J
2
1
C182
180P_0402_50V8J
2
Athlon 64 S1g1
uPGA638
A A
Top View
PROCESSOR POWER AND GROUND
AF1
Security Classification
Issued Date
THIS SHEET OF ENG INEE RING D RAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY CO MPAL ELECTRONICS, IN C. NEITHER THIS SHE ET NOR THE INFORMATI ON IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PART Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/05/09 2006/03/08
Compal Secret Data
Deciphered Date
2
Compal Electronics. inc.
Title
SCHEMATIC, M/B LA-3121P
Size Document Number Rev
C
401411
星期三 五月
Date: Sheet
006
1
951, 10, 2
of
D
5
4
3
2
1
+1.8V+DIMM_VREF+1.8V+1.8V
JP19
1
VREF
3
DDR_A_D0
D D
C C
DDR_CKE0_DIMMA(7)
DDR_CS2_DIMMA#(7)
DDR_A_BS#2(7)
DDR_A_BS#0(7)
DDR_A_WE#(7)
DDR_A_CAS#(7)
DDR_CS1_DIMMA#(7)
DDR_A_ODT1(7)
B B
A A
SB_CK_SDAT(11,17,19,31,34)
SB_CK_SCLK(11,17,19,31,34)
DDR_A_D1
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18 DDR_A_D22
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
DDR_CKE0_DIMMA
DDR_CS2_DIMMA#
DDR_A_BS#2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
DDR_A_ODT1
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43 DDR_A_D47
DDR_A_D48
DDR_A_D49 DDR_A_D53
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51 DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
SB_CK_SDAT
SB_CK_SCLK
+3VS
1
C448
0.1U_0402_16V4Z
2
5
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
P-TWO_A5692C-A0G16
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
VDD
VDD
BA1
RAS#
VDD
ODT0
NC/A13
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
A11
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
108
110
S0#
112
114
116
118
120
NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
4
DDR_A_D4
DDR_A_D5
DDR_A_DM0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
DDR_A_DM1
DDR_A_CLK1
DDR_A_CLK#1
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_CKE1_DIMMA
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6DDR_A_MA8
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#
DDR_A_ODT0
DDR_A_MA13
DDR_CS3_DIMMA#
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D52
DDR_A_CLK2
DDR_A_CLK#2
DDR_A_DM6
DDR_A_D54
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
R12 10K_0402_5%
1 2
R10 10K_0402_5%
1 2
DDR_A_CLK1 (7)
DDR_A_CLK#1 (7)
DDR_CKE1_DIMMA (7)
DDR_A_BS#1 (7)
DDR_A_RAS# (7)
DDR_CS0_DIMMA# (7)
DDR_A_ODT0 (7)
DDR_CS3_DIMMA# (7)
DDR_A_CLK2 (7)
DDR_A_CLK#2 (7)
C507
0.1U_0402_16V4Z
1
1
2
2
4.7U_0805_10V4Z
DDR_A_D[0..63](7)
DDR_A_DM[0..7](7)
DDR_A_DQS[0..7](7)
DDR_A_MA[0..15](7)
DDR_A_DQS#[0..7](7)
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C503
3
12
R398
1K_0402_1%
12
R397
1K_0402_1%
DDR_A_D[0..63]
DDR_A_DM[0..7]
DDR_A_DQS[0..7]
DDR_A_MA[0..15]
DDR_A_DQS#[0..7]
2005/05/09 2006/10/11
+1.8V
1
2
C639
4.7U_0805_6.3V6K
4.7U_0805_10V4Z
1
2
+0.9V
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C63
C67
DDR_CKE0_DIMMA
DDR_CS2_DIMMA#
DDR_A_BS#2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
DDR_CS3_DIMMA#
+0.9V
Compal Secret Data
Deciphered Date
1
2
C643
0.01U_0402_16V7K
4.7U_0805_10V4Z
1
2
0.1U_0402_16V4Z
1
2
C114
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
0.1U_0402_16V4Z
1
2
C618
C644
0.01U_0402_16V7K
1
2
4.7U_0805_10V4Z
1
C98
2
0.1U_0402_16V4Z
1
1
2
2
C107
C95
0.1U_0402_16V4Z
1
2
C619
C646
10P_0402_25V8K
1
1
2
2
C645
10P_0402_25V8K
4.7U_0805_10V4Z
1
C475
2
0.1U_0402_16V4Z
1
2
C69
+0.9V
0.1U_0402_16V4Z
1
2
+1.8V
C55
C56
Custom
Date: Sheet
C640
4.7U_0805_6.3V6K
1
2
C470
0.1U_0402_16V4Z
C642
4.7U_0805_6.3V6K
1
1
2
2
C641
4.7U_0805_6.3V6K
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
1
C62
C77
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C80
C71
Layout Note:
Place one ca p c l o se to every 2 pullup
resistors terminated to +0.9V
RP28 47_0404_4P2R_5%
RP25 47_0404_4P2R_5%
RP21 47_0404_4P2R_5%
RP18 47_0404_4P2R_5%
RP13 47_0404_4P2R_5%
RP9 47_0404_4P2R_5%
RP5 47_0404_4P2R_5%
R32 47_0402_1%
1 2
R28 47_0402_1%
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C616
C617
Layout Note:
Place one 0.1uF cap close to every 2 pullup
resistors terminated to +0.9V
2
C648
0.22U_0603_16V7K
1
1
2
2
C647
0.22U_0603_16V7K
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
1
C473
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C74
1 4
2 3
RP22 47_0404_4P2R_5%
1 4
2 3
RP17 47_0404_4P2R_5%
1 4
2 3
RP14 47_0404_4P2R_5%
1 4
2 3
RP10 47_0404_4P2R_5%
1 4
2 3
RP6 47_0404_4P2R_5%
1 4
2 3
RP2 47_0404_4P2R_5%
1 4
2 3
RP1 47_0404_4P2R_5%
0.1U_0402_16V4Z
1
2
C620
Compal Electronics. inc.
Title
SCHEMATIC, M/B LA-3121P
Size Docum ent Number Rev
401411
星期三 五月
1
2
C649
0.22U_0603_16V7K
4.7U_0805_10V4Z
1
C57
2
0.1U_0402_16V4Z
1
1
2
2
C88
0.1U_0402_16V4Z
1
2
C621
C650
0.22U_0603_16V7K
1
2
4.7U_0805_10V4Z
C463
0.1U_0402_16V4Z
1
2
C45
C65
DDR_CKE1_DIMMA
DDR_CS0_DIMMA#
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C622
1
1
2
2
C651
0.22U_0603_16V7K
1
1
+
C477
220U_D2_4VM_R15
C58
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C101
DDR_A_MA15
DDR_A_MA7
DDR_A_MA14
DDR_A_MA6
DDR_A_MA11
DDR_A_MA2
DDR_A_MA4
DDR_A_BS#1
DDR_A_MA0
DDR_A_RAS#
DDR_A_MA13DDR_A_ODT1
DDR_A_ODT0
1
2
C623
1
C652
0.22U_0603_16V7K
1
C636
1
+
150U_D2_6.3VM
2
2
C51
+1.8V
of
10 51, 10, 2006
D
5
4
3
2
1
1
C52
2
0.1U_0402_16V4Z
1
2
C7
DDR_B_D[0..63](7)
DDR_B_DM[0..7](7)
DDR_B_DQS[0..7](7)
DDR_B_MA[0..15](7)
DDR_B_DQS#[0..7](7)
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
C99
2
0.1U_0402_16V4Z
1
2
C10
0.1U_0402_16V4Z
4.7U_0805_10V4Z
1
C103
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C18
C13
Layout Note:
Place one cap c lo se to every 2 pullup
resistors te r m inated to +0.9V
1 4
2 3
RP27 47_0404_4P2R_5%
1 4
2 3
RP24 47_0404_4P2R_5%
1 4
2 3
RP19 47_0404_4P2R_5%
1 4
2 3
RP15 47_0404_4P2R_5%
1 4
2 3
RP11 47_0404_4P2R_5%
1 4
2 3
RP8 47_0404_4P2R_5%
1 4
2 3
RP7 47_0404_4P2R_5%
R29 47_0402_1%
1 2
R30 47_0402_1%
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C624
C625
Layout Note:
Place one 0.1u F c ap cl ose to every 2 pullup
resistors te r m inated to +0.9V
Deciphered Date
2
+DIMM_VREF+1.8V+1.8V
0.1U_0402_16V4Z
C202
JP18
1
VREF
3
DDR_B_D0
D D
C C
DDR_CKE0_DIMMB(7)
DDR_CS2_DIMMB#(7)
DDR_B_BS#2(7)
DDR_B_BS#0(7)
DDR_B_WE#(7)
DDR_B_CAS#(7)
DDR_CS1_DIMMB#(7)
DDR_B_ODT1(7)
B B
A A
SB_CK_SDAT(10,17,19,31,34)
SB_CK_SCLK(10,17,19,31,34)
DDR_B_D1
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18 DDR_B_D22
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
DDR_CKE0_DIMMB
DDR_CS2_DIMMB#
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#
DDR_B_CAS#
DDR_CS1_DIMMB#
DDR_B_ODT1
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43 DDR_B_D47
DDR_B_D48
DDR_B_D49 DDR_B_D53
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51 DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
SB_CK_SDAT
SB_CK_SCLK
+3VS
1
C21
0.1U_0402_16V4Z
2
5
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
P-TWO_A5652C-A0G16
DQ12
DQ13
CK0#
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQS3#
DQS3
DQ30
DQ31
NC/CKE1
NC/A15
NC/A14
RAS#
ODT0
NC/A13
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQS5#
DQS5
DQ46
DQ47
DQ52
DQ53
CK1#
DQ54
DQ55
DQ60
DQ61
DQS7#
DQS7
DQ62
DQ63
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
VSS
DM1
VSS
CK0
VSS
VSS
VSS
VSS
DM2
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
BA1
VDD
VDD
VSS
VSS
DM4
VSS
VSS
VSS
VSS
VSS
VSS
CK1
VSS
DM6
VSS
VSS
VSS
VSS
VSS
SAO
SA1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
A11
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
108
110
S0#
112
114
116
118
120
NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
4
DDR_B_D4
DDR_B_D5
DDR_B_DM0
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
DDR_B_DM1
DDR_B_CLK1
DDR_B_CLK#1
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_DM2
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDR_CKE1_DIMMB
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6DDR_B_MA8
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS#1
DDR_B_RAS#
DDR_CS0_DIMMB#
DDR_B_ODT0
DDR_B_MA13
DDR_CS3_DIMMB#
DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D52
DDR_B_CLK2
DDR_B_CLK#2
DDR_B_DM6
DDR_B_D54
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
R11 10K_0402_5%
1 2
R9 10K_0402_5%
1 2
4.7U_0805_10V4Z
1
2
DDR_B_CLK1 (7)
DDR_B_CLK#1 (7)
DDR_CKE1_DIMMB (7)
DDR_B_BS#1 (7)
DDR_B_RAS# (7)
DDR_CS0_DIMMB# (7)
DDR_B_ODT0 (7)
DDR_CS3_DIMMB# (7)
DDR_B_CLK2 (7)
DDR_B_CLK#2 (7)
+3VS
C198
1
2
4.7U_0805_10V4Z
+0.9V
0.1U_0402_16V4Z
1
2
C4
DDR_CS2_DIMMB#
DDR_CKE0_DIMMB
DDR_B_MA12
DDR_B_BS#2
DDR_B_MA8
DDR_B_MA9
DDR_B_MA3
DDR_B_MA5
DDR_B_MA10
DDR_B_MA1
DDR_B_WE#
DDR_B_BS#0
DDR_CS0_DIMMB#
DDR_B_RAS#
DDR_B_ODT1
DDR_CS3_DIMMB#
+0.9V
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/05/09 2006/10/11
Compal Secret Data
1
2
1
2
C626
C59
0.1U_0402_16V4Z
DDR_B_D[0..63]
DDR_B_DM[0..7]
DDR_B_DQS[0..7]
DDR_B_MA[0..15]
DDR_B_DQS#[0..7]
4.7U_0805_10V4Z
1
C64
2
0.1U_0402_16V4Z
1
2
C8
1
2
C627
+1.8V
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
C53
2
0.1U_0402_16V4Z
1
2
C11
+0.9V
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C12
4.7U_0805_10V4Z
1
1
C81
C78
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C19
C14
1 4
2 3
RP26 47_0404_4P2R_5%
1 4
2 3
RP23 47_0404_4P2R_5%
1 4
2 3
RP20 47_0404_4P2R_5%
1 4
2 3
RP16 47_0404_4P2R_5%
1 4
2 3
RP12 47_0404_4P2R_5%
1 4
2 3
RP3 47_0404_4P2R_5%
1 4
2 3
RP4 47_0404_4P2R_5%
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
1
2
2
C628
C6
C5
Compal Electronics. inc.
Title
SCHEMATIC, M/B LA-3121P
Size Docum ent Number Rev
Custom
401411
Date: Sheet
4.7U_0805_10V4Z
1
2
0.1U_0402_16V4Z
1
2
C629
星期三 五月
4.7U_0805_10V4Z
C61
0.1U_0402_16V4Z
1
2
C9
DDR_CKE1_DIMMB
DDR_CS1_DIMMB#
0.1U_0402_16V4Z
1
2
C630
1
1
+
C125
2
2
0.1U_0402_16V4Z
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS#1
DDR_B_CAS#
DDR_B_ODT0
DDR_B_MA13
0.1U_0402_16V4Z
1
2
C631
C633
220U_D2_4VM_R15
0.1U_0402_16V4Z
1
1
2
2
C20
C15
+1.8V
1
D
of
11 51, 10, 2006
5
4
3
2
1
D D
C C
+1.2V_HT
H_CADOP15(6)
H_CADON15(6)
H_CADOP14(6)
H_CADON14(6)
H_CADOP13(6)
H_CADON13(6)
H_CADOP12(6)
H_CADON12(6)
H_CADOP11(6)
H_CADON11(6)
H_CADOP10(6)
H_CADON10(6)
H_CADOP9(6)
H_CADON9(6)
H_CADOP8(6)
H_CADON8(6)
H_CADOP7(6)
H_CADON7(6)
H_CADOP6(6)
H_CADON6(6)
H_CADOP5(6)
H_CADON5(6)
H_CADOP4(6)
H_CADON4(6)
H_CADOP3(6)
H_CADON3(6)
H_CADOP2(6)
H_CADON2(6)
H_CADOP1(6)
H_CADON1(6)
H_CADOP0(6)
H_CADON0(6)
H_CLKOP1(6)
H_CLKON1(6)
H_CLKOP0(6)
H_CLKON0(6)
H_CTLOP0(6)
H_CTLON0(6)
R382 49.9_0402_1%
R380 49.9_0402_1%
1 2
1 2
H_CADOP15
H_CADON15
H_CADOP14
H_CADON14
H_CADOP13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADOP10
H_CADON10
H_CADOP9
H_CADON9
H_CADOP8
H_CADON8
H_CADOP7
H_CADON7
H_CADOP6
H_CADON6
H_CADOP5
H_CADON5
H_CADOP4
H_CADON4
H_CADOP3
H_CADON3
H_CADOP2
H_CADON2
H_CADOP1
H_CADON1
H_CADOP0
H_CADON0
H_CLKOP1
H_CLKON1
H_CLKON0
H_CTLON0
HT_RXCALP
HT_RXCALN
U39A
R19
HT_RXCAD15P
R18
HT_RXCAD15N
R21
HT_RXCAD14P
R22
HT_RXCAD14N
U22
HT_RXCAD13P
U21
HT_RXCAD13N
U18
HT_RXCAD12P
U19
HT_RXCAD12N
W19
HT_RXCAD11P
W20
HT_RXCAD11N
AC21
HT_RXCAD10P
AB22
HT_RXCAD10N
AB20
HT_RXCAD9P
AA20
HT_RXCAD9N
AA19
HT_RXCAD8P
Y19
HT_RXCAD8N
T24
HT_RXCAD7P
R25
HT_RXCAD7N
U25
HT_RXCAD6P
U24
HT_RXCAD6N
V23
HT_RXCAD5P
U23
HT_RXCAD5N
V24
HT_RXCAD4P
V25
HT_RXCAD4N
AA25
HT_RXCAD3P
AA24
HT_RXCAD3N
AB23
HT_RXCAD2P
AA23
HT_RXCAD2N
AB24
HT_RXCAD1P
AB25
HT_RXCAD1N
AC24
HT_RXCAD0P
AC25
HT_RXCAD0N
W21
HT_RXCLK1P
W22
HT_RXCLK1N
Y24
HT_RXCLK0P
W25
HT_RXCLK0N
P24
HT_RXCTLP
P25
HT_RXCTLN
A24
HT_RXCALP
C24
HT_RXCALN
216MSA4ALA11FG RS485MC_BGA465
PART 1 OF 5
HT_TXCAD15P
HT_TXCAD15N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD0P
HT_TXCAD0N
HT_TXCLK1P
HYPER TRANSPORT CPU
HT_TXCLK1N
I/F
HT_TXCLK0P
HT_TXCLK0N
HT_TXCTLP
HT_TXCTLN
HT_TXCALP
HT_TXCALN
P21
P22
P18
P19
M22
M21
M18
M19
L18
L19
G22
G21
J20
J21
F21
F22
N24
N25
L25
M24
K25
K24
J23
K23
G25
H24
F25
F24
E23
F23
E24
E25
L21
L22
J24
J25
N23
P23
C25
D24
H_CADIP15
H_CADIN15
H_CADIP14
H_CADIN14
H_CADIP13
H_CADIN13H_CADON13
H_CADIP12
H_CADIN12
H_CADIP11
H_CADIN11
H_CADIP10
H_CADIN10
H_CADIP9
H_CADIN9
H_CADIP8
H_CADIN8
H_CADIP7
H_CADIN7
H_CADIP6
H_CADIN6
H_CADIP5
H_CADIN5
H_CADIP4
H_CADIN4
H_CADIP3
H_CADIN3
H_CADIP2
H_CADIN2
H_CADIP1
H_CADIN1
H_CADIP0
H_CADIN0
H_CLKIP1
H_CLKIN1
H_CLKIP0H_CLKOP0
H_CLKIN0
H_CTLIP0H_CTLOP0
H_CTLIN0
HT_TXCALP
HT_TXCALN
R379
1 2
100_0402_1%
H_CADIP15 (6)
H_CADIN15 (6)
H_CADIP14 (6)
H_CADIN14 (6)
H_CADIP13 (6)
H_CADIN13 (6)
H_CADIP12 (6)
H_CADIN12 (6)
H_CADIP11 (6)
H_CADIN11 (6)
H_CADIP10 (6)
H_CADIN10 (6)
H_CADIP9 (6)
H_CADIN9 (6)
H_CADIP8 (6)
H_CADIN8 (6)
H_CADIP7 (6)
H_CADIN7 (6)
H_CADIP6 (6)
H_CADIN6 (6)
H_CADIP5 (6)
H_CADIN5 (6)
H_CADIP4 (6)
H_CADIN4 (6)
H_CADIP3 (6)
H_CADIN3 (6)
H_CADIP2 (6)
H_CADIN2 (6)
H_CADIP1 (6)
H_CADIN1 (6)
H_CADIP0 (6)
H_CADIN0 (6)
H_CLKIP1 (6)
H_CLKIN1 (6)
H_CLKIP0 (6)
H_CLKIN0 (6)
H_CTLIP0 (6)
H_CTLIN0 (6)
B B
A A
Security Classification
Issued Date
THIS SHEET OF ENG INEE RIN G DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY O R DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/05/09 2006/03/08
Compal Secret Data
Deciphered Date
Compal Electronics. inc.
Title
SCHEMATIC, M/B LA-3121P
Size Document Number R ev
Custom
401411
Date: Sheet
星期三 五
10, 2006
2
月
12 51,
1
D
of
5
D D
R18 0_0402_5%
PCIE_MRX_PTX_P0(31)
C C
PCIE_MRX_PTX_N0(31)
PCIE_MRX_PTX_P1(34)
PCIE_MRX_PTX_N1(34)
R14:
R15:
1 2
R19 0_0402_5%
1 2
R16 0_0402_5%
1 2
R17 0_0402_5%
1 2
10KOhm FOR RS485
1.47KOhm FOR RS690
8.25KOhm FOR RS485
DNI FOR RS690
A_MRX_STX_N0(18)
A_MRX_STX_P1(18)
A_MRX_STX_N1(18)
R14 10K_0402_1%
R15 8.25K_0402_1%
4
U39B
G5
GFX_RX0P
G4
GFX_RX0N
J8
GFX_RX1P
J7
GFX_RX1N
J4
GFX_RX2P
J5
GFX_RX2N
L8
GFX_RX3P
L7
GFX_RX3N
L4
GFX_RX4P
L5
GFX_RX4N
M8
GFX_RX5P
M7
GFX_RX5N
M4
GFX_RX6P
M5
GFX_RX6N
P8
GFX_RX7P
P7
GFX_RX7N
P4
GFX_RX8P
P5
GFX_RX8N
R4
GFX_RX9P
R5
GFX_RX9N
R7
GFX_RX10P
R8
GFX_RX10N
U4
GFX_RX11P
U5
GFX_RX11N
W4
GFX_RX12P
W5
GFX_RX12N
Y4
GFX_RX13P
Y5
GFX_RX13N
V9
GFX_RX14P
W9
GFX_RX14N
AB7
GFX_RX15P
AB6
PCIE_MRX_PTX_P0_R
PCIE_MRX_PTX_N0_R
PCIE_MRX_PTX_P1_R
PCIE_MRX_PTX_N1_R
A_MRX_STX_P0
A_MRX_STX_N0 A_MTX_SRX_N0
A_MRX_STX_P1
A_MRX_STX_N1
1 2
1 2
GFX_RX15N
W11
GPP_RX0P
W12
GPP_RX0N
AA11
GPP_RX1P
AB11
GPP_RX1N
Y7
GPP_RX2P
AA7
GPP_RX2N
AB9
GPP_RX3P
AA9
GPP_RX3N
W14
SB_RX0P
W15
SB_RX0N
AB12
SB_RX1P
AA12
SB_RX1N
AA14
PCEH_ISET
AB14
PCEH_TXISET
216MSA4ALA11FG RS485MC_BGA465
PART 2 OF 5
PCIE I/F GFX
PCIE I/F GPP
PCIE I/F SB
GFX_TX10N
GFX_TX11N
GFX_TX12N
GFX_TX13N
GFX_TX14N
GFX_TX15N
PCEH_PCAL
PCEH_NCAL
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX11P
GFX_TX12P
GFX_TX13P
GFX_TX14P
GFX_TX15P
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
3
J1
H2
K2
K1
K3
L3
L1
L2
N2
N1
P2
P1
P3
R3
R1
R2
T2
U1
V2
V1
V3
W3
W1
W2
Y2
AA1
AA2
AB2
AB1
AC1
AE3
AE4
AD8
AE8
AD7
AE7
AD4
AE5
AD5
AD6
AE9
AD10
AC8
AD9
AD11
AE11
PCIE_MTX_PRX_P0
PCIE_MTX_PRX_N0
PCIE_MTX_PRX_P1
PCIE_MTX_PRX_N1
A_MTX_SRX_N1
R375 150_0402_1%
1 2
R376 100_0402_1%
1 2
R375:
R215:
C457 0.1U_0402_10V6K
1 2
C458 0.1U_0402_10V6K
C466 0.1U_0402_10V6K
1 2
C467 0.1U_0402_10V6K
C465 0.1U_0402_10V6K
1 2
C464 0.1U_0402_10V6K
C468 0.1U_0402_10V6K
1 2
C469 0.1U_0402_10V6K
150 Ohm FOR RS485
562 Ohm FOR RS690
82.5 Ohm FOR RS485
2KOhm FOR RS690
1 2
1 2
1 2
1 2
2
PCIE_MTX_C_PRX_P0
PCIE_MTX_C_PRX_N0
PCIE_MTX_C_PRX_P1
PCIE_MTX_C_PRX_N1
A_MTX_C_SRX_P0A_MTX_SRX_P0
A_MTX_C_SRX_N0
A_MTX_C_SRX_P1A_MTX_SRX_P1
A_MTX_C_SRX_N1
+1.2V_HT
PCIE_MTX_C_PRX_P0 (31)
PCIE_MTX_C_PRX_N0 (31)
PCIE_MTX_C_PRX_P1 (34)
PCIE_MTX_C_PRX_N1 (34)
A_MTX_C_SRX_P0 (18)A_MRX_STX_P0(18)
A_MTX_C_SRX_N0 (18)
A_MTX_C_SRX_P1 (18)
A_MTX_C_SRX_N1 (18)
1
B B
A A
Security Classification
Issued Date
THIS SHEET OF ENG INEE RIN G DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY O R DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/05/09 2006/03/08
Compal Secret Data
Deciphered Date
Compal Electronics. inc.
Title
SCHEMATIC, M/B LA-3121P
Size Document Number R ev
Custom
401411
Date: Sheet
星期三 五
10, 2006
2
月
13 51,
1
D
of
5
R540 0_0805_5%
D D
150U_D2_6.3VM
C C
B B
A A
+1.8VS
CHB2012U121_0805
CHB2012U121_0805
1
+
C183
2
+1.8VS
CHB2012U121_0805
4.7K_0402_5%
NOTE: ACCESS TO STRAP_DATA and I2C_CLK PINS
IS MANDAT ORY.
L52
1 2
@
L53
1 2
C499
@
L56
1 2
@
R50
1 2
AVDDQ
2.2U_0805_10V6K
1
C489
C495
10U_0805_10V4Z
2
PLLVDD
1
1
C485
10U_0805_10V4Z
2
2
1U_0603_10V4Z
HTPVDD
10U_0805_10V4Z
1
1
C493
2
2
1U_0603_10V4Z
+3VS
4.7K_0402_5%
4.7K_0402_5%
R51
1 2
U2
1
A0
2
A1
3
A2
4
VSS
AT24C04N-10SI-2.7_SO8
@
5
1
2
AVSSQ_GND
1
C492
4.7U_0805_10V4Z
2
C498
R49
1 2
EDID_LCD_CLK
EDID_LCD_DAT
VCC
WP
SCL
SDA
1
C484
1U_0603_10V4Z
2
R230-R232 CLOSE TO NB
CRT_R(24)
CRT_G(24)
CRT_B(24)
+1.8VS
1
C488
4.7U_0805_10V4Z
2
DDC_DATA
+3VS +3VS
8
7
6
5
R568 10K_0402_5%
LDT_STOP#(8,19)
12
R40
10K_0402_5%
@
EDID_LCD_CLK
1
C117
0.1U_0402_16V4Z
2
@
150_0402_1%
BMREQ#(18)
1 2
150U_D2_6.3VM
CRT_R
CRT_G
CRT_B
150_0402_1%
12
R75
12
B
2
E
3 1
C
MMBT3904_SOT23
12
R41
2K_0402_5%
@
STRP_DATA
12
R39
2K_0402_5%
@
C186
Q27
4
12
R76
+3VS
+3VS
4
AVSSQ_GND
+1.8VS
1
+
2
150_0402_1%
12
12
R46
1K_0402_5%
12
R569
10K_0402_5%
1
C635
18P_0402_50V8J
2
+3VS AVDD
L43
1 2
CHB2012U121_0805
1U_0603_10V4Z
L44
1 2
CHB2012U121_0805
1U_0603_10V4Z
R74
ALLOW_LDTSTOP(18)
HTREFCLK(17)
SB_OSCIN(17,19)
NBSRC_CLKP(17)
NBSRC_CLKN(17)
SBLINK_CLKP(17)
SBLINK_CLKN(17)
LOAD_ROM#(16)
C490
AVDDQ
AVSSQ_GND
8mils TRACE
VGA_DDC_CLK(24)
VGA_DDC_DATA(24)
NB_RST#(18,23,28,31,36)
NB_PWROK(37)
NB_OSC(17)
D27
12
1N4148_SOT23
1
2
1
C483
2
1
C496
2
2.2U_0805_10V6K
VGA_TV_CRMA(24)
VGA_TV_LUMA(24)
VGA_TV_COMPS(24)
VGA_CRT_VSYNC(24)
VGA_CRT_HSYNC(24)
R55 0_0402_5%
R56 0_0402_5%
PLLVDD
HTPVDD
R62 0_0402_5%
1 2
LDT_STOP#_NB
R388 22_0402_5%@
1 2
R73 2.7K_0402_5%@
1 2
R60 2.7K_0402_5%@
1 2
R57 2.7K_0402_5%@
1 2
R58 2.7K_0402_5%@
1 2
R59 2.7K_0402_5%@
1 2
EDID_LCD_CLK(25)
EDID_LCD_DAT(25)
12
R377
4.7K_0402_5%
Security Classification
Issued Date
THIS SHEET OF ENG INEE RIN G DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY O R DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
+3VS
12
1
C487
4.7U_0805_10V4Z
2
VGA_TV_CRMA
VGA_TV_LUMA
VGA_TV_COMPS
VGA_CRT_VSYNC
VGA_CRT_HSYNC
1 2
R386 715_0402_1%
1 2
1 2
R383 10K_0402_5%
12
SB_OSC_INT_R
DFT_GPIO0
DFT_GPIO2
DFT_GPIO3
DFT_GPIO4
DFT_GPIO5
EDID_LCD_CLK
EDID_LCD_DAT
DDC_DATA
STRP_DATA
2005/05/09 2006/03/08
3
R575
4.7K_0402_5%
12
R576
4.7K_0402_5%
AA15
AB15
TP5PAD
R590
150_0402_1%
TV@
U39C
B22
AVDD1
C22
AVDD2
G17
AVSSN1
H17
AVSSN2
A20
AVDDDI
B20
AVSSDI
A21
AVDDQ
A22
AVSSQ
C21
C_R
C20
Y_G
D19
COMP_B
E19
RED
F19
GREEN
G19
BLUE
C6
DACVSYNC
A5
DACHSYNC
B21
RSET
B6
DACSCL
A6
DACSDA
A10
PLLVDD
B10
PLLVSS
B24
HTPVDD
B25
HTPVSS
C10
SYSRESET#
C11
POWERGOOD
C5
LDTSTOP#
B5
ALLOW_LDTSTOP
C23
HTTSTCLK
B23
HTREFCLK
C2
TVCLKIN
B11
OSCIN
A11
OSCOUT
F2
GFX_CLKP
E1
GFX_CLKN
G1
SB_CLKP
G2
SB_CLKN
D6
DFT_GPIO0
D7
DFT_GPIO1
C8
DFT_GPIO2
C7
DFT_GPIO3
B8
DFT_GPIO4
A8
DFT_GPIO5
B2
BMREQb
A2
I2C_CLK
B4
I2C_DATA
THERMALDIODE_P
THERMALDIODE_N
C14
TMDS_HPD
B3
DDC_DATA
C3
TESTMODE
A3
STRP_DATA
216MSA4ALA11FG RS485MC_BGA465
CRT/TVOUT
PLL PWR
PM
CLOCKs
MIS.
Compal Secret Data
Deciphered Date
12
12
R591
150_0402_1% TV@
PART 3 OF 5
2
VGA_TV_CRMA
VGA_TV_LUMA
VGA_TV_COMPS
12
R592
150_0402_1% TV@
TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N
TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N
TXCLK_LP
TXCLK_LN
TXCLK_UP
TXCLK_UN
LPVDD
LPVSS
LVDDR18D_1
LVDDR18D_2
LVDDR18A_1
LVDDR18A_2
LVSSR1
LVSSR3
LVSSR5
LVSSR6
LVSSR7
LVSSR8
LVSSR12
LVSSR13
LVDS_DIGON
LVDS_BLON
LVDS_BLEN
DVO_D0
DVO_D1
DVO_D2
DVO_D3
DVO_D4
DVO_D5
DVO_D6
DVO_D7
DVO_D8
DVO_D9
DVO_D10
DVO_D11
DVO_VSYNC
DVO_DE
DVO_HSYNC
DVO_IDCKP
DVO_IDCKN
2
B14
B15
B13
A13
H14
G14
D17
E17
A15
B16
C17
C18
B17
A17
A18
B18
E15
D15
H15
G15
D14
E14
A12
B12
C12
C13
A16
A14
D12
C19
C15
C16
F14
F15
E12
G12
F12
AD14
AD15
AE15
AD16
AE16
AC17
AD18
AE19
AD19
AE20
AD20
AE21
AD13
AC13
AE13
AE17
AD17
1
2005/12/30 Added
LVDS_TXLP0
LVDS_TXLN0
LVDS_TXLP1
LVDS_TXLN1
LVDS_TXLP2
LVDS_TXLN2
LVDS_TXUP0
LVDS_TXUN0
LVDS_TXUP1
LVDS_TXUN1
LVDS_TXUP2
LVDS_TXUN2
LVDS_TXLCKP
LVDS_TXLCKN
LVDS_TXUCKP
LVDS_TXUCKN
0.1U_0402_16V4Z
C171
1U_0603_10V4Z
ENVDD
ENBKL
TP4 PAD
Title
Size Document Number R ev
Custom
Date: Sheet
LVDS_TXLP0 (25)
LVDS_TXLN0 (25)
LVDS_TXLP1 (25)
LVDS_TXLN1 (25)
LVDS_TXLP2 (25)
LVDS_TXLN2 (25)
LVDS_TXUP0 (25)
LVDS_TXUN0 (25)
LVDS_TXUP1 (25)
LVDS_TXUN1 (25)
LVDS_TXUP2 (25)
LVDS_TXUN2 (25)
LVDS_TXLCKP (25)
LVDS_TXLCKN (25)
1
C172
C154
2
1U_0603_10V4Z
4.7U_0805_10V4Z
1
2
ENVDD (25)
ENBKL (28)
LVDS_TXUCKP (25)
LVDS_TXUCKN (25)
1
2
0.1U_0402_16V4Z
1
C176
2
R541 0_0805_5%
R542 0_0805_5%
1 2
1
C177
4.7U_0805_10V4Z
2
1
C481
2
1 2
1 2
L54
CHB2012U121_0805
LPVSS_GND
L57
1 2
CHB2012U121_0805
C491
0.1U_0402_16V4Z
1
C131
2
LPVSS_GND
Compal Electronics. inc.
SCHEMATIC, M/B LA-3121P
401411
星期三 五
10, 2006
月
1
RS485: LVDDR18A=1.8V
+1.8VS
12
+1.8VS
L55
CHB2012U121_0805
4.7U_0805_10V4Z
1U_0603_10V4Z
1
1
C497
2
2
LVSSR_GND
LVSSR_GND
14 51,
of
D
5
4
3
2
1
NB RS485 POWER STATES
Power Signal
VDDHT
VDDR
VDD18
D D
VDDC
VDDA18
VDDA12
AVDDDI
PLLVDD
HTPVDD
VDDR3
LPVDD
L63
CHB2012U121_0805
L64
CHB2012U121_0805
10U_0805_10V4Z
C C
1
C37
2
2006/4/14 FOR EMI
+1.8VS VDD18
L2
1 2
CHB2012U121_0805
820P_0603_50V7K
+1.8VS
L58
1 2
1
CHB2012U121_0805
+
C25
150U_D2_6.3VM
2
+3VS VDDR3
L3
1 2
CHB2012U121_0805
B B
+1.8VS
VDDA12
1U_0402_6.3V4Z
L1
1 2
CHB2012U121_0805
+1.2V_HT
12
12
CURRENT MEASUREMENT
1
1
C54
C46
2
2
1U_0402_6.3V4Z
C330
2.2U_0805_10V6K
10U_0805_10V4Z
1
C44
2
1
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
1
C141
2
2
1
1
C459
C40
2
2
10U_0805_10V4Z
1U_0402_6.3V4Z
1
C161
C160
4.7U_0805_10V4Z
2
VDDR
1
1
C42
C38
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
VDDPLL VDDA12_PKG1
4.7U_0805_10V4Z
1
1
C140
2
2
VDD_HT
1
C50
2
1U_0402_6.3V4Z
1
C142
2.2U_0805_10V6K
2
1
C460
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C43
2
C168
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C49
2
1U_0402_6.3V4Z
1
C462
2
1U_0402_6.3V4Z
1
C48
2
1
C123
2
VDDA18
1
C456
2
1U_0402_6.3V4Z
LVDDR18D
LVDDR18A OFFON ON OFF OFF
1
C461
2
+1.2V_HT
VDDA12_PKG1
+1.2V_HT
1
C134
10U_0805_10V4Z
2
AE24
AD24
AD22
AB17
AE23
W17
AC18
AD21
AC19
AC20
AB19
AD23
AA17
AE25
AC12
AD12
AE12
AC11
Y17
AE2
AB3
AB4
AC3
AD2
AE1
E11
D11
D22
J14
J15
U7
W7
E7
F7
F9
G9
M1
S3
S0
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
U39D
VDD_HT1
VDD_HT2
VDD_HT5
VDD_HT6
VDD_HT9
VDD_HT10
VDD_HT11
VDD_HT12
VDD_HT13
VDD_HT14
VDD_HT15
VDD_HT16
VDD_HT17
VDD_HT18
VDD_HT19
VDD18_1
VDD18_2
VDDA18_1
VDDA18_2
VDDA18_3
VDDA18_4
VDDA18_5
VDDA18_6
VDDA18_7
VDDA18_8
VDDR3_2
VDDR3_1
VDDR_1
VDDR_2
VDDR_3
VDDA12/VDDPLL_1
VDDA12/VDDPLL_2
VSSA12/VSSPLL_1
VSSA12/VSSPLL_2
VDDHT_PKG
VDDA12_PKG1
VDDA12_PKG2
216MSA4ALA11FG RS485MC_BGA465
S1
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
S4/S5
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFFAVDD
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
PART 4 OF 5
VDDA_12_10
VDDA_12_11
VDDA_12_12
POWER
VDDA_12_1
VDDA_12_2
VDDA_12_3
VDDA_12_4
VDDA_12_5
VDDA_12_6
VDDA_12_7
VDDA_12_8
VDDA_12_9
G3
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
VDDC_24
VDDC_25
VDDC_26
VDDC_27
VDDC_28
VDDC_29
VDDC_30
VDDC_31
VDDC_32
D1
G7
E2
C1
E3
D2
M9
F4
B1
D3
L9
E6
L11
L13
L15
M12
R15
M14
N11
N13
N15
J11
H11
P12
P14
R11
R13
A19
B19
U11
U14
P17
L17
J19
D20
G20
A9
B9
C9
D9
A7
A4
U12
U15
VDDA12
1U_0402_6.3V4Z
1
C110
2
10U_0805_10V4Z
1
C24
+
150U_D2_6.3VM
2
1
C130
2
1U_0402_6.3V4Z
1
C115
2
10U_0805_10V4Z
1
C31
10U_0805_10V4Z
2
CURRENT MEASUREMENT
1
1
C93
C112
10U_0805_10V4Z
2
2
1U_0402_6.3V4Z
1
2
1
C126
2
1U_0402_6.3V4Z
1
2
1U_0402_6.3V4Z
C87
1U_0402_6.3V4Z
C108
1U_0402_6.3V4Z
1 2
L59 CHB2012U121_0805
1 2
L60 CHB2012U121_0805
1
C106
10U_0805_10V4Z
2
1
1
C60
C94
2
2
1
2
1U_0402_6.3V4Z
1
C138
2
1U_0402_6.3V4Z
C135
+1.2V_HT
1
C79
1U_0402_6.3V4Z
2
+1.2V_HT
1
C75
+
150U_D2_6.3VM
2
U39E
A25
VSS1
AE18
M15
M11
M20
M23
M25
W23
AD25
W24
AC23
AC14
AC22
AE22
AE14
M17
AC15
AC16
M13
F11
D23
G11
Y23
P11
R24
G23
N12
N14
P13
P20
P15
R12
R14
R20
Y25
U20
H25
Y22
D25
G24
H12
R23
T23
T25
R17
H23
A23
F17
E9
J22
J12
L12
L14
L20
L23
B7
L24
C4
D4
PAR 5 OF 5
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
216MSA4ALA11FG RS485MC_BGA465
GROUND
VSSA1
VSSA2
VSSA3
VSSA4
VSSA5
VSSA6
VSSA7
VSSA8
VSSA9
VSSA10
VSSA11
VSSA12
VSSA13
VSSA14
VSSA15
VSSA16
VSSA17
VSSA18
VSSA19
VSSA20
VSSA21
VSSA22
VSSA23
VSSA24
VSSA25
VSSA26
VSSA27
VSSA28
VSSA29
VSSA30
VSSA31
VSSA32
VSSA33
VSSA34
VSSA35
VSSA36
VSSA93
VSSA94
VSSA95
VSSA37
VSSA38
VSSA39
VSSA40
VSSA41
VSSA42
VSSA43
VSSA44
VSSA45
M3
V12
V11
V14
F3
V15
A1
H1
G3
J2
H3
AE10
J6
AE6
F1
L6
M2
M6
J3
P6
T1
N3
P9
R6
U2
T3
U3
U6
AC4
Y1
Y15
W6
AC2
Y3
Y9
Y11
Y12
Y14
AA3
R9
AD1
AC5
AC6
AC7
AD3
AC9
AC10
G6
RS485: 0 Ohm RESISTOR
RS690: 220 Ohm 500mA FERRITE BEAD
A A
Security Classification
Issued Date
THIS SHEET OF ENG INEE RIN G DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY O R DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/05/09 2006/10/10
Compal Secret Data
Deciphered Date
Compal Electronics. inc.
Title
SCHEMATIC, M/B LA-3121P
Size Document Number R ev
Custom
401411
Date: Sheet
星期三 五
10, 2006
2
月
15 51,
1
D
of
5
4
3
2
1
R67
LOAD_ROM#(14)
D D
1 2
3K_0402_5% @
H1
H_S394D138
1
H2
H_S394D138
@
@
1
H4
H_S394D138
1
@
H21
H_S394D138
1
@
H22
H_S394D138
1
@
LOAD_ROM#: LOAD ROM ST RA P ENABLE
High, LOAD R O M STRAP DISABLE
Low, LOAD ROM STRAP ENABLE
C C
1
C653
@
2
0.1U_0402_16V4Z
1
C654
@
2
0.1U_0402_16V4Z
+3VS+5VS +1.8VALW +1.8VS+3VALW+5VS +3VS+1.8VALW
1
C655
@
2
0.1U_0402_16V4Z
1
C656
@
2
0.1U_0402_16V4Z
H23
H_S394D138
@
1
H8
H_C236D165
@
1
H29
H_C236D161
@
1
H18
H_O134X118D55X39
@
1
H25
H_S354D138
@
1
H14
H_S394D138
@
1
H9
H_C236D165
@
1
H31
H_S315D118
@
1
H16
H_C276D118
@
1
H32
H_S315D138
@
1
H15
H_S394D138
@
1
H10
H_C236D165
@
1
H11
H_O134X118D55X39
@
1
H19
H_C276D118
@
1
H33
H_C315D236
@
1
H28
H_S394D138
@
1
H3
H_C236D161
@
1
H12
H_O134X118D55X39
@
1
H13
H_S354D138
@
1
H35
H_C163D163N
@
1
H7
H_C236D165
@
1
H6
H_C236D161
@
1
H17
H_O134X118D55X39
@
1
H24
H_S354D138
@
1
H34
H_O217X157D217X157N
@
1
B B
FD4
FD1
FD2
@
1
1
CF20
CF8
@
1
1
CF1
CF9
@
1
1
A A
FD5
FD3
@
@
1
1
CF21
@
@
CF2
1
CF3
@
1
1
Security Classification
Issued Date
THIS SHEET OF ENG INEE RIN G DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY O R DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
FD6
@
@
@
@
CF7
CF5
@
1
1
CF12
CF10
@
1
1
CF11
@
1
1
3
CF4
CF6
@
@
@
@
1
2005/05/09 2006/03/08
@
1
1
Compal Secret Data
Deciphered Date
Compal Electronics. inc.
Title
SCHEMATIC, M/B LA-3121P
Size Document Number R ev
Custom
401411
Date: Sheet
星期三 五
10, 2006
2
月
16 51,
1
D
of
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