Acer Aspire 3040, Aspire 5040 Schematics

See 'TEXT' in 0MEMO or 1MEMO property in component

5

4

3

2

1

Dummy when use '10/100'

Dummy when use 'GIGA'

Dummy when use 'UMA'

D D

Dummy when use 'DIS'

Dummy when use 'SATA'

Dummy when use 'IDE'

CLK GEN

IDT CV137

LEDs

RTC BAT.

PWR SW

CP2211

PCMCIA SLOT

Support TypeII

26

MS/MS Pro/xD/

C C

MMC/SD

5 in 1

PCMCIA I/F

28

26

RICOH

BUTTONs

ENE

CB1410

1* Slot Cardbus

25

R5C832

1394 CONN

28

Mini-PCI

802.11a/b/g

29

RJ45

31

B B

TXFM

1394

CardReader

31

27,28

1000Mb

10/100Mb

PCI Bus / 33MHz

PCI LAN

Realtek RTL8110SBL 1000/100/10 RTL8100C 100/10

Bolsena-E(AB2) Block Diagram

AMD CPU

3

16 17 33

35W/25W

4,5,6,7

HyperTransport

6.4GB/S 16b/8b

ATI

RS482M

AGTL+ CPU I/F + UMA

11,12,13,14

PCI-Express x2

PCI Express x16

ATI

SB450

ACPI 2.0

PCI

30

ATA 133

6xUSB 2.0

AZALIA

LPC I/F

17,18,19,20,21

DDR 333/400

USB x 4

24

AZALIA

MODEM MDC Card

LPC Bus / 33MHz

ATI

M52P

49,50,51,52,53

VRAM x4

54,55

RJ11 CONN

31

200-PIN DDR SODIMM

DDR x2

CODEC

ALC883

OP AMP

G1421

8,9,10

RGB CRT

32

3323

LVDS

tv

LCD

CRT

BlueTooth miniUSB

Line In MIC In

Line Out

Int. SPKR

16

15

23

3

33

Project Code: 91.4G401.001 REVISION: 05236-SA

PCB Layer Stackup

L1: Signal 1 L2:VCC L3: Signal 2 L4: Signal 3 L5: GND L6: Signal 4

Power Block Diag -> Page 40

NS SIO

PC87381

37

SATA

PIDE

HDD

24

SIDE

DVD/ CD-RW

24

FIR

TFDU6102

A A

5

4

3

37

2

Thermal & Fan

G792

KBC

23

Title

Size Document Number Rev

Date: Sheet

KB3910

Touch Pad

35 35

BLOCK DIAGRAM

A3

Bolsena-E

Int. KB

XBUS

34

ISA ROM

36

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

158Thursday, October 13, 2005

1

of

SA

5

4

3

2

1

PCI Routing

IRQ

MiniPCI

LAN

D D

21 23 2 22 17411 E (CardBus)

F H

17 37411 G (1394) 17 37411 E (FlashMedia)

C C

REQ/GNTIDSEL

0

B B

Ref. function schematic BOM

------------------------U81 cpu socket 62.10055.121 (DON'T CHANGE) (3mm high) U80 north bridge 71.RS482.M03 71.RS482.M03 (ver A12) U43 south bridge 71.SB400.B0U 71.SB400.D0U (ver A13) U32 clock gen. 71.00137.C0W 71.00137.C0W

--U70 VGA M52 71.0M52P.A0U U64 VRAM FOR M52 U65 VRAM FOR M52 U69 VRAM FOR M52 U71 VRAM FOR M52

--U66 BIOS SOCKET 72.39040.G03 62.10002.032 (NO NEED WHEN PD)

A A

U66 BIOS IC 72.39040.G03 72.39040.H03 (DIP STAGE IN LAB, SMT IN PD)

--U75 GIGA LAN 71.08110.00G 71.08110.A0G U75 10/100 LAN 71.08110.00G 71.08100.C0G

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

HISTORY

Bolsena-E

258Thursday, October 13, 2005

of

1

of

SA

A

3D3V_S0

L13

1 2

0R0603-PAD

4 4

SMBD_SB8,20

3 3

SMBC_SB8,20

12

C490

C490 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

C485

C485 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

C476

C476 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

C486

C486 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

C443

C443 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

C489

C489 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

RN48 SRN33J-5-GP-URN48 SRN33J-5-GP-U

1 2

CLK48_USB20

2 3 1

12

C445

C445 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

C488

C488 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C459

SC33P50V2JN-3GP

X-14D318MHZ-18GP

1 2

C472

SC33P50V2JN-3GP

4

CLK14_NB13

SB_OSC_CLK20 CLK14_SIO37

B

12

C444

C444 SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

3D3V_CLK_VDDA

3D3V_S0 3D3V_CLK_VDD

3D3VDD48_S0

12

C446

C446 SC2D2U16V5ZY-GP

SC2D2U16V5ZY-GP

12

R223

R223 DUMMY-R3

DUMMY-R3

USB_48M SMBC_CLK SMBD_CLK

R218 22R2J-2-GPR218 22R2J-2-GP

1 2

2 3 1

RN54 SRN33J-5-GP-URN54 SRN33J-5-GP-U

1 2

12

R242 33R2J-2-GPR242 33R2J-2-GP

1 2

75R2F-2-GP

R241

R249

R249 100R2F-L1-GP-U

100R2F-L1-GP-U

4

IREF_CLKGEN

12

FS2 FS1 FS0

CLK_HTT66

R240

R240 475R2F-L1-GP

475R2F-L1-GP

X2

HTREF_CLK13

1 2

0R0603-PAD

XI_CLK

XO_CLK

L14

U23

3

VDD_48

39

VDDA

32

VDD_SRC

21

VDD_SRC

14

VDD_SRC

35

VDD_SRC

56

VDD_REF

51

VDD_PC1

43

VDD_CPU

48

VDD_HTT

1

XIN

2

XOUT

4

USB_48

7

SCL

8

SDA

10

CLKREQ0#

11

CLKREQ1#

9

SEL24/24_48#

53

REF1

54

REF0

52

REF2

47

HTT66

50

PCI0

37

IREF

6

NC#6

IDTCV137PAG-2-GP

71.00137.C0W

C

SRCC0 SRCT0 SRCC3 SRCT3 SRCC4 SRCT4 SRCC5 SRCT5 SRCC6 SRCT6 SRCC7 SRCT7

CPUC1 CPUT1 CPUC0 CPUT0

SRCC1 SRCT1 SRCC2 SRCT2

VSS_SRC VSS_SRC

RESET#

TURBO1

VSS_CPU

VSS_PCI

VSS_HTT

VSS_SRC

VSS_48

VSS_REF

VSSA

33 34 25 24 23 22 19 18 17 16 13 12

40 41 44 45

29 30 28 27

36 20 15 26

42 49 46 31 38 5 55

3D3V_CLK_VDDA3D3V_CLK_VDD

SRC_CLK0# SRC_CLK0 SRC_CLK3# SRC_CLK3

CPUCLKJ_CY CPUCLK_CY

12

C487

SCD1U16V2ZY-2GP

ATI_CLK0# ATI_CLK0 ATI_CLK1# ATI_CLK1

3D3V_S0

L15

1 2

0R0603-PAD

12

C496

C496 SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

2 3 1

1 2 3

R247 15R2J-L1-GPR247 15R2J-L1-GP

1 2

R248 15R2J-L1-GPR248 15R2J-L1-GP

1 2

RN52

2 3 1

4

SRN33J-5-GP-U

RN46

1

4

2 3

SRN33J-5-GP-U

Dummy when use UMA

D

RN53

SRN33J-5-GP-U

4

RN47

4

SRN33J-5-GP-U

CPUCLK# 6

CPUCLK 6

NBSRC_CLK# 13 NBSRC_CLK 13

GFX_CLK# 49 GFX_CLK 49

SBLINK_CLK# 13 SBLINK_CLK 13

SBSRC_CLK# 17 SBSRC_CLK 17

SBLINK_CLK SBLINK_CLK#

SBSRC_CLK# SBSRC_CLK

GFX_CLK# GFX_CLK

E

RN58

2 3 1

RN38

2 3 1

RN37

1 2 3

SRN49D9F-GP

4

SRN49D9F-GP

4

SRN49D9F-GP

4

Dummy when use UMA

2 2

SRN49D9F-GP

RN57

NBSRC_CLK# NBSRC_CLK

3D3V_CLK_VDD

DY

R245

1 2

2K2R2J-2-GP

1 2

DUMMY-R2

R246

R243

1 2

1 1

R216

1 2 1 2

2K2R2J-2-GP

DUMMY-R2

R244

2K2R2J-2-GP

2K2R2J-2-GP DUMMY-R2

DUMMY-R2

R217

DY

for ICS

A

FS0

FS1

FS2

Title

Size Document Number Rev

A3

Date: Sheet

B

C

D

Date: Sheet

CLKGEN_IDTCV137

Bolsena-E

RN57

2 3 1

4

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

358Thursday, October 13, 2005

of

E

of

SA

A

4 4

B

C

D

E

HTT for CPU sideA Transmit power and NB sideA Receive power

1D2V_S0

12

3 3

C289

C289 SCD22U16V3ZY-GP

SCD22U16V3ZY-GP

12

C268

C268 SCD22U16V3ZY-GP

SCD22U16V3ZY-GP

12

C273

C273 SCD22U16V3ZY-GP

SCD22U16V3ZY-GP

NB0CADOUT[15..0]11 NB0CADOUTJ[15..0]11

Used SideB Power Plane

2 2

1D2V_HT0B_S0

12

C269

C269 SCD22U16V3ZY-GP

SCD22U16V3ZY-GP

NB0HTTCLKOUT111 NB0HTTCLKOUTJ111 NB0HTTCLKOUT011 NB0HTTCLKOUTJ011

R141 49D9R2F-GPR141 49D9R2F-GP

1 2

R140 49D9R2F-GPR140 49D9R2F-GP

1 2

NB0HTTCTLOUT11 NB0HTTCTLOUTJ11

NB0CADOUT15 NB0CADOUTJ15 NB0CADOUT14 NB0CADOUTJ14 NB0CADOUT13 NB0CADOUTJ13 NB0CADOUT12 NB0CADOUTJ12 NB0CADOUT11 NB0CADOUTJ11 NB0CADOUT10 NB0CADOUTJ10 NB0CADOUT9 NB0CADOUTJ9 NB0CADOUT8 NB0CADOUTJ8 NB0CADOUT7 NB0CADOUTJ7 NB0CADOUT6 NB0CADOUTJ6 NB0CADOUT5 NB0CADOUTJ5 NB0CADOUT4 NB0CADOUTJ4 NB0CADOUT3 NB0CADOUTJ3 NB0CADOUT2 NB0CADOUTJ2 NB0CADOUT1 NB0CADOUTJ1 NB0CADOUT0 NB0CADOUTJ0

NB0HTTCLKOUT1 NB0HTTCLKOUTJ1 NB0HTTCLKOUT0 NB0HTTCLKOUTJ0

CPUHTTCTLIN1 CPUHTTCTLINJ1 NB0HTTCTLOUT NB0HTTCTLOUTJ

W27

W26 AA27 AA26 AB25 AA25 AC27 AC26 AD25 AC25

W29 AB29 AA29 AB27 AB28 AD29 AC29 AD27 AD28

W25

D29 D27 D25 C28 C26 B29 B27

T25 R25 U27 U26 V25 U25

T27 T28 V29 U29 V27 V28 Y29

Y25 Y27

Y28 R27

R26 T29 R29

U62A

VLDT0_A VLDT0_A VLDT0_A VLDT0_A VLDT0_A VLDT0_A VLDT0_A

L0_CADIN_H15 L0_CADIN_L15 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H0 L0_CADIN_L0

L0_CLKIN_H1 L0_CLKIN_L1 L0_CLKIN_H0 L0_CLKIN_L0

L0_CTLIN_H1 L0_CTLIN_L1 L0_CTLIN_H0 L0_CTLIN_L0

62.10055.121

VLDT0_B VLDT0_B VLDT0_B VLDT0_B VLDT0_B VLDT0_B VLDT0_B

L0_CADOUT_H15

L0_CADOUT_L15

L0_CADOUT_H14

L0_CADOUT_L14

L0_CADOUT_H13

L0_CADOUT_L13

L0_CADOUT_H12

L0_CADOUT_L12

L0_CADOUT_H11

L0_CADOUT_L11

L0_CADOUT_H10

L0_CADOUT_L10

L0_CADOUT_H9

L0_CADOUT_L9

L0_CADOUT_H8

L0_CADOUT_L8

L0_CADOUT_H7

L0_CADOUT_L7

L0_CADOUT_H6

L0_CADOUT_L6

L0_CADOUT_H5

L0_CADOUT_L5

L0_CADOUT_H4

L0_CADOUT_L4

L0_CADOUT_H3

L0_CADOUT_L3

L0_CADOUT_H2

L0_CADOUT_L2

L0_CADOUT_H1

L0_CADOUT_L1

L0_CADOUT_H0

L0_CADOUT_L0 L0_CLKOUT_H1

L0_CLKOUT_L1

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CTLOUT_H1

L0_CTLOUT_L1

L0_CTLOUT_H0

L0_CTLOUT_L0

AH29 AH27 AG28 AG26 AF29 AE28 AF25

N26 N27 L25 M25 L26 L27 J25 K25 G25 H25 G26 G27 E25 F25 E26 E27 N29 P29 M28 M27 L29 M29 K28 K27 H28 H27 G29 H29 F28 F27 E29 F29

J26 J27 J29 K29

N25 P25 P28 P27

CPUCADOUT15 CPUCADOUTJ15 CPUCADOUT14 CPUCADOUTJ14 CPUCADOUT13 CPUCADOUTJ13 CPUCADOUT12 CPUCADOUTJ12 CPUCADOUT11 CPUCADOUTJ11 CPUCADOUT10 CPUCADOUTJ10 CPUCADOUT9 CPUCADOUTJ9 CPUCADOUT8 CPUCADOUTJ8 CPUCADOUT7 CPUCADOUTJ7 CPUCADOUT6 CPUCADOUTJ6 CPUCADOUT5 CPUCADOUTJ5 CPUCADOUT4 CPUCADOUTJ4 CPUCADOUT3 CPUCADOUTJ3 CPUCADOUT2 CPUCADOUTJ2 CPUCADOUT1 CPUCADOUTJ1 CPUCADOUT0 CPUCADOUTJ0

CPUHTTCLKOUT1 CPUHTTCLKOUTJ1 CPUHTTCLKOUT0 CPUHTTCLKOUTJ0

CPUHTTCTLOUT0 CPUHTTCTLOUTJ0

HTT for CPU sideB Receive power and NB sideA Transmit power

1D2V_HT0B_S0

12

Used SideA Power Plane

CPUHTTCLKOUT1 11 CPUHTTCLKOUTJ1 11 CPUHTTCLKOUT0 11 CPUHTTCLKOUTJ0 11

CPUHTTCTLOUT0 11 CPUHTTCTLOUTJ0 11

LAYOUT: Place bypass cap on topside of board near

C267

C267 SC4D7U10V5ZY-3GP

SC4D7U10V5ZY-3GP

HTT power pins that are not connected directly to downstream HTT device, but connected internally to other HTT power pins.

CPUCADOUT[15..0] 11 CPUCADOUTJ[15..0] 11

ME : 62.10055.121

1 1

A

B

2nd:62.10055.101

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

C

D

Date: Sheet

CPU(1/4)_HyperTransport I/F

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

SA

458Thursday, October 13, 2005

of

E

of

SA

A

VREF_DDR_MEM

B

C

D

E

NOTE: Test with passive probes only. NOTE: Install to bypass op-amp

2D5V_S3

4 4

12

R222

R222 100R2F-L1-GP-U

100R2F-L1-GP-U

R229

R229 100R2F-L1-GP-U

100R2F-L1-GP-U

C470

C470 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

VREF_DDR_MEM

12

C474

C474 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C473

C473 SC1000P50V2JN-N1

SC1000P50V2JN-N1

2D5V_S3

M_DATA[63..0]9

1 2 1 2

LAYOUT: Locate close to DIMMs.

NOTE: Remove to bypass op-amp

3 3

VREF_DDR_CLAW

2D5V_S3

12

2 2

Place it near CPU

1 1

12

R166

R166 100R2F-L1-GP-U

100R2F-L1-GP-U

R162

R162 100R2F-L1-GP-U

100R2F-L1-GP-U

C348

C348 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

VREF_DDR_CLAW

C338

C338 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

LAYOUT: Locate close to CPU.

R173

1 2

R168

1 2

R172

1 2

R167

1 2

121R2F-GP

A

M_CLK7 M_CLK#7

M_CLK6 M_CLK#6

M_CLK5 M_CLK#5

M_CLK4 M_CLK#4

12

C349

C349 SC1000P50V2JN-N1

SC1000P50V2JN-N1

M_ADM[7..0]9

M_DQS[7..0]9

B

TP44TPAD30 TP44TPAD30

VREF_DDR_CLAW

R169 34D8R2F-N1-GPR169 34D8R2F-N1-GP R163 34D8R2F-N1-GPR163 34D8R2F-N1-GP

DDRVTT_SENSE

MEMZN MEMZP

M_DATA63 M_DATA62 M_DATA61 M_DATA60 M_DATA59 M_DATA58 M_DATA57 M_DATA56 M_DATA55 M_DATA54 M_DATA53 M_DATA52 M_DATA51 M_DATA50 M_DATA49 M_DATA48 M_DATA47 M_DATA46 M_DATA45 M_DATA44 M_DATA43 M_DATA42 M_DATA41 M_DATA40 M_DATA39 M_DATA38 M_DATA37 M_DATA36 M_DATA35 M_DATA34 M_DATA33 M_DATA32 M_DATA31 M_DATA30 M_DATA29 M_DATA28 M_DATA27 M_DATA26 M_DATA25 M_DATA24 M_DATA23 M_DATA22 M_DATA21 M_DATA20 M_DATA19 M_DATA18 M_DATA17 M_DATA16 M_DATA15 M_DATA14 M_DATA13 M_DATA12 M_DATA11 M_DATA10 M_DATA9 M_DATA8 M_DATA7 M_DATA6 M_DATA5 M_DATA4 M_DATA3 M_DATA2 M_DATA1 M_DATA0

M_ADM8 M_ADM7 M_ADM6 M_ADM5 M_ADM4 M_ADM3 M_ADM2 M_ADM1 M_ADM0 M_DQS8 M_DQS7 M_DQS6 M_DQS5 M_DQS4 M_DQS3 M_DQS2 M_DQS1 M_DQS0

AE13

AG12

D14 C14

A16 B15 A12 B11 A17 A15 C13 A11 A10

C11

AC1 AC3

AC2 AD1 AE1 AE3

AG3

AJ4

AE2

AF1

AH3

AJ3 AJ5 AJ6

AJ7 AH9 AG5 AH5

AJ9

AJ10

AH11

AJ11

AH15

AJ15

AG11

AJ12 AJ14 AJ16

A13

AA1 AG1 AH7

AH13

A14

AB1

AJ2

AJ8

AJ13

B9 C7 A6

A9 A5 B5 C5 A4 E2 E1 A3 B3 E3

F1 G2 G1

L3

L1 G3

J2

L2 M1 W1 W3

W2

Y1

R1

A7

C2

H1

T1

A8

D1

J1

VTT_SENSE

MEMVREF1 MEMZN

MEMZP

MEMDATA63 MEMDATA62 MEMDATA61 MEMDATA60 MEMDATA59 MEMDATA58 MEMDATA57 MEMDATA56 MEMDATA55 MEMDATA54 MEMDATA53 MEMDATA52 MEMDATA51 MEMDATA50 MEMDATA49 MEMDATA48 MEMDATA47 MEMDATA46 MEMDATA45 MEMDATA44 MEMDATA43 MEMDATA42 MEMDATA41 MEMDATA40 MEMDATA39 MEMDATA38 MEMDATA37 MEMDATA36 MEMDATA35 MEMDATA34 MEMDATA33 MEMDATA32 MEMDATA31 MEMDATA30 MEMDATA29 MEMDATA28 MEMDATA27 MEMDATA26 MEMDATA25 MEMDATA24 MEMDATA23 MEMDATA22 MEMDATA21 MEMDATA20 MEMDATA19 MEMDATA18 MEMDATA17 MEMDATA16 MEMDATA15 MEMDATA14 MEMDATA13 MEMDATA12 MEMDATA11 MEMDATA10 MEMDATA9 MEMDATA8 MEMDATA7 MEMDATA6 MEMDATA5 MEMDATA4 MEMDATA3 MEMDATA2 MEMDATA1 MEMDATA0

MEMDQS17 MEMDQS16 MEMDQS15 MEMDQS14 MEMDQS13 MEMDQS12 MEMDQS11 MEMDQS10 MEMDQS9 MEMDQS8 MEMDQS7 MEMDQS6 MEMDQS5 MEMDQS4 MEMDQS3 MEMDQS2 MEMDQS1 MEMDQS0

U62BU62B

MEMRESET_L

MEMCLK_H7 MEMCLK_L7 MEMCLK_H6 MEMCLK_L6 MEMCLK_H5 MEMCLK_L5 MEMCLK_H4 MEMCLK_L4 MEMCLK_H3 MEMCLK_L3 MEMCLK_H2 MEMCLK_L2 MEMCLK_H1 MEMCLK_L1 MEMCLK_H0 MEMCLK_L0

MEMCS_L7 MEMCS_L6 MEMCS_L5 MEMCS_L4 MEMCS_L3 MEMCS_L2 MEMCS_L1 MEMCS_L0

MEMRASA_L MEMCASA_L

MEMWEA_L

MEMBANKA1 MEMBANKA0

MEMADDA13 MEMADDA12 MEMADDA11 MEMADDA10

MEMADDA9 MEMADDA8 MEMADDA7 MEMADDA6 MEMADDA5 MEMADDA4 MEMADDA3 MEMADDA2 MEMADDA1 MEMADDA0

MEMRASB_L MEMCASB_L

MEMWEB_L

MEMBANKB1 MEMBANKB0

MEMADDB13 MEMADDB12 MEMADDB11 MEMADDB10

MEMADDB9 MEMADDB8 MEMADDB7 MEMADDB6 MEMADDB5 MEMADDB4 MEMADDB3 MEMADDB2 MEMADDB1 MEMADDB0

MEMCHECK7 MEMCHECK6 MEMCHECK5 MEMCHECK4 MEMCHECK3 MEMCHECK2 MEMCHECK1 MEMCHECK0

C

VTT_A VTT_A VTT_A VTT_A VTT_B VTT_B VTT_B VTT_B

MEMCKEA MEMCKEB

NC_E13 NC_C12

NC_E14 NC_D12

D17 A18 B17 C17 AF16 AG16 AH16 AJ17

AG10 AE8

AE7 D10

C10 E12 E11 AF8 AG8 AF10 AE10 V3 V4 K5 K4 R5 P5 P3 P4

D8 C8 E8 E7 D6 E6 C4 E5

H5 D4 G5

K3 H3

E13 C12 E10 AE6 AF3 M5 AE5 AB5 AD3 Y5 AB4 Y3 V5 T5 T3 N5

H4 F5 F4

L5 J5

E14 D12 E9 AF6 AF4 M4 AD5 AC5 AD4 AA5 AB3 Y4 W5 U5 T4 M3

N3 N1 U3 V1 N2 P1 U1 U2

1D25V_S3

MEMRESET# M_CKE#0

M_CKE#1 M_CLK7

M_CLK#7 M_CLK6 M_CLK#6 M_CLK5 M_CLK#5 M_CLK4 M_CLK#4

M_CLK1 M_CLK#1 M_CLK0 M_CLK#0

M_CS#7 M_CS#6 M_CS#5 M_CS#4 M_CS#3 M_CS#2 M_CS#1 M_CS#0

M_ARAS# M_ACAS# M_AWE#

M_ABS#1 M_ABS#0

RSVD_M_AA15 RSVD_M_AA14 M_AA13 M_AA12 M_AA11 M_AA10 M_AA9 M_AA8 M_AA7 M_AA6 M_AA5 M_AA4 M_AA3 M_AA2 M_AA1 M_AA0

M_BRAS# M_BCAS# M_BWE#

M_BBS#1 M_BBS#0

RSVD_M_BA15 RSVD_M_BA14 M_BA13 M_BA12 M_BA11 M_BA10 M_BA9 M_BA8 M_BA7 M_BA6 M_BA5 M_BA4 M_BA3 M_BA2 M_BA1 M_BA0

CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0

12

For REGISTED DIMM Only UNBUFFER DIMM NC

12

C309

M_CKE#0 8,9 M_CKE#1 8,9

M_CLK7 8 M_CLK#7 8 M_CLK6 8 M_CLK#6 8 M_CLK5 8 M_CLK#5 8 M_CLK4 8 M_CLK#4 8

M_CS#3 8,9 M_CS#2 8,9 M_CS#1 8,9 M_CS#0 8,9

M_ARAS# 8,9 M_ACAS# 8,9 M_AWE# 8,9

M_ABS#1 8,9 M_ABS#0 8,9

M_BRAS# 8,9 M_BCAS# 8,9 M_BWE# 8,9

M_BBS#1 8,9 M_BBS#0 8,9

TP58

TPAD30

TP117

TPAD30

TP57

TPAD30

TP110

TPAD30

TP116

TPAD30

TP115

TPAD30

TP111

TPAD30

TP112

TPAD30

C309 SC1000P50V2JN-N1

SC1000P50V2JN-N1

M_CLK#1 M_CLK#0 M_CLK1 M_CLK0

M_AA[13..0] 8,9

M_BA[13..0] 8,9

Title

Size Document Number Rev

A3

Date: Sheet

C320

C320 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

AMD suggested M_AA13 connect to DIMM pin123

AMD suggested M_BA13 connect to DIMM pin123

D

2D5V_S3

RN29

1

8

2

7

3

6

45

SRN10KJ-6-GP

M_DQS8 M_ADM8

MEMRESET# M_CS#7 M_CS#6 M_CS#5 M_CS#4 RSVD_M_AA15 RSVD_M_AA14 RSVD_M_BA15 RSVD_M_BA14

TP113TPAD30TP113TPAD30 TP114TPAD30TP114TPAD30

TP50 TPAD30TP50 TPAD30 TP53 TPAD30TP53 TPAD30 TP56 TPAD30TP56 TPAD30 TP54 TPAD30TP54 TPAD30 TP55 TPAD30TP55 TPAD30 TP46 TPAD30TP46 TPAD30 TP48 TPAD30TP48 TPAD30 TP41 TPAD30TP41 TPAD30 TP47 TPAD30TP47 TPAD30

NOT SUPPORT ECC CHECK AMD suggested remove PULL-HI resistor.

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU(2/4)_DDR

Bolsena-E

558Thursday, October 13, 2005

E

SA

of

SA

A

2D5V_VDDA_S0

2D5V_S0

4 4

2D5V_CPUA_S0

R139

1 2

0R0603-PAD

12

C262

C262 SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

1 2

DY

R136

0R3J-3-GP

2D5V_CPUR_S0

1 2

0R0805-PAD

12

TC8

ST100U4VBM-U

AMD SUGGEST TO USE 2D5V_CPUA_S0

KEMET,NT:5.7, B2 size ST100U4VBM-1 (80.10716.321)

3 3

2D5V_S0

2 2

DY

DBREQJ DBRDY TCK TMS TDI TRST_L TDO

2D5V_S3

CHANGE FROM 1KR3 TO 680R2 FOR AMD CHECK LIST

NC_AG17 NC_AJ18 NC_D18

NC_B19

1 1

NC_C19 NC_D20 NC_C21

Iripple=1.1A,ESR=70mohm

SANYO, NT$:6.1 Iripple=1.1A,ESR=70mohm

3.5/2.8/2.0

77.21071.031

678

RN21

12

C234

C234 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

R164

1 2

1 2 3 4 5

RN21

123

4 5

680R3F-GP

DY

RN23 SRN680J-GPRN23 SRN680J-GP

8 7 6

RN25

SRN680J-GP

A

DY

SRN680J-GP

AMD SUGGEST TO USE 100 ~ 300UH

LAYOUT: Route trace 50 mils wide and 500 to 750 mils long between these caps.

12

C286

C286 SC4D7U10V5ZY-3GP

SC4D7U10V5ZY-3GP

1D2V_HT0B_S0

12

R120

R119

680R3F-GP

DY

R143

2D5V_VDDA_S0

12

R133 44D2R2F-L1-GPR133 44D2R2F-L1-GP

1 2

R134 44D2R2F-L1-GPR134 44D2R2F-L1-GP

1 2

AMD suggest voltege from 2D5V_S0 to 2D5V_S3

differentially impedance 100

B

3D3V_S0

12

C242

C242 SC1U10V3KX-3GP

SC1U10V3KX-3GP

DY

2D5V_S0

DY

LDT_RST#17 SB_CPUPWRGD17 LDT_STP#13,17

1 2

1D25V_S3

2D5V_S0

SRN680J-GP

LDT_RST# SB_CPUPWRGD LDT_STP#

12

C288

C288 SC3300P50V2KX-1GP

SC3300P50V2KX-1GP

12

C256

C256 SC1000P50V2JN-N1

SC1000P50V2JN-N1

2D5V_S3

R518 820R3-GPR518 820R3-GP

1 2

R514 820R3-GPR514 820R3-GP

1 2

R154 680R3F-GPR154 680R3F-GP

1 2

R158 680R3F-GPR158 680R3F-GP

1 2

R512 680R3F-GPR512 680R3F-GP

1 2

LAYOUT: Route VDDA trace approx. 50 mils wide (use 2x25 mil traces to exit ball field) and 500 mils long.

12

C287

C287 SCD22U16V3ZY-GP

SCD22U16V3ZY-GP

12

C257

C257 SC1000P50V2JN-N1

SC1000P50V2JN-N1

CPUCLK3

CPUCLK#3

Validation Test Points

NC_C15 NC_AE23 NC_AF23 NC_AF22 NC_AF21

B

LAYOUT: Place close to the CPU.

TP42

TPAD30

TP33

TPAD30

TP31

TPAD30

TP32

TPAD30

TP38

TPAD30

LDT_RST# CLKIN CLKIN# CORE_SENSE VDDIOFB VDDIOFBJ VDDIOSENSE NC_AE24 NC_AF24

C

Iomax=120mA

U57

1

SHDN#

2

GND

3

IN

G913CF-GP

DY

COREFB41

COREFB#41

C803

C803 SC3900P50V3KX-GP

SC3900P50V3KX-GP

C796

C796 SC3900P50V3KX-GP

SC3900P50V3KX-GP

R159

1 2

R156

1 2

RN22

123

C

L0_REF1 L0_REF0

COREFB COREFB# CORE_SENSE

VDDIOFB VDDIOFBJ VDDIOSENSE

CLKIN

12

R519

R519 169R2F-GP

169R2F-GP

CLKIN# NC_AJ23 NC_AH23 NC_AE24 NC_AF24

DBRDY NC_C15 TMS

TCK TRST_L TDI

680R3F-GP

680R3F-GP 680R3F-GP

680R3F-GP

NC_AE23 NC_AF23 NC_AF22 NC_AF21

678

4 5

TP37

TP37 TP35

TP35 TP36

TP36 TP34

TP34 TP45

TP45 TP43

TP43 TP51

TP51 TP30

TP30 TP29

TP29

SET

OUT

DY

TPAD30

TPAD30 TPAD30

TPAD30

2D5V_CPUA_S0

2D5V_VDDA_VREF

5 4

DY

NC_C18 NC_A19

12

DY

12

C768

C768 SC1U10V3KX-3GP

SC1U10V3KX-3GP

U62CU62C

AH25

VDDA1

AJ25

VDDA2

AF20

RESET_L

AE18

PWROK

AJ27

LDTSTOP_L

AF27

L0_REF1

AE26

L0_REF0

A23

COREFB_H

A24

COREFB_L

B23

CORE_SENSE

AE12

VDDIOFB_H

AF12

VDDIOFB_L

AE11

VDDIO_SENSE

AJ21

CLKIN_H

AH21

CLKIN_L

AJ23

NC_AJ23

AH23

NC_AH23

AE24

NC_AE24

AF24

NC_AF24

C16

VTT_A

AG15

VTT_B

AH17

DBRDY

C15

NC_C15

E20

TMS

E17

TCK

B21

TRST_L

A21

TDI

C18

NC_C18

A19

NC_A19

A28

KEY1

AJ28

KEY0

AE23

NC_AE23

AF23

NC_AF23

AF22

NC_AF22

AF21

NC_AF21

C1

NC_C1

J3

NC_J3

R3

NC_R3

AA2

NC_AA2

D3

NC_D3

AG2

NC_AG2

B18

NC_B18

AH1

NC_AH1

AE21

NC_AE21

C20

NC_C20

AG4

NC_AG4

C6

NC_C6

AG6

NC_AG6

AE9

NC_AE9

AG9

NC_AG9

12

R509

R509 20KR2F-L-GP

20KR2F-L-GP

C767

C767 SC22P50V2JN-4GP

SC22P50V2JN-4GP

12

R129

R129 20KR2F-L-GP

20KR2F-L-GP

DY

D

R1

Vout = 1.25*(1+ R1/R2)

R2

THERMTRIP#

THERMDA THERMDC

VID4 VID3 VID2 VID1 VID0

NC_AG18 NC_AH18 NC_AG17

NC_AJ18

DBREQ_L

NC_D20 NC_C21 NC_D18 NC_C19 NC_B19

TDO

NC_AF18

A20 A26

A27 AG13

AF14 AG14 AF15 AE15

AG18 AH18 AG17 AJ18

AH19 AJ19

AE19 D20

C21 D18 C19 B19

A22

AF18

VID4 VID3 VID2 VID1 VID0

NC_AG18 NC_AH18 NC_AG17 NC_AJ18

NC_D20 NC_C21 NC_D18 NC_C19 NC_B19

TDO

THERMTRIP_L

FBCLKOUT_H

FBCLKOUT_L

Connect to VDDIO for AMD suggest.

D22

NC_D22

C22

NC_C22

B13

NC_B13

B7

NC_B7

C3

NC_C3

K1

NC_K1

R2

NC_R2

AA3

NC_AA3

F3

NC_F3

C23

NC_C23

AG7

NC_AG7

AE22

NC_AE22

C24

NC_C24

A25

NC_A25

C9

NC_C9

D

E

THERMDP 22 THERMDN 22

VID[4..0] 41

TP40 TPAD30TP40 TPAD30 TP39 TPAD30TP39 TPAD30

LAYOUT: Route FBCLKOUT_H/L

FBCLKOUT

FBCLKOUTJ

DBREQJ

differentially impedance 80

12

R520

R520 80D6R2F-L-GP

80D6R2F-L-GP

R155

1 2

DUMMY-R3

2D5V_S3

THERMTRIP#Level shift to SB400

2D5V_S0

12

R152

R152 680R3F-GP

680R3F-GP

Q7

THERMTRIP#

MMBT3904-2-GP

Title

Size Document Number Rev

A3

Date: Sheet

Q7

C

E

B

NS3

R157

1 2

1KR2J-1-GP

12

CPU(3/4)_Control & Debug

Bolsena-E

1KR2J-1-GP

C304

C304 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

E

CPU_THERMTRIP# 22

SB_CPUPWRGD 17

658Thursday, October 13, 2005

of

SA

U62EU62E

Y17

VSS

K17

VSS

H17

VSS

F17

VSS

E18

VSS

AJ26

VSS

AE29

VSS

AC16

VSS

AA16

VSS

J16

VSS

G16

VSS

E16

VSS

AH14

4 4

3 3

2 2

1 1

AD15 AB15

K15 E15

D16 AE14 AC14 AA14

G14

AF17 AD13 AB13

Y13 K13 H13

F13 AH12 AC12 AA12

G12

B12 AD11 AB11

Y11

K11

H11

F11 AH10 AC10

W10

U10

R10

N10

G10

B10

AD9

AH8 AC8

AD7

AB7

AH6 AC6

AA6

AH4 AH2

AD2

AB2

C29 AH28

AF28

AC28

W28

R28

VSS VSS VSS VSS VSS VSS VSS VSS VSS

J14

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

L10

VSS

J10

VSS VSS VSS VSS

Y9

VSS

V9

VSS

T9

VSS

P9

VSS

M9

VSS

K9

VSS

H9

VSS

F9

VSS VSS VSS

W8

VSS

U8

VSS

R8

VSS

N8

VSS

L8

VSS

J8

VSS

G8

VSS

B8

VSS VSS VSS

V7

VSS

T7

VSS

P7

VSS

M7

VSS

K7

VSS

H7

VSS

F7

VSS VSS VSS VSS

U6

VSS

R6

VSS

N6

VSS

L6

VSS

J6

VSS

G6

VSS

B6

VSS VSS

B4

VSS VSS VSS VSS

Y2

VSS

V2

VSS

T2

VSS

P2

VSS

M2

VSS

K2

VSS

H2

VSS

F2

VSS VSS VSS VSS VSS VSS VSS

L28

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

A

VCC_CORE_S0 2D5V_S3

N20 L20 J20 AF19 AD19 AB19 Y19 K19 H19 F19 D19 AC18 AA18 G18 B16 AD17 AB17 H15 F15 G28 D28 B28 C27 AH26 AF26 AD26 Y26 T26 M26 H26 D26 B26 C25 B25 AJ24 AG24 AC24 AA24 W24 U24 R24 N24 J24 G24 E24 AG23 AD23 AB23 Y23 V23 T23 P23 K23 H23 F23 D23 AJ22 AH22 AG22 AC22 AA22 AG29 U22 R22 N22 L22 J22 G22 E22 B22 AG21 AD21 Y21 V21 T21 P21 M21 K21 H21 F21 D21 AJ20 AG20 AE20 AC20 AA20 W20 U20 R20 G20 J18 AE16 Y15 B14 J12 AA10 AB9 AA8 Y7 W6 AF2 D2 AG27 AG25 L24 M23 W22 AB21 AH20 B2

A

AC15

H18 B20 E21 H22

H24 F26

V10 G13 K14 Y14

AB14

G15

AA15

H16 K16 Y16

AB16

G17

AA17 AC17 AE17

F18 K18

Y18 AB18 AD18 AG19

E19

G19 AC19 AA19

F20

H20

K20

M20

P20

T20

V20

Y20 AB20 AD20

G21

N21

R21

U21

W21 AA21 AC21

F22 K22

M22

P22 T22 V22

Y22 AB22 AD22

E23

G23

N23

R23

U23

W23 AA23 AC23

B24 D24 F24 K24

M24

P24 T24 V24

Y24 AB24 AD24 AH24 AE25

K26

P26

V26

U62DU62D

L7

VDD VDD VDD VDD VDD VDD

J23

VDD VDD VDD

N7

VDD

L9

VDD VDD VDD VDD VDD VDD VDD

J15

VDD VDD VDD VDD VDD VDD VDD

J17

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

J19

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

J21

VDD

L21

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

L23

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

E4 G4 J4 L4 N4 U4 W4 AA4 AC4 AE4 D5 AF5 F6 H6 K6 M6 P6 T6 V6 Y6 AB6 AD6 D7 G7 J7 AA7 AC7 AF7 F8 H8 AB8 AD8 D9 G9 AC9 AF9 F10 AD10 D11 AF11 F12 AD12 D13 AF13 F14 AD14 F16 AD16 D15 R4

N28 U28 AA28 AE27 R7 U7 W7 K8 M8 P8 T8 V8 Y8 J9 N9 R9 U9 W9 AA9 H10 K10 M10 P10 T10 Y10 AB10 G11 J11 AA11 AC11 H12 K12 Y12 AB12 J13 AA13 AC13 H14 AB26 E28 J28

B

VCC_CORE_S0

B

VCC_CORE_S0

12

VCC_CORE_S0

C820

1 2

0.22u x 4

DY

2D5V_S3

12

C321

1D25V_S3

12

C325

0.22u x 2

C

LAYOUT: Place in uPGA socket cavity.

0.22u x 6

12

C295

C294

LAYOUT: Place on backside of processor.

SCD22U16V3ZY-GP

C814

C818

1 2

SCD22U16V3ZY-GP

DY

12

SCD22U16V3ZY-GP

DY

12

C367

C368

SCD22U16V3ZY-GP

1D25V_S3

12

C326

SCD22U16V3ZY-GP

C813

SCD22U16V3ZY-GP

C819

1 2

DY

SCD22U16V3ZY-GP

12

C324

SCD22U16V3ZY-GP

12

C310

4.7u x 2

SC4D7U10V5ZY-3GP

C

12

C360

SCD22U16V3ZY-GP

12

C827

10u x 2

SC10U10V5ZY-1GP

12

C363

SCD22U16V3ZY-GP

12

C319

SC4D7U10V5ZY-3GP

12

C362

SCD22U16V3ZY-GP

C808

SC10U10V5ZY-1GP

C369

SCD22U16V3ZY-GP

C821

2D5V_S3

10u x 1 4.7u x 6

10u x 4

12

C339

SC10U10V5ZY-1GP

SCD22U16V3ZY-GP

12

C351

SC10U10V5ZY-1GP

12

C323

SC10U10V5ZY-1GP

12

C350

C359

SC4D7U10V5ZY-3GP

D

12

C809

C828

SC10U10V5ZY-1GP

12

C395

SC4D7U10V5ZY-3GP

D

12

C398

C361

SC4D7U10V5ZY-3GP

E

12

C396

SC4D7U10V5ZY-3GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

CPU(4/4)_Power

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

758Thursday, October 13, 2005

of

E

of

SA

A

M_AA0 M_AA1 M_AA2 M_AA3 M_AA4 M_AA5 M_AA6 M_AA7 M_AA8 M_AA9 M_AA10 M_AA11

12

C492

C492 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

A

M_AA12 M_ABS#0

M_ABS#1 M_DATA_R_0

M_DATA_R_1 M_DATA_R_2 M_DATA_R_3 M_DATA_R_4 M_DATA_R_5 M_DATA_R_6 M_DATA_R_7 M_DATA_R_8 M_DATA_R_9 M_DATA_R_10 M_DATA_R_11 M_DATA_R_12 M_DATA_R_13 M_DATA_R_14 M_DATA_R_15 M_DATA_R_16 M_DATA_R_17 M_DATA_R_18 M_DATA_R_19 M_DATA_R_20 M_DATA_R_21 M_DATA_R_22 M_DATA_R_23 M_DATA_R_24 M_DATA_R_25 M_DATA_R_26 M_DATA_R_27 M_DATA_R_28 M_DATA_R_29 M_DATA_R_30 M_DATA_R_31 M_DATA_R_32 M_DATA_R_33 M_DATA_R_34 M_DATA_R_35 M_DATA_R_36 M_DATA_R_37 M_DATA_R_38 M_DATA_R_39 M_DATA_R_40 M_DATA_R_41 M_DATA_R_42 M_DATA_R_43 M_DATA_R_44 M_DATA_R_45 M_DATA_R_46 M_DATA_R_47 M_DATA_R_48 M_DATA_R_49 M_DATA_R_50 M_DATA_R_51 M_DATA_R_52 M_DATA_R_53 M_DATA_R_54 M_DATA_R_55 M_DATA_R_56 M_DATA_R_57 M_DATA_R_58 M_DATA_R_59 M_DATA_R_60 M_DATA_R_61 M_DATA_R_62 M_DATA_R_63

12

3D3V_S0

TP59 TPAD30TP59 TPAD30

4 4

3 3

2 2

1 1

M_ARAS#5,9 M_ACAS#5,9 M_AWE#5,9

VREF_DDR_MEM VREF_DDR_MEM

Layout trace 20 mil Layout trace 20 mil

C493

SCD1U25V3ZY-3GP

DDR1

112

A0

111

A1

110

A2

109

A3

108

A4

107

A5

106

A6

105

A7

102

A8

101

A9

115

A10 / AP

100

A11

99

A12

117

BA0

116

BA1

5

DQ0

7

DQ1

13

DQ2

17

DQ3

6

DQ4

8

DQ5

14

DQ6

18

DQ7

19

DQ8

23

DQ9

29

DQ10

31

DQ11

20

DQ12

24

DQ13

30

DQ14

32

DQ15

41

DQ16

43

DQ17

49

DQ18

53

DQ19

42

DQ20

44

DQ21

50

DQ22

54

DQ23

55

DQ24

59

DQ25

65

DQ26

67

DQ27

56

DQ28

60

DQ29

66

DQ30

68

DQ31

127

DQ32

129

DQ33

135

DQ34

139

DQ35

128

DQ36

130

DQ37

136

DQ38

140

DQ39

141

DQ40

145

DQ41

151

DQ42

153

DQ43

142

DQ44

146

DQ45

152

DQ46

154

DQ47

163

DQ48

165

DQ49

171

DQ50

175

DQ51

164

DQ52

166

DQ53

172

DQ54

176

DQ55

177

DQ56

181

DQ57

187

DQ58

189

DQ59

178

DQ60

182

DQ61

188

DQ62

190

DQ63

71

CB0

73

CB1

79

CB2

83

CB3

72

CB4

74

CB5

80

CB6

84

CB7

85

NC#85

86

NC#86/(RESET#)

97

NC#97/A13

98

NC#98/BA2

123

NC#123

124

NC#124

200

NC#200

118

/RAS

120

/CAS

119

/WE

1

VREF

2

VREF

197

VDDSPD

199

VDDID

201

GND

/CS0 /CS1

CKE0 CKE1

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8

CK0

/CK0

CK1

/CK1

CK2

/CK2

SCL SDA

SA0 SA1 SA2

VDD VDD VDD VDD VDD VDD VDD

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS

VSS GND

B

121 122

M_CKE#0

96 95

M_DQS_R0

11

M_DQS_R1

25

M_DQS_R2

47

M_DQS_R3

61

M_DQS_R4

133

M_DQS_R5

147

M_DQS_R6

169

M_DQS_R7

183 77

M_ADM_R0

12

M_ADM_R1

26

M_ADM_R2

48

M_ADM_R3

62 134

M_ADM_R5

148

M_ADM_R6

170

M_ADM_R7

184 78

35 37 160 158

DDR_CLK0

89

DDR_CLK#0

91

SMBC_SB

195

SMBD_SB

193 194

196 198

9 10 21 22 33 34 36 45 46 57 58 69 70 81 82 92 93 94 113 114 131 132 143 144 155 156 157 167 168 179 180 191 192

3 4 15 16 27 28 38 39 40 51 52 63 64 75 76 87 88 90 103 104 125 126 137 138 149 150

ME : 62.10017.701

159

2nd :62.10017.691

161 162 173 174 185 186

202

B

M_CS#0 5,9 M_CS#1 5,9

M_CKE#0 5,9 M_CKE#1 5,9

M_ADM#0 M_ADM#1 M_ADM#2 M_ADM#3 M_ADM#4 M_ADM#5 M_ADM#6 M_ADM#7

M_CLK5 5 M_CLK#5 5 M_CLK7 5 M_CLK#7 5

2D5V_S3

NOT SUPPORT ECC CHECK AMD suggested pull-low

1ST 62.10017.701 - 2ND 62.10017.201

Part Number = 62.10017.701

SKT-SODIMM200-24GP

C515

SCD1U25V3ZY-3GP

C515

M_BRAS#5,9 M_BCAS#5,9 M_BWE#5,9

12

C516

SCD1U25V3ZY-3GP

M_BA0 M_BA1 M_BA2 M_BA3 M_BA4 M_BA5 M_BA6 M_BA7 M_BA8 M_BA9 M_BA10 M_BA11 M_BA12

M_BBS#0 M_BBS#1

M_DATA_R_0 M_DATA_R_1 M_DATA_R_2 M_DATA_R_3 M_DATA_R_4 M_DATA_R_5 M_DATA_R_6 M_DATA_R_7 M_DATA_R_8 M_DATA_R_9 M_DATA_R_10 M_DATA_R_11 M_DATA_R_12 M_DATA_R_13 M_DATA_R_14 M_DATA_R_15 M_DATA_R_16 M_DATA_R_17 M_DATA_R_18 M_DATA_R_19 M_DATA_R_20 M_DATA_R_21 M_DATA_R_22 M_DATA_R_23 M_DATA_R_24 M_DATA_R_25 M_DATA_R_26 M_DATA_R_27 M_DATA_R_28 M_DATA_R_29 M_DATA_R_30 M_DATA_R_31 M_DATA_R_32 M_DATA_R_33 M_DATA_R_34 M_DATA_R_35 M_DATA_R_36 M_DATA_R_37 M_DATA_R_38 M_DATA_R_39 M_DATA_R_40 M_DATA_R_41 M_DATA_R_42 M_DATA_R_43 M_DATA_R_44 M_DATA_R_45 M_DATA_R_46 M_DATA_R_47 M_DATA_R_48 M_DATA_R_49 M_DATA_R_50 M_DATA_R_51 M_DATA_R_52 M_DATA_R_53 M_DATA_R_54 M_DATA_R_55 M_DATA_R_56 M_DATA_R_57 M_DATA_R_58 M_DATA_R_59 M_DATA_R_60 M_DATA_R_61 M_DATA_R_62 M_DATA_R_63

M_BA13M_AA13

12

3D3V_S0

TP60 TPAD30TP60 TPAD30

C

DDR2

112

A0

111

A1

110

A2

109

A3

108

A4

107

A5

106

A6

105

A7

102

A8

101

A9

115

A10 / AP

100

A11

99

A12

117

BA0

116

BA1

5

DQ0

7

DQ1

13

DQ2

17

DQ3

6

DQ4

8

DQ5

14

DQ6

18

DQ7

19

DQ8

23

DQ9

29

DQ10

31

DQ11

20

DQ12

24

DQ13

30

DQ14

32

DQ15

41

DQ16

43

DQ17

49

DQ18

53

DQ19

42

DQ20

44

DQ21

50

DQ22

54

DQ23

55

DQ24

59

DQ25

65

DQ26

67

DQ27

56

DQ28

60

DQ29

66

DQ30

68

DQ31

127

DQ32

129

DQ33

135

DQ34

139

DQ35

128

DQ36

130

DQ37

136

DQ38

140

DQ39

141

DQ40

145

DQ41

151

DQ42

153

DQ43

142

DQ44

146

DQ45

152

DQ46

154

DQ47

163

DQ48

165

DQ49

171

DQ50

175

DQ51

164

DQ52

166

DQ53

172

DQ54

176

DQ55

177

DQ56

181

DQ57

187

DQ58

189

DQ59

178

DQ60

182

DQ61

188

DQ62

190

DQ63

71

CB0

73

CB1

79

CB2

83

CB3

72

CB4

74

CB5

80

CB6

84

CB7

85

NC#85

86

NC#86/(RESET#)

97

NC#97/A13

98

NC#98/BA2

123

NC#123

124

NC#124

200

NC#200

118

/RAS

120

/CAS

119

/WE

1

VREF

2

VREF

197

VDDSPD

199

VDDID

201

GND

SKT-SODIMM2006U1GP

C

/CS0 /CS1

CKE0 CKE1

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8

CK0

/CK0

CK1

/CK1

CK2

/CK2

SCL SDA

SA0 SA1 SA2

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

GND

D

121 122

96 95

M_DQS_R0

11

M_DQS_R1

25

M_DQS_R2

47

M_DQS_R3

61

M_DQS_R4

133

M_DQS_R5

147

M_DQS_R6

169

M_DQS_R7

183 77

M_ADM_R0

12

M_ADM_R1

26

M_ADM_R2

48

M_ADM_R3

62

M_ADM_R4M_ADM_R4

134

M_ADM_R5

148

M_ADM_R6

170

M_ADM_R7

184 78

35 37 160 158

DDR_CLK1

89

DDR_CLK#1

91 195

193 194

196 198

9 10 21 22 33 34 36 45 46 57 58 69 70 81 82 92 93 94 113 114 131 132 143 144 155 156 157 167 168 179 180 191 192

3 4 15 16 27 28 38 39 40 51 52 63 64 75 76 87 88 90 103 104 125 126 137 138 149 150 159 161 162 173 174 185 186

202

ME : 62.10017.391

M_CS#2 5,9 M_CS#3 5,9

! NOT THIS LIBRARY

M_ADM#0 M_ADM#1 M_ADM#2 M_ADM#3 M_ADM#4 M_ADM#5 M_ADM#6 M_ADM#7

M_CLK4 5 M_CLK#4 5 M_CLK6 5 M_CLK#6 5

SMBC_SB 3,20 SMBD_SB 3,20

DM_SA0

2D5V_S3

62.10017.391

R255

1 2

4K7R2J-2-GP

3D3V_S0

DDR1(Reverse 5.2mm)

DDR2(Reverse 9.2mm)

Title

Size Document Number Rev

A3

Date: Sheet

D

Date: Sheet

M_ADM_R[7..0] 9 M_DATA_R_[63..0] 9 M_DQS_R[7..0] 9

M_AA[13..0] 5,9 M_ABS#[1..0] 5,9 M_BA[13..0] 5,9 M_BBS#[1..0] 5,9

RN62

DDR_CLK#1 DDR_CLK#0 DDR_CLK1 DDR_CLK0

RN62

8 7 6

SRN10KJ-6-GP

AMD CPU

MD63

SMA11

Pin 199

Pin 200 Pin 2

Pin 199 Pin 1

Pin 200 Pin 2

(Bottom view)

DDR SO-DIMM SKT

Bolsena-E

E

2D5V_S3

1 2 3 45

SMA10 SMA0

SMA14

SMA12

MD0

Pin 1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

858Thursday, October 13, 2005

of

E

of

SA

A

SERIES DAMPING PARALLEL TERMINATION

PLACE RNs CLOSE TO FIRST DIMM, < 0.75" STRICT EQUAL LENGTH LIMITATION WITH DQS, CB PINS

SRN10J-3

M_DATA4 M_ADM0

M_DATA6 M_DATA7 M_DATA13 M_DATA12

4 4

M_ADM1

M_DATA1 M_DATA0 M_DQS0 M_DATA2 M_DATA3 M_DATA8 M_DATA9 M_DQS1

M_DATA14 M_DATA_R_14 M_DATA15 M_DATA21 M_DATA20 M_ADM2 M_DATA23 M_DATA_R_23 M_DATA22 M_DATA28 M_DATA_R_28

3 3

M_DATA11 M_DATA10 M_DATA17 M_DATA16 M_DQS2 M_DQS_R2 M_DATA19 M_DATA_R_19 M_DATA18

M_DATA31 M_DATA_R_31

M_DATA24 M_DATA_R_24 M_DATA_R_27 M_DQS3 M_DQS_R3 M_DATA26 M_DATA_R_26 M_DATA27 M_DATA_R_27

2 2

SRN10J-3

8 9 7 6 5 4 3 2 1

RN40

RN40 SRN10J-3

SRN10J-3

8 9 7 6 5 4 3 2 1

RN31

RN31 SRN10J-3

SRN10J-3

8 9 7 6 5 4 3 2 1

RN41

RN41 SRN10J-3

SRN10J-3

8 9 7 6 5 4 3 2 1

RN32

RN42

4 5 3 2 1

RN33

SRN10J-5-GP

10 11 12 13 14 15 16

SRN10J-5-GP

M_DATA_R_29M_DATA29 M_ADM_R3M_ADM3

6 7

M_DATA_R_30M_DATA30

8

6 7 8

M_DATA_R_4 M_DATA_R_5M_DATA5 M_ADM_R0 M_DATA_R_6 M_DATA_R_7 M_DATA_R_13 M_DATA_R_12 M_ADM_R1

M_DATA_R_1 M_DATA_R_0 M_DQS_R0 M_DATA_R_2 M_DATA_R_3 M_DATA_R_8 M_DATA_R_9 M_DQS_R1

M_DATA_R_15 M_DATA_R_21 M_DATA_R_20 M_ADM_R2

M_DATA_R_22

M_DATA_R_11 M_DATA_R_10 M_DATA_R_17 M_DATA_R_16

M_DATA_R_18 M_DATA_R_25M_DATA25

M_ADM4 M_ADM_R4 M_DATA39 M_DATA_R_39

M_DATA33 M_DATA_R_33 M_DATA34 M_DATA_R_34

M_DATA35 M_DATA41 M_DATA40 M_DQS5 M_DATA42 M_DATA43 M_DATA49 M_DATA48

M_DATA38 M_DATA45 M_DATA44 M_ADM5 M_DATA47 M_DATA46 M_DATA53 M_DATA52

M_DQS6 M_DATA50 M_DATA51 M_DATA56 M_DATA57 M_DQS7 M_DATA58 M_DATA59

M_ADM6 M_DATA54 M_DATA55 M_DATA61 M_DATA60 M_ADM7 M_DATA62 M_DATA63

4 5 3 2 1

RN34

8 9 7 6 5 4 3 2 1

SRN10J-5-GP

RN43

6 7 8

SRN10J-5-GP

SRN10J-5-GP SRN10J-3

SRN10J-3

10 11 12 13 14 15 16

RN35

RN35 SRN10J-3

SRN10J-3

10 11 12 13 14 15 16

RN44

RN44 SRN10J-3

SRN10J-3

10 11 12 13 14 15 16

RN36

RN36 SRN10J-3

SRN10J-3

10 11 12 13 14 15 16

RN45

B

M_DATA_R_37M_DATA37 M_DATA_R_36M_DATA36

M_DATA_R_32M_DATA32 M_DQS_R4M_DQS4

M_DATA_R_35 M_DATA_R_41 M_DATA_R_40 M_DQS_R5 M_DATA_R_42 M_DATA_R_43 M_DATA_R_49 M_DATA_R_48

M_DATA_R_38

M_DATA_R_45

M_DATA_R_44 M_ADM_R5 M_DATA_R_47 M_DATA_R_46 M_DATA_R_53 M_DATA_R_52

M_DQS_R6 M_DATA_R_50 M_DATA_R_51 M_DATA_R_56 M_DATA_R_57 M_DQS_R7 M_DATA_R_58 M_DATA_R_59

M_ADM_R6 M_DATA_R_54 M_DATA_R_55 M_DATA_R_61 M_DATA_R_60 M_ADM_R7 M_DATA_R_62 M_DATA_R_63

C

PULL HIGH STUBS < 0.8", PLACE RPs CLOSE TO SECOND DM ( DM2 )

SRN68J-4-GP

M_ADM_R1 M_DATA_R_13 M_DATA_R_12 M_DATA_R_7 M_DATA_R_6 M_ADM_R0 M_DATA_R_5 M_DATA_R_4

M_DATA_R_1 M_DATA_R_0 M_DQS_R0 M_DATA_R_2 M_DATA_R_3 M_DATA_R_8 M_DATA_R_9 M_DQS_R1

M_DATA_R_28 M_DATA_R_23 M_DATA_R_22 M_ADM_R2 M_ADM_R5 M_DATA_R_21 M_DATA_R_20 M_DATA_R_15 M_DATA_R_14

M_DATA_R_11 M_DATA_R_10 M_DATA_R_16 M_DATA_R_17 M_DQS_R2 M_DATA_R_19 M_DATA_R_18 M_DATA_R_24

M_DATA_R_26 M_DQS_R3 M_DATA_R_25

M_DATA_R_31 M_DATA_R_30 M_ADM_R3 M_DATA_R_29

SRN68J-4-GP

8 9 7 6 5 4 3 2 1

RN113

SRN68J-4-GP

8 9 7 6 5 4 3 2 1

RN59

RN59 SRN68J-4-GP

SRN68J-4-GP

8 9 7 6 5 4 3 2 1

RN114

RN114 SRN68J-4-GP

SRN68J-4-GP

8 9 7 6 5 4 3 2 1

RN60

RN60 RN61

RN61

1 2 3 4 5

4 5 3 2 1

RN115

1D25V_S3 1D25V_S3

4 5 10 11 12 13 14 15 16

10 11 12 13 14 15 16

SRN68J-3-GP

8 7 6

6 7 8

SRN68J-3-GP

3

2

1

RN56

4 5

3

2

1

RN110

SRN68J-4-GP

8 9 7 6 5 4 3 2 1

RN66

RN66 SRN68J-4-GP

SRN68J-4-GP

8 9 7 6 5 4 3 2 1

RN111

RN111 SRN68J-4-GP

SRN68J-4-GP

8 9 7 6 5 4 3 2 1

RN67

RN67 SRN68J-4-GP

SRN68J-4-GP

8 9 7 6 5 4 3 2 1

RN112

NO EQUAL LENGTH LIMITATION

M_DATA_R_32 M_DATA_R_33

6

M_DQS_R4

7

M_DATA_R_35

8

SRN68J-3-GP

M_DATA_R_36 M_DATA_R_37

6

M_ADM_R4

7

M_DATA_R_38

8

SRN68J-3-GP

M_DATA_R_48 M_DATA_R_49

10

M_DATA_R_43

11

M_DATA_R_42

12

M_DQS_R5

13

M_DATA_R_41

14

M_DATA_R_40

15

M_DATA_R_34

16

M_DATA_R_39 M_DATA_R_44

10

M_DATA_R_45

11 12

M_DATA_R_46

13

M_DATA_R_47

14

M_DATA_R_52

15

M_DATA_R_53

16

M_DATA_R_59 M_DATA_R_58

10

M_DQS_R7

11

M_DATA_R_57

12

M_DATA_R_56

13

M_DATA_R_51

14

M_DATA_R_50

15

M_DQS_R6

16

M_ADM_R6 M_DATA_R_54

10

M_DATA_R_55

11

M_DATA_R_60

12

M_DATA_R_61

13

M_ADM_R7

14

M_DATA_R_62

15

M_DATA_R_63

16

D

M_CKE#0 M_AA12

M_BA12 M_BA5

M_AA11 M_AA9 M_AA7 M_AA5 M_AA4 M_AA8 M_AA6 M_AA3

M_AWE# M_ABS#0

M_BA3 M_BA7

M_AA1 M_AA10 M_AA2 M_AA0 M_ABS#1 M_ARAS# M_CS#2 M_BA13

M_BA9 M_BA6 M_BA10 M_BA1 M_BA2 M_BA0 M_BBS#0 M_BWE#

M_BA4 M_BA8 M_BA11 M_CKE#1

M_AA13 M_CS#0 M_CS#1 M_ACAS#

M_CS#3 M_BCAS# M_BRAS# M_BBS#1

4 5 3 2 1

SRN47J-7-GP

1 4 2

8 9 7 6 5 4 3 2 1

SRN47J-4-GP

RN108

SRN47J-4-GP

RN51

3

RN50

RN50 SRN47J-7-GP

SRN47J-7-GP

3

RN55

RN55 SRN47J-6-GP

SRN47J-6-GP

10 11 12 13 14 15 16

SRN47J-4-GP

RN63

4 5 3 2 1

RN109

RN65 SRN47J-7-GPRN65 SRN47J-7-GP

1 4 2

3

RN68

SRN47J-7-GP

1 4 2

3

SRN47J-6-GP

10 11 12 13 14 15 16

RN64

RN64 SRN47J-6-GP

SRN47J-6-GP

10 11 12 13 14 15 16

RN69

6 7 8

E

M_ADM_R[7..0] 8

M_ADM[7..0] 5 M_DATA[63..0] 5 M_DATA_R_[63..0] 8 M_DQS[7..0] 5 M_DQS_R[7..0] 8

M_AA[13..0] 5,8

M_ABS#[1..0] 5,8

M_BA[13..0] 5,8

M_BBS#[1..0] 5,8

M_AWE# 5,8

M_ACAS# 5,8

6 7 8

M_CKE#05,8 M_CKE#15,8

M_ARAS# 5,8

M_BWE# 5,8

M_BCAS# 5,8

M_BRAS# 5,8

M_CS#0 5,8

M_CS#1 5,8

M_CS#2 5,8

M_CS#3 5,8

M_CKE#0 M_CKE#1

1 1

05/10 Remove the damping resistor for AMD suggest.

A

B

C

D

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

DDR DAMPING & TERMINATION

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

958Thursday, October 13, 2005

E

of

SA

A

B

C

D

E

4 4

2D5V_S3

1D25V_S3

3 3

2D5V_S3

1D25V_S3

2 2

12

C866

C866 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C861

C861 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C872

C872 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C875

C875 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C868

C870

SCD1U25V3ZY-3GP

12

C863

C865

SCD1U25V3ZY-3GP

12

C876

C874

SCD1U25V3ZY-3GP

12

C881

C879

SCD1U25V3ZY-3GP

LAYOUT:Place altemating caps to GND and 2D5_S3

12

C860

C860 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C867

C867 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C878

C878 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C883

C883 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C862

C862 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C869

C869 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C880

C880 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C873

C873 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C864

C864 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C871

C871 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C882

C882 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C877

C877 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C394

C417

SCD1U25V3ZY-3GP

DY

12

C509

C481

SCD1U25V3ZY-3GP

DY

12

C510

C402

SCD1U25V3ZY-3GP

DY

12

C403

C511

SCD1U25V3ZY-3GP

DY

12

C430

C430 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C464

C464 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C450

C450 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C451

C451 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C437

C437 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C456

C456 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C364

C364 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C365

C365 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C469

C457

SCD1U25V3ZY-3GP

12

C436

C418

SCD1U25V3ZY-3GP

12

C378

C409

SCD1U25V3ZY-3GP

12

C379

C388

SCD1U25V3ZY-3GP

12

C383

C383 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C424

C424 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C421

C421 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C422

C422 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C491

C491 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C416

C416 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C441

C441 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C442

C442 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C358

C425

SCD1U25V3ZY-3GP

12

C382

C401

SCD1U25V3ZY-3GP

12

C471

C458

SCD1U25V3ZY-3GP

12

C397

C475

SCD1U25V3ZY-3GP

12

C498

C498 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C419

C419 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C495

C495 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C497

C497 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

1D25V_S3

12

DY

12

C501

C500

SCD1U25V3ZY-3GP

12

C494

C494 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C503

C503 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C499

C499 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C520

C520 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

C357

C357 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

LAYOUT:Place close to Power Pin of DDR socket.

LAYOUT:Place at end of the DIMMs

1D25V_S3

12

DY

TC15

TC15 ST100U4VBM-U

ST100U4VBM-U

12

TC26

SE100U10VM-4GP

79.10111.40L

12

C889

C889 SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

12

C886

C886 SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

12

C888

C888 SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

12

C887

C887 SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

2D5V_S3 2D5V_S3

C466

1 2

SCD22U16V3ZY-GP

SCD22U16V3ZY-GP C465

C465

1 2

SCD22U16V3ZY-GP

SCD22U16V3ZY-GP C484

C484

1 2

DY

SCD22U16V3ZY-GP

DY

C483

C483 SCD22U16V3ZY-GP

SCD22U16V3ZY-GP C482

C482 SCD22U16V3ZY-GP

SCD22U16V3ZY-GP

1 2

C504

C504 SCD22U16V3ZY-GP

SCD22U16V3ZY-GP C519

C519 SCD22U16V3ZY-GP

SCD22U16V3ZY-GP

DY

C518

C518 SCD22U16V3ZY-GP

SCD22U16V3ZY-GP

DY

C502

C502 SCD22U16V3ZY-GP

SCD22U16V3ZY-GP C517

C517 SCD22U16V3ZY-GP

SCD22U16V3ZY-GP

0.22u x 10

1 1

A

B

C

D

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

DDR DECOUPLING

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

10 58Thursday, October 13, 2005

of

E

of

SA

A

4 4

B

C

D

E

CLAW HAMMER TO NB NB TO CLAW HAMMER

CPUCADOUT[15..0]4 CPUCADOUTJ[15..0]4

3 3

1D2V_S0

12

2 2

AROUND NB

12

C254

C254 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C248

C248 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

DY

1D2V_S0

CPUHTTCLKOUT14 CPUHTTCLKOUTJ14

CPUHTTCLKOUT04 CPUHTTCLKOUTJ04

CPUHTTCTLOUT04 CPUHTTCTLOUTJ04

R124 49D9R2F-GPR124 49D9R2F-GP

1 2

R123 49D9R2F-GPR123 49D9R2F-GP

1 2

CPUCADOUT15 CPUCADOUTJ15 CPUCADOUT14 CPUCADOUTJ14 CPUCADOUT13 CPUCADOUTJ13 CPUCADOUT12 CPUCADOUTJ12 CPUCADOUT11 CPUCADOUTJ11 CPUCADOUT10 CPUCADOUTJ10 CPUCADOUT9 CPUCADOUTJ9 CPUCADOUT8 CPUCADOUTJ8

CPUCADOUT7 CPUCADOUTJ7 CPUCADOUT6 CPUCADOUTJ6 CPUCADOUT5 CPUCADOUTJ5 CPUCADOUT4 CPUCADOUTJ4 CPUCADOUT3 CPUCADOUTJ3 CPUCADOUT2 CPUCADOUTJ2 CPUCADOUT1 CPUCADOUTJ1 CPUCADOUT0 CPUCADOUTJ0

CPUHTTCLKOUT1 CPUHTTCLKOUTJ1

CPUHTTCLKOUT0 CPUHTTCLKOUTJ0

CPUHTTCTLOUT0 CPUHTTCTLOUTJ0

HT_RXCALN HT_RXCALP

W25

W24 AA25 AA24 AB26 AA26 AC25 AC24 AD26 AC26

W30

AB29 AA29 AC29 AC28

W26

W29

W28

T26 R26 U25 U24 V26 U26

R29 R28 T30 R30 T28 T29 V29 U29 Y30

Y28 Y29

Y26

P29 N29

D27 E27

U61A

HT_RXCAD15P HT_RXCAD15N HT_RXCAD14P HT_RXCAD14N HT_RXCAD13P HT_RXCAD13N HT_RXCAD12P HT_RXCAD12N HT_RXCAD11P HT_RXCAD11N HT_RXCAD10P HT_RXCAD10N HT_RXCAD9P HT_RXCAD9N HT_RXCAD8P HT_RXCAD8N

HT_RXCAD7P HT_RXCAD7N HT_RXCAD6P HT_RXCAD6N HT_RXCAD5P HT_RXCAD5N HT_RXCAD4P HT_RXCAD4N HT_RXCAD3P HT_RXCAD3N HT_RXCAD2P HT_RXCAD2N HT_RXCAD1P HT_RXCAD1N HT_RXCAD0P HT_RXCAD0N

HT_RXCLK1P HT_RXCLK1N

HT_RXCLK0P HT_RXCLK0N

HT_RXCTLP HT_RXCTLN

HT_RXCALN HT_RXCALP

NB0CADOUT15

PART 1OF6

HT_TXCAD15P HT_TXCAD15N HT_TXCAD14P HT_TXCAD14N HT_TXCAD13P HT_TXCAD13N HT_TXCAD12P HT_TXCAD12N HT_TXCAD11P HT_TXCAD11N HT_TXCAD10P HT_TXCAD10N

HT_TXCAD9P HT_TXCAD9N HT_TXCAD8P HT_TXCAD8N

HT_TXCAD7P HT_TXCAD7N HT_TXCAD6P HT_TXCAD6N HT_TXCAD5P HT_TXCAD5N HT_TXCAD4P HT_TXCAD4N HT_TXCAD3P HT_TXCAD3N HT_TXCAD2P HT_TXCAD2N HT_TXCAD1P HT_TXCAD1N HT_TXCAD0P HT_TXCAD0N

HT_TXCLK1P HT_TXCLK1N

HYPER TRANSPORT CPU I/F

HT_TXCLK0P HT_TXCLK0N

HT_TXCTLP

HT_TXCTLN HT_TXCALP

HT_TXCALN

R24 R25 N26 P26 N24 N25 L26 M26 J26 K26 J24 J25 G26 H26 G24 G25

L30 M30 L28 L29 J29 K29 H30 H29 E29 E28 D30 E30 D28 D29 B29 C29

L24 L25

F29 G29

M29 M28

B28 A28

NB0CADOUTJ15 NB0CADOUT14 NB0CADOUTJ14 NB0CADOUT13 NB0CADOUTJ13 NB0CADOUT12 NB0CADOUTJ12 NB0CADOUT11 NB0CADOUTJ11 NB0CADOUT10 NB0CADOUTJ10 NB0CADOUT9 NB0CADOUTJ9 NB0CADOUT8 NB0CADOUTJ8

NB0CADOUT7 NB0CADOUTJ7 NB0CADOUT6 NB0CADOUTJ6 NB0CADOUT5 NB0CADOUTJ5 NB0CADOUT4 NB0CADOUTJ4 NB0CADOUT3 NB0CADOUTJ3 NB0CADOUT2 NB0CADOUTJ2 NB0CADOUT1 NB0CADOUTJ1 NB0CADOUT0 NB0CADOUTJ0

NB0HTTCLKOUT1 NB0HTTCLKOUTJ1

NB0HTTCLKOUT0 NB0HTTCLKOUTJ0

NB0HTTCTLOUT NB0HTTCTLOUTJ

HT_TXCALP HT_TXCALN

R498

1 2

NB0CADOUT[15..0] 4 NB0CADOUTJ[15..0] 4

NB0HTTCLKOUT1 4 NB0HTTCLKOUTJ1 4

NB0HTTCLKOUT0 4 NB0HTTCLKOUTJ0 4

NB0HTTCTLOUT 4 NB0HTTCTLOUTJ 4

100R2F-L1-GP-U

1 1

A

B

C

D

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

ATI-RS482M (1 of 4) HT

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

11 58Thursday, October 13, 2005

of

E

of

SA

A

4 4

3 3

Dummy when 'USE DVO'

C829 SCD47U10V3ZY-GPC829 SCD47U10V3ZY-GP

MEM_CAP1

2 2

R178

1D8V_S0

1 2

0R0603-PAD

1 2

MEM_CAP2

1 2

C837 SCD47U10V3ZY-GPC837 SCD47U10V3ZY-GP

RS480_MEM_VMODE

MEM_VREF MPVDD_PLL

12

C366

C366 SC1U10V3KX-3GP

SC1U10V3KX-3GP

AF17 AK17 AH16

AF16

AJ22

AJ21 AH20 AH21 AK19 AH19

AJ17 AG16 AG17 AH17

AJ18 AG26

AJ29 AE21 AH24 AH12 AG13

AH8 AE8

AF25 AH30 AG20

AJ25 AH13

AF14

AG8

AG25 AH29

AF21 AK25

AJ12

AF13

AK7 AF9

AE17 AH18 AE18

AJ19

AF18 AK16

AJ16

AE28

AJ20

AK20

AJ15

AJ14

AJ7

AJ4

U61C

NC#AF17 NC#AK17 NC#AH16 NC#AF16 NC#AJ22 NC#AJ21 NC#AH20 NC#AH21 NC#AK19 NC#AH19 NC#AJ17 NC#AG16 NC#AG17 NC#AH17 NC#AJ18

NC#AG26 NC#AJ29 NC#AE21 NC#AH24 NC#AH12 NC#AG13 NC#AH18 NC#AE8

NC#AF25 NC#AH30 NC#AG20 NC#AJ25 DVO_IDCKP NC#AF14 NC#AJ7 NC#AG8

NC#AG25 NC#AH29 NC#AF21 NC#AK25 DVO_IDCKN NC#AF13 NC#AK7 NC#AF9

NC#AE17 NC#AH18 NC#AE18 NC#AJ19 NC#AF18

NC#AK16 NC#AJ16

NC#AE28 NC#AJ4

NC#AJ20

NC#AK20 VDD_18

VSS

PART 3 OF 6

B

AF28

NC#AF28

AF27

NC#AF27

AG28

NC#AG28

AF26

NC#AF26

AE25

NC#AE25

AE24

NC#AE24

AF24

NC#AF24

AG23

NC#AG23

AE29

NC#AE29

AF29

NC#AF29

AG30

NC#AG30

AG29

NC#AG29

AH28

NC#AH28

AJ28

NC#AJ28

AH27

NC#AH27

AJ27

NC#AJ27

AE23

NC#AE23

AG22

NC#AG22

AF23

NC#AF23

AF22

NC#AF22

AE20

NC#AE20

AG19

NC#AG19

AF20

NC#AF20

AF19

NC#AF19

AH26

NC#AH26

AJ26

NC#AJ26

AK26

NC#AK26

AH25

NC#AH25

AJ24

NC#AJ24

AH23

NC#AH23

AJ23

NC#AJ23

AH22

NC#AH22

AK14

NC#AK14

AH14

DVO_D11

AK13

DVO_D10

AJ13

DVO_D9

AJ11

DVO_D8

AH11

DVO_D7

AJ10

DVO_D6

AH10

DVO_D4

AE15

NC#AE15

AF15

NC#AF15

AG14

NC#AG14

AE14

NC#AE14 NC#AE12

NC#AF12 NC#AG11 NC#AE11

DVO_D5 DVO_D1 DVO_D2 DVO_D3 DVO_D0

DVO_DE

NC#AG10

NC#AF11

NC#AF10

NC#AE9

NC#AG7

NC#AF8 NC#AF7 NC#AE7

NC#AH5

NC#AD30

AE12 AF12 AG11 AE11 AJ9 AH9 AJ8 AK8 AH7 AJ6 AH6 AJ5 AG10 AF11 AF10 AE9 AG7 AF8 AF7 AE7

AH5 AD30

MEM_A I/F

DVO_HSYNC DVO_VSYNC

C

PEG_TXP15 PEG_TXN15 PEG_TXP14 PEG_TXN14 PEG_TXP13 PEG_TXN13 PEG_TXP12 PEG_TXN12 PEG_TXP11 PEG_TXN11 PEG_TXP10 PEG_TXN10 PEG_TXP9 PEG_TXN9 PEG_TXP8 PEG_TXN8 PEG_TXP7 PEG_TXN7 PEG_TXP6 PEG_TXN6 PEG_TXP5 PEG_TXN5

LANE REVERSE

PEG_TXP4 PEG_TXN4 PEG_TXP3 PEG_TXN3 PEG_TXP2 PEG_TXN2 PEG_TXP1 PEG_TXN1 PEG_TXP0 PEG_TXN0

PCIE_RX0P_SB17 PCIE_RX0N_SB17

PCIE_RX1P_SB17 PCIE_RX1N_SB17

R531 10KR2J-2-GPR531 10KR2J-2-GP

1 2 1 2

8K25R3F-2-GP

R532

PEG_TXP[15..0]49 PEG_TXN[15..0]49

PEG_RXP[15..0]49 PEG_RXN[15..0]49

PCE_ISET

PCE_TXISET

U61B

D8

GFX_RX0P

D7

GFX_RX0N

D5

GFX_RX1P

D4

GFX_RX1N

E4

GFX_RX2P

F4

GFX_RX2N

G5

GFX_RX3P

G4

GFX_RX3N

H4

GFX_RX4P

J4

GFX_RX4N

H5

GFX_RX5P

H6

GFX_RX5N

G1

GFX_RX6P

G2

GFX_RX6N

K5

GFX_RX7P

K4

GFX_RX7N

L4

GFX_RX8P

M4

GFX_RX8N

N5

GFX_RX9P

N4

GFX_RX9N

P4

GFX_RX10P

R4

GFX_RX10N

P5

GFX_RX11P

P6

GFX_RX11N

P2

GFX_RX12P

R2

GFX_RX12N

T5

GFX_RX13P

T4

GFX_RX13N

U4

GFX_RX14P

V4

GFX_RX14N

W1

GFX_RX15P

W2

GFX_RX15N

AE1

GPP_RX0P/SB_RX2P

AE2

GPP_RX0N/SB_RX2N

AB2

GPP_RX1P/SB_RX3P

AC2

GPP_RX1N/SB_RX3N

AB5

GPP_RX2P

AB4

GPP_RX2N

Y4

GPP_RX3P

AA4

GPP_RX3N

AG1

SB_RX0P

AH1

SB_RX0N

AC5

SB_RX1P

AC6

SB_RX1N

AH3

PCE_ISET

AJ3

PCE_TXISET

PART 2 OF 6

GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N GFX_TX8P GFX_TX8N GFX_TX9P GFX_TX9N

GFX_TX10P

GFX_TX10N

GFX_TX11P

GFX_TX11N

GFX_TX12P

GFX_TX12N

GFX_TX13P

GFX_TX13N

GFX_TX14P

GFX_TX14N

PCIE I/F TO VIDEO

GFX_TX15P

GFX_TX15N

GPP_TX0P/SB_TX2P GPP_TX0N/SB_TX2N

GPP_TX1P/SB_TX3P

PCIE I/F TO SLOT

PCIE I/F TO SB

GPP_TX1N/SB_TX3N

GPP_TX2P GPP_TX2N

GPP_TX3P GPP_TX3N

PCE_PCAL PCE_NCAL

SB_TX0P SB_TX0N

SB_TX1P SB_TX1N

D

PEG_RXP15_NB PEG_RXP15

A7 B7

PEG_RXP14_NB

B6 B5

PEG_RXP13_NB

A5

PEG_RXN13_NB

A4

PEG_RXP12_NB

B3

PEG_RXN12_NB

B2

PEG_RXP11_NB

C1

PEG_RXN11_NB

D1

PEG_RXP10_NB

D2

PEG_RXN10_NB

E2

PEG_RXP9_NB

F2

PEG_RXN9_NB

F1

PEG_RXP8_NB

H2

PEG_RXN8_NB

J2

PEG_RXP7_NB

J1

PEG_RXN7_NB

K1

PEG_RXP6_NB

K2

PEG_RXN6_NB

L2

PEG_RXP5_NB

M2

PEG_RXN5_NB

M1

PEG_RXP4_NB

N1

PEG_RXN4_NB

N2

PEG_RXP3_NB

R1

PEG_RXN3_NB

T1

PEG_RXP2_NB

T2

PEG_RXN2_NB

U2

PEG_RXP1_NB

V2

PEG_RXN1_NB

V1

PEG_RXP0_NB

Y2

PEG_RXN0_NB

AA2

AD2 AD1

AA1 AB1

Y5 Y6

W5 W4

SB_TX0P

AF2

SB_TX0N

AG2

SB_TX1P

AC4

SB_TX1N

AD4

PCE_PCAL

AH2

PCE_NCAL

AJ2

C752

C752 C753

C753 C754

C754 C755

C755 C756

C756 C757

C757 C758

C758 C759

C759 C771

C771 C770

C770 C775

C775 C774

C774 C776

C776 C784

C784 C783

C783 C789

C789 C792

C792 C791

C791 C790

C790 C794

C794 C795

C795 C801

C801 C799

C799 C798

C798 C800

C800 C805

C805 C804

C804 C810

C810 C811

C811 C812

C812 C816

C816 C817

C817

C824

1 2

C825

1 2

C826

1 2

C830

1 2

R528 150R2F-1-GPR528 150R2F-1-GP

1 2

R529 100R2F-L1-GP-UR529 100R2F-L1-GP-U

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

PCIE_TX0P_SB 17 PCIE_TX0N_SB 17

PCIE_TX1P_SB 17 PCIE_TX1N_SB 17

E

PEG_RXN15PEG_RXN15_NB PEG_RXP14 PEG_RXN14PEG_RXN14_NB PEG_RXP13 PEG_RXN13 PEG_RXP12 PEG_RXN12 PEG_RXP11 PEG_RXN11 PEG_RXP10 PEG_RXN10 PEG_RXP9 PEG_RXN9 PEG_RXP8 PEG_RXN8 PEG_RXP7 PEG_RXN7 PEG_RXP6 PEG_RXN6 PEG_RXP5 PEG_RXN5 PEG_RXP4 PEG_RXN4 PEG_RXP3 PEG_RXN3 PEG_RXP2 PEG_RXN2 PEG_RXP1 PEG_RXN1 PEG_RXP0 PEG_RXN0

Dummy when use UMA

1D2V_S0

LANE REVERSE

12

R174

R174 1KR2F-3-GP

1KR2F-3-GP

MEM_VREF

12

1 1

R175

R175 1KR2F-3-GP

1KR2F-3-GP

NO DVO: MEM_COMPP = NC MEM_COMPN = NC MEM_CAP1 = 470nF MEM_CAP2 = 470nF MEM_VMODE = GND (IF VDD_MEM = 2.5V) MEM_VREF = VDD_MEM / 2

A

WITH DVO: MEM_COMPP = 61.9 OHM TO GND MEM_COMPN = 61.9 OHM TO VDD_MEM MEM_CAP1 = NC MEM_CAP2 = NC MEM_VMODE = 1.8V(IF VDD_MEM = 1.8V) MEM_VREF = VDD_MEM / 2

B

RS480_MEM_VMODE

C

R170

R170 1KR2J-1-GP

1KR2J-1-GP

1 2

Dummy when 'USE DVO'

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

ATI-RS482M (2 of 4) PCIE

Size Document Number Rev

A3

Date: Sheet

D

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

12 58Thursday, October 13, 2005

E

SA

of

SA

A

12

C782

DY

1 2

150R5F

12

NB_SUS_STAT#

AVDDQ

12

C781

SC10U10V5ZY-1GP

SCD1U16V2ZY-2GP

Dummy when use Discrete

UMA_CRMA57

UMA_LUMA57

UMA_COMP57

UMA_R57 UMA_G57

1D8V_S0

12

R535

R535 4K7R2J-2-GP

4K7R2J-2-GP

UMA_B57

R487

1 2

BLM11A121S-GP

HTPVDD

12

C793

SC10U10V5ZY-1GP

12

C788

C787

SCD1U16V2ZY-2GP

DO NOT SUPPORT SIDEPORT MEMORY DO NOT SUPPORT SERIAL STRAP ROM DUMMY IT

PLVDD

12

C747

C748

SC10U10V5ZY-1GP

SC2D2U16V5ZY-GP

3D3V_S01D8V_S0

R151

1 2

SCD1U16V2ZY-2GP

0R0603-PAD

EDID_CLK16,50 EDID_DAT16,50

1 2

R491 150R2F-1-GPR491 150R2F-1-GP

R492 150R2F-1-GPR492 150R2F-1-GP

12

C741

SCD1U16V2ZY-2GP

1 2

R493 150R2F-1-GPR493 150R2F-1-GP

12

C280

C280 SC1U10V3ZY-6GP

SC1U10V3ZY-6GP

3 4

1D8V_S0

3D3VDDR_S0

RN105

RN105 SRN0J-6-GP

SRN0J-6-GP

1D8V_S0

R511

1 2

0R0603-PAD

4 4

3 3

1D8V_S0

R515

2 2

Dummy when use Discrete

R126

1 2

0R0603-PAD

R495

1 2

150R2F-1-GP

3D3V_S0

2 1

B

R494

R496

150R2F-1-GP

UMA_CRT_DDC_C15 UMA_CRT_DDC_D15

3

R490

1 2

0R0603-PAD

12

C247

C247 SC2D2U16V5ZY-GP

SC2D2U16V5ZY-GP

AVDDQ

12

UMA_VS15 UMA_HS15

CLK14_NB3

RN104

SRN10KJ-5-GP

C

AVDD3D3V_S0

12

C751

C751 SC2D2U16V5ZY-GP

SC2D2U16V5ZY-GP

1D8VAVDDD1_S0

U61D

B27

AVDD1

C27

AVDD2

D26

AVSSN1

D25

AVSSN2

C24

AVDDDI

B24

C263

C263 SC1U10V3ZY-6GP

SC1U10V3ZY-6GP

R125

1 2

715R2F-GP

NB_PWRGD39,52

LDT_STP#6,17

ALLOW_LDTSTOP17

TP97TPAD30 TP97TPAD30

TP22TPAD30 TP22TPAD30 TP21TPAD30 TP21TPAD30 TP95 TPAD30TP95 TPAD30

14 2

BMREQ#17

IRSET_NB

RS480_RST#

NB_SUS_STAT#

NB_OSC_OUT

10KR2J-2-GP

10KR2J-2-GP R497

R497

1 2

DFT_GPIO0 DFT_GPIO2

RS480_CLK RS480_DAT

AVSSDI

E24

AVDDQ

D24

AVSSQ

B25

C

A25

Y

A24

COMP

C25

RED

A26

GREEN

B26

BLUE

A11

DAC_VSYNC

B11

DAC_HSYNC

C26

RSET

E11

DAC_SCL

F11

DAC_SDA

A14

PLLVDD

B14

PLLVSS

M23

HTPVDD

L23

HTPVSS

D14

SYSRESET#

B15

POWERGOOD

B12

LDTSTOP#

C12

ALLOW_LDTSTOP

AH4

NC

H13

VDDR3_1

H12

VDDR3_2

A13

OSCIN

B13

OSCOUT

B9

TVCLKIN

F12

DFT_GPIO0

E13

DFT_GPIO1

D13

DFT_GPIO2

F10

BMREQ#

C10

I2C_CLK

C11

I2C_DATA

AF4

THERMALDIODE_P

AE4

THERMALDIODE_N

PART 4 OF 6

CRT/TVOUT

PLL PWR

PM

CLOCKs

MIS.

TXOUT_U0P TXOUT_U0N TXOUT_U1P TXOUT_U1N TXOUT_U2P TXOUT_U2N TXOUT_U3P TXOUT_U3N

TXOUT_L0P TXOUT_L0N TXOUT_L1P TXOUT_L1N TXOUT_L2P TXOUT_L2N TXOUT_L3P TXOUT_L3N

TXCLK_UP TXCLK_UN

TXCLK_LP

LVDS

TXCLK_LN

LPVDD

LPVSS

LVDDR18D LVDDR18A_1 LVDDR18A_2

LVSSR1 LVSSR2 LVSSR3 LVSSR4 LVSSR5 LVSSR6 LVSSR7 LVSSR8

LVDS_DIGON

LVDS_BLON LVDS_BLEN

GFX_CLKP

GFX_CLKN

HTTSTCLK

HTREFCLK

SB_CLKP SB_CLKN

DFT_GPIO3 DFT_GPIO4 DFT_GPIO5

TMDS_HPD

STRP_DATA

DDC_DATA

TESTMODE

VCC_CORE_S0

12

D18 C18 B19 A19 D19 C19 D20 C20

B16 A16 D16 C16 B17 A17 E17 D17

B20 A20 B18 C17

E18 F17 E19 G20 H20

G19 E20 F20 H18 G18 F19 H19 F18

E14 F14 F13

B8 A8

P23 N23

E8 E7

C13 C14 C15

A10 E10 B10 E12

R147

R147 DUMMY-R2

DUMMY-R2

D

TXBOUT0+ TXBOUT0TXBOUT1+ TXBOUT1TXBOUT2+

TXBOUT2TXBOUT3+ TXBOUT3-

TXAOUT0+

TXAOUT0-

TXAOUT1+

TXAOUT1-

TXAOUT2+

TXAOUT2TXAOUT3+ TXAOUT3-

TXBCLK+

TXBCLK-

TXACLK+

TXACLK-

LCDVDD_ON LVDS_BLON LVDS_BLEN_NB

HTTST_CLK

DFT_GPIO3

DFT_GPIO4DFT_GPIO1

DFT_GPIO5

DDC_DATA TESTMODE_NB

TP23TP23 TP20TP20

R153

1 2

TP28TP28 TP27TP27

TP24 TPAD30TP24 TPAD30

NBSRC_CLK 3 NBSRC_CLK# 3

10KR2J-2-GP

HTREF_CLK 3 SBLINK_CLK 3

SBLINK_CLK# 3

TP99 TPAD28TP99 TPAD28 TP26 TPAD28TP26 TPAD28 TP100 TPAD28TP100 TPAD28

TXACLK+ TXACLKTXAOUT2+ TXAOUT2-

TXAOUT1+ TXAOUT1TXAOUT0+ TXAOUT0-

TXBOUT1+ TXBOUT1TXBOUT0+ TXBOUT0-

TXBCLK+ TXBCLKTXBOUT2+ TXBOUT2-

LCDVDD_ON

1D8VLPVDD_S0

TP98 TPAD30TP98 TPAD30TP25TPAD30 TP25TPAD30 TP96 TPAD30TP96 TPAD30

45

R137

RN80

RN78

RN84

RN86

SRN0J-4-GP

12

0R2J-GP

3 2 1

45 3 2 1

6 7 8

Dummy when use Discrete

12

C746

LVDDR18D_S0

LVDDR18A_S0

12

C744

SC1U10V3ZY-6GP

C745

12

E

LCD_TXACLK+ 16,57 LCD_TXACLK- 16,57

LCD_TXAOUT2+ 16,57

LCD_TXAOUT2- 16,57

LCD_TXAOUT1+ 16,57

LCD_TXAOUT1- 16,57

LCD_TXAOUT0+ 16,57

LCD_TXAOUT0- 16,57

LCD_TXBOUT1+ 16,57

LCD_TXBOUT1- 16,57

LCD_TXBOUT0+ 16,57

LCD_TXBOUT0- 16,57

LCD_TXBCLK+ 16,57 LCD_TXBCLK- 16,57

LCD_TXBOUT2+ 16,57

LCD_TXBOUT2- 16,57

LCD_VDD_ON 16,57

1 2

12

C251

1 2

12

C250

SC1U10V3ZY-6GP

SC2D2U16V5ZY-GP

1 2

C249

SC1U10V3ZY-6GP

SCD1U16V2ZY-2GP

R486

R485

R484

1D8V_S0

BLM11A121S-GP

12

R142

R142 4K7R2J-2-GP

1 1

R118

LPC_RST#17,34,37,49

1 2

33R2J-2-GP

RS480_RST#

12

C235

C235 DUMMY-C3

DUMMY-C3

LVDS_BLON

12

1 2

R474

R474 1KR2J-1-GP

1KR2J-1-GP

R475

0R2J-GP

Dummy when use Discrete

A

B

C

4K7R2J-2-GP

R305

R305 10KR2J-2-GP

10KR2J-2-GP

1 2

D

BL_ON 34,52

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet

ATI-RS482M (3 of 4) LVDS CRT

A3

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

13 58Thursday, October 13, 2005

E

of

SA

A

B

C

D

E

VSS89

U61F

4 4

3 3

12

C297

SC10U10V5ZY-1GP

12

C311

SCD1U16V2ZY-2GP

2 2

12

C822

SC10U10V5ZY-1GP

12

C354

1D8V_S0

SCD1U16V2ZY-2GP

1 1

3D3V_S0

1 2

U13

U13 BAV99PT-GP-U

BAV99PT-GP-U

DY

C291

DY

12

C312

12

C823

12

C334

3

12

C276

SCD1U16V2ZY-2GP

12

C313

DY

SCD1U16V2ZY-2GP

12

C330

SCD1U16V2ZY-2GP

12

C343

DY

SCD1U16V2ZY-2GP

L12

1 2

BLM11A121S-GP

DY

0R2J-GP

3

1 2

U14

U14 BAV99PT-GP-U

BAV99PT-GP-U

DY

A

12

C278

SCD1U16V2ZY-2GP

12

C329

SCD1U16V2ZY-2GP

12

C344

SCD1U16V2ZY-2GP

12

C341

SCD1U16V2ZY-2GP

12

R177

DY

12

C277

SCD1U16V2ZY-2GP

12

C328

SCD1U16V2ZY-2GP

12

C331

SCD1U16V2ZY-2GP

12

C345

DY

SCD1U16V2ZY-2GP

12

C373

12

DY

R176

0R2J-GP

12

C258

SCD1U16V2ZY-2GP

12

C296

SCD1U16V2ZY-2GP

12

C340

SCD1U16V2ZY-2GP

12

C371

SCD1U16V2ZY-2GP

1D8VDD_S0

12

C279

SCD1U16V2ZY-2GP

AD28

F24

F27

G28

VSS110

VSS111

VSS112

12

C259

SCD1U16V2ZY-2GP

12

C327

1D8V_S0

SCD1U16V2ZY-2GP

12

C355

SCD1U16V2ZY-2GP

12

C342

SCD1U16V2ZY-2GP

12

C333

SCD1U16V2ZY-2GP

T27

R27

VSS107

VSS108

VSS109

12

C372

SCD1U16V2ZY-2GP

12

C356

SCD1U16V2ZY-2GP

C332

1D2V_S0

SC1U10V3KX-3GP

AE26

AE27

VSS106

1D2V_S0

AK29

W19

VSS103

VSS104

VSS105

VDDHT30 VDDHT31

AD21

AK22

VSS102

AK10

AC13

VSS100

VSS101

B

AK5

VSS98

VSS99

N27 U27 V27 G27 V24 H27 K24

AB24

P27

AA27

K27

P24 AB27 AB23

V23

G23

E23

W23

K23

H23

U23 AA23

D23

C23

B23

A23

A29 AC30

AK23 AK28 AK11

AK4 AE30 AC14 AD12 AC18 AC20 AD10 AD14 AD15 AD20 AC10 AD18 AC12 AD22 AC22 AH15

H15 AC17 AC15

B21

C21

A22

B22

C22

E21

G21

AC21

J27

J23

F23

F21 F22

AJ30

VSS96

VSS97

AG27

AC11

AD7

VSS94

VSS95

U61E

VDD_HT1 VDD_HT2 VDD_HT3 VDD_HT4 VDD_HT5 VDD_HT6 VDD_HT7 VDD_HT8 VDD_HT9 VDD_HT10 VDD_HT11 VDD_HT12 VDD_HT13 VDD_HT14 VDD_HT15 VDD_HT16 VDD_HT17 VDD_HT18 VDD_HT19 VDD_HT20 VDD_HT21 VDD_HT22 VDD_HT23 VDD_HT24 VDD_HT25 VDD_HT26 VDD_HT27 VDD_HT28 VDD_HT29 VDD_HT30 VDD_HT31

VDD_DVO_1 VDD_DVO_2 VDD_DVO_3 VDD_DVO_4 VDD_DVO_5 VDD_DVO_6 VDD_DVO_7 VDD_DVO_8 VDD_DVO_9 VDD_DVO_10 VDD_DVO_11 VDD_DVO_12 VDD_DVO_13 VDD_DVO_14 VDD_DVO_15 VDD_DVO_16 VDD_DVO_17 VDD_DVO_18 VDD_DVO_19

VDD_18_1 VDD_18_2 VDD_18_3

VDD_CORE47 VDD_CORE46 VDD_CORE45 VDD_CORE44 VDD_CORE43 VDD_CORE42 VDD_CORE41 VDD_CORE40 VDD_CORE39

AC19

VSS92

VSS93

AG9

VSS91

AG15

AG12

AF30

AG24

VSS88

VSS89

VSS90

VSS132

V28

R23

PART 5 OF 6

AD19

AD23

AG5

AG6

AG21

AD17

VSS82

VSS83

VSS84

VSS85

VSS86

VSS87

VSS126

VSS127

VSS128

VSS129

VSS130

VSS131

P25

P28

E26

K25

V25

U28

VDDA_12_14

VDDA_12_1 VDDA_12_2 VDDA_12_3 VDDA_12_4 VDDA_12_5 VDDA_12_6 VDDA_12_7 VDDA_12_8

VDDA_12_9 VDDA_12_10 VDDA_12_11 VDDA_12_12 VDDA_12_13

VDDA_18_1

VDDA_18PLL_1

VDDA_18_2

VDDA_18_3

VDDA_18_4

VDDA_18_5

VDDA_18PLL_2 VDDA_18PLL_3

VDDA_18_6

VDDA_18_7

VDDA_18_8

VDDA_18_9 VDDA_18_10 VDD_CORE1 VDD_CORE2 VDD_CORE3 VDD_CORE4 VDD_CORE5 VDD_CORE6 VDD_CORE7 VDD_CORE8 VDD_CORE9

VDD_CORE10 VDD_CORE11 VDD_CORE12 VDD_CORE13 VDD_CORE14 VDD_CORE15 VDD_CORE16 VDD_CORE17 VDD_CORE18 VDD_CORE19 VDD_CORE20 VDD_CORE21 VDD_CORE22 VDD_CORE23 VDD_CORE24 VDD_CORE25 VDD_CORE26 VDD_CORE27 VDD_CORE28 VDD_CORE29 VDD_CORE30 VDD_CORE31 VDD_CORE32 VDD_CORE33 VDD_CORE34 VDD_CORE35 VDD_CORE36

POWER

VDD_CORE37 VDD_CORE38

AD13

AD16

VSS80

VSS81

VSS124

VSS125

H24

N28

AD8

AD11

VSS78

VSS79

VSS122

VSS123

M27

AC23

VSS76

VSS77

VSS120

L27

H9 AA7 G9 U8 N7 N8 U7 F9 AA8 G8 G7 J8 J7 B1 AG4 R8 AC8 AC7 AF6 AE6 L8 W8 W7 L7 R7 AF5 AK2 N16 M13 M15 W16 N18 P19 N12 P15 N14 M17 T19 G22 R12 P13 R14 V19 R18 U16 U12 T13 U14 T17 U18 E22 R16 V13 T15 P17 W18 D22 W12 V15 W14 V17 M19 H22 H21 D21

AG18

T23

U19

AC16

VSS73

VSS74

VSS75

VSS117

VSS118

VSS119

K28

N19

VDDA12_13

VDDA18_13

VSS116

J28

M24

M16

P16

VSS72

VSS114

VSS115

F28

H28

N17

W15

V16

T18

M14

M12

VSS66

VSS67

VSS68

VSS69

VSS70

VSS71

GROUND

VSSA68

VSS113

L5

T8

12

C281

1D8V_VDDA

12

C352

1D2V_S0

C

W13

W17

P18

V18

M18

U13

VSS60

VSS61

VSS62

VSS63

VSS64

VSS65

VSSA62

VSSA63

VSSA64

VSSA65

VSSA66

VSSA67

F6

V7

E6

E5

U5

U6

12

C282

SC1U10V3KX-3GP

SCD1U16V2ZY-2GP

12

C318

SC1U10V3KX-3GP

SCD1U16V2ZY-2GP

12

C298

SC10U10V5ZY-1GP

12

C316

DY

SC10U10V5ZY-1GP

R17

P12

T12

R13

VSS56

VSS57

VSS58

VSS59

VSSA58

VSSA59

VSSA60

VSSA61

L6

M7

AJ1

AG3

VSSA59

12

C303

12

C302

12

C299

SCD1U16V2ZY-2GP

12

C315

SCD1U16V2ZY-2GP

U17

T16

VSS54

VSS55

VSSA56

VSSA57

H8

C2

SCD1U16V2ZY-2GP

12

T14

N15

V12

N13

P14

VSS49

VSS50

VSS51

VSS52

VSS53

VSSA51

VSSA52

VSSA53

VSSA54

VSSA55

K7

V6

H7

M3

AD6

12

C306

SCD1U16V2ZY-2GP

12

C293

SCD1U16V2ZY-2GP

12

C300

DY

SCD1U16V2ZY-2GP

12

C314

SCD1U16V2ZY-2GP

R15

VSS48

VSSA50

Y7

12

E15

F15

U15

V14

VSS44

VSS45

VSS46

VSS47

VSSA44

VSSA45

VSSA46

VSSA47

VSSA48

VSSA49

T7

K3

D6

C4

AB8

AD5

1D2V_VDDA_RS480_S0

12

C335

SCD1U16V2ZY-2GP

C336

SCD1U16V2ZY-2GP

12

C292

C270

DY

SCD1U16V2ZY-2GP

12

C317

C305

SCD1U16V2ZY-2GP

H17

H10

H16

H14

E16

D10

VSS37

VSS38

VSS39

VSS40

VSS41

VSS42

VSS43

VSSA37

VSSA38

VSSA39

VSSA40

VSSA41

VSSA42

VSSA43

J5

J3

C9

C7

R6

AA5

C307

SC10U10V5ZY-1GP

12

TC10

TC10 ST100U6D3VDM-6GP

ST100U6D3VDM-6GP

DY

12

SCD1U16V2ZY-2GP

D

T24

F26

W27

D11

H11

AD25

VSS32

VSS33

VSS34

VSS35

VSS36

VSSA32

VSSA33

VSSA34

VSSA35

VSSA36

B4

P7

G3

M5

AF3

AB7

12

TC9

TC9 ST100U6D3VDM-6GP

ST100U6D3VDM-6GP

DY

L11

1 2

MLB-201209-21-GP

C301

SCD1U16V2ZY-2GP

VSS30

E9

D15

AD9

G11

F16

G30

AB28

AB25

D12

AD24

AA28

G17

Y23

AC9

R19

Y27

C28

G16

F25

B30

VSS16

VSS17

VSS18

VSS19

VSS20

VSS21

VSS22

VSS23

VSS24

VSS25

VSS26

VSS27

VSS28

VSS29

VSS30

VSS31

VSSA16

VSSA17

VSSA18

VSSA19

VSSA20

VSSA21

VSSA22

VSSA23

VSSA24

VSSA25

VSSA26

VSSA27

VSSA28

VSSA29

VSSA30

VSSA31

J6

F3

V8

AE3

1 2

1D8V_S0

A2

P8

C8

AA3

AB3

AD3

VSSA22

1D2V_S0

L10

L10 MLB-201209-21-GP

MLB-201209-21-GP

SB 0127

Title

Size Document Number Rev

A3

Date: Sheet

V3

K8

C3

D3

C6

W3

ATI-RS482M (4 of 4) PWR, GND

G13

VSS10

VSS11

VSS12D9VSS13

VSS14

VSS15

VSSA11

VSSA12

VSSA13

VSSA14

VSSA15

F8

Y8

C5

M6

M8

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

Y24

VSS9

VSSA9T3VSSA10

AA6

G14

VSS7

VSS8

VSSA8

R3

G15

AD29

AD27

AC27

VSS3

VSS4

VSS5

VSS6

VSSA3

VSSA4N3VSSA5F7VSSA6F5VSSA7

V5

VDDA12_13

VSSA22

VDDA18_13

VSSA59

VDDHT30

VSS30

VDDHT31

VSS89

E

G10

G12

VSS1

VSS2

PAR 6 OF 6

VSSA1

VSSA2

R5

AE5

12

14 58Thursday, October 13, 2005

of

C264

C264 SC4D7U10V5ZY-3GP

SC4D7U10V5ZY-3GP

C353

C353 SC4D7U10V5ZY-3GP

SC4D7U10V5ZY-3GP

C769

C769 SC4D7U10V5ZY-3GP

SC4D7U10V5ZY-3GP

C815

C815 SC4D7U10V5ZY-3GP

SC4D7U10V5ZY-3GP

SA

A

CRT CONN

200mA Rating/Spec 500mA

5V_S0

4 4

RN4

2

UMA_HS UMA_VS

Dummy when use Discrete

DIS_HS DIS_VS

3 4

Dummy when use UMA

SRN0J-6-GP

RN5

SRN0J-6-GP

VSYNC_5_1

1

2 1

HSYNC_5_1

14

4

5 6

7

2 3

U3B

TSAHCT125PW-GP

14

7

U3A

1

TSAHCT125PW-GP

C2

DUMMY-C2

B

UMA_CRT_DDC_D13

SYS_HS

UMA_CRT_DDC_C13

C

RN3

CRT_DDC_D_1

SRN0J-6-GP

2

CRT_DDC_C_1

1

3 4

D

3D3V_S0

U2

U2 2N7002DW-7F-GP

2N7002DW-7F-GP

34 5 6

2

1

RN1

123

5V_CRT_S0

678

4 5

SRN10KJ-6-GP

SYS_CRT_DDC_D5 SYS_CRT_DDC_C5

E

Dummy when use Discrete

RN2

SYS_VS

12

C1

DUMMY-C2

DIS_CRT_DDC_D50

DIS_CRT_DDC_C50

RN2

SRN0J-6-GP

2 1

3 4

Dummy when use UMA

5V_S0

12

C653

C653 SCD01U25V2KX-3GP

SCD01U25V2KX-3GP

D28

1 2

RB751V-40-1-GP

5V_CRT_S0

3 3

CRT_R_157

CRT_G_157

CRT_B_157

2 2

TV_LUMA57

TV_COMP57

TV_CRMA57

1 1

12

DY

12

C663

SC47P50V2JN-3GP

DY

A

12

C664

C665

SC47P50V2JN-3GP

DY

R148

R132

R138

1 2

150R2F-1-GP

12

R381150R2F-1-GPR381150R2F-1-GP

SC47P50V2JN-3GP

12

-1 0302

R382150R2F-1-GPR382150R2F-1-GP

1 2

C285

C285 SC100P50V2JN-U

SC100P50V2JN-U

1 2

C272

C272 SC100P50V2JN-U

SC100P50V2JN-U

1 2

C261

L18

1 2

L19

1 2

L20

1 2

12

R383150R2F-1-GPR383150R2F-1-GP

C283

1 2

SC47P50V2JN-3GP

L9

IND-1D2UH-5-GP

C271

1 2

SC47P50V2JN-3GP

L8

IND-1D2UH-5-GP

C260

1 2

SC47P50V2JN-3GP

L6

IND-1D2UH-5-GP

SC100P50V2JN-U

BLM11B750S-GP

TV_LUMA_CON

12

C284

C284 SC270P50V2JN-2GP

SC270P50V2JN-2GP

TV_COMP_CON

12

C266

C266 SC270P50V2JN-2GP

SC270P50V2JN-2GP

TV_CRMA_CON

12

C255

SC270P50V2JN-2GP

B

12

C659

SC8D2P50V2CC

D37

3

BAV99PT-GP-U

D34

3

BAV99PT-GP-U

D32

3

BAV99PT-GP-U

12

C660

SC8D2P50V2CC

2

DY

1

2

DY

1

2

DY

1

12

C661

SC8D2P50V2CC

3D3V_S0

3

D27

1

BAV99PT-GP-U

DY

CRT_R

CRT_G

CRT_B

D26

2

BAV99PT-GP-U

DY

TV_LUMA_CON

TV_COMP_CON

TV_CRMA_CON

CRT1

SYS_CRT_DDC_D5

SYS_HS

SYS_VS

SYS_CRT_DDC_C5

C655

12

C651

3

1

2

3

D25

1

BAV99PT-GP-U

DY

2

SC100P50V2JN-U

5V_S0

12

C652

SC10P50V2JN-1

SC100P50V2JN-U

12

C654

SC10P50V2JN-1

CRT_R

CRT_G CRT_B

5V_CRT_S0

10

ME : 20.20378.015

17

6 1

11

7 2

12 8 3

13 9 4

14 5

15

16

20.20378.015

VIDEO-15-42-GP

SYS_CRT_DDC_D5 SYS_HS SYS_VS SYS_CRT_DDC_C5

TV CONN

TV1

1 4

2 5 7 6 3

MINDIN7-11-U-GP

22.10021.D81

ME : 22.10021.D81

C

8

4

56

1

23

7

9

COMPOSIT

D

Title

Size Document Number Rev

A3

Date: Sheet

LUMACHROMA

CRT/TV

CRT/TV Bolsena-E

Bolsena-E

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

15 58Thursday, October 13, 2005

of

E

of

SA

A

B

C

D

E

LEDs

4 4

Dummy when use IDE

R11

EDID_CLK13,50

EDID_DAT13,50

C668

C667

1 2

SC100P50V2JN-U

A

1 2

R21

1 2

0R2J-GP

WLAN_LED#29

0R2J-GP

DCBATOUT

C658

D7

2

1

BAW56PT-U

NUM_LED#34 CAP_LED#34 MAIL_LED#34 BLT_LED#34

STDBY_LED#34 CHARGE_LED#34 DC_BATFULL#34

FRONT_PWRLED#34

MEDIA_LED#

3

LCD CONN

42

2 4

6 8

3D3V_S0

C662

SCD1U25V3ZY-3GP

12

SC10U35V0ZY-1GP

10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 41

ACES-CONN40A-GP

20.F0737.040

1ST 20.D0198.108 - 2ND 20.F0687.040

LCD1

DY

SRC100P50V-2-GP

RC2

NUM_LED# CAP_LED#

MAIL_LED# MEDIA_LED#

WLAN_LED# STDBY_LED#

BLT_LED#

CHARGE_LED#

DC_BATFULL#

FRONT_PWRLED#

LCDPOWER_S0

12

C44

C22

1 3

5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

SB 0202

B

DY

LCD_TXBCLK+ 13,57 LCD_TXBCLK- 13,57 LCD_TXBOUT2+ 13,57 LCD_TXBOUT2- 13,57 LCD_TXBOUT1+ 13,57 LCD_TXBOUT1- 13,57 LCD_TXBOUT0+ 13,57 LCD_TXBOUT0- 13,57 LCD_TXACLK+ 13,57 LCD_TXACLK- 13,57 LCD_TXAOUT2+ 13,57 LCD_TXAOUT2- 13,57 LCD_TXAOUT1+ 13,57 LCD_TXAOUT1- 13,57 LCD_TXAOUT0+ 13,57 LCD_TXAOUT0- 13,57

C22

SC10U10V5ZY-1GP

RC2

1 2 3 4 5

DY

RC11

1 2 3 4 5

C646 SC100P50V2JN-U

DY

1 2

C512 SC100P50V2JN-U

DY

1 2

12

C31

SCD1U25V3ZY-3GP

DY

SCD1U25V3ZY-3GP

EVEN CHANNEL

ODD CHANNEL

8 7 6

SRC100P50V-2-GP

8 7 6

on KB cover

LED ButtonVV

POWER1 E-MAIL INTERNETe-BTN PROGRAM

Front panel

LED ButtonVV

BlutToothWireless Charger Power2

LCD_VDD_ON13,57

C

SATA_LED#18

HDD_LED#_524

Dummy when use SATA

CDROM_LED#_524

3 3

2 2

BRIGHTNESS34

FPBACK34

1 1

NUM_LED#

CAP_LED#

MAIL_LED#

MEDIA_LED#

WLAN_LED#

FRONT_PWRLED#

DC_BATFULL#

BLT_LED#

STDBY_LED#

CHARGE_LED#

R19

1 2

100R2F-L1-GP-U

100R2F-L1-GP-U R26

R26

1 2

100R2F-L1-GP-U

100R2F-L1-GP-U R10

R10

1 2

100R2F-L1-GP-U

100R2F-L1-GP-U R20

R20

1 2

100R2F-L1-GP-U

1 2

R4

1 2

100R2F-L1-GP-U

100R2F-L1-GP-U R24

R24

1 2

100R2F-L1-GP-U

100R2F-L1-GP-U R378

R378

1 2

100R2F-L1-GP-U

R376

1 2

100R2F-L1-GP-U

R579

470R2J-2-GP

1 2

R377

1 2

100R2F-L1-GP-U

100R2F-L1-GP-U R375

R375

1 2

100R2F-L1-GP-U

R580

R580 22R2J-2-GP

22R2J-2-GP

V VVVV

V

VV

V

(Please See M.E. drawing LED position)

LCD POWER

Layout 40 mil

1KR2J-1-GP

12

LCDVDD_ON_1

12

C23

C69

SCD1U25V3ZY-3GP

SC1U10V3KX-3GP

R48

1 2

-2 0408

Charger: Green : DC only with Battery full with DC Orange : Charging Orange Blink : Battery low

U7

1

OUT

2

GND ON/OFF#3IN

AAT4280IGU-3-T1GP

D

LED-G-106-GP

D5

AK

LED-G-106-GP

D4

AK

LED-G-106-GP

D3

AK

LED-G-106-GP

D6

AK

D48 LED-Y-22D48 LED-Y-22

LED-G-106-GP

D2

AK

LED-G-106-GP

D9

AK

LED-G-106-GP

D46

AK

LED-G-106-GP

D44

AK

D47

12

LED-B-27-U-GP

D45 LED-Y-22D45 LED-Y-22

1 2

D43 LED-Y-22D43 LED-Y-22

1 2

CAPS NUM HDD

6

IN

5

GND

4

5V_S0

on KB Cover on KB Cover on KB Cover on KB Cover

on Front Panel

on KB Cover

on Front Panel

5V_S5

on Front Panel

5V_S0

on Front Panel

5V_S5

on Front Panel on Front Panel

VVV

Power2: Green : S0 Orange : S3 Orange Blinking : Enter S4

3D3V_S0LCDPOWER_S0

12

C70

C70 SC1U10V3KX-3GP

SC1U10V3KX-3GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

LCD / LEDs

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

16 58Thursday, October 13, 2005

of

E

of

SA

A

?3.9p need app PN

CHANGE TO - 3.9P -> 78.3R974.1F1

C742

1 2

SC12P50V2JN-LGP

12

4 4

X-32D768KHZ-38GPU

1 2

X7

41

2 3

C760

C760 SC12P50V2JN-LGP

SC12P50V2JN-LGP

CHANGE TO - 3.9P -> 78.3R974.1F1

SB

R488

20MR3-GP

R479

20MR3-GP

32K_X1 32K_X2

PCIE_RX0P_SB12 PCIE_RX0N_SB12 PCIE_RX1P_SB12 PCIE_RX1N_SB12

SBSRC_CLK3 SBSRC_CLK#3

PCIE_TX0P_SB12 PCIE_TX0N_SB12 PCIE_TX1P_SB12 PCIE_TX1N_SB12

MAIN SOURCE: 82.30001.031 EPSON

1D8V_S0

3 3

2 2

1 1

L23

1 2

MLB-201209-21-GP

A_RST# RSTDRV#_R

A_RST#

12

R297

R297 8K2R2J-3-GP

8K2R2J-3-GP

DY

PCIRST#

12

5V_S0

14

13

12 11

TSAHCT125PW-GP

7

3D3V_S5

1 2

DY

3D3V_S5

4 5

DY

R295

1 2

0R2J-GP

PCIE_PVDD

12

C728

C727

1D8V_S0 PCIE_VDDR

SC1U10V3KX-3GP

SC10U10V5ZY-1GP

L24

1 2

0R0603-PAD

INT_PIRQG# INT_PIRQE# INT_PIRQD#

INT_PIRQH#

3D3V_S0

U3D

U39A

147

3

TSLCX08MTCX-GP

U39B

147

6

TSLCX08MTCX-GP

Secondary PCI Bus reset signal.

A

2ND SOURCE: 82.30001.341 KDS

PCIE_VDDR

12

C725

SCD1U16V2ZY-2GP

C735

SC22U6D3V5MX-2GP

RP1

SRN10KJ-L3-GP

33R2J-2-GP

R298

1 2

33R2J-2-GP

R296

1 2

12

DY

1 2 3 4 5 6

R8

1 2

PCIRST# 3V to 5V level shift for HDD & CDROM

SB400 asserts PLTRST# to reset devices on the platform.

R307

1 2

0R2J-GP

PLT_RST#_R

PCI_RST#

C184

SCD1U16V2ZY-2GP

10 9

INT_PIRQC#INT_PIRQF#

8

INT_PIRQB#

7

INT_PIRQA#

RSTDRV#_5 24

10R2J-2-GP

12

C179

DY

SCD1U16V2ZY-2GP

3D3V_S0

LPC_RST# 13,34,37,49

ALLOW_LDTSTOP13 SB_CPUPWRGD6

BMREQ#13 LDT_RST#6

B

DY

A_RST#

C736 SCD01U16V2KX-3GPC736 SCD01U16V2KX-3GP

1 2

C733 SCD01U16V2KX-3GPC733 SCD01U16V2KX-3GP

1 2

C740 SCD01U16V2KX-3GPC740 SCD01U16V2KX-3GP

1 2

C737 SCD01U16V2KX-3GPC737 SCD01U16V2KX-3GP

1 2

R482 150R2F-1-GPR482 150R2F-1-GP

1 2

R473 150R2F-1-GPR473 150R2F-1-GP

1 2

R483 4K12R2F-GPR483 4K12R2F-GP

1 2

A11, A12 4K53 1% A21, A22 5K5 1% A23 4K12 1% PA_IXP400AC10.PDF

12

C233

DY

SCD1U16V2ZY-2GP

TP86TP86 TP85TP85

INT_PIRQE#25,27 INT_PIRQF#25,29 INT_PIRQG#27 INT_PIRQH#30

LDT_STP#6,13

PCIRST_BUF# 25,27,29,30

B

12

C183

SCD1U16V2ZY-2GP

TP92TP92 TP107TP107 TP18TP18 TP93TP93 TP91TP91

TP94TP94 TP11TP11 TP12TP12

TP14TP14

PCIE_PVDD

12

C734

RTC_AUX_S5

C

12

R83

R83 8K2R2J-3-GP

8K2R2J-3-GP

1 OF 4

U55A

AH8

A_RST#

L27

PCIE_RCLKP

M27

TX0P TX0N TX1P TX1N

PCIE_CALRP PCIE_CALRN

PCIE_CALI

SCD1U16V2ZY-2GP

SB_CPUSTP# SB_PCISTP# INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD# INT_PIRQE# INT_PIRQF# INT_PIRQG# INT_PIRQH#

32K_X1 32K_X2

SB_C29 SB_A28 H_NMI FWH_INIT# SB_D29 LPC_LDRQ0#

SB_B30 H_A20M# H_FERR#

H_DPRSLP#H_DPRSLP#

PCIE_RCLKN

M30

PCIE_TX0P

N30

PCIE_TX0N

K30

PCIE_TX1P

L30

PCIE_TX1N

H30

PCIE_TX2P

J30

PCIE_TX2N

F30

PCIE_TX3P

G30

PCIE_TX3N

M29

PCIE_RX0P

N29

PCIE_RX0N

M28

PCIE_RX1P

N28

PCIE_RX1N

J29

PCIE_RX2P

K29

PCIE_RX2N

J28

PCIE_RX3P

K28

PCIE_RX3N

G27

PCIE_CALRP

H27

PCIE_CALRN

G28

PCIE_CALI

R30

PCIE_PVDD

F26

PCIE_VDDR

R29

PCIE_VDDR

G26

PCIE_VDDR

P26

PCIE_VDDR

K26

PCIE_VDDR

L26

PCIE_VDDR

P28

PCIE_VDDR

N26

PCIE_VDDR

P27

PCIE_VDDR

H28

PCIE_VSS

F29

PCIE_VSS

H29

PCIE_VSS

H26

PCIE_VSS

F27

PCIE_VSS

G29

PCIE_VSS

L29

PCIE_VSS

J26

PCIE_VSS

L28

PCIE_VSS

J27

PCIE_VSS

N27

PCIE_VSS

M26

PCIE_VSS

K27

PCIE_VSS

P29

PCIE_VSS

P30

PCIE_VSS

AJ8

CPU_STP#/DPSLP_3V#

AK7

DPSLP_OD#/GPIO37

AG5

INTA#

AH5

INTB#

AJ5

INTC#

AH6

INTD#

AJ6

INTE#/GPIO33

AK6

INTF#/GPIO34

AG7

INTG#/GPIO35

AH7

INTH#/GPIO36

B2

X1

B1

X2

C29

CPU_PG

A28

INTR/LINT0

C28

NMI/LINT1

B29

INIT#

D29

SMI#

E4

SLP#/LDT_STP#

B30

IGNNE#

F28

A20M#

E28

FERR#

E29

STPCLK#/ALLOW_LDTSTP

D25

LDT_PG/SSMUXSEL/GPIO0

E27

DPRSLPVR

D27

BMREQ#

D28

LDT_RST#

R510

12

1KR2J-1-GP

PCI EXPRESS INTERFACE

XTAL

CPU

RTC_AUX_S5_1

41235

RTC1

MLX-CON3-9-GP

20.D0198.103

C

PCI CLKS

PCI INTERFACELPCRTC

REQ3#/PDMA_REQ0#

REQ4#/PLL_BP33/PDMA_REQ1#

GNT3#/PLL_BP66/PDMA_GNT0# GNT4#/PLL_BP50/PDMA_GNT1#

RTC_IRQ#/ACPWR_STRAP

12

EC71

EC71 SC470P50V2KX

SC470P50V2KX

1 OF 4

PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5 PCICLK6 PCICLK7 PCICLK8 PCICLK9

PCICLK_FB

PCIRST# AD0/ROMA18 AD1/ROMA17 AD2/ROMA16 AD3/ROMA15 AD4/ROMA14 AD5/ROMA13 AD6/ROMA12 AD7/ROMA11

AD8/ROMA9

AD9/ROMA8 AD10/ROMA7 AD11/ROMA6 AD12/ROMA5 AD13/ROMA4 AD14/ROMA3 AD15/ROMA2 AD16/ROMD0 AD17/ROMD1 AD18/ROMD2 AD19/ROMD3 AD20/ROMD4 AD21/ROMD5 AD22/ROMD6 AD23/ROMD7

AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

CBE0#/ROMA10

CBE1#/ROMA1

CBE2#/ROMWE#

CBE3#

FRAME#

DEVSEL#/ROMA0

IRDY#

TRDY#/ROMOE#

PAR/ROMA19

STOP# PERR# SERR# REQ0# REQ1# REQ2#

REQ5#/GPIO13 REQ6#/GPIO31

GNT0# GNT1# GNT2#

GNT5#/GPIO14 GNT6#/GPIO32

CLKRUN#

LOCK#

LAD0 LAD1 LAD2 LAD3

LFRAME#

LDRQ0# LDRQ1#

SERIRQ RTCCLK

VBAT

RTC_GND

L4

PCI_CLK1_R

L3

PCI_CLK2_R

L2

PCI_CLK3_R

L1

PCI_CLK4_R

M4

PCI_CLK5_R

M3

PCI_CLK6_R

M2

PCLK_R5C833_R

M1 N4

PCI_CLK9_R

N3

PCI_CLK9_FB

N2 AJ7

W3 Y2 W4 Y3 V1 Y4 V2 W2 AA4 V4 AA3 U1 AA2 U2 AA1 U3 T4 AC1 R2 AD4 R3 AD3 R4 AD2 P2 AE3 P3 AE2 P4 AF2 N1 AF1 V3 AB4 AC2 AE4 T3 AC4 AC3 T2 U4 T1 AB2 AB3 AF4 AF3 AG2 AG3 AH1 AH2 AH3 AJ2 AK2 AJ3 AK3 AG4 AH4 AJ4 AG1 AB1

AG25 AH25 AJ25 AH24 AG24 AH26 AG26

AK27 C2

F3 A2

A1

PCIRST# PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31

PCI_REQ#3PCI_REQ#3

PCI_REQ#4

PCI_REQ#5 PCI_REQ#6

PCI_GNT#3 PCI_GNT#4 PCI_GNT#5 PCI_GNT#6

LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3

LPC_LDRQ1#

P_SERIRQ 27,34,37

RTC_CLK 21 AUTO_ON# 21

VBAT

12

C761

SCD1U16V2ZY-2GP

D

RN102

1 2 3 4 5 4 5 3 2 1

R459

1 2

22R2J-2-GP

PCI_AD[31..0] 21,25,27,29,30

3D3V_S0

10

12345 6

3D3V_S0

TP10TP10

PCI_LOCK#

LPC_LAD[0..3] 34,37

LPC_LFRAME# 21,34,37 LPC_LDRQ0# 37

3D3V_AUX_S5

3

12

C762

SC1U10V3KX-3GP

RTC_AUX_S5

D

32K suspend clock output

PM_SLP_S3#20,34,38,39,45,56 RTC_CLK21

SRN22J-2-GP

8 7 6

6 7 8

CLK33_CBUS CLK33_LAN CLK33_MINI CLK33_KBC CLK33_SIO PCLK_R5C832 CLK33_LPCROM

RN98 SRN22J-2-GPRN98 SRN22J-2-GP

PCI_CLK8 21

1 2

DY

789

RN15

RN15 SRN10KJ-L1-GP-U

SRN10KJ-L1-GP-U

Close to chip

U58

U58 BAT54C-1-GP

BAT54C-1-GP

1 2

R4518K2R2J-3-GP R4518K2R2J-3-GP

12

3D3V_S0

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

5V_S5

U33A

147

1 2

PCLK_R5C832 CLK33_CBUS CLK33_LAN CLK33_MINI CLK33_KBC

C724SC100P50V2JN-UDYC724SC100P50V2JN-U

CLK33_SIO CLK33_LPCROM

3D3V_S0

PCI_GNT#5 PCI_GNT#6

RN13

SRN10KJ-L1-GP-U

1 2 3 4 5 6

ATI-SB450 (1 of 5) PCI, PCIE

10 9 8 7

1

LPC_LAD0

2

LPC_LAD3

3

LPC_LAD2

4

LPC_LAD1

5 6

Bolsena-E SA

1 2

3

TSLCX08MTCX-GP

12

R92

R92 DUMMY-R2

DUMMY-R2

12

R93

R93 DUMMY-R2

DUMMY-R2

RN12

SRN10KJ-L1-GP-U

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

E

R280

10R2J-2-GP

PCLK_R5C832 21,27 CLK33_CBUS 25 CLK33_LAN 21,30 CLK33_MINI 21,29 CLK33_KBC 21,34 CLK33_SIO 21,37 CLK33_LPCROM 21

PCB-Ver

12

R430

R430 DUMMY-R2

DUMMY-R2

12

R429

R429 DUMMY-R2

DUMMY-R2

PCI_CBE#0 25,27,29,30 PCI_CBE#1 25,27,29,30 PCI_CBE#2 25,27,29,30 PCI_CBE#3 25,27,29,30 PCI_FRAME# 25,27,29,30 PCI_DEVSEL# 25,27,29,30 PCI_IRDY# 25,27,29,30 PCI_TRDY# 25,27,29,30 PCI_PAR 25,27,29,30 PCI_STOP# 25,27,29,30 PCI_PERR# 25,27,29,30 PCI_SERR# 25,27,29,30

PCI_REQ#0 29 PCI_REQ#1 25 PCI_REQ#2 30 PCI_REQ#3 27

PCI_GNT#0 29 PCI_GNT#1 25 PCI_GNT#2 30 PCI_GNT#3 27

PM_CLKRUN# 25,27,29,30,34,37

10

LPC_LDRQ1#

9

LPC_LDRQ0#

8

P_SERIRQ

7

3D3V_S0

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CLK32_G791 22

A

U55B

AK22

AJ22

AK21

AJ21

AK19

AJ19

AK18

AJ18

AK14

AJ14

AK13

AJ13

AK11

AJ11

AK10

AJ10 AJ15 AJ16

AK16

AK8

AH15 AH16

AG10 AG14 AH12 AG12 AG18 AG21 AH18 AG20

AG9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22

AH9 AG11 AG15 AG17 AG19 AG22 AG23

AF9 AH17 AH23 AH13 AH20

AK9

AJ12 AK17 AK23

U55B

SATA_TX0+ SATA_TX0-

SATA_RX0SATA_RX0+

SATA_TX1+ SATA_TX1-

SATA_RX1SATA_RX1+

SATA_TX2+ SATA_TX2-

SATA_RX2SATA_RX2+

SATA_TX3+ SATA_TX3-

SATA_RX3SATA_RX3+

SATA_CAL SATA_X1

SATA_X2 SATA_ACT# PLLVDD_SATA

XTLVDD_SATA AVDD_SATA

AVDD_SATA AVDD_SATA AVDD_SATA AVDD_SATA AVDD_SATA AVDD_SATA AVDD_SATA

AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA

4 4

SATA_TXP024 SATA_TXN024

SATA_RXN024 SATA_RXP024

C704 SCD01U50V3KX-4GPC704 SCD01U50V3KX-4GP

1 2

C703 SCD01U50V3KX-4GPC703 SCD01U50V3KX-4GP

1 2

C630 SCD01U50V3KX-4GPC630 SCD01U50V3KX-4GP

1 2

C629 SCD01U50V3KX-4GPC629 SCD01U50V3KX-4GP

1 2

SATA_TP0 SATA_TN0

SATA_RN0

SATA_RP0

Close to SouthBridge

R431

1 2

1KR2F-3-GP

C700

1 2

SCD01U50V3KX-4GP

DY

3 3

SATA_X2

12

R432

10MR2J-L-GP

SATA_X1

DY

1D8V_SX_S0

1 2

X6

XTAL-25MHZ-70GP

1 2

SATA_LED#16

1D8V_SP_S0

C701

C701 SC27P50V2JN-2-GP

SC27P50V2JN-2-GP

C702

C702 SC27P50V2JN-2-GP

SC27P50V2JN-2-GP

Dummy when use IDE

R433

R433 0R2J-GP

0R2J-GP

1D8V_SATA_S0

12

R102

R102 0R2J-GP

0R2J-GP

2 2

SATA_X1

12

Dummy when use SATA

1D8V_SATA_S0

SATA_X1 SATA_X2

B

SERIAL ATA

PRIMARY ATA 66/100SECONDARY ATA 66/100

SERIAL ATA

PRIMARY ATA 66/100SECONDARY ATA 66/100

SERIAL ATA POWER

2 OF 4

PIDE_IORDY

PIDE_IRQ

PIDE_A0 PIDE_A1 PIDE_A2

PIDE_DACK#

PIDE_DRQ PIDE_IOR# PIDE_IOW# PIDE_CS1# PIDE_CS3#

PIDE_D0 PIDE_D1 PIDE_D2 PIDE_D3 PIDE_D4 PIDE_D5 PIDE_D6 PIDE_D7 PIDE_D8

PIDE_D9 PIDE_D10 PIDE_D11 PIDE_D12 PIDE_D13 PIDE_D14 PIDE_D15

SIDE_IORDY

SIDE_IRQ

SIDE_A0

SIDE_A1

SIDE_A2

SIDE_DACK#

SIDE_DRQ SIDE_IOR# SIDE_IOW# SIDE_CS1# SIDE_CS3#

SIDE_D0/GPIO15 SIDE_D1/GPIO16 SIDE_D2/GPIO17 SIDE_D3/GPIO18 SIDE_D4/GPIO19 SIDE_D5/GPIO20 SIDE_D6/GPIO21 SIDE_D7/GPIO22 SIDE_D8/GPIO23

SIDE_D9/GPIO24 SIDE_D10/GPIO25 SIDE_D11/GPIO26 SIDE_D12/GPIO27 SIDE_D13/GPIO28 SIDE_D14/GPIO29 SIDE_D15/GPIO30

AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA

AD30 AE28 AD27 AC27 AD28 AD29 AE27 AE30 AE29 AC28 AC29

AF29 AF27 AG29 AH30 AH28 AK29 AK28 AH27 AG27 AJ28 AJ29 AH29 AG28 AG30 AF30 AF28

V29 T27 T28 U29 T29 V30 U28 W29 W30 R27 R28

V28 W28 Y30 AA30 Y28 AA28 AB28 AB27 AB29 AA27 Y27 AA29 W27 Y29 V27 U27

AG13 AH22 AK12 AH11 AJ17 AH14 AH19 AJ20 AH21 AJ9 AG16 AH10 AJ23 AK15 AK20

PIDE_D0 PIDE_D1 PIDE_D2 PIDE_D3 PIDE_D4 PIDE_D5 PIDE_D6 PIDE_D7 PIDE_D8 PIDE_D9 PIDE_D10 PIDE_D11 PIDE_D12 PIDE_D13 PIDE_D14 PIDE_D15

SIDE_D0 SIDE_D1 SIDE_D2 SIDE_D3 SIDE_D4 SIDE_D5 SIDE_D6 SIDE_D7 SIDE_D8 SIDE_D9 SIDE_D10 SIDE_D11 SIDE_D12 SIDE_D13 SIDE_D14 SIDE_D15

C

PIDE_IORDY 24 PIDE_IRQ14 24 PIDE_A0 24 PIDE_A1 24 PIDE_A2 24

PIDE_DREQ 24 PIDE_IOR# 24 PIDE_IOW# 24 PIDE_CS#0 24 PIDE_CS#1 24

PIDE_D[15..0] 24

SIDE_IORDY 24 SIDE_IRQ15 24 SIDE_A0 24 SIDE_A1 24 SIDE_A2 24 SIDE_DACK# 24 SIDE_DREQ 24 SIDE_IOR# 24 SIDE_IOW# 24 SIDE_CS#0 24 SIDE_CS#1 24

SIDE_D[15..0] 24

R361

12

also strap function

0R0402-PAD

PIDE_DACK# 24

PDACK# 21

D

E

1D8V_S0 1D8V_SATA_S0

R105

1 1

1 2

0R5J-5-GP

12

A

12

C127

SC10U10V5ZY-1GP

12

C155

SCD1U50V3ZY-GP

12

C128

C160

SCD1U50V3ZY-GP

12

C129

SCD1U50V3ZY-GP

L4

1 2

0R3J-3-GP

Capacitor PLACE NEAR THE ACCORDED BALLS

B

12

C157

C157 SC2D2U16V5ZY-GP

SC2D2U16V5ZY-GP

1D8V_S01D8V_S0 1D8V_SX_S01D8V_SP_S0

L5

1 2

0R3J-3-GP

Capacitor PLACE NEAR THE ACCORDED BALLS

12

Dummy when use IDE

C159

C159 SC2D2U16V5ZY-GP

SC2D2U16V5ZY-GP

C

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

ATI-SB400 (2 of 5) IDE

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

D

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

SA

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Acer Aspire 3040, Aspire 5040 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual