Acer Aspire 3040, Aspire 5040 Schematics

See 'TEXT' in 0MEMO or 1MEMO property in component

5

4

3

2

1

Dummy when use '10/100'

Dummy when use 'GIGA'

Dummy when use 'UMA'

D D

Dummy when use 'DIS'

Dummy when use 'SATA'

Dummy when use 'IDE'

CLK GEN

IDT CV137

LEDs

RTC BAT.

PWR SW

CP2211

PCMCIA SLOT

Support TypeII

26

MS/MS Pro/xD/

C C

MMC/SD

5 in 1

PCMCIA I/F

28

26

RICOH

BUTTONs

ENE

CB1410

1* Slot Cardbus

25

R5C832

1394 CONN

28

Mini-PCI

802.11a/b/g

29

RJ45

31

B B

TXFM

1394

CardReader

31

27,28

1000Mb

10/100Mb

PCI Bus / 33MHz

PCI LAN

Realtek RTL8110SBL 1000/100/10 RTL8100C 100/10

Bolsena-E(AB2) Block Diagram

AMD CPU

3

16 17 33

35W/25W

4,5,6,7

HyperTransport

6.4GB/S 16b/8b

ATI

RS482M

AGTL+ CPU I/F + UMA

11,12,13,14

PCI-Express x2

PCI Express x16

ATI

SB450

ACPI 2.0

PCI

30

ATA 133

6xUSB 2.0

AZALIA

LPC I/F

17,18,19,20,21

DDR 333/400

USB x 4

24

AZALIA

MODEM MDC Card

LPC Bus / 33MHz

ATI

M52P

49,50,51,52,53

VRAM x4

54,55

RJ11 CONN

31

200-PIN DDR SODIMM

DDR x2

CODEC

ALC883

OP AMP

G1421

8,9,10

RGB CRT

32

3323

LVDS

tv

LCD

CRT

BlueTooth miniUSB

Line In MIC In

Line Out

Int. SPKR

16

15

23

3

33

Project Code: 91.4G401.001 REVISION: 05236-SA

PCB Layer Stackup

L1: Signal 1 L2:VCC L3: Signal 2 L4: Signal 3 L5: GND L6: Signal 4

Power Block Diag -> Page 40

NS SIO

PC87381

37

SATA

PIDE

HDD

24

SIDE

DVD/ CD-RW

24

FIR

TFDU6102

A A

5

4

3

37

2

Thermal & Fan

G792

KBC

23

Title

Size Document Number Rev

Date: Sheet

KB3910

Touch Pad

35 35

BLOCK DIAGRAM

A3

Bolsena-E

Int. KB

XBUS

34

ISA ROM

36

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

158Thursday, October 13, 2005

1

of

SA

5

4

3

2

1

PCI Routing

IRQ

MiniPCI

LAN

D D

21 23 2 22 17411 E (CardBus)

F H

17 37411 G (1394) 17 37411 E (FlashMedia)

C C

REQ/GNTIDSEL

0

B B

Ref. function schematic BOM

------------------------U81 cpu socket 62.10055.121 (DON'T CHANGE) (3mm high) U80 north bridge 71.RS482.M03 71.RS482.M03 (ver A12) U43 south bridge 71.SB400.B0U 71.SB400.D0U (ver A13) U32 clock gen. 71.00137.C0W 71.00137.C0W

--U70 VGA M52 71.0M52P.A0U U64 VRAM FOR M52 U65 VRAM FOR M52 U69 VRAM FOR M52 U71 VRAM FOR M52

--U66 BIOS SOCKET 72.39040.G03 62.10002.032 (NO NEED WHEN PD)

A A

U66 BIOS IC 72.39040.G03 72.39040.H03 (DIP STAGE IN LAB, SMT IN PD)

--U75 GIGA LAN 71.08110.00G 71.08110.A0G U75 10/100 LAN 71.08110.00G 71.08100.C0G

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

HISTORY

Bolsena-E

258Thursday, October 13, 2005

of

1

of

SA

A

3D3V_S0

L13

1 2

0R0603-PAD

4 4

SMBD_SB8,20

3 3

SMBC_SB8,20

12

C490

C490 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

C485

C485 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

C476

C476 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

C486

C486 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

C443

C443 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

C489

C489 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

RN48 SRN33J-5-GP-URN48 SRN33J-5-GP-U

1 2

CLK48_USB20

2 3 1

12

C445

C445 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

C488

C488 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C459

SC33P50V2JN-3GP

X-14D318MHZ-18GP

1 2

C472

SC33P50V2JN-3GP

4

CLK14_NB13

SB_OSC_CLK20 CLK14_SIO37

B

12

C444

C444 SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

3D3V_CLK_VDDA

3D3V_S0 3D3V_CLK_VDD

3D3VDD48_S0

12

C446

C446 SC2D2U16V5ZY-GP

SC2D2U16V5ZY-GP

12

R223

R223 DUMMY-R3

DUMMY-R3

USB_48M SMBC_CLK SMBD_CLK

R218 22R2J-2-GPR218 22R2J-2-GP

1 2

2 3 1

RN54 SRN33J-5-GP-URN54 SRN33J-5-GP-U

1 2

12

R242 33R2J-2-GPR242 33R2J-2-GP

1 2

75R2F-2-GP

R241

R249

R249 100R2F-L1-GP-U

100R2F-L1-GP-U

4

IREF_CLKGEN

12

FS2 FS1 FS0

CLK_HTT66

R240

R240 475R2F-L1-GP

475R2F-L1-GP

X2

HTREF_CLK13

1 2

0R0603-PAD

XI_CLK

XO_CLK

L14

U23

3

VDD_48

39

VDDA

32

VDD_SRC

21

VDD_SRC

14

VDD_SRC

35

VDD_SRC

56

VDD_REF

51

VDD_PC1

43

VDD_CPU

48

VDD_HTT

1

XIN

2

XOUT

4

USB_48

7

SCL

8

SDA

10

CLKREQ0#

11

CLKREQ1#

9

SEL24/24_48#

53

REF1

54

REF0

52

REF2

47

HTT66

50

PCI0

37

IREF

6

NC#6

IDTCV137PAG-2-GP

71.00137.C0W

C

SRCC0 SRCT0 SRCC3 SRCT3 SRCC4 SRCT4 SRCC5 SRCT5 SRCC6 SRCT6 SRCC7 SRCT7

CPUC1 CPUT1 CPUC0 CPUT0

SRCC1 SRCT1 SRCC2 SRCT2

VSS_SRC VSS_SRC

RESET#

TURBO1

VSS_CPU

VSS_PCI

VSS_HTT

VSS_SRC

VSS_48

VSS_REF

VSSA

33 34 25 24 23 22 19 18 17 16 13 12

40 41 44 45

29 30 28 27

36 20 15 26

42 49 46 31 38 5 55

3D3V_CLK_VDDA3D3V_CLK_VDD

SRC_CLK0# SRC_CLK0 SRC_CLK3# SRC_CLK3

CPUCLKJ_CY CPUCLK_CY

12

C487

SCD1U16V2ZY-2GP

ATI_CLK0# ATI_CLK0 ATI_CLK1# ATI_CLK1

3D3V_S0

L15

1 2

0R0603-PAD

12

C496

C496 SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

2 3 1

1 2 3

R247 15R2J-L1-GPR247 15R2J-L1-GP

1 2

R248 15R2J-L1-GPR248 15R2J-L1-GP

1 2

RN52

2 3 1

4

SRN33J-5-GP-U

RN46

1

4

2 3

SRN33J-5-GP-U

Dummy when use UMA

D

RN53

SRN33J-5-GP-U

4

RN47

4

SRN33J-5-GP-U

CPUCLK# 6

CPUCLK 6

NBSRC_CLK# 13 NBSRC_CLK 13

GFX_CLK# 49 GFX_CLK 49

SBLINK_CLK# 13 SBLINK_CLK 13

SBSRC_CLK# 17 SBSRC_CLK 17

SBLINK_CLK SBLINK_CLK#

SBSRC_CLK# SBSRC_CLK

GFX_CLK# GFX_CLK

E

RN58

2 3 1

RN38

2 3 1

RN37

1 2 3

SRN49D9F-GP

4

SRN49D9F-GP

4

SRN49D9F-GP

4

Dummy when use UMA

2 2

SRN49D9F-GP

RN57

NBSRC_CLK# NBSRC_CLK

3D3V_CLK_VDD

DY

R245

1 2

2K2R2J-2-GP

1 2

DUMMY-R2

R246

R243

1 2

1 1

R216

1 2 1 2

2K2R2J-2-GP

DUMMY-R2

R244

2K2R2J-2-GP

2K2R2J-2-GP DUMMY-R2

DUMMY-R2

R217

DY

for ICS

A

FS0

FS1

FS2

Title

Size Document Number Rev

A3

Date: Sheet

B

C

D

Date: Sheet

CLKGEN_IDTCV137

Bolsena-E

RN57

2 3 1

4

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

358Thursday, October 13, 2005

of

E

of

SA

A

4 4

B

C

D

E

HTT for CPU sideA Transmit power and NB sideA Receive power

1D2V_S0

12

3 3

C289

C289 SCD22U16V3ZY-GP

SCD22U16V3ZY-GP

12

C268

C268 SCD22U16V3ZY-GP

SCD22U16V3ZY-GP

12

C273

C273 SCD22U16V3ZY-GP

SCD22U16V3ZY-GP

NB0CADOUT[15..0]11 NB0CADOUTJ[15..0]11

Used SideB Power Plane

2 2

1D2V_HT0B_S0

12

C269

C269 SCD22U16V3ZY-GP

SCD22U16V3ZY-GP

NB0HTTCLKOUT111 NB0HTTCLKOUTJ111 NB0HTTCLKOUT011 NB0HTTCLKOUTJ011

R141 49D9R2F-GPR141 49D9R2F-GP

1 2

R140 49D9R2F-GPR140 49D9R2F-GP

1 2

NB0HTTCTLOUT11 NB0HTTCTLOUTJ11

NB0CADOUT15 NB0CADOUTJ15 NB0CADOUT14 NB0CADOUTJ14 NB0CADOUT13 NB0CADOUTJ13 NB0CADOUT12 NB0CADOUTJ12 NB0CADOUT11 NB0CADOUTJ11 NB0CADOUT10 NB0CADOUTJ10 NB0CADOUT9 NB0CADOUTJ9 NB0CADOUT8 NB0CADOUTJ8 NB0CADOUT7 NB0CADOUTJ7 NB0CADOUT6 NB0CADOUTJ6 NB0CADOUT5 NB0CADOUTJ5 NB0CADOUT4 NB0CADOUTJ4 NB0CADOUT3 NB0CADOUTJ3 NB0CADOUT2 NB0CADOUTJ2 NB0CADOUT1 NB0CADOUTJ1 NB0CADOUT0 NB0CADOUTJ0

NB0HTTCLKOUT1 NB0HTTCLKOUTJ1 NB0HTTCLKOUT0 NB0HTTCLKOUTJ0

CPUHTTCTLIN1 CPUHTTCTLINJ1 NB0HTTCTLOUT NB0HTTCTLOUTJ

W27

W26 AA27 AA26 AB25 AA25 AC27 AC26 AD25 AC25

W29 AB29 AA29 AB27 AB28 AD29 AC29 AD27 AD28

W25

D29 D27 D25 C28 C26 B29 B27

T25 R25 U27 U26 V25 U25

T27 T28 V29 U29 V27 V28 Y29

Y25 Y27

Y28 R27

R26 T29 R29

U62A

VLDT0_A VLDT0_A VLDT0_A VLDT0_A VLDT0_A VLDT0_A VLDT0_A

L0_CADIN_H15 L0_CADIN_L15 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H0 L0_CADIN_L0

L0_CLKIN_H1 L0_CLKIN_L1 L0_CLKIN_H0 L0_CLKIN_L0

L0_CTLIN_H1 L0_CTLIN_L1 L0_CTLIN_H0 L0_CTLIN_L0

62.10055.121

VLDT0_B VLDT0_B VLDT0_B VLDT0_B VLDT0_B VLDT0_B VLDT0_B

L0_CADOUT_H15

L0_CADOUT_L15

L0_CADOUT_H14

L0_CADOUT_L14

L0_CADOUT_H13

L0_CADOUT_L13

L0_CADOUT_H12

L0_CADOUT_L12

L0_CADOUT_H11

L0_CADOUT_L11

L0_CADOUT_H10

L0_CADOUT_L10

L0_CADOUT_H9

L0_CADOUT_L9

L0_CADOUT_H8

L0_CADOUT_L8

L0_CADOUT_H7

L0_CADOUT_L7

L0_CADOUT_H6

L0_CADOUT_L6

L0_CADOUT_H5

L0_CADOUT_L5

L0_CADOUT_H4

L0_CADOUT_L4

L0_CADOUT_H3

L0_CADOUT_L3

L0_CADOUT_H2

L0_CADOUT_L2

L0_CADOUT_H1

L0_CADOUT_L1

L0_CADOUT_H0

L0_CADOUT_L0 L0_CLKOUT_H1

L0_CLKOUT_L1

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CTLOUT_H1

L0_CTLOUT_L1

L0_CTLOUT_H0

L0_CTLOUT_L0

AH29 AH27 AG28 AG26 AF29 AE28 AF25

N26 N27 L25 M25 L26 L27 J25 K25 G25 H25 G26 G27 E25 F25 E26 E27 N29 P29 M28 M27 L29 M29 K28 K27 H28 H27 G29 H29 F28 F27 E29 F29

J26 J27 J29 K29

N25 P25 P28 P27

CPUCADOUT15 CPUCADOUTJ15 CPUCADOUT14 CPUCADOUTJ14 CPUCADOUT13 CPUCADOUTJ13 CPUCADOUT12 CPUCADOUTJ12 CPUCADOUT11 CPUCADOUTJ11 CPUCADOUT10 CPUCADOUTJ10 CPUCADOUT9 CPUCADOUTJ9 CPUCADOUT8 CPUCADOUTJ8 CPUCADOUT7 CPUCADOUTJ7 CPUCADOUT6 CPUCADOUTJ6 CPUCADOUT5 CPUCADOUTJ5 CPUCADOUT4 CPUCADOUTJ4 CPUCADOUT3 CPUCADOUTJ3 CPUCADOUT2 CPUCADOUTJ2 CPUCADOUT1 CPUCADOUTJ1 CPUCADOUT0 CPUCADOUTJ0

CPUHTTCLKOUT1 CPUHTTCLKOUTJ1 CPUHTTCLKOUT0 CPUHTTCLKOUTJ0

CPUHTTCTLOUT0 CPUHTTCTLOUTJ0

HTT for CPU sideB Receive power and NB sideA Transmit power

1D2V_HT0B_S0

12

Used SideA Power Plane

CPUHTTCLKOUT1 11 CPUHTTCLKOUTJ1 11 CPUHTTCLKOUT0 11 CPUHTTCLKOUTJ0 11

CPUHTTCTLOUT0 11 CPUHTTCTLOUTJ0 11

LAYOUT: Place bypass cap on topside of board near

C267

C267 SC4D7U10V5ZY-3GP

SC4D7U10V5ZY-3GP

HTT power pins that are not connected directly to downstream HTT device, but connected internally to other HTT power pins.

CPUCADOUT[15..0] 11 CPUCADOUTJ[15..0] 11

ME : 62.10055.121

1 1

A

B

2nd:62.10055.101

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

C

D

Date: Sheet

CPU(1/4)_HyperTransport I/F

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

SA

458Thursday, October 13, 2005

of

E

of

SA

A

VREF_DDR_MEM

B

C

D

E

NOTE: Test with passive probes only. NOTE: Install to bypass op-amp

2D5V_S3

4 4

12

R222

R222 100R2F-L1-GP-U

100R2F-L1-GP-U

R229

R229 100R2F-L1-GP-U

100R2F-L1-GP-U

C470

C470 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

VREF_DDR_MEM

12

C474

C474 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C473

C473 SC1000P50V2JN-N1

SC1000P50V2JN-N1

2D5V_S3

M_DATA[63..0]9

1 2 1 2

LAYOUT: Locate close to DIMMs.

NOTE: Remove to bypass op-amp

3 3

VREF_DDR_CLAW

2D5V_S3

12

2 2

Place it near CPU

1 1

12

R166

R166 100R2F-L1-GP-U

100R2F-L1-GP-U

R162

R162 100R2F-L1-GP-U

100R2F-L1-GP-U

C348

C348 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

VREF_DDR_CLAW

C338

C338 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

LAYOUT: Locate close to CPU.

R173

1 2

R168

1 2

R172

1 2

R167

1 2

121R2F-GP

A

M_CLK7 M_CLK#7

M_CLK6 M_CLK#6

M_CLK5 M_CLK#5

M_CLK4 M_CLK#4

12

C349

C349 SC1000P50V2JN-N1

SC1000P50V2JN-N1

M_ADM[7..0]9

M_DQS[7..0]9

B

TP44TPAD30 TP44TPAD30

VREF_DDR_CLAW

R169 34D8R2F-N1-GPR169 34D8R2F-N1-GP R163 34D8R2F-N1-GPR163 34D8R2F-N1-GP

DDRVTT_SENSE

MEMZN MEMZP

M_DATA63 M_DATA62 M_DATA61 M_DATA60 M_DATA59 M_DATA58 M_DATA57 M_DATA56 M_DATA55 M_DATA54 M_DATA53 M_DATA52 M_DATA51 M_DATA50 M_DATA49 M_DATA48 M_DATA47 M_DATA46 M_DATA45 M_DATA44 M_DATA43 M_DATA42 M_DATA41 M_DATA40 M_DATA39 M_DATA38 M_DATA37 M_DATA36 M_DATA35 M_DATA34 M_DATA33 M_DATA32 M_DATA31 M_DATA30 M_DATA29 M_DATA28 M_DATA27 M_DATA26 M_DATA25 M_DATA24 M_DATA23 M_DATA22 M_DATA21 M_DATA20 M_DATA19 M_DATA18 M_DATA17 M_DATA16 M_DATA15 M_DATA14 M_DATA13 M_DATA12 M_DATA11 M_DATA10 M_DATA9 M_DATA8 M_DATA7 M_DATA6 M_DATA5 M_DATA4 M_DATA3 M_DATA2 M_DATA1 M_DATA0

M_ADM8 M_ADM7 M_ADM6 M_ADM5 M_ADM4 M_ADM3 M_ADM2 M_ADM1 M_ADM0 M_DQS8 M_DQS7 M_DQS6 M_DQS5 M_DQS4 M_DQS3 M_DQS2 M_DQS1 M_DQS0

AE13

AG12

D14 C14

A16 B15 A12 B11 A17 A15 C13 A11 A10

C11

AC1 AC3

AC2 AD1 AE1 AE3

AG3

AJ4

AE2

AF1

AH3

AJ3 AJ5 AJ6

AJ7 AH9 AG5 AH5

AJ9

AJ10

AH11

AJ11

AH15

AJ15

AG11

AJ12 AJ14 AJ16

A13

AA1 AG1 AH7

AH13

A14

AB1

AJ2

AJ8

AJ13

B9 C7 A6

A9 A5 B5 C5 A4 E2 E1 A3 B3 E3

F1 G2 G1

L3

L1 G3

J2

L2 M1 W1 W3

W2

Y1

R1

A7

C2

H1

T1

A8

D1

J1

VTT_SENSE

MEMVREF1 MEMZN

MEMZP

MEMDATA63 MEMDATA62 MEMDATA61 MEMDATA60 MEMDATA59 MEMDATA58 MEMDATA57 MEMDATA56 MEMDATA55 MEMDATA54 MEMDATA53 MEMDATA52 MEMDATA51 MEMDATA50 MEMDATA49 MEMDATA48 MEMDATA47 MEMDATA46 MEMDATA45 MEMDATA44 MEMDATA43 MEMDATA42 MEMDATA41 MEMDATA40 MEMDATA39 MEMDATA38 MEMDATA37 MEMDATA36 MEMDATA35 MEMDATA34 MEMDATA33 MEMDATA32 MEMDATA31 MEMDATA30 MEMDATA29 MEMDATA28 MEMDATA27 MEMDATA26 MEMDATA25 MEMDATA24 MEMDATA23 MEMDATA22 MEMDATA21 MEMDATA20 MEMDATA19 MEMDATA18 MEMDATA17 MEMDATA16 MEMDATA15 MEMDATA14 MEMDATA13 MEMDATA12 MEMDATA11 MEMDATA10 MEMDATA9 MEMDATA8 MEMDATA7 MEMDATA6 MEMDATA5 MEMDATA4 MEMDATA3 MEMDATA2 MEMDATA1 MEMDATA0

MEMDQS17 MEMDQS16 MEMDQS15 MEMDQS14 MEMDQS13 MEMDQS12 MEMDQS11 MEMDQS10 MEMDQS9 MEMDQS8 MEMDQS7 MEMDQS6 MEMDQS5 MEMDQS4 MEMDQS3 MEMDQS2 MEMDQS1 MEMDQS0

U62BU62B

MEMRESET_L

MEMCLK_H7 MEMCLK_L7 MEMCLK_H6 MEMCLK_L6 MEMCLK_H5 MEMCLK_L5 MEMCLK_H4 MEMCLK_L4 MEMCLK_H3 MEMCLK_L3 MEMCLK_H2 MEMCLK_L2 MEMCLK_H1 MEMCLK_L1 MEMCLK_H0 MEMCLK_L0

MEMCS_L7 MEMCS_L6 MEMCS_L5 MEMCS_L4 MEMCS_L3 MEMCS_L2 MEMCS_L1 MEMCS_L0

MEMRASA_L MEMCASA_L

MEMWEA_L

MEMBANKA1 MEMBANKA0

MEMADDA13 MEMADDA12 MEMADDA11 MEMADDA10

MEMADDA9 MEMADDA8 MEMADDA7 MEMADDA6 MEMADDA5 MEMADDA4 MEMADDA3 MEMADDA2 MEMADDA1 MEMADDA0

MEMRASB_L MEMCASB_L

MEMWEB_L

MEMBANKB1 MEMBANKB0

MEMADDB13 MEMADDB12 MEMADDB11 MEMADDB10

MEMADDB9 MEMADDB8 MEMADDB7 MEMADDB6 MEMADDB5 MEMADDB4 MEMADDB3 MEMADDB2 MEMADDB1 MEMADDB0

MEMCHECK7 MEMCHECK6 MEMCHECK5 MEMCHECK4 MEMCHECK3 MEMCHECK2 MEMCHECK1 MEMCHECK0

C

VTT_A VTT_A VTT_A VTT_A VTT_B VTT_B VTT_B VTT_B

MEMCKEA MEMCKEB

NC_E13 NC_C12

NC_E14 NC_D12

D17 A18 B17 C17 AF16 AG16 AH16 AJ17

AG10 AE8

AE7 D10

C10 E12 E11 AF8 AG8 AF10 AE10 V3 V4 K5 K4 R5 P5 P3 P4

D8 C8 E8 E7 D6 E6 C4 E5

H5 D4 G5

K3 H3

E13 C12 E10 AE6 AF3 M5 AE5 AB5 AD3 Y5 AB4 Y3 V5 T5 T3 N5

H4 F5 F4

L5 J5

E14 D12 E9 AF6 AF4 M4 AD5 AC5 AD4 AA5 AB3 Y4 W5 U5 T4 M3

N3 N1 U3 V1 N2 P1 U1 U2

1D25V_S3

MEMRESET# M_CKE#0

M_CKE#1 M_CLK7

M_CLK#7 M_CLK6 M_CLK#6 M_CLK5 M_CLK#5 M_CLK4 M_CLK#4

M_CLK1 M_CLK#1 M_CLK0 M_CLK#0

M_CS#7 M_CS#6 M_CS#5 M_CS#4 M_CS#3 M_CS#2 M_CS#1 M_CS#0

M_ARAS# M_ACAS# M_AWE#

M_ABS#1 M_ABS#0

RSVD_M_AA15 RSVD_M_AA14 M_AA13 M_AA12 M_AA11 M_AA10 M_AA9 M_AA8 M_AA7 M_AA6 M_AA5 M_AA4 M_AA3 M_AA2 M_AA1 M_AA0

M_BRAS# M_BCAS# M_BWE#

M_BBS#1 M_BBS#0

RSVD_M_BA15 RSVD_M_BA14 M_BA13 M_BA12 M_BA11 M_BA10 M_BA9 M_BA8 M_BA7 M_BA6 M_BA5 M_BA4 M_BA3 M_BA2 M_BA1 M_BA0

CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0

12

For REGISTED DIMM Only UNBUFFER DIMM NC

12

C309

M_CKE#0 8,9 M_CKE#1 8,9

M_CLK7 8 M_CLK#7 8 M_CLK6 8 M_CLK#6 8 M_CLK5 8 M_CLK#5 8 M_CLK4 8 M_CLK#4 8

M_CS#3 8,9 M_CS#2 8,9 M_CS#1 8,9 M_CS#0 8,9

M_ARAS# 8,9 M_ACAS# 8,9 M_AWE# 8,9

M_ABS#1 8,9 M_ABS#0 8,9

M_BRAS# 8,9 M_BCAS# 8,9 M_BWE# 8,9

M_BBS#1 8,9 M_BBS#0 8,9

TP58

TPAD30

TP117

TPAD30

TP57

TPAD30

TP110

TPAD30

TP116

TPAD30

TP115

TPAD30

TP111

TPAD30

TP112

TPAD30

C309 SC1000P50V2JN-N1

SC1000P50V2JN-N1

M_CLK#1 M_CLK#0 M_CLK1 M_CLK0

M_AA[13..0] 8,9

M_BA[13..0] 8,9

Title

Size Document Number Rev

A3

Date: Sheet

C320

C320 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

AMD suggested M_AA13 connect to DIMM pin123

AMD suggested M_BA13 connect to DIMM pin123

D

2D5V_S3

RN29

1

8

2

7

3

6

45

SRN10KJ-6-GP

M_DQS8 M_ADM8

MEMRESET# M_CS#7 M_CS#6 M_CS#5 M_CS#4 RSVD_M_AA15 RSVD_M_AA14 RSVD_M_BA15 RSVD_M_BA14

TP113TPAD30TP113TPAD30 TP114TPAD30TP114TPAD30

TP50 TPAD30TP50 TPAD30 TP53 TPAD30TP53 TPAD30 TP56 TPAD30TP56 TPAD30 TP54 TPAD30TP54 TPAD30 TP55 TPAD30TP55 TPAD30 TP46 TPAD30TP46 TPAD30 TP48 TPAD30TP48 TPAD30 TP41 TPAD30TP41 TPAD30 TP47 TPAD30TP47 TPAD30

NOT SUPPORT ECC CHECK AMD suggested remove PULL-HI resistor.

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU(2/4)_DDR

Bolsena-E

558Thursday, October 13, 2005

E

SA

of

SA

A

2D5V_VDDA_S0

2D5V_S0

4 4

2D5V_CPUA_S0

R139

1 2

0R0603-PAD

12

C262

C262 SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

1 2

DY

R136

0R3J-3-GP

2D5V_CPUR_S0

1 2

0R0805-PAD

12

TC8

ST100U4VBM-U

AMD SUGGEST TO USE 2D5V_CPUA_S0

KEMET,NT:5.7, B2 size ST100U4VBM-1 (80.10716.321)

3 3

2D5V_S0

2 2

DY

DBREQJ DBRDY TCK TMS TDI TRST_L TDO

2D5V_S3

CHANGE FROM 1KR3 TO 680R2 FOR AMD CHECK LIST

NC_AG17 NC_AJ18 NC_D18

NC_B19

1 1

NC_C19 NC_D20 NC_C21

Iripple=1.1A,ESR=70mohm

SANYO, NT$:6.1 Iripple=1.1A,ESR=70mohm

3.5/2.8/2.0

77.21071.031

678

RN21

12

C234

C234 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

R164

1 2

1 2 3 4 5

RN21

123

4 5

680R3F-GP

DY

RN23 SRN680J-GPRN23 SRN680J-GP

8 7 6

RN25

SRN680J-GP

A

DY

SRN680J-GP

AMD SUGGEST TO USE 100 ~ 300UH

LAYOUT: Route trace 50 mils wide and 500 to 750 mils long between these caps.

12

C286

C286 SC4D7U10V5ZY-3GP

SC4D7U10V5ZY-3GP

1D2V_HT0B_S0

12

R120

R119

680R3F-GP

DY

R143

2D5V_VDDA_S0

12

R133 44D2R2F-L1-GPR133 44D2R2F-L1-GP

1 2

R134 44D2R2F-L1-GPR134 44D2R2F-L1-GP

1 2

AMD suggest voltege from 2D5V_S0 to 2D5V_S3

differentially impedance 100

B

3D3V_S0

12

C242

C242 SC1U10V3KX-3GP

SC1U10V3KX-3GP

DY

2D5V_S0

DY

LDT_RST#17 SB_CPUPWRGD17 LDT_STP#13,17

1 2

1D25V_S3

2D5V_S0

SRN680J-GP

LDT_RST# SB_CPUPWRGD LDT_STP#

12

C288

C288 SC3300P50V2KX-1GP

SC3300P50V2KX-1GP

12

C256

C256 SC1000P50V2JN-N1

SC1000P50V2JN-N1

2D5V_S3

R518 820R3-GPR518 820R3-GP

1 2

R514 820R3-GPR514 820R3-GP

1 2

R154 680R3F-GPR154 680R3F-GP

1 2

R158 680R3F-GPR158 680R3F-GP

1 2

R512 680R3F-GPR512 680R3F-GP

1 2

LAYOUT: Route VDDA trace approx. 50 mils wide (use 2x25 mil traces to exit ball field) and 500 mils long.

12

C287

C287 SCD22U16V3ZY-GP

SCD22U16V3ZY-GP

12

C257

C257 SC1000P50V2JN-N1

SC1000P50V2JN-N1

CPUCLK3

CPUCLK#3

Validation Test Points

NC_C15 NC_AE23 NC_AF23 NC_AF22 NC_AF21

B

LAYOUT: Place close to the CPU.

TP42

TPAD30

TP33

TPAD30

TP31

TPAD30

TP32

TPAD30

TP38

TPAD30

LDT_RST# CLKIN CLKIN# CORE_SENSE VDDIOFB VDDIOFBJ VDDIOSENSE NC_AE24 NC_AF24

C

Iomax=120mA

U57

1

SHDN#

2

GND

3

IN

G913CF-GP

DY

COREFB41

COREFB#41

C803

C803 SC3900P50V3KX-GP

SC3900P50V3KX-GP

C796

C796 SC3900P50V3KX-GP

SC3900P50V3KX-GP

R159

1 2

R156

1 2

RN22

123

C

L0_REF1 L0_REF0

COREFB COREFB# CORE_SENSE

VDDIOFB VDDIOFBJ VDDIOSENSE

CLKIN

12

R519

R519 169R2F-GP

169R2F-GP

CLKIN# NC_AJ23 NC_AH23 NC_AE24 NC_AF24

DBRDY NC_C15 TMS

TCK TRST_L TDI

680R3F-GP

680R3F-GP 680R3F-GP

680R3F-GP

NC_AE23 NC_AF23 NC_AF22 NC_AF21

678

4 5

TP37

TP37 TP35

TP35 TP36

TP36 TP34

TP34 TP45

TP45 TP43

TP43 TP51

TP51 TP30

TP30 TP29

TP29

SET

OUT

DY

TPAD30

TPAD30 TPAD30

TPAD30

2D5V_CPUA_S0

2D5V_VDDA_VREF

5 4

DY

NC_C18 NC_A19

12

DY

12

C768

C768 SC1U10V3KX-3GP

SC1U10V3KX-3GP

U62CU62C

AH25

VDDA1

AJ25

VDDA2

AF20

RESET_L

AE18

PWROK

AJ27

LDTSTOP_L

AF27

L0_REF1

AE26

L0_REF0

A23

COREFB_H

A24

COREFB_L

B23

CORE_SENSE

AE12

VDDIOFB_H

AF12

VDDIOFB_L

AE11

VDDIO_SENSE

AJ21

CLKIN_H

AH21

CLKIN_L

AJ23

NC_AJ23

AH23

NC_AH23

AE24

NC_AE24

AF24

NC_AF24

C16

VTT_A

AG15

VTT_B

AH17

DBRDY

C15

NC_C15

E20

TMS

E17

TCK

B21

TRST_L

A21

TDI

C18

NC_C18

A19

NC_A19

A28

KEY1

AJ28

KEY0

AE23

NC_AE23

AF23

NC_AF23

AF22

NC_AF22

AF21

NC_AF21

C1

NC_C1

J3

NC_J3

R3

NC_R3

AA2

NC_AA2

D3

NC_D3

AG2

NC_AG2

B18

NC_B18

AH1

NC_AH1

AE21

NC_AE21

C20

NC_C20

AG4

NC_AG4

C6

NC_C6

AG6

NC_AG6

AE9

NC_AE9

AG9

NC_AG9

12

R509

R509 20KR2F-L-GP

20KR2F-L-GP

C767

C767 SC22P50V2JN-4GP

SC22P50V2JN-4GP

12

R129

R129 20KR2F-L-GP

20KR2F-L-GP

DY

D

R1

Vout = 1.25*(1+ R1/R2)

R2

THERMTRIP#

THERMDA THERMDC

VID4 VID3 VID2 VID1 VID0

NC_AG18 NC_AH18 NC_AG17

NC_AJ18

DBREQ_L

NC_D20 NC_C21 NC_D18 NC_C19 NC_B19

TDO

NC_AF18

A20 A26

A27 AG13

AF14 AG14 AF15 AE15

AG18 AH18 AG17 AJ18

AH19 AJ19

AE19 D20

C21 D18 C19 B19

A22

AF18

VID4 VID3 VID2 VID1 VID0

NC_AG18 NC_AH18 NC_AG17 NC_AJ18

NC_D20 NC_C21 NC_D18 NC_C19 NC_B19

TDO

THERMTRIP_L

FBCLKOUT_H

FBCLKOUT_L

Connect to VDDIO for AMD suggest.

D22

NC_D22

C22

NC_C22

B13

NC_B13

B7

NC_B7

C3

NC_C3

K1

NC_K1

R2

NC_R2

AA3

NC_AA3

F3

NC_F3

C23

NC_C23

AG7

NC_AG7

AE22

NC_AE22

C24

NC_C24

A25

NC_A25

C9

NC_C9

D

E

THERMDP 22 THERMDN 22

VID[4..0] 41

TP40 TPAD30TP40 TPAD30 TP39 TPAD30TP39 TPAD30

LAYOUT: Route FBCLKOUT_H/L

FBCLKOUT

FBCLKOUTJ

DBREQJ

differentially impedance 80

12

R520

R520 80D6R2F-L-GP

80D6R2F-L-GP

R155

1 2

DUMMY-R3

2D5V_S3

THERMTRIP#Level shift to SB400

2D5V_S0

12

R152

R152 680R3F-GP

680R3F-GP

Q7

THERMTRIP#

MMBT3904-2-GP

Title

Size Document Number Rev

A3

Date: Sheet

Q7

C

E

B

NS3

R157

1 2

1KR2J-1-GP

12

CPU(3/4)_Control & Debug

Bolsena-E

1KR2J-1-GP

C304

C304 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

E

CPU_THERMTRIP# 22

SB_CPUPWRGD 17

658Thursday, October 13, 2005

of

SA

U62EU62E

Y17

VSS

K17

VSS

H17

VSS

F17

VSS

E18

VSS

AJ26

VSS

AE29

VSS

AC16

VSS

AA16

VSS

J16

VSS

G16

VSS

E16

VSS

AH14

4 4

3 3

2 2

1 1

AD15 AB15

K15 E15

D16 AE14 AC14 AA14

G14

AF17 AD13 AB13

Y13 K13 H13

F13 AH12 AC12 AA12

G12

B12 AD11 AB11

Y11

K11

H11

F11 AH10 AC10

W10

U10

R10

N10

G10

B10

AD9

AH8 AC8

AD7

AB7

AH6 AC6

AA6

AH4 AH2

AD2

AB2

C29 AH28

AF28

AC28

W28

R28

VSS VSS VSS VSS VSS VSS VSS VSS VSS

J14

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

L10

VSS

J10

VSS VSS VSS VSS

Y9

VSS

V9

VSS

T9

VSS

P9

VSS

M9

VSS

K9

VSS

H9

VSS

F9

VSS VSS VSS

W8

VSS

U8

VSS

R8

VSS

N8

VSS

L8

VSS

J8

VSS

G8

VSS

B8

VSS VSS VSS

V7

VSS

T7

VSS

P7

VSS

M7

VSS

K7

VSS

H7

VSS

F7

VSS VSS VSS VSS

U6

VSS

R6

VSS

N6

VSS

L6

VSS

J6

VSS

G6

VSS

B6

VSS VSS

B4

VSS VSS VSS VSS

Y2

VSS

V2

VSS

T2

VSS

P2

VSS

M2

VSS

K2

VSS

H2

VSS

F2

VSS VSS VSS VSS VSS VSS VSS

L28

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

A

VCC_CORE_S0 2D5V_S3

N20 L20 J20 AF19 AD19 AB19 Y19 K19 H19 F19 D19 AC18 AA18 G18 B16 AD17 AB17 H15 F15 G28 D28 B28 C27 AH26 AF26 AD26 Y26 T26 M26 H26 D26 B26 C25 B25 AJ24 AG24 AC24 AA24 W24 U24 R24 N24 J24 G24 E24 AG23 AD23 AB23 Y23 V23 T23 P23 K23 H23 F23 D23 AJ22 AH22 AG22 AC22 AA22 AG29 U22 R22 N22 L22 J22 G22 E22 B22 AG21 AD21 Y21 V21 T21 P21 M21 K21 H21 F21 D21 AJ20 AG20 AE20 AC20 AA20 W20 U20 R20 G20 J18 AE16 Y15 B14 J12 AA10 AB9 AA8 Y7 W6 AF2 D2 AG27 AG25 L24 M23 W22 AB21 AH20 B2

A

AC15

H18 B20 E21 H22

H24 F26

V10 G13 K14 Y14

AB14

G15

AA15

H16 K16 Y16

AB16

G17

AA17 AC17 AE17

F18 K18

Y18 AB18 AD18 AG19

E19

G19 AC19 AA19

F20

H20

K20

M20

P20

T20

V20

Y20 AB20 AD20

G21

N21

R21

U21

W21 AA21 AC21

F22 K22

M22

P22 T22 V22

Y22 AB22 AD22

E23

G23

N23

R23

U23

W23 AA23 AC23

B24 D24 F24 K24

M24

P24 T24 V24

Y24 AB24 AD24 AH24 AE25

K26

P26

V26

U62DU62D

L7

VDD VDD VDD VDD VDD VDD

J23

VDD VDD VDD

N7

VDD

L9

VDD VDD VDD VDD VDD VDD VDD

J15

VDD VDD VDD VDD VDD VDD VDD

J17

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

J19

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

J21

VDD

L21

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

L23

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

E4 G4 J4 L4 N4 U4 W4 AA4 AC4 AE4 D5 AF5 F6 H6 K6 M6 P6 T6 V6 Y6 AB6 AD6 D7 G7 J7 AA7 AC7 AF7 F8 H8 AB8 AD8 D9 G9 AC9 AF9 F10 AD10 D11 AF11 F12 AD12 D13 AF13 F14 AD14 F16 AD16 D15 R4

N28 U28 AA28 AE27 R7 U7 W7 K8 M8 P8 T8 V8 Y8 J9 N9 R9 U9 W9 AA9 H10 K10 M10 P10 T10 Y10 AB10 G11 J11 AA11 AC11 H12 K12 Y12 AB12 J13 AA13 AC13 H14 AB26 E28 J28

B

VCC_CORE_S0

B

VCC_CORE_S0

12

VCC_CORE_S0

C820

1 2

0.22u x 4

DY

2D5V_S3

12

C321

1D25V_S3

12

C325

0.22u x 2

C

LAYOUT: Place in uPGA socket cavity.

0.22u x 6

12

C295

C294

LAYOUT: Place on backside of processor.

SCD22U16V3ZY-GP

C814

C818

1 2

SCD22U16V3ZY-GP

DY

12

SCD22U16V3ZY-GP

DY

12

C367

C368

SCD22U16V3ZY-GP

1D25V_S3

12

C326

SCD22U16V3ZY-GP

C813

SCD22U16V3ZY-GP

C819

1 2

DY

SCD22U16V3ZY-GP

12

C324

SCD22U16V3ZY-GP

12

C310

4.7u x 2

SC4D7U10V5ZY-3GP

C

12

C360

SCD22U16V3ZY-GP

12

C827

10u x 2

SC10U10V5ZY-1GP

12

C363

SCD22U16V3ZY-GP

12

C319

SC4D7U10V5ZY-3GP

12

C362

SCD22U16V3ZY-GP

C808

SC10U10V5ZY-1GP

C369

SCD22U16V3ZY-GP

C821

2D5V_S3

10u x 1 4.7u x 6

10u x 4

12

C339

SC10U10V5ZY-1GP

SCD22U16V3ZY-GP

12

C351

SC10U10V5ZY-1GP

12

C323

SC10U10V5ZY-1GP

12

C350

C359

SC4D7U10V5ZY-3GP

D

12

C809

C828

SC10U10V5ZY-1GP

12

C395

SC4D7U10V5ZY-3GP

D

12

C398

C361

SC4D7U10V5ZY-3GP

E

12

C396

SC4D7U10V5ZY-3GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

CPU(4/4)_Power

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

758Thursday, October 13, 2005

of

E

of

SA

A

M_AA0 M_AA1 M_AA2 M_AA3 M_AA4 M_AA5 M_AA6 M_AA7 M_AA8 M_AA9 M_AA10 M_AA11

12

C492

C492 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

A

M_AA12 M_ABS#0

M_ABS#1 M_DATA_R_0

M_DATA_R_1 M_DATA_R_2 M_DATA_R_3 M_DATA_R_4 M_DATA_R_5 M_DATA_R_6 M_DATA_R_7 M_DATA_R_8 M_DATA_R_9 M_DATA_R_10 M_DATA_R_11 M_DATA_R_12 M_DATA_R_13 M_DATA_R_14 M_DATA_R_15 M_DATA_R_16 M_DATA_R_17 M_DATA_R_18 M_DATA_R_19 M_DATA_R_20 M_DATA_R_21 M_DATA_R_22 M_DATA_R_23 M_DATA_R_24 M_DATA_R_25 M_DATA_R_26 M_DATA_R_27 M_DATA_R_28 M_DATA_R_29 M_DATA_R_30 M_DATA_R_31 M_DATA_R_32 M_DATA_R_33 M_DATA_R_34 M_DATA_R_35 M_DATA_R_36 M_DATA_R_37 M_DATA_R_38 M_DATA_R_39 M_DATA_R_40 M_DATA_R_41 M_DATA_R_42 M_DATA_R_43 M_DATA_R_44 M_DATA_R_45 M_DATA_R_46 M_DATA_R_47 M_DATA_R_48 M_DATA_R_49 M_DATA_R_50 M_DATA_R_51 M_DATA_R_52 M_DATA_R_53 M_DATA_R_54 M_DATA_R_55 M_DATA_R_56 M_DATA_R_57 M_DATA_R_58 M_DATA_R_59 M_DATA_R_60 M_DATA_R_61 M_DATA_R_62 M_DATA_R_63

12

3D3V_S0

TP59 TPAD30TP59 TPAD30

4 4

3 3

2 2

1 1

M_ARAS#5,9 M_ACAS#5,9 M_AWE#5,9

VREF_DDR_MEM VREF_DDR_MEM

Layout trace 20 mil Layout trace 20 mil

C493

SCD1U25V3ZY-3GP

DDR1

112

A0

111

A1

110

A2

109

A3

108

A4

107

A5

106

A6

105

A7

102

A8

101

A9

115

A10 / AP

100

A11

99

A12

117

BA0

116

BA1

5

DQ0

7

DQ1

13

DQ2

17

DQ3

6

DQ4

8

DQ5

14

DQ6

18

DQ7

19

DQ8

23

DQ9

29

DQ10

31

DQ11

20

DQ12

24

DQ13

30

DQ14

32

DQ15

41

DQ16

43

DQ17

49

DQ18

53

DQ19

42

DQ20

44

DQ21

50

DQ22

54

DQ23

55

DQ24

59

DQ25

65

DQ26

67

DQ27

56

DQ28

60

DQ29

66

DQ30

68

DQ31

127

DQ32

129

DQ33

135

DQ34

139

DQ35

128

DQ36

130

DQ37

136

DQ38

140

DQ39

141

DQ40

145

DQ41

151

DQ42

153

DQ43

142

DQ44

146

DQ45

152

DQ46

154

DQ47

163

DQ48

165

DQ49

171

DQ50

175

DQ51

164

DQ52

166

DQ53

172

DQ54

176

DQ55

177

DQ56

181

DQ57

187

DQ58

189

DQ59

178

DQ60

182

DQ61

188

DQ62

190

DQ63

71

CB0

73

CB1

79

CB2

83

CB3

72

CB4

74

CB5

80

CB6

84

CB7

85

NC#85

86

NC#86/(RESET#)

97

NC#97/A13

98

NC#98/BA2

123

NC#123

124

NC#124

200

NC#200

118

/RAS

120

/CAS

119

/WE

1

VREF

2

VREF

197

VDDSPD

199

VDDID

201

GND

/CS0 /CS1

CKE0 CKE1

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8

CK0

/CK0

CK1

/CK1

CK2

/CK2

SCL SDA

SA0 SA1 SA2

VDD VDD VDD VDD VDD VDD VDD

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS

VSS GND

B

121 122

M_CKE#0

96 95

M_DQS_R0

11

M_DQS_R1

25

M_DQS_R2

47

M_DQS_R3

61

M_DQS_R4

133

M_DQS_R5

147

M_DQS_R6

169

M_DQS_R7

183 77

M_ADM_R0

12

M_ADM_R1

26

M_ADM_R2

48

M_ADM_R3

62 134

M_ADM_R5

148

M_ADM_R6

170

M_ADM_R7

184 78

35 37 160 158

DDR_CLK0

89

DDR_CLK#0

91

SMBC_SB

195

SMBD_SB

193 194

196 198

9 10 21 22 33 34 36 45 46 57 58 69 70 81 82 92 93 94 113 114 131 132 143 144 155 156 157 167 168 179 180 191 192

3 4 15 16 27 28 38 39 40 51 52 63 64 75 76 87 88 90 103 104 125 126 137 138 149 150

ME : 62.10017.701

159

2nd :62.10017.691

161 162 173 174 185 186

202

B

M_CS#0 5,9 M_CS#1 5,9

M_CKE#0 5,9 M_CKE#1 5,9

M_ADM#0 M_ADM#1 M_ADM#2 M_ADM#3 M_ADM#4 M_ADM#5 M_ADM#6 M_ADM#7

M_CLK5 5 M_CLK#5 5 M_CLK7 5 M_CLK#7 5

2D5V_S3

NOT SUPPORT ECC CHECK AMD suggested pull-low

1ST 62.10017.701 - 2ND 62.10017.201

Part Number = 62.10017.701

SKT-SODIMM200-24GP

C515

SCD1U25V3ZY-3GP

C515

M_BRAS#5,9 M_BCAS#5,9 M_BWE#5,9

12

C516

SCD1U25V3ZY-3GP

M_BA0 M_BA1 M_BA2 M_BA3 M_BA4 M_BA5 M_BA6 M_BA7 M_BA8 M_BA9 M_BA10 M_BA11 M_BA12

M_BBS#0 M_BBS#1

M_DATA_R_0 M_DATA_R_1 M_DATA_R_2 M_DATA_R_3 M_DATA_R_4 M_DATA_R_5 M_DATA_R_6 M_DATA_R_7 M_DATA_R_8 M_DATA_R_9 M_DATA_R_10 M_DATA_R_11 M_DATA_R_12 M_DATA_R_13 M_DATA_R_14 M_DATA_R_15 M_DATA_R_16 M_DATA_R_17 M_DATA_R_18 M_DATA_R_19 M_DATA_R_20 M_DATA_R_21 M_DATA_R_22 M_DATA_R_23 M_DATA_R_24 M_DATA_R_25 M_DATA_R_26 M_DATA_R_27 M_DATA_R_28 M_DATA_R_29 M_DATA_R_30 M_DATA_R_31 M_DATA_R_32 M_DATA_R_33 M_DATA_R_34 M_DATA_R_35 M_DATA_R_36 M_DATA_R_37 M_DATA_R_38 M_DATA_R_39 M_DATA_R_40 M_DATA_R_41 M_DATA_R_42 M_DATA_R_43 M_DATA_R_44 M_DATA_R_45 M_DATA_R_46 M_DATA_R_47 M_DATA_R_48 M_DATA_R_49 M_DATA_R_50 M_DATA_R_51 M_DATA_R_52 M_DATA_R_53 M_DATA_R_54 M_DATA_R_55 M_DATA_R_56 M_DATA_R_57 M_DATA_R_58 M_DATA_R_59 M_DATA_R_60 M_DATA_R_61 M_DATA_R_62 M_DATA_R_63

M_BA13M_AA13

12

3D3V_S0

TP60 TPAD30TP60 TPAD30

C

DDR2

112

A0

111

A1

110

A2

109

A3

108

A4

107

A5

106

A6

105

A7

102

A8

101

A9

115

A10 / AP

100

A11

99

A12

117

BA0

116

BA1

5

DQ0

7

DQ1

13

DQ2

17

DQ3

6

DQ4

8

DQ5

14

DQ6

18

DQ7

19

DQ8

23

DQ9

29

DQ10

31

DQ11

20

DQ12

24

DQ13

30

DQ14

32

DQ15

41

DQ16

43

DQ17

49

DQ18

53

DQ19

42

DQ20

44

DQ21

50

DQ22

54

DQ23

55

DQ24

59

DQ25

65

DQ26

67

DQ27

56

DQ28

60

DQ29

66

DQ30

68

DQ31

127

DQ32

129

DQ33

135

DQ34

139

DQ35

128

DQ36

130

DQ37

136

DQ38

140

DQ39

141

DQ40

145

DQ41

151

DQ42

153

DQ43

142

DQ44

146

DQ45

152

DQ46

154

DQ47

163

DQ48

165

DQ49

171

DQ50

175

DQ51

164

DQ52

166

DQ53

172

DQ54

176

DQ55

177

DQ56

181

DQ57

187

DQ58

189

DQ59

178

DQ60

182

DQ61

188

DQ62

190

DQ63

71

CB0

73

CB1

79

CB2

83

CB3

72

CB4

74

CB5

80

CB6

84

CB7

85

NC#85

86

NC#86/(RESET#)

97

NC#97/A13

98

NC#98/BA2

123

NC#123

124

NC#124

200

NC#200

118

/RAS

120

/CAS

119

/WE

1

VREF

2

VREF

197

VDDSPD

199

VDDID

201

GND

SKT-SODIMM2006U1GP

C

/CS0 /CS1

CKE0 CKE1

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8

CK0

/CK0

CK1

/CK1

CK2

/CK2

SCL SDA

SA0 SA1 SA2

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

GND

D

121 122

96 95

M_DQS_R0

11

M_DQS_R1

25

M_DQS_R2

47

M_DQS_R3

61

M_DQS_R4

133

M_DQS_R5

147

M_DQS_R6

169

M_DQS_R7

183 77

M_ADM_R0

12

M_ADM_R1

26

M_ADM_R2

48

M_ADM_R3

62

M_ADM_R4M_ADM_R4

134

M_ADM_R5

148

M_ADM_R6

170

M_ADM_R7

184 78

35 37 160 158

DDR_CLK1

89

DDR_CLK#1

91 195

193 194

196 198

9 10 21 22 33 34 36 45 46 57 58 69 70 81 82 92 93 94 113 114 131 132 143 144 155 156 157 167 168 179 180 191 192

3 4 15 16 27 28 38 39 40 51 52 63 64 75 76 87 88 90 103 104 125 126 137 138 149 150 159 161 162 173 174 185 186

202

ME : 62.10017.391

M_CS#2 5,9 M_CS#3 5,9

! NOT THIS LIBRARY

M_ADM#0 M_ADM#1 M_ADM#2 M_ADM#3 M_ADM#4 M_ADM#5 M_ADM#6 M_ADM#7

M_CLK4 5 M_CLK#4 5 M_CLK6 5 M_CLK#6 5

SMBC_SB 3,20 SMBD_SB 3,20

DM_SA0

2D5V_S3

62.10017.391

R255

1 2

4K7R2J-2-GP

3D3V_S0

DDR1(Reverse 5.2mm)

DDR2(Reverse 9.2mm)

Title

Size Document Number Rev

A3

Date: Sheet

D

Date: Sheet

M_ADM_R[7..0] 9 M_DATA_R_[63..0] 9 M_DQS_R[7..0] 9

M_AA[13..0] 5,9 M_ABS#[1..0] 5,9 M_BA[13..0] 5,9 M_BBS#[1..0] 5,9

RN62

DDR_CLK#1 DDR_CLK#0 DDR_CLK1 DDR_CLK0

RN62

8 7 6

SRN10KJ-6-GP

AMD CPU

MD63

SMA11

Pin 199

Pin 200 Pin 2

Pin 199 Pin 1

Pin 200 Pin 2

(Bottom view)

DDR SO-DIMM SKT

Bolsena-E

E

2D5V_S3

1 2 3 45

SMA10 SMA0

SMA14

SMA12

MD0

Pin 1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

858Thursday, October 13, 2005

of

E

of

SA

A

SERIES DAMPING PARALLEL TERMINATION

PLACE RNs CLOSE TO FIRST DIMM, < 0.75" STRICT EQUAL LENGTH LIMITATION WITH DQS, CB PINS

SRN10J-3

M_DATA4 M_ADM0

M_DATA6 M_DATA7 M_DATA13 M_DATA12

4 4

M_ADM1

M_DATA1 M_DATA0 M_DQS0 M_DATA2 M_DATA3 M_DATA8 M_DATA9 M_DQS1

M_DATA14 M_DATA_R_14 M_DATA15 M_DATA21 M_DATA20 M_ADM2 M_DATA23 M_DATA_R_23 M_DATA22 M_DATA28 M_DATA_R_28

3 3

M_DATA11 M_DATA10 M_DATA17 M_DATA16 M_DQS2 M_DQS_R2 M_DATA19 M_DATA_R_19 M_DATA18

M_DATA31 M_DATA_R_31

M_DATA24 M_DATA_R_24 M_DATA_R_27 M_DQS3 M_DQS_R3 M_DATA26 M_DATA_R_26 M_DATA27 M_DATA_R_27

2 2

SRN10J-3

8 9 7 6 5 4 3 2 1

RN40

RN40 SRN10J-3

SRN10J-3

8 9 7 6 5 4 3 2 1

RN31

RN31 SRN10J-3

SRN10J-3

8 9 7 6 5 4 3 2 1

RN41

RN41 SRN10J-3

SRN10J-3

8 9 7 6 5 4 3 2 1

RN32

RN42

4 5 3 2 1

RN33

SRN10J-5-GP

10 11 12 13 14 15 16

SRN10J-5-GP

M_DATA_R_29M_DATA29 M_ADM_R3M_ADM3

6 7

M_DATA_R_30M_DATA30

8

6 7 8

M_DATA_R_4 M_DATA_R_5M_DATA5 M_ADM_R0 M_DATA_R_6 M_DATA_R_7 M_DATA_R_13 M_DATA_R_12 M_ADM_R1

M_DATA_R_1 M_DATA_R_0 M_DQS_R0 M_DATA_R_2 M_DATA_R_3 M_DATA_R_8 M_DATA_R_9 M_DQS_R1

M_DATA_R_15 M_DATA_R_21 M_DATA_R_20 M_ADM_R2

M_DATA_R_22

M_DATA_R_11 M_DATA_R_10 M_DATA_R_17 M_DATA_R_16

M_DATA_R_18 M_DATA_R_25M_DATA25

M_ADM4 M_ADM_R4 M_DATA39 M_DATA_R_39

M_DATA33 M_DATA_R_33 M_DATA34 M_DATA_R_34

M_DATA35 M_DATA41 M_DATA40 M_DQS5 M_DATA42 M_DATA43 M_DATA49 M_DATA48

M_DATA38 M_DATA45 M_DATA44 M_ADM5 M_DATA47 M_DATA46 M_DATA53 M_DATA52

M_DQS6 M_DATA50 M_DATA51 M_DATA56 M_DATA57 M_DQS7 M_DATA58 M_DATA59

M_ADM6 M_DATA54 M_DATA55 M_DATA61 M_DATA60 M_ADM7 M_DATA62 M_DATA63

4 5 3 2 1

RN34

8 9 7 6 5 4 3 2 1

SRN10J-5-GP

RN43

6 7 8

SRN10J-5-GP

SRN10J-5-GP SRN10J-3

SRN10J-3

10 11 12 13 14 15 16

RN35

RN35 SRN10J-3

SRN10J-3

10 11 12 13 14 15 16

RN44

RN44 SRN10J-3

SRN10J-3

10 11 12 13 14 15 16

RN36

RN36 SRN10J-3

SRN10J-3

10 11 12 13 14 15 16

RN45

B

M_DATA_R_37M_DATA37 M_DATA_R_36M_DATA36

M_DATA_R_32M_DATA32 M_DQS_R4M_DQS4

M_DATA_R_35 M_DATA_R_41 M_DATA_R_40 M_DQS_R5 M_DATA_R_42 M_DATA_R_43 M_DATA_R_49 M_DATA_R_48

M_DATA_R_38

M_DATA_R_45

M_DATA_R_44 M_ADM_R5 M_DATA_R_47 M_DATA_R_46 M_DATA_R_53 M_DATA_R_52

M_DQS_R6 M_DATA_R_50 M_DATA_R_51 M_DATA_R_56 M_DATA_R_57 M_DQS_R7 M_DATA_R_58 M_DATA_R_59

M_ADM_R6 M_DATA_R_54 M_DATA_R_55 M_DATA_R_61 M_DATA_R_60 M_ADM_R7 M_DATA_R_62 M_DATA_R_63

C

PULL HIGH STUBS < 0.8", PLACE RPs CLOSE TO SECOND DM ( DM2 )

SRN68J-4-GP

M_ADM_R1 M_DATA_R_13 M_DATA_R_12 M_DATA_R_7 M_DATA_R_6 M_ADM_R0 M_DATA_R_5 M_DATA_R_4

M_DATA_R_1 M_DATA_R_0 M_DQS_R0 M_DATA_R_2 M_DATA_R_3 M_DATA_R_8 M_DATA_R_9 M_DQS_R1

M_DATA_R_28 M_DATA_R_23 M_DATA_R_22 M_ADM_R2 M_ADM_R5 M_DATA_R_21 M_DATA_R_20 M_DATA_R_15 M_DATA_R_14

M_DATA_R_11 M_DATA_R_10 M_DATA_R_16 M_DATA_R_17 M_DQS_R2 M_DATA_R_19 M_DATA_R_18 M_DATA_R_24

M_DATA_R_26 M_DQS_R3 M_DATA_R_25

M_DATA_R_31 M_DATA_R_30 M_ADM_R3 M_DATA_R_29

SRN68J-4-GP

8 9 7 6 5 4 3 2 1

RN113

SRN68J-4-GP

8 9 7 6 5 4 3 2 1

RN59

RN59 SRN68J-4-GP

SRN68J-4-GP

8 9 7 6 5 4 3 2 1

RN114

RN114 SRN68J-4-GP

SRN68J-4-GP

8 9 7 6 5 4 3 2 1

RN60

RN60 RN61

RN61

1 2 3 4 5

4 5 3 2 1

RN115

1D25V_S3 1D25V_S3

4 5 10 11 12 13 14 15 16

10 11 12 13 14 15 16

SRN68J-3-GP

8 7 6

6 7 8

SRN68J-3-GP

3

2

1

RN56

4 5

3

2

1

RN110

SRN68J-4-GP

8 9 7 6 5 4 3 2 1

RN66

RN66 SRN68J-4-GP

SRN68J-4-GP

8 9 7 6 5 4 3 2 1

RN111

RN111 SRN68J-4-GP

SRN68J-4-GP

8 9 7 6 5 4 3 2 1

RN67

RN67 SRN68J-4-GP

SRN68J-4-GP

8 9 7 6 5 4 3 2 1

RN112

NO EQUAL LENGTH LIMITATION

M_DATA_R_32 M_DATA_R_33

6

M_DQS_R4

7

M_DATA_R_35

8

SRN68J-3-GP

M_DATA_R_36 M_DATA_R_37

6

M_ADM_R4

7

M_DATA_R_38

8

SRN68J-3-GP

M_DATA_R_48 M_DATA_R_49

10

M_DATA_R_43

11

M_DATA_R_42

12

M_DQS_R5

13

M_DATA_R_41

14

M_DATA_R_40

15

M_DATA_R_34

16

M_DATA_R_39 M_DATA_R_44

10

M_DATA_R_45

11 12

M_DATA_R_46

13

M_DATA_R_47

14

M_DATA_R_52

15

M_DATA_R_53

16

M_DATA_R_59 M_DATA_R_58

10

M_DQS_R7

11

M_DATA_R_57

12

M_DATA_R_56

13

M_DATA_R_51

14

M_DATA_R_50

15

M_DQS_R6

16

M_ADM_R6 M_DATA_R_54

10

M_DATA_R_55

11

M_DATA_R_60

12

M_DATA_R_61

13

M_ADM_R7

14

M_DATA_R_62

15

M_DATA_R_63

16

D

M_CKE#0 M_AA12

M_BA12 M_BA5

M_AA11 M_AA9 M_AA7 M_AA5 M_AA4 M_AA8 M_AA6 M_AA3

M_AWE# M_ABS#0

M_BA3 M_BA7

M_AA1 M_AA10 M_AA2 M_AA0 M_ABS#1 M_ARAS# M_CS#2 M_BA13

M_BA9 M_BA6 M_BA10 M_BA1 M_BA2 M_BA0 M_BBS#0 M_BWE#

M_BA4 M_BA8 M_BA11 M_CKE#1

M_AA13 M_CS#0 M_CS#1 M_ACAS#

M_CS#3 M_BCAS# M_BRAS# M_BBS#1

4 5 3 2 1

SRN47J-7-GP

1 4 2

8 9 7 6 5 4 3 2 1

SRN47J-4-GP

RN108

SRN47J-4-GP

RN51

3

RN50

RN50 SRN47J-7-GP

SRN47J-7-GP

3

RN55

RN55 SRN47J-6-GP

SRN47J-6-GP

10 11 12 13 14 15 16

SRN47J-4-GP

RN63

4 5 3 2 1

RN109

RN65 SRN47J-7-GPRN65 SRN47J-7-GP

1 4 2

3

RN68

SRN47J-7-GP

1 4 2

3

SRN47J-6-GP

10 11 12 13 14 15 16

RN64

RN64 SRN47J-6-GP

SRN47J-6-GP

10 11 12 13 14 15 16

RN69

6 7 8

E

M_ADM_R[7..0] 8

M_ADM[7..0] 5 M_DATA[63..0] 5 M_DATA_R_[63..0] 8 M_DQS[7..0] 5 M_DQS_R[7..0] 8

M_AA[13..0] 5,8

M_ABS#[1..0] 5,8

M_BA[13..0] 5,8

M_BBS#[1..0] 5,8

M_AWE# 5,8

M_ACAS# 5,8

6 7 8

M_CKE#05,8 M_CKE#15,8

M_ARAS# 5,8

M_BWE# 5,8

M_BCAS# 5,8

M_BRAS# 5,8

M_CS#0 5,8

M_CS#1 5,8

M_CS#2 5,8

M_CS#3 5,8

M_CKE#0 M_CKE#1

1 1

05/10 Remove the damping resistor for AMD suggest.

A

B

C

D

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

DDR DAMPING & TERMINATION

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

958Thursday, October 13, 2005

E

of

SA

A

B

C

D

E

4 4

2D5V_S3

1D25V_S3

3 3

2D5V_S3

1D25V_S3

2 2

12

C866

C866 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C861

C861 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C872

C872 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C875

C875 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C868

C870

SCD1U25V3ZY-3GP

12

C863

C865

SCD1U25V3ZY-3GP

12

C876

C874

SCD1U25V3ZY-3GP

12

C881

C879

SCD1U25V3ZY-3GP

LAYOUT:Place altemating caps to GND and 2D5_S3

12

C860

C860 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C867

C867 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C878

C878 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C883

C883 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C862

C862 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C869

C869 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C880

C880 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C873

C873 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C864

C864 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C871

C871 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C882

C882 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C877

C877 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C394

C417

SCD1U25V3ZY-3GP

DY

12

C509

C481

SCD1U25V3ZY-3GP

DY

12

C510

C402

SCD1U25V3ZY-3GP

DY

12

C403

C511

SCD1U25V3ZY-3GP

DY

12

C430

C430 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C464

C464 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C450

C450 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C451

C451 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C437

C437 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C456

C456 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C364

C364 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C365

C365 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C469

C457

SCD1U25V3ZY-3GP

12

C436

C418

SCD1U25V3ZY-3GP

12

C378

C409

SCD1U25V3ZY-3GP

12

C379

C388

SCD1U25V3ZY-3GP

12

C383

C383 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C424

C424 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C421

C421 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C422

C422 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C491

C491 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C416

C416 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C441

C441 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C442

C442 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C358

C425

SCD1U25V3ZY-3GP

12

C382

C401

SCD1U25V3ZY-3GP

12

C471

C458

SCD1U25V3ZY-3GP

12

C397

C475

SCD1U25V3ZY-3GP

12

C498

C498 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C419

C419 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C495

C495 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C497

C497 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

1D25V_S3

12

DY

12

C501

C500

SCD1U25V3ZY-3GP

12

C494

C494 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C503

C503 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C499

C499 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

12

C520

C520 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

C357

C357 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

LAYOUT:Place close to Power Pin of DDR socket.

LAYOUT:Place at end of the DIMMs

1D25V_S3

12

DY

TC15

TC15 ST100U4VBM-U

ST100U4VBM-U

12

TC26

SE100U10VM-4GP

79.10111.40L

12

C889

C889 SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

12

C886

C886 SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

12

C888

C888 SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

12

C887

C887 SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

2D5V_S3 2D5V_S3

C466

1 2

SCD22U16V3ZY-GP

SCD22U16V3ZY-GP C465

C465

1 2

SCD22U16V3ZY-GP

SCD22U16V3ZY-GP C484

C484

1 2

DY

SCD22U16V3ZY-GP

DY

C483

C483 SCD22U16V3ZY-GP

SCD22U16V3ZY-GP C482

C482 SCD22U16V3ZY-GP

SCD22U16V3ZY-GP

1 2

C504

C504 SCD22U16V3ZY-GP

SCD22U16V3ZY-GP C519

C519 SCD22U16V3ZY-GP

SCD22U16V3ZY-GP

DY

C518

C518 SCD22U16V3ZY-GP

SCD22U16V3ZY-GP

DY

C502

C502 SCD22U16V3ZY-GP

SCD22U16V3ZY-GP C517

C517 SCD22U16V3ZY-GP

SCD22U16V3ZY-GP

0.22u x 10

1 1

A

B

C

D

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

DDR DECOUPLING

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

10 58Thursday, October 13, 2005

of

E

of

SA

A

4 4

B

C

D

E

CLAW HAMMER TO NB NB TO CLAW HAMMER

CPUCADOUT[15..0]4 CPUCADOUTJ[15..0]4

3 3

1D2V_S0

12

2 2

AROUND NB

12

C254

C254 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C248

C248 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

DY

1D2V_S0

CPUHTTCLKOUT14 CPUHTTCLKOUTJ14

CPUHTTCLKOUT04 CPUHTTCLKOUTJ04

CPUHTTCTLOUT04 CPUHTTCTLOUTJ04

R124 49D9R2F-GPR124 49D9R2F-GP

1 2

R123 49D9R2F-GPR123 49D9R2F-GP

1 2

CPUCADOUT15 CPUCADOUTJ15 CPUCADOUT14 CPUCADOUTJ14 CPUCADOUT13 CPUCADOUTJ13 CPUCADOUT12 CPUCADOUTJ12 CPUCADOUT11 CPUCADOUTJ11 CPUCADOUT10 CPUCADOUTJ10 CPUCADOUT9 CPUCADOUTJ9 CPUCADOUT8 CPUCADOUTJ8

CPUCADOUT7 CPUCADOUTJ7 CPUCADOUT6 CPUCADOUTJ6 CPUCADOUT5 CPUCADOUTJ5 CPUCADOUT4 CPUCADOUTJ4 CPUCADOUT3 CPUCADOUTJ3 CPUCADOUT2 CPUCADOUTJ2 CPUCADOUT1 CPUCADOUTJ1 CPUCADOUT0 CPUCADOUTJ0

CPUHTTCLKOUT1 CPUHTTCLKOUTJ1

CPUHTTCLKOUT0 CPUHTTCLKOUTJ0

CPUHTTCTLOUT0 CPUHTTCTLOUTJ0

HT_RXCALN HT_RXCALP

W25

W24 AA25 AA24 AB26 AA26 AC25 AC24 AD26 AC26

W30

AB29 AA29 AC29 AC28

W26

W29

W28

T26 R26 U25 U24 V26 U26

R29 R28 T30 R30 T28 T29 V29 U29 Y30

Y28 Y29

Y26

P29 N29

D27 E27

U61A

HT_RXCAD15P HT_RXCAD15N HT_RXCAD14P HT_RXCAD14N HT_RXCAD13P HT_RXCAD13N HT_RXCAD12P HT_RXCAD12N HT_RXCAD11P HT_RXCAD11N HT_RXCAD10P HT_RXCAD10N HT_RXCAD9P HT_RXCAD9N HT_RXCAD8P HT_RXCAD8N

HT_RXCAD7P HT_RXCAD7N HT_RXCAD6P HT_RXCAD6N HT_RXCAD5P HT_RXCAD5N HT_RXCAD4P HT_RXCAD4N HT_RXCAD3P HT_RXCAD3N HT_RXCAD2P HT_RXCAD2N HT_RXCAD1P HT_RXCAD1N HT_RXCAD0P HT_RXCAD0N

HT_RXCLK1P HT_RXCLK1N

HT_RXCLK0P HT_RXCLK0N

HT_RXCTLP HT_RXCTLN

HT_RXCALN HT_RXCALP

NB0CADOUT15

PART 1OF6

HT_TXCAD15P HT_TXCAD15N HT_TXCAD14P HT_TXCAD14N HT_TXCAD13P HT_TXCAD13N HT_TXCAD12P HT_TXCAD12N HT_TXCAD11P HT_TXCAD11N HT_TXCAD10P HT_TXCAD10N

HT_TXCAD9P HT_TXCAD9N HT_TXCAD8P HT_TXCAD8N

HT_TXCAD7P HT_TXCAD7N HT_TXCAD6P HT_TXCAD6N HT_TXCAD5P HT_TXCAD5N HT_TXCAD4P HT_TXCAD4N HT_TXCAD3P HT_TXCAD3N HT_TXCAD2P HT_TXCAD2N HT_TXCAD1P HT_TXCAD1N HT_TXCAD0P HT_TXCAD0N

HT_TXCLK1P HT_TXCLK1N

HYPER TRANSPORT CPU I/F

HT_TXCLK0P HT_TXCLK0N

HT_TXCTLP

HT_TXCTLN HT_TXCALP

HT_TXCALN

R24 R25 N26 P26 N24 N25 L26 M26 J26 K26 J24 J25 G26 H26 G24 G25

L30 M30 L28 L29 J29 K29 H30 H29 E29 E28 D30 E30 D28 D29 B29 C29

L24 L25

F29 G29

M29 M28

B28 A28

NB0CADOUTJ15 NB0CADOUT14 NB0CADOUTJ14 NB0CADOUT13 NB0CADOUTJ13 NB0CADOUT12 NB0CADOUTJ12 NB0CADOUT11 NB0CADOUTJ11 NB0CADOUT10 NB0CADOUTJ10 NB0CADOUT9 NB0CADOUTJ9 NB0CADOUT8 NB0CADOUTJ8

NB0CADOUT7 NB0CADOUTJ7 NB0CADOUT6 NB0CADOUTJ6 NB0CADOUT5 NB0CADOUTJ5 NB0CADOUT4 NB0CADOUTJ4 NB0CADOUT3 NB0CADOUTJ3 NB0CADOUT2 NB0CADOUTJ2 NB0CADOUT1 NB0CADOUTJ1 NB0CADOUT0 NB0CADOUTJ0

NB0HTTCLKOUT1 NB0HTTCLKOUTJ1

NB0HTTCLKOUT0 NB0HTTCLKOUTJ0

NB0HTTCTLOUT NB0HTTCTLOUTJ

HT_TXCALP HT_TXCALN

R498

1 2

NB0CADOUT[15..0] 4 NB0CADOUTJ[15..0] 4

NB0HTTCLKOUT1 4 NB0HTTCLKOUTJ1 4

NB0HTTCLKOUT0 4 NB0HTTCLKOUTJ0 4

NB0HTTCTLOUT 4 NB0HTTCTLOUTJ 4

100R2F-L1-GP-U

1 1

A

B

C

D

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

ATI-RS482M (1 of 4) HT

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

11 58Thursday, October 13, 2005

of

E

of

SA

A

4 4

3 3

Dummy when 'USE DVO'

C829 SCD47U10V3ZY-GPC829 SCD47U10V3ZY-GP

MEM_CAP1

2 2

R178

1D8V_S0

1 2

0R0603-PAD

1 2

MEM_CAP2

1 2

C837 SCD47U10V3ZY-GPC837 SCD47U10V3ZY-GP

RS480_MEM_VMODE

MEM_VREF MPVDD_PLL

12

C366

C366 SC1U10V3KX-3GP

SC1U10V3KX-3GP

AF17 AK17 AH16

AF16

AJ22

AJ21 AH20 AH21 AK19 AH19

AJ17 AG16 AG17 AH17

AJ18 AG26

AJ29 AE21 AH24 AH12 AG13

AH8 AE8

AF25 AH30 AG20

AJ25 AH13

AF14

AG8

AG25 AH29

AF21 AK25

AJ12

AF13

AK7 AF9

AE17 AH18 AE18

AJ19

AF18 AK16

AJ16

AE28

AJ20

AK20

AJ15

AJ14

AJ7

AJ4

U61C

NC#AF17 NC#AK17 NC#AH16 NC#AF16 NC#AJ22 NC#AJ21 NC#AH20 NC#AH21 NC#AK19 NC#AH19 NC#AJ17 NC#AG16 NC#AG17 NC#AH17 NC#AJ18

NC#AG26 NC#AJ29 NC#AE21 NC#AH24 NC#AH12 NC#AG13 NC#AH18 NC#AE8

NC#AF25 NC#AH30 NC#AG20 NC#AJ25 DVO_IDCKP NC#AF14 NC#AJ7 NC#AG8

NC#AG25 NC#AH29 NC#AF21 NC#AK25 DVO_IDCKN NC#AF13 NC#AK7 NC#AF9

NC#AE17 NC#AH18 NC#AE18 NC#AJ19 NC#AF18

NC#AK16 NC#AJ16

NC#AE28 NC#AJ4

NC#AJ20

NC#AK20 VDD_18

VSS

PART 3 OF 6

B

AF28

NC#AF28

AF27

NC#AF27

AG28

NC#AG28

AF26

NC#AF26

AE25

NC#AE25

AE24

NC#AE24

AF24

NC#AF24

AG23

NC#AG23

AE29

NC#AE29

AF29

NC#AF29

AG30

NC#AG30

AG29

NC#AG29

AH28

NC#AH28

AJ28

NC#AJ28

AH27

NC#AH27

AJ27

NC#AJ27

AE23

NC#AE23

AG22

NC#AG22

AF23

NC#AF23

AF22

NC#AF22

AE20

NC#AE20

AG19

NC#AG19

AF20

NC#AF20

AF19

NC#AF19

AH26

NC#AH26

AJ26

NC#AJ26

AK26

NC#AK26

AH25

NC#AH25

AJ24

NC#AJ24

AH23

NC#AH23

AJ23

NC#AJ23

AH22

NC#AH22

AK14

NC#AK14

AH14

DVO_D11

AK13

DVO_D10

AJ13

DVO_D9

AJ11

DVO_D8

AH11

DVO_D7

AJ10

DVO_D6

AH10

DVO_D4

AE15

NC#AE15

AF15

NC#AF15

AG14

NC#AG14

AE14

NC#AE14 NC#AE12

NC#AF12 NC#AG11 NC#AE11

DVO_D5 DVO_D1 DVO_D2 DVO_D3 DVO_D0

DVO_DE

NC#AG10

NC#AF11

NC#AF10

NC#AE9

NC#AG7

NC#AF8 NC#AF7 NC#AE7

NC#AH5

NC#AD30

AE12 AF12 AG11 AE11 AJ9 AH9 AJ8 AK8 AH7 AJ6 AH6 AJ5 AG10 AF11 AF10 AE9 AG7 AF8 AF7 AE7

AH5 AD30

MEM_A I/F

DVO_HSYNC DVO_VSYNC

C

PEG_TXP15 PEG_TXN15 PEG_TXP14 PEG_TXN14 PEG_TXP13 PEG_TXN13 PEG_TXP12 PEG_TXN12 PEG_TXP11 PEG_TXN11 PEG_TXP10 PEG_TXN10 PEG_TXP9 PEG_TXN9 PEG_TXP8 PEG_TXN8 PEG_TXP7 PEG_TXN7 PEG_TXP6 PEG_TXN6 PEG_TXP5 PEG_TXN5

LANE REVERSE

PEG_TXP4 PEG_TXN4 PEG_TXP3 PEG_TXN3 PEG_TXP2 PEG_TXN2 PEG_TXP1 PEG_TXN1 PEG_TXP0 PEG_TXN0

PCIE_RX0P_SB17 PCIE_RX0N_SB17

PCIE_RX1P_SB17 PCIE_RX1N_SB17

R531 10KR2J-2-GPR531 10KR2J-2-GP

1 2 1 2

8K25R3F-2-GP

R532

PEG_TXP[15..0]49 PEG_TXN[15..0]49

PEG_RXP[15..0]49 PEG_RXN[15..0]49

PCE_ISET

PCE_TXISET

U61B

D8

GFX_RX0P

D7

GFX_RX0N

D5

GFX_RX1P

D4

GFX_RX1N

E4

GFX_RX2P

F4

GFX_RX2N

G5

GFX_RX3P

G4

GFX_RX3N

H4

GFX_RX4P

J4

GFX_RX4N

H5

GFX_RX5P

H6

GFX_RX5N

G1

GFX_RX6P

G2

GFX_RX6N

K5

GFX_RX7P

K4

GFX_RX7N

L4

GFX_RX8P

M4

GFX_RX8N

N5

GFX_RX9P

N4

GFX_RX9N

P4

GFX_RX10P

R4

GFX_RX10N

P5

GFX_RX11P

P6

GFX_RX11N

P2

GFX_RX12P

R2

GFX_RX12N

T5

GFX_RX13P

T4

GFX_RX13N

U4

GFX_RX14P

V4

GFX_RX14N

W1

GFX_RX15P

W2

GFX_RX15N

AE1

GPP_RX0P/SB_RX2P

AE2

GPP_RX0N/SB_RX2N

AB2

GPP_RX1P/SB_RX3P

AC2

GPP_RX1N/SB_RX3N

AB5

GPP_RX2P

AB4

GPP_RX2N

Y4

GPP_RX3P

AA4

GPP_RX3N

AG1

SB_RX0P

AH1

SB_RX0N

AC5

SB_RX1P

AC6

SB_RX1N

AH3

PCE_ISET

AJ3

PCE_TXISET

PART 2 OF 6

GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N GFX_TX8P GFX_TX8N GFX_TX9P GFX_TX9N

GFX_TX10P

GFX_TX10N

GFX_TX11P

GFX_TX11N

GFX_TX12P

GFX_TX12N

GFX_TX13P

GFX_TX13N

GFX_TX14P

GFX_TX14N

PCIE I/F TO VIDEO

GFX_TX15P

GFX_TX15N

GPP_TX0P/SB_TX2P GPP_TX0N/SB_TX2N

GPP_TX1P/SB_TX3P

PCIE I/F TO SLOT

PCIE I/F TO SB

GPP_TX1N/SB_TX3N

GPP_TX2P GPP_TX2N

GPP_TX3P GPP_TX3N

PCE_PCAL PCE_NCAL

SB_TX0P SB_TX0N

SB_TX1P SB_TX1N

D

PEG_RXP15_NB PEG_RXP15

A7 B7

PEG_RXP14_NB

B6 B5

PEG_RXP13_NB

A5

PEG_RXN13_NB

A4

PEG_RXP12_NB

B3

PEG_RXN12_NB

B2

PEG_RXP11_NB

C1

PEG_RXN11_NB

D1

PEG_RXP10_NB

D2

PEG_RXN10_NB

E2

PEG_RXP9_NB

F2

PEG_RXN9_NB

F1

PEG_RXP8_NB

H2

PEG_RXN8_NB

J2

PEG_RXP7_NB

J1

PEG_RXN7_NB

K1

PEG_RXP6_NB

K2

PEG_RXN6_NB

L2

PEG_RXP5_NB

M2

PEG_RXN5_NB

M1

PEG_RXP4_NB

N1

PEG_RXN4_NB

N2

PEG_RXP3_NB

R1

PEG_RXN3_NB

T1

PEG_RXP2_NB

T2

PEG_RXN2_NB

U2

PEG_RXP1_NB

V2

PEG_RXN1_NB

V1

PEG_RXP0_NB

Y2

PEG_RXN0_NB

AA2

AD2 AD1

AA1 AB1

Y5 Y6

W5 W4

SB_TX0P

AF2

SB_TX0N

AG2

SB_TX1P

AC4

SB_TX1N

AD4

PCE_PCAL

AH2

PCE_NCAL

AJ2

C752

C752 C753

C753 C754

C754 C755

C755 C756

C756 C757

C757 C758

C758 C759

C759 C771

C771 C770

C770 C775

C775 C774

C774 C776

C776 C784

C784 C783

C783 C789

C789 C792

C792 C791

C791 C790

C790 C794

C794 C795

C795 C801

C801 C799

C799 C798

C798 C800

C800 C805

C805 C804

C804 C810

C810 C811

C811 C812

C812 C816

C816 C817

C817

C824

1 2

C825

1 2

C826

1 2

C830

1 2

R528 150R2F-1-GPR528 150R2F-1-GP

1 2

R529 100R2F-L1-GP-UR529 100R2F-L1-GP-U

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

1 2

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

PCIE_TX0P_SB 17 PCIE_TX0N_SB 17

PCIE_TX1P_SB 17 PCIE_TX1N_SB 17

E

PEG_RXN15PEG_RXN15_NB PEG_RXP14 PEG_RXN14PEG_RXN14_NB PEG_RXP13 PEG_RXN13 PEG_RXP12 PEG_RXN12 PEG_RXP11 PEG_RXN11 PEG_RXP10 PEG_RXN10 PEG_RXP9 PEG_RXN9 PEG_RXP8 PEG_RXN8 PEG_RXP7 PEG_RXN7 PEG_RXP6 PEG_RXN6 PEG_RXP5 PEG_RXN5 PEG_RXP4 PEG_RXN4 PEG_RXP3 PEG_RXN3 PEG_RXP2 PEG_RXN2 PEG_RXP1 PEG_RXN1 PEG_RXP0 PEG_RXN0

Dummy when use UMA

1D2V_S0

LANE REVERSE

12

R174

R174 1KR2F-3-GP

1KR2F-3-GP

MEM_VREF

12

1 1

R175

R175 1KR2F-3-GP

1KR2F-3-GP

NO DVO: MEM_COMPP = NC MEM_COMPN = NC MEM_CAP1 = 470nF MEM_CAP2 = 470nF MEM_VMODE = GND (IF VDD_MEM = 2.5V) MEM_VREF = VDD_MEM / 2

A

WITH DVO: MEM_COMPP = 61.9 OHM TO GND MEM_COMPN = 61.9 OHM TO VDD_MEM MEM_CAP1 = NC MEM_CAP2 = NC MEM_VMODE = 1.8V(IF VDD_MEM = 1.8V) MEM_VREF = VDD_MEM / 2

B

RS480_MEM_VMODE

C

R170

R170 1KR2J-1-GP

1KR2J-1-GP

1 2

Dummy when 'USE DVO'

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

ATI-RS482M (2 of 4) PCIE

Size Document Number Rev

A3

Date: Sheet

D

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

12 58Thursday, October 13, 2005

E

SA

of

SA

A

12

C782

DY

1 2

150R5F

12

NB_SUS_STAT#

AVDDQ

12

C781

SC10U10V5ZY-1GP

SCD1U16V2ZY-2GP

Dummy when use Discrete

UMA_CRMA57

UMA_LUMA57

UMA_COMP57

UMA_R57 UMA_G57

1D8V_S0

12

R535

R535 4K7R2J-2-GP

4K7R2J-2-GP

UMA_B57

R487

1 2

BLM11A121S-GP

HTPVDD

12

C793

SC10U10V5ZY-1GP

12

C788

C787

SCD1U16V2ZY-2GP

DO NOT SUPPORT SIDEPORT MEMORY DO NOT SUPPORT SERIAL STRAP ROM DUMMY IT

PLVDD

12

C747

C748

SC10U10V5ZY-1GP

SC2D2U16V5ZY-GP

3D3V_S01D8V_S0

R151

1 2

SCD1U16V2ZY-2GP

0R0603-PAD

EDID_CLK16,50 EDID_DAT16,50

1 2

R491 150R2F-1-GPR491 150R2F-1-GP

R492 150R2F-1-GPR492 150R2F-1-GP

12

C741

SCD1U16V2ZY-2GP

1 2

R493 150R2F-1-GPR493 150R2F-1-GP

12

C280

C280 SC1U10V3ZY-6GP

SC1U10V3ZY-6GP

3 4

1D8V_S0

3D3VDDR_S0

RN105

RN105 SRN0J-6-GP

SRN0J-6-GP

1D8V_S0

R511

1 2

0R0603-PAD

4 4

3 3

1D8V_S0

R515

2 2

Dummy when use Discrete

R126

1 2

0R0603-PAD

R495

1 2

150R2F-1-GP

3D3V_S0

2 1

B

R494

R496

150R2F-1-GP

UMA_CRT_DDC_C15 UMA_CRT_DDC_D15

3

R490

1 2

0R0603-PAD

12

C247

C247 SC2D2U16V5ZY-GP

SC2D2U16V5ZY-GP

AVDDQ

12

UMA_VS15 UMA_HS15

CLK14_NB3

RN104

SRN10KJ-5-GP

C

AVDD3D3V_S0

12

C751

C751 SC2D2U16V5ZY-GP

SC2D2U16V5ZY-GP

1D8VAVDDD1_S0

U61D

B27

AVDD1

C27

AVDD2

D26

AVSSN1

D25

AVSSN2

C24

AVDDDI

B24

C263

C263 SC1U10V3ZY-6GP

SC1U10V3ZY-6GP

R125

1 2

715R2F-GP

NB_PWRGD39,52

LDT_STP#6,17

ALLOW_LDTSTOP17

TP97TPAD30 TP97TPAD30

TP22TPAD30 TP22TPAD30 TP21TPAD30 TP21TPAD30 TP95 TPAD30TP95 TPAD30

14 2

BMREQ#17

IRSET_NB

RS480_RST#

NB_SUS_STAT#

NB_OSC_OUT

10KR2J-2-GP

10KR2J-2-GP R497

R497

1 2

DFT_GPIO0 DFT_GPIO2

RS480_CLK RS480_DAT

AVSSDI

E24

AVDDQ

D24

AVSSQ

B25

C

A25

Y

A24

COMP

C25

RED

A26

GREEN

B26

BLUE

A11

DAC_VSYNC

B11

DAC_HSYNC

C26

RSET

E11

DAC_SCL

F11

DAC_SDA

A14

PLLVDD

B14

PLLVSS

M23

HTPVDD

L23

HTPVSS

D14

SYSRESET#

B15

POWERGOOD

B12

LDTSTOP#

C12

ALLOW_LDTSTOP

AH4

NC

H13

VDDR3_1

H12

VDDR3_2

A13

OSCIN

B13

OSCOUT

B9

TVCLKIN

F12

DFT_GPIO0

E13

DFT_GPIO1

D13

DFT_GPIO2

F10

BMREQ#

C10

I2C_CLK

C11

I2C_DATA

AF4

THERMALDIODE_P

AE4

THERMALDIODE_N

PART 4 OF 6

CRT/TVOUT

PLL PWR

PM

CLOCKs

MIS.

TXOUT_U0P TXOUT_U0N TXOUT_U1P TXOUT_U1N TXOUT_U2P TXOUT_U2N TXOUT_U3P TXOUT_U3N

TXOUT_L0P TXOUT_L0N TXOUT_L1P TXOUT_L1N TXOUT_L2P TXOUT_L2N TXOUT_L3P TXOUT_L3N

TXCLK_UP TXCLK_UN

TXCLK_LP

LVDS

TXCLK_LN

LPVDD

LPVSS

LVDDR18D LVDDR18A_1 LVDDR18A_2

LVSSR1 LVSSR2 LVSSR3 LVSSR4 LVSSR5 LVSSR6 LVSSR7 LVSSR8

LVDS_DIGON

LVDS_BLON LVDS_BLEN

GFX_CLKP

GFX_CLKN

HTTSTCLK

HTREFCLK

SB_CLKP SB_CLKN

DFT_GPIO3 DFT_GPIO4 DFT_GPIO5

TMDS_HPD

STRP_DATA

DDC_DATA

TESTMODE

VCC_CORE_S0

12

D18 C18 B19 A19 D19 C19 D20 C20

B16 A16 D16 C16 B17 A17 E17 D17

B20 A20 B18 C17

E18 F17 E19 G20 H20

G19 E20 F20 H18 G18 F19 H19 F18

E14 F14 F13

B8 A8

P23 N23

E8 E7

C13 C14 C15

A10 E10 B10 E12

R147

R147 DUMMY-R2

DUMMY-R2

D

TXBOUT0+ TXBOUT0TXBOUT1+ TXBOUT1TXBOUT2+

TXBOUT2TXBOUT3+ TXBOUT3-

TXAOUT0+

TXAOUT0-

TXAOUT1+

TXAOUT1-

TXAOUT2+

TXAOUT2TXAOUT3+ TXAOUT3-

TXBCLK+

TXBCLK-

TXACLK+

TXACLK-

LCDVDD_ON LVDS_BLON LVDS_BLEN_NB

HTTST_CLK

DFT_GPIO3

DFT_GPIO4DFT_GPIO1

DFT_GPIO5

DDC_DATA TESTMODE_NB

TP23TP23 TP20TP20

R153

1 2

TP28TP28 TP27TP27

TP24 TPAD30TP24 TPAD30

NBSRC_CLK 3 NBSRC_CLK# 3

10KR2J-2-GP

HTREF_CLK 3 SBLINK_CLK 3

SBLINK_CLK# 3

TP99 TPAD28TP99 TPAD28 TP26 TPAD28TP26 TPAD28 TP100 TPAD28TP100 TPAD28

TXACLK+ TXACLKTXAOUT2+ TXAOUT2-

TXAOUT1+ TXAOUT1TXAOUT0+ TXAOUT0-

TXBOUT1+ TXBOUT1TXBOUT0+ TXBOUT0-

TXBCLK+ TXBCLKTXBOUT2+ TXBOUT2-

LCDVDD_ON

1D8VLPVDD_S0

TP98 TPAD30TP98 TPAD30TP25TPAD30 TP25TPAD30 TP96 TPAD30TP96 TPAD30

45

R137

RN80

RN78

RN84

RN86

SRN0J-4-GP

12

0R2J-GP

3 2 1

45 3 2 1

6 7 8

Dummy when use Discrete

12

C746

LVDDR18D_S0

LVDDR18A_S0

12

C744

SC1U10V3ZY-6GP

C745

12

E

LCD_TXACLK+ 16,57 LCD_TXACLK- 16,57

LCD_TXAOUT2+ 16,57

LCD_TXAOUT2- 16,57

LCD_TXAOUT1+ 16,57

LCD_TXAOUT1- 16,57

LCD_TXAOUT0+ 16,57

LCD_TXAOUT0- 16,57

LCD_TXBOUT1+ 16,57

LCD_TXBOUT1- 16,57

LCD_TXBOUT0+ 16,57

LCD_TXBOUT0- 16,57

LCD_TXBCLK+ 16,57 LCD_TXBCLK- 16,57

LCD_TXBOUT2+ 16,57

LCD_TXBOUT2- 16,57

LCD_VDD_ON 16,57

1 2

12

C251

1 2

12

C250

SC1U10V3ZY-6GP

SC2D2U16V5ZY-GP

1 2

C249

SC1U10V3ZY-6GP

SCD1U16V2ZY-2GP

R486

R485

R484

1D8V_S0

BLM11A121S-GP

12

R142

R142 4K7R2J-2-GP

1 1

R118

LPC_RST#17,34,37,49

1 2

33R2J-2-GP

RS480_RST#

12

C235

C235 DUMMY-C3

DUMMY-C3

LVDS_BLON

12

1 2

R474

R474 1KR2J-1-GP

1KR2J-1-GP

R475

0R2J-GP

Dummy when use Discrete

A

B

C

4K7R2J-2-GP

R305

R305 10KR2J-2-GP

10KR2J-2-GP

1 2

D

BL_ON 34,52

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet

ATI-RS482M (3 of 4) LVDS CRT

A3

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

13 58Thursday, October 13, 2005

E

of

SA

A

B

C

D

E

VSS89

U61F

4 4

3 3

12

C297

SC10U10V5ZY-1GP

12

C311

SCD1U16V2ZY-2GP

2 2

12

C822

SC10U10V5ZY-1GP

12

C354

1D8V_S0

SCD1U16V2ZY-2GP

1 1

3D3V_S0

1 2

U13

U13 BAV99PT-GP-U

BAV99PT-GP-U

DY

C291

DY

12

C312

12

C823

12

C334

3

12

C276

SCD1U16V2ZY-2GP

12

C313

DY

SCD1U16V2ZY-2GP

12

C330

SCD1U16V2ZY-2GP

12

C343

DY

SCD1U16V2ZY-2GP

L12

1 2

BLM11A121S-GP

DY

0R2J-GP

3

1 2

U14

U14 BAV99PT-GP-U

BAV99PT-GP-U

DY

A

12

C278

SCD1U16V2ZY-2GP

12

C329

SCD1U16V2ZY-2GP

12

C344

SCD1U16V2ZY-2GP

12

C341

SCD1U16V2ZY-2GP

12

R177

DY

12

C277

SCD1U16V2ZY-2GP

12

C328

SCD1U16V2ZY-2GP

12

C331

SCD1U16V2ZY-2GP

12

C345

DY

SCD1U16V2ZY-2GP

12

C373

12

DY

R176

0R2J-GP

12

C258

SCD1U16V2ZY-2GP

12

C296

SCD1U16V2ZY-2GP

12

C340

SCD1U16V2ZY-2GP

12

C371

SCD1U16V2ZY-2GP

1D8VDD_S0

12

C279

SCD1U16V2ZY-2GP

AD28

F24

F27

G28

VSS110

VSS111

VSS112

12

C259

SCD1U16V2ZY-2GP

12

C327

1D8V_S0

SCD1U16V2ZY-2GP

12

C355

SCD1U16V2ZY-2GP

12

C342

SCD1U16V2ZY-2GP

12

C333

SCD1U16V2ZY-2GP

T27

R27

VSS107

VSS108

VSS109

12

C372

SCD1U16V2ZY-2GP

12

C356

SCD1U16V2ZY-2GP

C332

1D2V_S0

SC1U10V3KX-3GP

AE26

AE27

VSS106

1D2V_S0

AK29

W19

VSS103

VSS104

VSS105

VDDHT30 VDDHT31

AD21

AK22

VSS102

AK10

AC13

VSS100

VSS101

B

AK5

VSS98

VSS99

N27 U27 V27 G27 V24 H27 K24

AB24

P27

AA27

K27

P24 AB27 AB23

V23

G23

E23

W23

K23

H23

U23 AA23

D23

C23

B23

A23

A29 AC30

AK23 AK28 AK11

AK4 AE30 AC14 AD12 AC18 AC20 AD10 AD14 AD15 AD20 AC10 AD18 AC12 AD22 AC22 AH15

H15 AC17 AC15

B21

C21

A22

B22

C22

E21

G21

AC21

J27

J23

F23

F21 F22

AJ30

VSS96

VSS97

AG27

AC11

AD7

VSS94

VSS95

U61E

VDD_HT1 VDD_HT2 VDD_HT3 VDD_HT4 VDD_HT5 VDD_HT6 VDD_HT7 VDD_HT8 VDD_HT9 VDD_HT10 VDD_HT11 VDD_HT12 VDD_HT13 VDD_HT14 VDD_HT15 VDD_HT16 VDD_HT17 VDD_HT18 VDD_HT19 VDD_HT20 VDD_HT21 VDD_HT22 VDD_HT23 VDD_HT24 VDD_HT25 VDD_HT26 VDD_HT27 VDD_HT28 VDD_HT29 VDD_HT30 VDD_HT31

VDD_DVO_1 VDD_DVO_2 VDD_DVO_3 VDD_DVO_4 VDD_DVO_5 VDD_DVO_6 VDD_DVO_7 VDD_DVO_8 VDD_DVO_9 VDD_DVO_10 VDD_DVO_11 VDD_DVO_12 VDD_DVO_13 VDD_DVO_14 VDD_DVO_15 VDD_DVO_16 VDD_DVO_17 VDD_DVO_18 VDD_DVO_19

VDD_18_1 VDD_18_2 VDD_18_3

VDD_CORE47 VDD_CORE46 VDD_CORE45 VDD_CORE44 VDD_CORE43 VDD_CORE42 VDD_CORE41 VDD_CORE40 VDD_CORE39

AC19

VSS92

VSS93

AG9

VSS91

AG15

AG12

AF30

AG24

VSS88

VSS89

VSS90

VSS132

V28

R23

PART 5 OF 6

AD19

AD23

AG5

AG6

AG21

AD17

VSS82

VSS83

VSS84

VSS85

VSS86

VSS87

VSS126

VSS127

VSS128

VSS129

VSS130

VSS131

P25

P28

E26

K25

V25

U28

VDDA_12_14

VDDA_12_1 VDDA_12_2 VDDA_12_3 VDDA_12_4 VDDA_12_5 VDDA_12_6 VDDA_12_7 VDDA_12_8

VDDA_12_9 VDDA_12_10 VDDA_12_11 VDDA_12_12 VDDA_12_13

VDDA_18_1

VDDA_18PLL_1

VDDA_18_2

VDDA_18_3

VDDA_18_4

VDDA_18_5

VDDA_18PLL_2 VDDA_18PLL_3

VDDA_18_6

VDDA_18_7

VDDA_18_8

VDDA_18_9 VDDA_18_10 VDD_CORE1 VDD_CORE2 VDD_CORE3 VDD_CORE4 VDD_CORE5 VDD_CORE6 VDD_CORE7 VDD_CORE8 VDD_CORE9

VDD_CORE10 VDD_CORE11 VDD_CORE12 VDD_CORE13 VDD_CORE14 VDD_CORE15 VDD_CORE16 VDD_CORE17 VDD_CORE18 VDD_CORE19 VDD_CORE20 VDD_CORE21 VDD_CORE22 VDD_CORE23 VDD_CORE24 VDD_CORE25 VDD_CORE26 VDD_CORE27 VDD_CORE28 VDD_CORE29 VDD_CORE30 VDD_CORE31 VDD_CORE32 VDD_CORE33 VDD_CORE34 VDD_CORE35 VDD_CORE36

POWER

VDD_CORE37 VDD_CORE38

AD13

AD16

VSS80

VSS81

VSS124

VSS125

H24

N28

AD8

AD11

VSS78

VSS79

VSS122

VSS123

M27

AC23

VSS76

VSS77

VSS120

L27

H9 AA7 G9 U8 N7 N8 U7 F9 AA8 G8 G7 J8 J7 B1 AG4 R8 AC8 AC7 AF6 AE6 L8 W8 W7 L7 R7 AF5 AK2 N16 M13 M15 W16 N18 P19 N12 P15 N14 M17 T19 G22 R12 P13 R14 V19 R18 U16 U12 T13 U14 T17 U18 E22 R16 V13 T15 P17 W18 D22 W12 V15 W14 V17 M19 H22 H21 D21

AG18

T23

U19

AC16

VSS73

VSS74

VSS75

VSS117

VSS118

VSS119

K28

N19

VDDA12_13

VDDA18_13

VSS116

J28

M24

M16

P16

VSS72

VSS114

VSS115

F28

H28

N17

W15

V16

T18

M14

M12

VSS66

VSS67

VSS68

VSS69

VSS70

VSS71

GROUND

VSSA68

VSS113

L5

T8

12

C281

1D8V_VDDA

12

C352

1D2V_S0

C

W13

W17

P18

V18

M18

U13

VSS60

VSS61

VSS62

VSS63

VSS64

VSS65

VSSA62

VSSA63

VSSA64

VSSA65

VSSA66

VSSA67

F6

V7

E6

E5

U5

U6

12

C282

SC1U10V3KX-3GP

SCD1U16V2ZY-2GP

12

C318

SC1U10V3KX-3GP

SCD1U16V2ZY-2GP

12

C298

SC10U10V5ZY-1GP

12

C316

DY

SC10U10V5ZY-1GP

R17

P12

T12

R13

VSS56

VSS57

VSS58

VSS59

VSSA58

VSSA59

VSSA60

VSSA61

L6

M7

AJ1

AG3

VSSA59

12

C303

12

C302

12

C299

SCD1U16V2ZY-2GP

12

C315

SCD1U16V2ZY-2GP

U17

T16

VSS54

VSS55

VSSA56

VSSA57

H8

C2

SCD1U16V2ZY-2GP

12

T14

N15

V12

N13

P14

VSS49

VSS50

VSS51

VSS52

VSS53

VSSA51

VSSA52

VSSA53

VSSA54

VSSA55

K7

V6

H7

M3

AD6

12

C306

SCD1U16V2ZY-2GP

12

C293

SCD1U16V2ZY-2GP

12

C300

DY

SCD1U16V2ZY-2GP

12

C314

SCD1U16V2ZY-2GP

R15

VSS48

VSSA50

Y7

12

E15

F15

U15

V14

VSS44

VSS45

VSS46

VSS47

VSSA44

VSSA45

VSSA46

VSSA47

VSSA48

VSSA49

T7

K3

D6

C4

AB8

AD5

1D2V_VDDA_RS480_S0

12

C335

SCD1U16V2ZY-2GP

C336

SCD1U16V2ZY-2GP

12

C292

C270

DY

SCD1U16V2ZY-2GP

12

C317

C305

SCD1U16V2ZY-2GP

H17

H10

H16

H14

E16

D10

VSS37

VSS38

VSS39

VSS40

VSS41

VSS42

VSS43

VSSA37

VSSA38

VSSA39

VSSA40

VSSA41

VSSA42

VSSA43

J5

J3

C9

C7

R6

AA5

C307

SC10U10V5ZY-1GP

12

TC10

TC10 ST100U6D3VDM-6GP

ST100U6D3VDM-6GP

DY

12

SCD1U16V2ZY-2GP

D

T24

F26

W27

D11

H11

AD25

VSS32

VSS33

VSS34

VSS35

VSS36

VSSA32

VSSA33

VSSA34

VSSA35

VSSA36

B4

P7

G3

M5

AF3

AB7

12

TC9

TC9 ST100U6D3VDM-6GP

ST100U6D3VDM-6GP

DY

L11

1 2

MLB-201209-21-GP

C301

SCD1U16V2ZY-2GP

VSS30

E9

D15

AD9

G11

F16

G30

AB28

AB25

D12

AD24

AA28

G17

Y23

AC9

R19

Y27

C28

G16

F25

B30

VSS16

VSS17

VSS18

VSS19

VSS20

VSS21

VSS22

VSS23

VSS24

VSS25

VSS26

VSS27

VSS28

VSS29

VSS30

VSS31

VSSA16

VSSA17

VSSA18

VSSA19

VSSA20

VSSA21

VSSA22

VSSA23

VSSA24

VSSA25

VSSA26

VSSA27

VSSA28

VSSA29

VSSA30

VSSA31

J6

F3

V8

AE3

1 2

1D8V_S0

A2

P8

C8

AA3

AB3

AD3

VSSA22

1D2V_S0

L10

L10 MLB-201209-21-GP

MLB-201209-21-GP

SB 0127

Title

Size Document Number Rev

A3

Date: Sheet

V3

K8

C3

D3

C6

W3

ATI-RS482M (4 of 4) PWR, GND

G13

VSS10

VSS11

VSS12D9VSS13

VSS14

VSS15

VSSA11

VSSA12

VSSA13

VSSA14

VSSA15

F8

Y8

C5

M6

M8

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

Y24

VSS9

VSSA9T3VSSA10

AA6

G14

VSS7

VSS8

VSSA8

R3

G15

AD29

AD27

AC27

VSS3

VSS4

VSS5

VSS6

VSSA3

VSSA4N3VSSA5F7VSSA6F5VSSA7

V5

VDDA12_13

VSSA22

VDDA18_13

VSSA59

VDDHT30

VSS30

VDDHT31

VSS89

E

G10

G12

VSS1

VSS2

PAR 6 OF 6

VSSA1

VSSA2

R5

AE5

12

14 58Thursday, October 13, 2005

of

C264

C264 SC4D7U10V5ZY-3GP

SC4D7U10V5ZY-3GP

C353

C353 SC4D7U10V5ZY-3GP

SC4D7U10V5ZY-3GP

C769

C769 SC4D7U10V5ZY-3GP

SC4D7U10V5ZY-3GP

C815

C815 SC4D7U10V5ZY-3GP

SC4D7U10V5ZY-3GP

SA

A

CRT CONN

200mA Rating/Spec 500mA

5V_S0

4 4

RN4

2

UMA_HS UMA_VS

Dummy when use Discrete

DIS_HS DIS_VS

3 4

Dummy when use UMA

SRN0J-6-GP

RN5

SRN0J-6-GP

VSYNC_5_1

1

2 1

HSYNC_5_1

14

4

5 6

7

2 3

U3B

TSAHCT125PW-GP

14

7

U3A

1

TSAHCT125PW-GP

C2

DUMMY-C2

B

UMA_CRT_DDC_D13

SYS_HS

UMA_CRT_DDC_C13

C

RN3

CRT_DDC_D_1

SRN0J-6-GP

2

CRT_DDC_C_1

1

3 4

D

3D3V_S0

U2

U2 2N7002DW-7F-GP

2N7002DW-7F-GP

34 5 6

2

1

RN1

123

5V_CRT_S0

678

4 5

SRN10KJ-6-GP

SYS_CRT_DDC_D5 SYS_CRT_DDC_C5

E

Dummy when use Discrete

RN2

SYS_VS

12

C1

DUMMY-C2

DIS_CRT_DDC_D50

DIS_CRT_DDC_C50

RN2

SRN0J-6-GP

2 1

3 4

Dummy when use UMA

5V_S0

12

C653

C653 SCD01U25V2KX-3GP

SCD01U25V2KX-3GP

D28

1 2

RB751V-40-1-GP

5V_CRT_S0

3 3

CRT_R_157

CRT_G_157

CRT_B_157

2 2

TV_LUMA57

TV_COMP57

TV_CRMA57

1 1

12

DY

12

C663

SC47P50V2JN-3GP

DY

A

12

C664

C665

SC47P50V2JN-3GP

DY

R148

R132

R138

1 2

150R2F-1-GP

12

R381150R2F-1-GPR381150R2F-1-GP

SC47P50V2JN-3GP

12

-1 0302

R382150R2F-1-GPR382150R2F-1-GP

1 2

C285

C285 SC100P50V2JN-U

SC100P50V2JN-U

1 2

C272

C272 SC100P50V2JN-U

SC100P50V2JN-U

1 2

C261

L18

1 2

L19

1 2

L20

1 2

12

R383150R2F-1-GPR383150R2F-1-GP

C283

1 2

SC47P50V2JN-3GP

L9

IND-1D2UH-5-GP

C271

1 2

SC47P50V2JN-3GP

L8

IND-1D2UH-5-GP

C260

1 2

SC47P50V2JN-3GP

L6

IND-1D2UH-5-GP

SC100P50V2JN-U

BLM11B750S-GP

TV_LUMA_CON

12

C284

C284 SC270P50V2JN-2GP

SC270P50V2JN-2GP

TV_COMP_CON

12

C266

C266 SC270P50V2JN-2GP

SC270P50V2JN-2GP

TV_CRMA_CON

12

C255

SC270P50V2JN-2GP

B

12

C659

SC8D2P50V2CC

D37

3

BAV99PT-GP-U

D34

3

BAV99PT-GP-U

D32

3

BAV99PT-GP-U

12

C660

SC8D2P50V2CC

2

DY

1

2

DY

1

2

DY

1

12

C661

SC8D2P50V2CC

3D3V_S0

3

D27

1

BAV99PT-GP-U

DY

CRT_R

CRT_G

CRT_B

D26

2

BAV99PT-GP-U

DY

TV_LUMA_CON

TV_COMP_CON

TV_CRMA_CON

CRT1

SYS_CRT_DDC_D5

SYS_HS

SYS_VS

SYS_CRT_DDC_C5

C655

12

C651

3

1

2

3

D25

1

BAV99PT-GP-U

DY

2

SC100P50V2JN-U

5V_S0

12

C652

SC10P50V2JN-1

SC100P50V2JN-U

12

C654

SC10P50V2JN-1

CRT_R

CRT_G CRT_B

5V_CRT_S0

10

ME : 20.20378.015

17

6 1

11

7 2

12 8 3

13 9 4

14 5

15

16

20.20378.015

VIDEO-15-42-GP

SYS_CRT_DDC_D5 SYS_HS SYS_VS SYS_CRT_DDC_C5

TV CONN

TV1

1 4

2 5 7 6 3

MINDIN7-11-U-GP

22.10021.D81

ME : 22.10021.D81

C

8

4

56

1

23

7

9

COMPOSIT

D

Title

Size Document Number Rev

A3

Date: Sheet

LUMACHROMA

CRT/TV

CRT/TV Bolsena-E

Bolsena-E

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

15 58Thursday, October 13, 2005

of

E

of

SA

A

B

C

D

E

LEDs

4 4

Dummy when use IDE

R11

EDID_CLK13,50

EDID_DAT13,50

C668

C667

1 2

SC100P50V2JN-U

A

1 2

R21

1 2

0R2J-GP

WLAN_LED#29

0R2J-GP

DCBATOUT

C658

D7

2

1

BAW56PT-U

NUM_LED#34 CAP_LED#34 MAIL_LED#34 BLT_LED#34

STDBY_LED#34 CHARGE_LED#34 DC_BATFULL#34

FRONT_PWRLED#34

MEDIA_LED#

3

LCD CONN

42

2 4

6 8

3D3V_S0

C662

SCD1U25V3ZY-3GP

12

SC10U35V0ZY-1GP

10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 41

ACES-CONN40A-GP

20.F0737.040

1ST 20.D0198.108 - 2ND 20.F0687.040

LCD1

DY

SRC100P50V-2-GP

RC2

NUM_LED# CAP_LED#

MAIL_LED# MEDIA_LED#

WLAN_LED# STDBY_LED#

BLT_LED#

CHARGE_LED#

DC_BATFULL#

FRONT_PWRLED#

LCDPOWER_S0

12

C44

C22

1 3

5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

SB 0202

B

DY

LCD_TXBCLK+ 13,57 LCD_TXBCLK- 13,57 LCD_TXBOUT2+ 13,57 LCD_TXBOUT2- 13,57 LCD_TXBOUT1+ 13,57 LCD_TXBOUT1- 13,57 LCD_TXBOUT0+ 13,57 LCD_TXBOUT0- 13,57 LCD_TXACLK+ 13,57 LCD_TXACLK- 13,57 LCD_TXAOUT2+ 13,57 LCD_TXAOUT2- 13,57 LCD_TXAOUT1+ 13,57 LCD_TXAOUT1- 13,57 LCD_TXAOUT0+ 13,57 LCD_TXAOUT0- 13,57

C22

SC10U10V5ZY-1GP

RC2

1 2 3 4 5

DY

RC11

1 2 3 4 5

C646 SC100P50V2JN-U

DY

1 2

C512 SC100P50V2JN-U

DY

1 2

12

C31

SCD1U25V3ZY-3GP

DY

SCD1U25V3ZY-3GP

EVEN CHANNEL

ODD CHANNEL

8 7 6

SRC100P50V-2-GP

8 7 6

on KB cover

LED ButtonVV

POWER1 E-MAIL INTERNETe-BTN PROGRAM

Front panel

LED ButtonVV

BlutToothWireless Charger Power2

LCD_VDD_ON13,57

C

SATA_LED#18

HDD_LED#_524

Dummy when use SATA

CDROM_LED#_524

3 3

2 2

BRIGHTNESS34

FPBACK34

1 1

NUM_LED#

CAP_LED#

MAIL_LED#

MEDIA_LED#

WLAN_LED#

FRONT_PWRLED#

DC_BATFULL#

BLT_LED#

STDBY_LED#

CHARGE_LED#

R19

1 2

100R2F-L1-GP-U

100R2F-L1-GP-U R26

R26

1 2

100R2F-L1-GP-U

100R2F-L1-GP-U R10

R10

1 2

100R2F-L1-GP-U

100R2F-L1-GP-U R20

R20

1 2

100R2F-L1-GP-U

1 2

R4

1 2

100R2F-L1-GP-U

100R2F-L1-GP-U R24

R24

1 2

100R2F-L1-GP-U

100R2F-L1-GP-U R378

R378

1 2

100R2F-L1-GP-U

R376

1 2

100R2F-L1-GP-U

R579

470R2J-2-GP

1 2

R377

1 2

100R2F-L1-GP-U

100R2F-L1-GP-U R375

R375

1 2

100R2F-L1-GP-U

R580

R580 22R2J-2-GP

22R2J-2-GP

V VVVV

V

VV

V

(Please See M.E. drawing LED position)

LCD POWER

Layout 40 mil

1KR2J-1-GP

12

LCDVDD_ON_1

12

C23

C69

SCD1U25V3ZY-3GP

SC1U10V3KX-3GP

R48

1 2

-2 0408

Charger: Green : DC only with Battery full with DC Orange : Charging Orange Blink : Battery low

U7

1

OUT

2

GND ON/OFF#3IN

AAT4280IGU-3-T1GP

D

LED-G-106-GP

D5

AK

LED-G-106-GP

D4

AK

LED-G-106-GP

D3

AK

LED-G-106-GP

D6

AK

D48 LED-Y-22D48 LED-Y-22

LED-G-106-GP

D2

AK

LED-G-106-GP

D9

AK

LED-G-106-GP

D46

AK

LED-G-106-GP

D44

AK

D47

12

LED-B-27-U-GP

D45 LED-Y-22D45 LED-Y-22

1 2

D43 LED-Y-22D43 LED-Y-22

1 2

CAPS NUM HDD

6

IN

5

GND

4

5V_S0

on KB Cover on KB Cover on KB Cover on KB Cover

on Front Panel

on KB Cover

on Front Panel

5V_S5

on Front Panel

5V_S0

on Front Panel

5V_S5

on Front Panel on Front Panel

VVV

Power2: Green : S0 Orange : S3 Orange Blinking : Enter S4

3D3V_S0LCDPOWER_S0

12

C70

C70 SC1U10V3KX-3GP

SC1U10V3KX-3GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

LCD / LEDs

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

16 58Thursday, October 13, 2005

of

E

of

SA

A

?3.9p need app PN

CHANGE TO - 3.9P -> 78.3R974.1F1

C742

1 2

SC12P50V2JN-LGP

12

4 4

X-32D768KHZ-38GPU

1 2

X7

41

2 3

C760

C760 SC12P50V2JN-LGP

SC12P50V2JN-LGP

CHANGE TO - 3.9P -> 78.3R974.1F1

SB

R488

20MR3-GP

R479

20MR3-GP

32K_X1 32K_X2

PCIE_RX0P_SB12 PCIE_RX0N_SB12 PCIE_RX1P_SB12 PCIE_RX1N_SB12

SBSRC_CLK3 SBSRC_CLK#3

PCIE_TX0P_SB12 PCIE_TX0N_SB12 PCIE_TX1P_SB12 PCIE_TX1N_SB12

MAIN SOURCE: 82.30001.031 EPSON

1D8V_S0

3 3

2 2

1 1

L23

1 2

MLB-201209-21-GP

A_RST# RSTDRV#_R

A_RST#

12

R297

R297 8K2R2J-3-GP

8K2R2J-3-GP

DY

PCIRST#

12

5V_S0

14

13

12 11

TSAHCT125PW-GP

7

3D3V_S5

1 2

DY

3D3V_S5

4 5

DY

R295

1 2

0R2J-GP

PCIE_PVDD

12

C728

C727

1D8V_S0 PCIE_VDDR

SC1U10V3KX-3GP

SC10U10V5ZY-1GP

L24

1 2

0R0603-PAD

INT_PIRQG# INT_PIRQE# INT_PIRQD#

INT_PIRQH#

3D3V_S0

U3D

U39A

147

3

TSLCX08MTCX-GP

U39B

147

6

TSLCX08MTCX-GP

Secondary PCI Bus reset signal.

A

2ND SOURCE: 82.30001.341 KDS

PCIE_VDDR

12

C725

SCD1U16V2ZY-2GP

C735

SC22U6D3V5MX-2GP

RP1

SRN10KJ-L3-GP

33R2J-2-GP

R298

1 2

33R2J-2-GP

R296

1 2

12

DY

1 2 3 4 5 6

R8

1 2

PCIRST# 3V to 5V level shift for HDD & CDROM

SB400 asserts PLTRST# to reset devices on the platform.

R307

1 2

0R2J-GP

PLT_RST#_R

PCI_RST#

C184

SCD1U16V2ZY-2GP

10 9

INT_PIRQC#INT_PIRQF#

8

INT_PIRQB#

7

INT_PIRQA#

RSTDRV#_5 24

10R2J-2-GP

12

C179

DY

SCD1U16V2ZY-2GP

3D3V_S0

LPC_RST# 13,34,37,49

ALLOW_LDTSTOP13 SB_CPUPWRGD6

BMREQ#13 LDT_RST#6

B

DY

A_RST#

C736 SCD01U16V2KX-3GPC736 SCD01U16V2KX-3GP

1 2

C733 SCD01U16V2KX-3GPC733 SCD01U16V2KX-3GP

1 2

C740 SCD01U16V2KX-3GPC740 SCD01U16V2KX-3GP

1 2

C737 SCD01U16V2KX-3GPC737 SCD01U16V2KX-3GP

1 2

R482 150R2F-1-GPR482 150R2F-1-GP

1 2

R473 150R2F-1-GPR473 150R2F-1-GP

1 2

R483 4K12R2F-GPR483 4K12R2F-GP

1 2

A11, A12 4K53 1% A21, A22 5K5 1% A23 4K12 1% PA_IXP400AC10.PDF

12

C233

DY

SCD1U16V2ZY-2GP

TP86TP86 TP85TP85

INT_PIRQE#25,27 INT_PIRQF#25,29 INT_PIRQG#27 INT_PIRQH#30

LDT_STP#6,13

PCIRST_BUF# 25,27,29,30

B

12

C183

SCD1U16V2ZY-2GP

TP92TP92 TP107TP107 TP18TP18 TP93TP93 TP91TP91

TP94TP94 TP11TP11 TP12TP12

TP14TP14

PCIE_PVDD

12

C734

RTC_AUX_S5

C

12

R83

R83 8K2R2J-3-GP

8K2R2J-3-GP

1 OF 4

U55A

AH8

A_RST#

L27

PCIE_RCLKP

M27

TX0P TX0N TX1P TX1N

PCIE_CALRP PCIE_CALRN

PCIE_CALI

SCD1U16V2ZY-2GP

SB_CPUSTP# SB_PCISTP# INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD# INT_PIRQE# INT_PIRQF# INT_PIRQG# INT_PIRQH#

32K_X1 32K_X2

SB_C29 SB_A28 H_NMI FWH_INIT# SB_D29 LPC_LDRQ0#

SB_B30 H_A20M# H_FERR#

H_DPRSLP#H_DPRSLP#

PCIE_RCLKN

M30

PCIE_TX0P

N30

PCIE_TX0N

K30

PCIE_TX1P

L30

PCIE_TX1N

H30

PCIE_TX2P

J30

PCIE_TX2N

F30

PCIE_TX3P

G30

PCIE_TX3N

M29

PCIE_RX0P

N29

PCIE_RX0N

M28

PCIE_RX1P

N28

PCIE_RX1N

J29

PCIE_RX2P

K29

PCIE_RX2N

J28

PCIE_RX3P

K28

PCIE_RX3N

G27

PCIE_CALRP

H27

PCIE_CALRN

G28

PCIE_CALI

R30

PCIE_PVDD

F26

PCIE_VDDR

R29

PCIE_VDDR

G26

PCIE_VDDR

P26

PCIE_VDDR

K26

PCIE_VDDR

L26

PCIE_VDDR

P28

PCIE_VDDR

N26

PCIE_VDDR

P27

PCIE_VDDR

H28

PCIE_VSS

F29

PCIE_VSS

H29

PCIE_VSS

H26

PCIE_VSS

F27

PCIE_VSS

G29

PCIE_VSS

L29

PCIE_VSS

J26

PCIE_VSS

L28

PCIE_VSS

J27

PCIE_VSS

N27

PCIE_VSS

M26

PCIE_VSS

K27

PCIE_VSS

P29

PCIE_VSS

P30

PCIE_VSS

AJ8

CPU_STP#/DPSLP_3V#

AK7

DPSLP_OD#/GPIO37

AG5

INTA#

AH5

INTB#

AJ5

INTC#

AH6

INTD#

AJ6

INTE#/GPIO33

AK6

INTF#/GPIO34

AG7

INTG#/GPIO35

AH7

INTH#/GPIO36

B2

X1

B1

X2

C29

CPU_PG

A28

INTR/LINT0

C28

NMI/LINT1

B29

INIT#

D29

SMI#

E4

SLP#/LDT_STP#

B30

IGNNE#

F28

A20M#

E28

FERR#

E29

STPCLK#/ALLOW_LDTSTP

D25

LDT_PG/SSMUXSEL/GPIO0

E27

DPRSLPVR

D27

BMREQ#

D28

LDT_RST#

R510

12

1KR2J-1-GP

PCI EXPRESS INTERFACE

XTAL

CPU

RTC_AUX_S5_1

41235

RTC1

MLX-CON3-9-GP

20.D0198.103

C

PCI CLKS

PCI INTERFACELPCRTC

REQ3#/PDMA_REQ0#

REQ4#/PLL_BP33/PDMA_REQ1#

GNT3#/PLL_BP66/PDMA_GNT0# GNT4#/PLL_BP50/PDMA_GNT1#

RTC_IRQ#/ACPWR_STRAP

12

EC71

EC71 SC470P50V2KX

SC470P50V2KX

1 OF 4

PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5 PCICLK6 PCICLK7 PCICLK8 PCICLK9

PCICLK_FB

PCIRST# AD0/ROMA18 AD1/ROMA17 AD2/ROMA16 AD3/ROMA15 AD4/ROMA14 AD5/ROMA13 AD6/ROMA12 AD7/ROMA11

AD8/ROMA9

AD9/ROMA8 AD10/ROMA7 AD11/ROMA6 AD12/ROMA5 AD13/ROMA4 AD14/ROMA3 AD15/ROMA2 AD16/ROMD0 AD17/ROMD1 AD18/ROMD2 AD19/ROMD3 AD20/ROMD4 AD21/ROMD5 AD22/ROMD6 AD23/ROMD7

AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

CBE0#/ROMA10

CBE1#/ROMA1

CBE2#/ROMWE#

CBE3#

FRAME#

DEVSEL#/ROMA0

IRDY#

TRDY#/ROMOE#

PAR/ROMA19

STOP# PERR# SERR# REQ0# REQ1# REQ2#

REQ5#/GPIO13 REQ6#/GPIO31

GNT0# GNT1# GNT2#

GNT5#/GPIO14 GNT6#/GPIO32

CLKRUN#

LOCK#

LAD0 LAD1 LAD2 LAD3

LFRAME#

LDRQ0# LDRQ1#

SERIRQ RTCCLK

VBAT

RTC_GND

L4

PCI_CLK1_R

L3

PCI_CLK2_R

L2

PCI_CLK3_R

L1

PCI_CLK4_R

M4

PCI_CLK5_R

M3

PCI_CLK6_R

M2

PCLK_R5C833_R

M1 N4

PCI_CLK9_R

N3

PCI_CLK9_FB

N2 AJ7

W3 Y2 W4 Y3 V1 Y4 V2 W2 AA4 V4 AA3 U1 AA2 U2 AA1 U3 T4 AC1 R2 AD4 R3 AD3 R4 AD2 P2 AE3 P3 AE2 P4 AF2 N1 AF1 V3 AB4 AC2 AE4 T3 AC4 AC3 T2 U4 T1 AB2 AB3 AF4 AF3 AG2 AG3 AH1 AH2 AH3 AJ2 AK2 AJ3 AK3 AG4 AH4 AJ4 AG1 AB1

AG25 AH25 AJ25 AH24 AG24 AH26 AG26

AK27 C2

F3 A2

A1

PCIRST# PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31

PCI_REQ#3PCI_REQ#3

PCI_REQ#4

PCI_REQ#5 PCI_REQ#6

PCI_GNT#3 PCI_GNT#4 PCI_GNT#5 PCI_GNT#6

LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3

LPC_LDRQ1#

P_SERIRQ 27,34,37

RTC_CLK 21 AUTO_ON# 21

VBAT

12

C761

SCD1U16V2ZY-2GP

D

RN102

1 2 3 4 5 4 5 3 2 1

R459

1 2

22R2J-2-GP

PCI_AD[31..0] 21,25,27,29,30

3D3V_S0

10

12345 6

3D3V_S0

TP10TP10

PCI_LOCK#

LPC_LAD[0..3] 34,37

LPC_LFRAME# 21,34,37 LPC_LDRQ0# 37

3D3V_AUX_S5

3

12

C762

SC1U10V3KX-3GP

RTC_AUX_S5

D

32K suspend clock output

PM_SLP_S3#20,34,38,39,45,56 RTC_CLK21

SRN22J-2-GP

8 7 6

6 7 8

CLK33_CBUS CLK33_LAN CLK33_MINI CLK33_KBC CLK33_SIO PCLK_R5C832 CLK33_LPCROM

RN98 SRN22J-2-GPRN98 SRN22J-2-GP

PCI_CLK8 21

1 2

DY

789

RN15

RN15 SRN10KJ-L1-GP-U

SRN10KJ-L1-GP-U

Close to chip

U58

U58 BAT54C-1-GP

BAT54C-1-GP

1 2

R4518K2R2J-3-GP R4518K2R2J-3-GP

12

3D3V_S0

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

5V_S5

U33A

147

1 2

PCLK_R5C832 CLK33_CBUS CLK33_LAN CLK33_MINI CLK33_KBC

C724SC100P50V2JN-UDYC724SC100P50V2JN-U

CLK33_SIO CLK33_LPCROM

3D3V_S0

PCI_GNT#5 PCI_GNT#6

RN13

SRN10KJ-L1-GP-U

1 2 3 4 5 6

ATI-SB450 (1 of 5) PCI, PCIE

10 9 8 7

1

LPC_LAD0

2

LPC_LAD3

3

LPC_LAD2

4

LPC_LAD1

5 6

Bolsena-E SA

1 2

3

TSLCX08MTCX-GP

12

R92

R92 DUMMY-R2

DUMMY-R2

12

R93

R93 DUMMY-R2

DUMMY-R2

RN12

SRN10KJ-L1-GP-U

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

E

R280

10R2J-2-GP

PCLK_R5C832 21,27 CLK33_CBUS 25 CLK33_LAN 21,30 CLK33_MINI 21,29 CLK33_KBC 21,34 CLK33_SIO 21,37 CLK33_LPCROM 21

PCB-Ver

12

R430

R430 DUMMY-R2

DUMMY-R2

12

R429

R429 DUMMY-R2

DUMMY-R2

PCI_CBE#0 25,27,29,30 PCI_CBE#1 25,27,29,30 PCI_CBE#2 25,27,29,30 PCI_CBE#3 25,27,29,30 PCI_FRAME# 25,27,29,30 PCI_DEVSEL# 25,27,29,30 PCI_IRDY# 25,27,29,30 PCI_TRDY# 25,27,29,30 PCI_PAR 25,27,29,30 PCI_STOP# 25,27,29,30 PCI_PERR# 25,27,29,30 PCI_SERR# 25,27,29,30

PCI_REQ#0 29 PCI_REQ#1 25 PCI_REQ#2 30 PCI_REQ#3 27

PCI_GNT#0 29 PCI_GNT#1 25 PCI_GNT#2 30 PCI_GNT#3 27

PM_CLKRUN# 25,27,29,30,34,37

10

LPC_LDRQ1#

9

LPC_LDRQ0#

8

P_SERIRQ

7

3D3V_S0

17 58Thursday, October 13, 2005

of

E

of

CLK32_G791 22

A

U55B

AK22

AJ22

AK21

AJ21

AK19

AJ19

AK18

AJ18

AK14

AJ14

AK13

AJ13

AK11

AJ11

AK10

AJ10 AJ15 AJ16

AK16

AK8

AH15 AH16

AG10 AG14 AH12 AG12 AG18 AG21 AH18 AG20

AG9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22

AH9 AG11 AG15 AG17 AG19 AG22 AG23

AF9 AH17 AH23 AH13 AH20

AK9

AJ12 AK17 AK23

U55B

SATA_TX0+ SATA_TX0-

SATA_RX0SATA_RX0+

SATA_TX1+ SATA_TX1-

SATA_RX1SATA_RX1+

SATA_TX2+ SATA_TX2-

SATA_RX2SATA_RX2+

SATA_TX3+ SATA_TX3-

SATA_RX3SATA_RX3+

SATA_CAL SATA_X1

SATA_X2 SATA_ACT# PLLVDD_SATA

XTLVDD_SATA AVDD_SATA

AVDD_SATA AVDD_SATA AVDD_SATA AVDD_SATA AVDD_SATA AVDD_SATA AVDD_SATA

AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA

4 4

SATA_TXP024 SATA_TXN024

SATA_RXN024 SATA_RXP024

C704 SCD01U50V3KX-4GPC704 SCD01U50V3KX-4GP

1 2

C703 SCD01U50V3KX-4GPC703 SCD01U50V3KX-4GP

1 2

C630 SCD01U50V3KX-4GPC630 SCD01U50V3KX-4GP

1 2

C629 SCD01U50V3KX-4GPC629 SCD01U50V3KX-4GP

1 2

SATA_TP0 SATA_TN0

SATA_RN0

SATA_RP0

Close to SouthBridge

R431

1 2

1KR2F-3-GP

C700

1 2

SCD01U50V3KX-4GP

DY

3 3

SATA_X2

12

R432

10MR2J-L-GP

SATA_X1

DY

1D8V_SX_S0

1 2

X6

XTAL-25MHZ-70GP

1 2

SATA_LED#16

1D8V_SP_S0

C701

C701 SC27P50V2JN-2-GP

SC27P50V2JN-2-GP

C702

C702 SC27P50V2JN-2-GP

SC27P50V2JN-2-GP

Dummy when use IDE

R433

R433 0R2J-GP

0R2J-GP

1D8V_SATA_S0

12

R102

R102 0R2J-GP

0R2J-GP

2 2

SATA_X1

12

Dummy when use SATA

1D8V_SATA_S0

SATA_X1 SATA_X2

B

SERIAL ATA

PRIMARY ATA 66/100SECONDARY ATA 66/100

SERIAL ATA

PRIMARY ATA 66/100SECONDARY ATA 66/100

SERIAL ATA POWER

2 OF 4

PIDE_IORDY

PIDE_IRQ

PIDE_A0 PIDE_A1 PIDE_A2

PIDE_DACK#

PIDE_DRQ PIDE_IOR# PIDE_IOW# PIDE_CS1# PIDE_CS3#

PIDE_D0 PIDE_D1 PIDE_D2 PIDE_D3 PIDE_D4 PIDE_D5 PIDE_D6 PIDE_D7 PIDE_D8

PIDE_D9 PIDE_D10 PIDE_D11 PIDE_D12 PIDE_D13 PIDE_D14 PIDE_D15

SIDE_IORDY

SIDE_IRQ

SIDE_A0

SIDE_A1

SIDE_A2

SIDE_DACK#

SIDE_DRQ SIDE_IOR# SIDE_IOW# SIDE_CS1# SIDE_CS3#

SIDE_D0/GPIO15 SIDE_D1/GPIO16 SIDE_D2/GPIO17 SIDE_D3/GPIO18 SIDE_D4/GPIO19 SIDE_D5/GPIO20 SIDE_D6/GPIO21 SIDE_D7/GPIO22 SIDE_D8/GPIO23

SIDE_D9/GPIO24 SIDE_D10/GPIO25 SIDE_D11/GPIO26 SIDE_D12/GPIO27 SIDE_D13/GPIO28 SIDE_D14/GPIO29 SIDE_D15/GPIO30

AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA

AD30 AE28 AD27 AC27 AD28 AD29 AE27 AE30 AE29 AC28 AC29

AF29 AF27 AG29 AH30 AH28 AK29 AK28 AH27 AG27 AJ28 AJ29 AH29 AG28 AG30 AF30 AF28

V29 T27 T28 U29 T29 V30 U28 W29 W30 R27 R28

V28 W28 Y30 AA30 Y28 AA28 AB28 AB27 AB29 AA27 Y27 AA29 W27 Y29 V27 U27

AG13 AH22 AK12 AH11 AJ17 AH14 AH19 AJ20 AH21 AJ9 AG16 AH10 AJ23 AK15 AK20

PIDE_D0 PIDE_D1 PIDE_D2 PIDE_D3 PIDE_D4 PIDE_D5 PIDE_D6 PIDE_D7 PIDE_D8 PIDE_D9 PIDE_D10 PIDE_D11 PIDE_D12 PIDE_D13 PIDE_D14 PIDE_D15

SIDE_D0 SIDE_D1 SIDE_D2 SIDE_D3 SIDE_D4 SIDE_D5 SIDE_D6 SIDE_D7 SIDE_D8 SIDE_D9 SIDE_D10 SIDE_D11 SIDE_D12 SIDE_D13 SIDE_D14 SIDE_D15

C

PIDE_IORDY 24 PIDE_IRQ14 24 PIDE_A0 24 PIDE_A1 24 PIDE_A2 24

PIDE_DREQ 24 PIDE_IOR# 24 PIDE_IOW# 24 PIDE_CS#0 24 PIDE_CS#1 24

PIDE_D[15..0] 24

SIDE_IORDY 24 SIDE_IRQ15 24 SIDE_A0 24 SIDE_A1 24 SIDE_A2 24 SIDE_DACK# 24 SIDE_DREQ 24 SIDE_IOR# 24 SIDE_IOW# 24 SIDE_CS#0 24 SIDE_CS#1 24

SIDE_D[15..0] 24

R361

12

also strap function

0R0402-PAD

PIDE_DACK# 24

PDACK# 21

D

E

1D8V_S0 1D8V_SATA_S0

R105

1 1

1 2

0R5J-5-GP

12

A

12

C127

SC10U10V5ZY-1GP

12

C155

SCD1U50V3ZY-GP

12

C128

C160

SCD1U50V3ZY-GP

12

C129

SCD1U50V3ZY-GP

L4

1 2

0R3J-3-GP

Capacitor PLACE NEAR THE ACCORDED BALLS

B

12

C157

C157 SC2D2U16V5ZY-GP

SC2D2U16V5ZY-GP

1D8V_S01D8V_S0 1D8V_SX_S01D8V_SP_S0

L5

1 2

0R3J-3-GP

Capacitor PLACE NEAR THE ACCORDED BALLS

12

Dummy when use IDE

C159

C159 SC2D2U16V5ZY-GP

SC2D2U16V5ZY-GP

C

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

ATI-SB400 (2 of 5) IDE

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

D

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

SA

18 58Thursday, October 13, 2005

of

E

of

SA

A

B

C

D

E

1D8V_S0

12

C178

DY

4 4

SC10U10V5ZY-1GP

12

C165

DY

SCD1U16V2ZY-2GP

3D3V_SB_S0

12

C721

3 3

SC10U10V5ZY-1GP

12

C161

DY

SCD1U16V2ZY-2GP

3D3V_SB_S5

12

C180

DY

2 2

SC10U10V5ZY-1GP

1D8V_S5 1D8V_S5

12

C777

SC10U10V5ZY-1GP

DY

1 1

C204

DY

SC10U10V5ZY-1GP

12

C181

SCD1U16V2ZY-2GP

12

C722

SCD1U16V2ZY-2GP

12

C726

SCD1U16V2ZY-2GP

12

C238

DY

SCD1U16V2ZY-2GP

12

C778

DY

SCD1U16V2ZY-2GP

12

C172

SCD1U16V2ZY-2GP

12

C780

SCD1U16V2ZY-2GP

12

C143

SCD1U16V2ZY-2GP

12

C144

DY

SCD1U16V2ZY-2GP

12

C240

SCD1U16V2ZY-2GP

12

C225

SCD1U16V2ZY-2GP

A

12

C158

DY

SCD1U16V2ZY-2GP

12

C203

DY

SCD1U16V2ZY-2GP

12

C154

SCD1U16V2ZY-2GP

12

C705

SCD1U16V2ZY-2GP

12

C239

DY

SCD1U16V2ZY-2GP

12

C223

DY

SCD1U16V2ZY-2GP

12

C719

DY

SCD1U16V2ZY-2GP

C182

SCD1U16V2ZY-2GP

12

C202

SCD1U16V2ZY-2GP

12

C766

SCD1U16V2ZY-2GP

C222

SCD1U16V2ZY-2GP

12

C230

SCD1U16V2ZY-2GP

12

C738

DY

SCD1U16V2ZY-2GP

12

C156

DY

SCD1U16V2ZY-2GP

12

C169

SCD1U16V2ZY-2GP

12

C145

DY

SCD1U16V2ZY-2GP

0R0805-PAD

12

C221

SCD1U16V2ZY-2GP

12

C228

DY

SCD1U16V2ZY-2GP

12

C171

SCD1U16V2ZY-2GP

12

C170

SCD1U16V2ZY-2GP

R450

0R0805-PAD

12

C177

DY

SCD1U16V2ZY-2GP

12

C743

SCD1U16V2ZY-2GP

R114

12

C226

SCD1U16V2ZY-2GP

3D3V_S0

12

C699

SCD1U16V2ZY-2GP

3D3V_S5

12

C231

SCD1U16V2ZY-2GP

Vf = 0.38v (@1mA) 1v (@40mA)

12

C173

C698

DY

SCD1U16V2ZY-2GP

1D8V_S5

D33

1 2

RB751V-40-1-GP

B

12

C232

SCD1U16V2ZY-2GP

3D3V_S5

1D8V_S0

1 2

MLB-201209-21-GP

5V_S0

12

D30

RB751V-40-1-GP

3D3V_S0

D31

1 2

RB751V-40-1-GP

L26

C779

SC10U10V5ZY-1GP

DY

V5_VREF MIN 4.5 NORMAL 5.0 MAX 5.5

R440

1 2

1D8VAVDDCK_S0

12

C773

1KR2J-1-GP

1D8V_S5

12

C765

SC1U10V3KX-3GP

SCD1U16V2ZY-2GP

12

C717

SC1U10V3KX-3GP

1D2V_S0

12

V5_VREF

12

C142

3D3V_SB_S0

1D8V_S0

3D3V_SB_S5

1D8V_S5

R489

1 2

0R0402-PAD

SCD1U16V2ZY-2GP

C

AA5 AK4

AF25

AB5

AA26

AD5

AD26

AE1 AE5

AF24 AE26

AC30

AK1 AK26 AK30

M12

W12

M13

W13

M18

W18

M19

W19

CPU_1D2V

V5_VREF

AG6

12

C750SCD1U16V2ZY-2GP C750SCD1U16V2ZY-2GP

D30 A30

E24 E25

U26 V26 Y26

AF6 U30

AF7

N12 V12

N13 V13

N18 V18

N19 V19

E10 E13 E14 E16 E17 E20 E21

C30

A24 B24

B28 E30 E23

E11

J5 K1 K5 N5 R1 P5 Y1 U5

V5

A3 A7 E6 E7 E1 F5

E9

A4 A8

C1 E5

G5

F1 H5 E8

U55C

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

S5_3.3V S5_3.3V S5_3.3V S5_3.3V S5_3.3V S5_3.3V

S5_1.8V S5_1.8V USB_PHY_1.8V USB_PHY_1.8V USB_PHY_1.8V USB_PHY_1.8V S5_1.8V S5_1.8V

CPU_PWR V5_VREF AVDDCK

AVSSCK VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

3 OF 4

D

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

E12 E15 E18 E19 E22 K4 J1 J4 R5 T5 F4 P1 L5 M5 W1 AK25 W5 AJ24 R26 E26 Y5 T26 AF5 T30 AC5 W26 AG8 AF8 AB26 AK5 AC26 AD1 AF23 AF26 A29 AB30 AJ1 AJ30 P12 R12 T12 U12 P13 R13 T13 U13 M14 N14 P14 R14 T14 U14 V14 W14 M15 N15 P15 R15 T15 U15 V15 W15 M16 N16 P16 R16 T16 U16 V16 W16 M17 N17 P17 R17 T17 U17 V17 W17 P18 R18 T18 U18 P19 R19 T19 U19

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

ATI-SB400 (3 of 5) POWER

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

19 58Thursday, October 13, 2005

of

E

of

SA

A

3D3V_S5

3D3V_S0

DY

12

123456

4 4

3D3V_S5

3 3

3D3V_S0

RN20

SRN10KJ-6-GP

2 2

1 1

10

123

SRN4K7J-9-GP-U1

SRN4K7J-9-GP-U1 RN18

RN18

789

678

4 5

DDC1_SCL DDC1_SDA

DDC2_SCL DDC2_SDA

PM_SLP_S3#_SB

PME#_SB

PCIE_WAKE#

GPM6# PM_SLP_S5# PM_PWRBTN# SYS_REST

PM_THRM#

A

12

R50510KR2J-2-GP R50510KR2J-2-GP

R12710KR2J-2-GP R12710KR2J-2-GP

12

R87 10KR2J-2-GP

ECSCI#_KBC34 ECSMI#_KBC34 ECSWI#34

SMBC_SB3,8 SMBD_SB3,8

3D3V_S5

RN107 SRN10KJ-5-GPRN107 SRN10KJ-5-GP

4

12

R502 10KR2J-2-GPR502 10KR2J-2-GP R501 10KR2J-2-GPR501 10KR2J-2-GP

1

2 3

LUSB2#

S3_STATE

PM_SUS_STAT# KA20GATE

R86 10KR2J-2-GP

KBRCIN# ECSCI#_KBC ECSMI#_KBC

RI#

TP13TP13

3D3V_S5

AZ_BITCLK32

ACZ_BITCLK_MDC23

ACZ_DOUT32

ACZ_DOUT_MDC23

ACZ_SYNC32

ACZ_SYNC_MDC23

R463 10KR2J-2-GP

1 2

DY

ACZ_SDATAIN032 ACZ_SDATAIN123

R457 10KR2J-2-GP

1 2

DY

SPDIF_OUT_STRAP21

ACZ_RST#32

ACZ_RST#_MDC23

123

ECSWI#

SB_OSC_CLK3

R131 10KR2J-2-GPR131 10KR2J-2-GP

1 2

R130 10KR2J-2-GPR130 10KR2J-2-GP

1 2

KBC_SLP_WAKE34

SPKR_SB32

SMBC_SB SMBD_SB

R469 33R2J-2-GPR469 33R2J-2-GP R466 22R2J-2-GPR466 22R2J-2-GP

R477 47R2J-L2-GPR477 47R2J-L2-GP R468 33R2J-2-GPR468 33R2J-2-GP

R467 33R2J-2-GPR467 33R2J-2-GP R462 33R2J-2-GPR462 33R2J-2-GP

R478 33R2J-2-GPR478 33R2J-2-GP R470 33R2J-2-GPR470 33R2J-2-GP

3D3V_S0

4

1

2 3

B

678

RN19

RN19 SRN10KJ-6-GP

SRN10KJ-6-GP

4 5

KBC_SLP_WAKE GPIO1 GPIO6

PM_THRM#22

PME#_SB30

PM_SLP_S5#34,45 PM_PWRBTN#34 SB_PWRGD39 PM_SUS_STAT#34

KA20GATE34 KBRCIN#34

R128 0R0402-PADR128 0R0402-PAD

1 2

R506 0R0402-PADR506 0R0402-PAD

1 2

R500 0R2J-GP

1 2

DY

RSMRST#_KBC34,44

TP87TP87

VRM_PWRGD39,41

R507 33R2J-2-GPR507 33R2J-2-GP

1 2

R508 33R2J-2-GPR508 33R2J-2-GP

1 2

1 2 1 2

R464 10KR2J-2-GP

1 2

DY

AC97_DOUT21

R115

3D3V_S5

1 2 1 2

RN39

RN39 SRN2K2J-1-GP

SRN2K2J-1-GP

SMBC_SB SMBD_SB

B

GPM6#

PM_SLP_S3#_SB

R476 10KR2J-2-GP

R476 10KR2J-2-GP R465 10KR2J-2-GP

R465 10KR2J-2-GP

DY

DY DY

DY

R472

R116 10KR2J-2-GPR116 10KR2J-2-GP

R471 10KR2J-2-GP

1 2

DY

RI#

R480 10KR2J-2-GPR480 10KR2J-2-GP

1 2

R481 10KR2J-2-GPR481 10KR2J-2-GP

1 2

LUSB2#

S3_STATE SYS_REST PCIE_WAKE#

SIO_CLK_SB

AGP_STP#

AGP_BUSY#

SMBC_SB_1 SMBD_SB_1 DDC1_SCL DDC1_SDA DDC2_SCL DDC2_SDA

AZ_BITCLK_ICH

ACZ_DOUT_ICH

AZ_SYNC_ICH

4K7R2J-2-GP

12

4K7R2J-2-GP

12

1 2

AZ_RST#_ICH

ECSCI# ECSMI#

GPIO1 GPIO6

C6 D5 C4 D3 B4 E3 B3 C3 D4 F2

E2 AJ26 AJ27

D6

C5

A25

D8

D7

D2

D1

A23 B23

AK24

B25 C25 C23 D24 D23 A27 C24 A26 B26 B27 C26 C27 D26

J2

K3

J3

K2

G1 G2

H4

G3 G4

H1

H3

H2

PM_SLP_S3#_SB

C

U55D

TALERT#/TEMP_ALERT#/GPIO10 BLINK/AZ_SDIN3/GPM6# PCI_PME#/GEVENT4# RI#/EXTEVNT0# SLP_S3# SLP_S5# PWR_BTN# PWR_GOOD SUS_STAT# TEST1 TEST0 GA20IN KBRST# SMBALERT#/THRMTRIP#/GEVENT2# LPC_PME#/GEVENT3# LPC_SMI#/EXTEVNT1# S3_STATE/GEVENT5# SYS_RESET#/GPM7# WAKE#/GEVENT8#

RSMRST# 14M_X1/OSC

14M_X2 SIO_CLK ROM_CS#/GPIO1

GHI#/GPIO6 VGATE/GPIO7 GPIO4 GPIO5 FANOUT0/GPIO3 SPKR/GPIO2 SCL0/GPOC0# SDA0/GPOC1# DDC1_SCL/GPIO9 DDC1_SDA/GPIO8 DDC2_SCL/GPIO11 DDC2_SDA/GPIO12

AZ_BITCLK 48M_AZ AZ_SDOUT AZ_SYNC

AC_BITCLK AC_SDOUT ACZ_SDIN0 ACZ_SDIN1 ACZ_SDIN2 AC_SYNC AC_RST# SPDIF_OUT

AC97

3D3V_S5

4 5

CLK/RSTGPIO

(NTO USED)

147

C

USB_OC2#/FANOUT1/LLB#/GPM2#

ACPI/WAKE UP EVENTS

USB INTERFACE

U30B

6

TSLCX08MTCX-GP

PM_SLP_S3# 17,34,38,39,45,56

4 OF 4

48M_X1/USBCLK

48M_X2

USB_RCOMP

USB_VREFOUT

USB_ATEST1

USB_ATEST0 USB_OC0#/GPM0# USB_OC1#/GPM1# USB_OC4#/GPM4#

USB_OC3#/GPM3#

USB_OC5#/AZ_RST#/GPM5#

USB_OC6#/GEVENT6# USB_OC7#/GEVENT7#

USB_HSDP7+

USB_HSDM7-

USB_HSDP6+

USB_HSDM6-

USB_HSDP5+

USB_HSDM5-

USB_HSDP4+

USB_HSDM4-

USB_HSDP3+

USB_HSDM3-

USB_HSDP2+

USB_HSDM2-

USB_HSDP1+

USB_HSDM1-

USB_HSDP0+

USB_HSDM0-

AVDDTX_0 AVDDTX_1 AVDDTX_2 AVDDTX_3

AVDDRX_0 AVDDRX_1 AVDDRX_2 AVDDRX_3

AVDDC

AVSSC

AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB

USB PWR

AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB

B15 D16

C16 D15 B8 C8 B6 C7 B7 A6 B5 A5

A11 B11

A10 B10

A14 B14

A13 B13

A18 B18

A17 B17

A21 B21

A20 B20

C21 C18 D13 D10

D20 D17 C14 C11

A16 B16 A9

A12 A19 A22 B9 B12 B19 B22 C9 C10 C12 C13 C17 C19 C20 C22 D9 D11 D12 D14 D18 D19 D21 D22

A15 C15

D

USB_PCOMP USB_VREFOUT USB_TE1 USB_TE0

USB_OC#4 USB_OC#2 USB_OC#3 AZ_RST#_ICH USB_OC#6

LUSB1# USB_PP7

USB_PN7 USB_PP6

USB_PN6 USB_PP5

USB_PN5 USB_PP4

USB_PN4 USB_PP3

USB_PN3

D

R504

1 2

DY

R499

1 2

0R0402-PAD

USB_PP4 23 USB_PN4 23

USB_PP3 23 USB_PN3 23

USB_PP2 23 USB_PN2 23

USB_PP1 23 USB_PN1 23

USB_PP0 23 USB_PN0 23

AVDD_USB

3D3V_AVDDC

E

CLK48_USB 3

0R2J-GP

R503

1 2

11K8R3F-GP

TP17TP17 TP16TP16 TP15TP15

USB_OC#01 23

USB_OC#2 23 USB_OC#3 23

ECSWI#

TP19TP19 TP103TP103

TP104TP104 TP101TP101

TP102TP102

TP105TP105 TP106TP106

USB_OC#4 USB_OC#01

USB_OC#2 USB_OC#3

3D3V_S5

RP2

1 2 3 4 5 6

SRN10KJ-L3-GP

BlueTooth

3D3V_S5

L7

1 2

0R0603-PAD

1 2

MLB-201209-21-GP

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

12

C265

SC10U10V5ZY-1GP

DY

12

C224

C224 SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

DY

L25

3D3V_AVDDC

12

C772

C772 SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

DY

ATI-SB450 (4 of 5) USB GPIO

Bolsena-E

12

C236

12

C227

12

C764

C763

SC1U10V3KX-3GP

SCD1U16V2ZY-2GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

20 58Thursday, October 13, 2005

E

10

USB_OC#6

9

LUSB1#

8 7

AVDD_USB

12

C229

SCD1U16V2ZY-2GP

of

3D3V_S5

12

C241

SCD1U16V2ZY-2GP

SA

A

10KR2J-2-GP

LPC_LFRAME#17,34,37 AUTO_ON#17 AC97_DOUT20 RTC_CLK17

4 4

SPDIF_OUT_STRAP20 CLK33_LAN17,30 CLK33_MINI17,29 CLK33_KBC17,34 CLK33_SIO17,37 CLK33_LPCROM17 PCLK_R5C83217,27 PCI_CLK817

R85

3D3V_S0

DY

12

R84

R84 10KR2J-2-GP

10KR2J-2-GP

3D3V_S5

RN106

SRN10KJ-5-GP

B

4

RN103

1

2 3

1

2 3

SRN10KJ-5-GP

RN100

SRN10KJ-5-GP

3D3V_S0

4

1

2 3

C

4

1

2 3

RN101

SRN10KJ-5-GP

RN97

SRN10KJ-5-GP

D

3D3V_S03D3V_S0

4

12

R458

R458 10KR2J-2-GP

10KR2J-2-GP

1

2 3

Place these R close to SouthBridge if possible

E

3D3V_S0

12

DY

12

PCI_CLK3

USB PHY PWRDOWN DISABLE

DEFAULT

USB PHY PWRDOWN ENABLE

R443

R443 10KR2J-2-GP

10KR2J-2-GP

R444

R444 10KR2J-2-GP

10KR2J-2-GP

PCI_CLK4

(CLK33_KBC)(CLK33_LAN) (CLK33_MINI) (CLK33_SIO) (CLK33_LPCROM)

PCIE_CM_SET

4

RN16

1

2 3

SRN10KJ-5-GP

HIGH

DEFAULT

LOW

RN14

SRN10KJ-5-GP

USB INT PLL48

USB EXT. 48MHZ

4

1

2 3

PCI_CLK6

CPU I/F=K8

DEFAULT

CPU I/F=P4

REQUIRED SYSTEM STRAPS

3 3

PDACK#18 PCI_AD3117,25,27,29,30 PCI_AD3017,25,27,29,30 PCI_AD2917,25,27,29,30 PCI_AD2817,25,27,29,30

2 2

PCI_AD2717,25,27,29,30 PCI_AD2617,25,27,29,30 PCI_AD2517,25,27,29,30 PCI_AD2417,25,27,29,30 PCI_AD2317,25,27,29,30

STRAP HIGH

STRAP LOW

LFRAME#

Thermal Trip is not enable as default

Optional

Thermal Trip is enable as default

Optional

10KR2J-2-GP

DEBUG STRAPS

ACPWRON PCI_CLK5SPDIF_OUT

MANUAL PWR ON

DEFAULT

AUTO PWR ON

3D3V_S0

12

R360

DY

12

RN95

R362

R362 1KR2J-1-GP

1KR2J-1-GP

AC_SDOUT RTC_CLK

USE DEBUG STRAPS

IGNORE DEBUG STRAPS

DEFAULT

3D3V_S0

4

1

2 3

1

2 3

SRN10KJ-5-GP

RN17

SRN10KJ-5-GP

INTERNAL RTC

DEFAULT

EXTENNAL RTC (NOT SUPPORTED W/IT8712)

PCI_CLK2

SIO 24MHz

SIO 48MHz

DEFAULT Use External only

48MHZ

-Crytsal Pad

48MHZClock Input Buffer

DEFAULT

PCI_CLK7

(PCLK_R5C832)

ROM TYPE H,H=PCI (X Bus) ROM

H,L=LPC ROM I

L,H=LPC ROM II

L,L=Firmware Hub ROM

PCI_CLK8

PCI_AD31 PCI_AD30

STRAP

1 1

HIGH

STRAP LOW

USE LONG RESET

DEFAULT

USE SHORT RESET

RESERVED

RESERVED RESERVED RESERVED

PCI_AD29

PCI_AD28

PCI_AD27

BYPASS PCI PLL

USE PCI PLL

DEFAULT DEFAULT

PCI_AD26

BYPASS ACPI BCLK

USE ACPI BCLK

PCI_AD25 PCI_AD24PDACK#

BYPASS IDE PLL

USE IDE PLL

DEFAULT

EEPROM PCIE STRAPS

USE DEFAULT PCIE STRAPS

DEFAULT

PCI_AD23

RESERVEDUSE

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

ATI-SB400 STRAPPING(5 of 5)

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

21 58Thursday, October 13, 2005

of

SA

*Layout* 15 mil

12

C244

DY

SCD1U25V3ZY-3GP

5V_S0

R150

1 2

200R3-GP

12

C290

C290 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

Setting T8 as 100 Degree

V_DEGREE =(((Degree-72)*0.02)+0.34)*VCC

HW thermal shut down tempature setting 95 degree . Put Near CPU .

FAN1_VCC

C243

C243 SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

5V_G792_S0

R146

R146 10KR2J-2-GP

10KR2J-2-GP

V_DEGREE

R145

R145 49K9R2F-L-GP

49K9R2F-L-GP

DY

SB

D11

S1N4148-U2

1 2

*Layout* 30 mil

5V_S0

12

C245

C246

RUNPWROK39

SC4D7U10V5ZY-3GP

ALERT#

12

DY

C252

C252 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

12

C237

SCD1U25V3ZY-3GP

12

R121

1 2

0R2J-GP

DY

1 2

R144 0R2J-GPR144 0R2J-GP

R149

R149 10KR2J-2-GP

10KR2J-2-GP

5V_S0

12

R122

R122 10KR2J-2-GP

10KR2J-2-GP

PR_HW_SDN#

G792_RST#

PM_THRM# 20

6

20

7 9

11

ALERT#

15 13

3 2

DXP1:108 Degree DXP2:H/W Setting DXP3:88 Degree

U11

VCC DVCC

DXP1 DXP2 DXP3

ALERT# THERM# THERM_SET RESET#

G792SFUF-GP

FAN1

FG1

CLK SDA SCL

DGND DGND

SGND1 SGND2 SGND3

5V_S0

C185

G8

1 2

12

R117

R117 10KR2J-2-GP

10KR2J-2-GP

12

C275

C275 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

12

C253

C253 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

USE 0R2 63.R0034.1D1 WHEN UMA

GAP-CLOSE

U12

1

SET

2

GND OUT#3HYST

G709T1UF-GP

VCC

FAN1

4 1

2 3 5

MLX-CON3-9-GP

20.D0198.103

ME : 20.D0198.103 2nd:20.F0714.003

12

C274

C274 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

5V_AUX_S5

12

R161

R161 150R2F-1-GP

150R2F-1-GP

5 4

THERMDP 6

To CPU

THERMDN 6

By Sourcer requset: Main souce 74.00709.07F Second souce

74.00710.03P

74.06509.07F

74.06510.A7P

12

C322

C322 SC4D7U10V5ZY-3GP

SC4D7U10V5ZY-3GP

THERM_SYS_DP

THERM_SYS_DN

VGA_LOCAL_DP 50 VGA_LOCAL_DN 50

1

3

Q27

Q27 MMBT3904-U1

MMBT3904-U1

2

12

C308

SC470P50V2KX

3904 on system (Thermal Sensor)

Dummy when use UMA

*Layout* 15 mil

FAN1_VCC

FAN1_FB

SC100P50V2JN-3GP

1 4 14 16 18 19

NC

5 17

8 10 12

CLK32_G791 17

SMBD_G792 34

SMBC_G792 34

G7

1 2

GAP-CLOSE

Dummy when G792 enhanced T8 function

T8_RSET:27K SET TO 80°C T8_RSET:20K SET TO 90°C T8_RSET:15K SET TO 100°C

T8_SET 5V_G709_AUX_S5

12

R160

R160 20KR2F-L-GP

20KR2F-L-GP

3D3V_AUX_S5

3

D36

R513

R513 10KR2J-2-GP

10KR2J-2-GP

D36

1

BAT54PT-GP

12

(dummy, KBC already delay)

2

C785

C785 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

DY

Put under CPU Socket

S5_ENABLE34

PURE_THRM_SDN#

RSMRST# 34

U59

DY

1

A

VCC

2

B GND3Y

NC7S08M5X-NL-GP

R516

1 2

0R2J-GP

5

4

3D3V_AUX_S5

S5PWR_ENABLE 43,45

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

THERMAL G792

Bolsena-E

of

22 58Thursday, October 13, 2005

of

22 58Thursday, October 13, 2005

of

22 58Thursday, October 13, 2005

SA

CPU_THERMTRIP#6

2

1

D40

3

BAW56PT-U

3

DY

D38

2

LOW3_OFF48

1

100 mil

12

TC23

SE150U10VM-2GP

12

TC14

SE100U10VM-4GP

12

TC1

SE100U10VM-4GP

5V_USB0_S0

12

100 mil

5V_USB1_S0

12

100 mil

5V_USB2_S0

12

C5

12

C838

C463

SCD1U25V3ZY-3GP

C836

SCD1U25V3ZY-3GP

SC1000P50V2JN-N1

12

C848

SC1000P50V2JN-N1

12

C4

SC1000P50V2JN-N1

5V_S5

USB_PWR_EN#34

U73

1

GND

2

IN

3

EN1/EN1# EN2/EN2#4OC2#

G546A2P1UF-GP

G5258B2 Active Low 1.5A

5V_S0

AK

D1

D1 SSM5817PT-GP-U

5V_S5 5V_USB2_S0

USB_PWR_EN#

SSM5817PT-GP-U

1

GND

2

IN

3

IN EN#/EN4FLG

U1

G528P1UF-GP

G528P1U Active Low

BLUETOOTH MODULE

3D3V_BT_S0

BLUE1

9

10

MLX-CON8-9-GP

20.D0198.108

8 7 6 5 4 3 2

1

BT_AUX

TP2 TPAD30TP2 TPAD30

BT_GPIO2 BT_GPIO1 BT_LINK_LED

3D3V_BT_S0

ME :20.D0198.108 2ND : 20.F0714.008

MDC 1.5 CONN

MH1

ACZ_DOUT_MDC20 ACZ_SYNC_MDC20

ACZ_SDATAIN120

ACZ_RST#_MDC20 ACZ_BITCLK_MDC 20

1 2

39R2J-L-GP

12

C16

C16 SC22P50V2JN-4GP

SC22P50V2JN-4GP

R25

AC_DIN1A_R

MH2 17

AMP-CONN12A-GP

TP1

TP1 TPAD30

TPAD30

13

1 3

5 7 9

11 16

20.F0582.012

MDC1

U4

1

OUT

2

GND NC#33ON/OFF#

AAT4250IGV-T1-GP

BLUETOOTH_EN34

12

DY

EC8

SC1000P50V2JN-N1

15 14 2

4 6 8 10 12

18

IN

R27 0R2J-GP

1 2

R23 0R2J-GP

1 2

12

DY

EC5

SC1000P50V2JN-N1

5 4

12

OC1# OUT1 OUT2

OUT OUT OUT

3D3V_S0

DY

DY DY

DY

C671

C671 DUMMY-C2

DUMMY-C2

5V_USB0_S0

8 7 6 5

12

R393

R393 100KR2J-1-GP

100KR2J-1-GP

5V_USB1_S0

R1 1KR2J-1-GPR1 1KR2J-1-GP

BT_COEX2 29 BT_COEX1 29

USB_PN4 20 USB_PP4 20

12

C669

C669 SC1U10V3KX-3GP

SC1U10V3KX-3GP

R204

1KR2J-1-GP

1 2

R200

1KR2J-1-GP

1 2

3D3V_LAN_S5

2nd source: 20.F0604.012

USB PORT

USB_PN020

USB_OC#01 20

USB_OC#2 20

12

SB 0127

C429

C428

SCD1U25V3ZY-3GP

USB_PP020

USB_PN120

USB_OC#3 20

C3

SCD1U25V3ZY-3GP

USB_PP120

USB_PN220

USB_PP220

USB_PN320

USB_PP320

1

TR2

L-63UH-GP

4

RN26

3 4

SRN0J-6-GP

1

TR3

L-63UH-GP

4

RN30

3 4

SRN0J-6-GP

1

TR4

L-63UH-GP

4

RN49

3 4

SRN0J-6-GP

1

TR1

L-63UH-GP

4

RN77

3 4

SRN0J-6-GP

2

DY

68.03216.20B

3

2 1

2

68.03216.20B

3

2 1

2

68.03216.20B

3

2 1

2

DY

68.03216.20B

3

2 1

5V_USB0_S0

USB_0-

USB_0USB_0+

USB_0+

5V_USB0_S0

USB_1-

USB_1USB_1+

DY

USB_1+

5V_USB1_S0

USB_2-

DY

USB_2+

USB_3-

USB_3+

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

USB / MDC / BLUETOOTH

USB_2+

5V_USB2_S0

USB_3USB_3+

ME : 22.10218.H01 2ND : 22.10245.H11

Bolsena-E

USB2

6 1

2 3 4 5

SKT-USB-97-UGP

22.10218.H01

USB3

6 1

2 3 4 5

SKT-USB-97-UGP

22.10218.H01

USB4

6 1

2 3 4 5

SKT-USB-97-UGP

22.10218.H01

USB1

6 1

2 3 4 5

SKT-USB-97-UGP

22.10218.H01

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

23 58Thursday, October 13, 2005

of

SA

A

B

C

D

E

HDD

PIDE_D[15..0]18

RSTDRV#_517

4 4

PIDE_DREQ18 PIDE_IOW#18 PIDE_IOR#18 PIDE_IORDY18 PIDE_DACK#18 PIDE_IRQ1418 PIDE_A118 PIDE_A018 PIDE_CS#018

HDD_LED#_516

5V_S0

3 3

R353

R353 4K7R2J-2-GP

4K7R2J-2-GP

1 2

5V_S0

PIDE_D6 PIDE_D5 PIDE_D4 PIDE_D3 PIDE_D2 PIDE_D1 PIDE_D0

12

C643

DY

SC10U10V5ZY-1GP

12

C642

SCD1U25V3ZY-3GP

SATA Connector

2 2

12

SATA_TXP018 SATA_TXN018

SATA_RXN018 SATA_RXP018

TC17

TC17 ST22U6D3VBM

ST22U6D3VBM

PWR TRACE 100mil

1 1

A

12

5V_S0

C626

C626 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

HDD1

46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10

8 6 4

2

20.80175.044

CHANGE TO 20.80592.044

3D3V_S0

43

41

39

37

35

33

31

29

27

25

23

21

19

17

15

13

11

9

7

5

3

1

45

ME : 20.80592.044 (DIFFERENT FROM ORCAD P/N)

SATA1

23

MH1

1 2

3 4 5 6 7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22

MH2

24

SPD-CON22-7-GP

20.F0777.022

Dummy when use IDE

PIDE_D8PIDE_D7 PIDE_D9 PIDE_D10 PIDE_D11 PIDE_D12 PIDE_D13 PIDE_D14 PIDE_D15

B240LA-13F-GP

ME : 20.F0777.022

B

5V_S0

12

PIDE_IORDY

PIDE_A2 18 PIDE_CS#1 18

PWR TRACE 100mil

5V_S0

Dummy when use SATA

For HDD & SATA both

5V_S0

D24

KA

12

TC18

ST100U6D3VDM-5

12

C631

C631 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

R363

R363 4K7R2J-2-GP

4K7R2J-2-GP

CDROM

ODD1

SIDE_D[15..0]18

SIDE_D8 SIDE_D9

SIDE_D11 SIDE_D12 SIDE_D13 SIDE_D14

SIDE_DREQ18 SIDE_IOR#18

SIDE_DACK#18

SIDE_A218 SIDE_CS#118

5V_S0

12

C

SIDE_D15

TP52TPAD30 TP52TPAD30 TP49TPAD30 TP49TPAD30

12

C337

SC10U10V5ZY-1GP

BAY_ID0 BAY_ID1

12

C347

SCD1U25V3ZY-3GP

ODD1

2 4

6 8

10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50

C346

SPD-CONN50-4R-14GP

20.80338.050

SCD1U25V3ZY-3GP

D

51 1

3

RSTDRV#_5

5

SIDE_D7

7

SIDE_D6SIDE_D10

9

SIDE_D5

11

SIDE_D4

13

SIDE_D3

15

SIDE_D2

17

SIDE_D1

19

SIDE_D0

21 23 25 27 29 31 33 35 37 39 41 43 45

CSEL

47 49 52

R165

1 2

SIDE_IOW# 18 SIDE_IORDY 18 SIDE_IRQ15 18 SIDE_A1 18 SIDE_A0 18 SIDE_CS#0 18

4K7R2J-2-GP

SIDE_IORDY

CDROM_LED#_5 16

5V_S0

ME : 20.80338.050

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet

HDD / CDROM / SATA

A3

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

24 58Thursday, October 13, 2005

E

5V_S0

12

R171

R171 4K7R2J-2-GP

4K7R2J-2-GP

of

SA

A

B

C

D

E

3D3V_S0

R570

12

C908

C908 SC1000P50V2JN-N1

3D3V_S0

12

SC1000P50V2JN-N1

C915

C915 SC1000P50V2JN-N1

SC1000P50V2JN-N1

4 4

3 3

2 2

CLK33_CBUS17

1 1

12

C907

C907 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

C904

C904 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

PCI_AD22 CARD_IDESL

12

R575

R575 10R2J-2-GP

10R2J-2-GP

DY

CLK33_PCM1

12

C913

C913 SC10P50V2JN-1

SC10P50V2JN-1

DY

A

R576

1 2

100R2F-L1-GP-U

12

C912

C912 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

C899

C899 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

PCI_AD[31..0]17,21,27,29,30

PCI_CBE#[3..0]17,27,29,30

PCI_FRAME#17,27,29,30 PCI_IRDY#17,27,29,30 PCI_TRDY#17,27,29,30 PCI_STOP#17,27,29,30

PCI_DEVSEL#17,27,29,30 PCI_PERR#17,27,29,30

PCI_SERR#17,27,29,30

PCI_PAR17,27,29,30 PCIRST_BUF#17,27,29,30

TP120TP120

CB1410_GBRST#

3D3V_S0

130

6

PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0

PCI_CBE#3 PCI_CBE#2 PCI_CBE#1 PCI_CBE#0

PCI_GNT#117

PCI_REQ#117

12

C914

SC22P50V2JN-4GP

3

AD31

4

AD30

5

AD29

7

AD28

8

AD27

9

AD26

10

AD25

11

AD24

15

AD23

16

AD22

17

AD21

19

AD20

23

AD19

24

AD18

25

AD17

26

AD16

38

AD15

39

AD14

40

AD13

41

AD12

43

AD11

45

AD10

46

AD9

47

AD8

49

AD7

51

AD6

52

AD5

53

AD4

54

AD3

55

AD2

56

AD1

57

AD0

12

C_BE3#

27

C_BE2#

37

C_BE1#

48

C_BE0#

28

FRAME#

29

IRDY#

31

TRDY#

33

STOP#

13

IDSEL

32

DEVSEL#

34

PERR#

35

SERR#

36

PAR

21

PCI_CLK

20

RST#

59

RI_OUT#/PME#

2

GNT#

1

REQ#

VCCD1#26 VCCD0#26 VPPD126 VPPD026

3D3V_S0

B

50

PCI_VCC18PCI_VCC30PCI_VCC44PCI_VCC

VCCD1#/SMBCLK/SCLK

VCCD0#/SMBDATA/SDATA

74

73

1 2

R567 10KR2J-2-GPR567 10KR2J-2-GP

114

14

66

GND

GND94GND78GND58GND42GND22GND

CORE_VCC

GRST#

VPPD172VPPD0/SLATCH

SUSPEND70O2MF669O2MF568O2MF467O2MF365O2MF264O2MF161O2MF060SPKR_OUT#

71

CBUS_SUSPEND

62

PCM_INTA# PCM_INTB# CB_MFUNC2 CB_MFUNC3 CB_MFUNC4 CB_MFUNC5

102

122

138

CORE_VCC

CORE_VCC86CORE_VCC

CORE_VCC

R570

1 2

0R2J-GP

63

90

126

AUX_VCC

SOCKET_VCC

WP/IOIS16/CCLKRUN#

BVD2/SPKR/LED/AUDIO

BVD1/STSCHG/RI/CSTSCHG

RC12 43KR3-GPRC12 43KR3-GP

1 2

R573 0R0402-PADR573 0R0402-PAD

1 2

R572 0R0402-PADR572 0R0402-PAD

1 2

C

12

CB1410_GBRST#_1

12

C903

C903 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

REG#/CCBE3#

A25/CAD19 A24/CAD17

A23/CFRAME#

A22/CTRDY#

A21/CDEVSEL#

A20/CSTOP#

A19/CBLOCK#

A18/RFU A17/CAD16 A16/CCLK#

A15/CIRDY#

A14/CPERR#

A13/CPAR

A12/CCBE2#

A11/CAD12

A10/CAD9 A9/CAD14

A8/CCBE1#

A7/CAD18 A6/CAD20 A5/CAD21 A4/CAD22 A3/CAD23 A2/CAD24 A1/CAD25 A0/CAD26 D15/CAD8

D14/RFU

D13/CAD6 D12/CAD4 D11/CAD2

D10/CAD31

D9/CAD30 D8/CAD28

D7/CAD7

D6/CAD5

D5/CAD3

D4/CAD1

D3/CAD0

D2/RFU D1/CAD29 D0/CAD27

OE#/CAD11

WE#/CGNT#

IORD#/CAD13

IOW#/CAD15

INPACK#/CREQ#

RDY_IREQ#/CINT#

WAIT#/CSERR#

CD2/CCD2# CD1/CCD1#

CE2/CAD10

CE1#/CCBE0#

RESET/CRST#

VS2/CVS2 VS1/CVS1

R569

R569 4K7R2J-2-GP

4K7R2J-2-GP

C900

SC1000P50V2JN-N1

U79

125 116 113 111 109 107 105 103 100 98 108 110 104 101 112 95 89 97 99 115 118 120 121 124 127 128 129 87 84 82 80 77 144 142 140 85 83 81 79 76 143 141 139 92 106 93 96 136 123 132 133 137 75 91 88 119 134 135 117 131

CB1410B0-1-U

VCC_ASKT_S0

12

CBB_REG# CBB_A25 CBB_A24 CBB_A23 CBB_A22 CBB_A21 CBB_A20 CBB_A19 CBB_A18 CBB_A17 A_CCLKXX CBB_A15 CBB_A14 CBB_A13 CBB_A12 CBB_A11 CBB_A10 CBB_A9 CBB_A8 CBB_A7 CBB_A6 CBB_A5 CBB_A4 CBB_A3 CBB_A2 CBB_A1 CBB_A0 CBB_D15 CBB_D14 CBB_D13 CBB_D12 CBB_D11 CBB_D10 CBB_D9 CBB_D8 CBB_D7 CBB_D6 CBB_D5 CBB_D4 CBB_D3

CBB_D1 CBB_D0 CBB_OE#

CBB_IORD# CBB_IOWR#

CBB_CE2# CBB_CE1#

INT_PIRQE# 17,27 INT_PIRQF# 17,29

PM_CLKRUN# 17,27,29,30,34,37

C906

C906 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

CBB_REG# 26 CBB_A25 26 CBB_A24 26 CBB_A23 26 CBB_A22 26 CBB_A21 26 CBB_A20 26 CBB_A19 26 CBB_A18 26 CBB_A17 26

R568 33R2J-2-GPR568 33R2J-2-GP

CBB_A15 26 CBB_A14 26 CBB_A13 26 CBB_A12 26 CBB_A11 26 CBB_A10 26 CBB_A9 26 CBB_A8 26 CBB_A7 26 CBB_A6 26 CBB_A5 26 CBB_A4 26 CBB_A3 26 CBB_A2 26 CBB_A1 26 CBB_A0 26 CBB_D15 26 CBB_D14 26 CBB_D13 26 CBB_D12 26 CBB_D11 26 CBB_D10 26 CBB_D9 26 CBB_D8 26 CBB_D7 26 CBB_D6 26 CBB_D5 26 CBB_D4 26 CBB_D3 26 CBB_D2 26 CBB_D1 26 CBB_D0 26 CBB_OE# 26 CBB_WE# 26 CBB_IORD# 26 CBB_IOWR# 26

CBB_INPACK# 26 CBB_RDY 26 CBB_WAIT# 26 CBB_CD2#_1 26 CBB_CD1#_1 26 CBB_CE2# 26 CBB_CE1# 26 CBB_RESET 26 CBB_BVD2# 26 CBB_BVD1# 26 CBB_VS2# 26 CBB_VS1# 26

12

1 2

CB_SPKR 32

R571

R571 47KR2J-2-GP

47KR2J-2-GP

D

VCC_ASKT_S0

12

10KR2J-2-GP

10KR2J-2-GP R574

R574

CB_MFUNC2 CB_MFUNC3 CB_MFUNC4 CB_MFUNC5

CBB_OE# CBB_CE1# CBB_RESET CBB_CE2#

CBB_A16 26

CBB_WP 26

Title

Size Document Number Rev

A3

Date: Sheet

CBB_D[0..15] 26 CBB_A[0..25] 26

3D3V_S0

RN117

1 2 3 4 5

3D3V_S0

678

123

INTA# CARBUS 1 (INT_PIRQE#) INTB# (WIFI) (INT_PIRQF#) INTC# 1394 (INT_PIRQG#) INTD# CardReader (INT_PIRQE#) share

CardBus_ENE CB1410

SRN10KJ-6-GP

RN116

SRN47KJ-L1-GP

4 5

8 7 6

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

E

25 58Thursday, October 13, 2005

SA

of

SA

A

B

C

D

E

PCMCIA Socket

PCH1

NP1

1

4 4

VCC_ASKT_S0

C576

C577

12

C574

C574 SC1000P50V2JN-N1

SC1000P50V2JN-N1

3 3

CBB_A16

2 2

VPP_ASKT_S0

SC10U10V5ZY-1GP

12

C901

C901 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

Place close to pin 19.

12

C902

C902 DUMMY-C2

DUMMY-C2

CBB_D3 CBB_D4

CBB_D11 CBB_D5 CBB_D12 CBB_D6 CBB_D13 CBB_D7 CBB_D14

CBB_D15

12

C575

C575 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

CBB_D0 CBB_D8 CBB_D1 CBB_D9 CBB_D2 CBB_D10

CBB_A10

CBB_A11 CBB_A9 CBB_A8

CBB_A17 CBB_A13 CBB_A18 CBB_A14 CBB_A19

CBB_A20 CBB_A21

CBB_A16 CBB_A22 CBB_A15 CBB_A23 CBB_A12 CBB_A24 CBB_A7 CBB_A25 CBB_A6

CBB_A5 CBB_A4 CBB_A3 CBB_A2 CBB_A1 CBB_A0

Clock AC termination

CBB_CD1#

CBB_CE1#

CBB_CE2# CBB_OE# CBB_VS1#

CBB_IORD# CBB_IOWR#

CBB_WE# CBB_RDY

CBB_VS2# CBB_RESET CBB_WAIT# CBB_INPACK# CBB_REG# CBB_BVD2# CBB_BVD1#

CBB_WP CBB_CD2#

33MHz clock for 32-bit Cardbus card I/F

VCC_ASKT_S0

12

47K

R320

R320 DUMMY-R2

DUMMY-R2

35

2

36

3

37

4

38

5

39

6

40

7

41

8

42

9 43 10 44 11 45 12 46 13 47 14 48 15 49 16 50 17 51 18 52 19 53 20 54 21 55 22 56 23 57 24 58 25 59 26 60 27 61 28 62 29 63 30 64 31 65 32 66 33 67 34 68

NP2

CARDBUS68P-11-GP

ME : 62.10024.131

Cardbus I/F

CBB_D[0..15] 25

CBB_A[0..25] 25

CBB_IORD# 25 CBB_IOWR# 25 CBB_OE# 25 CBB_WE# 25 CBB_REG# 25

CBB_RESET 25

CBB_WAIT# 25

CBB_INPACK# 25

CBB_CE1# 25 CBB_CE2# 25

CBB_BVD1# 25 CBB_BVD2# 25

CBB_VS1# 25 CBB_VS2# 25

PC1

3 4

CARD-SKT18-U

DY

21.H0056.001

ME : 21.H0056.001

CBB_RDY 25

CBB_WP 25

21

Power switch

3D3V_S0

U43

CBB_CD1#

CBB_CD2#

1

VCCD0#

2

VCCD1#

3

3.3V

4

3.3V

5

5V

6

5V

7

GND

8

OC#

CP2211F-GP

R281

1 2

0R2J-GP

R346

1 2

0R2J-GP

SHTDN#

VPPD0

VPPD1 VCCOUT VCCOUT VCCOUT VPPOUT

12

C543

C543 SC270P50V2JN-2GP

SC270P50V2JN-2GP

DY

12

C628

C628 SC270P50V2JN-2GP

SC270P50V2JN-2GP

DY

VCCD0#25 VCCD1#25

3D3V_S0 VCC_ASKT_S0

12

C624

SC1U10V3ZY-6GP

12

5V_S0

C623

SCD1U16V2ZY-2GP

12

C622

SCD1U16V2ZY-2GP

C621

SC1U10V3ZY-6GP

12V

16 15 14 13 12 11 10 9

2211_SHDN#

1 2

CBB_CD1#_1 25

CBB_CD2#_1 25

R354

R354 4K7R2J-2-GP

4K7R2J-2-GP

VPPD0 25 VPPD1 25

VPP_ASKT_S0

12

C598

C598 SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

1 1

A

B

C

D

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet

PCMCA / 1394 / CARD READER

A3

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

26 58Thursday, October 13, 2005

of

E

of

SA

A

B

C

D

E

3D3V_S0

12

C579

SC10U6D3V5MX-LGP

12

C563

SCD01U16V2KX-3GP

12

PCI_CBE#[3..0]17,25,29,30

3D3V_S0

PM_CLKRUN#17,25,29,30,34,37

C613

SCD47U10V3KX-LGP

PCI_AD17 R5C834_IDSELGBUS_GRST#

12

C558

SC10U6D3V5MX-LGP

DY

R342

10KR2J-2-GP

D22

K A

CH751H-40PT-1GP

1 2

DY

PCIRST_BUF#

SHIELD GND

3D3V_S0

12

C562

0R2J-GP

1 2

R330

R331

10R2J-2-GP

12

C559

SCD1U10V2KX-LGP

SCD01U16V2KX-3GP

12

DY

R339

100KR2J-1-GP

0R2J-GP

SB Solve S3 wake up and leakage issue

12

PCLK_R5C832_PL1

12

C614

SC10P50V2JN-4GP

4 4

3 3

3D3V_S5 3D3V_S0

12

DY

2 2

PCLK_R5C83217,21

1 1

R341

SB Add 0.01U*4 for TQFP

12

C564

12

PCI_AD[31..0]17,21,25,29,30

PCI_PAR17,25,29,30

R309 10KR2J-2-GPR309 10KR2J-2-GP

12

C584

C581

SCD01U16V2KX-3GP

C565

SCD01U16V2KX-3GP

PCI_FRAME#17,25,29,30

PCI_DEVSEL#17,25,29,30

PCIRST_BUF#17,25,29,30

1 2

SCD01U16V2KX-3GP

12

C585

SCD47U10V3KX-LGP

1 2

R318 10R2J-2-GPR318 10R2J-2-GP

PCI_REQ#317

PCI_GNT#317 PCI_IRDY#17,25,29,30

PCI_TRDY#17,25,29,30

PCI_STOP#17,25,29,30 PCI_PERR#17,25,29,30 PCI_SERR#17,25,29,30

1 2

R328

12

C588

C602

SCD01U16V2KX-3GP

R5C832_VCCROUT

C561

SCD01U16V2KX-3GP

PCI_CBE#3 PCI_CBE#2 PCI_CBE#1 PCI_CBE#0

GBUS_GRST#_1

CBUS_PME# PM_CLKRUN#_R5C832

0R2J-GP

DY

12

R329

1KR2J-L1-GP

10 20 27 32 41

128

61 16

34

64 114 120

125 126 127

1 2 3 5 6

9 11 12 14 15 17 18 19 36 37 38 39 40 42 43 44 46 47 48 49 50 51 52 53 33

7 21 35 45

8

124 123

23 24 25 26 29 30 31

71

119 121

70

117

R5C832-1-GP

SCD01U16V2KX-3GP

PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0

IC1B

VCC_PCI1 VCC_PCI2 VCC_PCI3 VCC_PCI4 VCC_PCI5 VCC_PCI6

VCC_RIN VCC_ROUT1

VCC_ROUT2 VCC_ROUT3 VCC_ROUT4 VCC_ROUT5

AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 PAR C/BE3# C/BE2# C/BE1# C/BE0# IDSEL

REQ# GNT# FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# SERR#

GBRST# PCIRST#

PCICLK PME# CLKRUN#

HWSPND#

PCI / OTHER

UDIO0/SRIRQ#

VCC_3V

VCC_MD

GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9

GND10

AGND1 AGND2 AGND3 AGND4 AGND5

MSEN

XDEN

UDIO5

UDIO3 UDIO4

UDIO2 UDIO1

INTA# INTB#

TEST

67

86

4 13 22 28 54 62 63 68 118 122

99 102 103 107 111

GBUS_GRST#_2

69

58 55

UDIO5

57

UDIO3

65

UDIO4

59 56 60 72

115 116

R5C832_TEST

66

3D3V_S0

12

C578

SCD01U16V2KX-3GP

3D3V_S0

12

R304

10KR2J-2-GP

MSEN

1 2

R292 10KR2J-2-GPR292 10KR2J-2-GP

XDEN

1 2

R294 10KR2J-2-GPR294 10KR2J-2-GP

1 2

R293 100KR2J-1-GPR293 100KR2J-1-GP

1 2

R290 10KR2J-2-GPR290 10KR2J-2-GP

1 2

R291 10KR2J-2-GPR291 10KR2J-2-GP

PCI_SPKR 32 P_SERIRQ 17,34,37

INT_PIRQG# 17 INT_PIRQE# 17,25

1

TP78 TPAD30TP78 TPAD30

R300

100KR2J-1-GP

1 2

12

C587

SC10U6D3V5MX-LGP

DY

D20

KA

CH751H-40PT-1GP

3D3V_S0

GBUS_GRST#_3

DY

1 2

R289

0R2J-GP

GBUS_GRST# 34

1394 : INTA# 7in1 : INTB#(INT_PIRQE#)share

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

A

B

C

D

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

R5C832_1394_7IN1(2/2)

Bolsena-E SA

27 58Thursday, October 13, 2005

of

E

of

5

IC1A

AVCC_PHY1 AVCC_PHY2 AVCC_PHY3

GUARD GND

1 2

C591 SC15P50V2JN-2-GPC591 SC15P50V2JN-2-GP

D D

SC

1 2

C593 SC15P50V2JN-2-GPC593 SC15P50V2JN-2-GP

GUARD_GND

1 2

C599 SCD01U16V2KX-3GPC599 SCD01U16V2KX-3GP

1 2

R323 10KR2F-2-GPR323 10KR2F-2-GP

1 2

C601 SCD01U16V2KX-3GPC601 SCD01U16V2KX-3GP

GUARD_GND

GUARD GND

C C

B B

1394_XI

12

X4

X-24D576MHZ-39GP

1394_XO

RICHO_FILO

RICHO_REXT

RICHO_VREF

94

XI

95

XO

96

FIL0

101

REXT

100

VREF

97

RSV

R5C832-1-GP

AVCC_PHY4

TPBIAS0

IEEE1394/SD

MDIO17 MDIO16 MDIO15 MDIO14 MDIO13 MDIO12 MDIO11 MDIO10

MDIO05 MDIO08 MDIO19 MDIO18 MDIO02

MDIO03 MDIO00

MDIO01

MDIO09

MDIO04 MDIO06

MDIO07

TPBN0 TPBP0

TPAN0 TPAP0

4

+3VRUN_PHY

98 106 110 112

113

104 105

108 109

XD_DATA7

87

XD_DATA6

92

XD_DATA5

89

XD_DATA4

91

SD/XD/MS_DATA3_1

90

SD/XD/MS_DATA2_1

93

SD/XD/MS_DATA1_1

81

SD/XD/MS_DATA0_1

82

XD_WP#

75

SD/XD/MS_CMD

88

XD_ALE

83

XD_CLE

85

XD_CE#

78

SD_WP#(XDR/B#)

77 80

MS_INS#

79

SD/XD/MS_CLK

84

MC_PWR_CTRL_0

76

MS_LED#

74

73

TPBIAS0

TPB0N TPB0P

TPA0N TPA0P

SD_CD#

TP80TP80

3

3D3V_S0 +3VRUN_PHY

1 2

1

2

1

2

12

R566

100KR2J-1-GP

SD

GUARD_GND

D19

BAS16-1-GP

D18

BAS16-1-GP

L17 MLB1608080600A1GPL17 MLB1608080600A1GP

G50

1 2

GAP-CLOSE

G51

1 2

GAP-CLOSE

3

12

C609

SC10U6D3V5MX-LGP

6

5

SKT1

SKT-1394-4P-14GP

22.10218.M01

XD_SW#

12

4 3 2 1

2

+3VRUN_CARD

12

C610

C600

SCD1U10V2KX-LGP

SCD01U16V2KX-3GP

check with EMI, can change to 0 ohm

TPA0+

TPA0-

20mil

12

C896

SC1U10V3ZY-6GP

R523

1 2

0R3J-3-GP

DY

4

1

R522

1 2

0R3J-3-GP

DY

TPB0+

TPB0-

12

C905

SCD1U16V2ZY-2GP

12

C897

SC1U10V3ZY-6GP

Reserve R547,R548,R550,R551 for co-layout

NCMS20C900-GP

3

R525

L27

2

+3VRUN_CARD

12

C894

C894 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SD/XD/MS_DATA1_1 SD/XD/MS_DATA2_1 SD/XD/MS_DATA3_1

SD/XD/MS_DATA0_1 SD/XD/MS_DATA1_1 SD/XD/MS_DATA2_1 SD/XD/MS_DATA3_1

SD/XD/MS_DATA1_1 SD/XD/MS_DATA2_1 SD/XD/MS_DATA3_1 XD_DATA4 XD_DATA5 XD_DATA6 XD_DATA7

SD/XD/MS_DATA0_1

1 2

0R3J-3-GP

DY

3

4

1

2

R526

1 2

0R3J-3-GP

DY

CARD1

40

XD-VCC

29

S.M-VCC

20

MS-VCC

9

SD-VCC

7

SD-DAT0

6

SD-DAT1

12

SD-DAT2

11

SD-DAT3

15

MS-DATA0

14

MS-DATA1

16

MS-DATA2

18

MS-DATA3

33

S.M/XD-D1

32

S.M/XD-D2

31

S.M/XD-D3

21

S.M/XD-D4

22

S.M/XD-D5

23

S.M/XD-D6

24

S.M/XD-D7

25

S.M-LVD

30

S.M-CD#

34

S.M-D0

SKT-MEMO-12-GP

62.10051.431

U78

1

OUT

2

GND NC#33ON/OFF#

AAT4250IGV-T1-GP

NCMS20C900-GP

L29

5

IN

4

SM-CD-COM

SM-CD-SW

SM-WP-SW

MS-BS

MS-INS

MS-SCLK

RSV#4 XD-CD

SD-CD-COM

SD-CD-SW SD-WP-SW

SD-CLK

SD-CMD

S.M#/XD-CLE S.M#/XD-ALE

S.M#/XD-WE

S.M#/XD-CE S.M#/XD-RE

S.M#/XD-R/B

S.M/XD-WP-IN

GND GND GND GND

3D3V_S0

MC_PWR_CTRL_0

12

C898

SCD1U10V2KX-LGP

C612

SCD01U16V2KX-3GP

1 2

R324

56R2J-4-GP

1 2

R32556R2J-4-GPR32556R2J-4-GP

2 3 43

13 17 19

4 39

41 42 5 8 10

38 37 36 28 27 26 35

46 45 44 1

For SD/MS Card Power

CLOSE TO CHIP

C625

R327

R326

SCD33U10V3KX-2GP

12

56R2J-4-GP

R337

1 2

1394_TPB1_R

1 2

C611 SC270P50V2JN-2GPC611 SC270P50V2JN-2GP

SD/XD/MS_CMD MS_INS# SD/XD/MS_CLKSD/XD/MS_DATA0_1

XD_SW#

SD_CD# SD_WP#(XDR/B#) SD/XD/MS_CLK SD/XD/MS_CMD

XD_CLE XD_ALE SD/XD/MS_CMD XD_CE# SD/XD/MS_CLK SD_WP#(XDR/B#) XD_WP#

1

56R2J-4-GP

5K11R2F-L1-GP

TPBIAS0 TPA0P TPA0N TPB0P TPB0N

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

R5C832_1394_7IN1(2/2)

Bolsena-E SA

28 58Thursday, October 13, 2005

of

1

of

A

B

C

D

E

MINI-PCI

4 4

3D3V_S0

PCI_AD[31..0]17,21,25,27,30 PCI_CBE#[3..0]17,25,27,30

MINI1

1 3

5 7

80211_ACTIVE

WIRELESS_EN34

MINI_P_IRQF#

PCI_AD31 PCI_AD29

PCI_AD27 PCI_AD25

PCI_CBE#3 PCI_AD24 PCI_AD23

PCI_AD21

PCI_AD17 PCI_CBE#2

PCI_CBE#1 PCI_AD14

PCI_AD12 PCI_AD10

PCI_AD8 PCI_AD7

PCI_AD5 PCI_AD3 PCI_AD1

B

PM_CLKRUN#17,25,27,30,34,37

3D3V_S0

CLK33_MINI17,21

PCI_IRDY#17,25,27,30

PCI_SERR#17,25,27,30

5V_S0

3 3

BT_COEX223

3D3V_S0

12

R533

R533 10KR2J-2-GP

10KR2J-2-GP

PCI_PERR#17,25,27,30

2 2

1 1

A

9

11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97

99 101 103 105 107 109 111 113 115 117 119 121

123

ME : 62.10032.061 2ND : 62.10043.221

125 2

4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122

124 126

PCISLT124-4-GP

62.10032.061

RINGTIP

(VCC)

(M66EN)

12

C806

C806 SC4D7U10V5ZY-3GP

SC4D7U10V5ZY-3GP

DY

5V_S0

12

DY

MINI_P_IRQF#

PME#_MINI PCI_AD30 PCI_AD28

PCI_AD26 MINI_IDSEL PCI_AD22

PCI_AD20PCI_AD19 PCI_AD18

PCI_AD16

PCI_AD15 PCI_AD13 PCI_AD11

PCI_AD9 PCI_CBE#0

PCI_AD6 PCI_AD4 PCI_AD2 PCI_AD0

62.10032.031 - 2ND

12

C807

C807 SC4D7U10V5ZY-3GP

SC4D7U10V5ZY-3GP

R521

1 2

0R0402-PAD

C

12

C834

C834 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C833

SCD1U25V3ZY-3GP

DY

INT_PIRQF# 17,25

PCIRST_BUF# 17,25,27,30 PCI_GNT#0 17PCI_REQ#017

BT_COEX1 23

TP109

TP109 TPAD30

TPAD30

R534

1 2

100R2F-L1-GP-U

PCI_PAR 17,25,27,30

PCI_FRAME# 17,25,27,30 PCI_TRDY# 17,25,27,30 PCI_STOP# 17,25,27,30

PCI_DEVSEL# 17,25,27,30

12

C802

C802 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

PCI_AD21

C835

C835 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

D

WLAN_TEST_LED34

80211_ACTIVE

WIRELESS_EN

3D3V_S0

R517

R517 100KR2J-1-GP

100KR2J-1-GP

1 2

Title

Size Document Number Rev

Date: Sheet

MINI-PCI

A3

D

1

G

2 3

S

D

1

G

2 3

S

Q24

R1

2

IN

DTC124EKA-1-GP

Bolsena-E

Q26

Q26 2N7002PT-U

2N7002PT-U

Q25

Q25 2N7002PT-U

2N7002PT-U

OUT

3

GND

1

R2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

E

29 58Thursday, October 13, 2005

WLAN_LED# 16

of

SA

A

SCD1U25V3ZY-3GP

TGN0 TGP0 TGP1

4

4 4

1

12

TGN1

RN91

RN91 SRN49D9F-GP

SRN49D9F-GP

2 3

C672

C672 SCD01U50V3KX-4GP

SCD01U50V3KX-4GP

4

1

12

TGN2 TGP2

RN92

RN92 SRN49D9F-GP

SRN49D9F-GP

2 3

C673

C673 SCD01U50V3KX-4GP

SCD01U50V3KX-4GP

LAVDDH LAN_X1 LAN_X2 CTRL18 LDVDD_A

4

1

2 3

12

C674

C674 SCD01U50V3KX-4GP

SCD01U50V3KX-4GP

Dummy when use Giga

R43

1 2

5K6R3F-GP

R38

1 2

2K49R3F-GP

3 3

Dummy when use 10/100

LAVDDH

LDVDD

Dummy when use Giga

TGP231

TGN231

2 2

3D3V_S0

1

-1 0308

2

PME#_SB20

1 1

Dummy when use 10/100

TGP031

TGN031

TGP131

TGN131

R29

1 2

0R2J-GP

R28

1 2

0R2J-GP

TGP331

TGN331

3

D8 BAT54PT-GPD8 BAT54PT-GP

1 2

R394

1 2

15KR2F-GP

INT_PIRQH#17

3D3V_LAN_S5

PCIRST_BUF#17,25,27,29

CLK33_LAN17,21

PCI_GNT#217

PCI_REQ#217

1 2

0R0402-PAD

(10/100) 71.08100.C0G - (GIGA ver:D) 71.08110.C0G

CLK33_LAN

TGP0 TGN0 LAVDDL

TGP1 TGN1 LAVDDL CTRL25

LAVDDH

LV_12P

TGP2 TGN2

LAVDDL TGP3

TGN3 LAVDDL

R395 1KR2J-1-GPR395 1KR2J-1-GP

ISOLATE# LDVDD INT_PIRQH#

CLK33_LAN PCI_GNT#2 PCI_REQ#2 PME#_LAN

R396

LDVDD PCI_AD31 PCI_AD30

PCI_AD29 PCI_AD28

12

C679

C679 SC10P50V2JN-1

SC10P50V2JN-1

R413

1 2

100R2F-L1-GP-U

A

LAN_IDSELPCI_AD23

RSET

U52

1

MDI0+

2

MDI0-

3

AVDDL

4

VSS

5

MDI1+

6

MDI1-

7

AVDDL

8

CTRL25

9

VSS

10

AVDDH

11

HSDAC+

12

HSDAC-

13

VSS

14

MDI2+

15

MDI2-

16

AVDDL

17

VSS

18

MDI3+

19

MDI3-

20

AVDDL

21

VSSPST

22

GND

23

ISOLATE#

24

VDD18

25

INTA#

26

VDD33

27

PCIRST#

28

PCICLK

29

GNT#

30

REQ#

31

PME#

32

VDD18

33

PCIAD31

34

PCIAD30

35

GND

36

PCIAD29

37

PCIAD28

38

VSSPST

RTL8110SBL

3D3V_LAN_S5

2K49R3F-GP

128

127

VSS

RSET

PCI_AD27 PCI_AD26

PCI_AD25 PCI_AD24 PCI_CBE#3 LDVDD LAN_IDSEL

PCI_AD23 PCI_AD22 PCI_AD21

126

AVDD18

B

TGN3 TGP3

RN93

RN93 SRN49D9F-GP

SRN49D9F-GP

CLOSE TO LAN CHIP

4

RN94

RN94 SRN49D9F-GP

SRN49D9F-GP

1

2 3

12

C675

C675 SCD01U50V3KX-4GP

SCD01U50V3KX-4GP

Dummy when use 10/100

TP6 TPAD28TP6 TPAD28 TP5 TPAD28TP5 TPAD28

125

124

CTRL18

PCIAD2739PCIAD2640VDD3341PCIAD2542PCIAD2443CBEB344VDD1845IDSEL46PCIAD2347GND48PCIAD2249PCIAD2150VSSPST51GND52PCIAD2053VDD1854PCIAD1955VDD3356PCIAD1857PCIAD1758PCIAD1659CBEB260FRAME#61GND62IRDY#63VDD18

VSS

122

121

123

VSS

XTAL2

B

XTAL1

120

119

AVDDH

117

118

GND

VSSPST

116

LED0

115

LED1

VDD18

114

113

LED2

112

LED3

GND

111

110

EESK

109

VDD18

64

=> LED1 : LINK

RTL_LED1#

ACT_LED# LDVDD

RTL_LED1#

3D3V_LAN_S5 LAN_EECS_3

PCI_AD0 PCI_AD1

106

108

107

105

104

103

EEDI

EECS

EEDO

VDD33

PCIAD0

PCIAD1

LANWAKE

PCIAD2

VSSPST

PCIAD3 PCIAD4 PCIAD5 PCIAD6

PCIAD7

VSSPST

PCIAD8 PCIAD9

PCIAD10 PCIAD11 PCIAD12

PCIAD13 PCIAD14

VSSPST

PCIAD15

DEVSEL#

VSSPST

CLKRUN#

LDVDD PCI_IRDY# PCI_FRAME# PCI_CBE#2 PCI_AD16 PCI_AD17 PCI_AD18

PCI_AD19 LDVDD PCI_AD20

LAN_EESK LDVDD LAN_EEDI LAN_EEDO

GND

VDD18

VDD33 CBEB0

M66EN

VDD33

GND

VDD18 CBEB1

PAR

SERR#

NC#74

GND

NC#72 VDD33 PERR# STOP#

TRDY#

C

R47 0R0402-PADR47 0R0402-PAD

1 2

ACT_LED# 31

=> LED0 : ACT

3D3V_LAN_S5

Dummy when use Giga

PCI_AD2

102 101 100

LDVDD

99

PCI_AD3

98

PCI_AD4

97

PCI_AD5

96

PCI_AD6

95 94

PCI_AD7

93

PCI_CBE#0

92 91

PCI_AD8

90

PCI_AD9

89 88

PCI_AD10

87

PCI_AD11

86

PCI_AD12

85 84

PCI_AD13

83

PCI_AD14

82 81 80

PCI_AD15

79

LDVDD

78

PCI_CBE#1

77

PCI_PAR

76

PCI_SERR#

75 74 73 72 71

PCI_PERR#

70

PCI_STOP#

69

PCI_DEVSEL#

68

PCI_TRDY#

67 66

PM_CLKRUN#

65

Dummy when use 10/100

GIGALAN: RTL8110SBL 10/100 LAN:RTL8100C

PCI_IRDY# 17,25,27,29 PCI_FRAME# 17,25,27,29

3D3V_LAN_S5

C

3D3V_S5

D

PCI_CBE#[3..0]17,25,27,29

PCI_AD[31..0]17,21,25,27,29

10M_LED# 31

3D3V_LAN_S5 3D3V_LAN_S5

EEPROM LED OPTION USE '01' (DEFINED IN SPEC) => LED0 : ACT => LED1 : LINK (BOTH 10/100 AND GIGA CHIP)

3D3V_LAN_S5

12

C86

0R2J-GP

CTRL25

R69

1 2

CTRL18

1 2

R70 0R2J-GPR70 0R2J-GP

PCI_PAR 17,25,27,29 PCI_SERR# 17,25,27,29

PCI_PERR# 17,25,27,29 PCI_STOP# 17,25,27,29 PCI_DEVSEL# 17,25,27,29 PCI_TRDY# 17,25,27,29

PM_CLKRUN# 17,25,27,29,34,37

1 2

3D3V_LAN_S5

1

G59

GAP-CLOSE-PWR

SC10U10V5ZY-1GP

3

Q5

Q5 BCP69T1-1-GP

BCP69T1-1-GP

2

12

C43

SCD1U25V3ZY-3GP

3D3V_LAN_S5

D

DY

R427 10KR2J-2-GP

1 2

R426 3K6R3-GPR426 3K6R3-GP

1 2

12

C676

SCD1U25V3ZY-3GP

12

C42

C57

SCD1U25V3ZY-3GP

C683

SCD1U25V3ZY-3GP

12

C74

SCD1U25V3ZY-3GP

12

C80

SCD1U25V3ZY-3GP

LDVDD

12

C694

SCD1U25V3ZY-3GP

CTRL25

Dummy when use 10/100

Title

Size Document Number Rev

A3

Date: Sheet

E

LAN_X2

X5

XTAL-25MHZ-70GP

LAN_X1

C96

C89

RTL8110SBL/RTL8100C

1 2

LAN_EECS_3 LAN_EESK LAN_EEDI LAN_EEDO

1 2

0R0603-PAD

12

C88

SCD1U25V3ZY-3GP

12

C73

C87

SCD1U25V3ZY-3GP

3D3V_LAN_S5

3

Q3

1

BCP69T1-1-GP

2

C17

12

SC10U10V5ZY-1GP

Bolsena-E

45 Ohm, 600mA

12

C690

1 2

SC12P50V2JN-LGP

C691

1 2

SC12P50V2JN-LGP

U10

1

CS

VCC

2

SK

3 4

L21

SCD1U25V3ZY-3GP

DC

DI

ORG

DO

GND

AT93C46-10SU-1GP

LAVDDH

45 Ohm, 600mA

L3

1 2

0R0603-PAD

12

C68

SCD1U25V3ZY-3GP

Dummy when use Giga

12

R68

R68 0R3J-3-GP

0R3J-3-GP

C41

C39

12

SCD1U25V3ZY-3GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

E

3D3V_LAN_S5

8 7 6 5

12

C56

SCD1U25V3ZY-3GP

LDVDD_A

LAVDDL

C38

12

SCD1U25V3ZY-3GP

30 58Thursday, October 13, 2005

12

C696

12

C678

C670

SCD1U25V3ZY-3GP

12

C55

SCD1U25V3ZY-3GP

C40

SCD1U25V3ZY-3GP

of

SCD1U25V3ZY-3GP

SA

A

Green - 10Mbps/802.11b

Link: YellowActivity:

Orange - 100Mbps/802.11a Yellow - 1Gbps

TIP

R6

RING

10M_LED# CONN_PWR

R5

12

470R2J-2-GP

TDP_RJ45-1 TDN_RJ45-2 RDP_RJ45-3 RJ45-4 RJ45-5 RDN_RJ45-6 RJ45-7 RJ45-8 CONN_PWR_B2

12

470R2J-2-GP

ACT_LED#

LINK:GREEN ON

10M_LED#30

3D3V_LAN_S5

4 4

3D3V_LAN_S5

ACT_LED#30

ACT:YELLOW BLINKING

ME : 22.10177.721 2nd : (canceled)

MDCW1

34

MLXCON2

1 2

3 3

21.D0010.102

ME : 21.D0010.102

TGP030 TGN030

LAN1

9 RJ11_1 RJ11_2

A1 A2

A3 RJ45_1 RJ45_2 RJ45_3 RJ45_4 RJ45_5 RJ45_6 RJ45_7 RJ45_8

B1

B2

10

22.10177.721

22.10177.711 LED COLOR

A1:GREEN

A3:ORANGE

B2:YELLOW

SKT-RJ45+RJ11-2GPU

1 2 1 2

L1

L2

22.10177.711 - 2ND

BLM18HG601SN-GP

BLM18HG601SN-GP BLM18HG601SN-GP

BLM18HG601SN-GP

10/100M Lan Transformer

7 8

MCT3 MCT4 V_DAC

6 14 11

3

Dummy when use Giga

U46

TD+ TD-

CT CT CT CT

XFORM-112

68.0H80P.301

B

10M_LED# ACT_LED#

TIPTIP_MDC RINGRING_MDC

TDP_RJ45-1

10

TX+

RD+

RD-

RX+

TX-

RX-

9 1

2 16

15

TDN_RJ45-2

RDP_RJ45-3 RDN_RJ45-6

LANKOM 68.0H80P.301

CONN_PWR_B2 CONN_PWR

C9

SC1000P50V2JN-N1

TGP1 30 TGN1 30

12

EC2

SCD1U25V3ZY-3GP

12

C8

SC1000P50V2JN-N1

RJ45-8 RJ45-7 RJ45-5 RJ45-4

EC3

SCD1U25V3ZY-3GP

MCT1

123

C

678

4 5

RN6

SRN0J-4-GP

MCT2

D

E

2 2

GIGA Lan Transformer

NETSWAP GIGA THICK PN IS 68.62401.301, DON'T USE NETSWAP THIN

U47

TGP330 TGN330

TGP230 TGN230

TGP130 TGN130

TGP030 TGN030

R398

1 2

LAVDDL

1 1

0R2J-GP

12

Dummy when use 10/100

V_DAC

12

C18

C19

SCD01U50V3KX-4GP

C21

SCD01U50V3KX-4GP

Dummy when use Giga

A

2

TD1+

3

TD1-

5

TD2+

6

TD2-

8

TD3+

9

TD3-

11

TD4+

12

TD4-

1

TCT1

4

TCT2

7

TCT3

10

12

C20

TCT4

XFORM-207-GP

68.62401.30A

Dummy when use 10/100

12

SCD01U50V3KX-4GP

MX1+

MX2+

MX3+

MX4+

MCT1 MCT2 MCT3 MCT4

C14

C14 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

LANKOM 68.02402.30A netSWAP 68.62401.301 (GIGA ,Thick)

RJ45-7

23

RJ45-8

MX1-

MX2-

MX3-

MX4-

22 20

19 17

16 14

13 24

21 18 15

C11

1 2

RJ45-4 RJ45-5

RDP_RJ45-3 RDN_RJ45-6

TDP_RJ45-1 TDN_RJ45-2

MCT1 MCT2 MCT3 MCT4

LAN_TC_GND

12

SC1KP2KV8KX-GP

SC1KP2KV8KX-GP C10

C10

DY

SC1000P50V2JN-N1

B

123

1.route on bottom as differential pairs.

2.Tx+/Tx- are pairs. Rx+/Rx- are pairs.

3.No vias, No 90 degree bends.

4.pairs must be equal lengths.

5.6mil trace width,12mil separation.

6.36mil between pairs and any other trace.

7.Must not cross ground moat,except RJ-45 moat.

678

RN7

4 5

SRN75J-1-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet

C

D

Date: Sheet

A3

LAN CONN

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

SA

31 58Thursday, October 13, 2005

of

E

of

SA

5

4

3

2

1

5V_S0

U42

D D

C604

SC1U10V3KX-3GP

C606C606

C594C594

C595C595

C605C605

1 2

AUD_MICIN_L33 AUD_MICIN_R33

PCI_SPKR_1

INT_MIC33

CB_SPKR_1

KBC_BEEP_1

SPKR_SB_1

SRN47KJ-L1-GP

4 5

3

2

1

6 7 8

RN75

SC1U10V3ZY-6GP

SC1U10V3ZY-6GP SC1U10V3ZY-6GP

SC1U10V3ZY-6GP

AUD_AGND

C618

C618 C619

C619

1 2 1 2 1 2

C617

R3142K2R2J-2-GP R3142K2R2J-2-GP

1 2

R3222K2R2J-2-GP R3222K2R2J-2-GP

1 2 1 2

R3172K2R2J-2-GP R3172K2R2J-2-GP

C583

AUDIO_BEEP

12

R336

R336 1KR2J-1-GP

1KR2J-1-GP

MIC1_L MIC1_R

MIC2_L

MIC1V_R

MIC1V_LMIC1V_L

MIC2_0

C592

1 2

SC4D7U10V5ZY-3GP

C596

AUDIP_PC_BEEP

1 2

SC1U10V3KX-3GP

12

C607

C607 SC100P50V3JN-2GP

SC100P50V3JN-2GP

1

9

25

U40

23

LINE1-L

24

LINE1-R

14

LINE2-L

15

LINE2-R

29

LINE1-VREFO

31

LINE2-VREFO

21

MIC1-L

22

MIC1-R

16

MIC2-L

17

MIC2-R

32

MIC1-VREFO-R

28

MIC1-VREFO-L

30

MIC2-VREFO

C590

1 2

ALC883-1-GP 71.00883.A0G

SC4D7U10V5ZY-3GP

38

AVDD1

DVDD1

DVDD2

ALC 883

DVSS1

AVSS126VREF

AVSS2

4

7

42

C608

CB_SPKR25

SPKR_SB20

C C

B B

KBC_BEEP34

PCI_SPKR27

3D3V_S0

SCD1U10V2KX-LGP

10

12

6

11

SYNC

AVDD2

RESET#

PCBEEP

DVSS2

JDREF

27

37

40

12

SC10U10V5ZY-1GP

12

C597

33

43

44

VAUX

BIT-CLK

LFE-OUT

GPIO02GPIO1

PIN37_VREFO

3

CEN-OUT

5VA_S0

12

C589

AUD_AGND

SCD1U10V2KX-LGP

13

34

SENSE_A

SENSE_B

SDATA-OUT

SDATA-IN

SPDIFI/EAPD

SIDESURR-OUT-L

SIDESURR-OUT-R

SURR-OUT-L

SURR-OUT-R

FRONT-OUT-L

FRONT-OUT-R

CD-L18CD-GND

CD-R

19

20

"VAUX" Pull high to enable standby mode

12

C582

C582 SCD1U10V2KX-LGP

SCD1U10V2KX-LGP

SPDIFO

AUD_AGND

R338

1 2

20KR2F-L-GP

5

AC97_DATIN

8

48 47

45 46

39 41

35 36

12

C620

SCD1U10V2KX-LGP

ACZ_RST# 20 ACZ_SYNC 20 AZ_BITCLK 20

R316

1 2

12

10KR2J-2-GP

R319

39R2J-L-GP

12

R313

4K7R2J-2-GP

ACZ_DOUT 20

ACZ_SDATAIN0 20

SPDIF 33

G1421_MUTE 33

1 2

12

AUD_AGND

MIC_JKIN#_1 33

AUD_LOL 33 AUD_LOR 33

SHDN#

SET GND IN3OUT

G923-330T1UF-GP

5

5V_AUDIO_S0

4

5VA_SET

12

5VA_S0

12

C615

SC22P50V2JN-4GP

C616

C616 SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

AUD_AGND

12

R334

R334 28K7R2F

28K7R2F

12

R335

R335 10KR2F-2-GP

10KR2F-2-GP

AUD_AGND

A A

5

4

AUD_AGND

G49

1 2

GAP-CLOSE

AUD_AGND

3

GAP-CLOSE

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet

AUDIO (1/2) -- CODEC ALC655

A3

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

32 58Thursday, October 13, 2005

of

1

of

SA

12

C627

C627 SC4D7U10V5ZY-3GP

SC4D7U10V5ZY-3GP

AMPGND

5VA_OP_S0

12

C909

SC1U10V3KX-3GP

AMPGND

12

R345

R345 10KR2J-2-GP

10KR2J-2-GP

DY

AMPGND

AUD_LOR32

12

C633

AMPGND

SC4D7U10V5ZY-3GP

A

C634

SCD1U25V3ZY-3GP

PDTA124EU-1-GP

B

R1

Q20

DY

AMPGND

1 2

SC2D2U16V5ZY-GP

1 2

SC2D2U16V5ZY-GP

5VA_OP_S0

DY

R2

E C

AMPGND

HP_IN_1

12

R350

GAP-CLOSE

C640

CSOUTL1

C911

CSOUTL2

R352

R352 10KR2J-2-GP

10KR2J-2-GP

1 2

R351

R351 10KR2J-2-GP

10KR2J-2-GP

1 2

AMPGND

C632

CSOUTR1

1 2

SC2D2U16V5ZY-GP

C636

CSOUTR2

1 2

SC2D2U16V5ZY-GP

1 2

R578

1 2

HP_L L_BYPASS

HP_IN_1

AMPGND

R_BYPASS HP_R

1 2

R357

15KR2F-GP

R349

R355

10KR2J-2-GP

L_LINE_IN

15KR2F-GP

10KR2J-2-GP

SYS_LOUT_IN

5V_S0 5VA_OP_S0

G53

1 2

GAP-CLOSE-PWR

4 4

AUD_LOL32

12

C910

SC10U10V5ZY-1GP

AMP_SHUTDOWN34

3 3

R_BYPASS

L_BYPASS

12

C635

AMPGND

2 2

HP_L

4 5 6 7

8

2 17 23

18 19 20 21

R_LINE_IN

HP_R

B

SB 0203ALL AUD_AGND -> AMPGND

SC220P50V2KX-3GP

U44

LLINEIN LHPIN LBYPASS LVDD

SHUTDOWN TJ HP-IN VOL

RVDD RBYPASS RHPIN RLINEIN

G1421BF3UF-GP

AMPGND

1 2

R356

1 2

10KR2J-2-GP

1 2

R577

1 2

18KR2F-GP

SE/BTL#

HP/LINE#

MUTEIN

MUTEOUT

GND/HS GND/HS GND/HS GND/HS

GND

25

R359

1 2

18KR2F-GP

1 2

R358

1 2

10KR2J-2-GP

1 2

5VA_OP_S0

12

R348

2K2R2J-2-GP

OUT

3

GND

1

DTC124EKA-1-GP

C639

C638

C638 SC220P50V2KX-3GP

SC220P50V2KX-3GP

3

LOUT+

10

LOUT-

14 16 11 9 1 12 13 24

15

ROUT-

22

ROUT+

AMPGND

C637

C637 SC220P50V2KX-3GP

SC220P50V2KX-3GP

C641

C641 SC220P50V2KX-3GP

SC220P50V2KX-3GP

Q21

R1

2

IN

R2

SPKR_L+ SPKR_L-

HP_IN

AUD_MUTE

SPKR_RSPKR_R+

12

R372

R372 10KR2J-2-GP

10KR2J-2-GP

SYS_LOUT_IN#SYS_LOUT_IN#

C

5V_S0

10

U3C

TSAHCT125PW-GP

12

R340

R340 100KR2J-1-GP

100KR2J-1-GP

D

G55 GAP-CLOSEG55 GAP-CLOSE

12

G56 GAP-CLOSEG56 GAP-CLOSE

12

G52 GAP-CLOSEG52 GAP-CLOSE

12

G54 GAP-CLOSEG54 GAP-CLOSE

12

AMPGND

R347

5

6

1 2 1 2

SYS_LOUT_IN

14

98

7

3 4

2

1

RB731U-1GP-U

12

R344

R344 100KR2J-1-GP

100KR2J-1-GP

D23

10KR2J-2-GP

10KR2J-2-GP R343

R343 10KR2J-2-GP

10KR2J-2-GP

DY

AMPGND AMPGND

G1421_MUTE 32

KBC_MUTE 34

SPKR_LSPKR_L+ SPKR_R+ SPKR_R-

12

Internal Speaker

12

C917

C919

C916

SC680P50V2KX-2GP

C919

SC680P50V2KX-2GP

E

12

C918

ME : 20.D0198.104 2ND : 20.F0714.004

SC680P50V2KX-2GP

SPK1

4 3 2

1

MLX-CON4-19-GP

20.D0198.104

6

5

LINE IN/MIC IN

AMPGNDAMPGND

LIN1

5 4 3 6 2 1

AUDIO-JK60-GP

22.10088.B41

22.10271.051 - 2ND

ME : 22.10088.B41 2ND : 22.10271.051

3D3V_S0

12

EC50

LOUT1

9

GND

8

VCC

7

VIN

16

6 5 4 2 3 1

MINDIN9-7-GP

22.10147.111

22.10251.231 2ND

SC330P50V2KX-3GP

AUD_MICIN_R32

AUD_MICIN_L32

AMPGND

LINE OUT

79.10111.40L

TC29

SPKR_L+ SPKR_R+

TC28 SE100U10VM-4GP

R370

1 2

R368

1 2

12

R36910KR2J-2-GP R36910KR2J-2-GP

R37110KR2J-2-GP R37110KR2J-2-GP

AMPGND

SE100U10VM-4GP

1 2 1 2

79.10111.40L

1KR2J-1-GP

AUD_LINE_R

AUD_LINE_L

C647

SC100P50V2JN-U

SYS_LOUT_IN#=LOW after PLUG-IN

SPKR_L+1

SPKR_R+1 SPKR_R_A1

R374

12

1KR2J-1-GP

AMPGNDAMPGND

1 2 1 2

R373

1KR2J-1-GP

R365

R365 R364

R364

22R2J-2-GP

22R2J-2-GP 22R2J-2-GP

22R2J-2-GP

SYS_LOUT_IN#

MIC_JKIN#_132

C648

12

SPDIF32

SPKR_L_A1

12

C650

SC680P50V2KX-2GP

SC100P50V2JN-U

12

EC45

C649

SC680P50V2KX-2GP

SC330P50V2KX-3GP

MIC1

3

INT_MIC32

C6

1 1

A

B

C6

SC1000P50V2JN-N1

DY

C

1 2

4

1 2

MLX-CON2-5-GP

20.D0173.102

R3

1 2

0R3J-3-GPR30R3J-3-GP

ME : 20.D0173.102 2ND :20.F0714.002

D

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

AUDIO (2/2)

Size Document Number Rev

Custom

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

33 58Thursday, October 13, 2005

of

E

SA

12

5V_S0

RN71

SRN10KJ-5-GP

R285

DUMMY-R2

R284

R284 10KR2J-2-GP

10KR2J-2-GP

5

3D3V_AUX_S5

C567

C567 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

LPC_LFRAME#17,21,37 P_SERIRQ17,27,37

KBCBIOS_RD# KBCBIOS_WE# KBCBIOS_CS#

A036 A136 A236 A336 A436 A536 A636 A736 A836 A936 A1036 A1136 A1236 A1336 A1436 A1536 A1636 A1736 A1836

TDATA_535 TCLK_535

12

C552

1 2

12

C525

SCD1U16V2ZY-2GP

LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3

150 151 173 152

KBC_D0

138

KBC_D1

139

KBC_D2

140

KBC_D3

141

KBC_D4

144

KBC_D5

145

KBC_D6

146

KBC_D7

147 124

125 126 127 128 131 132 133 143 142 135 134 130 129 121 120 113 112 104 103

117 116 115 114 111 110

ECSWI#20

PM_PWRBTN#20 RSMRST#_KBC20,44

S5_ENABLE22

BRIGHTNESS16

KBC_PWRBTN#35

KBC_LID#35

KBC_SLP_WAKE20

L16

BLM11P600S

C529

SCD1U16V2ZY-2GP

15

LAD0

14

LAD1

13

LAD2

10

LAD3

9

LFRAME#

18

LCLK

7

SERIRQ

RD# WR# MEMCS# IOCS#

D0 D1 D2 D3 D4 D5 D6 D7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19

PSDAT3 PSCLK3 PSDAT2 PSCLK2 PSDAT1 PSCLK1

KBC_BEEP32

1 2

AC_IN#47

SB 0201

12

C545

C545 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

TP79TP79

SRN47J-4-GP

4 5 3 2 1

RN70

3

5

12

C570

C570 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

LPC_LAD[0..3]17,37

CLK33_KBC17,21

KBCBIOS_RD#36 KBCBIOS_WE#36 KBCBIOS_CS#36

KBC_D[0..7]36 BAT_SDA_548

6 7 8

TDATA_5 TCLK_5

3D3V_AUX_S5

12

D D

C C

B B

A1

A A

A1 for the internal pull-up resistors on XIOCS[F:0] pins==>High=enable,Low=Disable A4 for DMRP==>High=Disable,Low=Enable

A5 for EMWB==>High=Enable,Low=Disable

GPIO05 for Clock test mode==>High=test Mode,Low=32KHz clock in normal running(Recommended) GPIO06 for DPLL test mode==>High=Test Mode,Low=Normal operation(Recommended)

12

C513

C513 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

5V_S0

3D3V_AUX_S5

C534

C534 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

1 4 2

12

3D3V_KBC_AUX_S5

12

VCC16VCC34VCC45VCC

LPC

X-bus ROM

PS/2

PWM743PWM640PWM539PWM438PWM337PWM236PWM133PWM0

R261

1KR2J-1-GP

PM_SLP_S3#17,20,38,39,45,56

4

123

136

157

166

VCC

TP118TP118

RSMRST#_KBC

4

VCC

95

32

VCCA

161

VCCBAT

TP74TP74

KCOL1

KCOL2

KCOL3

KCOL4

KCOL5

KCOL6

50

53

KSO049KSO1

KSO251KSO352KSO4

KB3910

GPWU02GPWU126GPWU229GPWU330GPWU444GPWU576GPWU6

USB_PWR_EN#23

172

TP119TP119

GPWU7

176

KCOL7

KCOL8

KCOL9

KCOL10

KCOL11

KCOL12

KCOL13

KCOL14

60

KSO556KSO657KSO758KSO859KSO9

KSO1061KSO1164KSO1265KSO1366KSO1467KSO1568KSO16

KB Matrix

DA099DA1

DA2

DA3

DA41DA542DA647DA7

100

101

102

TP67TP67

TP69TP69

TP70TP70

3S 47 3S2P_I 47

KCOL15

KCOL16

153

154

KSO17

AD081AD182AD283AD384AD487AD588AD689AD7

174

TP65TP65

TP64TP64

3

KCOL[1..16] 35 KROW[8..1] 35

KROW1

KROW2

KROW3

KROW4

KROW5

KSI071KSI172KSI273KSI374KSI477KSI578KSI679KSI7

TP63TP63

KBC_BB_ENABLE#

3

KROW6

KROW7

KROW8

BAT_SCL_5

BAT_SDA_5

80

163

164

SCL1

ECRST#19ECSCI#31GND17GND35GND46GND

90

1KR2J-1-GP

EC_RST#

R265

1 2

AD_IA

KBC_XO

KBC_XI

KBC_SCL2

KBC_SDA2

160

169

158

170

SCL2

SDA1

SDA2

XCLKI

XCLKO

AGND96BATGND

159

AD_IA 47

KBC_BB_ENABLE# 36

1 2

X3

X3 X-32D768KHZ-15

X-32D768KHZ-15

3

1 2

GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24 GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO09 GPIO08 GPIO07 GPIO06 GPIO05 GPIO04 GPIO03 GPIO02 GPIO01 GPIO00

GPIO0F

GPIO0E GPIO0D GPIO0C

GPIO0B

GPIO0A

GPIO1F

GPIO1E GPIO1D GPIO1C

GPIO1B

GPIO1A

GPIOI2D

GPIO2F

GPIO2E GPIO2C

GPIO2B

GPIO2A

GND

KB3910SF-2-GP

CHANGE TO 71.03910.B0G

122

137

167

3D3V_AUX_S5

ECSCI#_KBC 20

C553

SCD1U16V2ZY-2GP

C569

C569 SC22P50V2JN-4GP

SC22P50V2JN-4GP

C568

C568 SC22P50V2JN-4GP

SC22P50V2JN-4GP

U32

155 149 148 119 118 109

A20

108

E51TXD

107

E51RXD

106

E51CS#

105 86 85 75 70 69 63

1 2

62 55 54 48 22 21 20 12 11 8

KBCRST#

6 5 4 3

41

1 2

28 27 25 24 23

98 97 94 93 92 91

VCC3VSB

168 175 171

KBC_PCIRST#

165 162 156

12

R278

R278 10KR2J-2-GP

10KR2J-2-GP

12

E

Q15

Q15 CH3906PT-GP

CH3906PT-GP

C

2

KBC_SCL2 KBC_SDA2

TP71 TPAD28TP71 TPAD28

R251

DY

0R2J-GP

12

R287 10KR2J-2-GPR287 10KR2J-2-GP

TP68TP68

R271 1KR2J-1-GPR271 1KR2J-1-GP

1 2

B

2

3D3V_AUX_S5

3

RN72

SRN10KJ-5-GP

2

1 4

SMBC_G79222

MATRIXID2# 36 MATRIXID1# 36

PRE_CHG 47

BLT_BTN# 35

CHG_ON# 47 AD_OFF 48

STDBY_LED# 16

GBUS_GRST# 27

KBC_MUTE 33

WIRELESS_BTN# 35 KA20GATE 20

BAT_THERMAL 47,48

WIRELESS_EN 29 PM_CLKRUN# 17,25,27,29,30,37

MAIL_LED# 16 CHARGE_LED# 16

R306

R272

10KR2J-2-GP

TP73 TPAD28TP73 TPAD28 TP72TP72

INTERNET# 35 MAIL# 35 PM_SLP_S5# 20,45

4S1P_I 47

PM_SUS_STAT# 20

TP66TP66

CAP_LED# 16

FRONT_PWRLED# 16

TP75TP75

KEY5# 35

TP76TP76 TP77TP77

KEY4# 35

ECSMI#_KBC 20

FPBACK 16 NUM_LED# 16

BLUETOOTH_EN 23

DC_BATFULL# 16

BLT_LED# 16

WLAN_TEST_LED 29

AMP_SHUTDOWN 33

0R0402-PAD

12

LPC_RST# 13,17,37,49

BL_ON 13,52

CHK_PW# 36

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

KBC_SDA2

3D3V_AUX_S5

12

R286 10KR2J-2-GPR286 10KR2J-2-GP

3D3V_S5

RSMRST# 22

U38 2N7002DW-7F-GPU38 2N7002DW-7F-GP

34 5 6

R270

R270 100KR2J-1-GP

100KR2J-1-GP

1 2

12

2

1

BAT_SCL_548

KBRCIN# 20

R302

R302 100KR2J-1-GP

100KR2J-1-GP

C571

SC1U10V3ZY-6GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

KBC KB3910

KBC KB3910 Bolsena-E

Bolsena-E

1

3D3V_S0

KBC_SCL2

1

SMBC_G792 SMBD_G792

SMBD_G792 22

2 1 4

PRE_CHG

34 58Thursday, October 13, 2005

5V_S0

3D3V_AUX_S5

RN73

3

SRN8K2J-3-GP

R301

R301 10KR2J-2-GP

10KR2J-2-GP

1 2

of

2

14

RN74

SRN10KJ-5-GP

3

SA

POWER BUTTON

4 4

A

Power

PWRBTN#_1

PWR1

1 2

5 43

SW-TACT-59-GP-U1

62.40009.431

ME : 62.40009.241 (ALL 11 PCS)

Buttons

Internet Mail P1 P2

MAIL#_1 INTERNET#_1 KEY4#_1 KEY5#_1

MAIL1

1 2

5 43

SW-TACT-59-GP-U1

62.40009.431

3 3

WIRELESS_BTN# BLT_BTN#

12

C644

C644 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

NET1

1 2

5 43

SW-TACT-59-GP-U1

62.40009.431

P1

1 2

5 43

SW-TACT-59-GP-U1

62.40009.431

Wireless ON/OFFBlueTooth ON/OFF

BLUE2

BLT_BTN#_1 WIRELESS_BTN#_1

12

C645

C645 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

BLUE2

1 2

PUSH-SW89

43

WIRELESS_BTN#34

BLT_BTN#34

B

3D3V_AUX_S5

PWRBTN#_1

3D3V_S5

P2

1 2

SW-TACT-59-GP-U1

62.40009.431

WLAN1

1 2

PUSH-SW89

R367 470R2J-2-GPR367 470R2J-2-GP

1 2

R366 470R2J-2-GPR366 470R2J-2-GP

1 2

12

R7

R7 10KR2J-2-GP

10KR2J-2-GP

1 2

SRN10KJ-6-GP

8 7 6

RN9

5 43

43

R9

470R2J-2-GP

12

1 2 3 45

ME : 22.40082.081 2nd:22.40069.811

WIRELESS_BTN#_1

BLT_BTN#_1

KBC_PWRBTN# 34

C12

C12 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

MAIL#_1 KEY4#_1 KEY5#_1 INTERNET#_1

1 4 2

4 5 3 2 1

RN76

SRN10KJ-5-GP

SRN470J-3-GP

6 7 8

RN8

3D3V_S5

3

C

45

678

123

RC1

RC1 SRC100P50V-2-GP

SRC100P50V-2-GP

MAIL# 34 KEY4# 34 KEY5# 34 INTERNET# 34

D

Cover Up Switch

KBC_LID#34

TOUCH PAD

TDATA_534

TP_SCROLL_LEFT

SCRL2

1 2

5 43

SW-TACT-59-GP-U1

62.40009.431

TCLK_534

TP_SCROLL_UP

SCRL1

1 2

SW-TACT-59-GP-U1

62.40009.431

?ESD ?

TP_SCROLL_DOWN

SCRL4

1 2

SW-TACT-59-GP-U1

62.40009.431

3D3V_S5

12

5V_S0

2

14

RN28

SRN10KJ-5-GP

3

1 2 3

5 43

R22

R22 47KR2J-2-GP

47KR2J-2-GP

R12

1 2

100R2F-L1-GP-U

C13

C13 SC1000P50V2JN-N1

SC1000P50V2JN-N1

SCD1U25V3ZY-3GP

RN27

4

SRN100J-3-GP

TP_SCROLL_RIGHT

SCRL3

1 2

SW-TACT-59-GP-U1

62.40009.431

LID_SW

C389

C385

12

SC47P50V2JN-3GP

5 43

E

Main : 20.D0173.102 2nd:20.F0714.002

LID1

3 1 2

MLX-CON2-5-GP

12

C374

12

1 2

SW-TACT-59-GP-U1

4

20.D0173.102

12

C390

SC1U10V3KX-3GP

TP_DATA TP_CLK

TP_RIGHT TP_SCROLL_RIGHT TP_SCROLL_UP TP_SCROLL_LEFT TP_SCROLL_DOWN

TP_LEFT

SC47P50V2JN-3GP

TP_LEFT

LEFT1

5 43

62.40009.431

5V_S0

TPAD1

MLX-CON12-10-GP

14 12 11 10

9 8 7 6 5 4 3 2

1

13

20.K0185.012

ME : 20.K0185.012 2nd:20.K0174.012

TP_RIGHT

RIGHT1

1 2

5 43

SW-TACT-59-GP-U1

62.40009.431

EMI Bypass cap.

KCOL1 KCOL2 KCOL3

KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9

KCOL10

KCOL11 KCOL12

KCOL13 KCOL14 KCOL15 KCOL16

KROW[8..1] 34 KCOL[1..16] 34

Pin1 ==>*R01 Pin2 ==>*R02 Pin3 ==>*R03 Pin4 ==> C01 Pin5 ==> C02 Pin6 ==> C03 Pin7 ==>*R04 Pin8 ==> C04 Pin9 ==> C05 Pin10 ==> C06 Pin11 ==> C07 Pin12 ==> C08 Pin13 ==> C09 Pin14 ==>*R05 Pin15 ==> C10 Pin16 ==>*R06 Pin17 ==>*R07 Pin18 ==> C11 Pin19 ==> C12 Pin20 ==>*R08 Pin21 ==> C13 Pin22 ==> C14 Pin23 ==> C15 Pin24 ==> C16 Pin25 ==> NC

C

KROW7 KCOL11 KCOL12 KROW8

KCOL5 KCOL6 KCOL7 KCOL8

KCOL2 KCOL3 KROW4 KCOL4

KCOL9 KROW5 KCOL10 KROW6

KROW1 KROW2 KROW3 KCOL1

KCOL13 KCOL14 KCOL15 KCOL16

RC7

1

8

2

7

3

6

4 5

SRC100P50V-2-GP

SRC100P50V-2-GP RC5

RC5

1

8

2

7

3

6

4 5

SRC100P50V-2-GP

SRC100P50V-2-GP RC4

RC4

1

8

2

7

3

6

4 5

SRC100P50V-2-GP

SRC100P50V-2-GP RC6

RC6

1

8

2

7

3

6

4 5

SRC100P50V-2-GP

SRC100P50V-2-GP RC3

RC3

1

8

2

7

3

6

4 5

SRC100P50V-2-GP

SRC100P50V-2-GP RC8

RC8

1

8

2

7

3

6

4 5

SRC100P50V-2-GP

TP_RIGHT TP_SCROLL_RIGHT TP_SCROLL_UP TP_SCROLL_LEFT

TP_LEFT TP_SCROLL_DOWN

D

Title

Size Document Number Rev

Date: Sheet

Internal KeyBoard CONN

2 2

KB1

125

........

1 1

ME :20.K0192.025 2nd:20.K0197.025

A

26

NC#26

1

C01

2

C02

3

C03

4

R01

5

R02

6

R03

7

C04

8

R04

9

R05

10

R06

11

R07

12

R08

13

R09

14

C05

15

R10

16

C06

17

C07

18

R11

19

R12

20

C08

21

R13

22

R14

23

R15

24

R16

25

NC#25

27

NC#27

MLX-CON25-1-GP

20.K0192.025

B

KROW1 KROW2 KROW3

KROW4

KROW5 KROW6

KROW7

KROW8

RC10

1

8

2

7

3

6

4 5

SRC100P50V-2-GP

DY

RC9

1

8

2

7

3

6

4 5

SRC100P50V-2-GP

DY

BUTTONs / KB / TOUCHPAD

A3

Bolsena-E

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

35 58Thursday, October 13, 2005

of

E

of

SA

5

D D

C C

4

KBC_D[0..7] 34

KBCBIOS_WE#34 KBCBIOS_RD#34 KBCBIOS_CS#34

KBC_D034 KBC_D134 KBC_D234 KBC_D334 KBC_D434 KBC_D534 KBC_D634 KBC_D734

(SOCKET) 62.10002.032 - (IC)72.39040.H03 IN DIP,SMT

A034 A134 A234 A334 A434 A534 A634 A734

3

12

C895

C895 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SST39VF040-70-1

3D3V_AUX_S5

U77

13

DQ0

14

DQ1

15

DQ2

17

DQ3

18

DQ4

19

DQ5

20

DQ6

21

DQ7

32

VDD

VSS

16

1

31

22

24

CE#

OE#

WE#

A012A111A210A39A48A57A66A7

2

A162A1730A18

3

A15

29

A14

28

A13

4

A12

25

A11

23

A10

26

A9

27

A8

5

ROM SIZE MAX. 512KBYTE

A18 34 A17 34 A16 34

A15 34 A14 34 A13 34 A12 34 A11 34 A10 34 A9 34 A8 34

1

PLCC32 Socket P/N:

3D3V_S0

678

B B

KBC_BB_ENABLE#34 CHK_PW#34 MATRIXID1#34 MATRIXID2#34

A A

5

RN24

RN24 SRN10KJ-6-GP

SRN10KJ-6-GP

123

4 5

Keyboard matrix ( from vendor )

Low Bit

MATRIXID1#

High Bit

MATRIXID2#

SW1

1

8

2

7

3

6

4

5

SW-2184LPSTR-1GP

1

JapUS

100

01

4

OtherEur

10

SSKT3262.10002.032 SSKT32 62.10005.032

3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

2

Date: Sheet

BIOS ROM

BIOS ROM Bolsena-E

Bolsena-E

Taipei Hsien 221, Taiwan, R.O.C.

36 58Thursday, October 13, 2005

of

1

of

SA

C541

1 2

3D3V_S0

12

DY

C551

SC4D7U10V5ZY-3GP

SCD1U16V2ZY-2GP

12

C540

SCD1U16V2ZY-2GP

PM_CLKRUN#17,25,27,29,30,34

BADRR_STRAP

R264

R264 10KR2J-2-GP

10KR2J-2-GP

12

C550

SCD1U16V2ZY-2GP

LPC_LFRAME#17,21,34

P_SERIRQ17,27,34

LPC_RST#13,17,34,49

LPC_LDRQ0#17

LPC_LAD[0..3]17,34

12

C533

SCD1U16V2ZY-2GP

VCORF

RB1

U31

1

CTS1#

44

DCD1#

45

DSR1#

3

RI1#

46

SIN1

19

CLKRUN#/GPIO22

10

VCORF

2

DTR1#_BOUT1/BADDR

47

RTS1#/TRIS#

48

SOUT1/TEST#

1 2

8

VDD

GPIO0011GPIO0112GPIO0213GPIO0314GPIO04

PCIRST_BUF#_SIO

33R2J-2-GP

24

35

VDD

15

LPC_LAD0

LPC_LAD1

LPC_LAD2

LPC_LAD3

32

36

38

40

LAD0

LAD1

LAD2

LAD3

GPIO20

GPIO21/LPCPD#

GPIO23

17

21

22

R282

42

30

SERIRQ

LFRAME#

RESERVED/GPO24

VSS

9

23

IRTX_3 IRSL0_3 IRRX_3

NC

VSS

43

CLKIN

VSS

34

25

27

28

16

LRESET#

LDRQ#/XOR_OUT

IRRX15IRTX6IRRX2_IRSL0/GPIO17

7

12

DY

10R2J-2-GP

LCLK

NC NC NC NC NC NC NC NC NC

PC87381-VBH-GP

C524 SC10P50V2JN-1C524 SC10P50V2JN-1

CLK33_SIO_T

C544

33 37 39 41 4 18 26 29 31

20

12

SC10P50V2JN-1

DY

CLK14_SIO 3

CLK33_SIO 17,21

3D3V_S0

12

C857

C857 SC1U10V3KX-3GP

SC1U10V3KX-3GP

12

C885

C885 SC4D7U10V5ZY-3GP

SC4D7U10V5ZY-3GP

Infineon FIR Module

40mil

IRTX_3 IRRX_3 IRSL0_3

IRMODE

10KR2J-2-GP

DY

10mil 10mil 10mil

1 2

R559

IR1

1

VCC2/IRED_ANODE

2

IRED_CATHODE

3

TXD

4

RXD

5

SD

6

VCC1

7

MODE

8

GND

FIR-TFDU6102-GP

56.15001.051

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet

SUPER IO NC87381

A3

Taipei Hsien 221, Taiwan, R.O.C.

SNIPE

37 58Thursday, October 13, 2005

of

-2

A

B

C

D

E

Run Power

4 4

DCBATOUT

PM_RUNCTL

R312

1 2

10KR2J-2-GP

PM_RUNCTL_G

R311

1 2

330KR2J-L1-GP

PM_SLP_S3#17,20,34,39,45,56

3 3

2 2

1 2

R315 1K5R3-GPR315 1K5R3-GP

1

12

C586

SC1U10V3KX-3GP

12VGATE_S041

Q17

Q17 TP0610T

TP0610T

12

3 12

R310

R310 1KR2J-1-GP

1KR2J-1-GP

3

Q19

PDTC144EU-1-GP

2

12

R303

R303 47KR2J-2-GP

47KR2J-2-GP

DY

1

G

2 3

12

C580

D

Q18

Q18 2N7002PT-U

2N7002PT-U

S

DY

1 2

12

R308

330KR2J-L1-GP

SCD22U16V3ZY-GP

2D5V_S01D8V_S0

D35

RB751V-40-1-GP

KA

D21

D21 MMGZ5242BPT-GP

MMGZ5242BPT-GP

SCD1U25V3ZY-3GP

C566

1 2

SCD1U25V3ZY-3GP

C505

1 2

SCD1U25V3ZY-3GP

DY

1 2

C786

3D3V_S0

SB 0201

2D5V_S0

1 2 3 4 5

C749 SCD1U25V3ZY-3GP

DY

1 2

U36

1

S

2

S

3

S

4 5

GD

AO4422-1-GP

U26

1

S

2

S

3

S

4 5

GD

AO4422-1-GP

U60

S

D

S

D

S

D

S

D

S

D

S

D

GD

AO4422-1-GP

1D8V_S0

U56

1

S

2

S

3

S

4 5

GD

AO4422-1-GP

D

D D

D

D D

D

8 7 6

2D5V_S3

5V_S55V_S0

12

C549

C549 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

3D3V_S5

12

C506

C506 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

C797

C797 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

8

D

7

D

6

D

1D8V_S5

12

C405

C405 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

1 1

A

B

C

D

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet

PWR CTL LOGIC / PWR PLANE

A3

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

38 58Thursday, October 13, 2005

of

E

of

SA

A

B

C

D

E

4 5

12

5V_S5

147

C526

C526 DUMMY-C3

DUMMY-C3

U33B

6

TSLCX08MTCX-GP

73.07408.02B

SB_PWRGD 20

1D2V_S0_EN

1D2V_S0_EN 45

2D5V_S0

R279

R279 10KR2J-2-GP

10KR2J-2-GP

1 2

12

C542

C542 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

VTT_VDDA_PG

PM_SLP_S3#

5V_S5

U33C

147

13 12

11

TSLCX08MTCX-GP

73.07408.02B

VCORE_EN 41,52

3D3V_AUX_S5 3D3V_AUX_S5

U41A

147

NB_PWRGD NB_PWRGD_N

4 4

3 3

1 2

?U54 CHOOSE CHEAPER

SB_PWRGD IS 35MS AFTER NB_PWRGD

TSLCX14MTC-L-U

VRM_PWRGD20,41

R332

1 2

DY

270KR2F-L-GP

12

R333

220KR2J-L2-GP

PM_SLP_S3#

VRM_PWRGD

12

C603

C603 SC1U10V3ZY-6GP

SC1U10V3ZY-6GP

3D3V_S5

13 12

147

73.07408.02B

147

3 4

TSLCX14MTC-L-U

NB_PWRGD

U30C

11

TSLCX08MTCX-GP

RUNPWROK22

Reduce leakage (WHEN 3D3V_AUX_S5 ON, 3D3V_S0 OFF)

U41B

R321

1KR2J-1-GP

1 2

3D3V_S5

147

1 2

3D3V_S5

U30D

VTT_VRM_PG

147

10

9

8

TSLCX08MTCX-GP

U30A

3

TSLCX08MTCX-GP

PM_SLP_S3#17,20,34,38,45,56

VRM_PWRGD

R258

1 2

NB_PWRGD 13,52

330R2J-3-GP

2 2

1 1

A

B

C

D

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet

POWERGOOD&ENABLES

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

of

39 58Thursday, October 13, 2005

E

SA

A

CPU_CORE MAX1544ETL

VID0_PWM

VID1_PWM

4 4

VID2_PWM

VID3_PWM

VID4_PWM

VID Setting

VID0(I / 3.3V)

VID1(I / 3.3V)

VID2(I / 3.3V)

VID3(I / 3.3V)

VID4(I / 3.3V)

Input Signal

VCORE_EN

EN (I / 3.3V)

Voltage Sense

COREFB

COREFB#

3 3

VSEN(I / Vcore)

RGND(I / Vcore)

Input Power

DCBATOUT

5V_S0

3D3V_S0

VCC(I)

Output Signal

VROK()

Output Power

VCC_CORE_PWR(O)

TPS51120 5V/3D3V

2 2

SHUTDOWN_S5 MAX1999_PGD

SHUTDOWN_S5

DCBATOUT

PM_SLP_S3#

Input Signal

ON3

ON5

SHDN#

SKIP#

Input Power

DCBATOUT

1 1

V+

A

Output Signal

PGOOD(OD / 5V)

Output Power

5V(O)

3D3V(O)

LDO5(O)

B

MAX1544_VRM

VCC_CORE_S0(Imax=27.3A)

1D2V_S0_EN

S5PWR_ENABLE

GND

DCBATOUT_5130

DCBATOUT

5V_S5

5V_AUX_S5

5V_S0

5V_S5 (6A)

3D3V_S5 (4A)

MAX1999_LDO5 (30mA)

MAX1999_LDO3 (30mA)LDO3 (O)

B

Input Signal

PM_SLP_S5#

SS_STBY1(I / 5V)

SS_STBY2(I / 5V)

SS_STBY3(I / 5V)

STBY_LDO(I / 5V)

STBY_VREF5(I / 28V)

STBY_VREF3.3(I / 28V)

Input Power

VIN (I / 28V)

REG5V_IN(I / 5V)

5V_AUX_S5

For PGOUT

CHARGE_OFF

BT_TH

BAT+SENSE

BT_SCL_5

BT_SDA_5

FLASH_GPIO1

FLASH_GPIO2

AC_IN

AD+

C

TI TPS5130 2D5V/1D2V/1D8V

FOR

2.5V FOR

1.2V FOR

1.8V

Charger_Max8725

CLS (I / 3.3V)

THM (I / 3.3V)

BATT (I / 3.3V)

SCL (IO / 5V)

SDA (IO / 5V)

RESET#/PB5 (I/5V)

PB0/MOSI/AIN0

Input Power

DCIN (I)

C

Output Signal

PGOUT(OD / 5V)

Pull High (5V)

Output Power

2D5(O)

1D2V(O)

1D8V(O)

2D5V (9A)

1D2V (5A)

1D8V (5A)

LDO(O)

Output SignalInput Signal

LDO (O / 5.4V)

XTAL2/PB4 (O/5V)

AD_IN

CHARGE_LED#

XTAL1/PB3 (O/5V) BL2#

Output Power

VCC (O)

DCBATOUT

BT+

D

DCBATOUT

AUX_SD

2D5V_S3

5V_S5

APL5331_1D25V_VREF

5V_S0

DCBATOUT

PM_SLP_S3#

AD_OFF

AD_JK

5V_AUX_S5

(Power Team)

D

5V_AUX_S5

E

INPUT

SD

LP2951ACM

OUT

5V_AUX_S5

1D25V_S3

VIN

VCNTL

VOUT

1D25V_S0

VREF

APL5331KAC

FAN5234_VGA_Core 1D15V or 1D20V

Input Power

VCC

VIN

Input Signal

EN

Output Signal

PG

Output Power

1D15V (O) or 1D20V (O)

1D15V (5.2A) or 1D20V (9A)

Adapter

Input Signal

(I)

Input Power

VCC(I)

Output Signal

(O)

Output Power

VCC(O)

VCC(I)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

POWER BLOCK DIAGRAM

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

AD_IN

AD+

40 58Thursday, October 13, 2005

of

E

of

SA

A

CPU_VCORE VID=1.20V Iomax=27.3A (35W) OCP=40A~45A

4 4

TABLE 1. VOLTAGE IDENTIFICATION CODES VID4 VID3 VID2 VID1 VID0 DAC 0 0 0 0 0 1.550 0 0 0 0 1 1.525 0 0 0 1 0 1.500 0 0 0 1 1 1.475 0 0 1 0 0 1.450 0 0 1 0 1 1.425 0 0 1 1 0 1.400 0 0 1 1 1 1.375 0 1 0 0 0 1.350 0 1 0 0 1 1.325 0 1 0 1 0 1.300 0 1 0 1 1 1.275 0 1 1 0 0 1.250 0 1 1 0 1 1.225 0 1 1 1 0 1.200 0 1 1 1 1 1.175 1 0 0 0 0 1.150

3 3

1 0 0 0 1 1.125 1 0 0 1 0 1.100 1 0 0 1 1 1.075 1 0 1 0 0 1.050 1 0 1 0 1 1.025 1 0 1 1 0 1.000 1 0 1 1 1 0.975 1 1 0 0 0 0.950 1 1 0 0 1 0.925 1 1 0 1 0 0.900 1 1 0 1 1 0.875 1 1 1 0 0 0.850 1 1 1 0 1 0.825 1 1 1 1 0 0.800 1 1 1 1 1 Shutdown

2 2

U16

2N7002DW-7F-GP

VID0_PWM

VID1_PWM

1 1

From KBC

VID4

A

VID3

VID2

1 2 3 4

U17

2N7002DW-7F-GP

1 2 3 4

1

D

2N7002PT-U

2N7002PT-U Q8

Q8

12

R206

R206 60K4R3F-GP

60K4R3F-GP

1544_AGND

TON: Frequency: GND 550KHz REF 300KHz OPEN 200KHz VCC 100KHz

6 5

G

23

S

VID0

VID3_PWM

VID1

VID2_PWM

VID4_PWM

B

DCBATOUT_MAX1544

MAX1544_V+

MAX1544_REF

12VGATE_S0 38

B

R202

R202 0R0603-PAD

0R0603-PAD

1 2

12

R201

R201 12K7R2F-GP

12K7R2F-GP

DY

R208

1 2

R192

1 2

0R0402-PAD

VID[4..0]6

121KR2F-L-GP

12

C433

C433 SC100P50V3JN-2GP

SC100P50V3JN-2GP

1544_AGND

MAX1544_ILIM

MAX1544_VCC

12

R207

R207 80K6R3F-1-GP

80K6R3F-1-GP

R209

12

100KR2F-L1-GP

R183

1 2

100KR2J-1-GP

1544_AGND

C426

12

SC1U25V5ZY-4GP

MAX1544_TIME

MAX1544_OFS MAX1544_REF MAX1544_CCI

VID0_PWM VID1_PWM VID2_PWM VID3_PWM VID4_PWM MAX1544_OVP

12

C438

C438 SCD22U16V3KX-2-GP

SCD22U16V3KX-2-GP

12

R196

R196 1KR3F-GP

1KR3F-GP

C

12

C431

1544_AGND

SC1U10V3KX-3GP

C420

12

U18

SC2D2U10V5KX-LGP

1

TIME

2

TON

3

SUS

7

OFS

8

REF

14

CCI

24

D0

23

D1

22

D2

21

D3

20

D4

19

OVP

MAX1544ETL-1-GP

12

R199

R199 511R3F-GP

511R3F-GP

12

R197

1KR2F-3-GP

R193

R193 1KR3F-GP

1KR3F-GP

C

5V_S0

D39

3

12

R214

R214 10R2J-2-GP

10R2J-2-GP

MAX1544_V+

MAX1544_VCC

36

10

30

V+

VCC

VDD

S04S1

OAIN-

OAIN+

5

16

17

MAX1544_OAIN-

MAX1544_OAIN+

12

R187

R187 511R3F-GP

511R3F-GP

12

MAX1544_BSTS

2

MAX1544_BSTM

1

BAW56PT-U

12

R186

R186 100KR2J-1-GP

100KR2J-1-GP

MAX1544_SKIP#

6

33

18

38

DHS

SKIP#

SHDN#

FB

BSTS

13

15

35

MAX1544_BSTS

MAX1544_FB

SC1000P50V3JN-GP

12

C427

R194

R194 1KR2F-3-GP

1KR2F-3-GP

SC470P50V3JN-2GP

MAX1544_CMP

MAX1544_CSP MAX1544_FB

MAX1544_CMN MAX1544_CSN

MAX1544_VCC

40

39

37

CSP

CMP

CMN

GNDS

PGND31GND

11

41

MAX1544_GNDS

C432

R198

R198 1MR2J-1-GP

1MR2J-1-GP

1544_AGND

MAX1544_CCI

D

R205

1 2

0R2J-GP

CSN

DLM DHM

LXM BSTM VROK

CCV

DLS

LXS

ILIM

GND

1544_AGND

12

MAX1544_VCC

DY

29 28

27 26 25

MAX1544_CCV

12 32 34

MAX1544_ILIM

9

26K7R2F

R203

R203 100R2F-L1-GP-U

100R2F-L1-GP-U

12

R210

1544_AGND

For Dummy Phase 2

MAX1544_CSP 42 MAX1544_CSN 42

C404

1 2

SCD22U16V3KX-2-GP

R185

1 2

100KR2J-1-GP

C423

1 2

SCD22U16V3KX-2-GP

12

C434

C434 SC270P50V2JN-2GP

SC270P50V2JN-2GP

1544_AGND

COREFB# 6

For alone test==>short C395 pin1 and pin2

COREFB 6

12

R188

R188 0R0402-PAD

0R0402-PAD

VCC_CORE_S0

VCC_CORE_S0 feedback

Title

Size Document Number Rev

Date: Sheet

(Power Team)

D

Date: Sheet

A3

3D3V_S0

MAX1544_BSTS

VCORE_EN 39,52

MAX1544_DHS 42

MAX1544_CMN 42 MAX1544_CMP 42

MAX1544_DLM 42 MAX1544_DHM 42 MAX1544_LXM 42,58

MAX1544_BSTM

VRM_PWRGD 20,39

MAX1544_DLS 42 MAX1544_LXS 42,58

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU Vcore 1

Bolsena-E

E

SA

41 58Thursday, October 13, 2005

of

E

of

SA

A

G71

1 2

G73

1 2

G74

1 2

G70

1 2

G72

4 4

DCBATOUT

12

C384

SC1U25V5ZY-4GP

MAX1544_DHM41

3 3

MAX1544_LXM41,58 MAX1544_DLM41

1 2

12

TC24

TC24 SE100U25VM-7GPU

SE100U25VM-7GPU

G78

G79

B

GAP-CLOSE-PWR

DCBATOUT_MAX1544

678

DDD

GD

4 5

U63

678

DDD

GD

4 5

AO4422-1-GP

AO4422-1-GP U64

U64

SSS

123

AO4430-1-GP

SSS

123

C370

1 2

SC1U25V5ZY-4GP

C842

1 2

SC10U35V0ZY-1GP

SC10U35V0ZY-1GP C831

C831

1 2

SC10U35V0ZY-1GP

C843

1 2

SC10U35V0ZY-1GP

C832

1 2

C

DUMMY-C3

L28

1 2

IND-D56UH-15-GP

R524 D001R7520F-1-GPR524 D001R7520F-1-GP

1 2

12

R527

0R0402-PAD

MAX1544_CMN 41 MAX1544_CMP 41

VCC_CORE_S0

D

VCC_CORE_S0

12

TC22

SE330U2VDM-L-GP

DY

12

TC6

SE330U2VDM-L-GP

12

TC4

SE330U2VDM-L-GP

E

12

TC3

SE330U2VDM-L-GP

12

TC5

SE330U2VDM-L-GP

12

TC7

SE330U2VDM-L-GP

DY

2 2

MAX1544_DHS41 MAX1544_LXS41,58 MAX1544_DLS41

1 1

A

B

DCBATOUT_MAX1544

678

DDD

GD

4 5

U67

678

AO4430-1-GP

GD

4 5

DDD

AO4422-1-GP

AO4422-1-GP U65

U65

SSS

123

SSS

123

1 2

C841

C841 SC10U35V0ZY-1GP

SC10U35V0ZY-1GP

C

L30

1 2

IND-D56UH-15-GP

R530

1 2

D001R7520F-1-GP

12

R536

R536 0R0402-PAD

0R0402-PAD

VCC_CORE_S0

MAX1544_CSN 41 MAX1544_CSP 41

(Power Team)

D

SB 0203

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

CPU Vcore 2

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

42 58Thursday, October 13, 2005

E

of

SA

5

4

3

2

1

DCBATOUT_51120

G33

1 2

GAP-OPEN-PWR

G34

1 2

GAP-OPEN-PWR

G36

D D

DCBATOUT

C C

B B

GND

SKIPSEL

COMP

TONSEL

A A

VFB1

VFB2

EN1,EN2

EN3,EN5 not use

AUTOSKIP

N/A

380k/CH1 590k/CH2

N/A

Switcher OFF

LDO OFF

1 2

GAP-OPEN-PWR

1 2

GAP-OPEN-PWR

1 2

GAP-OPEN-PWR

S5PWR_ENABLE22,45

51120_V5FILT

G36

G35

G37

TP61 TPAD30TP61 TPAD30 TP62 TPAD30TP62 TPAD30

VREF2

AUTOSKIP /FAULTS

OFF

N/A

290k/CH1 440k/CH2

not use

5

DCBATOUT_51120

51120_LL2

1 2

R252 0R3J-3-GPR252 0R3J-3-GP

51120_LL1 51120_LL1_1

1 2

R274 0R3J-3-GPR274 0R3J-3-GP

SC10U10V5KX-2GP

0R3J-3-GP

R275

1 2 1 2

R2530R3J-3-GPR2530R3J-3-GP

R260 0R3J-3-GPR260 0R3J-3-GP

1 2 1 2

R262 0R3J-3-GPR262 0R3J-3-GP

51120_GND

51120_V5FILT

FLOAT

PWM

CURRENT MODE

220k/CH1 330k/CH2

ADJ.

Swithchr ON

LDO ON

51120_VREG5

51120_LL2_1 51120_VBST2

1 2

SCD1U50V3ZY-GP

1 2

SCD1U50V3ZY-GP

51120_VREG5

SC10U10V5KX-2GP

51120_VREG3

12

51120_GND 51120_GND

5V_PWR 3D3V_PWR

51120_VREF2

12

C528

R266

R256

12

C531

51120_EN1 51120_EN2

51120_VFB2 51120_VFB1

SC1000P50V3JN-GP

29 12 10

9 6

3 1

8 4

U28

TPS51120RHBR-GPU1

11KR3F-GP

1 2

11KR3F-GP

C523

V5FILT

PWM

D-Cap MODE

180k/CH1 280k/CH2

5V Fixed Output

3.3V Fixed Output

Switcher ON

VREG3 on

R259

1 2

5D1R3F-GP

51120_GND

C514

C538

51120_VBST1

EN1 EN2 EN3 EN5

VFB2 VFB1

VO1 VO2

VREF2

51120_CS1

51120_CS2

DY

C537

SC390P50V3JN-GP

51120_V5FILT

SC1U10V3KX-3GP

12

C527

19

21

13

28

VBST2

VBST1

VREG3

VREG5

GND

PGND217CS2

PGND1

GND

5

24

33

51120_GND

51120_COMP1

DY

12

51120_GND

4

DCBATOUT_51120

12

C532

SCD1U50V3ZY-GP

51120_COMP2

2

7

20

22

VIN

V5FILT

COMP2

CS1

SKIPSEL

18

23

31

32

51120_SKIPSEL

12

51120_GND

12

R269

30KR3F-2-GP

51120_COMP1_PL

C856

SC1000P50V3JN-GP

12

DY

C539

R257 0R3J-3-GPR257 0R3J-3-GP

51120_COMP1

R263 0R3J-3-GPR263 0R3J-3-GP

COMP1

LL2 LL1

PGOOD1 PGOOD2

DRVL1 DRVL2

DRVH1 DRVH2

TONSEL

R277

0R3J-3-GP

51120_COMP2

12

DY

SC390P50V3JN-GP

1 2 1 2

15 26

51120_PGD1

30

51120_PGD2

11 25

16 27

14

R268

1 2

0R2J-GP

12

DY

51120_COMP2_PL

12

51120_GND

51120_V5FILT

51120_LL2 51120_LL1

51120_DRVL1 51120_DRVL2

51120_DRVH1 51120_DRVH2

51120_VREF2

R558

22KR3F-GP

SC680P50V3JN-GP

DY

C855

DDD

U37

AO4422-1-GP

SSS

GD

SSS

GD

123

51120_DRVH1 51120_LL1

AO4702-1-GP

51120_DRVL1

3D3V_S0

12

R276

100KR2J-1-GP

DY

1 2

R267 0R2J-GP

1 2

R254

DY

For TPS51120, Vout=5V

1. If you use a 6.8uH inductor, the minimum ESR is 70m ohm.

2. If you use a 4.7uH inductor, the minimum ESR is 48m ohm.

3. If you use a 3.3uH inductor, the minimum ESR is 34m ohm. Vout=3.3V

1. If you use a 4.7uH inductor, the minimum ESR is 51m ohm.

2. If you use a 3.3uH inductor, the minimum ESR is 36m ohm.

3. If you use a 2.5uH inductor, the minimum ESR is 27m ohm.

0R2J-GP

3

DY

AO4422-1-GP

51120_DRVH2 51120_LL251120_LL251120_LL251120_LL251120_LL251120_TONSEL

AO4702-1-GP

51120_DRVL2

4 5

678

DDD

U34

GD

4 5

678

DDD

U27

SSS

GD

SSS

GD

123

4 5

678

DDD

U25

SSS

GD

SSS

GD

123

4 5

SSS

123

SC10U35V0ZY-1GP

1 2

L36

IND-3D3UH-43-GP

51120_VFB1

12

C507

SC10U35V0ZY-1GP

L35

1 2

IND-2D5UH-6-GP

SC33P50V3JN-GP

C858

DY

51120_VFB2

C572

SC10U35V0ZY-1GP

DY

C859

DCBATOUT_51120

12

DY

12

SC10U35V0ZY-1GP

678

DDD

12

C573

SC33P50V3JN-GP

12

DY

51120_GND

C508

3D3V_PWR

12

DY

R560

30K9R3F-GP

12

R561

13KR3F-GP

51120_GND

2

C557

C557 SCD1U50V3ZY-GP

SCD1U50V3ZY-GP

5V_PWR

5V Iomax=5A OCP>10A

DY

12

R562

30KR3F-2-GP

TC27

ST220U6D3VDM-13GP

SANYO 220uF ESR=25mohm Iripple=2.4A

R563

7K5R3F-L1-GP

3D3V Iomax=5A OCP>10A

12

TC16

ST220U6D3VDM-13GP

SANYO 220uF ESR=25mohm Iripple=2.4A

Title

Size Document Number Rev

A3

Date: Sheet

3D3V_PWR 3D3V_S5

Vout=1V*(R1+R2)/R2

TPS51120 / 3D3V / 5V

Bolsena-E

G97

1 2

GAP-OPEN-PWR

G98

1 2

GAP-OPEN-PWR

G95

1 2

GAP-OPEN-PWR

G94

1 2

GAP-OPEN-PWR

G96

1 2

GAP-OPEN-PWR

G92

1 2

GAP-OPEN-PWR

G93

1 2

GAP-OPEN-PWR

G91

1 2

GAP-OPEN-PWR

G47

1 2

GAP-OPEN-PWR

G46

1 2

GAP-OPEN-PWR

G44

1 2

GAP-OPEN-PWR

G42

1 2

GAP-OPEN-PWR

G43

1 2

GAP-OPEN-PWR

G45

1 2

GAP-OPEN-PWR

G48

1 2

GAP-CLOSE-PWR

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

43 58Thursday, October 13, 2005

1

51120_GND

of

5V_S55V_PWR

-1

A

Output = 3.3

output=1.25(

4 4

R283

5V_AUX_2951

12

B

RSMRST#_KBC20,34

12

10KR2J-2-GP

3 3

SCD1U16V2ZY-2GP

C536

5V_S5

E

CH3906PT-GP

CH3906PT-GP Q16

Q16

C

12

C535

SC1U10V3ZY-6GP

B

12

R273

R273 10KR2J-2-GP

10KR2J-2-GP

1 2 3 4

LP2951CDR2G-GP

C530

1 2

SCD1U16V2ZY-2GP

U29

OUTPUT SENSE SHUTDOWN

100mA

GND

ERROR# OUTPUT

DY

FEEDBACK

INPUT

VO TAP

C

D

E

Aux Power

3D3V_AUX_S5

5V_S5

D17

21

CH521S-30-GP-U

D16

21

CH521S-30-GP-U

DCBATOUT

8 7 6

C522

5

DUMMY-C5

12

C521

C521 SC1U25V5ZY-4-GP

SC1U25V5ZY-4-GP

12

C555

DUMMY-C3

5V_S5_G913

12

C548

C556

SC10U10V5ZY-1GP

U35

1

SHDN#

2

GND

3

IN

G913CF-GP

SC1U10V3ZY-6GP

SET

OUT

SC10U10V5ZY-1GP

5 4

C547

3D3V_AUX_S5

3D3V_G913_SET

12

C554

3D3V_AUX_S5

12

C560

SC22P50V2JN-4GP

SC1U10V3ZY-6GP

12

C546

DY

Rx

12

R288

R288 16K5R2F-1-GP

16K5R2F-1-GP

12

R299

R299 10KR2F-2-GP

10KR2F-2-GP

Ry

2D5V_S3

GAP-CLOSE-PWR

G88

12

C893

C893 SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

78.10693.41L

2 2

1 1

A

12

C892

C892 SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

78.10693.41L

78.10693.41L DY

DY

2D5V_S3

12

R564

R564 1KR2F-3-GP

1KR2F-3-GP

APL5331_1D25V_VREF

12

R565

R565 1KR2F-3-GP

1KR2F-3-GP

12

C890

C890 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

5V_S5

12

C891

C891 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

U76

VIN1VOUT

3

VREF VCNTL6NC

2

GND

9

GND

APL5331KAC-TRLGP

SO-8-P

B

1D25V_S3 Iomax=1.5A

Vo(cal.)=1.250V

4 8

7

NC

5

NC

12

TC25

DY

SE100U10VM-4GP

79.10111.40L

KEMET 100uF / 4V / B2 Size / NTD:5.615 Iripple=1.1A / ESR=70mohm

1 2

12

C884

C884 SC22U10V6ZY-1-GP

SC22U10V6ZY-1-GP

G88

GAP-CLOSE-PWR

G87

GAP-CLOSE-PWR

G89

GAP-CLOSE-PWR

G90

C

1D25V_S31D25V_LDO

Trace Length=1cm (500mils) Trace Width=8mils Trace Resistance>25mohm

(Power Team)

D

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet

1D2V_S3 / 3D3V_AUX

A3

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

44 58Thursday, October 13, 2005

of

E

of

SA

5

A

For 2.5V SETTING=2.516V

R542

1 2

10KR2F-2-GP

12

SC3900P50V3KX-GP

C407

R539

1 2

10KR2F-2-GP

C410

SC3900P50V3KX-GP

12

SC3300P50V3KX-1GP

12

D D

For 1.2V SETTING=1.2172V

R541

R541 2KR2F-3-GP

2KR2F-3-GP

5130_INV3 5130_FB3

R189

R189 2KR2F-3-GP

2KR2F-3-GP

5130_INV1 5130_FB1

R182

1 2

330R2J-3-GP

1 2

19K6R3F-GP

close to IC

R184

1 2

680R3F-GP

1 2

4K32R2F-GP

close to IC

C393

1 2

SC5600P50V3KX-GP

R543

C406

1 2

SC4700P50V3KX-1GP

R544

2D5V_PWR

1D2V_PWR

PWM_SEL

C C

3D3V_AUX_S5

U41E

TSLCX14MTC-L-U

PM_SLP_S5#20,34

3D3V_AUX_S5

B B

1D2V_S0_EN39

5V_AUX_S5

R546

1 2

100KR2J-1-GP

PM_SLP_S3#17,20,34,38,39,56

147

11 10

147

9 8

TPS5130_1D8V_EN#

SC1500P50V3KX-GP

U41D

TSLCX14MTC-L-U

T(soft)=1.736ms

PM_SLP_S5

5130_SS_STBY1

12

3 4 2 1

1 2

R545

R545 100KR2J-1-GP

100KR2J-1-GP

C411

1D2V_S0_EN#

U70 2N7002DW-7F-GP

84.27002.C3F

R551

R551 0R2J-GP

0R2J-GP

DY

U69 2N7002DW-7F-GPU69 2N7002DW-7F-GP

34

5130_SS_STBY2

5130_STBY_LDO

12

R552

R552 0R0402-PAD

0R0402-PAD

2 1

S5PWR_ENABLE 22,43

12

5 6

5130_SS_STBY3

1D2V_S0_EN#

C413

C413 SC4700P50V3KX-1GP

SC4700P50V3KX-1GP

4

TI TPS5130 for 2.5V, 1.2V, 1.8V

Vo=(R1*0.85)/R2+0.85

(1D2V=>CH1 , 1D8V=>CH2 , 2D5V =>CH3)

For 1.8V SETTING=1.8275V

R190

1 2

10KR2F-2-GP

SC3900P50V3KX-GP

C412

Condition Voltage

H : Auto PWM/SKIP 2.2V(Min)~

*

L : PWM fixed (300KHz) ~0.3V(Max)

SB 0201

C408

1 2

SC1500P50V3KX-GP

5130_3D3V_LDO

12

R549

R549 100KR2J-1-GP

100KR2J-1-GP

R550

1 2

DUMMY-R2

R191

DCBATOUT_5130

1 2

100KR2J-1-GP

12

R195

R195 2KR2F-3-GP

2KR2F-3-GP

12

5130_INV2 5130_FB2

5130_FLT

12

C399

C399 SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

1 2

5130_FB1 5130_SS_STBY1 5130_INV2 5130_FB2 5130_SS_STBY2 5130_PWMSELPM_SLP_S3# 5130_CT

5130_REF STBY_REF

5130_STBY_LDO

5130_CT

12

R548

C844

1 2

680R3F-GP

SC5600P50V3KX-GP

R547

1 2

11K5R2F-GP

close to IC

C414

C414 SC47P50V2JN-3GP

SC47P50V2JN-3GP

5130_REF

12

C415

SC1U10V3ZY-6GP

BAT54PT-GP

5130_FLT 5130_INV1

1

FB1

2

SS_STBY1

3

INV2

4

FB2

5

SS_STBY2

6

PWM_SEL

7

CT

8

GND

9

REF

10

STBY_VREF5

11

STBY_VREF3.3

12

STBY_LDO

5130_SS_STBY3 5130_FB3 5130_INV3

5V_S0

12

R540

R540 10KR2J-2-GP

10KR2J-2-GP

DY

SB 0201

3

1D8V_PWR

5130_5V_LDO

1

D14

3

5130_LH1

SCD1U50V3KX-GP

47

46

48

45

FLT

LH1

INV1

OUT1_U

TPS5130

FB3

INV3

SS_STBY3

PGOUT16PG_DELAY

14

15

13

5130_PG_DELAY

2

C391

1 2

5130_OUT1U 5130_OUT1D

5130_TRIP1 5130_TRIP2

40

39

44

17

12

38

LL1

TRIP141TRIP2

OUT1_D43OUT2_D

OUTGND142OUTGND2

VIN_SENSE12

LH3

LL3

OUT3_D

OUT3_U

TRIP3

VIN_SENSE3

20

22

23

21

18

19

5130_LH3

3

BAT54PT-GP

BAT54PT-GP D13

D13

5130_TRIP3

C400

C400 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

DY

5130_LL1

DCBATOUT_5130

5130_OUT2D

37

LL2

OUT2_U

LH2 VIN

VREF3.3

VREF5

REG5V_IN

LDO_IN

LDO_CUR

LDO_GATE

LDO_OUT

INV_LDO

OUTGND3

24

TPS5130PTRG4-GP-U

5130_OUT3D 5130_LL3 5130_OUT3U

C387

1 2

SCD1U50V3KX-GP

1

2

5130_5V_LDO

D12

BAT54PT-GP

5130_LL1 46,58

5130_OUT1U 46 5130_OUT1D 46

5130_OUT2D 46

U15

36 35 34 33 32 31

5130_REGIN

30 29 28 27 26 25

5130_5V_LDO

DCBATOUT_5130

1

2

3

C381

5130_LH2

1 2

SCD1U50V3KX-GP

close to IC

5130_OUT2U

R538

1 2

0R0805-PAD

5130_3D3V_LDO

LDO SETTING

5130_OUT3D 46 5130_OUT3U 46 5130_LL3 46,58

2

5130_TRIP1

5130_TRIP2

5130_TRIP3

5130_LL2

DCBATOUT_5130

5130_OUT2U 46

(Power Team)

1

1D2V_OCP

R180

1 2

11K3R2F-2-GP

C386

1 2

close to IC

1D8V_OCP

R179

1 2

12K1R2F-L1-GP

C380

1 2

close to IC

2D5V_OCP

R181

1 2

18KR2F-GP

C392

1 2

close to IC

5130_LL2 46,58

1 2

5V_S5

5V_AUX_S5

1 2

PWM_SEL

Title

Size Document Number Rev

A3

Date: Sheet

DCBATOUT_5130

SCD1U25V3ZY-3GP

OCP

8.4A=>R226=13K 10A=>R226=22K

DCBATOUT_5130

SCD1U25V3ZY-3GP

OCP

8.4A=>R229=12.65K 10A=>R229=22K

DCBATOUT_5130

SCD1U25V3ZY-3GP

OCP 12A=>R225=18K 18A=>R225=28K

-1 0310

5130_5V_LDO

C375

C375 SCD1U50V3KX-GP

SCD1U50V3KX-GP

R537

R537 0R3J-3-GP

0R3J-3-GP

12

C377

C377 SC4D7U10V5ZY-3GP

SC4D7U10V5ZY-3GP

78.47593.41L

5130_3D3V_LDO

1 2

12

C376

C376 SC4D7U10V5ZY-3GP

SC4D7U10V5ZY-3GP

78.47593.41L

1 2

ZZ.CON2C.XX1

1 2

ZZ.CON2C.XX1

1 2

ZZ.CON2C.XX1

Condition Voltage

H : Auto PWM/SKIP 2.2V(Min)~

*

L : PWM fixed (300KHz) ~0.3V(Max)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

TPS5130 1D2V/1D8V2D5V/ (1/2)

Bolsena-E SA

45 58Thursday, October 13, 2005

DCBATOUT_5130DCBATOUT

G75

GAP-CLOSE-PWR

GAP-CLOSE-PWR G85

G85

GAP-CLOSE-PWR

GAP-CLOSE-PWR G77

G77

GAP-CLOSE-PWR

GAP-CLOSE-PWR G84

G84

GAP-CLOSE-PWR

GAP-CLOSE-PWR G83

G83

GAP-CLOSE-PWR

GAP-CLOSE-PWR G76

G76

GAP-CLOSE-PWR

GAP-CLOSE-PWR G82

G82

GAP-CLOSE-PWR

GAP-CLOSE-PWR G86

G86

GAP-CLOSE-PWR

G80

GAP-CLOSE

G81

GAP-CLOSE

GAP-CLOSE G24

G24

GAP-CLOSE

of

A

5

A

4

3

2

1

TI TPS5130 for 2D5V, 1D2V, 1D8V

(1D2V=>CH1 , 1D8V=>CH2 , 2D5V =>CH3)

DCBATOUT_5130

D D

5130_OUT1U45 5130_LL145,58

5130_OUT1D45

5130_OUT1U 5130_LL1

5130_OUT1D

U72

AO4422-1-GP

GD

4 5

U71

AO4422-1-GP

GD

4 5

678

DDD

Imax=9.3A

SSS

Rdson=19.6~24mohm

123

678

DDD

SSS

123

12

C845

C845 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

L32

1 2

IND-3D3UH-57GP

SE220U4VDM-3GP

12

TC12

C C

12

C839

678

DDD

U66

AO4422-1-GP

Imax=9.3A

SSS

GD

SSS

GD

Rdson=19.6~24mohm

123

4 5

5130_OUT2U45 5130_LL245,58

B B

5130_OUT2D45

5130_OUT3U45 5130_LL345,58

5130_OUT3D45

5130_OUT2U

5130_LL2

AO4422-1-GP

5130_OUT2D

AO4422-1-GP

5130_OUT3U

5130_LL3

AO4422-1-GP

5130_OUT3D

678

DDD

U68

SSS

GD

SSS

GD

123

4 5

678

DDD

U74

SSS

GD

SSS

GD

123

4 5

678

DDD

U75

SSS

GD

SSS

GD

123

4 5

Imax=9.3A Rdson=19.6~24mohm

C839 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

L31

1 2

IND-4D7UH-88-GP

12

C849

C849 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

L33

1 2

IND-4D7UH-88-GP

12

SC10U35V0ZY-1GP

1D2V_PWR

DCBATOUT_5130

12

1D8V_PWR

SE220U4VDM-3GP

12

DCBATOUT_5130

12

2D5V_PWR

SE220U4VDM-3GP

12

C846

1D2V Iomax=5A OCP>10A

KEMET, NTD:10.5 (Q1) ESR=25mohm Iripple=2.2A

7.3*4.3*1.9

C840

C840 SC10U35V0ZY-1GP

SC10U35V0ZY-1GP

1D8V Iomax=5A OCP>10A

TC11

C847

C847 SC10U35V0ZY-1GP

SC10U35V0ZY-1GP

2D5V Iomax=9A OCP>18A

TC13

1D2V_PWR 1D2V_S0

1D8V_PWR 1D8V_S5

G15

1 2

GAP-CLOSE-PWR

GAP-CLOSE-PWR G17

G17

1 2

GAP-CLOSE-PWR

GAP-CLOSE-PWR G18

G18

1 2

GAP-CLOSE-PWR

GAP-CLOSE-PWR G21

G21

1 2

GAP-CLOSE-PWR

GAP-CLOSE-PWR G20

G20

1 2

GAP-CLOSE-PWR

GAP-CLOSE-PWR G22

G22

1 2

GAP-CLOSE-PWR

GAP-CLOSE-PWR G23

G23

1 2

GAP-CLOSE-PWR

GAP-CLOSE-PWR G19

G19

1 2

GAP-CLOSE-PWR

G16

1 2

GAP-CLOSE-PWR

GAP-CLOSE-PWR G13

G13

1 2

GAP-CLOSE-PWR

GAP-CLOSE-PWR G10

G10

1 2

GAP-CLOSE-PWR

GAP-CLOSE-PWR G14

G14

1 2

GAP-CLOSE-PWR

GAP-CLOSE-PWR G12

G12

1 2

GAP-CLOSE-PWR

GAP-CLOSE-PWR G9

G9

1 2

GAP-CLOSE-PWR

GAP-CLOSE-PWR G11

G11

1 2

GAP-CLOSE-PWR

G31

1 2

GAP-CLOSE-PWR

GAP-CLOSE-PWR G29

G29

1 2

GAP-CLOSE-PWR

GAP-CLOSE-PWR G30

G30

1 2

GAP-CLOSE-PWR

GAP-CLOSE-PWR G26

G26

1 2

GAP-CLOSE-PWR

GAP-CLOSE-PWR G28

G28

1 2

GAP-CLOSE-PWR

GAP-CLOSE-PWR G27

G27

1 2

GAP-CLOSE-PWR

GAP-CLOSE-PWR G25

G25

1 2

GAP-CLOSE-PWR

2D5V_S32D5V_PWR

(Power Team)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

TPS5130 1D2V/1D8V2D5V/ (2/2)

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

46 58Thursday, October 13, 2005

SA

of

A

MAX1909_MODE

12

R250

R250 49K9R2F-L-GP

49K9R2F-L-GP

V (MODE) >=2.8V = 4Cell V (MODE) =1.8V = 3Cell

Q14

2N7002PT-U

D

3S34

3S2P_I34

CHG_ON#34

From KBC

D

1

G

3D3V_S5

12

2 3

D

S

1

G

Icharge=3.2A

2 3

S

12

R224

R224 100KR2J-1-GP

100KR2J-1-GP

1

G

2 3

MAX1909_ICTL

D

S

Pre charge=0.3A

PRE_CHG34

G41

AD_IA34

I Source = 4.5A ---> V (IINP) = 2.7V I Source = 3.42A ---> V (IINP) = 2.05V

1 2

GAP-CLOSE-PWR

AC_IN#34

S

R225

330KR2F-L-GP

Q9

2N7002PT-U

2N7002PT-U Q10

Q10

12

1

G

2 3

R235

20KR2F-L-GP

TSLCX14MTC-L-U

D

1

G

Q13

2 3

2N7002PT-U

AC_IN Threshold 2.089V Max. AC_IN > 2.089V --> AC DETECT

ACOK is 17.8V

AD+

12

R384

R384 100KR2F-L1-GP

100KR2F-L1-GP

MAX1909_ACIN

12

R385

R385 13K3R2F-L1-GP

13K3R2F-L1-GP

D15

12

R237

R237 49K9R2F-L-GP

49K9R2F-L-GP

21

12

C461

C461 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

MAX1909_LDO

R232

100KR2F-L1-GP

12

AD+

CH521S-30-GP-U

MAX1909_REF

Icharge=3.5A

12

R234

R234 2K94R2F-GP

2K94R2F-GP

D

2N7002PT-U

2N7002PT-U Q11

Q11

S

SB 0202

12

MAX1909_IINP

R236

R236 73K2R2F-GP

73K2R2F-GP

CELL is 4 Cell

12

3D3V_AUX_S5

U41F

147

1312

12

R233

R233 37K4R2F-1-GP

37K4R2F-1-GP

4S1P_I34

1

G

Icharge=1.4A

From Battery Connector

12

R239

R239 10KR2J-2-GP

10KR2J-2-GP

12

C479

SCD1U16V3KX-3GP

C477

SCD1U16V3KX-3GP

SC1U10V3KX-3GP

SCD1U16V3KX-3GP

MAX1909_LDO

MAX1909_ACOKMAX1909_ACOKMAX1909_ACOKMAX1909_ACOK

12

C854

D

8

D

7

D

6

2 3

12

AO4433-GP

12

D

2N7002PT-U

2N7002PT-U Q12

Q12

S

12

R557

R557 100KR2J-1-GP

100KR2J-1-GP

R555

R555 150KR2J-GP

150KR2J-GP

U48

S

1

S

2

S

3

GD

45

SCD1U25V3ZY-3GP

R238

R238 10KR2J-L2-GP

10KR2J-L2-GP

MAX1909_CCV MAX1909_CCI MAX1909_CCS

12

C480

SCD01U50V3KX-4GP

C478

SCD01U50V3KX-4GP

SC1U25V5ZY-4GP

Close to MAX1909 pin 24

C452

MAX1909_PDS AD+_TO_SYS MAX1909_DC_IN

MAX1909_VCTL

MAX1909_ICTL MAX1909_MODE

MAX1909_IINP MAX1909_CLS

MAX1909_ACOK

PKPRES#

AD+_TO_SYS

12

C677

12

U24

27 24

1

11 10

7

3 8 9

6

5

13 12 14

MAX8725ETI-GP-U

Rx

R399 D01R2512F-4-GPR399 D01R2512F-4-GP

1 2

G58

GAP-CLOSE-PWR

1 2

12

MAX1909_CSSP

26

CSSP

PDS SRC DCIN

VCTL ICTL MODE

ACIN IINP CLS

ACOK

PKPRES

CCV CCI CCS

MAX1909_REF

SC1U10V3KX-3GP

12

C467

Rx

DCBATOUT

For EMI

G57

GAP-CLOSE-PWR

1 2

MAX1909_CSSN

25

CSSN

22

DHIV

28

PDL

2

LDO

21

DLOV

23

DHI

20

DLO

19

PGND

29

PGND

18

CSIP

17

CSIN

16

BATT

15

GND

90W ADAPTER

AD+_TO_SYS

12

MAX1909_DHIV

MAX1909_DLOV

MAX1909_DHI

MAX1909_DLO

MAX1909_LDO

C454

C454 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

SC1U10V3KX-3GP

12

MAX1909_CSIP

MAX1909_CSIN

Near MAX1909 Pin 2

1 2

R220

R220 33R2J-2-GP

33R2J-2-GP

Near MAX1909 Pin 21

C468

SC1U10V3KX-3GP

From Battery Connector

-1 0302

C453

C453 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

REF

4

V_REF :4.2235V (<500uA)

12

R228

R228 49K9R2F-L-GP

49K9R2F-L-GP

MAX1909_CLS

12

R226

R226 63K4R3F-GP

63K4R3F-GP

64.63425.55L

ISOURCE_MAX = (0.075/Rx)*(VCLS/VREF) TOTAL_POWER : Adapter=90W,Total_Power=79.7W

12

C440

C440 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

C460

AO4422-1-GP

84.04422.B37

U21

BAT+SENSE 48

MAX1909_PDL

R219 DUMMY-R3R219 DUMMY-R3

1 2

45

GD

DDD

678

DDD

GD

4 5

12

123

SSS

U20

AO4411-1-GP

84.04411.B37

CHG_PWR-2

SSS

123

R215

R215 DUMMY-R3

DUMMY-R3

SCD1U25V3ZY-3GP

-1 0310

G40 GAP-CLOSEG40 GAP-CLOSE

1 2

G32 GAP-CLOSEG32 GAP-CLOSE

1 2

(Power Team)

1 2 3 4 5

12

C447

CHG_PWR-2 58

L34

1 2

IND-15UH-41-GP

BT+

12

DY

C449

C449 SCD1U25V3ZY-3GP

U22

S

D

S

D

S

S S

S GD

GD

8

D

7

D

6

AO4433-GP

DCBATOUT

12

C439

SC10U35V0ZY-GP

CHG_PWR-3 58

-1 0310

R221

CHG_PWR-3

BAT_THERMAL34,48

R221

1 2

D015R2512F-5-GP

G38

1 2

GAP-CLOSE-PWR

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet

Date: Sheet

Bolsena-E

SCD1U25V3ZY-3GP

DY

12

G39

1 2

R230

0R0402-PAD

CHARGER MAX8725

C448

SC10U25V6KX-1GP

GAP-CLOSE-PWR

SB 0127

MAX1909_LDO

12

R231

R231 68KR2F-GP

68KR2F-GP

12

PKPRES#

12

R227

R227 100KR2J-1-GP

100KR2J-1-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

C455

SC10U25V0KX-3GP

47 58Thursday, October 13, 2005

BT+

C462

12

of

SC10U25V0KX-3GP

SA

A

B

C

D

E

Adaptor in to generate DCBATOUT

D29

K A

DY

MMPZ5252BPT-GP

U45

S

D

S

1 2 3 4 5

3

SCD1U50V3ZY-GP

D

S

S S

S GD

GD

AO4433-GP

8

D

7

D

6

ID = -10A/70deg Rds(ON) = 24mohm SO-8

R556

1 2

SC1KP50V2JN-2GP

C852

1

27R3F-GP

12

2

12

5V_AUX_S5

2

3

1 2

SC1KP50V2JN-2GP

C853

BAV99PT-GP-U

D41

DY

R553

27R3F-GP

12

C850

12

C657

SCD1U50V3ZY-GP

12

AD_JK

R2

R2 1KR2J-1-GP

1KR2J-1-GP

12

C656

SCD1U50V3ZY-GP

R1

1

IN

R379

GND

200KR2J-L1-GP

2

OUT

R379

Q2

CHDTA124EUPT-GP

OUT

3

R2

CHDTC124EU-1GP

Q1

2

GND

IN

1

R2

R1

3

BATTERY CONNECTOR

BAT_SCL_534

BT+

Put close to battery connector

BAT_SDA_534

BAT_THERMAL34,47

BAT+SENSE47

1 2

12

R554

12

C7

SCD1U50V3ZY-GP

0R0402-PAD

AD+_2

12

R380

R380 100KR2J-1-GP

100KR2J-1-GP

1

BAV99PT-GP-U

DY

SCD1U50V3ZY-GP

12

C851

DY

D42

DC1

4 4

3 3

2 2

DC1

DC-JACK75-U1-GP

22.10037.701

ME : 22.10037.701 2nd:22.10037.B02

4

1

2

3 5

6 MH1

AD_OFF34

BTSMCLK BTSMDATA

12

EC68

SC10P50V2JN-1

AD+

12

C666

C666 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

12

EC66

1 2

3 4 5 6 7

AMP-CON7-S-GP

20.80604.007

ME :20.80604.007 2nd:20.80269.007

SC10P50V2JN-1

BAT1

DCBATOUT

DY

C435

SCD1U10V2KX-LGP

VCC

DY

HTH

B

12

R213

R213 1MR2J-1-GP

1MR2J-1-GP

DY

12

DY

R212

R212 15KR2F-GP

15KR2F-GP

DY

12

R211

R211 110KR2F-GP

110KR2F-GP

U19

HTH

1

HTH

2

GND LTH3RESET#/RESET

G680LT1F-GP

Output type: Open-Drain RESET#

Low3 Circuit :

L3# at 11.25V

1 1

A

MAX1999_LDO5

12

12.78V (High) Turn On

11.25V (Low)

5 4

LOW3_OFF 22

C

Turn Off

D

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet

AD/BATT CONN

A3

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

48 58Thursday, October 13, 2005

of

E

of

SA

5

PEG_RXP0 PEG_RXN0

PCIE TEST PADS

PCIE TEST POINTS MUST BE WITHIN 250 MILS OF THE ASIC BALL WITH POSITIVE AND NEGATIVE SIGNALS THE SAME DISTANCE

D D

TP108TPAD28 TP108TPAD28

1

TP90TPAD28 TP90TPAD28

1

C C

PEG_RXP[15..0]12 PEG_RXN[15..0]12

PEG_TXP[15..0]12 PEG_TXN[15..0]12

REFER TO PCI EXPRESS DESIGN GUIDE FOR RECOMMENDED AC COUPLING CAPS PLACEMENT ALONG THE TX INTERCONNECT

B B

PCIE SIGNALS CONNECT TO ROOT COMPLEX

PEG_RXP[15..0] PEG_RXN[15..0] PEG_TXP[15..0] PEG_TXN[15..0]

GFX_CLK3 GFX_CLK#3

LPC_RST#13,17,34,37 VGA_GPIO850

R107

1 2

0R2J-GP

1 2

R103

10KR2F-2-GP

PEG_RXP1 PEG_RXN1

PEG_RXP2 PEG_RXN2

PEG_RXP3 PEG_RXN3

PEG_RXP4 PEG_RXN4

PEG_RXP5 PEG_RXN5

PEG_RXP6 PEG_RXN6

PEG_RXP7 PEG_RXN7

PEG_RXP8 PEG_RXN8

PEG_RXP9 PEG_RXN9

PEG_RXP10 PEG_RXN10

PEG_RXP11 PEG_RXN11

PEG_RXP12 PEG_RXN12

PEG_RXP13 PEG_RXN13

PEG_RXP14 PEG_RXN14

PEG_RXP15

PEG_RXN15

AG_RST#_1 PCIE_TEST

PERSTB_MASK

AJ31

AH31

AH30

AG30

AG32

AF32

AF31 AE31

AE30 AD30

AD32 AC32

AC31 AB31

AB30 AA30

AA32

W31

W30

AL28 AK28

AG24

AA24

AF24

U32

U31 T31

T30 R30

R32 P32

P31 N31

Y32

Y31

V30

V32

4

U54A

PCIE_RX0P PCIE_RX0N

PCIE_RX1P PCIE_RX1N

PCIE_RX2P PCIE_RX2N

PCIE_RX3P PCIE_RX3N

PCIE_RX4P PCIE_RX4N

PCIE_RX5P PCIE_RX5N

PCIE_RX6P PCIE_RX6N

PCIE_RX7P PCIE_RX7N

PCIE_RX8P PCIE_RX8N

PCIE_RX9P PCIE_RX9N

PCIE_RX10P PCIE_RX10N

PCIE_RX11P PCIE_RX11N

PCIE_RX12P PCIE_RX12N

PCIE_RX13P PCIE_RX13N

PCIE_RX14P PCIE_RX14N

PCIE_RX15P PCIE_RX15N

Clock

PCIE_REFCLKP PCIE_REFCLKN

PERSTB PCIE_TEST

PERSTB_MASK

PART 1 OF 7

P

P C

C I

I

-

E

E X

X P

P R

R E

E S

S S

S

I

I N

N T

T E

E R

R F

F A

A C

C E

E

Tie To VSS

M52P:71.0M52P.A0U

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

PCIE_TX8P PCIE_TX8N

PCIE_TX9P PCIE_TX9N

PCIE_TX10P PCIE_TX10N

PCIE_TX11P PCIE_TX11N

PCIE_TX12P PCIE_TX12N

PCIE_TX13P PCIE_TX13N

PCIE_TX14P PCIE_TX14N

PCIE_TX15P PCIE_TX15N

Calibration

PCIE_CALRN PCIE_CALRP

PCIE_CALI

71.0M52P.00U

AK27 AJ27

AJ25 AH25

AH28 AG28

AG27 AF27

AF25 AE25

AE28 AD28

AD27 AC27

AC25 AB25

AB28 AA28

AA27 Y27

Y25 W25

W28 V28

V27 U27

U25 T25

T28 R28

R27 P27

PCIE_CALRN_VGA

AE24

PCIE_CALRP_VGA

AD24

PCIE_CALI_VGA

AB24

FOR M26X PCIE_CALRN = 100R PCIE CALRP = 150R PCIE CALI = 10K FOR M52P,M54P,M56P PCIE_CALRN = 2K PCIE CALRP = 562R PCIE CALI = 1.47K

3

C219 SCD1U16V2ZY-2GPC219 SCD1U16V2ZY-2GP

1 2

C220 SCD1U16V2ZY-2GPC220 SCD1U16V2ZY-2GP

1 2

C200 SCD1U16V2ZY-2GPC200 SCD1U16V2ZY-2GP

1 2

C201 SCD1U16V2ZY-2GPC201 SCD1U16V2ZY-2GP

1 2

C217 SCD1U16V2ZY-2GPC217 SCD1U16V2ZY-2GP

1 2

C218 SCD1U16V2ZY-2GPC218 SCD1U16V2ZY-2GP

1 2

C198 SCD1U16V2ZY-2GPC198 SCD1U16V2ZY-2GP

1 2

C199 SCD1U16V2ZY-2GPC199 SCD1U16V2ZY-2GP

1 2

C215 SCD1U16V2ZY-2GPC215 SCD1U16V2ZY-2GP

1 2

C216 SCD1U16V2ZY-2GPC216 SCD1U16V2ZY-2GP

1 2

C196 SCD1U16V2ZY-2GPC196 SCD1U16V2ZY-2GP

1 2

C197 SCD1U16V2ZY-2GPC197 SCD1U16V2ZY-2GP

1 2

C213 SCD1U16V2ZY-2GPC213 SCD1U16V2ZY-2GP

1 2

C214 SCD1U16V2ZY-2GPC214 SCD1U16V2ZY-2GP

1 2

C194 SCD1U16V2ZY-2GPC194 SCD1U16V2ZY-2GP

1 2

C195 SCD1U16V2ZY-2GPC195 SCD1U16V2ZY-2GP

1 2

C211 SCD1U16V2ZY-2GPC211 SCD1U16V2ZY-2GP

1 2

C212 SCD1U16V2ZY-2GPC212 SCD1U16V2ZY-2GP

1 2

C192 SCD1U16V2ZY-2GPC192 SCD1U16V2ZY-2GP

1 2

C193 SCD1U16V2ZY-2GPC193 SCD1U16V2ZY-2GP

1 2

C209 SCD1U16V2ZY-2GPC209 SCD1U16V2ZY-2GP

1 2

C210 SCD1U16V2ZY-2GPC210 SCD1U16V2ZY-2GP

1 2

C190 SCD1U16V2ZY-2GPC190 SCD1U16V2ZY-2GP

1 2

C191 SCD1U16V2ZY-2GPC191 SCD1U16V2ZY-2GP

1 2

C207 SCD1U16V2ZY-2GPC207 SCD1U16V2ZY-2GP

1 2

C208 SCD1U16V2ZY-2GPC208 SCD1U16V2ZY-2GP

1 2

C188 SCD1U16V2ZY-2GPC188 SCD1U16V2ZY-2GP

1 2

C189 SCD1U16V2ZY-2GPC189 SCD1U16V2ZY-2GP

1 2

C205 SCD1U16V2ZY-2GPC205 SCD1U16V2ZY-2GP

1 2

C206 SCD1U16V2ZY-2GPC206 SCD1U16V2ZY-2GP

1 2

C186 SCD1U16V2ZY-2GPC186 SCD1U16V2ZY-2GP

1 2

C187 SCD1U16V2ZY-2GPC187 SCD1U16V2ZY-2GP

1 2

R110 2KR2F-3-GPR110 2KR2F-3-GP

1 2

R111 562R3F-GPR111 562R3F-GP

1 2

R108 1K47R3F-GPR108 1K47R3F-GP

1 2

PEG_TXP0 PEG_TXN0

PEG_TXP1 PEG_TXN1

PEG_TXP2 PEG_TXN2

PEG_TXP3 PEG_TXN3

PEG_TXP4 PEG_TXN4

PEG_TXP5 PEG_TXN5

PEG_TXP6 PEG_TXN6

PEG_TXP7 PEG_TXN7

PEG_TXP8 PEG_TXN8

PEG_TXP9 PEG_TXN9

PEG_TXP10 PEG_TXN10

PEG_TXP11 PEG_TXN11

PEG_TXP12 PEG_TXN12

PEG_TXP13 PEG_TXN13

PEG_TXP14 PEG_TXN14

PEG_TXP15 PEG_TXN15

1D2V_S0

23 22 21 20

MEM_ID0

MEM_ID2

MEM_ID1

11

0

1 1

000

MEM_ID3

0

111

11

00

1

0

1

0

1

0 0

2

STRAP_B_PTX_PWRS_ENB

STRAP_B_PTX_DEEMPH_EN

RSVD REVERSE LANES DEBUG ACCESS

STRAP_FORCE_COMPLIANCE sets the desired PCIE PLL bandwidth for M5x parts.

COMMON MODE RANGE RSVD

DEBUG ACCESS FORCE_COMPLIANCE

ROMIDCFG(3:0) GPIO[9,13:11]

MEMORY APERTURE SIZE

RSVD NO STRAP FUNCTION

NO STRAP FUNCTION

MEM

SIZE

0

64M

0

64M 16M*16

0

128M 16M*16

0

256M 32M*16

0

128M 16M*16 x4

0

256M

0

128M 16M*16

0

256M 32M*16

16M*16

VENDOR

Infineon Hynix Samsung0 Samsung Infineon Infineon Hynix Hynix

PIN DESCRIPTION OF RECOMMENDED SETTING

TRANSMITTER POWER SAVINGS ENABLE

- FULL TX OUTPUT SWING TRANSMITTER DE-EMPHASIS ENABLE

DEPENDS ON PCIE CHIPSET BEING USED FOR M26X,M5X INSTALL WITH ATI RS480,RS400,RX480, RC410,RS482 CHIPSETS FOR M26X ONLY DO NOT INSTALL WITH INTEL 915PM CHIPSET

NO ATI FEATURE ENABLED

NOT REVERSED LANE (M26X) NO DEBUG ACCESS (M52P,M54P,M56P)

DO NOT FORCE COMPLIANCE STATE QUICKLY (M26X) NO ATI FEATURE ENABLED (M52P,M54P,M56P)

NORMAL RANGE (M26X)

NO ATI FEATURE ENABLED (M52P,M54P,M56P) NO DEBUG ACCESS (M26X) DON'T FORCE COMPLIANCE STATE(M52P,M54P,M56P)

SERIAL FLASH ROM TYPE (M26X,M52P,M54P,M56P)

- SERIAL M25P10 ROM IF NO ROM

GPIO11(M26X) AND GPIO12,13(M52,M54,M56) SET MEMORY APERTURE SIZE SEE M26X,M54X,M56X DATA BOOK FOR MEMORY,FRAME BUFFER APERATURE SETTINGS

MEMORY TYPE AND SPEED SELECT

ATI FEATURE NOT ENABLED (M52P,M54P,M56P) NO STRAP (M26X)

VGA_GPIO050 VGA_GPIO150 VGA_GPIO250 VGA_GPIO350 VGA_GPIO450 VGA_GPIO550 VGA_GPIO650

VGA_GPIO1150 VGA_GPIO1250 VGA_GPIO1350 VGA_GPIO950

MEM_ID350 MEM_ID250 MEM_ID150

MEM_ID050 DAC2_HSY50 DAC2_VSY50 GENERICC50

DY

DY DY

DY

GPIO[9,13:11]=0010 for 256M

DY

DY DY

DY

128V

DY

DY DY

DY

PCIE_TEST

DY

GPIO(3:2)

GPIO4

GPIO5

GPIO6

GPIO8

GPIO[13:11]

MEMIDMEM_TYPE

H2SYNC V2SYNC GENERICC

PCIE_TESTRSVD

CHIPs x2

x2 x4 x4

x432M*16 x4 x4

GPIO0

GPIO1

(3:0)

1

RECOMMENDEDSTRAPS

INSTALL 10K RESISTOR

DO NOT INSTALL 10K RESISTORS

DO NOT INSTALL 10K RESISTOR

INSTALL 10K RESISTORS

DO NOT INSTALL 10K RESISTORS

1011

TBD

DO NOT INSTALL 10K RESISTORS

R62 10KR2J-2-GPR62 10KR2J-2-GP

1 2

R412 10KR2J-2-GPR412 10KR2J-2-GP

1 2

R409 10KR2J-2-GP

1 2

R411 10KR2J-2-GP

1 2

R402 10KR2J-2-GP

1 2

R403 10KR2J-2-GPR403 10KR2J-2-GP

1 2

R408 10KR2J-2-GP

1 2

R58 10KR2J-2-GP

1 2

R67 10KR2J-2-GP

1 2

R397 10KR2J-2-GP

1 2

R59 10KR2J-2-GPR59 10KR2J-2-GP

1 2

R56 10KR2J-2-GP

1 2

R60 10KR2J-2-GP

1 2

R65 10KR2J-2-GP

1 2

R64 10KR2J-2-GP

1 2

R63 10KR2J-2-GP

1 2

R66 10KR2J-2-GP

1 2

R88 10KR2J-2-GP

1 2

R89 10KR2J-2-GP

1 2

R100 10KR2J-2-GP

1 2

R113 10KR2J-2-GP

1 2

TBD

3D3V_S0

When no ROM is attached, GPIO[9] is set to 0. GPIO[13:12] is used to select the frame buffer aperture size. GPIO[13:12] = 00: 128M frame buffer, same as ROM strap 00 GPIO[13:12] = 01: 256M frame buffer, same as ROM strap 01 GPIO[13:12] = 10: 64M frame buffer, same as ROM strap 10

A A

5

4

3

2

GPIO[13:12] = 11: reserved, same as ROM strap 11

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet

ATI M5X-P PCIE 1/4

A3

Taipei Hsien 221, Taiwan, R.O.C.

AG1

49 58Thursday, October 13, 2005

of

1

of

SA

5

[USE ICS MK1726-08]

12

R39

C36

1MR2J-1-GP

R57

R57 10KR2J-2-GP

10KR2J-2-GP

1 2

VGA_ALERT#

1MR2J-1-GP

12

C64

C64 SC27P50V2JN-2-GP

SC27P50V2JN-2-GP

D D

DVPCNTL,DVPDATA[23..0] ARE CONFIGURED FOR +3.3V SIGNALING MODE ON THIS DESIGN

C C

FOR M26X CONNECT TO +1.8V OR VSS TO DEFINE DVO SIGNAL LEVEL FOR M52P,M54P,M56P NOT CONNECTED

ANY UNUSED GPIO CAN OPTIONALLY BE PANEL TYPE CONFIG STRAPS

3D3V_S0

B B

A A

MK1726_XI

X1

X1 XTAL-27MHZ-31-GP

XTAL-27MHZ-31-GP

1 2

MK1726_XO

3D3V_S0

R30

0R2J-GP

DY

1 2

SS_SEL

R31

0R2J-GP

DY

1 2

Modulation Rate

SEL1 SEL0

L

L LH H

L H

ANY UNUSED GPIO CAN OPTIONALLY BE MEMORY TYPE CONFIG STRAPS

499R2F-1-GP

FOR M26X PVDD CONNECT TO +1.8V FOR M52P,M54P,M56P CONNECT TO +2.5V

2D5V_S0

FOR M26X MPVDD CONNECT TO +1.8V FOR M52P,M54P,M56P CONNECT TO VDDC

No Spread

H

3D3V_S0

R77

R78

0R3J-3-GP

VGA_CORE_S0

VOLTAGE DIVIDER 3.3V MEM SS MODOUT TO 1.2V XTALIN/OUT

U5

1 2 3

VGA_GPIO16

X1/CLK GND SO SSCLK4REFCLK

MK1726-08SLF-GPU

VDD

PD#

X2

adjust SWING at 1.2v

Center Spread +-0.5%

+-1.0% +-1.5%

EDID_DAT13,16 EDID_CLK13,16

VGA_GPIO049 VGA_GPIO149 VGA_GPIO249 VGA_GPIO349 VGA_GPIO449

12

VGA_GPIO849 VGA_GPIO949

SCD1U10V2KX-LGP

12

C107

PLACE VREF DIVIDER AND CAP CLOSE TO ASIC

R437

1 2

R79

1 2

0R3J-3-GP

SC10U10V5KX-2GP

VGA_GPIO549 VGA_GPIO649

VGA_GPIO1149 VGA_GPIO1249 VGA_GPIO1349

GPIO_PWRCNTL56

VGA_LOCAL_DP22 VGA_LOCAL_DN22

C708

adjust SWING at 1.2v

5

4

8 7

SS_PD

6

MK1726_REF

5

XTALIN_M24

MEM_ID349 MEM_ID249 MEM_ID149 MEM_ID049

TP82TPAD28 TP82TPAD28

12

C102

C101

12

SC1U6D3V2KX-GP

SCD1U10V2KX-LGP

3D3V_S0

4

3D3V_S0

12

R50

180R2F-1-GP

12

R44

105R3F-2-GP

3D3V_S0

4

1

2 3

1

VGA

R82

1 2

12

C126

C126 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

VGA_MPVDD

R99

1 2

1KR2J-1-GP

12

C71

TC2

SCD1U25V3ZY-3GP

SC22U6D3V5MX-2GP

R51

R51 0R2J-GP

0R2J-GP

DY

1 2

R423 1KR2J-1-GPR423 1KR2J-1-GP

RN11

RN11 SRN4K7J-8-GP

SRN4K7J-8-GP

EDID_DAT EDID_CLK

TP7TPAD30 TP7TPAD30

0R2J-GP

VGA_ALERT#

VGA_PVDD

XTALIN_M24

VGA_TESTEN

R61

1 2

10KR2J-2-GP

DY

TP84TPAD30 TP84TPAD30 TP83TPAD30 TP83TPAD30

POW_SW

VGA_GPIO16

VGA_VREF

TP89TPAD28 TP89TPAD28

U54B

AG10

AF10

AE10

AF13

AE13

AG12 AH12

AJ14

AH14

AL26

1

AM26

AG14 AG22

AK17

AJ19

AF18 AH17 AG17 AG19 AH19

AG8 AH7 AG9 AH8

AH9

AH6

AG7

AG1 AG2 AG3 AH2 AH3

AM3

AG4 AH4 AG5

AH5

AG6 AD4

AD2 AD1 AD3 AC1 AC2 AC3

AC6 AC5 AC4

AD5

AC8

AC7

AJ8

AF8 AF7 AE9

AF9

AK4 AL4

AF2 AF1 AF3

AJ2 AJ1 AK2 AK1 AK3 AL2 AL3

AE6 AF4 AF5

AJ3 AJ4

AF6 AE7

AB2

AB3 AB4 AB5

AB8 AA8 AB7 AB6

A6 A5

GPIO_34 GPIO_33 GPIO_32 GPIO_31 GPIO_30 GPIO_29 GPIO_28 GPIO_27 GPIO_26 GPIO_25 GPIO_24 GPIO_23 GPIO_22 GPIO_21 GPIO_20 GPIO_19 GPIO_18

NC_DVOVMODE_0 NC_DVOVMODE_1

DVPCNTL_0 DVPCNTL_1 DVPCNTL_2 DVPCLK DVPDATA_0 DVPDATA_1 DVPDATA_2 DVPDATA_3 DVPDATA_4 DVPDATA_5 DVPDATA_6 DVPDATA_7 DVPDATA_8 DVPDATA_9 DVPDATA_10 DVPDATA_11 DVPDATA_12 DVPDATA_13 DVPDATA_14 DVPDATA_15 DVPDATA_16 DVPDATA_17 DVPDATA_18 DVPDATA_19 DVPDATA_20 DVPDATA_21 DVPDATA_22 DVPDATA_23

GPIO_0

General

GPIO_1

Purpose

GPIO_2

I/O

GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7_BLON GPIO_8 GPIO_9 GPIO_10 GPIO_11 GPIO_12 GPIO_13 GPIO_14 GPIO_15 GPIO_16 GPIO_17 NC_AB6

VREFG DPLUS

Thermal

Thermal Diode

Diode

DMINUS PVDD

PLL &

PLL & XTAL

XTAL

PVSS MPVDD

MPVSS XTALIN

XTALOUT PLLTEST TESTEN

Test

ROMCSb

ROM

LVSSR_1 LVSSR_2

LVDS PLL

LVSSR_3

and I/O

LVSSR_4

GND

LVSSR_5 LVSSR_6 LVSSR_7

3

PART 2 OF 7

Integrated

Integrated TMDS

TMDS

V

V I

I D

D E

E O

O

&

Expand GPIO

M

M U

U L

L T

T I

I M

M E

E D

D I

I A

A

DAC / CRT

VIP Host/External TMDS

DAC2 (TV/CRT2)

Monitor

Monitor Interface

Interface

External

External SSC

SSC

LVDS PLL

LVDS PLL and I/O

and I/O GND

GND

3

TXCM

TXCP TX0M

TX0P TX1M

TX1P TX2M

TX2P TX3M

TX3P TX4M

TX4P TX5M

TX5P TPVDD TPVSS

TXVDDR_1 TXVDDR_2 TXVDDR_3 TXVDDR_4

TXVSSR_1 TXVSSR_2 TXVSSR_3 TXVSSR_4 TXVSSR_5

HSYNC VSYNC

GENERICA GENERICB

RSET

AVDD_1 AVDD_2

AVSSQ AVSSN_1 AVSSN_2

VDD1DI

VSS1DI

H2SYNC

V2SYNC

COMP

R2SET

A2VDD_1 A2VDD_2

A2VSSN_1 A2VSSN_2

NC_A2VDDQ

A2VSSQ

VDD2DI

VSS2DI

HPD1

DDC1DATA

DDC1CLK

DDC2DATA

DDC2CLK

DDC3DATA

DDC3CLK

GENERICC

LPVSS

LVSSR_10

LVSSR_9 LVSSR_8

AL9 AM9

AK10 AL10

AL11 AM11

AL12 AM12

AK9

Placed close to ASIC end.

AJ9 AK11

AJ11 AK12

AJ12

VGA_TPVDD

AM8 AL8 AJ6

AK6 AL6

VGA_TXVDDR

AM6

AJ7 AK7 AL7 AM7 AK8

AK24

R

AM24

G

AL24

B

AJ23 AJ22 AK22

VGA_GENERICB

AF23

VGA_CRT_RSET

AL22 AL25

AM25 AK23

AK25 AJ24

AM23 AL23 AK15

R2

AM15

G2

AL15

B2

AF15 AG15

AJ15

Y

AJ13

C

AH15

VGA_TV_RSET

AK14 AM16

AL16 AM17

AL17

VGA_A2VDDQ

AL14 AK13

VGA_VDD2DI

AJ16

C125

AJ17

SC1U6D3V2KX-GP

1

AF11

R80 100KR2J-1-GPR80 100KR2J-1-GP

AH22 AH23

AH13 AG13

For DVI

AE12 AF12

For THERMAL SENSOR

AE23 AE18

AF22 AF17 AF21

C697

12

SC1U6D3V2KX-GP

C695

12

SC1U6D3V2KX-GP

VGA_AVDD

VGA_VDD1DI

VGA_A2VDD

12

TP9 TPAD28TP9 TPAD28

C104

SCD1U10V2KX-LGP

12

DIS_HS 15 DIS_VS 15

R104 1KR2F-3-GPR104 1KR2F-3-GP

1 2

R441 499R2F-1-GPR441 499R2F-1-GP

1 2

C714

SC1U6D3V2KX-GP

R438 715R2F-GPR438 715R2F-GP

1

12

FOR M26X GENERICC NO CONNECT OR EXT SPREAD SPECTRUM INPUT FOR M52P,M54P,M56P IT IS GPIO

C714

DAC2_HSY 49 DAC2_VSY 49

1 2

C711

12

TP88TPAD28 TP88TPAD28

SC4D7U6D3V3KX-GP

12

C716

C715

C715 SCD1U10V2KX-LGP

SCD1U10V2KX-LGP

DIS_CRT_DDC_D 15 DIS_CRT_DDC_C 15

GENERICC 49

2

DUAL LINK IS ONLY SUPPORTED ON M56P DO NOT CONNECT TXM,P[3:5] WITH M52P,M54P,M26X

1 2

0R3J-3-GP

C103

C103 SCD1U10V2KX-LGP

SCD1U10V2KX-LGP

C720

12

SC1U6D3V2KX-GP

12

SC4D7U6D3V3KX-GP

SCD1U10V2KX-LGP

1 2

R455 0R3J-3-GPR455 0R3J-3-GP

1 2

C713

SCD1U10V2KX-LGP

12

C718

C710

1 2

12

SC1U6D3V2KX-GP

R449 0R3J-3-GPR449 0R3J-3-GP

For CRT

2

1

R428

0R3J-3-GP

R439

2D5V_S0

R425

1 2

2D5V_S0

12

2D5V_S0

0R3J-3-GP

0R3J-3-GP R447

R447

DAC2 CAN BE TV SIGNALS OR SECONDARY CRT SIGNALS AS CONTROLLED BY AN INTERNAL MUX

0R3J-3-GP

2D5V_S0

Title

Size Document Number Rev

A3

Date: Sheet

2D5V_S0

ATI M5X-P IO 2/4

FOR M26X TPVDD CONNECT TO +1.8V FOR M52P,M54P,M56P CONNECT TO +2.5V

FOR M26X TXVDDR CONNECT TO +1.8V FOR M52P,M54P,M56P CONNECT TO +2.5V

DIS_R 57 DIS_G 57

12

R452150R2F-1-GP R452150R2F-1-GP

R445150R2F-1-GP R445150R2F-1-GP

R446150R2F-1-GP R446150R2F-1-GP

R91150R2F-1-GP R91150R2F-1-GP

R94150R2F-1-GP R94150R2F-1-GP

R90150R2F-1-GP R90150R2F-1-GP

12

Bolsena-E

DIS_B 57

FOR M26X AVDD CONNECT TO +1.8V FOR M52P,M54P,M56P CONNECT TO +2.5V

FOR M26X VDD1DI CONNECT TO +1.8V FOR M52P,M54P,M56P CONNECT TO +2.5V

DIS_LUMA 57 DIS_CRMA 57 DIS_COMP 57

FOR M26X A2VDDQ CONNECT TO +1.8V FOR M52P,M54P,M56P IT IS NO CONNECT

FOR M26X VDD2DI CONNECT TO +1.8V FOR M52P,M54P,M56P CONNECT TO +2.5V

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

SA

50 58Thursday, October 13, 2005

of

SA

5

U54C

Part 3 of 7

M31

DQA_0

M30

DQA_1

D D

C C

B B

A A

L31

DQA_2

L30

DQA_3

H30

DQA_4

G31

DQA_5

G30

DQA_6

F31

DQA_7

M27

DQA_8

M29

DQA_9

L28

DQA_10

L27

DQA_11

J27

DQA_12

H29

DQA_13

G29

DQA_14

G27

DQA_15

M26

DQA_16

L26

DQA_17

M25

DQA_18

L25

DQA_19

J25

DQA_20

G28

DQA_21

H27

DQA_22

H26

DQA_23

F26

DQA_24

G26

DQA_25

H25

DQA_26

H24

DQA_27

H23

DQA_28

H22

DQA_29

J23

DQA_30

J22

DQA_31

E23

DQA_32

D22

DQA_33

D23

DQA_34

E22

DQA_35

E20

DQA_36

F20

DQA_37

D19

DQA_38

D18

DQA_39

B19

DQA_40

B18

DQA_41

C17

DQA_42

B17

DQA_43

C14

DQA_44

B14

DQA_45

C13

DQA_46

B13

DQA_47

D17

DQA_48

E18

DQA_49

E17

DQA_50

F17

DQA_51

E15

DQA_52

E14

DQA_53

F14

DQA_54

D13

DQA_55

H18

DQA_56

H17

DQA_57

G18

DQA_58

G17

DQA_59

G15

DQA_60

G14

DQA_61

H14

DQA_62

J14

DQA_63

C31

MVREFD_0

C30

MVREFS_0

PLACE MVREF DIVIDERS AND CAPS CLOSE TO ASIC

5

MEMORY INTERFACE A

MAA_0 MAA_1 MAA_2 MAA_3 MAA_4 MAA_5 MAA_6 MAA_7 MAA_8

MAA_9 MAA_10 MAA_11 MAA_12 MAA_13 MAA_14 MAA_15

DQMAb_0 DQMAb_1 DQMAb_2 DQMAb_3 DQMAb_4 DQMAb_5 DQMAb_6 DQMAb_7

QSA_0 QSA_1 QSA_2 QSA_3 QSA_4 QSA_5 QSA_6 QSA_7

QSA_0B QSA_1B QSA_2B QSA_3B QSA_4B QSA_5B QSA_6B QSA_7B

write strobe read strobe

ODTA

ODTA1

CLKA0

CLKA0b

CKEA0 RASA0b CASA0b

WEA0b

CSA0b_0 CSA0b_1

CLKA1

CLKA1b

CKEA1 RASA1b CASA1b

WEA1b

CSA1b_0 CSA1b_1

D26 F28 D28 D25 E24 E26 D27 F25 C26 B26 D29 B27 E27 E29 B25 C25

H31 J29 J26 G23 E21 B15 D14 J17

J31 K29 K25 F23 D20 B16 D16 H15

K31 K28 K26 G24 D21 C16 D15 J15

F29 D24

D31 E31

B30 B28 C29 B31 B29

C28

B20 C19

C22 B24 B22 B21 B23

C23

4

Ch-A FOR M52P,M54P,M26X PIN B25 IS MA12 (BA0) PIN C25 IS MA13 (BA1) PIN E29 IS MA15 (BA2) PIN E27 IS MA14 FOR M56P PIN B25 IS MA14 (BA0) PIN C25 IS MA15 (BA1) PIN E29 IS MA13 (BA2) PIN E27 IS MA12

1D8V_S0

12

R71

R71 100R2F-L1-GP-U

100R2F-L1-GP-U

C90

SCD1U10V2KX-LGP

12

R72

R72 100R2F-L1-GP-U

100R2F-L1-GP-U

1D8V_S0

12

R49

R49 100R2F-L1-GP-U

100R2F-L1-GP-U

12

R55

R55 100R2F-L1-GP-U

100R2F-L1-GP-U

SCD1U10V2KX-LGP

C75

SCD1U10V2KX-LGP

12

678

123

PLACE MVREF DIVIDERS AND CAPS CLOSE TO ASIC

12

4

MVREFD1 MVREFS1

MEM_RST

RN10

RN10 SRN4K7J-6-GP

SRN4K7J-6-GP

4 5

MDB0 MDB1 MDB2 MDB3 MDB4 MDB5 MDB6 MDB7 MDB8

MDB9 MDB10 MDB11 MDB12 MDB13 MDB14 MDB15 MDB16 MDB17 MDB18 MDB19 MDB20 MDB21 MDB22 MDB23 MDB24 MDB25 MDB26 MDB27 MDB28 MDB29 MDB30 MDB31 MDB32 MDB33 MDB34 MDB35 MDB36 MDB37 MDB38 MDB39 MDB40 MDB41 MDB42 MDB43 MDB44 MDB45 MDB46 MDB47 MDB48 MDB49 MDB50 MDB51 MDB52 MDB53 MDB54 MDB55 MDB56 MDB57 MDB58 MDB59 MDB60 MDB61 MDB62 MDB63

3

U54D

Part 4 of 7

B12

DQB_0

C12

DQB_1

B11

DQB_2

C11

DQB_3

C8

DQB_4

B7

DQB_5

C7

DQB_6

B6

DQB_7

F12

DQB_8

D12

DQB_9

E11

DQB_10

F11

DQB_11

F9

DQB_12

D8

DQB_13

D7

DQB_14

F7

DQB_15

G12

DQB_16

G11

DQB_17

H12

DQB_18

H11

DQB_19

H9

DQB_20

E7

DQB_21

F8

DQB_22

G8

DQB_23

G6

DQB_24

G7

DQB_25

H8

DQB_26

J8

DQB_27

K8

DQB_28

L8

DQB_29

K9

DQB_30

L9

DQB_31

K5

DQB_32

L4

DQB_33

K4

DQB_34

L5

DQB_35

N5

DQB_36

N6

DQB_37

P4

DQB_38

R4

DQB_39

P2

DQB_40

R2

DQB_41

T3

DQB_42

T2

DQB_43

W3

DQB_44

W2

DQB_45

Y3

DQB_46

Y2

DQB_47

T4

DQB_48

R5

DQB_49

T5

DQB_50

T6

DQB_51

V5

DQB_52

W5

DQB_53

W6

DQB_54

Y4

DQB_55

R8

DQB_56

T8

DQB_57

R7

DQB_58

T7

DQB_59

V7

DQB_60

W7

DQB_61

W8

DQB_62

W9

DQB_63

B3

MVREFD_1

C3

MVREFS_1

AA3

DRAM_RST

AA5

TEST_MCLK

AA2

TEST_YCLK

AA7

MEMTEST

3

MEMORY INTERFACE B

MAB_0 MAB_1 MAB_2 MAB_3 MAB_4 MAB_5 MAB_6 MAB_7 MAB_8

MAB_9 MAB_10 MAB_11 MAB_12 MAB_13 MAB_14 MAB_15

DQMBb_0 DQMBb_1 DQMBb_2 DQMBb_3 DQMBb_4 DQMBb_5 DQMBb_6 DQMBb_7

QSB_0 QSB_1 QSB_2 QSB_3 QSB_4 QSB_5 QSB_6 QSB_7

QSB_0B QSB_1B QSB_2B QSB_3B QSB_4B QSB_5B QSB_6B QSB_7B

write strobe read strobe

ODTB

ODTB1

CLKB0

CLKB0b

CKEB0 RASB0b CASB0b

WEB0b

CSB0b_0 CSB0b_1

CLKB1

CLKB1b

CKEB1 RASB1b CASB1b

WEB1b

CSB1b_0 CSB1b_1

G4 E6 E4 H4 J5 G5 F4 H6 G3 G2 D4 F2 F5 D5 H2 H3

B8 D9 G9 K7 M5 V2 W4 T9

B9 D10 H10 K6 N4 U2 U4 V8

B10 E10 G10 J7 M4 U3 V4 V9

D6 J4

B4 B5

C2 E2 D3 B2 D2

E3

N2 P3

L3 J2 L2 M2 K2

K3

2

MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11

DQMB#0 DQMB#1 DQMB#2 DQMB#3 DQMB#4 DQMB#5 DQMB#6 DQMB#7

RDQSB0 RDQSB1 RDQSB2 RDQSB3 RDQSB4 RDQSB5 RDQSB6 RDQSB7

WDQSB0 WDQSB1 WDQSB2 WDQSB3 WDQSB4 WDQSB5 WDQSB6 WDQSB7

ODTB0 ODTB1

CLKB0 CLKB0#

CKEB0 RASB0# CASB0# WEB0# CSB0_0#

CSB0_1#

CLKB1 CLKB1#

CKEB1 RASB1# CASB1# WEB1# CSB1_0#

CSB1_1#

2

1

Ch-B FOR M52P,M54P,M26X PIN H2 IS MAB12 (BA0) PIN H3 IS MAB13 (BA1) PIN D5 IS MAB15 (BA2) PIN F5 IS MAB14 FOR M56P PIN H2 IS MA14 (BA0) PIN H3 IS MA15 (BA1) PIN D5 IS MA13 (BA2) PIN F5 IS MAB12

MAB12_14 54,55

TP8 TPAD28TP8 TPAD28

1

B_BA0 54,55 B_BA1 54,55

RASB0#54 RASB1#54,55

CASB0#54 CASB1#54,55

WEB0#54 WEB1#54,55

CSB0_0#54 CSB1_0#54,55

CKEB054 CKEB154,55

For GDDR2

ODTB0 54 ODTB1 54,55

TP81 TPAD28TP81 TPAD28

1

TP4 TPAD28TP4 TPAD28

1

Title

Size Document Number Rev

Date: Sheet

ATI M5X-P MEM 3/4

A3

CLKB054 CLKB0#54

CLKB155 CLKB1#55

RDQSB[7..0]54,55 DQMB#[7..0]54,55 MDB[63..0]54,55 MAB[11..0]54,55 WDQSB[7..0]54,55

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

1

51 58Thursday, October 13, 2005

RASB0# RASB1#

CASB0# CASB1#

WEB0# WEB1#

CSB0_0# CSB1_0#

CKEB0 CKEB1

CLKB0 CLKB0#

CLKB1 CLKB1#

RDQSB[7..0] DQMB#[7..0] MDB[63..0] MAB[11..0] WDQSB[7..0]

of

SA

5

U54F

AH27

PCIE_VSS_1

AC23

PCIE_VSS_2

AL27

PCIE_VSS_3

R23

PCIE_VSS_4

P25

PCIE_VSS_5

R25

PCIE_VSS_6

T26

PCIE_VSS_7

U26

PCIE_VSS_8

W26

PCIE_VSS_9

D D

C C

B B

A A

AB26 AC26 AD25 AE26

AD26 AG25 AH26 AC28

AH29

AC29 AB27

AK29

AA29 AB29 AD29 AE29

AG29 AK26

AK30 AG26

AC30

AA31 AD31

AK32

AK31 AA23 AG31

AB23

AC24 AH24

AA25 AA26 AE27

AD10

AG11 AG16

AF26

AF28

AJ26 AJ32

AF29 AJ29

AF30

AJ28 AJ30

AF14

Y26

Y28 U28 P28

V29

W27

V26

P26 P29 R29 T29 U29

W29

Y29

N30 R31

V31 P30

U30

Y30

N24 P24

R24 T24 U24 V24

W24

Y24

V25 R26 T27

W23

B1 H1

P1 U1

Y1 AD7 AE8

AL1

A2 AM2

E8

H5

K10

M8

T10 E12

AC9 AD8

C5

F10

M6

P6 AA4

V3

R3

C6

C9

F6

H7

L1

J3 L6

J6

PCIE_VSS_10 PCIE_VSS_11 PCIE_VSS_12 PCIE_VSS_13 PCIE_VSS_14 PCIE_VSS_15 PCIE_VSS_16 PCIE_VSS_17 PCIE_VSS_18 PCIE_VSS_19 PCIE_VSS_20 PCIE_VSS_21 PCIE_VSS_22 PCIE_VSS_23 PCIE_VSS_24 PCIE_VSS_25 PCIE_VSS_26 PCIE_VSS_27 PCIE_VSS_28 PCIE_VSS_29 PCIE_VSS_30 PCIE_VSS_31 PCIE_VSS_32 PCIE_VSS_33 PCIE_VSS_34 PCIE_VSS_35 PCIE_VSS_36 PCIE_VSS_37 PCIE_VSS_38 PCIE_VSS_39 PCIE_VSS_40 PCIE_VSS_41 PCIE_VSS_42 PCIE_VSS_43 PCIE_VSS_44 PCIE_VSS_45 PCIE_VSS_46 PCIE_VSS_47 PCIE_VSS_48 PCIE_VSS_49 PCIE_VSS_50 PCIE_VSS_51 PCIE_VSS_52 PCIE_VSS_53 PCIE_VSS_54 PCIE_VSS_55 PCIE_VSS_56 PCIE_VSS_57 PCIE_VSS_58 PCIE_VSS_59 PCIE_VSS_60 PCIE_VSS_61 PCIE_VSS_62 PCIE_VSS_63 PCIE_VSS_64 PCIE_VSS_65 PCIE_VSS_66 PCIE_VSS_67 PCIE_VSS_68 PCIE_VSS_69 PCIE_VSS_70 PCIE_VSS_71 PCIE_VSS_72 PCIE_VSS_73 PCIE_VSS_74 PCIE_VSS_75 PCIE_VSS_76 PCIE_VSS_77 PCIE_VSS_78 PCIE_VSS_79 PCIE_VSS_80 PCIE_VSS_81 PCIE_VSS_82

PCIE_PVSS VSS_1

VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37

Part 6 of 7

PCI-Express GND

CORE GND

5

VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98

VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158

VSS_159

AD16 AA6 P7 P5 M3 M9 L7 M7 AD17 AH11 A8 U7 C10 E9 F3 J9 N7 N3 Y5 AM13 AC10 Y6 U6 E5 AL13 A11 U8 U9 U10 R6 AD6 V6 AD14 AD13 D11 J12 K12 A13 F13 E13 F15 K16 J21 H16 T15 V17 C15 C4 U14 P15 A16 E16 G13 G16 P17 R16 R14 W16 C18 F16 W18 U18 AE16 AE17 A19 H32 F19 G19 N8 Y7 T19 V19 G21 C21 F21 AE14 AK16 U5 F22 F18 K30 C24 F24 M24 A25 D30 E25 G25 G20 G22 F27 E28 H21 C27 E32 H28 J30 K17 K27 M32 A22 C20 E19 H20 J24 M28 J28 J16 F30 L29 A31 B32 E30 AE15 AG23 AD9 AF16 AH10 AJ10 AD15 AH16

K23

4

1D8V_S0

12

C729

SC1U6D3V2KX-GP

12

C116

C709

C135

SCD01U25V2KX-3GP

12

C739

C77

VGA_VDDR3

R424

1 2

0R3J-3-GP

R76

1 2

0R3J-3-GP

VDDR4 AND VDDR5 IN M26X CAN BE 1.8V OR 3.3V DEPENDING ON M26X DVOMODE OR M52P,M54P,M56P REGISTER CONFIGURATION

1D8V_S0

DY

R453

R453 0R3J-3-GP

0R3J-3-GP Q22

Q22

SI2301BDS-T1-GP

D

1

G

R461

1 2

0R2J-GP

1 2

0R2J-GP

4

SCD01U25V2KX-3GP

12

C140

SC1U6D3V2KX-GP

SC1U6D3V2ZY-GP

1 2

0R3J-3-GP

1 2

0R3J-3-GP

12

SD

G

PWROK#

Q23

Q23 2N7002PT-U

2N7002PT-U

2 3

S

R456

DY

C76

SC1U6D3V2KX-GP

12

C92

12

C85

R454

R422

R448

R448 100KR2J-1-GP

100KR2J-1-GP

1 2

NB_PWRGD 13,39

VCORE_EN 39,41

12

C109

C105

SC1U6D3V2KX-GP

12

C163

SCD01U25V2KX-3GP

12

SCD01U25V2KX-3GP

12

C139

12

C693

SC1U6D3V2KX-GP

VGA_VDDRH0

VGA_VDDRH1

3D3V_S0

U54E

C1

VDDR1_1

SCD01U25V2KX-3GP

AB10

AC19 AD18 AC20 AD19 AD20

AM5 AK5 AE2

AE3 AE4 AE5

R96

1 2

0R2J-GP

0R2J-GP R95

R95

1 2

0R2J-GP

2D5V_S0

12

C113

SC1U6D3V2ZY-GP

J1

VDDR1_2

M1

VDDR1_3

R1

VDDR1_4

V1

VDDR1_5

AA1

VDDR1_6

A3

VDDR1_7

P9

VDDR1_8

J10

VDDR1_9

N9

VDDR1_10

P10

VDDR1_11

A9

VDDR1_12

Y10

VDDR1_13

P8

VDDR1_14

R9

VDDR1_15

Y9

VDDR1_16

J11

VDDR1_17

A21

VDDR1_18

M10

VDDR1_20

N10

VDDR1_21

Y8

VDDR1_22

J18

VDDR1_23

J19

VDDR1_24

K21

VDDR1_25

A12

VDDR1_26

H13

VDDR1_27

A15

VDDR1_28

J20

VDDR1_29

J13

VDDR1_30

K11

VDDR1_31

K19

VDDR1_32

A18

VDDR1_33

L23

VDDR1_34

K20

VDDR1_35

K24

VDDR1_36

L24

VDDR1_37

H19

VDDR1_38

A24

VDDR1_39

K13

VDDR1_40

J32

VDDR1_41

A30

VDDR1_42

C32

VDDR1_43

F32

VDDR1_45

L32

VDDR1_46

AB9

VDDR3_1 VDDR3_2

AA9

VDDR3_3 VDDR3_4 VDDR3_5 VDDR3_6 VDDR3_7 VDDR3_8

AJ5

VDDR4_1 VDDR4_2

AL5

VDDR4_3 VDDR4_4

VDDR5_1 VDDR5_2 VDDR5_3 VDDR5_4

A27

VDDRH0

F1

VDDRH1

A28

VSSRH0

E1

VSSRH1

VGA_BBN

VGA_BBP

12

C78

SC10U10V5KX-2GP

12

C112

C117

SCD01U25V2KX-3GP

TC21

TC21 ST100U6D3VDM-5

ST100U6D3VDM-5

C106

SCD1U10V2KX-LGP

12

SC1U6D3V2KX-GP

VGA_VDDR5

12

C91

12

C723

SC1U6D3V2KX-GP

12

C689

SC1U6D3V2KX-GP

M56P

VGA_CORE_S0

M56P

BACK BIASING APPLIES TO M56P ONLY IF BACK BIAS NOT USED ON M56,CONNECT BBN PINS TO VSS AND BBP PINS TO VDDC BBN,BBP PINS ARE NO CONNECT FOR M26X,M54P,M52P

3

C108

SCD1U10V2KX-LGP

12

3

PART 5 OF 7

Memory I/O

P

P O

O W

W E

E R

R

I/0

Memory

I/O

Clock

Memory

I/O

Clock

U54G

Forward

Compatibility

Y23

BBN_4

K15

BBN_3

R10

BBN_2

AC17

BBN_1

AC14

BBP_4

M23

BBP_3

V10

BBP_2

K18

BBP_1

L10

VDD25_4 VDD25_5 VDD25_6

This channel is used as the transmitting channel in single channel LVDS mode.

K22

AA10

C146

SCD1U10V2KX-LGP

CONNECT THESE VDD25 PINS TO 2.5V FOR M52P,M54P,M56P THESE VDD25 PINS ARE NO CONNECT FOR M26X

PCIE_PVDD_12_1 PCIE_PVDD_12_2 PCIE_PVDD_12_3 PCIE_PVDD_12_4

PCIE_VDDR_12_10 PCIE_VDDR_12_11 PCIE_VDDR_12_12 PCIE_VDDR_12_13 PCIE_VDDR_12_14

PCIE_VDDR_12_1 PCIE_VDDR_12_2 PCIE_VDDR_12_3 PCIE_VDDR_12_4 PCIE_VDDR_12_5 PCIE_VDDR_12_6 PCIE_VDDR_12_7 PCIE_VDDR_12_8

PCI-Express

PCIE_VDDR_12_9

VDDC_10 VDDC_11 VDDC_12 VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22 VDDC_23

VDD25_1 VDD25_2 VDD25_3

VDDCI_1 VDDCI_2 VDDCI_3 VDDCI_4 VDDCI_5 VDDCI_6 VDDCI_7

LPVDD/VDDL0

LVDDR/VDDL0_1 LVDDR/VDDL0_2 LVDDR/VDDL0_3

LVDDR/VDDL1_1 LVDDR/VDDL1_2 LVDDR/VDDL1_3 LVDDR/VDDL2_1 LVDDR/VDDL2_2 LVDDR/VDDL2_3

LVDS PLL, I/O I/O Internal Core

PART 7 OF 7

Control and External SSC

Only used in dual-channel LVDS mode.

LVDS channel

VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8 VDDC_9

VDDPLL

VARY_BL

DIGON

GENERICD

TXCLK_UP

TXCLK_UN TXOUT_U3P TXOUT_U3N TXOUT_U2P TXOUT_U2N TXOUT_U1P TXOUT_U1N TXOUT_U0P TXOUT_U0N

TXOUT_L0N

TXOUT_L0P

TXOUT_L1N

TXOUT_L1P

TXOUT_L2N

TXOUT_L2P

TXOUT_L3N

TXOUT_L3P

TXCLK_LN

TXCLK_LP

V23 N23 P23 U23

N29 N28 N27 N26 N25

AL31 AM31 AM30 AL32 AL30 AM28 AL29 AM29 AM27

AC11 AC12 P14 U15 W14 W15 R17 R15 V15 V16 T16 U16 T17 U17 V14 R18 T18 V18 P18 P19 R19 W19 AD11

AC13 AC16 AC18

AC15 W10

T14 W17 P16 T23 K14 U19

AE19 AF20

AE20 AF19

AC21 AC22 AD22 AE21 AD21 AE22

AD12 AE11 AD23

AJ21 AK21 AH21 AG21 AG20 AH20 AK20 AJ20 AG18 AH18

AK19 AL19 AL20 AM20 AL21 AM21 AK18 AJ18 AL18 AM18

2

VGA_PCIE_PVDD12

VGA_PCIE_VDDR12_1

VGA_PCIE_VDDR12_2

C732

C111

12

VGA_VDD25

VGA_VDDPLL

VGA_VDDCI

SCD1U10V2KX-LGP

12

C110

VGA_LPVDDVGA_VDDR4

VGA_LVDDRL0

12

C134

VGA_LVDDRL1

SC1U6D3V2ZY-GP

12

C174

SC1U6D3V2ZY-GP

2

C147

12

C150

C150 SC1KP16V2KX-GP

SC1KP16V2KX-GP

C167

12

SC1KP16V2KX-GP

12

C731

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP C152

C152

SCD1U10V2KX-LGP

12

C136

C122

SCD1U10V2KX-LGP

12

SC1U6D3V2ZY-GP

12

C712

SCD1U10V2KX-LGP

12

C131

C132

SCD1U10V2KX-LGP

12

C141

SCD1U10V2KX-LGP

12

C153

SCD1U10V2KX-LGP

12

BL_ON 13,34

12

R81

R81 10KR2J-2-GP

10KR2J-2-GP

C147

12

SCD1U10V2KX-LGP

12

C176

C138

12

C130

12

SCD1U10V2KX-LGP

1 2

0R5J-5-GP

1 2

0R5J-5-GP

SC4D7U6D3V3KX-GP

12

C162

12

C175

C164

SC1U6D3V2KX-GP

SC4D7U6D3V3KX-GP

12

C730

SC4D7U6D3V3KX-GP

SC1U6D3V2KX-GP

C115

12

C137

SCD1U10V2KX-LGP

12

SC4D7U6D3V3KX-GP

SCD1U10V2KX-LGP

12

C119

C133

12

SCD1U10V2KX-LGP

BLON CAN ALSO BE A PWM OUTPUT FOR BRIGHTNESS CONTROL

ATI_TXBCLK+ 57 ATI_TXBCLK- 57

ATI_TXBOUT2+ 57 ATI_TXBOUT2- 57 ATI_TXBOUT1+ 57 ATI_TXBOUT1- 57 ATI_TXBOUT0+ 57 ATI_TXBOUT0- 57

ATI_TXAOUT0- 57 ATI_TXAOUT0+ 57 ATI_TXAOUT1- 57 ATI_TXAOUT1+ 57 ATI_TXAOUT2- 57 ATI_TXAOUT2+ 57

ATI_TXACLK- 57 ATI_TXACLK+ 57

1

R106 0R5J-5-GPR106 0R5J-5-GP

1 2

R112

C166

0R5J-5-GP

R460

1 2

SC1U6D3V2KX-GP

0R5J-5-GP

12

C168

SC1U6D3V2KX-GP

C120

C148

SCD1U10V2KX-LGP

12

C121

SCD1U10V2KX-LGP

C149

1 2

0R3J-3-GP

R98

R109

C151

C114

SCD1U10V2KX-LGP

12

C93

SCD1U10V2KX-LGP

12

C124

12

SCD1U10V2KX-LGP

R101

2D5V_S0

ATI_LCDVDD_ON 57

FOR M26X GENERICD NO CONNECT OR EXT SPREAD SPECTRUM OUTPUT FOR M52P,M54P IT IS A GPIO FOR M56P IT IS A BACK BIAS REGULATOR CONTROL

Title

Size Document Number Rev

C

Date: Sheet of

1D2V_S0

FOR M26X PCIE_VDDR12 CONNECT TO +1.8V FOR M52P,M54P,M56P CONNECT TO +1.2V

VGA_CORE_S0

C118

SCD1U10V2KX-LGP

12

SCD1U10V2KX-LGP

12

R75

C123

1 2

SCD1U10V2KX-LGP

12

0R3J-3-GP

R442

1 2

0R3J-3-GP

R97

1 2

0R5J-5-GP

FOR M26X LPVDD CONNECT TO +1.8V FOR M52P,M54P,M56P CONNECT TO +2.5V

FOR M26X LVDDR PINS AE20,AF20,AF19 CONNECT TO +1.8V FOR M52P,M54P,M56P CONNECT TO +2.5V

FOR M26X LVDDR PINS AC21,AC22,AD21,AD22,AE21,AE22 CONNECT TO +2.8V FOR M52P,M54P,M56P CONNECT TO +2.5V

ATI M5X-P Power 4/4

Bolsena-E

FOR M26X VDD25 CONNECT TO +1.5V FOR M52P,M54P,M56P CONNECT TO +2.5V

2D5V_S0

FOR M26X VDDPLL CONNECT TO VDDC FOR M52P,M54P,M56P CONNECT TO +1.2V

1D2V_S0

VGA_CORE_S0

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

SA

52 58Thursday, October 13, 2005

SA

5

A

4

3

2

1

Ideal Power Up Sequence

Real Power Up Sequence

D D

VBBN

VBBP

VDDC

MVDDC

PCIE_VDDR_12

PCIE_PVDD_12

1mS

VBBN

VBBP

VDDC

MVDDC

PCIE_VDDR_12

PCIE_PVDD_12

C C

VDD25

VDDR1

VDD25

VDDR1

<5mS

VDDR3

RESISTOR

Symbol name

B B

10KR3

33D3R5

1KR3F

The naming rule is value + R + size + tolerance For the value, it can be read by the number before R. (R means resistor) For the tolerance, it can be read from the last letter. For the rating, we don't show on the symbol name.

For the size, R2=>0402, R3=>0603, R5=>0805,....

Value

10K Ohm

33.3 Ohm

1K Ohm

Tolerance

(J: 5%, F: 1%, D: 0.5%, B: 0.1 %)

If no letter, it means J: 5%

If no letter, it means J: 5% 0805

F: 1%

Rating

0402=> 1/16W, 25V 0603 => 1/16W, 75V 0805 => 1/10W, 100V

1/16W, 75V

1/10W, 100V

1/16W, 75V

Size

2=>0402, 3=>0603, 5=>0805, 6=>1206, 0=>1210

0603

General Guidelines:

‧

BBN and BBP must ramp up before or at the same time as VDDC but not after. VDDC and MVDDC must be ramped up first, followed by PCIE_VDDR_12, PCIE_PVDD12, VDD25, VDDR1 and

‧

VDDR3 (and other I/O powers).

‧

All powers must be ramped up within 5ms of each other (from the ramp of VDDC to 90% of VDDR3). VDD25 can be ramped with VDDC or VDDR1 but it cannot be ramped later than VDDR1.

‧

The power down is the opposite of the power on sequence: VDDR3/VDDR1 -> VDD25

‧

->VDDC/MVDDC/BBN/BBP. Due to the level shifter design in the memory I/Os, in order to avoid over-stressing the thin oxide transistors when VDDR1 is powered on but VDDC is not, VDDC must ramp up before VDDR1. Similarly, VDDC must ramp up before VDDR3. The level shifter design is a function of the transistor types used in 90nm technology and of the voltage level support. The drawback of ramping up VDDC before the I/O voltages (such as VDDR1 and VDDR3) is that parasitic P/N junctions are forward biased, thus creating a conduction path. These conduction paths will pump up VDDR1 (from the memory IOs) and VDDR3 (from the GPIOs). The real power up sequence will appear as follows: Figure 2-2. Real Power Up Sequence As long as MVDDC ramps up with VDDC, the pump voltage on VDDR1 should be all right since the DRAM spec will not be violated.

CAPACITOR

Symbol name

SCD1U10V2MX-1

SC10U6D3V5MX

SC2D2U16V5ZY

Value

0.1uF

10uF

2.2uF

Tolerance

(J: +/-5, K: +/-10, M: +/-20, Z: +80/-20)

M/X5R

Z/Y5V

Rating

( X5R / X7R < 80%, Y5V/Y5U/Z5U < 1/3 )

10V

6.3V

16V

Size

2=>0402, 3=>0603, 5=>0805, 6=>1206, 0=>1210

0402

0805

The naming rule is Capacitor type + value + rating + size + tolerance + material SCD1U10V2MX-1 SC=> SMT Ceremic, TC=> POS cap or SP cap D1U => 0.1uF 10V => the voltage rating is 10V 2=> 0402, 3=>0603, 5=>0805 M=>tolerance J, K, M, Z X=> X7R/X5R, Y=> Y5V

-1 => symbol version, nonsense to EE characteristic

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

ATI M5X-P POWER SEQUENCE

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E SA

53 58Thursday, October 13, 2005

of

A

5

4

3

2

1

CHAN B DDR2 84BGA 32MX16 MEMORY

D D

U53

C C

B B

A A

1D8V_S0

12

R435

R435 1KR2F-3-GP

1KR2F-3-GP

B_BA051,55 B_BA151,55

MAB12_1451,55

12

R434

R434 1KR2F-3-GP

1KR2F-3-GP

(SSTL-1.8) VREF = .5*VDDQ (SSTL-1.8) VREF = .5*VDDQ

12

C706

SCD1U10V2KX-LGP

5

MAB11 MAB10 MAB9 MAB8 MAB7 MAB6 MAB5 MAB4 MAB3 MAB2 MAB1 MAB0

CLKB0# CLKB0

CKEB0

CSB0_0# WEB0# RASB0# CASB0# DQMB#2

DQMB#0

ODTB0

RDQSB2 WDQSB2

RDQSB0 WDQSB0

U53

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

K3

WE

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

NC#L1

R3

NC#R3

R7

NC#R7

R8

NC#R8

HY5PS561621A-25GP

72.55616.C0U

DQ15 DQ14 DQ13 DQ12 DQ11 DQ10

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9

VDDQ10

VDD1 VDD2 VDD3 VDD4 VDD5

VDDL

VSSDL

VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9

VSSQ10

VSS1 VSS2 VSS3 VSS4 VSS5

1D8V_S0

B9 B1 D9 D1 D3 D7 C2

DQ9

C8

DQ8

F9

DQ7

F1

DQ6

H9

DQ5

H1

DQ4

H3

DQ3

H7

DQ2

G2

DQ1

G8

DQ0

A9 C1 C3 C7 C9 E9 G1 G3 G7 G9

A1 E1 J9 M9 R1

J1 J7

A7 B2 B8 D2 D8 E7 F2 F8 H2 H8

A3 E3 J3 N1 P9

72.55616.C0U IC VRAM HY5PS561621AFP-25 FBGA(16M*16, 400Mhz)

72.51216.D0U IC VRAM HY5PS121621BFP-25 FBGA(32M*16, 400Mhz)

12

C100

C84

SCD1U10V2KX-LGP

SC1U6D3V2KX-GP

12

C97

C45

SCD1U10V2KX-LGP

SC1U6D3V2KX-GP

MDB7 MDB0 MDB5 MDB2 MDB3 MDB4 MDB1 MDB6 MDB23 MDB18 MDB20 MDB16 MDB17 MDB21 MDB19 MDB22

CLKB0#51

CLKB051

1D8V_S0 1D8V_S0

1 2

0R2J-GP

12

C707

SCD1U10V2KX-LGP

4

R436

56R2J-4-GP

CLOSE TO MEM !!

1D8V_S0

12

R390

R390 1KR2F-3-GP

1KR2F-3-GP

C83

SCD1U10V2KX-LGP

12

C59

SCD1U10V2KX-LGP

12

R420

BC857_1

12

R389

R389 1KR2F-3-GP

1KR2F-3-GP

12

C680

SCD1U10V2KX-LGP

12

C82

12

R421

R421 56R2J-4-GP

56R2J-4-GP

C688

SC470P50V2KX-3GP

12

C81

SC1U6D3V2KX-GP

12

C47

C58

SCD1U10V2KX-LGP

B_BA0 B_BA1

MAB12_14 MAB11 MAB10 MAB9 MAB8 MAB7 MAB6 MAB5 MAB4 MAB3 MAB2 MAB1 MAB0

CLKB0# CLKB0

CKEB0

CSB0_0# WEB0# RASB0# CASB0# DQMB#1

DQMB#3

ODTB0

RDQSB1 WDQSB1

RDQSB3 WDQSB3

VRAM_VREF2VRAM_VREF1

12

C99

SCD1U10V2KX-LGP

SC1U6D3V2KX-GP

12

C32

SC1U6D3V2KX-GP

12

C98

SCD1U10V2KX-LGP

12

C24

SCD1U10V2KX-LGP

U49

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

K3

WE

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

NC#L1

R3

NC#R3

R7

NC#R7

R8

NC#R8

HY5PS561621A-25GP

72.55616.C0U

3

12

C46

SC1U6D3V2KX-GP

12

C25

SC1U6D3V2KX-GP

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9

VDDQ10

VSSDL

VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9

VSSQ10

DQ15 DQ14 DQ13 DQ12 DQ11 DQ10

DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

VDD1 VDD2 VDD3 VDD4 VDD5

VDDL

VSS1 VSS2 VSS3 VSS4 VSS5

DDR_VREF_S0

M56P

RN88

MAB6 MAB2 MAB1 MAB10

SRN56J-2-GP

MAB8 MAB0 MAB11 MAB5

SRN56J-2-GP

MAB4 MAB3 MAB7 MAB9

SRN56J-2-GP

B_BA0 B_BA1 MAB12_14

ODTB0 ODTB1

RASB0# RASB1#

CASB0# CASB1#

WEB0# WEB1#

CSB0_0# CSB1_0#

CKEB0 CKEB1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

VRAM_VDDLVRAM_VDDL

12

MDB27 MDB28 MDB24 MDB31 MDB30 MDB25 MDB29 MDB26 MDB15 MDB9 MDB12 MDB8 MDB11 MDB13 MDB10 MDB14

R404

1 2

0R2J-GP

C684

SCD1U10V2KX-LGP

ODTB051 ODTB151,55

RASB0#51 RASB1#51,55

CASB0#51 CASB1#51,55

WEB0#51 WEB1#51,55

CSB0_0#51 CSB1_0#51,55

CKEB051 CKEB151,55

FOR M56P AT DDR2 MEMORY SPEEDS ABOVE 350MHZ MEMORY CONTROL SIGNALS WE,CAS,RAS,CS,CKE,ODT AND MEMORY ADDRESS SIGNALS REQUIRE 55 OHM PULLUP TO A VTT RAIL (50% OF VDDQ)

CLKB051 CLKB0#51

RDQSB[7..0]51,55 DQMB#[7..0]51,55 MDB[63..0]51,55 MAB[11..0]51,55 WDQSB[7..0]51,55

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

A3

VRAM 1/2

Bolsena-E

B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8

A9 C1 C3 C7 C9 E9 G1 G3 G7 G9

A1 E1 J9 M9 R1

J1 J7

A7 B2 B8 D2 D8 E7 F2 F8 H2 H8

A3 E3 J3 N1 P9

RN88

1

8

2

7

3

6

4 5

RN89

1

8

2

7

3

6

4 5

RN90

1

8

2

7

3

6

4 5

R388 56R2J-4-GPR388 56R2J-4-GP

1 2

R387 56R2J-4-GPR387 56R2J-4-GP

1 2

R386 56R2J-4-GPR386 56R2J-4-GP

1 2

R418 56R2J-4-GPR418 56R2J-4-GP

1 2

R18 56R2J-4-GPR18 56R2J-4-GP

1 2

R416 56R2J-4-GPR416 56R2J-4-GP

1 2

R14 56R2J-4-GPR14 56R2J-4-GP

1 2

R414 56R2J-4-GPR414 56R2J-4-GP

1 2

R16 56R2J-4-GPR16 56R2J-4-GP

1 2

R419 56R2J-4-GPR419 56R2J-4-GP

1 2

R17 56R2J-4-GPR17 56R2J-4-GP

1 2

R415 56R2J-4-GPR415 56R2J-4-GP

1 2

R15 56R2J-4-GPR15 56R2J-4-GP

1 2

R417 56R2J-4-GPR417 56R2J-4-GP

1 2

R13 56R2J-4-GPR13 56R2J-4-GP

1 2

CLKB0 CLKB0#

RDQSB[7..0] DQMB#[7..0] MDB[63..0] MAB[11..0] WDQSB[7..0]

54 58Thursday, October 13, 2005

of

1

of

SA

5

D D

4

3

1D8V_S0

2

12

C26

SC1KP16V2KX-GP

12

C49

SC1U6D3V2KX-GP

12

C60

SC1U6D3V2KX-GP

12

C15

SCD1U10V2KX-LGP

12

C50

SC1U6D3V2KX-GP

12

C51

SCD1U10V2KX-LGP

1

12

C52

SCD1U10V2KX-LGP

12

C61

SC10U10V5ZY-1GP

1D8V_S0

C C

B_BA051,54 B_BA151,54

MAB12_1451,54

B B

1D8V_S0

12

R400

R400 1KR2F-3-GP

1KR2F-3-GP

12

R405

1KR2F-3-GP

A A

(SSTL-1.8) VREF = .5*VDDQ

12

C685

C685 SCD1U10V2KX-LGP

SCD1U10V2KX-LGP

5

B_BA0 B_BA1

MAB12_14 MAB11 MAB10 MAB9 MAB8 MAB7 MAB6 MAB5 MAB4 MAB3 MAB2 MAB1 MAB0

CLKB1# CLKB1

CKEB1

CSB1_0#

WEB1# RASB1# CASB1#

DQMB#5 DQMB#4

ODTB1

RDQSB5 WDQSB5

RDQSB4 WDQSB4

VRAM_VREF3

U50

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

K3

WE

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

NC#L1

R3

NC#R3

R7

NC#R7

R8

NC#R8

HY5PS561621A-25GP

72.55616.C0U

DQ15 DQ14 DQ13 DQ12 DQ11 DQ10

DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9

VDDQ10

VDD1 VDD2 VDD3 VDD4 VDD5

VDDL

VSSDL

VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9

VSSQ10

VSS1 VSS2 VSS3 VSS4 VSS5

4

MDB39 MDB32 MDB38 MDB34 MDB33 MDB37 MDB35 MDB36 MDB44 MDB43 MDB47 MDB40 MDB41 MDB46 MDB42 MDB45

1D8V_S0

1 2

0R2J-GP

12

C686

SCD1U10V2KX-LGP

R392

1KR2F-3-GP

R410

CLKB1#51 CLKB151

56R2J-4-GP

1D8V_S0

12

R407

R406

R406 56R2J-4-GP

56R2J-4-GP

BC856_1

C687

12

SC470P50V2KX-3GP

CLOSE TO MEM !!

12

R391

R391 1KR2F-3-GP

1KR2F-3-GP

(SSTL-1.8) VREF = .5*VDDQ

12

C681

SCD1U10V2KX-LGP

B_BA0 B_BA1

MAB12_14 MAB11 MAB10 MAB9 MAB8 MAB7 MAB6 MAB5 MAB4 MAB3 MAB2 MAB1 MAB0

CLKB1# CLKB1

CKEB1

CSB1_0#

WEB1# RASB1# CASB1#

DQMB#6 DQMB#7

ODTB1

RDQSB6 WDQSB6

RDQSB7 WDQSB7

VRAM_VREF4

B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8

A9 C1 C3 C7 C9 E9 G1 G3 G7 G9

A1 E1 J9 M9 R1

J1 J7

A7 B2 B8 D2 D8 E7 F2 F8 H2 H8

A3 E3 J3 N1 P9

3

U51

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

K3

WE

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

NC#L1

R3

NC#R3

R7

NC#R7

R8

NC#R8

HY5PS561621A-25GP

72.55616.C0U

DQ15 DQ14 DQ13 DQ12 DQ11 DQ10

DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9

VDDQ10

VDD1 VDD2 VDD3 VDD4 VDD5

VDDL

VSSDL

VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9

VSSQ10

VSS1 VSS2 VSS3 VSS4 VSS5

B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8

A9 C1 C3 C7 C9 E9 G1 G3 G7 G9

A1 E1 J9 M9 R1

J1 J7

A7 B2 B8 D2 D8 E7 F2 F8 H2 H8

A3 E3 J3 N1 P9

MDB59 MDB60 MDB58 MDB62 MDB63 MDB56 MDB61 MDB57 MDB51 MDB53 MDB48 MDB55 MDB52 MDB49 MDB54 MDB50

1D8V_S0

1 2

0R2J-GP

12

C682

SCD1U10V2KX-LGP

R401

12

2

12

C48

C33

SC1KP16V2KX-GP

C34

C34 SC1U10V3KX-3GP

SC1U10V3KX-3GP

12

C62

C27

SC1U6D3V2KX-GP

Title

Size Document Number Rev

A3

Date: Sheet

SCD1U10V2KX-LGP

SC1U6D3V2KX-GP

RDQSB[7..0]51,54 DQMB#[7..0]51,54 MDB[63..0]51,54 MAB[11..0]51,54 WDQSB[7..0]51,54

VRAM 2/2

12

C53

RASB1#51,54

CASB1#51,54

WEB1#51,54

CSB1_0#51,54 CKEB151,54 ODTB151,54

C28

SC1U6D3V2KX-GP

CLKB151 CLKB1#51

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

SCD1U10V2KX-LGP

12

C35

SCD1U10V2KX-LGP

RASB1#

CASB1#

WEB1#

CSB1_0# CKEB1 ODTB1

CLKB1 CLKB1#

RDQSB[7..0] DQMB#[7..0] MDB[63..0] MAB[11..0] WDQSB[7..0]

55 58Thursday, October 13, 2005

1

12

C63

SC10U10V5ZY-1GP

of

SA

A

B

C

D

E

FAN5234 FOR VGA_Core

Dummy when use 'UMA' (whole page)

4 4

5V_S5

12

C67

C67 SC10U10V5KX-2GP

SC10U10V5KX-2GP

3 3

PM_SLP_S3#17,20,34,38,39,45

R36

1 2

10KR2J-2-GP

2 2

5V_S0

12

DCBATOUT_5234

1 2

0R0603-PAD

12

C29

C29 SCD22U16V3ZY-GP

SCD22U16V3ZY-GP

R32

R32 DUMMY-R2

DUMMY-R2

R33

5234_VIN

12

C65

SC2200P50V2KX-2GP

5234_SS

5234_ILIM

5234_EN

R35

R35 44K2R3F-2-GP

44K2R3F-2-GP

D10

SSM5818SLPT-GP

U6

16

FPWM

15

BOOT

7

SS

4

ILIM

3

EN

6

VSEN

5

VOUT

1

VIN

11

VCC

FAN5234MTCX-1GP 74.05234.A7G

12

C30

C30 SCD1U25V3KX-GP

SCD1U25V3KX-GP

5234_VSEN

Rilim=(11.2/Iilim)*((100+Rsense)/Rdson)

12

21

PGND AGND

ISNS

SW

HDRV LDRV

PGOOD

PWM Mode: FPWM (High)=>Fixed PWM Mode. FPWM (Low)=>Hysteretic Mode.

DCBATOUT DCBATOUT_5234

C66

C66 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C37

5234_ISEN 5234_SW

5234_HDRV 5234_LDRV

TP3

TP3 TPAD30

TPAD30

C37

1 2

SCD1U25V3KX-GP

5234_BOOT

9 8

12 13

14 10

2

G2

1 2

G3

1 2

G1

1 2

G4

1 2

G6

1 2

G5

1 2

R42

1K2R3F-GP

1 2

GAP-CLOSE-PWR

AO4422-1-GP

AO4430-1-GP

DCBATOUT_5234

SC10U25V6KX-1GP

12

C95

678

DDD

U8

SSS

GD

SSS

GD

123

4 5

L22

1 2

IND-1UH-42-GP

678

DDD

U9

SSS

GD

SSS

GD

123

4 5

POWERPLAY: high (3.3V) = set lower core voltage (e.g. VDDC = 1.0V) low (0V) = set higher core voltage (e.g. VDDC = 1.08V)

High :R800 + R59 set Vout to 1V. Low : R800 set Vout to 1.08V.

5V_S0

300KHz

12

R37

R37 10KR2J-2-GP

10KR2J-2-GP

12

R34

R34 DUMMY-R3

DUMMY-R3

C94

12

SCD1U25V3ZY-1GP

12

C54

2KR2F-3-GP

SC10U25V6KX-1GP

12

C79

12

R41

R41 442R2F-GP

442R2F-GP

M54P

SCD01U16V2KX-3GP

2KR2F-3-GP

12

R45

M54P

R46

1K62R2F-GP

Vout Setting:

0.9V/Rlow=(Vout-0.9V)/Rhigh

12

R40

R40 402R3F-GP

402R3F-GP

M56P

12

R54

M56P

SC4D7U10V5ZY-3GP

C692

SCD1U25V3ZY-1GP

Q4

2N7002PT-U

D

1

G

C72

S

2 3

DY

12

VGA_CORE_PWR VGA_CORE_S0

1 2

GAP-CLOSE-PWR

1 2

Vosetting=1.0809V

12

TC19

SE330U2VDM-L-GP

DY

Panasonic V Size 330uF 2V ESR=9mohm, Iripple=3.0A USD:0.250 (Q3/05)

3D3V_S0

12

R52

10KR2J-2-GP

R53

1 2

20KR2J-L2-GP

CHT2222APT-GP

Q6

C

B

E 12

R74

R74 1KR2J-1-GP

1KR2J-1-GP

GAP-CLOSE-PWR

G60

GAP-CLOSE-PWR

G67

GAP-CLOSE-PWR

G64

GAP-CLOSE-PWR

G63

GAP-CLOSE-PWR

G69

GAP-CLOSE-PWR

G66

GAP-CLOSE-PWR

G65

GAP-CLOSE-PWR

G61

G68

GAP-CLOSE-PWR

G62

12

GPIO_PWRCNTL 50

12

R73

R73 100KR2J-1-GP

100KR2J-1-GP

M52/M54:1.1V M56: 1.08V Iomax=17A OCP>28A

TC20

SE330U2VDM-L-GP

VGA_CORE_PWR

1 1

A

B

C

(Power Team)

D

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

VGA CORE 1D1V

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Bolsena-E

56 58Thursday, October 13, 2005

of

E

of

SA

5

4

3

2

1

6 7 8

0R2J-GP

S L H

LCD_TXBCLK+ 13,16 LCD_TXBCLK- 13,16 LCD_TXBOUT2+ 13,16 LCD_TXBOUT2- 13,16

LCD_TXBOUT1+ 13,16 LCD_TXBOUT1- 13,16 LCD_TXBOUT0+ 13,16 LCD_TXBOUT0- 13,16

LCD_TXACLK+ 13,16 LCD_TXACLK- 13,16 LCD_TXAOUT2+ 13,16 LCD_TXAOUT2- 13,16

LCD_TXAOUT1+ 13,16 LCD_TXAOUT1- 13,16 LCD_TXAOUT0+ 13,16 LCD_TXAOUT0- 13,16

LCD_VDD_ON 13,16

TV SWITCH

Function A to B0 A to B1

RN96

D D

DIS_COMP50 DIS_LUMA50 DIS_CRMA50

UMA_CRMA13 UMA_LUMA13 UMA_COMP13

1 2 3 4 5

SRN0J-4-GP

Dummy when use UMA

RN99

1 2 3 4 5

SRN0J-4-GP

Dummy when use Discrete

C C

1

DIS_B50 DIS_G50 DIS_R50

2 3 4 5

Dummy when use UMA

B B

UMA_R13 UMA_G13 UMA_B13

Dummy when use Discrete

8 7 6

8

TV_CRMA

7

TV_LUMA

6

TV_COMP

-1 0308

RN83

SRN0J-4-GP

RN82

1 2 3 4 5

SRN0J-4-GP

TV_COMP

TV_LUMA

TV_CRMA

8 7 6

CRT_B_1 CRT_G_1 CRT_R_1

CRT_R_1 CRT_G_1 CRT_B_1

TV_COMP 15 TV_LUMA 15 TV_CRMA 15

CRT_B_1 15 CRT_G_1 15 CRT_R_1 15

SRN0J-4-GP

ATI_TXBCLK+52 ATI_TXBCLK-52 ATI_TXBOUT2+52 ATI_TXBOUT2-52

ATI_TXBOUT1+52 ATI_TXBOUT1-52 ATI_TXBOUT0+52 ATI_TXBOUT0-52

ATI_TXACLK+52 ATI_TXACLK-52 ATI_TXAOUT2+52 ATI_TXAOUT2-52

ATI_TXAOUT1+52 ATI_TXAOUT1-52 ATI_TXAOUT0+52 ATI_TXAOUT0-52

ATI_LCDVDD_ON52

4 5 3 2 1

RN87

RN87 SRN0J-4-GP

SRN0J-4-GP

4 5 3 2 1

RN85

RN85 SRN0J-4-GP

SRN0J-4-GP

4 5 3 2 1

RN81

RN81 SRN0J-4-GP

SRN0J-4-GP

4 5 3 2 1

RN79

R135

1 2

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

VGA SELECTOR

Size Document Number Rev

A3

Bolsena-E

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

57 58Thursday, October 13, 2005

of

1

of

SA

5

A

4

HOLE2

HOLE2 HOLE

HOLE

HOLE25

HOLE25 HOLE

HOLE

HOLE4

HOLE4 HOLE

HOLE

3

HOLE7

HOLE7 HOLE

HOLE

HOLE12

HOLE12 HOLE

HOLE

HOLE8

HOLE8 HOLE

HOLE

HOLE10

HOLE10 HOLE

HOLE

HOLE11

HOLE11 HOLE

HOLE

2

HOLE6

HOLE6 HOLE

HOLE

HOLE9

HOLE9 HOLE

HOLE

HOLE1

HOLE1 HOLE

HOLE

HOLE13

HOLE13 HOLE

HOLE

HOLE3

HOLE3 HOLE

HOLE

HOLE22

HOLE22 HOLE

HOLE

1

HOLE20

HOLE20 HOLE

HOLE

HOLE5

HOLE5 HOLE

HOLE

HOLE24

HOLE24 HOLE

HOLE

VGA_CORE_PWR 1D8V_S0 1D2V_S0

12

DY

EC11

D D

SCD1U16V2ZY-2GP

C C

2D5V_S3 2D5V_S0

12

EC72

12

EC21

SCD1U16V2ZY-2GP

12

EC74

SCD1U16V2ZY-2GP

FAN1_VCC

12

EC14

SCD1U16V2ZY-2GP

12

SCD1U16V2ZY-2GP

12

EC27

SCD1U16V2ZY-2GP

12

EC33

12

DY

EC51

SCD1U16V2ZY-2GP

12

DY

EC9

EC20

SCD1U16V2ZY-2GP

12

DY

EC39

SCD1U16V2ZY-2GP

1D2V_PWR2D5V_PWR1D8V_PWR

12

EC28

SCD1U16V2ZY-2GP

3D3V_LAN_S53D3V_BT_S02D5V_S0 DCBATOUTDCBATOUT

12

DY

EC52

SCD1U16V2ZY-2GP

IMPORTANT:

12

SCD1U => VOLTAGE 25V SCD1U16V => VOLTAGE 16V

B B

DY

GND15

SPRING-23-GP

1

34.39S07.001

GND7

SPRING-24-GP

1

34.45T31.001

GND2

SPRING-1-GP

1

GND21

SPRING-23-GP

DY

34.40V16.001

1

34.39S07.001

DY

GND20

SPRING-1-GP

1

34.40V16.001

GND1

SPRING-24-GP

1

34.45T31.001

GND22

SPRING-23-GP

1

GND18

1

GND5

SPRING-24-GP

1

GREEN COLOR FOR INSTALL

GND17

SPRING-1-GP

1

34.39S07.001

34.49U24.001

34.45T31.001

GND19

1

34.49U24.001

GND3

SPRING-1-GP

1

34.40V16.001

DY

34.40V16.001

DY

GND9

SPRING-23-GP

1

34.39S07.001

DY

GND8

SPRING-1-GP

1

34.40V16.001

GND4

SPRING-1-GP

DY

1

34.40V16.001

GND10

SPRING-1-GP

DY

1

3D3V_S5

12

SCD1U16V2ZY-2GP

EC75

EC25

ZZ.NDPAD.XXX

34.40V16.001

SCD1U16V2ZY-2GP

SCD1U25V3ZY-3GP

GND13

1

GNDPAD

GND12

SPRING-1-GP

DY

1

34.40V16.001

ZZ.NDPAD.XXX

EC49

12

EC41

SCD1U25V3ZY-3GP

GND14

1

GNDPAD

GND11

SPRING-1-GP

1

34.40V16.001

GND16

SPRING-29-GP

1

DY

DCBATOUT

12

EC69

EC69 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

34.42T14.001

DY

GND6

SPRING-1-GP

1

34.40V16.001

1

12

EC32

SCD1U16V2ZY-2GP

12

EC6

12

SCD1U16V2ZY-2GP

EC16

SCD1U16V2ZY-2GP

12

EC13

EC4

12

EC53

12

SCD1U16V2ZY-2GP

EC15

SCD1U16V2ZY-2GP

12

EC10

1

12

EC12

SCD1U16V2ZY-2GP

12

EC65

12

EC55

12

SCD1U16V2ZY-2GP

EC23

12

EC57

1

12

SCD1U16V2ZY-2GP

1

5V_AUX_S5 AD+3D3V_LAN_S5

12

SCD1U16V2ZY-2GP

3D3V_S0

12

EC44

2D5V_S0 3D3V_S5 5VA_OP_S0

12

SCD1U16V2ZY-2GP

EC70

DCBATOUT

SCD1U16V2ZY-2GP

12

EC73

1

12

EC17

SCD1U25V3ZY-3GP

12

EC7

12

SCD1U16V2ZY-2GP

EC40

SCD1U16V2ZY-2GP

EC48

SCD1U16V2ZY-2GP

12

EC42

EC34

12

1

12

EC35

SCD1U25V3ZY-3GP

12

EC43

12

SCD1U16V2ZY-2GP

EC56

SCD1U16V2ZY-2GP

12

EC62

SCD1U => VOLTAGE 25V

BT+

12

SCD1U25V3ZY-3GP

EC67

EC67 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

CHG_PWR-3 47

12

EC36

SCD1U25V3ZY-3GP

12

EC1

SCD1U16V2ZY-2GP

EC46

SCD1U16V2ZY-2GP

12

EC24

SCD1U25V3ZY-3GP

1

12

SCD1U16V2ZY-2GP

EC47

SCD1U16V2ZY-2GP

12

1

12

EC30

DY

12

EC37

EC54

SCD1U16V2ZY-2GP

12

EC64

SCD1U25V3ZY-3GP

1

CHG_PWR-2 47

12

EC29

SC1500P50V3KX-GP

SC1000P50V2JN-N1

DY

1

12

EC61

SC1500P50V3KX-GP

DY

1

5130_LL1 45,46

12

EC26

SC1000P50V2JN-N1

DY

12

EC22

SC1500P50V3KX-GP

DY

12

EC18

SC1500P50V3KX-GP

DY

1

12

EC58

SC1000P50V2JN-N1

DY

MAX1544_LXM 41,42

12

EC19

SC1000P50V2JN-N1

DY

HOLE P/N: 34.42E05.001

FOR VGA CHIP

HOLE16

EC38

HOLE17

SCD1U25V3ZY-3GP

1

ZZ.0HOLE.XXX

Title

Size Document Number Rev

A3

Date: Sheet

1

ZZ.0HOLE.XXX

HOLE18

1

ZZ.0HOLE.XXX

FOR NORTH BRIDGE

HOLE19

HOLE21

ZZ.0HOLE.XXX

HOLE23

1

ZZ.0HOLE.XXX

Bolsena-E

HOLE14

ZZ.0HOLE.XXX

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

EMI

1

12

DY

12

DY

FOR MDC

1

58 58Thursday, October 13, 2005

1

5130_LL3 45,465130_LL2 45,46

12

EC31

EC63

SC1000P50V2JN-N1

SC1500P50V3KX-GP

DY

MAX1544_LXS 41,42

12

EC59

EC60

SC1000P50V2JN-N1

SC1500P50V3KX-GP

DY

HOLE15

1

ZZ.0HOLE.XXX

of

1

SA

A