Acer Aspire 3020, Aspire 5020 Schematics

5

4

3

2

1

Dummy when use EZ4

Dummy when no EZ4

Dummy when use 10/100

Dummy when use Giga

D D

Dummy when use UMA

Dummy when use Discrete

Dummy when use SATA

Dummy when use IDE

CLK GEN

IDT CV137

LEDs

Bolsena Block Diagram

AMD CPU

3

17

35W/25W

4,5,6,7

DDR 333/400

HyperTransport

PWR SW

TSP2220A

PCMCIA SLOT

Support TypeII

28

1394 4pin Conn

C C

28

PCMCIA I/F

MS/MSpro SDIO/MMC/SD

5 in 1

28

Mini-PCI

802.11a/b/g

31

RJ45

30

TXFM

1000Mb

30

TI

PCI 7411

1* Slot Cardbus 1* 1394

26,27

PCI LAN

Realtek

AGTL+ CPU I/F + UMA

PCI Bus / 33MHz

PCI

RTL8110SBL

B B

TXFM

10/100Mb

30

1000/100/10 RTL8100C 100/10

29

ATA 133

6.4GB/S 16b/8b

ATI

RS480M

11,12,13,14

PCI-Express x2

ATI

SB400

ACPI 2.0

18,19,20,21,22

6xUSB 2.0

6-CH AC97 2.2

LPC I/F

PCI Express x16

VRAM x4

HY5DS573222F

USB x 4

AC97

MODEM MDC Card

ATI

M26/M24

50,51,52

53,54

24

RJ11 CONN

91.4C501.001 (04243)

SiI1162

CODEC

ALC655

OP AMP

29

G1421

LPC Bus / 33MHz

200-PIN DDR SODIMM

DDR x2

8,9,10

SVIDEO/COMP

LVDS

RGB CRT

15

TMDS

BlueTooth miniUSB

32

3324

TVOUT

LCD

CRT

DVI-D

(EZ4 only )

Line In MIC In

Line Out

Int. SPKR

24

33

16

17

16

15

PCB Layer Stackup

L1: Signal 1 L2: GND L3: Signal 2 L4: Signal 3 L5: VCC L6: Signal 4

?modify power block

Battery Charger

INPUTS

AD+ BAT+

SYSTEM DC/DC

INPUT

DCBATOUT

SYSTEM DC/DC

INPUT

DCBATOUT 2D5V_S3

CPU V_CORE

INPUT

DCBATOUT

SYSTEM POWER

OUTPUTS

DCBATOUT

OUTPUT

5V_S5 , 3D3V_S5

OUTPUT

1D8V_S5 1D2V_S0

OUTPUT

VCC_CORE_S0

48

44

45,46

42,43

47

37

Thermal & Fan

G792

23

SATA

25

PIDE

HDD

25

SIDE

DVD/ CD-RW

NS SIO

PC87392

25

FIR

TFDU6102

A A

37

KBC

KB3910

Touch Pad

35 35

Int. KB

XBUS

34

ISA ROM

36

Port Replicator 4 (124 PIN)

AC IN

RJ45-11

SEARIAL PORT

5

CRT

PRINTER

PS2

4

MIC

LINE IN

LINE OUT

TV OUT

DVI PCIeX2 SMBUS

3

2

Title

BLOCK DIAGRAM

Size Document Number Rev

A3

Bolsena

Date: Sheet of

INPUT

2D5V_S3 DCBATOUT

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

OUTPUT

1D25V_S3 5V_AUX_S5

158Tuesday, December 28, 2004

1

SA

5

D D

C C

4

3

2

1

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

CHANGE HISTORY

Size Document Number Rev

Bolsena SA

A3

Date: Sheet

258Tuesday, December 28, 2004

1

of

A

3D3V_S0

L1

1 2

0R3-U

4 4

3 3

SB_OSC_CLK21

CLK14_AUDIO32

12

C1 SCD1U16V

C8 SCD1U16V

12

C2 SCD1U16V

C9 SCD1U16V

12

C3 SCD1U16V

12

C10 SCD1U16V

1 2

CLK48_CARDBUS26 CLK48_USB21 SMBC_SB8,21,57 SMBD_SB8,21,57

R8 33R2

R11 33R2

12

1 2

CLK14_NB13

CLK14_SIO37

C4 SCD1U16V

C11 SCD1U16V

C13 SC33P50V2JN

X1

X-14D318MHZ-1-U1

1 2

C14 SC33P50V2JN

B

12

C5 SC22U10V6ZY-U

3D3V_CLK_VDDA

3D3V_S0 3D3V_CLK_VDD

3D3VDD48_S0

L3

1 2

0R3-U

12

C12 SC2D2U16V5ZY

XI_CLK

XO_CLK

HTREF_CLK13

12

DY

R4

1 2

R5

1 2

R7

1 2

R6

1 2

R2 DUMMY-R3

22R2 22R2 0R2-0 0R2-0

1 2

1 2 1 2

12

R15 49D9R2F

USB_48M SMBC_CLK SMBD_CLK

R9 33R2

R10 33R2 R12 33R2

IREF_CLKGEN

12

FS2 FS1 FS0

CLK_REF2 CLK_HTT66

R16 475R2F

U1

3

VDD_48

39

VDDA

32

VDD_SRC

21

VDD_SRC

14

VDD_SRC

35

VDD_SRC

56

VDD_REF

51

VDD_PC1

43

VDD_CPU

48

VDD_HTT

1

XIN

2

XOUT

4

USB_48

7

SCL

8

SDA

10

CLKREQ0#

11

CLKREQ1#

9

SEL24/24_48#

53

REF1

54

REF0

52

REF2

47

HTT66

50

PCI0

37

IREF

6

NC#6

IDTCV137PAG

C

SRCC0 SRCT0 SRCC3 SRCT3 SRCC4 SRCT4 SRCC5 SRCT5 SRCC6 SRCT6 SRCC7 SRCT7

CPUC1 CPUT1 CPUC0 CPUT0

SRCC1 SRCT1 SRCC2 SRCT2

VSS_SRC VSS_SRC

RESET#

TURBO1

VSS_CPU

VSS_PCI

VSS_HTT

VSS_SRC

VSS_48

VSS_REF

VSSA

33 34 25 24 23 22 19 18 17 16 13 12

40 41 44 45

29 30 28 27

36 20 15 26

42 49 46 31 38 5 55

3D3V_CLK_VDDA3D3V_CLK_VDD

12

C6 SCD1U16V

SRC_CLK0# SRC_CLK0 SRC_CLK3# SRC_CLK3 SRC_CLK4# SRC_CLK4 SRC_CLK5# SRC_CLK5

CPUCLKJ_CY CPUCLK_CY

ATI_CLK0# ATI_CLK0 ATI_CLK1# ATI_CLK1

3D3V_S0

L2

1 2

12

1 2 1 2

RN5

2 3 1

SRN33-2-U2

1 2 3

0R3-U

C7 SC22U10V6ZY-U

RN1

2 3 1

RN2 SRN33-2-U2

1 2 3

SRN33-2-U2 RN3

1 2 3

SRN33-2-U2 RN4

1 2 3

SRN33-2-U2

Dummy when no EZ4

R1 15R2J

R3 15R2J

4

RN6

4

SRN33-2-U2

Dummy when use UMA

D

4 4

4

CPUCLK# 6 CPUCLK 6

NBSRC_CLK# 13 NBSRC_CLK 13

GFX_CLK# 49 GFX_CLK 49

SBLINK_CLK# 13 SBLINK_CLK 13

SBSRC_CLK# 18 SBSRC_CLK 18

CLK_PCIE_DOCK1# 57 CLK_PCIE_DOCK1 57

CLK_PCIE_DOCK2# 57 CLK_PCIE_DOCK2 57

SBLINK_CLK# SBLINK_CLK SBSRC_CLK# SBSRC_CLK GFX_CLK# GFX_CLK

E

1 2 1 2 1 2 1 2 1 2 1 2

R13 49D9R2F R14 49D9R2F R17 49D9R2F R18 49D9R2F R19 49D9R2F R20 49D9R2F

Dummy when use UMA

2 2

NBSRC_CLK# NBSRC_CLK

3D3V_CLK_VDD

1 1

1 2 1 2

1 2

1 2 1 2

R23 2K2R2 R24 DUMMY-R2

R25 2K2R2

R26 DUMMY-R2

R27 2K2R2 R28 DUMMY-R2

DY

FS0

DY

FS1

DY

FS2

DY

A

B

C

D

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

CLKGEN_IDTCV137

Bolsena

1 2 1 2

E

R21 49D9R2F R22 49D9R2F

358Tuesday, December 28, 2004

SA

of

A

1D2V_HT0A_S0

B

C

D

E

12

C19

SCD22U16V3ZY

4 4

3 3

12

C20 SCD22U16V3ZY

NB0CADOUT[15..0]11 NB0CADOUTJ[15..0]11

12

C21 SCD22U16V3ZY

Used SideB Power Plane

2 2

NB0HTTCLKOUT111 NB0HTTCLKOUTJ 111

1D2V_HT0B_S0

NB0HTTCLKOUT011 NB0HTTCLKOUTJ 011

1 2 1 2

NB0HTTCTLOUT11 NB0HTTCTLOUTJ11

12

C22 SCD22U16V3ZY

HTT for CPU sideA Transmit power and NB sideA Receive power

D29 D27 D25 C28 C26 B29 B27

T25 R25 U27 U26 V25

U25 W27 W26

AA27 AA26 AB25 AA25 AC27 AC26 AD25 AC25

T27

T28

V29

U29

V27

V28

Y29 W29

AB29 AA29 AB27 AB28 AD29 AC29 AD27 AD28

Y25 W25

Y27

Y28

R27

R26

T29

R29

U2A

VLDT0_A VLDT0_A VLDT0_A VLDT0_A VLDT0_A VLDT0_A VLDT0_A

L0_CADIN_H15 L0_CADIN_L15 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H0 L0_CADIN_L0

L0_CLKIN_H1 L0_CLKIN_L1 L0_CLKIN_H0 L0_CLKIN_L0

L0_CTLIN_H1 L0_CTLIN_L1 L0_CTLIN_H0 L0_CTLIN_L0

62.10030.041

VLDT0_B VLDT0_B VLDT0_B VLDT0_B VLDT0_B VLDT0_B VLDT0_B

L0_CADOUT_H15

L0_CADOUT_L15

L0_CADOUT_H14

L0_CADOUT_L14

L0_CADOUT_H13

L0_CADOUT_L13

L0_CADOUT_H12

L0_CADOUT_L12

L0_CADOUT_H11

L0_CADOUT_L11

L0_CADOUT_H10

L0_CADOUT_L10

L0_CADOUT_H9

L0_CADOUT_L9

L0_CADOUT_H8

L0_CADOUT_L8

L0_CADOUT_H7

L0_CADOUT_L7

L0_CADOUT_H6

L0_CADOUT_L6

L0_CADOUT_H5

L0_CADOUT_L5

L0_CADOUT_H4

L0_CADOUT_L4

L0_CADOUT_H3

L0_CADOUT_L3

L0_CADOUT_H2

L0_CADOUT_L2

L0_CADOUT_H1

L0_CADOUT_L1

L0_CADOUT_H0

L0_CADOUT_L0 L0_CLKOUT_H1

L0_CLKOUT_L1

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CTLOUT_H1

L0_CTLOUT_L1

L0_CTLOUT_H0

L0_CTLOUT_L0

AH29 AH27 AG28 AG26 AF29 AE28 AF25

N26 N27 L25 M25 L26 L27 J25 K25 G25 H25 G26 G27 E25 F25 E26 E27 N29 P29 M28 M27 L29 M29 K28 K27 H28 H27 G29 H29 F28 F27 E29 F29

J26 J27 J29 K29

N25 P25 P28 P27

CPUCADOUT15 CPUCADOUTJ15 CPUCADOUT14 CPUCADOUTJ14 CPUCADOUT13 CPUCADOUTJ13 CPUCADOUT12 CPUCADOUTJ12 CPUCADOUT11 CPUCADOUTJ11 CPUCADOUT10 CPUCADOUTJ10 CPUCADOUT9 CPUCADOUTJ9 CPUCADOUT8 CPUCADOUTJ8 CPUCADOUT7 CPUCADOUTJ7 CPUCADOUT6 CPUCADOUTJ6 CPUCADOUT5 CPUCADOUTJ5 CPUCADOUT4 CPUCADOUTJ4 CPUCADOUT3 CPUCADOUTJ3 CPUCADOUT2 CPUCADOUTJ2 CPUCADOUT1 CPUCADOUTJ1 CPUCADOUT0 CPUCADOUTJ0

CPUHTTCLKOUT1 CPUHTTCLKOUTJ1 CPUHTTCLKOUT0 CPUHTTCLKOUTJ0

CPUHTTCTLOUT0 CPUHTTCTLOUTJ0

1D2V_HT0A_S0 1D2V_HT0B_S0

NB0CADOUT15 NB0CADOUTJ15 NB0CADOUT14 NB0CADOUTJ14 NB0CADOUT13 NB0CADOUTJ13 NB0CADOUT12 NB0CADOUTJ12 NB0CADOUT11 NB0CADOUTJ11 NB0CADOUT10 NB0CADOUTJ10 NB0CADOUT9 NB0CADOUTJ9 NB0CADOUT8 NB0CADOUTJ8 NB0CADOUT7 NB0CADOUTJ7 NB0CADOUT6 NB0CADOUTJ6 NB0CADOUT5 NB0CADOUTJ5 NB0CADOUT4 NB0CADOUTJ4 NB0CADOUT3 NB0CADOUTJ3 NB0CADOUT2 NB0CADOUTJ2 NB0CADOUT1 NB0CADOUTJ1 NB0CADOUT0 NB0CADOUTJ0

NB0HTTCLKOUT1 NB0HTTCLKOUTJ1 NB0HTTCLKOUT0 NB0HTTCLKOUTJ0

R29 49D9R3F

R30 49D9R3F

CPUHTTCTLIN1 CPUHTTCTLINJ1 NB0HTTCTLOUT NB0HTTCTLOUTJ

HTT for CPU sideB Receive power and NB sideA Transmit power

12

C23 SC4D7U10V5ZY

Used SideA Power Plane

CPUHTTCLKOUT1 11 CPUHTTCLKOUTJ1 11 CPUHTTCLKOUT0 11 CPUHTTCLKOUTJ0 11

CPUHTTCTLOUT0 11 CPUHTTCTLOUTJ0 11

LAYOUT: Place bypass cap on topside of board near HTT power pins that are not connected directly to downstream HTT device, but connected internally to other HTT power pins.

CPUCADOUT[15..0] 11 CPUCADOUTJ[15..0] 11

By ME requset U11 P/N:

1 1

Main 62.10030.041 Second 62.10053.191 Third 62.10053.201

A

B

C

BGA754-SKT-U

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

D

Date: Sheet

CPU(1/4)_HyperTransport I/F

Bolsena

458Tuesday, December 28, 2004

E

of

SA

A

B

C

D

E

U2B

MEMRESET_L

MEMCLK_H7 MEMCLK_L7 MEMCLK_H6 MEMCLK_L6 MEMCLK_H5 MEMCLK_L5 MEMCLK_H4 MEMCLK_L4 MEMCLK_H3 MEMCLK_L3 MEMCLK_H2 MEMCLK_L2 MEMCLK_H1 MEMCLK_L1 MEMCLK_H0 MEMCLK_L0

MEMCS_L7 MEMCS_L6 MEMCS_L5 MEMCS_L4 MEMCS_L3 MEMCS_L2 MEMCS_L1 MEMCS_L0

MEMRASA_L MEMCASA_L

MEMWEA_L

MEMBANKA1 MEMBANKA0

MEMADDA13 MEMADDA12 MEMADDA11 MEMADDA10

MEMADDA9 MEMADDA8 MEMADDA7 MEMADDA6 MEMADDA5 MEMADDA4 MEMADDA3 MEMADDA2 MEMADDA1 MEMADDA0

MEMRASB_L MEMCASB_L

MEMWEB_L

MEMBANKB1 MEMBANKB0

MEMADDB13 MEMADDB12 MEMADDB11 MEMADDB10

MEMADDB9 MEMADDB8 MEMADDB7 MEMADDB6 MEMADDB5 MEMADDB4 MEMADDB3 MEMADDB2 MEMADDB1 MEMADDB0

MEMCHECK7 MEMCHECK6 MEMCHECK5 MEMCHECK4 MEMCHECK3 MEMCHECK2 MEMCHECK1 MEMCHECK0

C

VTT_A VTT_A VTT_A VTT_A VTT_B VTT_B VTT_B VTT_B

MEMCKEA MEMCKEB

NC_E13 NC_C12

NC_E14 NC_D12

D17 A18 B17 C17 AF16 AG16 AH16 AJ17

AG10 AE8

AE7 D10

C10 E12 E11 AF8 AG8 AF10 AE10 V3 V4 K5 K4 R5 P5 P3 P4

D8 C8 E8 E7 D6 E6 C4 E5

H5 D4 G5

K3 H3

E13 C12 E10 AE6 AF3 M5 AE5 AB5 AD3 Y5 AB4 Y3 V5 T5 T3 N5

H4 F5 F4

L5 J5

E14 D12 E9 AF6 AF4 M4 AD5 AC5 AD4 AA5 AB3 Y4 W5 U5 T4 M3

N3 N1 U3 V1 N2 P1 U1 U2

BGA754-SKT-U

4 4

2D5V_S3

VREF_DDR_CLAW

R32

1 2

34D8R2F

R31

1 2

34D8R2F

TP1 TPAD30

DDRVTT_SENSE

MEMZN MEMZP

AE13

AG12

D14 C14

VTT_SENSE

MEMVREF1 MEMZN

MEMZP

VREF_DDR_MEM

NOTE: Test wi th p assive probes only.

M_DATA[63..0]9

2D5V_S3

3 3

NOTE: Install to bypass op-amp

12

R33 100R3F

R34 100R3F

12

C27 SCD1U

12

VREF_DDR_MEM

C28 SCD1U

12

C25 SC1000P50V2KX

LAYOUT: L ocate close to D IMMs.

NOTE: Remove to bypass op-amp

2 2

VREF_DDR_CLAW

2D5V_S3

12

1 1

12

R35 100R3

R36 100R3

C29 SCD1U

12

C30 SCD1U

VREF_DDR_CLAW

LAYOUT: Locate close to CPU .

A

12

C31 SC1000P50V2KX

M_ADM[7..0]9

M_DQS[7..0]9

B

M_DATA63 M_DATA62 M_DATA61 M_DATA60 M_DATA59 M_DATA58 M_DATA57 M_DATA56 M_DATA55 M_DATA54 M_DATA53 M_DATA52 M_DATA51 M_DATA50 M_DATA49 M_DATA48 M_DATA47 M_DATA46 M_DATA45 M_DATA44 M_DATA43 M_DATA42 M_DATA41 M_DATA40 M_DATA39 M_DATA38 M_DATA37 M_DATA36 M_DATA35 M_DATA34 M_DATA33 M_DATA32 M_DATA31 M_DATA30 M_DATA29 M_DATA28 M_DATA27 M_DATA26 M_DATA25 M_DATA24 M_DATA23 M_DATA22 M_DATA21 M_DATA20 M_DATA19 M_DATA18 M_DATA17 M_DATA16 M_DATA15 M_DATA14 M_DATA13 M_DATA12 M_DATA11 M_DATA10 M_DATA9 M_DATA8 M_DATA7 M_DATA6 M_DATA5 M_DATA4 M_DATA3 M_DATA2 M_DATA1 M_DATA0

M_ADM8 M_ADM7 M_ADM6 M_ADM5 M_ADM4 M_ADM3 M_ADM2 M_ADM1 M_ADM0 M_DQS8 M_DQS7 M_DQS6 M_DQS5 M_DQS4 M_DQS3 M_DQS2 M_DQS1 M_DQS0

A16 B15 A12 B11 A17 A15 C13 A11 A10

C11

AC1 AC3

AC2 AD1 AE1 AE3

AG3

AJ4

AE2

AF1

AH3

AJ3 AJ5 AJ6

AJ7 AH9 AG5 AH5

AJ9

AJ10

AH11

AJ11

AH15

AJ15

AG11

AJ12 AJ14 AJ16

A13

AA1 AG1 AH7

AH13

A14

AB1

AJ2

AJ8

AJ13

B9 C7 A6

A9 A5 B5 C5 A4 E2 E1 A3 B3 E3

F1 G2 G1

L3

L1 G3

J2

L2 M1 W1 W3

W2

Y1

R1

A7

C2

H1

T1

A8

D1

J1

MEMDATA63 MEMDATA62 MEMDATA61 MEMDATA60 MEMDATA59 MEMDATA58 MEMDATA57 MEMDATA56 MEMDATA55 MEMDATA54 MEMDATA53 MEMDATA52 MEMDATA51 MEMDATA50 MEMDATA49 MEMDATA48 MEMDATA47 MEMDATA46 MEMDATA45 MEMDATA44 MEMDATA43 MEMDATA42 MEMDATA41 MEMDATA40 MEMDATA39 MEMDATA38 MEMDATA37 MEMDATA36 MEMDATA35 MEMDATA34 MEMDATA33 MEMDATA32 MEMDATA31 MEMDATA30 MEMDATA29 MEMDATA28 MEMDATA27 MEMDATA26 MEMDATA25 MEMDATA24 MEMDATA23 MEMDATA22 MEMDATA21 MEMDATA20 MEMDATA19 MEMDATA18 MEMDATA17 MEMDATA16 MEMDATA15 MEMDATA14 MEMDATA13 MEMDATA12 MEMDATA11 MEMDATA10 MEMDATA9 MEMDATA8 MEMDATA7 MEMDATA6 MEMDATA5 MEMDATA4 MEMDATA3 MEMDATA2 MEMDATA1 MEMDATA0

MEMDQS17 MEMDQS16 MEMDQS15 MEMDQS14 MEMDQS13 MEMDQS12 MEMDQS11 MEMDQS10 MEMDQS9 MEMDQS8 MEMDQS7 MEMDQS6 MEMDQS5 MEMDQS4 MEMDQS3 MEMDQS2 MEMDQS1 MEMDQS0

1D25V_S3

MEMRESET# M_CKE#0

M_CKE#1 M_CLK7

M_CLK#7 M_CLK6 M_CLK#6 M_CLK5 M_CLK#5 M_CLK4 M_CLK#4

M_CLK1 M_CLK#1 M_CLK0 M_CLK#0

M_CS#7 M_CS#6 M_CS#5 M_CS#4 M_CS#3 M_CS#2 M_CS#1 M_CS#0

M_ARAS# M_ACAS# M_AWE#

M_ABS#1 M_ABS#0

RSVD_M_AA15 RSVD_M_AA14 M_AA13 M_AA12 M_AA11 M_AA10 M_AA9 M_AA8 M_AA7 M_AA6 M_AA5 M_AA4 M_AA3 M_AA2 M_AA1 M_AA0

M_BRAS# M_BCAS# M_BWE#

M_BBS#1 M_BBS#0

RSVD_M_BA15 RSVD_M_BA14 M_BA13 M_BA12 M_BA11 M_BA10 M_BA9 M_BA8 M_BA7 M_BA6 M_BA5 M_BA4 M_BA3 M_BA2 M_BA1 M_BA0

CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0

12

C24 SCD1U

For REGISTED DIMM Only UNBUFFER DIMM NC

TP16 TP15

TPAD30 TP18

TPAD30 TPAD30

TP17 TP20

TPAD30 TP19

TPAD30 TPAD30

TP22 TPAD30

TP21 TPAD30

D

C26 SC1000P50V2KX

M_CKE#0 8,9 M_CKE#1 8,9

M_CLK7 8,9 M_CLK#7 8,9 M_CLK6 8,9 M_CLK#6 8,9 M_CLK5 8,9 M_CLK#5 8,9 M_CLK4 8,9 M_CLK#4 8,9

M_CLK#1 M_CLK#0 M_CLK1 M_CLK0

M_CS#3 8,9 M_CS#2 8,9 M_CS#1 8,9 M_CS#0 8,9

M_ARAS# 8,9 M_ACAS# 8,9 M_AWE# 8,9

M_ABS#1 8,9 M_ABS#0 8,9

M_AA[13..0] 8,9

AMD suggested M_AA13 connect to DIMM pin123

M_BRAS# 8,9 M_BCAS# 8,9 M_BWE# 8,9

M_BBS#1 8,9 M_BBS#0 8,9

M_BA[13..0] 8,9

AMD suggested M_BA13 connect to DIMM pin123

Title

Size Document Number Rev

A3

Date: Sheet of

2D5V_S3

RN7

1

8

2

7

3

6

45

SRN10K-2

M_DQS8 M_ADM8

MEMRESET# M_CS#7 M_CS#6 M_CS#5 M_CS#4 RSVD_M_AA15 RSVD_M_AA14 RSVD_M_BA15 RSVD_M_BA14

NOT SUPPORT ECC CHECK AMD suggested remove PULL-HI resistor.

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

CPU(2/4)_DDR

Bolsena

558Tuesday, December 28, 2004

E

TP5 TP4

TPAD30 TPAD30

TP7 TP6

TPAD30 TPAD30

TP8 TPAD30

TP10 TP9

TPAD30 TPAD30

TP11 TP12

TPAD30 TPAD30

TP14 TPAD30

TP13 TPAD30

SA

A

2D5V_VDDA_S0

2D5V_S0

4 4

12

2D5V_CPUA_S0

R39

1 2

0R3-U

C35 SC10U10V5ZY

1 2

63.R0004.151

DY

2D5V_CPUR_S0

R40 0R3-U

12

1 2

TC1 ST100U4VBM-1

AMD SUGGEST TO USE 2D5V_CPUA_S0

KEMET,NT:5.7, B2 size ST100U4VBM-1 (80.10716.321)

3 3

2D5V_S0

2 2

DBREQJ

DY

DBRDY TCK TMS TDI TRST_L TDO

2D5V_S3

CHANGE FROM 1KR3 TO 680R2 FOR AMD CHECK LIST

NC_AG17 NC_AJ18 NC_D18

NC_B19

1 1

NC_C19 NC_D20 NC_C21

Iripple=1.1A,ESR=70mohm

SANYO, NT$:6.1 Iripple=1.1A,ESR=70mohm

3.5/2.8/2.0

77.21071.031

678

C44 SCD1U

RN8

123

SRN680-U

DY

1 2

DY

RN10

1 2 3 4 5

RN11

SRN680-U

1 2 3 4 5

SRN680-U

R57 680R3

A

4 5

8 7 6

12

AMD SUGGEST TO USE 100 ~ 300UH

Change L270H

2D5V_VDDA_S0

R59 0R5J-1

12

DY

LAYOUT: Rou te tr ace 50 mils wide and 500 to 750 mils long between these caps.

12

C39 SC4D7U10V5ZY

78.47593.411 1D2V_HT0B_S0

12

R53

R54

680R3

DY

1 2 1 2

64.44R25.551

AMD suggest voltege from 2D5V_S0 to 2D5V_S3

differentially im pedance 100

B

3D3V_S0

12

C33 SC1U10V3KX

LAYOUT: Route VDDA trace approx. 50 mils wid e (use 2x25 mil traces to exit ball field) and 500 mils long.

1 2 1 2

12

C40 SCD22U16V3ZY

12

R46 820R3

R42 820R3

1 2 1 2 1 2

C41 SC1000P50V2KX

CPUCLK3

CPUCLK#3

R48 680R3

R43 680R3

R50 680R3

2D5V_S0

LDT_RST#18 SB_CPUPWRGD18 LDT_STP#13,18

1 2

COREFB#41

1D25V_S3

2D5V_S0

COREFB41

C42 SC3900P50V3KX

C38 SC3900P50V3KX

R44 44D2R3F

R41 44D2R3F

12

C36 SC3300P50V2KX

12

2D5V_S3

LDT_RST# SB_CPUPWRGD LDT_STP#

C37 SC1000P50V2KX

Validation Test Points

LAYOUT: Place close to the CPU.

NC_C15 NC_AE23 NC_AF23 NC_AF22 NC_AF21

B

TP28 TPAD30

TP30 TPAD30 TP34

TPAD30 TPAD30

TP35 TPAD30

LDT_RST# CLKIN CLKIN# CORE_SENSE VDDIOFB VDDIOFBJ VDDIOSENSE NC_AE24 NC_AF24

C

Iomax=120mA

U3

1

SHDN#

2

GND

3

IN

G913C-U

DY

12

R51

1 2

680R3 R52

1 2

680R3

678

RN9

123

SRN680-U

DY

C

SET

OUT

L0_REF1 L0_REF0

COREFB COREFB# CORE_SENSE

VDDIOFB VDDIOFBJ VDDIOSENSE

CLKIN

R45 169R3F

CLKIN# NC_AJ23 NC_AH23 NC_AE24 NC_AF24

DBRDY NC_C15 TMS

TCK TRST_L

TDI

NC_AE23 NC_AF23 NC_AF22 NC_AF21

4 5

TP26 TP25

TPAD30 TPAD30

TP27 TPAD30

TP29 TP31

TPAD30 TPAD30

TP33 TPAD30TP32

TP37 TP36

TPAD30 TPAD30

TP38 TPAD30

2D5V_CPUA_S0

2D5V_VDDA_VREF

5 4

NC_C18 NC_A19

12

C34 SC1U10V3KX

AH25

AJ25 AF20

AE18

AJ27

AF27 AE26

A23 A24 B23

AE12 AF12 AE11

AJ21

AH21

AJ23

AH23

AE24 AF24

C16

AG15 AH17

C15 E20

E17 B21 A21

C18 A19 A28

AJ28

AE23 AF23 AF22 AF21

C1

J3

R3

AA2

D3

AG2

B18

AH1

AE21

C20

AG4

C6 AG6 AE9 AG9

12

C32 SC22P50V2JN-1

U2C

VDDA1 VDDA2

RESET_L PWROK LDTSTOP_L

L0_REF1 L0_REF0

COREFB_H COREFB_L CORE_SENSE

VDDIOFB_H VDDIOFB_L VDDIO_SENSE

CLKIN_H CLKIN_L

NC_AJ23 NC_AH23

NC_AE24 NC_AF24

VTT_A VTT_B

DBRDY NC_C15 TMS

TCK TRST_L TDI

NC_C18 NC_A19 KEY1

KEY0 NC_AE23

NC_AF23 NC_AF22 NC_AF21

NC_C1 NC_J3 NC_R3 NC_AA2 NC_D3 NC_AG2 NC_B18 NC_AH1 NC_AE21 NC_C20 NC_AG4 NC_C6 NC_AG6 NC_AE9 NC_AG9

BGA754-SKT-U

D

12

R37

R1

20KR3F

12

DY

R38 20KR3F

Vout = 1.25*(1+ R1/R2)

R2

E

DY

THERMTRIP#

THERMDA THERMDC

VID4 VID3 VID2 VID1 VID0

NC_AG18 NC_AH18 NC_AG17

NC_AJ18

DBREQ_L

NC_D20 NC_C21 NC_D18 NC_C19 NC_B19

TDO

NC_AF18

A20 A26

A27 AG13

AF14 AG14 AF15 AE15

AG18 AH18 AG17 AJ18

AH19 AJ19

AE19 D20

C21 D18 C19 B19

A22

AF18

THERMDP 23

VID4 VID3 VID2 VID1 VID0

NC_AG18 NC_AH18 NC_AG17 NC_AJ18

FBCLKOUT

FBCLKOUTJ

DBREQJ

NC_D20 NC_C21 NC_D18 NC_C19 NC_B19

TDO

THERMDN 23

TP23 TP24

TPAD30 TPAD30

LAYOUT: Route FBCLKOUT_H/L

differentially i mpedance 80

12

R47 80D6R3F-U

R49

1 2

DUMMY-R3

DY

2D5V_S3

VID[4..0] 41

THERMTRIP_L

FBCLKOUT_H

FBCLKOUT_L

Connect to VDDIO for AMD suggest.

D22

NC_D22

C22

NC_C22

NC_B13

NC_B7 NC_C3 NC_K1 NC_R2

NC_AA3

NC_F3 NC_C23 NC_AG7

NC_AE22

NC_C24 NC_A25

NC_C9

B13 B7 C3 K1 R2 AA3 F3 C23 AG7 AE22 C24 A25 C9

THERMTRIP#

2D5V_S0

12

2

R55 680R3

1

3D3V_S5

3

Q1 MMBT3904-U1

NS3

1 2

12

R56 10KR2

CPU_THERMTRIP# 21,23

2D5V_S0

R58 1KR2

THERMTRIP#Level shift to SB400

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

D

Date: Sheet of

CPU(3/4)_Control & Debug

Bolsena

658Tuesday, December 28, 2004

E

SA

A

VCC_CORE_S0 2D5V_S3

N20

Y17

VSS

K17

VSS

H17

VSS

F17

U2E

VSS

E18

VSS

AJ26

VSS

AE29

VSS

AC16

VSS

AA16

VSS

J16

VSS

G16

VSS

E16

VSS

AH14

4 4

3 3

2 2

1 1

AD15 AB15

K15 E15

D16 AE14 AC14 AA14

G14

AF17 AD13 AB13

Y13 K13 H13

F13 AH12 AC12 AA12

G12

B12 AD11 AB11

Y11

K11

H11

F11 AH10 AC10

W10

U10

R10

N10

G10

B10

AD9

AH8 AC8

AD7

AB7

AH6 AC6

AA6

AH4 AH2

AD2

AB2

C29 AH28

AF28

AC28

W28

R28

VSS VSS VSS VSS VSS VSS VSS VSS VSS

J14

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

L10

VSS

J10

VSS VSS VSS VSS

Y9

VSS

V9

VSS

T9

VSS

P9

VSS

M9

VSS

K9

VSS

H9

VSS

F9

VSS VSS VSS

W8

VSS

U8

VSS

R8

VSS

N8

VSS

L8

VSS

J8

VSS

G8

VSS

B8

VSS VSS VSS

V7

VSS

T7

VSS

P7

VSS

M7

VSS

K7

VSS

H7

VSS

F7

VSS VSS VSS VSS

U6

VSS

R6

VSS

N6

VSS

L6

VSS

J6

VSS

G6

VSS

B6

VSS VSS

B4

VSS VSS VSS VSS

Y2

VSS

V2

VSS

T2

VSS

P2

VSS

M2

VSS

K2

VSS

H2

VSS

F2

VSS VSS VSS VSS VSS VSS VSS

L28

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

L20 J20 AF19 AD19 AB19 Y19 K19 H19 F19 D19 AC18 AA18 G18 B16 AD17 AB17 H15 F15 G28 D28 B28 C27 AH26 AF26 AD26 Y26 T26 M26 H26 D26 B26 C25 B25 AJ24 AG24 AC24 AA24 W24 U24 R24 N24 J24 G24 E24 AG23 AD23 AB23 Y23 V23 T23 P23 K23 H23 F23 D23 AJ22 AH22 AG22 AC22 AA22 AG29 U22 R22 N22 L22 J22 G22 E22 B22 AG21 AD21 Y21 V21 T21 P21 M21 K21 H21 F21 D21 AJ20 AG20 AE20 AC20 AA20 W20 U20 R20 G20 J18 AE16 Y15 B14 J12 AA10 AB9 AA8 Y7 W6 AF2 D2 AG27 AG25 L24 M23 W22 AB21 AH20 B2

A

AC15

H18 B20 E21 H22

H24 F26

V10 G13 K14 Y14

AB14

G15

AA15

H16 K16 Y16

AB16

G17

AA17 AC17 AE17

F18 K18

Y18 AB18 AD18 AG19

E19

G19 AC19 AA19

F20

H20

K20

M20

P20

T20

V20

Y20 AB20 AD20

G21

N21

R21

U21

W21 AA21 AC21

F22 K22 M22 P22 T22 V22

Y22 AB22 AD22

E23

G23

N23

R23

U23

W23 AA23 AC23

B24 D24 F24 K24 M24 P24 T24 V24

Y24 AB24 AD24 AH24 AE25

K26

P26

V26

L7

VDD VDD VDD VDD

U2D

VDD VDD

J23

VDD VDD VDD

N7

VDD

L9

VDD VDD VDD VDD VDD VDD VDD

J15

VDD VDD VDD VDD VDD VDD VDD

J17

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

J19

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

J21

VDD

L21

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

L23

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

E4 G4 J4 L4 N4 U4 W4 AA4 AC4 AE4 D5 AF5 F6 H6 K6 M6 P6 T6 V6 Y6 AB6 AD6 D7 G7 J7 AA7 AC7 AF7 F8 H8 AB8 AD8 D9 G9 AC9 AF9 F10 AD10 D11 AF11 F12 AD12 D13 AF13 F14 AD14 F16 AD16 D15 R4

N28 U28 AA28 AE27 R7 U7 W7 K8 M8 P8 T8 V8 Y8 J9 N9 R9 U9 W9 AA9 H10 K10 M10 P10 T10 Y10 AB10 G11 J11 AA11 AC11 H12 K12 Y12 AB12 J13 AA13 AC13 H14 AB26 E28 J28

B

VCC_CORE_S0

B

VCC_CORE_S0

12

VCC_CORE_S0

C55 SCD22U16V3ZY

1 2

0.22u x 4

DY

2D5V_S3

12

C61 SCD22U16V3ZY

1D25V_S3

12

C74 SCD22U16V3ZY

0.22u x 2

C

LAYOUT: Place in uPGA socket cavity.

0.22u x 6

12

C45

C46

SCD22U16V3ZY

12

C47 SCD22U16V3ZY

12

C48 SCD22U16V3ZY

12

C49 SCD22U16V3ZY

12

C50 SCD22U16V3ZY

LAYOUT: Place on backside of processor.

C56 SCD22U16V3ZY

1 2

C57 SCD22U16V3ZY

1 2

C58 SCD22U16V3ZY

1 2

12

C59 SC10U10V5ZY

C60 SC10U10V5ZY

12

10u x 2

DY

12

DY

12

C63

C62

SCD22U16V3ZY

12

C64 SCD22U16V3ZY

12

C65 SCD22U16V3ZY

12

C66 SCD22U16V3ZY

2D5V_S3

10u x 1 4.7u x 6

1D25V_S3

12

C75 SCD22U16V3ZY

C77

C76

SC4D7U10V5ZY

4.7u x 2

C

12

C67 SC10U10V5ZY

10u x 4

12

C51 SC10U10V5ZY

12

C68 SC4D7U10V5ZY

12

C52 SC10U10V5ZY

12

C69 SC4D7U10V5ZY

D

12

C53 SC10U10V5ZY

12

C70 SC4D7U10V5ZY

D

BGA754-SKT-U

C54 SC10U10V5ZY

12

C71 SC4D7U10V5ZY

E

BGA754-SKT-U

12

78.47593.411

C72

C73

SC4D7U10V5ZY

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

CPU(4/4)_Power

Bolsena

758Tuesday, December 28, 2004

E

SA

of

A

M_AA0 M_AA1 M_AA2 M_AA3 M_AA4 M_AA5 M_AA6 M_AA7 M_AA8 M_AA9 M_AA10 M_AA11

4 4

3 3

2 2

1 1

M_ARAS#5,9 M_ACAS#5,9 M_AWE#5,9

VREF_DDR_MEM VREF_DDR_MEM

Layout trace 20 mil Layout trace 20 mil

M_AA12 M_ABS#0

M_ABS#1 M_DATA_R_0

M_DATA_R_1 M_DATA_R_2 M_DATA_R_3 M_DATA_R_4 M_DATA_R_5 M_DATA_R_6 M_DATA_R_7 M_DATA_R_8 M_DATA_R_9 M_DATA_R_10 M_DATA_R_11 M_DATA_R_12 M_DATA_R_13 M_DATA_R_14 M_DATA_R_15 M_DATA_R_16 M_DATA_R_17 M_DATA_R_18 M_DATA_R_19 M_DATA_R_20 M_DATA_R_21 M_DATA_R_22 M_DATA_R_23 M_DATA_R_24 M_DATA_R_25 M_DATA_R_26 M_DATA_R_27 M_DATA_R_28 M_DATA_R_29 M_DATA_R_30 M_DATA_R_31 M_DATA_R_32 M_DATA_R_33 M_DATA_R_34 M_DATA_R_35 M_DATA_R_36 M_DATA_R_37 M_DATA_R_38 M_DATA_R_39 M_DATA_R_40 M_DATA_R_41 M_DATA_R_42 M_DATA_R_43 M_DATA_R_44 M_DATA_R_45 M_DATA_R_46 M_DATA_R_47 M_DATA_R_48 M_DATA_R_49 M_DATA_R_50 M_DATA_R_51 M_DATA_R_52 M_DATA_R_53 M_DATA_R_54 M_DATA_R_55 M_DATA_R_56 M_DATA_R_57 M_DATA_R_58 M_DATA_R_59 M_DATA_R_60 M_DATA_R_61 M_DATA_R_62 M_DATA_R_63

12

A

3D3V_S0

C519 SCD1U

TP126 TPAD30

DDR1

112

A0

111

A1

110

A2

109

A3

108

A4

107

A5

106

A6

105

A7

102

A8

101

A9

115

A10 / AP

100

A11

99

A12

117

BA0

116

BA1

5

DQ0

7

DQ1

13

DQ2

17

DQ3

6

DQ4

8

DQ5

14

DQ6

18

DQ7

19

DQ8

23

DQ9

29

DQ10

31

DQ11

20

DQ12

24

DQ13

30

DQ14

32

DQ15

41

DQ16

43

DQ17

49

DQ18

53

DQ19

42

DQ20

44

DQ21

50

DQ22

54

DQ23

55

DQ24

59

DQ25

65

DQ26

67

DQ27

56

DQ28

60

DQ29

66

DQ30

68

DQ31

127

DQ32

129

DQ33

135

DQ34

139

DQ35

128

DQ36

130

DQ37

136

DQ38

140

DQ39

141

DQ40

145

DQ41

151

DQ42

153

DQ43

142

DQ44

146

DQ45

152

DQ46

154

DQ47

163

DQ48

165

DQ49

171

DQ50

175

DQ51

164

DQ52

166

DQ53

172

DQ54

176

DQ55

177

DQ56

181

DQ57

187

DQ58

189

DQ59

178

DQ60

182

DQ61

188

DQ62

190

DQ63

71

CB0

73

CB1

79

CB2

83

CB3

72

CB4

74

CB5

80

CB6

84

CB7

85

NC#85

86

NC#86/(RESET#)

97

NC#97/A13

98

NC#98/BA2

123

NC#123

124

NC#124

200

NC#200

118

/RAS

120

/CAS

119

/WE

1

VREF

2

VREF

197

VDDSPD

199

VDDID

201

GND

SKT-SODIMM200-24

/CS0 /CS1

CKE0 CKE1

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8

CK0

/CK0

CK1

/CK1

CK2

/CK2

SCL SDA

SA0 SA1 SA2

VDD VDD VDD VDD VDD VDD VDD

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS

REVERSE TYPE 5.2MM

VSS

VSS GND

121 122

96 95

11 25 47 61 133 147 169 183 77

12 26 48 62 134 148 170 184 78

35 37 160 158 89 91

195 193

194 196 198

9 10 21 22 33 34 36 45 46 57 58 69 70 81 82 92 93 94 113 114 131 132 143 144 155 156 157 167 168 179 180 191 192

3 4 15 16 27 28 38 39 40 51 52 63 64 75 76 87 88 90 103 104 125 126 137 138 149 150 159 161 162 173 174 185 186

202

B

M_CKE#0

M_DQS_R0 M_DQS_R1 M_DQS_R2 M_DQS_R3 M_DQS_R4 M_DQS_R5 M_DQS_R6 M_DQS_R7

M_ADM_R0 M_ADM_R1 M_ADM_R2 M_ADM_R3

M_ADM_R5 M_ADM_R6 M_ADM_R7

DDR_CLK0 DDR_CLK#0

SMBC_SB SMBD_SB

NOT SUPPORT ECC CHECK AMD suggested pull-low

2D5V_S3

M_ADM#0 M_ADM#1 M_ADM#2 M_ADM#3 M_ADM#4 M_ADM#5 M_ADM#6 M_ADM#7

M_CLK5 5,9 M_CLK#5 5,9 M_CLK7 5,9 M_CLK#7 5,9

62.10017.701

B

C

M_CS#0 5,9 M_CS#1 5,9

M_CKE#0 5,9 M_CKE#1 5,9

M_BRAS#5,9 M_BCAS#5,9 M_BWE#5,9

M_BA0 M_BA1 M_BA2 M_BA3 M_BA4 M_BA5 M_BA6 M_BA7 M_BA8 M_BA9 M_BA10 M_BA11 M_BA12

M_BBS#0 M_BBS#1

M_DATA_R_0 M_DATA_R_1 M_DATA_R_2 M_DATA_R_3 M_DATA_R_4 M_DATA_R_5 M_DATA_R_6 M_DATA_R_7 M_DATA_R_8 M_DATA_R_9 M_DATA_R_10 M_DATA_R_11 M_DATA_R_12 M_DATA_R_13 M_DATA_R_14 M_DATA_R_15 M_DATA_R_16 M_DATA_R_17 M_DATA_R_18 M_DATA_R_19 M_DATA_R_20 M_DATA_R_21 M_DATA_R_22 M_DATA_R_23 M_DATA_R_24 M_DATA_R_25 M_DATA_R_26 M_DATA_R_27 M_DATA_R_28 M_DATA_R_29 M_DATA_R_30 M_DATA_R_31 M_DATA_R_32 M_DATA_R_33 M_DATA_R_34 M_DATA_R_35 M_DATA_R_36 M_DATA_R_37 M_DATA_R_38 M_DATA_R_39 M_DATA_R_40 M_DATA_R_41 M_DATA_R_42 M_DATA_R_43 M_DATA_R_44 M_DATA_R_45 M_DATA_R_46 M_DATA_R_47 M_DATA_R_48 M_DATA_R_49 M_DATA_R_50 M_DATA_R_51 M_DATA_R_52 M_DATA_R_53 M_DATA_R_54 M_DATA_R_55 M_DATA_R_56 M_DATA_R_57 M_DATA_R_58 M_DATA_R_59 M_DATA_R_60 M_DATA_R_61 M_DATA_R_62 M_DATA_R_63

M_BA13M_AA13

12

3D3V_S0

C520 SCD1U

TP127 TPAD30

DDR2

112

A0

111

A1

110

A2

109

A3

108

A4

107

A5

106

A6

105

A7

102

A8

101

A9

115

A10 / AP

100

A11

99

A12

117

BA0

116

BA1

5

DQ0

7

DQ1

13

DQ2

17

DQ3

6

DQ4

8

DQ5

14

DQ6

18

DQ7

19

DQ8

23

DQ9

29

DQ10

31

DQ11

20

DQ12

24

DQ13

30

DQ14

32

DQ15

41

DQ16

43

DQ17

49

DQ18

53

DQ19

42

DQ20

44

DQ21

50

DQ22

54

DQ23

55

DQ24

59

DQ25

65

DQ26

67

DQ27

56

DQ28

60

DQ29

66

DQ30

68

DQ31

127

DQ32

129

DQ33

135

DQ34

139

DQ35

128

DQ36

130

DQ37

136

DQ38

140

DQ39

141

DQ40

145

DQ41

151

DQ42

153

DQ43

142

DQ44

146

DQ45

152

DQ46

154

DQ47

163

DQ48

165

DQ49

171

DQ50

175

DQ51

164

DQ52

166

DQ53

172

DQ54

176

DQ55

177

DQ56

181

DQ57

187

DQ58

189

DQ59

178

DQ60

182

DQ61

188

DQ62

190

DQ63

71

CB0

73

CB1

79

CB2

83

CB3

72

CB4

74

CB5

80

CB6

84

CB7

85

NC#85

86

NC#86/(RESET#)

97

NC#97/A13

98

NC#98/BA2

123

NC#123

124

NC#124

200

NC#200

118

/RAS

120

/CAS

119

/WE

1

VREF

2

VREF

197

VDDSPD

199

VDDID

201

GND

SKT-SODIMM200-6U

C

121

/CS0

122

/CS1

96

CKE0

95

CKE1

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8

CK0

/CK0

CK1

/CK1

CK2

/CK2

SCL SDA

SA0 SA1 SA2

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

REVERSE TYPE 9.2MM

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

GND

11 25 47 61 133 147 169 183 77

12 26 48 62 134 148 170 184 78

35 37 160 158 89 91

195 193

194 196 198

9 10 21 22 33 34 36 45 46 57 58 69 70 81 82 92 93 94 113 114 131 132 143 144 155 156 157 167 168 179 180 191 192

3 4 15 16 27 28 38 39 40 51 52 63 64 75 76 87 88 90 103 104 125 126 137 138 149 150 159 161 162 173 174 185 186

202

M_DQS_R0 M_DQS_R1 M_DQS_R2 M_DQS_R3 M_DQS_R4 M_DQS_R5 M_DQS_R6 M_DQS_R7

M_ADM_R0 M_ADM_R1 M_ADM_R2 M_ADM_R3 M_ADM_R4M_ADM_R4 M_ADM_R5 M_ADM_R6 M_ADM_R7

DDR_CLK1

DDR_CLK#1

62.10017.391

2D5V_S3

D

M_CS#2 5,9 M_CS#3 5,9

M_ADM#0 M_ADM#1 M_ADM#2 M_ADM#3 M_ADM#4 M_ADM#5 M_ADM#6 M_ADM#7

M_CLK4 5,9 M_CLK#4 5,9 M_CLK6 5,9 M_CLK#6 5,9

SMBC_SB 3,21,57 SMBD_SB 3,21,57

1 2

D

?NEED CHANGE LIBRARY

R563

3D3V_S0

4K7R2

DDR_CLK#1 DDR_CLK#0 DDR_CLK1 DDR_CLK0

MD63

DDR1(Reverse 5.2mm)

DDR2(Reverse 9.2mm)

Title

Size Document Number Rev

A3

Date: Sheet

E

M_ADM_R[7..0] 9 M_DATA_R_[63..0] 9 M_DQS_R[7..0] 9

M_AA[13..0] 5,9 M_ABS#[1..0] 5,9 M_BA[13..0] 5,9 M_BBS#[1..0] 5,9

2D5V_S3

RN92

SRN10K-2

DY

1 2 3 45

8 7 6

AMD CPU

SMA10

SMA11

Pin 199

Pin 200 Pin 2

Pin 199 Pin 1

Pin 200 Pin 2

(Bottom view)

DDR SO-DIMM SKT

Bolsena

SMA14

SMA0 SMA12

Pin 1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

E

MD0

858Tuesday, December 28, 2004

SA

of

A

SERIES DAMPING PARALLEL TERMINATION

PLACE RNs CLOSE TO FIRST DIMM, < 0.75" STRICT EQUAL LENGTH LIMITATION WITH DQS, CB PINS

M_DATA4 M_ADM0

M_DATA6 M_DATA7 M_DATA13 M_DATA12

4 4

M_ADM1

M_DATA1 M_DATA0 M_DQS0 M_DATA2 M_DATA3 M_DATA8 M_DATA9 M_DQS1

M_DATA14 M_DATA_R_14 M_DATA15 M_DATA21 M_DATA20 M_ADM2 M_DATA23 M_DATA_R_23 M_DATA22 M_DATA25 M_DATA_R_25

3 3

M_DATA11 M_DATA10 M_DATA17 M_DATA16 M_DQS2 M_DQS_R2 M_DATA19 M_DATA_R_19 M_DATA18 M_DATA24

M_DATA29 M_DATA28

M_ADM3 M_DATA26 M_DATA27 M_DATA30 M_DATA_R_30 M_DATA31

2 2

SRN10J-3

8 9 7 6 5 4 3 2 1

RN13 SRN10J-3

8 9 7 6 5 4 3 2 1

RN18 SRN10J-3

8 9 7 6 5 4 3 2 1

RN24 SRN10J-3

8 9 7 6 5 4 3 2 1

RN29 SRN10J-3

8 9 7 6 5 4 3 2 1

RN34

10 11 12 13 14 15 16

M_DATA_R_4 M_DATA_R_5M_DATA5 M_ADM_R0 M_DATA_R_6 M_DATA_R_7 M_DATA_R_13 M_DATA_R_12 M_ADM_R1

M_DATA_R_1 M_DATA_R_0 M_DQS_R0 M_DATA_R_2 M_DATA_R_3 M_DATA_R_8 M_DATA_R_9 M_DQS_R1

M_DATA_R_15 M_DATA_R_21 M_DATA_R_20 M_ADM_R2

M_DATA_R_22

M_DATA_R_11 M_DATA_R_10 M_DATA_R_17 M_DATA_R_16

M_DATA_R_18 M_DATA_R_24

M_DATA_R_29 M_DATA_R_28 M_DQS_R3M_DQS3 M_ADM_R3 M_DATA_R_26 M_DATA_R_27

M_DATA_R_31

M_DATA32 M_DATA33 M_DATA_R_33 M_DATA_R_33 M_DATA36 M_DATA_R_36

M_DQS4 M_DQS_R4 M_ADM4 M_ADM_R4 M_DATA34 M_DATA39

M_DATA35 M_DATA41 M_DATA40 M_DQS5 M_DATA42 M_DATA43 M_DATA49 M_DATA48

M_DATA38 M_DATA45 M_DATA44 M_ADM5 M_DATA47 M_DATA46 M_DATA53 M_DATA52

M_DQS6 M_DATA50 M_DATA51 M_DATA56 M_DATA57 M_DQS7 M_DATA58 M_DATA59

M_ADM6 M_DATA54 M_DATA55 M_DATA61 M_DATA60 M_ADM7 M_DATA62 M_DATA63

8 9 7 6 5 4 3 2 1

SRN10J-3

RN14 SRN10J-3

RN19 SRN10J-3

RN25 SRN10J-3

RN30 SRN10J-3

RN35

B

M_DATA_R_32 M_DATA_R_32

10 11

M_DATA_R_37M_DATA37 M_DATA_R_37

12 13 14

M_DATA_R_34

15

M_DATA_R_39

16

M_DATA_R_35 M_DATA_R_41

10

M_DATA_R_40

11

M_DQS_R5

12

M_DATA_R_42

13

M_DATA_R_43

14

M_DATA_R_49

15

M_DATA_R_48

16

M_DATA_R_38 M_DATA_R_45

10

M_DATA_R_44

11

M_ADM_R5

12

M_DATA_R_47

13

M_DATA_R_46

14

M_DATA_R_53

15

M_DATA_R_52

16

M_DQS_R6 M_DATA_R_50

10

M_DATA_R_51

11

M_DATA_R_56

12

M_DATA_R_57

13

M_DQS_R7

14

M_DATA_R_58

15

M_DATA_R_59

16

M_ADM_R6 M_DATA_R_54

10

M_DATA_R_55

11

M_DATA_R_61

12

M_DATA_R_60

13

M_ADM_R7

14

M_DATA_R_62

15

M_DATA_R_63

16

M_ADM_R1 M_DATA_R_13 M_DATA_R_12 M_DATA_R_7 M_DATA_R_6 M_ADM_R0 M_DATA_R_5 M_DATA_R_4

M_DATA_R_1 M_DATA_R_0 M_DQS_R0 M_DATA_R_2 M_DATA_R_3 M_DATA_R_8 M_DATA_R_9 M_DQS_R1

M_DATA_R_25

M_DATA_R_23

M_DATA_R_22 M_ADM_R2 M_DATA_R_21 M_DATA_R_20 M_DATA_R_15 M_DATA_R_14

M_DATA_R_11 M_DATA_R_10 M_DATA_R_16 M_DATA_R_17 M_DQS_R2 M_DATA_R_19 M_DATA_R_18 M_DATA_R_24

M_DATA_R_31 M_DATA_R_30 M_DATA_R_26 M_DATA_R_27 M_ADM_R3 M_DQS_R3 M_DATA_R_29 M_DATA_R_28

SRN68J-1

8 9 7 6 5 4 3 2 1

RN15 SRN68J-1

8 9 7 6 5 4 3 2 1

RN20 SRN68J-1

8 9 7 6 5 4 3 2 1

RN26 SRN68J-1

8 9 7 6 5 4 3 2 1

RN31 SRN68J-1

8 9 7 6 5 4 3 2 1

RN36

C

1D25V_S3 1D25V_S3

10 11 12 13 14 15 16

SRN68J-1

8 9 7 6 5 4 3 2 1

RN16 SRN68J-1

8 9 7 6 5 4 3 2 1

RN21 SRN68J-1

8 9 7 6 5 4 3 2 1

RN27 SRN68J-1

8 9 7 6 5 4 3 2 1

RN32 SRN68J-1

8 9 7 6 5 4 3 2 1

RN37

10 11 12 13 14 15 16

D

PULL HIGH STUBS < 0.8", PLACE RPs CLOSE TO SECOND DM ( DM2 ) NO EQUAL LENGTH LIMITATION

M_DATA_R_36 M_ADM_R4

M_DQS_R4 M_DATA_R_38 M_DATA_R_39

M_DATA_R_48 M_DATA_R_49 M_DATA_R_43 M_DATA_R_42 M_DQS_R5 M_DATA_R_41 M_DATA_R_40 M_DATA_R_34

M_DATA_R_35 M_DATA_R_44 M_DATA_R_45 M_ADM_R5 M_DATA_R_46

M_DATA_R_47 M_DATA_R_52 M_DATA_R_53

M_DATA_R_59 M_DATA_R_58 M_DQS_R7 M_DATA_R_57 M_DATA_R_56 M_DATA_R_51 M_DATA_R_50 M_DQS_R6

M_ADM_R6 M_DATA_R_54 M_DATA_R_55 M_DATA_R_60 M_DATA_R_61 M_ADM_R7 M_DATA_R_62 M_DATA_R_63

M_CKE#0 M_CKE#1

M_BA12 M_AA12

M_AA11 M_AA9 M_AA7 M_AA5 M_AA4 M_AA8 M_AA6 M_AA3

M_CS#3 M_BCAS# M_BRAS# M_BBS#1 M_CS#2 M_BA13 M_BA0 M_BA2

M_AA1 M_AA10 M_AA2 M_AA0 M_ABS#1 M_ARAS# M_AWE# M_ABS#0

M_BA7 M_BA3 M_BA6 M_BA9 M_BA10 M_BA1 M_BBS#0 M_BWE#

M_BA4 M_BA8 M_BA11 M_BA5

M_AA13 M_CS#0 M_ACAS# M_CS#1

SRN47J

1 4 2

RN17 SRN47J

1 4 2

RN22 SRN47J-1-U

8 9 7 6 5 4 3 2 1

RN23 SRN47J-1-U

8 9 7 6 5 4 3 2 1

RN28 SRN47J-1-U

8 9 7 6 5 4 3 2 1

RN33 SRN47J-1-U

8 9 7 6 5 4 3 2 1

RN38

SRN47-1

4 5 3 2 1

RN39

SRN47-1

4 5 3 2 1

RN40

E

M_ADM_R[7..0] 8

3

10 11 12 13 14 15 16

6 7 8

M_ADM[7..0] 5 M_DATA[63..0] 5 M_DATA_R_[63..0] 8 M_DQS[7..0] 5 M_DQS_R[7..0] 8

M_AA[13..0] 5,8

M_ABS#[1..0] 5,8

M_BA[13..0] 5,8

M_BBS#[1..0] 5,8

M_AWE# 5,8

M_ACAS# 5,8

M_ARAS# 5,8

M_BWE# 5,8

M_BCAS# 5,8

M_BRAS# 5,8

M_CS#0 5,8

M_CS#1 5,8

M_CS#2 5,8

M_CS#3 5,8

M_CKE#05,8

M_CKE#15,8

05/10 Remove the damping resistor for AMD suggest.

1 1

M_CKE#0 M_CKE#1

R60

1 2

121R3F

R61

1 2

121R3F

R62

1 2

121R3F

R63

1 2

121R3F

A

B

M_CLK7 M_CLK#7

M_CLK6 M_CLK#6

M_CLK5 M_CLK#5

M_CLK4 M_CLK#4

C

M_CLK7 5,8 M_CLK#7 5,8

M_CLK6 5,8 M_CLK#6 5,8

M_CLK5 5,8 M_CLK#5 5,8

M_CLK4 5,8 M_CLK#4 5,8

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

D

Date: Sheet

DDR DAMPING & TERMINATION

Bolsena

958Tuesday, December 28, 2004

E

of

SA

Place it near CPU

A

B

C

D

E

4 4

2D5V_S3

1D25V_S3

12

C80 SCD1U

C81 SCD1U

12

C82 SCD1U

DY

12

C97 SCD1U

C98 SCD1U

12

C99 SCD1U

DY

3 3

2D5V_S3

1D25V_S3

12

C114 SCD1U

12

C122 SCD1U

C123 SCD1U

DY

12

C138 SCD1U

C139 SCD1U

C140 SCD1U

12

DY

2 2

LAYOUT:Place altemating caps to GND and 2D5_S3

12

C83 SCD1U

DY

12

C100 SCD1U

DY

12

C124 SCD1U

DY

12

C141 SCD1U

DY

12

C84 SCD1U

C85 SCD1U

12

C86 SCD1U

12

C87 SCD1U

C88 SCD1U

DY

12

C101

C102

SCD1U

C103 SCD1U

12

C104

C105

SCD1U

DY

C125 SCD1U

C126 SCD1U

C127 SCD1U

12

C128 SCD1U

C129 SCD1U

DY

12

C142

C143

SCD1U

12

C144 SCD1U

C145 SCD1U

12

C146 SCD1U

DY

12

C89 SCD1U

DY

12

C106 SCD1U

DY

12

C130 SCD1U

DY

12

C147 SCD1U

DY

12

C90 SCD1U

C91 SCD1U

C92 SCD1U

12

C93 SCD1U

DY

12

C107

C108

SCD1U

C109 SCD1U

12

C110 SCD1U

DY

12

C131

C132

SCD1U

12

C133 SCD1U

C134 SCD1U

DY

12

C148

C149

SCD1U

12

C150 SCD1U

C151 SCD1U

DY

12

C94 SCD1U

C95 SCD1U

12

C96 SCD1U

DY

12

C111 SCD1U

C112 SCD1U

12

C113 SCD1U

DY

12

C135 SCD1U

C136 SCD1U

C137 SCD1U

12

DY

12

C153 SCD1U

C154 SCD1U

C152 SCD1U

1D25V_S3

12

DY

C115 SCD1U

12

C116 SCD1U

DY

C117 SCD1U

12

C118 SCD1U

DY

C119 SCD1U

12

C120

C121

SCD1U

DY

LAYOUT:Place close to Power Pin of DDR socket.

LAYOUT:Place at end of the DIMMs

1D25V_S3

12

TC2 ST100U4VBM-U

12

TC3 ST100U4VBM-1

12

C157 SC22U10V6ZY-U

12

C158 SC22U10V6ZY-U

12

C159 SC22U10V6ZY-U

12

C160 SC22U10V6ZY-U

2D5V_S3 2D5V_S3

C155

1 2

SCD22U16V3ZY C161

1 2

SCD22U16V3ZY C163

1 2

DY

SCD22U16V3ZY C165

1 2

DY

SCD22U16V3ZY C167

1 2

SCD22U16V3ZY

1 2

DY

1 2

DY

1 2

C156 SCD22U16V3ZY

C162 SCD22U16V3ZY

C164 SCD22U16V3ZY

C166 SCD22U16V3ZY

C168 SCD22U16V3ZY

0.22u x 10

1 1

A

B

C

D

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

DDR DECOUPLING

Bolsena

E

10 58Tuesday, December 28, 2004

SA

A

4 4

B

C

D

E

CLAW HAMMER TO NB NB TO CLAW HAMMER

CPUCADOUT[15..0]4 CPUCADOUTJ[15..0]4

3 3

1D2V_S0

12

2 2

AROUND NB

C169 SCD1U16V

DY

12

C170 SCD1U16V

CPUHTTCLKOUT14 CPUHTTCLKOUTJ14

CPUHTTCLKOUT04 CPUHTTCLKOUTJ04

CPUHTTCTLOUT04 CPUHTTCTLOUTJ04

1D2V_HT0A_S0

1 2 1 2

CPUCADOUT15 CPUCADOUTJ15 CPUCADOUT14 CPUCADOUTJ14 CPUCADOUT13 CPUCADOUTJ13 CPUCADOUT12 CPUCADOUTJ12 CPUCADOUT11 CPUCADOUTJ11 CPUCADOUT10 CPUCADOUTJ10 CPUCADOUT9 CPUCADOUTJ9 CPUCADOUT8 CPUCADOUTJ8

CPUCADOUT7 CPUCADOUTJ7 CPUCADOUT6 CPUCADOUTJ6 CPUCADOUT5 CPUCADOUTJ5 CPUCADOUT4 CPUCADOUTJ4 CPUCADOUT3 CPUCADOUTJ3 CPUCADOUT2 CPUCADOUTJ2 CPUCADOUT1 CPUCADOUTJ1 CPUCADOUT0 CPUCADOUTJ0

CPUHTTCLKOUT1 CPUHTTCLKOUTJ1

CPUHTTCLKOUT0 CPUHTTCLKOUTJ0

CPUHTTCTLOUT0 CPUHTTCTLOUTJ0

R64 49D9R2F

R65 49D9R2F

HT_RXCALN HT_RXCALP

W25

W24 AA25 AA24 AB26 AA26 AC25 AC24 AD26 AC26

W30

AB29 AA29 AC29 AC28

W26

W29

W28

T26 R26 U25 U24 V26 U26

R29 R28 T30 R30 T28 T29 V29 U29 Y30

Y28 Y29

Y26

P29 N29

D27 E27

U4A

HT_RXCAD15P HT_RXCAD15N HT_RXCAD14P HT_RXCAD14N HT_RXCAD13P HT_RXCAD13N HT_RXCAD12P HT_RXCAD12N HT_RXCAD11P HT_RXCAD11N HT_RXCAD10P HT_RXCAD10N HT_RXCAD9P HT_RXCAD9N HT_RXCAD8P HT_RXCAD8N

HT_RXCAD7P HT_RXCAD7N HT_RXCAD6P HT_RXCAD6N HT_RXCAD5P HT_RXCAD5N HT_RXCAD4P HT_RXCAD4N HT_RXCAD3P HT_RXCAD3N HT_RXCAD2P HT_RXCAD2N HT_RXCAD1P HT_RXCAD1N HT_RXCAD0P HT_RXCAD0N

HT_RXCLK1P HT_RXCLK1N

HT_RXCLK0P HT_RXCLK0N

HT_RXCTLP HT_RXCTLN

HT_RXCALN HT_RXCALP

RS480M-U

PART 1OF6

HYPER TRANSPORT CPU I/F

HT_TXCAD15P HT_TXCAD15N HT_TXCAD14P HT_TXCAD14N HT_TXCAD13P HT_TXCAD13N HT_TXCAD12P HT_TXCAD12N HT_TXCAD11P HT_TXCAD11N HT_TXCAD10P HT_TXCAD10N

HT_TXCAD9P HT_TXCAD9N HT_TXCAD8P HT_TXCAD8N

HT_TXCAD7P HT_TXCAD7N HT_TXCAD6P HT_TXCAD6N HT_TXCAD5P HT_TXCAD5N HT_TXCAD4P HT_TXCAD4N HT_TXCAD3P HT_TXCAD3N HT_TXCAD2P HT_TXCAD2N HT_TXCAD1P HT_TXCAD1N HT_TXCAD0P HT_TXCAD0N

HT_TXCLK1P HT_TXCLK1N

HT_TXCLK0P HT_TXCLK0N

HT_TXCTLP HT_TXCTLN

HT_TXCALP

HT_TXCALN

R24 R25 N26 P26 N24 N25 L26 M26 J26 K26 J24 J25 G26 H26 G24 G25

L30 M30 L28 L29 J29 K29 H30 H29 E29 E28 D30 E30 D28 D29 B29 C29

L24 L25

F29 G29

M29 M28

B28 A28

NB0CADOUT15 NB0CADOUTJ15 NB0CADOUT14 NB0CADOUTJ14 NB0CADOUT13 NB0CADOUTJ13 NB0CADOUT12 NB0CADOUTJ12 NB0CADOUT11 NB0CADOUTJ11 NB0CADOUT10 NB0CADOUTJ10 NB0CADOUT9 NB0CADOUTJ9 NB0CADOUT8 NB0CADOUTJ8

NB0CADOUT7 NB0CADOUTJ7 NB0CADOUT6 NB0CADOUTJ6 NB0CADOUT5 NB0CADOUTJ5 NB0CADOUT4 NB0CADOUTJ4 NB0CADOUT3 NB0CADOUTJ3 NB0CADOUT2 NB0CADOUTJ2 NB0CADOUT1 NB0CADOUTJ1 NB0CADOUT0 NB0CADOUTJ0

NB0HTTCLKOUT1 NB0HTTCLKOUTJ1

NB0HTTCLKOUT0 NB0HTTCLKOUTJ0

NB0HTTCTLOUT NB0HTTCTLOUTJ

HT_TXCALP HT_TXCALN

1 2

NB0CADOUT[15..0] 4 NB0CADOUTJ[15..0] 4

NB0HTTCLKOUT1 4 NB0HTTCLKOUTJ 1 4

NB0HTTCLKOUT0 4 NB0HTTCLKOUTJ 0 4

NB0HTTCTLOUT 4 NB0HTTCTLOUTJ 4

R66 100R2F

1 1

A

B

C

D

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

ATI-RS480M (1 of 4) HT

Bolsena

11 58Tuesday, December 28, 2004

E

of

SA

A

B

C

D

E

PEG_TXP[15..0]49 PEG_TXN[15..0]49

PEG_RXP[15..0]49 PEG_RXN[15..0]49

D8 D7 D5 D4 E4 F4 G5 G4 H4

H5 H6 G1 G2 K5 K4

M4

N5 N4 P4 R4 P5 P6 P2 R2 T5 T4 U4

V4 W1 W2

AE1 AE2

AB2 AC2

AB5 AB4

Y4

AA4

AG1 AH1

AC5 AC6

AH3

AJ3

DVO_MDA5215 DVO_MDA4915 DVO_MDA5015 DVO_MDA5115 DVO_MDA3915 DVO_MDA4815 DVO_MDA3815 DVO_MDA3715 DVO_MDA3615 DVO_MDA3515 DVO_MDA3415 DVO_MDA3315

DVO_MDA5315 DVO_MDA5415

DVO_MDA5515

U4B

GFX_RX0P GFX_RX0N GFX_RX1P GFX_RX1N GFX_RX2P GFX_RX2N GFX_RX3P GFX_RX3N GFX_RX4P

J4

GFX_RX4N GFX_RX5P GFX_RX5N GFX_RX6P GFX_RX6N GFX_RX7P GFX_RX7N

L4

GFX_RX8P GFX_RX8N GFX_RX9P GFX_RX9N GFX_RX10P GFX_RX10N GFX_RX11P GFX_RX11N GFX_RX12P GFX_RX12N GFX_RX13P GFX_RX13N GFX_RX14P GFX_RX14N GFX_RX15P GFX_RX15N

GPP_RX0P/SB_RX2P GPP_RX0N/SB_RX2N

GPP_RX1P/SB_RX3P GPP_RX1N/SB_RX3N

GPP_RX2P GPP_RX2N

GPP_RX3P GPP_RX3N

SB_RX0P SB_RX0N

SB_RX1P SB_RX1N

PCE_ISET PCE_TXISET

RS480M-U

PART 2 OF 6

GPP_TX0P/SB_TX2P GPP_TX0N/SB_TX2N

GPP_TX1P/SB_TX3P GPP_TX1N/SB_TX3N

PCIE I/F TO VIDEO

PCIE I/F TO SLOT

PCIE I/F TO SB

DVO_MDA52 DVO_MDA49 DVO_MDA50 DVO_MDA51 DVO_MDA39 DVO_MDA48 DVO_MDA38 DVO_MDA37 DVO_MDA36 DVO_MDA35 DVO_MDA34 DVO_MDA33

DVO_MDA53 DVO_MDA54

DVO_MDA55

GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N GFX_TX8P GFX_TX8N GFX_TX9P

GFX_TX9N GFX_TX10P GFX_TX10N GFX_TX11P GFX_TX11N GFX_TX12P GFX_TX12N GFX_TX13P GFX_TX13N GFX_TX14P GFX_TX14N GFX_TX15P GFX_TX15N

GPP_TX2P

GPP_TX2N

GPP_TX3P

GPP_TX3N

SB_TX0P SB_TX0N

SB_TX1P SB_TX1N

PCE_PCAL

PCE_NCAL

A7 B7 B6 B5 A5 A4 B3 B2 C1 D1 D2 E2 F2 F1 H2 J2 J1 K1 K2 L2 M2 M1 N1 N2 R1 T1 T2 U2 V2 V1 Y2 AA2

AD2 AD1

AA1 AB1

Y5 Y6

W5 W4

AF2 AG2

AC4 AD4

AH2 AJ2

4 4

3 3

1D8V_S0

12

R67 1KR2F

MEM_VREF

R68 1KR2F

IDCKP15

IDCKN15

Connect MEM_VREF to VDD_MEM/2 PA_RS480F1.PDF

1D8V_S0

12

C213 SC1U10V3KX

MEM_CAP1 MEM_CAP2

MEM_VREF MPVDD_PLL

C212

2 2

1D8V_S0

1 2 1 2

DY DY

1 2

SCD47U16V3ZY

C211 SCD47U16V3ZY

L5 0R5J-1

AF17 AK17 AH16

AF16

AJ22

AJ21 AH20 AH21 AK19 AH19

AJ17 AG16 AG17 AH17

AJ18 AG26

AJ29 AE21 AH24 AH12 AG13

AH8 AE8

AF25 AH30 AG20

AJ25 AH13

AF14

AG8

AG25 AH29

AF21 AK25

AJ12

AF13

AK7 AF9

AE17 AH18 AE18

AJ19

AF18 AK16

AJ16

AE28

AJ20

AK20

AJ15

AJ14

AJ7

AJ4

U4C

MEM_A0 MEM_A1 MEM_A2 MEM_A3 MEM_A4 MEM_A5 MEM_A6 MEM_A7 MEM_A8 MEM_A9 MEM_A10 MEM_A11 MEM_A12 MEM_A13 MEM_A14

MEM_DM0 MEM_DM1 MEM_DM2 MEM_DM3 MEM_DM4 MEM_DM5 MEM_DM6 MEM_DM7

MEM_DQS0P MEM_DQS1P MEM_DQS2P MEM_DQS3P MEM_DQS4P MEM_DQS5P MEM_DQS6P MEM_DQS7P

MEM_DQS0N MEM_DQS1N MEM_DQS2N MEM_DQS3N MEM_DQS4N MEM_DQS5N MEM_DQS6N MEM_DQS7N

MEM_RAS# MEM_CAS# MEM_WE# MEM_CS# MEM_CKE

MEM_CKP MEM_CKN

MEM_CAP1 MEM_CAP2

MEM_VMODE

MEM_VREF MPVDD

MPVSS

RS480M-U

PART 3 OF 6

MEM_A I/F

MEM_DQ0 MEM_DQ1 MEM_DQ2 MEM_DQ3 MEM_DQ4 MEM_DQ5 MEM_DQ6 MEM_DQ7 MEM_DQ8

MEM_DQ9 MEM_DQ10 MEM_DQ11 MEM_DQ12 MEM_DQ13 MEM_DQ14 MEM_DQ15 MEM_DQ16 MEM_DQ17 MEM_DQ18 MEM_DQ19 MEM_DQ20 MEM_DQ21 MEM_DQ22 MEM_DQ23 MEM_DQ24 MEM_DQ25 MEM_DQ26 MEM_DQ27 MEM_DQ28 MEM_DQ29 MEM_DQ30 MEM_DQ31 MEM_DQ32 MEM_DQ33 MEM_DQ34 MEM_DQ35 MEM_DQ36 MEM_DQ37 MEM_DQ38 MEM_DQ39 MEM_DQ40 MEM_DQ41 MEM_DQ42 MEM_DQ43 MEM_DQ44 MEM_DQ45 MEM_DQ46 MEM_DQ47 MEM_DQ48 MEM_DQ49 MEM_DQ50 MEM_DQ51 MEM_DQ52 MEM_DQ53 MEM_DQ54 MEM_DQ55 MEM_DQ56 MEM_DQ57 MEM_DQ58 MEM_DQ59 MEM_DQ60 MEM_DQ61 MEM_DQ62 MEM_DQ63

MEM_COMPP MEM_COMPN

AF28 AF27 AG28 AF26 AE25 AE24 AF24 AG23 AE29 AF29 AG30 AG29 AH28 AJ28 AH27 AJ27 AE23 AG22 AF23 AF22 AE20 AG19 AF20 AF19 AH26 AJ26 AK26 AH25 AJ24 AH23 AJ23 AH22 AK14 AH14 AK13 AJ13 AJ11 AH11 AJ10 AH10 AE15 AF15 AG14 AE14 AE12 AF12 AG11 AE11 AJ9 AH9 AJ8 AK8 AH7 AJ6 AH6 AJ5 AG10 AF11 AF10 AE9 AG7 AF8 AF7 AE7

AH5 AD30

LANE REVERSE

DVO_MDA33 DVO_MDA34 DVO_MDA35 DVO_MDA36 DVO_MDA37 DVO_MDA38 DVO_MDA39

DVO_MDA48 DVO_MDA49 DVO_MDA50 DVO_MDA51 DVO_MDA52 DVO_MDA53 DVO_MDA54 DVO_MDA55

MEM_COMPP MEM_COMPN

DY DY

DO NOT SUPPORT SIDEPORT MEMORY DUMMY IT

1 2 1 2

PCIE_RX0P_SB18 PCIE_RX0N_SB18

PCIE_RX1P_SB18 PCIE_RX1N_SB18

1 2 1 2

R74 60D4R2F

R75 60D4R2F

PEG_TXP15 PEG_TXN15 PEG_TXP14 PEG_TXN14 PEG_TXP13 PEG_TXN13 PEG_TXP12 PEG_TXN12 PEG_TXP11 PEG_TXN11 PEG_TXP10 PEG_TXN10 PEG_TXP9 PEG_TXN9 PEG_TXP8 PEG_TXN8 PEG_TXP7 PEG_TXN7 PEG_TXP6 PEG_TXN6 PEG_TXP5 PEG_TXN5 PEG_TXP4 PEG_TXN4 PEG_TXP3 PEG_TXN3 PEG_TXP2 PEG_TXN2 PEG_TXP1 PEG_TXN1 PEG_TXP0 PEG_TXN0

PCIE_RXP057

PCIE_RXN057

PCIE_RXP157

PCIE_RXN157

R69 10KR2

R70 10KR2

2D5V_S3

PCE_ISET PCE_TXISET

When disable local frame buffer, VDD_MEM connect to 2D5V_S3,

1 1

MEM_VMODE connect to GND, MEM_VREF connect to 2D5V_S3, MPVDD connected to 1D8V

?CHECK THESE PINS

DSG-215-RS480-04.PDF

A

B

C

?PLACE THESE CAP CLOSE TO CONNECTOR

PEG_RXP15_NB PEG_RXP15 PEG_RXP14_NB PEG_RXP13_NB

PEG_RXN13_NB PEG_RXP12_NB PEG_RXN12_NB PEG_RXP11_NB PEG_RXN11_NB PEG_RXP10_NB PEG_RXN10_NB PEG_RXP9_NB PEG_RXN9_NB PEG_RXP8_NB PEG_RXN8_NB PEG_RXP7_NB PEG_RXN7_NB PEG_RXP6_NB PEG_RXN6_NB PEG_RXP5_NB PEG_RXN5_NB PEG_RXP4_NB PEG_RXN4_NB PEG_RXP3_NB PEG_RXN3_NB PEG_RXP2_NB PEG_RXN2_NB PEG_RXP1_NB PEG_RXN1_NB PEG_RXP0_NB PEG_RXN0_NB

PCIE_TXP0_NB PCIE_TXN0_NB

PCIE_TXP1_NB PCIE_TXN1_NB

?NEED STRAP FOR MULTI PIN?

D

SB_TX0P SB_TX0N

SB_TX1P SB_TX1N

PCE_PCAL PCE_NCAL

1 2 1 2

Title

Size Document Number Rev

Date: Sheet

C171

1 2

SCD1U16V

C173

1 2

SCD1U16V

C172

1 2

SCD1U16V

C174

1 2

SCD1U16V

C176

1 2

SCD1U16V

C175

1 2

SCD1U16V

C177

1 2

SCD1U16V

C179

1 2

SCD1U16V

C178

1 2

SCD1U16V

C180

1 2

SCD1U16V

C181

1 2

SCD1U16V

C182

1 2

SCD1U16V

C183

1 2

SCD1U16V

C184

1 2

SCD1U16V

C185

1 2

SCD1U16V

C187

1 2

SCD1U16V

C186

1 2

SCD1U16V

C188

1 2

SCD1U16V

C189

1 2

SCD1U16V

C191

1 2

SCD1U16V

C190

1 2

SCD1U16V

C192

1 2

SCD1U16V

C194

1 2

SCD1U16V

C193

1 2

SCD1U16V

C195

1 2

SCD1U16V

C197

1 2

SCD1U16V

C196

1 2

SCD1U16V

C198

1 2

SCD1U16V

C200

1 2

SCD1U16V

C199

1 2

SCD1U16V

C202

1 2

SCD1U16V

C201

1 2

SCD1U16V

C203

1 2

SCD1U16V

C204

1 2

SCD1U16V C205

1 2

SCD1U16V

C206

1 2

SCD1U16V

Dummy when no EZ4

C207 SCD1U16V

C208 SCD1U16V C209 SCD1U16V

C210 SCD1U16V

R71 150R2

R72 100R2

ATI-RS480M (2 of 4) PCIE

A3

PEG_RXN15PEG_RXN15_NB PEG_RXP14 PEG_RXN14PEG_RXN14_NB PEG_RXP13 PEG_RXN13 PEG_RXP12 PEG_RXN12 PEG_RXP11 PEG_RXN11 PEG_RXP10 PEG_RXN10 PEG_RXP9 PEG_RXN9 PEG_RXP8 PEG_RXN8 PEG_RXP7 PEG_RXN7 PEG_RXP6 PEG_RXN6 PEG_RXP5 PEG_RXN5 PEG_RXP4 PEG_RXN4 PEG_RXP3 PEG_RXN3 PEG_RXP2 PEG_RXN2 PEG_RXP1 PEG_RXN1 PEG_RXP0 PEG_RXN0

Dummy when use UMA

PCIE_TXP0 57 PCIE_TXN0 57

PCIE_TXP1 57 PCIE_TXN1 57

PCIE_TX0P_SB 18 PCIE_TX0N_SB 18

PCIE_TX1P_SB 18 PCIE_TX1N_SB 18

1D2V_S0

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Bolsena

12 58Tuesday, December 28, 2004

E

LANE REVERSE

SA

of

A

1D8V_S0

1 2

4 4

3 3

1D8V_S0

2 2

AVDDQ

R76 0R3-U

12

C214

DY

R93

1 2

BLM11A121S

12

R96 4K7R2

NB_SUS_STAT#

12

SC10U10V5ZY

C215

SCD1U16V

1D8V_S0

HTPVDD

12

C225 SC10U10V5ZY

UMA_CRMA57

UMA_LUMA57

UMA_COMP57

UMA_R57 UMA_G57 UMA_B57

R88

1 2

BLM11A121S

12

C227 SCD1U16V

12

C228 SCD1U16V

1 2

1D8V_S0

R287

R285

R288

150R2F

1 2

Dummy when use Discrete

PLVDD

12

C218 SC10U10V5ZY

3D3V_S01D8V_S0

R101 0R2-0

C219

C221

SCD1U16V

12

C231 SC1U10V3ZY

3D3VDDR_S0

R95

1 2

0R3-U

DO NOT SUPPORT SIDEPORT MEMORY DO NOT SUPPORT SERIAL STRAP ROM DUMMY IT

DY

3D3V_S5

U5A

ALL_PWROK39

LDT_RST#

1 1

LPC_RST#18,37

A

147

1 2

3

TSLCX08MTC-U

R112

1 2

33R2

AG_RST# 34,49

RS480_RST#

1 2

R292

150R2F

1 2

B

AVDD3D3V_S0

R77

1 2

0R3-U

12

C216 SC1U10V3ZY

C220 SC1U10V3ZY

LDT_STP#6,18 ALLOW_LDTSTOP18

RN102

SRN10KJ

LVDS_DIGON

1D8VAVDDD1_S0

14 2

R78

0R3-U

12

C217 SC1U10V3ZY

AVDDQ

R294

R293

CLK14_NB3 SB_OSC_INT21

VGA_SMB_CLK15,49,54 VGA_SMB_DAT49,54

NB_PWRGD

C233 DUMMY-C3

12

DY DY DY

3

LVDS_BLON

150R2F

UMA_CRT_DDC_C16 UMA_CRT_DDC_D16

Use CLK GEN REF 14.318M CLK to SB OSCIN DUMMY IT

3D3V_S0

12

B

NB_PWRGD39

1 2

R828

12

3KR2F

R578

12

3KR2F

R577

12

3KR2F

BMREQ#18

DY

R90 715R3F

12

R97 22R2

TP50 TPAD28

4 5

R113 1KR2

3D3V_S5

UMA_VS16 UMA_HS16

RS480_RST#

NB_SUS_STAT#

NB_OSC_OUT

DFT_GPIO0 DFT_GPIO2

147

3D3V_S5

12 13

C

IRSET_NB

1 2

U5B

6

TSLCX08MTC-U

147

C

B27 C27 D26 D25 C24

B24

E24 D24

B25

A25

A24 C25

A26

B26

A11

B11 C26

E11

F11

A14

B14 M23

L23

D14

B15

B12 C12 AH4

H13 H12

A13

B13

B9

F12

E13 D13

F10 C10 C11 AF4 AE4

R106 0R2-0

DY

U5D

11

TSLCX08MTC-U

U4D

AVDD1 AVDD2 AVSSN1 AVSSN2 AVDDDI AVSSDI

AVDDQ AVSSQ

C Y COMP

RED GREEN BLUE

DAC_VSYNC DAC_HSYNC RSET DAC_SCL DAC_SDA

PLLVDD PLLVSS

HTPVDD HTPVSS

SYSRESET# POWERGOOD LDTSTOP# ALLOW_LDTSTOP SUS_STAT#

VDDR3_1 VDDR3_2

OSCIN OSCOUT

TVCLKIN

DFT_GPIO0/RSV DFT_GPIO1/RSV DFT_GPIO2/RSV

BMREQb I2C_CLK I2C_DATA THERMALDIODE_P THERMALDIODE_N

RS480M-U

LCDVDD_ON

R114

1 2

PART 4 OF 6

CRT/TVOUT

PLL PWR

PM

CLOCKs

MIS.

0R2-0

UMA

TXOUT_U0P TXOUT_U0N TXOUT_U1P TXOUT_U1N TXOUT_U2P TXOUT_U2N TXOUT_U3P TXOUT_U3N

TXOUT_L0P TXOUT_L0N TXOUT_L1P TXOUT_L1N TXOUT_L2P TXOUT_L2N TXOUT_L3P TXOUT_L3N

TXCLK_UP TXCLK_UN

TXCLK_LP

LVDS

TXCLK_LN

LVDDR18D LVDDR18A_1 LVDDR18A_2

LVSSR1 LVSSR2 LVSSR3 LVSSR4 LVSSR5 LVSSR6 LVSSR7 LVSSR8

LVDS_DIGON

LVDS_BLON LVDS_BLEN

GFX_CLKP

GFX_CLKN

HTTSTCLK

HTREFCLK

SB_CLKP SB_CLKN

DFT_GPIO3/RSV DFT_GPIO4/RSV DFT_GPIO5/RSV

TMDS_HPD

STRP_DATA

DDC_DATA TESTMODE

VCC_CORE_S0

BL_ON 34,49

RESISTOR

R503 R504

LPVDD

LPVSS

DY

12

D

D18 C18 B19 A19 D19 C19

TXBOUT3+

D20

TXBOUT3-

C20 B16

A16 D16 C16 B17 A17

TXAOUT3+

E17

TXAOUT3-

D17 B20

A20 B18 C17

E18 F17 E19 G20 H20

G19 E20 F20 H18 G18 F19 H19 F18

E14 F14 F13

B8 A8

HTTST_CLK

P23 N23

E8 E7

C13 C14 C15

A10 E10

DDC_DATA

B10

TESTMODE_NB

E12

R107 DUMMY-R2

R110 4K7R2

RS480M MODE

TEST MODE

NORMAL MODE

D

TXBOUT0+ TXBOUT0TXBOUT1+ TXBOUT1TXBOUT2+ TXBOUT2-

TXAOUT0+ TXAOUT0TXAOUT1+ TXAOUT1TXAOUT2+ TXAOUT2-

TXBCLK+ TXBCLKTXACLK+ TXACLK-

LVDS_DIGON LVDS_BLON LVDS_BLEN_NB

DFT_GPIO3 DFT_GPIO4DFT_GPIO1 DFT_GPIO5

TP45 TPAD30

TP46 TPAD30

1 2

DDC_DATA 15

E

TXACLK+ TXACLKTXAOUT2+ TXAOUT2-

TXAOUT1+ TXAOUT1TXAOUT0+ TXAOUT0-

TXBOUT1+ TXBOUT1TXBOUT0+ TXBOUT0-

TXBCLK+ TXBCLKTXBOUT2+ TXBOUT2-

LCDVDD_ON

6 7 8

RN120

RN121

RN122

RN123

R818

12

0R2-0

45 3 2 1

SRN0-1-U

45 3 2 1

SRN0-1-U

45 3 2 1

SRN0-1-U

45 3 2 1

SRN0-1-U

LCD_TXACLK+ 17,54

LCD_TXACLK- 17,54

LCD_TXAOUT2+ 17,54

LCD_TXAOUT2- 17,54

LCD_TXAOUT1+ 17,54

LCD_TXAOUT1- 17,54

LCD_TXAOUT0+ 17,54

LCD_TXAOUT0- 17,54

LCD_TXBOUT1+ 17,54

LCD_TXBOUT1- 17,54

LCD_TXBOUT0+ 17,54

LCD_TXBOUT0- 17,54

LCD_TXBCLK+ 17,54

LCD_TXBCLK- 17,54

LCD_TXBOUT2+ 17,54

LCD_TXBOUT2- 17,54

LCD_VDD_ON 17,54

Dummy when use Discrete

TP47 TPAD30

TP48 TPAD30

1D8VLPVDD_S0

LVDDR18D_S0

LVDDR18A_S0

TP49 TPAD30

NBSRC_CLK 3 NBSRC_CLK# 3

R98 10KR2

HTREF_CLK 3 SBLINK_CLK 3

SBLINK_CLK# 3

DY DY DY

TMDS_UMA_HPD 15

TP52 TPAD28

R825

12

3KR2F R826

12

3KR2F R827

12

3KR2F

Title

Size Document Number Rev

Date: Sheet

ATI-RS480M (3 of 4) LVDS CRT

A3

12

C222 SC1U10V3ZY

12

C224 SC1U10V3ZY

12

C229 SC1U10V3ZY

DISABLE DEBUG MODE DUMMY IT

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Bolsena

12

C230 SCD1U16V

E

C223 SCD1U16V

C226 SCD1U16V

13 58Tuesday, December 28, 2004

1 2

of

1D8V_S0

R87 BLM11A121S

R92 BLM11A121S

R94 BLM11A121S

SA

A

B

C

D

E

VSS89

H17

H10

H16

H14

E16

D10

E15

F15

U15

V14

R15

T14

N15

V12

N13

P14

U17

T16

R17

P12

T12

R13

W13

W17

P18

V18

M18

U13

N17

W15

V16

T18

M14

M12

M16

P16

U19

AC16

AG18

AC23

AD8

AD11

AD13

AD16

AD19

AD23

AG5

AG6

AG21

AD17

AG15

AG12

AF30

AG24

AG9

AC19

AG27

AC11

AD7

AJ30

AC21

AK5

AK10

AC13

AD21

AK22

AK29

W19

AE26

AE27

T27

R27

AD28

F24

F27

G28

U4F

4 4

VSS108

VSS109

VSS110

VSS111

VSS112

VSS104

VSS105

VSS106

VSS107

VSS98

VSS99

VSS100

VSS101

VSS102

VSS103

VSS92

VSS93

VSS94

VSS95

VSS96

VSS97

VSS86

VSS87

VSS88

VSS89

VSS90

VSS91

VSS79

VSS80

VSS81

VSS82

VSS83

VSS84

VSS85

VSS73

VSS74

VSS75

VSS76

VSS77

VSS78

VSS67

VSS68

VSS69

VSS70

VSS71

VSS72

VSS60

VSS61

VSS62

VSS63

VSS64

VSS65

VSS66

VSS54

VSS55

VSS56

VSS57

VSS58

VSS59

VSS48

VSS49

VSS50

VSS51

VSS52

VSS53

VSS44

VSS45

VSS46

VSS47

VSS37

VSS38

VSS39

VSS40

VSS41

VSS42

VSS43

VSS30

D15

AD9

G11

F16

G30

AB28

AB25

D12

AD24

AA28

G17

Y23

AC9

R19

Y27

C28

G16

F25

B30

T24

F26

W27

D11

H11

AD25

VSS15

VSS16

VSS17

VSS18

VSS19

VSS20

VSS21

VSS22

VSS23

VSS24

VSS25

VSS26

VSS27

VSS28

VSS29

VSS30

VSS31

VSS32

VSS33

VSS34

VSS35

VSS36

Y24

G13

VSS8

VSS9

VSS10E9VSS11

VSS12D9VSS13

VSS14

G14

G15

VSS7

AC27

VSS6

AD27

VSS5

AD29

VSS4

G12

VSS3

G10

VSS2

VSS1

RS480M-U

PAR 6 OF 6

GROUND

VSSA1

VSSA2

VSSA3

VSSA4N3VSSA5F7VSSA6F5VSSA7R3VSSA8

VSSA22A2VSSA23

VSSA24P8VSSA25J6VSSA26C8VSSA27

VSSA28V8VSSA29F3VSSA30

VSSA31

VSSA32M5VSSA33

VSSA34G3VSSA35B4VSSA36P7VSSA37

VSSA38C9VSSA39C7VSSA40J5VSSA41R6VSSA42J3VSSA43

VSSA44D6VSSA45C4VSSA46K3VSSA47

VSSA48T7VSSA49Y7VSSA50

12

VSSA51K7VSSA52H7VSSA53M3VSSA54V6VSSA55H8VSSA56C2VSSA57

AD6

C240 SCD1U16V

C247 SCD1U16V

12

C273 SCD1U16V

DY

12

C287 SCD1U16V

AB8

12

C256 SCD1U16V

12

C264 SCD1U16V

C274 SCD1U16V

C288 SCD1U16V

AD5

12

L6

1 2

MLB-201209-11

12

C275 SCD1U16V

DY

12

C289 SCD1U16V

AA5

C257 SC22U10V6ZY-U

1D8V_S0

12

D

AB7

1D2V_S0

C276 SCD1U16V

AF3

AE3

AA3

AB3

AD3

VSSA22

Title

Size Document Number Rev

Date: Sheet of

ATI-RS480M (4 of 4) PWR, GND

A3

VSSA58L6VSSA59

12

C238 SCD1U16V

12

C263 SCD1U16V

12

C270 SC22U10V6ZY-U

12

C277 SC22U10V6ZY-U

DY

VSSA60M7VSSA61V7VSSA62F6VSSA63E6VSSA64U5VSSA65U6VSSA66E5VSSA67L5VSSA68

VSSA59

12

AJ1

12

AG3

C239 SCD1U16V

C246 SCD1U16V

C272 SCD1U16V

C286 SCD1U16V

VSS113

VSS114

VSS115

VSS116

VSS117

VSS118

VSS119

VSS120

VSS122

VSS123

VSS124

VSS125

VSS126

VSS127

VSS128

VSS129

VSS130

VSS131

VSS132

F28

T8

12

C255 SC1U10V3KX

1D8V_VDDA

12

C262 SC1U10V3KX

1D2V_S0

C

N28

H24

M27

H9 AA7 G9 U8 N7 N8 U7 F9 AA8 G8 G7 J8 J7 B1 AG4 R8 AC8 AC7 AF6 AE6 L8 W8 W7 L7 R7 AF5 AK2 N16 M13 M15 W16 N18 P19 N12 P15 N14 M17 T19 G22 R12 P13 R14 V19 R18 U16 U12 T13 U14 T17 U18 E22 R16 V13 T15 P17 W18 D22 W12 V15 W14 V17 M19 H22 H21 D21

K28

N19

VDDA12_13

VDDA18_13

M24

H28

P25

P28

E26

K25

V25

V28

U28

R23

1D2V_S0

12

C236 SCD1U16V

12

C244 SCD1U16V

12

C250 SCD1U16V

12

C283 SCD1U16V

1D8VDD_S0

12

C290 SCD1U16V

12

R119 0R5J-1

12

C237 SCD1U16V

12

C245 SCD1U16V

12

C251 SCD1U16V

12

C284 SCD1U16V

12

C291

C292

SCD1U16V

1D8V_S0

12

C293 SC1U10V3KX

1D2V_HT0A_S0

C271

SCD1U16V

C285 SCD1U16V

1D2V_S0

VDDHT30 VDDHT31

B

N27 U27 V27 G27 V24 H27 K24

AB24

P27

AA27

K27

P24 AB27 AB23

V23

G23

E23

W23

K23

H23

U23 AA23

D23

C23

B23

A23

A29 AC30

AK23 AK28 AK11

AK4 AE30 AC14 AD12 AC18 AC20 AD10 AD14 AD15 AD20 AC10 AD18 AC12 AD22 AC22 AH15

H15 AC17 AC15

B21

C21

A22

B22

C22

E21

G21

J27

J23

F23

F21 F22

U4E

RS480M-U

VDD_HT1 VDD_HT2 VDD_HT3 VDD_HT4 VDD_HT5 VDD_HT6 VDD_HT7 VDD_HT8 VDD_HT9 VDD_HT10 VDD_HT11 VDD_HT12 VDD_HT13 VDD_HT14 VDD_HT15 VDD_HT16 VDD_HT17 VDD_HT18 VDD_HT19 VDD_HT20 VDD_HT21 VDD_HT22 VDD_HT23 VDD_HT24 VDD_HT25 VDD_HT26 VDD_HT27 VDD_HT28 VDD_HT29 VDD_HT30 VDD_HT31

VDD_MEM1 VDD_MEM2 VDD_MEM3 VDD_MEM4 VDD_MEM5 VDD_MEM6 VDD_MEM7 VDD_MEM8 VDD_MEM9 VDD_MEM10 VDD_MEM11 VDD_MEM12 VDD_MEM13 VDD_MEM14 VDD_MEM15 VDD_MEM16 VDD_MEM17 VDD_MEM18 VDD_MEMCK

VDD_18_1 VDD_18_2 VDD_18_3

VDD_CORE47 VDD_CORE46 VDD_CORE45 VDD_CORE44 VDD_CORE43 VDD_CORE42 VDD_CORE41 VDD_CORE40 VDD_CORE39

PART 5 OF 6

VDDA_12_14

VDDA_12_1 VDDA_12_2 VDDA_12_3 VDDA_12_4 VDDA_12_5 VDDA_12_6 VDDA_12_7 VDDA_12_8

VDDA_12_9 VDDA_12_10 VDDA_12_11 VDDA_12_12 VDDA_12_13

VDDA_18_1

VDDA_18_2

VDDA_18_3

VDDA_18_4

VDDA_18_5

VDDA_18_6

VDDA_18_7

VDDA_18_8

VDDA_18_9 VDDA_18_10 VDDA_18_11 VDDA_18_12 VDDA_18_13 VDD_CORE1 VDD_CORE2 VDD_CORE3 VDD_CORE4 VDD_CORE5 VDD_CORE6 VDD_CORE7 VDD_CORE8 VDD_CORE9

VDD_CORE10 VDD_CORE11 VDD_CORE12 VDD_CORE13 VDD_CORE14 VDD_CORE15 VDD_CORE16 VDD_CORE17 VDD_CORE18 VDD_CORE19 VDD_CORE20 VDD_CORE21 VDD_CORE22 VDD_CORE23 VDD_CORE24 VDD_CORE25 VDD_CORE26 VDD_CORE27 VDD_CORE28 VDD_CORE29 VDD_CORE30 VDD_CORE31 VDD_CORE32 VDD_CORE33 VDD_CORE34 VDD_CORE35

POWER

VDD_CORE36 VDD_CORE37 VDD_CORE38

12

R117

12

C235 SCD1U16V

0R5J-1

C252 SCD1U16V

3 3

12

C234 SC22U10V6ZY-U

DY

12

C242 SCD1U16V

C243 SCD1U16V

12

C241 SCD1U16V

12

C253 SCD1U16V

DY

12

C260 SCD1U16V

R118 0R5J-1

C254 SCD1U16V

C261 SCD1U16V

DY

2 2

1 1

3D3V_S0

12

C248 SC22U10V6ZY-U

12

C278 SCD1U16V

1D8V_S0

1 2

U7 BAV99-1

DY

12

3

C249 SCD1U16V

C279 SCD1U16V

1 2

12

C266 SCD1U16V

12

C280 SCD1U16V

DY

L7 BLM11A121S

1 2

DY

3

U8 BAV99-1

A

12

C267 SCD1U16V

12

C281 SCD1U16V

12

R120 0R2-0

DY

C268 SCD1U16V

C282 SCD1U16V

DY

12

R121 0R2-0

J28

L27

T23

VSSA9T3VSSA10M6VSSA11C5VSSA12F8VSSA13M8VSSA14Y8VSSA15V3VSSA16C3VSSA17W3VSSA18K8VSSA19D3VSSA20C6VSSA21

V5

R5

VDDA12_13

VSSA22

VDDA18_13

VSSA59

VDDHT30

VSS30

VDDHT31

VSS89

E

AE5

14 58Tuesday, December 28, 2004

12

C258 SC4D7U10V5ZY

12

C259 SC4D7U10V5ZY

12

C265 SC4D7U10V5ZY

12

C269 SC4D7U10V5ZY

AA6

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Bolsena

SA

A

B

C

D

E

3D3V_S0

2

14

RN93

4 4

To Discrete

RN91

SRN0-2-U

2 1

DIS_DVI_DDC_D49

DIS_DVI_DDC_C49

3 4

SRN10KJ

3

5 6

34 2 1

U24 2N7002DW

5V_S0

2

14

RN94

SRN10KJ

3

!DEL DVI_VCC

To EZ4 (5V level)

EZ4_DVI_DDC_D 57

EZ4_DVI_DDC_C 57

Dummy when use UMA

3D3V_S0

12

C296 SC2200P50V2KX

12

C305 SC10U10V5ZY

12

C306 SC10U10V5ZY

1 2

C297 SCD1U10V2MX

1 2

C303 SCD1U10V2MX

1 2

C307 SCD1U10V2MX

1 2

To UMA

DDC_DATA13

VGA_SMB_CLK13,49,54

3 3

2 2

3 4

RN41

SRN0-2-U

DY

2 1

3D3V_S0

R128

1 2

BLM11A121S

1 2

R130 BLM11A121S

R133 BLM11A121S

R126 BLM11A121S

12

C298 SC10U10V5ZY

12

C304 SC2200P50V2KX

12

C308 SC2200P50V2KX

EXT_SWING_1

12

C300

C299

SC2200P50V2KX

SCD1U10V2MX

1 2

3D3V_SII1162_VCC_S0

3D3V_SII1162_PVCC1_S0 3D3V_SII1162_PVCC2_S0

DVO_MDA5212 DVO_MDA4912 DVO_MDA5012 DVO_MDA5112 DVO_MDA3912 DVO_MDA4812 DVO_MDA3812 DVO_MDA3712 DVO_MDA3612 DVO_MDA3512 DVO_MDA3412 DVO_MDA3312

IDCKN12 IDCKP12

DVO_MDA5312

3D3V_S0

DVO_MDA5412 DVO_MDA5512

DVO_MDA52 DVO_MDA49 DVO_MDA50 DVO_MDA51 DVO_MDA39 DVO_MDA48 DVO_MDA38 DVO_MDA37 DVO_MDA36 DVO_MDA35 DVO_MDA34 DVO_MDA33

DVO_MDA53

1 2

DVO_MDA54 DVO_MDA55

R134 5K1R2

1 2

DY

1 2

TMDS_EZ4_TX0- 49,57

TMDS_EZ4_TX0+ 49,57

TMDS_EZ4_TX1- 49,57

TMDS_EZ4_TX1+ 49,57

TMDS_EZ4_TX2- 49,57 TMDS_EZ4_TX2+ 49,57 TMDS_EZ4_TXC- 49,57

TMDS_EZ4_TXC+ 49,57

U9

34

AVCC AVCC

VCC VCC

PVCC1 PVCC2

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11

IDCKIDCK+

DE CTL3/A2

HSYNC VSYNC

EDGE/HTPLG

ISEL/RST#

SDA/DK0 SCL/DK1

MSEN

PD#

VREF

EXT_SWING

TX0-

TX0+

TX1-

TX1+

TX2TX2+ TXC-

TXC+

PGND PGND

GND GND GND GND

AGND AGND AGND

40 22

3

28 46

18 17 16 15 14 13 10

9 8 7 6 5

11 12

19 24

20 21

TMDS_UMA_HPD

44 25

DDC_DATA

26

VGA_SMB_CLK

27 48

47 2

EXT_SWING EXT_SWING_1

30

TMDS_UMA_TX0-

35

TMDS_UMA_TX0+

36

TMDS_UMA_TX1-

38

TMDS_UMA_TX1+

39 41 42 32 33

29 45

4 1 23 49

43 37 31

R131

1 2

5K1R2

R132

1 2

510R3

TMDS_UMA_TX2TMDS_UMA_TX2+ TMDS_UMA_TXCTMDS_UMA_TXC+

PCIRST_BUF# 18,26,2 8,29,31,34,57

2D5V_S3

RN100

1

8

2

7

3

6

4 5

RN101 SRN0-1-U

1

8

2

7

3

6

4 5

SRN0-1-U

DY

1 2

2D5V_S3

R127 1KR2

R129 1KR2

C301 SCD1U10V2MX

SII1162CS48

To Discrete

DVI_HPD49

TMDS_UMA_HPD13

To UMA & SiI1162

1 1

A

B

DY

R135

1 2

0R2-0

Dummy when use UMA

R137

1 2

0R2-0

Dummy when use Discrete

C

TMDS_HPD

C523 SCD1U10V2MX

1 2

R136

1 2

8K2R2

R139 8K2R2

1 2

Title

Size Document Number Rev

D

Date: Sheet of

Dummy when use Discrete

DVI_EZ4_HPD 57

Dummy when no EZ4

UMA DVI - SiI 1162

A3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Bolsena

15 58Tuesday, December 28, 2004

E

SA

A

CRT CONN

200mA Rating/Spec 500mA

5V_S0

4 4

DY DY

HSYNC_5_1

14

4

5 6

7

2 3

U10B

TSAHCT125

R144

UMA_HS13 UMA_VS13

1 2

R149

1 2

0R2-0 0R2-0

VSYNC_5_1

Dummy when use Discrete

R153 0R2-0

DIS_HS49 DIS_VS49

1 2

R158 0R2-0

1 2

U10A

14

1

HSYNC_5

TSAHCT125

7

VSYNC_5

Dummy when use UMA

B

To SYS and EZ4 CRT Both

SYS_HS

SYS_VS

1 2 1 2

Dummy when no EZ4

12

C309

C310

DUMMY-C2

1 2

R146 33R2

R150 33R2

R154 0R2-0 R155 0R2-0

UMA_CRT_DDC_D13

UMA_CRT_DDC_C13

EZ4_HS 57

EZ4_VS 57

C

RN98

3 4

Dummy when use Discrete

DIS_CRT_DDC_D49

DIS_CRT_DDC_C49

SRN0-2-U

2

14

RN96

SRN10KJ

3

DY

CRT_DDC_D_1

2

CRT_DDC_C_1

1

RN97

SRN0-2-U

2 1

3 4

Dummy when use UMA

D

3D3V_S0

5V_S0

To SYS and EZ4 CRT Both

2

14

RN95 U25 2N7002DW

34 5 6

2

1

SRN10KJ

3

?ddc channel EZ4,CRT same TIME?

SYS_CRT_DDC_D5 SYS_CRT_DDC_C5

RN99

SRN0-2-U

2 1

3 4

E

EZ4_CRT_DDC_D 57 EZ4_CRT_DDC_C 57

Dummy when no EZ4

3 3

2 2

TV_LUMA_SYS57

TV_COMP_SYS57

1 1

TV_CRMA_SYS57

CRT_R_SYS57

CRT_G_SYS57

CRT_B_SYS57

R296

R298

R295

150R2F

1 2

DY

1 2

12

C323 SC100P50V2JN

1 2

12

C325 SC100P50V2JN

1 2

12

C328

R443

R299

R467

150R2F

1 2

A

SC100P50V2JN

12

C312 SC47P50V2JN

L11 IND-1D2UH

L12 IND-1D2UH

L13 IND-1D2UH

12

DY

C322 SC47P50V2JN

TV_LUMA_CON

12

C330 SC47P50V2JN

TV_COMP_CON

12

C327 SC47P50V2JN

TV_CRMA_CON

12

B

C313 SC47P50V2JN

DY

C324 SC270P50V

C326 SC270P50V

C329 SC270P50V

1 2

12

C314 SC47P50V2JN

L8 BLM18BB750SN1D

L9 BLM18BB750SN1D

L10 BLM18BB750SN1D

D8

2

3

DY

1

BAV99-2

D9

2

3

DY

1

BAV99-2

D10

2

3

DY

1

BAV99-2

12

C315 SC2P50V

3D3V_S0

12

C316 SC2P50V

C

12

C317 SC2P50V

D5

1

BAV99-2

CRT_R

12

C318 SC100P50V2JN

SYS_CRT_DDC_D5

SYS_CRT_DDC_C5

12

C319

C320

SC100P50V2JN

SC10P50V2JN-1

12

C321 SC10P50V2JN-1

5V_S0

12

CRT_R

CRT_G CRT_B

C311 SCD01U50V2ZY

CRT_G

D7

1

BAV99-2

SYS_HS

SYS_VS

3

2

5V_S0

CRT_B

3

2

D6

1

BAV99-2

3

2

CRT1

6 1

7 2 8 3 9 4

10

5

VIDEO-15-42

20.20378.015

17

11

12 13 14 15 16

SYS_CRT_DDC_D5 SYS_HS SYS_VS SYS_CRT_DDC_C5

TV CONN

TV1

TV_LUMA_CON

TV_COMP_CON

TV_CRMA_CON

8 4

1 5 2 7 3 6

9

MINDIN7-9

22.10021.B31

D

456

123

7

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

CRT / TV Bolsena

16 58Tuesday, December 28, 2004

E

SA

A

B

C

D

E

NUM_LED#34 CAP_LED#34 MAIL_LED#34 BLT_LED#34 WLAN_LED#34

STDBY_LED#34

CHARGE_LED#34

4 4

NUM_LED# CAP_LED#

MAIL_LED#

Dummy when use IDE

DY

R138

SATA_LED#19

HDD_LED#_525

Dummy when use SATA

CDROM_LED#_525

3 3

3D3V_S0

1 2

3

1

2

0R2-0 R140

0R2-0

Q7 PDTC144EU

2

1

D11

BAW56

PWRLED#

MEDIA_LED#

3

MEDIA_LED#

WLAN_LED# STDBY_LED#

PWRLED# CHARGE_LED#

BLT_LED#

1 2 3 4 5

RC15

RC16

1 2

LEDs

SRC100P50V-U

8 7 6

SRC100P50V-U

8 7 6

C714 SC100P50V2JN

NUM_LED#

CAP_LED#

MAIL_LED#

MEDIA_LED#

WLAN_LED#

BLT_LED#

STDBY_LED#

PWRLED#

CHARGE_LED#

1 2

on KB cover

LED ButtonVV

POWER E-MAIL INTERNE T e-BTN PROGRAM

V VVVV

R566 330R2

R567 330R2

R568 330R2

R572 330R2

R573 330R2

R565 330R2

R569 330R2

R570 330R2

R571 330R2

D_NUM1

1 2

D_CAPS1 LED-G-31

1 2

D_MAIL1

1 2

D_MEDIA1

1 2

D_WLAN1 LED-Y-22

1 2

D_BTH1

1 2

D_STDBY1 L ED-Y-22

1 2

D_PWR1 LED-G-31

1 2

D_CHGR1 LED-Y-22

1 2

CAPS NUM HDD

3D3V_S0

LED-G-31

LED-B-13-U

3D3V_S5

VVV

Front panel

LED Button

V

VV

V

BlutTooth WirelessCharger Power

2 2

LCD POWERLCD CONN

139

1 2

Layout 40 mil

R160 1KR2

12

LCDVDD_ON_1

12

C346

C347

SC1U10V3KX

SCD1U

U11

1

OUT

2

GND ON/OFF#3IN

AAT4280IGU-3-T1

D

3D3V_S0LCDPOWER_S0

6

IN

5

GND

4

Title

Size Document Number Rev

Date: Sheet of

12

C348 SC1U10V3KX

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

INV / LCD / LEDs

A3

Bolsena

E

17 58Tuesday, December 28, 2004

SA

12

LCD CONN

2

C344 SCD1U

DY

12

C345 SCD1U

40

LCD_VDD_ON13,54

EVEN CHANNEL

ODD CHANNEL

LCDPOWER_S0

12

LCD1

41

MH1

1

2

3

PANEL_ID037 PANEL_ID137 PANEL_ID237 PANEL_ID337

R888

FPBACK34

BRIGHTNESS34

1 1

1 2

C716

1 2

SC100P50V2JN

10KR2

C715

1 2

SC100P50V2JN

?add net?

MH2

11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

42

5 7 9

ETY-CONN40D-1

4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

DY

C343 SC10U10V5ZY

LCD_TXBCLK+ 13,54 LCD_TXBCLK- 13,54 LCD_TXBOUT2+ 13,54 LCD_TXBOUT2- 13,54 LCD_TXBOUT1+ 13,54 LCD_TXBOUT1- 13,54 LCD_TXBOUT0+ 13,54 LCD_TXBOUT0- 13,54 LCD_TXACLK+ 13,54 LCD_TXACLK- 13,54 LCD_TXAOUT2+ 13,54 LCD_TXAOUT2- 13,54 LCD_TXAOUT1+ 13,54 LCD_TXAOUT1- 13,54 LCD_TXAOUT0+ 13,54 LCD_TXAOUT0- 13,54

20.F0322.040

A

B

C

A

3D3V_S0

PCI_REQ#5 PCI_GNT#5

1 2

DY

NB_EEPROM_WP

R161 1KR2

C349 SCD1U16V

DY

4 4

1D8V_S0

3 3

1D8V_S0 PCIE_VDDR

1 2

C367 SC12P50V2JN-1

2 3

C354 SC22P50V2JN-1

L14 MLB-201209-11

12

L15 0R3-U

12

41

X2 XTAL-32D768K-4P

12

C359 SC10U10V5ZY

12

C361 SC22U10V6ZY-U

DY

2 2

A_RST#

1 2

U15

A B GND3Y

NC7SZ32-U

5 6 7 8

12

R170

R169

20MR3

PCIE_PVDD

12

C360 SC1U10V3KX

12

C362 SCD1U16V

INT_PIRQA# INT_PIRQB#

INT_PIRQH#

3D3V_S0

5

VCC

4

U12

4

SDA SCL WP VCC

AT24C04N-10SI

DY

32K_X1 32K_X2

GND

3

A2

2

A1

1

A0

SBSRC_CLK3 SBSRC_CLK#3

PCIE_RX0P_SB12 PCIE_RX0N_SB12 PCIE_RX1P_SB12 PCIE_RX1N_SB12

PCIE_TX0P_SB12 PCIE_TX0N_SB12 PCIE_TX1P_SB12 PCIE_TX1N_SB12

MAIN SOURCE: 82.30001.031 EPSON 2ND SOURCE: 82.30001.341 KDS

PCIE_VDDR

C371 SCD1U16V

12

C363 SCD1U16V

5V_S0

RSTDRV#_R

12

C364 SCD1U16V

DY

RP1

1 2 3 4 5 6

SRP10K

C372 SCD1U16V

1 2

R179 33R2

12

10 9 8 7

C373 SCD1U16V

DY

INT_PIRQG# INT_PIRQD#INT_PIRQC# INT_PIRQE# INT_PIRQF#

PCIRST# 3V to 5V level shift for HDD & CDROM

3D3V_S0

147

A_RST#

1 1

12

R184 8K2R2

PCIRST#

1 2

4 5

3D3V_S0

147

U16B

6

TSLCX08-U

A

SB400 asserts PLTRST# to reset devices on the platform.

U16A

3

PLT_RST#_R

TSLCX08-U

PCI_RST#

1 2

R181 33R2

R186 33R2

LPC_RST# 13,37

PCIRST_BUF# 15,26, 28,29,31,34,57

Secondary PCI Bus reset signal.

ALLOW_LDTSTOP13 SB_CPUPWRGD6

BMREQ#13 LDT_RST#6

B

1 2 1 2

1 2

A11, A12 4K53 1% A21, A22 5K5 1% A23 4K12 1% PA_IXP400AC10.PDF

12

C374 SCD1U16V

DY

3D3V_S0

INT_PIRQE#26 INT_PIRQF#26,31 INT_PIRQG#26 INT_PIRQH#29

RSTDRV#_5 25

B

12

TP55 TP56

LDT_STP#6,13

1 2 1 2 1 2 1 2

R177 150R2F

R173 150R2F R178 4K12R2F

12

C365 SCD1U16V

A_RST#

C368 SCD1U10V2MX

C350 SCD1U10V2MX

C351 SCD1U10V2MX

C352 SCD1U10V2MX

PCIE_PVDD

C366 SCD1U16V

TP65 TPAD30

TP66 TP67

TPAD30 TPAD30

TP69 TPAD30

TP68 TPAD30 TP70 TPAD30

TP71 TPAD30

TP72 TPAD30

TP73 TPAD30

12

PCIE_CALRP PCIE_CALRN

PCIE_CALI

SB_CPUSTP#

SB_PCISTP# INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#

INT_PIRQE#

INT_PIRQF#

INT_PIRQG#

INT_PIRQH#

SB_C29 SB_A28 H_NMI FWH_INIT# SB_D29

SB_B30

H_A20M# H_FERR#

H_DPRSLP#

R162 8K2R2

TX0P TX0N TX1P TX1N

32K_X1

32K_X2

U14A

AH8

A_RST#

L27

PCIE_RCLKP

M27

PCIE_RCLKN

M30

PCIE_TX0P

N30

PCIE_TX0N

K30

PCIE_TX1P

L30

PCIE_TX1N

H30

PCIE_TX2P

J30

PCIE_TX2N

F30

PCIE_TX3P

G30

PCIE_TX3N

M29

PCIE_RX0P

N29

PCIE_RX0N

M28

PCIE_RX1P

N28

PCIE_RX1N

J29

PCIE_RX2P

K29

PCIE_RX2N

J28

PCIE_RX3P

K28

PCIE_RX3N

G27

PCIE_CALRP

H27

PCIE_CALRN

G28

PCIE_CALI

R30

PCIE_PVDD

F26

PCIE_VDDR_1

R29

PCIE_VDDR_2

G26

PCIE_VDDR_3

P26

PCIE_VDDR_4

K26

PCIE_VDDR_5

L26

PCIE_VDDR_6

P28

PCIE_VDDR_7

N26

PCIE_VDDR_8

P27

PCIE_VDDR_9

H28

PCIE_VSS_1

F29

PCIE_VSS_2

H29

PCIE_VSS_3

H26

PCIE_VSS_4

F27

PCIE_VSS_5

G29

PCIE_VSS_6

L29

PCIE_VSS_7

J26

PCIE_VSS_8

L28

PCIE_VSS_9

J27

PCIE_VSS_10

N27

PCIE_VSS_11

M26

PCIE_VSS_12

K27

PCIE_VSS_13

P29

PCIE_VSS_14

P30

PCIE_VSS_15

AJ8

CPU_STP#/DPSLP#

AK7

PCI_STP#

AG5

INTA#

AH5

INTB#

AJ5

INTC#

AH6

INTD#

AJ6

INTE#/GPIO33

AK6

INTF#/GPIO34

AG7

INTG#/GPIO35

AH7

INTH#/GPIO36

B2

X1

B1

X2

C29

CPU_PG

A28

INTR/LINT0

C28

NMI/LINT1

B29

INIT#

D29

SMI#

E4

SLP#/LDT_STP#

B30

IGNNE#

F28

A20M#

E28

FERR#

E29

STPCLK#/ALLOW_LDTSTP

D25

LDT_PG/SSMUXSEL/GPIO0

E27

DPRSLPVR

D27

BMREQ#

D28

LDT_RST#

CHS-215SB400

C

SB400 SB

Part 1 of 4

PCI EXPRESS INTERFACE

PCI INTERFACE

REQ4#/PLL_BP33/PDMA_REQ1#

GNT3#/PLL_BP66/PDMA_GNT0# GNT4#/PLL_BP50/PDMA_GNT1#

LPC

CPU XTAL

RTC_IRQ#/ACPWR_STRAP

RTC

C

PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5 PCICLK6 PCICLK7 PCICLK8 PCICLK9

PCICLK_FB

PCI CLKS

PCIRST# AD0/ROMA18 AD1/ROMA17 AD2/ROMA16 AD3/ROMA15 AD4/ROMA14 AD5/ROMA13 AD6/ROMA12 AD7/ROMA11

AD8/ROMA9

AD9/ROMA8 AD10/ROMA7 AD11/ROMA6 AD12/ROMA5 AD13/ROMA4 AD14/ROMA3 AD15/ROMA2 AD16/ROMD0 AD17/ROMD1 AD18/ROMD2 AD19/ROMD3 AD20/ROMD4 AD21/ROMD5 AD22/ROMD6 AD23/ROMD7

AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

CBE0#/ROMA10

CBE1#/ROMA1

CBE2#/ROMWE#

CBE3#

FRAME#

DEVSEL#/ROMA0

IRDY#

TRDY#/ROMOE#

PAR/ROMA19

STOP# PERR# SERR#

REQ0#

REQ1#

REQ3#/PDMA_REQ0#

REQ2#

REQ5#/GPIO13 REQ6#/GPIO31

GNT0#

GNT1#

GNT2#

GNT5#/GPIO14 GNT6#/GPIO32

CLKRUN#

LOCK#

LAD0 LAD1 LAD2 LAD3

LFRAME#

LDRQ0# LDRQ1#

SERIRQ

RTCCLK

VBAT

RTC_GND

L4 L3 L2 L1 M4 M3 M2 M1 N4 N3 N2

AJ7 W3 Y2 W4 Y3 V1 Y4 V2 W2 AA4 V4 AA3 U1 AA2 U2 AA1 U3 T4 AC1 R2 AD4 R3 AD3 R4 AD2 P2 AE3 P3 AE2 P4 AF2 N1 AF1 V3 AB4 AC2 AE4 T3 AC4 AC3 T2 U4 T1 AB2 AB3 AF4 AF3 AG2 AG3 AH1 AH2 AH3 AJ2 AK2 AJ3 AK3 AG4 AH4 AJ4 AG1 AB1

AG25 AH25 AJ25 AH24 AG24 AH26 AG26

AK27

C2 F3

A2 A1

PCI_CLK1_R PCI_CLK2_R PCI_CLK3_R PCI_CLK4_R PCI_CLK5_R PCI_CLK6_R PCI_CLK7_R PCI_CLK8_R PCI_CLK9_R PCI_CLK9_FB

PCIRST# PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31

PCI_REQ#4

PCI_REQ#5 PCI_REQ#6

PCI_GNT#3 PCI_GNT#4 PCI_GNT#5 PCI_GNT#6

PCI_LOCK#

LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3

LPC_LDRQ1#

VBAT

12

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2

PCI_AD[31..0] 22,26,29,31

PCI_REQ#3

TP62 TPAD30

TP61 TPAD30

TP64 TPAD30

TP63 TPAD30

LPC_LAD[0 . .3 ] 34,37

P_SERIRQ 26,34,37,57

3D3V_AUX_S5

RTC_CLK 22 AUTO_ON# 22

C375 SCD1U16V

12

C376 SC1U10V3KX

RTC_AUX_S5

3

D

32K suspend clock output

PM_SLP_S3#21,34,38,39,43,44,57 RTC_CLK22

R171 22R2

678

4 5

CLK33_CBUS CLK33_LAN CLK33_MINI CLK33_KBC CLK33_SIO CLK33_LPCROM

1 2

12

C355 DUMMY-C2

RN43

123

SRN8K2-1

R175 22R2

R176 22R2

R164 22R2

R165 22R2

R166 22R2

R167 22R2

R168 22R2

R172 22R2

3D3V_S0

RN42

123

SRN8K2-1

LPC_LFRAME# 34,37 LPC_LDRQ0# 37

U106 BAT54C-U

1 2

D

E

5V_S5

U13A

147

PCI_CLK7 22 PCI_CLK8 22

C353 SC100P50V2JN

1 2

3

TSAHCT08-U

CLK33_CBUS CLK33_LAN CLK33_MINI CLK33_KBC CLK33_SIO CLK33_LPCROM

1 2

63.10034.151

R163 10R3

CLK32_G791 23

CLK33_CBUS 26 CLK33_LAN 22,29 CLK33_MINI 22,31 CLK33_KBC 22,34 CLK33_SIO 22,37 CLK33_LPCROM 22

DY

12

C369 DUMMY-C2

678

RN44

123

4 5

SRN8K2-1

PM_CLKRUN# 26,29,31,34,37

RTC_AUX_S5

R156 1KR2

1 2

1

2

3 4

Title

Size Document Number Rev A3

Date: Sheet

ATI-SB400 (1 of 5) PCI, PCIE

12

C356 DUMMY-C2

678

RN45

12

R174 8K2R2

123

SRN8K2-1

?which is gnd

RTC1 MLXCON2

Bolsena SA

12

C358 DUMMY-C2

RN46

1 2 3 4 5

SRN100K

PCI_CBE#0 26,29,31 PCI_CBE#1 26,29,31 PCI_CBE#2 26,29,31 PCI_CBE#3 26,29,31 PCI_FRAME# 26,29,31 PCI_DEVSEL# 26,29,31 PCI_IRDY# 26,29,31 PCI_T R D Y # 26,29,31 PCI_PAR 26,29,31 PCI_STOP# 26 ,29,31 PCI_PERR# 26,29,31 PCI_SERR# 26,29,31

PCI_REQ#0 31 PCI_REQ#1 26 PCI_REQ#2 29

PCI_GNT#0 31 PCI_GNT#1 26 PCI_GNT#2 29

RN47

6 7 8

SRN10K-2

C370 DUMMY-C2

C357 DUMMY-C2

4 5

LPC_LAD0 LPC_LAD3 LPC_LAD1 LPC_LAD2

PCI_GNT#5 PCI_REQ#5 PCI_GNT#6 PCI_REQ#6

Pull up 100k to 3D3V_S0

P_SERIRQ

1 2

LPC_LDRQ1#

1 2

LPC_LDRQ0#

1 2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

18 58Tuesday, December 28, 2004

E

of

8 7 6

DY

3D3V_S0

45 3 2 1

R180 10KR2 R182 10KR2 R183 10KR2

3D3V_S0

Acer Aspire 3020, Aspire 5020 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual