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ASPIRE 3020
Schematics
58 pgs1.33 Mb1
Service Manual
95 pgs3.65 Mb0
User Guide
81 pgs4.19 Mb0
User Manual
82 pgs293.85 Kb0
User Manual [bg]
77 pgs2.75 Mb0
User Manual [cz]
71 pgs1.76 Mb0
User Manual [da]
71 pgs1.49 Mb0
User Manual [de]
78 pgs3.04 Mb0
User Manual [el]
73 pgs1.9 Mb0
User Manual [es]
78 pgs3.74 Mb0
User Manual [fi]
71 pgs1.46 Mb0
User Manual [fr]
75 pgs1.52 Mb0
User Manual [fr]
77 pgs3.67 Mb0
User Manual [hr]
73 pgs1.59 Mb0
User Manual [hu]
74 pgs1.57 Mb0
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77 pgs3.5 Mb0
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70 pgs1.49 Mb0
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Acer Aspire 3020, Aspire 5020 Schematics

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Page 1
5
4
3
2
1
Dummy when use EZ4
Dummy when no EZ4
Dummy when use 10/100
Dummy when use Giga
D D
Dummy when use UMA
Dummy when use Discrete
Dummy when use SATA
Dummy when use IDE
CLK GEN
IDT CV137
LEDs
Bolsena Block Diagram
AMD CPU
3
17
35W/25W
4,5,6,7
DDR 333/400
HyperTransport
PWR SW
TSP2220A
PCMCIA SLOT
Support TypeII
28
1394 4pin Conn
C C
28
PCMCIA I/F
MS/MSpro SDIO/MMC/SD
5 in 1
28
28
Mini-PCI
802.11a/b/g
31
RJ45
30
TXFM
1000Mb
30
TI
PCI 7411
1* Slot Cardbus 1* 1394
26,27
PCI LAN
Realtek
AGTL+ CPU I/F + UMA
PCI Bus / 33MHz
PCI
RTL8110SBL
B B
TXFM
10/100Mb
30
1000/100/10 RTL8100C 100/10
29
ATA 133
6.4GB/S 16b/8b
ATI
RS480M
11,12,13,14
PCI-Express x2
ATI
SB400
ACPI 2.0
18,19,20,21,22
6xUSB 2.0
6-CH AC97 2.2
LPC I/F
PCI Express x16
VRAM x4
HY5DS573222F
USB x 4
AC97
MODEM MDC Card
ATI
M26/M24
50,51,52
53,54
24
RJ11 CONN
91.4C501.001 (04243)
SiI1162
CODEC
ALC655
OP AMP
29
G1421
LPC Bus / 33MHz
200-PIN DDR SODIMM
DDR x2
8,9,10
SVIDEO/COMP
LVDS
RGB CRT
15
TMDS
BlueTooth miniUSB
32
3324
TVOUT
LCD
CRT
DVI-D
(EZ4 only )
Line In MIC In
Line Out
Int. SPKR
24
33
33
33
16
17
16
15
PCB Layer Stackup
L1: Signal 1 L2: GND L3: Signal 2 L4: Signal 3 L5: VCC L6: Signal 4
?modify power block
Battery Charger
INPUTS
AD+ BAT+
SYSTEM DC/DC
INPUT
DCBATOUT
SYSTEM DC/DC
INPUT
DCBATOUT 2D5V_S3
CPU V_CORE
INPUT
DCBATOUT
SYSTEM POWER
OUTPUTS
DCBATOUT
OUTPUT
5V_S5 , 3D3V_S5
OUTPUT
1D8V_S5 1D2V_S0
OUTPUT
VCC_CORE_S0
48
44
45,46
42,43
47
37
Thermal & Fan
G792
23
SATA
25
PIDE
HDD
25
SIDE
DVD/ CD-RW
NS SIO
PC87392
25
FIR
TFDU6102
A A
37
KBC
KB3910
Touch Pad
35 35
Int. KB
XBUS
34
ISA ROM
36
Port Replicator 4 (124 PIN)
AC IN
RJ45-11
SEARIAL PORT
5
CRT
PRINTER
PS2
4
MIC
LINE IN
LINE OUT
TV OUT
DVI PCIeX2 SMBUS
3
2
Title
BLOCK DIAGRAM
Size Document Number Rev
A3
Bolsena
Date: Sheet of
INPUT
2D5V_S3 DCBATOUT
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
OUTPUT
1D25V_S3 5V_AUX_S5
158Tuesday, December 28, 2004
1
SA
Page 2
5
D D
C C
4
3
2
1
B B
A A
5
4
3
2
<Variant Name>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
CHANGE HISTORY
Size Document Number Rev
Bolsena SA
A3
Date: Sheet
258Tuesday, December 28, 2004
1
of
Page 3
A
3D3V_S0
L1
1 2
0R3-U
4 4
3 3
SB_OSC_CLK21
CLK14_AUDIO32
12
12
C1 SCD1U16V
C8 SCD1U16V
12
12
C2 SCD1U16V
C9 SCD1U16V
12
C3 SCD1U16V
12
C10 SCD1U16V
1 2
1 2
CLK48_CARDBUS26 CLK48_USB21 SMBC_SB8,21,57 SMBD_SB8,21,57
R8 33R2
R11 33R2
12
12
1 2
1 2
CLK14_NB13
CLK14_SIO37
C4 SCD1U16V
C11 SCD1U16V
C13 SC33P50V2JN
X1
X-14D318MHZ-1-U1
1 2
C14 SC33P50V2JN
B
12
C5 SC22U10V6ZY-U
3D3V_CLK_VDDA
3D3V_S0 3D3V_CLK_VDD
3D3VDD48_S0
L3
1 2
0R3-U
12
C12 SC2D2U16V5ZY
XI_CLK
XO_CLK
HTREF_CLK13
12
DY
R4
1 2
R5
1 2
R7
1 2
R6
1 2
R2 DUMMY-R3
22R2 22R2 0R2-0 0R2-0
1 2
1 2 1 2
12
R15 49D9R2F
USB_48M SMBC_CLK SMBD_CLK
R9 33R2
R10 33R2 R12 33R2
IREF_CLKGEN
12
FS2 FS1 FS0
CLK_REF2 CLK_HTT66
R16 475R2F
U1
3
VDD_48
39
VDDA
32
VDD_SRC
21
VDD_SRC
14
VDD_SRC
35
VDD_SRC
56
VDD_REF
51
VDD_PC1
43
VDD_CPU
48
VDD_HTT
1
XIN
2
XOUT
4
USB_48
7
SCL
8
SDA
10
CLKREQ0#
11
CLKREQ1#
9
SEL24/24_48#
53
REF1
54
REF0
52
REF2
47
HTT66
50
PCI0
37
IREF
6
NC#6
IDTCV137PAG
C
SRCC0 SRCT0 SRCC3 SRCT3 SRCC4 SRCT4 SRCC5 SRCT5 SRCC6 SRCT6 SRCC7 SRCT7
CPUC1 CPUT1 CPUC0 CPUT0
SRCC1 SRCT1 SRCC2 SRCT2
VSS_SRC VSS_SRC
RESET#
TURBO1
VSS_CPU
VSS_PCI
VSS_HTT
VSS_SRC
VSS_48
VSS_REF
VSSA
33 34 25 24 23 22 19 18 17 16 13 12
40 41 44 45
29 30 28 27
36 20 15 26
42 49 46 31 38 5 55
3D3V_CLK_VDDA3D3V_CLK_VDD
12
C6 SCD1U16V
SRC_CLK0# SRC_CLK0 SRC_CLK3# SRC_CLK3 SRC_CLK4# SRC_CLK4 SRC_CLK5# SRC_CLK5
CPUCLKJ_CY CPUCLK_CY
ATI_CLK0# ATI_CLK0 ATI_CLK1# ATI_CLK1
3D3V_S0
L2
1 2
12
1 2 1 2
RN5
2 3 1
SRN33-2-U2
1 2 3
0R3-U
C7 SC22U10V6ZY-U
RN1
2 3 1
RN2 SRN33-2-U2
1 2 3
SRN33-2-U2 RN3
1 2 3
SRN33-2-U2 RN4
1 2 3
SRN33-2-U2
Dummy when no EZ4
R1 15R2J
R3 15R2J
4
RN6
4
SRN33-2-U2
Dummy when use UMA
D
4 4
4
4
CPUCLK# 6 CPUCLK 6
NBSRC_CLK# 13 NBSRC_CLK 13
GFX_CLK# 49 GFX_CLK 49
SBLINK_CLK# 13 SBLINK_CLK 13
SBSRC_CLK# 18 SBSRC_CLK 18
CLK_PCIE_DOCK1# 57 CLK_PCIE_DOCK1 57
CLK_PCIE_DOCK2# 57 CLK_PCIE_DOCK2 57
SBLINK_CLK# SBLINK_CLK SBSRC_CLK# SBSRC_CLK GFX_CLK# GFX_CLK
E
1 2 1 2 1 2 1 2 1 2 1 2
R13 49D9R2F R14 49D9R2F R17 49D9R2F R18 49D9R2F R19 49D9R2F R20 49D9R2F
Dummy when use UMA
2 2
NBSRC_CLK# NBSRC_CLK
3D3V_CLK_VDD
1 1
1 2 1 2
1 2
1 2
1 2 1 2
R23 2K2R2 R24 DUMMY-R2
R25 2K2R2
R26 DUMMY-R2
R27 2K2R2 R28 DUMMY-R2
DY
FS0
DY
DY
FS1
DY
DY
FS2
DY
A
B
C
D
<Variant Name>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
A3
Date: Sheet
CLKGEN_IDTCV137
Bolsena
1 2 1 2
E
R21 49D9R2F R22 49D9R2F
358Tuesday, December 28, 2004
SA
of
Page 4
A
1D2V_HT0A_S0
B
C
D
E
12
C19
SCD22U16V3ZY
4 4
3 3
12
C20 SCD22U16V3ZY
NB0CADOUT[15..0]11 NB0CADOUTJ[15..0]11
12
C21 SCD22U16V3ZY
Used SideB Power Plane
2 2
NB0HTTCLKOUT111 NB0HTTCLKOUTJ 111
1D2V_HT0B_S0
NB0HTTCLKOUT011 NB0HTTCLKOUTJ 011
1 2 1 2
NB0HTTCTLOUT11 NB0HTTCTLOUTJ11
12
C22 SCD22U16V3ZY
HTT for CPU sideA Transmit power and NB sideA Receive power
D29 D27 D25 C28 C26 B29 B27
T25 R25 U27 U26 V25
U25 W27 W26
AA27 AA26 AB25 AA25 AC27 AC26 AD25 AC25
T27
T28
V29
U29
V27
V28
Y29 W29
AB29 AA29 AB27 AB28 AD29 AC29 AD27 AD28
Y25 W25
Y27
Y28
R27
R26
T29
R29
U2A
VLDT0_A VLDT0_A VLDT0_A VLDT0_A VLDT0_A VLDT0_A VLDT0_A
L0_CADIN_H15 L0_CADIN_L15 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H0 L0_CADIN_L0
L0_CLKIN_H1 L0_CLKIN_L1 L0_CLKIN_H0 L0_CLKIN_L0
L0_CTLIN_H1 L0_CTLIN_L1 L0_CTLIN_H0 L0_CTLIN_L0
62.10030.041
VLDT0_B VLDT0_B VLDT0_B VLDT0_B VLDT0_B VLDT0_B VLDT0_B
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0 L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
AH29 AH27 AG28 AG26 AF29 AE28 AF25
N26 N27 L25 M25 L26 L27 J25 K25 G25 H25 G26 G27 E25 F25 E26 E27 N29 P29 M28 M27 L29 M29 K28 K27 H28 H27 G29 H29 F28 F27 E29 F29
J26 J27 J29 K29
N25 P25 P28 P27
CPUCADOUT15 CPUCADOUTJ15 CPUCADOUT14 CPUCADOUTJ14 CPUCADOUT13 CPUCADOUTJ13 CPUCADOUT12 CPUCADOUTJ12 CPUCADOUT11 CPUCADOUTJ11 CPUCADOUT10 CPUCADOUTJ10 CPUCADOUT9 CPUCADOUTJ9 CPUCADOUT8 CPUCADOUTJ8 CPUCADOUT7 CPUCADOUTJ7 CPUCADOUT6 CPUCADOUTJ6 CPUCADOUT5 CPUCADOUTJ5 CPUCADOUT4 CPUCADOUTJ4 CPUCADOUT3 CPUCADOUTJ3 CPUCADOUT2 CPUCADOUTJ2 CPUCADOUT1 CPUCADOUTJ1 CPUCADOUT0 CPUCADOUTJ0
CPUHTTCLKOUT1 CPUHTTCLKOUTJ1 CPUHTTCLKOUT0 CPUHTTCLKOUTJ0
CPUHTTCTLOUT0 CPUHTTCTLOUTJ0
1D2V_HT0A_S0 1D2V_HT0B_S0
NB0CADOUT15 NB0CADOUTJ15 NB0CADOUT14 NB0CADOUTJ14 NB0CADOUT13 NB0CADOUTJ13 NB0CADOUT12 NB0CADOUTJ12 NB0CADOUT11 NB0CADOUTJ11 NB0CADOUT10 NB0CADOUTJ10 NB0CADOUT9 NB0CADOUTJ9 NB0CADOUT8 NB0CADOUTJ8 NB0CADOUT7 NB0CADOUTJ7 NB0CADOUT6 NB0CADOUTJ6 NB0CADOUT5 NB0CADOUTJ5 NB0CADOUT4 NB0CADOUTJ4 NB0CADOUT3 NB0CADOUTJ3 NB0CADOUT2 NB0CADOUTJ2 NB0CADOUT1 NB0CADOUTJ1 NB0CADOUT0 NB0CADOUTJ0
NB0HTTCLKOUT1 NB0HTTCLKOUTJ1 NB0HTTCLKOUT0 NB0HTTCLKOUTJ0
R29 49D9R3F
R30 49D9R3F
CPUHTTCTLIN1 CPUHTTCTLINJ1 NB0HTTCTLOUT NB0HTTCTLOUTJ
HTT for CPU sideB Receive power and NB sideA Transmit power
12
C23 SC4D7U10V5ZY
Used SideA Power Plane
CPUHTTCLKOUT1 11 CPUHTTCLKOUTJ1 11 CPUHTTCLKOUT0 11 CPUHTTCLKOUTJ0 11
CPUHTTCTLOUT0 11 CPUHTTCTLOUTJ0 11
LAYOUT: Place bypass cap on topside of board near HTT power pins that are not connected directly to downstream HTT device, but connected internally to other HTT power pins.
CPUCADOUT[15..0] 11 CPUCADOUTJ[15..0] 11
By ME requset U11 P/N:
1 1
Main 62.10030.041 Second 62.10053.191 Third 62.10053.201
A
B
C
BGA754-SKT-U
<Variant Name>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
A3
D
Date: Sheet
CPU(1/4)_HyperTransport I/F
Bolsena
458Tuesday, December 28, 2004
E
of
SA
Page 5
A
B
C
D
E
U2B
MEMRESET_L
MEMCLK_H7 MEMCLK_L7 MEMCLK_H6 MEMCLK_L6 MEMCLK_H5 MEMCLK_L5 MEMCLK_H4 MEMCLK_L4 MEMCLK_H3 MEMCLK_L3 MEMCLK_H2 MEMCLK_L2 MEMCLK_H1 MEMCLK_L1 MEMCLK_H0 MEMCLK_L0
MEMCS_L7 MEMCS_L6 MEMCS_L5 MEMCS_L4 MEMCS_L3 MEMCS_L2 MEMCS_L1 MEMCS_L0
MEMRASA_L MEMCASA_L
MEMWEA_L
MEMBANKA1 MEMBANKA0
MEMADDA13 MEMADDA12 MEMADDA11 MEMADDA10
MEMADDA9 MEMADDA8 MEMADDA7 MEMADDA6 MEMADDA5 MEMADDA4 MEMADDA3 MEMADDA2 MEMADDA1 MEMADDA0
MEMRASB_L MEMCASB_L
MEMWEB_L
MEMBANKB1 MEMBANKB0
MEMADDB13 MEMADDB12 MEMADDB11 MEMADDB10
MEMADDB9 MEMADDB8 MEMADDB7 MEMADDB6 MEMADDB5 MEMADDB4 MEMADDB3 MEMADDB2 MEMADDB1 MEMADDB0
MEMCHECK7 MEMCHECK6 MEMCHECK5 MEMCHECK4 MEMCHECK3 MEMCHECK2 MEMCHECK1 MEMCHECK0
C
VTT_A VTT_A VTT_A VTT_A VTT_B VTT_B VTT_B VTT_B
MEMCKEA MEMCKEB
NC_E13 NC_C12
NC_E14 NC_D12
D17 A18 B17 C17 AF16 AG16 AH16 AJ17
AG10 AE8
AE7 D10
C10 E12 E11 AF8 AG8 AF10 AE10 V3 V4 K5 K4 R5 P5 P3 P4
D8 C8 E8 E7 D6 E6 C4 E5
H5 D4 G5
K3 H3
E13 C12 E10 AE6 AF3 M5 AE5 AB5 AD3 Y5 AB4 Y3 V5 T5 T3 N5
H4 F5 F4
L5 J5
E14 D12 E9 AF6 AF4 M4 AD5 AC5 AD4 AA5 AB3 Y4 W5 U5 T4 M3
N3 N1 U3 V1 N2 P1 U1 U2
BGA754-SKT-U
4 4
2D5V_S3
VREF_DDR_CLAW
R32
1 2
34D8R2F
R31
1 2
34D8R2F
TP1 TPAD30
DDRVTT_SENSE
MEMZN MEMZP
AE13
AG12
D14 C14
VTT_SENSE
MEMVREF1 MEMZN
MEMZP
VREF_DDR_MEM
NOTE: Test wi th p assive probes only.
M_DATA[63..0]9
2D5V_S3
3 3
NOTE: Install to bypass op-amp
12
12
R33 100R3F
R34 100R3F
12
C27 SCD1U
12
VREF_DDR_MEM
C28 SCD1U
12
C25 SC1000P50V2KX
LAYOUT: L ocate close to D IMMs.
NOTE: Remove to bypass op-amp
2 2
VREF_DDR_CLAW
2D5V_S3
12
12
1 1
12
R35 100R3
R36 100R3
C29 SCD1U
12
C30 SCD1U
VREF_DDR_CLAW
LAYOUT: Locate close to CPU .
A
12
C31 SC1000P50V2KX
M_ADM[7..0]9
M_DQS[7..0]9
B
M_DATA63 M_DATA62 M_DATA61 M_DATA60 M_DATA59 M_DATA58 M_DATA57 M_DATA56 M_DATA55 M_DATA54 M_DATA53 M_DATA52 M_DATA51 M_DATA50 M_DATA49 M_DATA48 M_DATA47 M_DATA46 M_DATA45 M_DATA44 M_DATA43 M_DATA42 M_DATA41 M_DATA40 M_DATA39 M_DATA38 M_DATA37 M_DATA36 M_DATA35 M_DATA34 M_DATA33 M_DATA32 M_DATA31 M_DATA30 M_DATA29 M_DATA28 M_DATA27 M_DATA26 M_DATA25 M_DATA24 M_DATA23 M_DATA22 M_DATA21 M_DATA20 M_DATA19 M_DATA18 M_DATA17 M_DATA16 M_DATA15 M_DATA14 M_DATA13 M_DATA12 M_DATA11 M_DATA10 M_DATA9 M_DATA8 M_DATA7 M_DATA6 M_DATA5 M_DATA4 M_DATA3 M_DATA2 M_DATA1 M_DATA0
M_ADM8 M_ADM7 M_ADM6 M_ADM5 M_ADM4 M_ADM3 M_ADM2 M_ADM1 M_ADM0 M_DQS8 M_DQS7 M_DQS6 M_DQS5 M_DQS4 M_DQS3 M_DQS2 M_DQS1 M_DQS0
A16 B15 A12 B11 A17 A15 C13 A11 A10
C11
AC1 AC3
AC2 AD1 AE1 AE3
AG3
AJ4
AE2
AF1
AH3
AJ3 AJ5 AJ6
AJ7 AH9 AG5 AH5
AJ9
AJ10
AH11
AJ11
AH15
AJ15
AG11
AJ12 AJ14 AJ16
A13
AA1 AG1 AH7
AH13
A14
AB1
AJ2
AJ8
AJ13
B9 C7 A6
A9 A5 B5 C5 A4 E2 E1 A3 B3 E3
F1 G2 G1
L3
L1 G3
J2
L2 M1 W1 W3
W2
Y1
R1
A7
C2
H1
T1
A8
D1
J1
MEMDATA63 MEMDATA62 MEMDATA61 MEMDATA60 MEMDATA59 MEMDATA58 MEMDATA57 MEMDATA56 MEMDATA55 MEMDATA54 MEMDATA53 MEMDATA52 MEMDATA51 MEMDATA50 MEMDATA49 MEMDATA48 MEMDATA47 MEMDATA46 MEMDATA45 MEMDATA44 MEMDATA43 MEMDATA42 MEMDATA41 MEMDATA40 MEMDATA39 MEMDATA38 MEMDATA37 MEMDATA36 MEMDATA35 MEMDATA34 MEMDATA33 MEMDATA32 MEMDATA31 MEMDATA30 MEMDATA29 MEMDATA28 MEMDATA27 MEMDATA26 MEMDATA25 MEMDATA24 MEMDATA23 MEMDATA22 MEMDATA21 MEMDATA20 MEMDATA19 MEMDATA18 MEMDATA17 MEMDATA16 MEMDATA15 MEMDATA14 MEMDATA13 MEMDATA12 MEMDATA11 MEMDATA10 MEMDATA9 MEMDATA8 MEMDATA7 MEMDATA6 MEMDATA5 MEMDATA4 MEMDATA3 MEMDATA2 MEMDATA1 MEMDATA0
MEMDQS17 MEMDQS16 MEMDQS15 MEMDQS14 MEMDQS13 MEMDQS12 MEMDQS11 MEMDQS10 MEMDQS9 MEMDQS8 MEMDQS7 MEMDQS6 MEMDQS5 MEMDQS4 MEMDQS3 MEMDQS2 MEMDQS1 MEMDQS0
1D25V_S3
MEMRESET# M_CKE#0
M_CKE#1 M_CLK7
M_CLK#7 M_CLK6 M_CLK#6 M_CLK5 M_CLK#5 M_CLK4 M_CLK#4
M_CLK1 M_CLK#1 M_CLK0 M_CLK#0
M_CS#7 M_CS#6 M_CS#5 M_CS#4 M_CS#3 M_CS#2 M_CS#1 M_CS#0
M_ARAS# M_ACAS# M_AWE#
M_ABS#1 M_ABS#0
RSVD_M_AA15 RSVD_M_AA14 M_AA13 M_AA12 M_AA11 M_AA10 M_AA9 M_AA8 M_AA7 M_AA6 M_AA5 M_AA4 M_AA3 M_AA2 M_AA1 M_AA0
M_BRAS# M_BCAS# M_BWE#
M_BBS#1 M_BBS#0
RSVD_M_BA15 RSVD_M_BA14 M_BA13 M_BA12 M_BA11 M_BA10 M_BA9 M_BA8 M_BA7 M_BA6 M_BA5 M_BA4 M_BA3 M_BA2 M_BA1 M_BA0
CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0
12
12
C24 SCD1U
For REGISTED DIMM Only UNBUFFER DIMM NC
TP16 TP15
TPAD30 TP18
TPAD30 TPAD30
TP17 TP20
TPAD30 TP19
TPAD30 TPAD30
TP22 TPAD30
TP21 TPAD30
D
C26 SC1000P50V2KX
M_CKE#0 8,9 M_CKE#1 8,9
M_CLK7 8,9 M_CLK#7 8,9 M_CLK6 8,9 M_CLK#6 8,9 M_CLK5 8,9 M_CLK#5 8,9 M_CLK4 8,9 M_CLK#4 8,9
M_CLK#1 M_CLK#0 M_CLK1 M_CLK0
M_CS#3 8,9 M_CS#2 8,9 M_CS#1 8,9 M_CS#0 8,9
M_ARAS# 8,9 M_ACAS# 8,9 M_AWE# 8,9
M_ABS#1 8,9 M_ABS#0 8,9
M_AA[13..0] 8,9
AMD suggested M_AA13 connect to DIMM pin123
M_BRAS# 8,9 M_BCAS# 8,9 M_BWE# 8,9
M_BBS#1 8,9 M_BBS#0 8,9
M_BA[13..0] 8,9
AMD suggested M_BA13 connect to DIMM pin123
<Variant Name>
Title
Size Document Number Rev
A3
Date: Sheet of
2D5V_S3
RN7
1
8
2
7
3
6
45
SRN10K-2
M_DQS8 M_ADM8
MEMRESET# M_CS#7 M_CS#6 M_CS#5 M_CS#4 RSVD_M_AA15 RSVD_M_AA14 RSVD_M_BA15 RSVD_M_BA14
NOT SUPPORT ECC CHECK AMD suggested remove PULL-HI resistor.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
CPU(2/4)_DDR
Bolsena
558Tuesday, December 28, 2004
E
TP5 TP4
TPAD30 TPAD30
TP7 TP6
TPAD30 TPAD30
TP8 TPAD30
TP10 TP9
TPAD30 TPAD30
TP11 TP12
TPAD30 TPAD30
TP14 TPAD30
TP13 TPAD30
SA
Page 6
A
2D5V_VDDA_S0
2D5V_S0
4 4
12
2D5V_CPUA_S0
R39
1 2
0R3-U
C35 SC10U10V5ZY
1 2
63.R0004.151
DY
2D5V_CPUR_S0
R40 0R3-U
12
1 2
TC1 ST100U4VBM-1
AMD SUGGEST TO USE 2D5V_CPUA_S0
KEMET,NT:5.7, B2 size ST100U4VBM-1 (80.10716.321)
3 3
2D5V_S0
2 2
DBREQJ
DY
DBRDY TCK TMS TDI TRST_L TDO
2D5V_S3
CHANGE FROM 1KR3 TO 680R2 FOR AMD CHECK LIST
NC_AG17 NC_AJ18 NC_D18
NC_B19
1 1
NC_C19 NC_D20 NC_C21
Iripple=1.1A,ESR=70mohm
SANYO, NT$:6.1 Iripple=1.1A,ESR=70mohm
3.5/2.8/2.0
77.21071.031
678
C44 SCD1U
RN8
123
SRN680-U
DY
1 2
DY
RN10
1 2 3 4 5
RN11
SRN680-U
1 2 3 4 5
SRN680-U
R57 680R3
A
4 5
8 7 6
8 7 6
12
AMD SUGGEST TO USE 100 ~ 300UH
Change L270H
2D5V_VDDA_S0
R59 0R5J-1
12
DY
LAYOUT: Rou te tr ace 50 mils wide and 500 to 750 mils long between these caps.
12
C39 SC4D7U10V5ZY
78.47593.411 1D2V_HT0B_S0
12
R53
R54
680R3
680R3
DY
1 2 1 2
64.44R25.551
AMD suggest voltege from 2D5V_S0 to 2D5V_S3
differentially im pedance 100
B
3D3V_S0
12
C33 SC1U10V3KX
LAYOUT: Route VDDA trace approx. 50 mils wid e (use 2x25 mil traces to exit ball field) and 500 mils long.
1 2 1 2
12
C40 SCD22U16V3ZY
12
R46 820R3
R42 820R3
1 2 1 2 1 2
C41 SC1000P50V2KX
CPUCLK3
CPUCLK#3
R48 680R3
R43 680R3
R50 680R3
2D5V_S0
LDT_RST#18 SB_CPUPWRGD18 LDT_STP#13,18
1 2
1 2
COREFB#41
1D25V_S3
2D5V_S0
COREFB41
C42 SC3900P50V3KX
C38 SC3900P50V3KX
R44 44D2R3F
R41 44D2R3F
12
C36 SC3300P50V2KX
12
2D5V_S3
LDT_RST# SB_CPUPWRGD LDT_STP#
C37 SC1000P50V2KX
Validation Test Points
LAYOUT: Place close to the CPU.
NC_C15 NC_AE23 NC_AF23 NC_AF22 NC_AF21
B
TP28 TPAD30
TP30 TPAD30 TP34
TPAD30 TPAD30
TP35 TPAD30
LDT_RST# CLKIN CLKIN# CORE_SENSE VDDIOFB VDDIOFBJ VDDIOSENSE NC_AE24 NC_AF24
C
Iomax=120mA
U3
1
SHDN#
2
GND
3
IN
G913C-U
DY
12
R51
1 2
680R3 R52
1 2
680R3
678
RN9
123
SRN680-U
DY
C
SET
OUT
L0_REF1 L0_REF0
COREFB COREFB# CORE_SENSE
VDDIOFB VDDIOFBJ VDDIOSENSE
CLKIN
R45 169R3F
CLKIN# NC_AJ23 NC_AH23 NC_AE24 NC_AF24
DBRDY NC_C15 TMS
TCK TRST_L
TDI
NC_AE23 NC_AF23 NC_AF22 NC_AF21
4 5
TP26 TP25
TPAD30 TPAD30
TP27 TPAD30
TP29 TP31
TPAD30 TPAD30
TP33 TPAD30TP32
TP37 TP36
TPAD30 TPAD30
TP38 TPAD30
2D5V_CPUA_S0
2D5V_VDDA_VREF
5 4
NC_C18 NC_A19
12
C34 SC1U10V3KX
AH25
AJ25 AF20
AE18
AJ27
AF27 AE26
A23 A24 B23
AE12 AF12 AE11
AJ21
AH21
AJ23
AH23
AE24 AF24
C16
AG15 AH17
C15 E20
E17 B21 A21
C18 A19 A28
AJ28
AE23 AF23 AF22 AF21
C1
J3
R3
AA2
D3
AG2
B18
AH1
AE21
C20
AG4
C6 AG6 AE9 AG9
12
C32 SC22P50V2JN-1
U2C
VDDA1 VDDA2
RESET_L PWROK LDTSTOP_L
L0_REF1 L0_REF0
COREFB_H COREFB_L CORE_SENSE
VDDIOFB_H VDDIOFB_L VDDIO_SENSE
CLKIN_H CLKIN_L
NC_AJ23 NC_AH23
NC_AE24 NC_AF24
VTT_A VTT_B
DBRDY NC_C15 TMS
TCK TRST_L TDI
NC_C18 NC_A19 KEY1
KEY0 NC_AE23
NC_AF23 NC_AF22 NC_AF21
NC_C1 NC_J3 NC_R3 NC_AA2 NC_D3 NC_AG2 NC_B18 NC_AH1 NC_AE21 NC_C20 NC_AG4 NC_C6 NC_AG6 NC_AE9 NC_AG9
BGA754-SKT-U
D
12
R37
R1
20KR3F
12
DY
R38 20KR3F
Vout = 1.25*(1+ R1/R2)
R2
E
DY
THERMTRIP#
THERMDA THERMDC
VID4 VID3 VID2 VID1 VID0
NC_AG18 NC_AH18 NC_AG17
NC_AJ18
DBREQ_L
NC_D20 NC_C21 NC_D18 NC_C19 NC_B19
TDO
NC_AF18
A20 A26
A27 AG13
AF14 AG14 AF15 AE15
AG18 AH18 AG17 AJ18
AH19 AJ19
AE19 D20
C21 D18 C19 B19
A22
AF18
THERMDP 23
VID4 VID3 VID2 VID1 VID0
NC_AG18 NC_AH18 NC_AG17 NC_AJ18
FBCLKOUT
FBCLKOUTJ
DBREQJ
NC_D20 NC_C21 NC_D18 NC_C19 NC_B19
TDO
THERMDN 23
TP23 TP24
TPAD30 TPAD30
LAYOUT: Route FBCLKOUT_H/L
differentially i mpedance 80
12
R47 80D6R3F-U
R49
1 2
DUMMY-R3
DY
2D5V_S3
VID[4..0] 41
THERMTRIP_L
FBCLKOUT_H
FBCLKOUT_L
Connect to VDDIO for AMD suggest.
D22
NC_D22
C22
NC_C22
NC_B13
NC_B7 NC_C3 NC_K1 NC_R2
NC_AA3
NC_F3 NC_C23 NC_AG7
NC_AE22
NC_C24 NC_A25
NC_C9
B13 B7 C3 K1 R2 AA3 F3 C23 AG7 AE22 C24 A25 C9
THERMTRIP#
2D5V_S0
12
2
R55 680R3
1
3D3V_S5
3
Q1 MMBT3904-U1
NS3
1 2
12
R56 10KR2
CPU_THERMTRIP# 21,23
2D5V_S0
R58 1KR2
THERMTRIP#Level shift to SB400
<Variant Name>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
A3
D
Date: Sheet of
CPU(3/4)_Control & Debug
Bolsena
658Tuesday, December 28, 2004
E
SA
Page 7
A
VCC_CORE_S0 2D5V_S3
N20
Y17
VSS
K17
VSS
H17
VSS
F17
U2E
VSS
E18
VSS
AJ26
VSS
AE29
VSS
AC16
VSS
AA16
VSS
J16
VSS
G16
VSS
E16
VSS
AH14
4 4
3 3
2 2
1 1
AD15 AB15
K15 E15
D16 AE14 AC14 AA14
G14
AF17 AD13 AB13
Y13 K13 H13
F13 AH12 AC12 AA12
G12
B12 AD11 AB11
Y11
K11
H11
F11 AH10 AC10
W10
U10
R10
N10
G10
B10
AD9
AH8 AC8
AD7
AB7
AH6 AC6
AA6
AH4 AH2
AD2
AB2
C29 AH28
AF28
AC28
W28
R28
VSS VSS VSS VSS VSS VSS VSS VSS VSS
J14
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
L10
VSS
J10
VSS VSS VSS VSS
Y9
VSS
V9
VSS
T9
VSS
P9
VSS
M9
VSS
K9
VSS
H9
VSS
F9
VSS VSS VSS
W8
VSS
U8
VSS
R8
VSS
N8
VSS
L8
VSS
J8
VSS
G8
VSS
B8
VSS VSS VSS
V7
VSS
T7
VSS
P7
VSS
M7
VSS
K7
VSS
H7
VSS
F7
VSS VSS VSS VSS
U6
VSS
R6
VSS
N6
VSS
L6
VSS
J6
VSS
G6
VSS
B6
VSS VSS
B4
VSS VSS VSS VSS
Y2
VSS
V2
VSS
T2
VSS
P2
VSS
M2
VSS
K2
VSS
H2
VSS
F2
VSS VSS VSS VSS VSS VSS VSS
L28
VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
L20 J20 AF19 AD19 AB19 Y19 K19 H19 F19 D19 AC18 AA18 G18 B16 AD17 AB17 H15 F15 G28 D28 B28 C27 AH26 AF26 AD26 Y26 T26 M26 H26 D26 B26 C25 B25 AJ24 AG24 AC24 AA24 W24 U24 R24 N24 J24 G24 E24 AG23 AD23 AB23 Y23 V23 T23 P23 K23 H23 F23 D23 AJ22 AH22 AG22 AC22 AA22 AG29 U22 R22 N22 L22 J22 G22 E22 B22 AG21 AD21 Y21 V21 T21 P21 M21 K21 H21 F21 D21 AJ20 AG20 AE20 AC20 AA20 W20 U20 R20 G20 J18 AE16 Y15 B14 J12 AA10 AB9 AA8 Y7 W6 AF2 D2 AG27 AG25 L24 M23 W22 AB21 AH20 B2
A
AC15
H18 B20 E21 H22
H24 F26
V10 G13 K14 Y14
AB14
G15
AA15
H16 K16 Y16
AB16
G17
AA17 AC17 AE17
F18 K18
Y18 AB18 AD18 AG19
E19
G19 AC19 AA19
F20
H20
K20
M20
P20
T20
V20
Y20 AB20 AD20
G21
N21
R21
U21
W21 AA21 AC21
F22 K22 M22 P22 T22 V22
Y22 AB22 AD22
E23
G23
N23
R23
U23
W23 AA23 AC23
B24 D24 F24 K24 M24 P24 T24 V24
Y24 AB24 AD24 AH24 AE25
K26
P26
V26
L7
VDD VDD VDD VDD
U2D
VDD VDD
J23
VDD VDD VDD
N7
VDD
L9
VDD VDD VDD VDD VDD VDD VDD
J15
VDD VDD VDD VDD VDD VDD VDD
J17
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
J19
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
J21
VDD
L21
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
L23
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
E4 G4 J4 L4 N4 U4 W4 AA4 AC4 AE4 D5 AF5 F6 H6 K6 M6 P6 T6 V6 Y6 AB6 AD6 D7 G7 J7 AA7 AC7 AF7 F8 H8 AB8 AD8 D9 G9 AC9 AF9 F10 AD10 D11 AF11 F12 AD12 D13 AF13 F14 AD14 F16 AD16 D15 R4
N28 U28 AA28 AE27 R7 U7 W7 K8 M8 P8 T8 V8 Y8 J9 N9 R9 U9 W9 AA9 H10 K10 M10 P10 T10 Y10 AB10 G11 J11 AA11 AC11 H12 K12 Y12 AB12 J13 AA13 AC13 H14 AB26 E28 J28
B
VCC_CORE_S0
B
VCC_CORE_S0
12
VCC_CORE_S0
C55 SCD22U16V3ZY
1 2
0.22u x 4
DY
2D5V_S3
12
C61 SCD22U16V3ZY
1D25V_S3
12
C74 SCD22U16V3ZY
0.22u x 2
C
LAYOUT: Place in uPGA socket cavity.
0.22u x 6
12
C45
C46
SCD22U16V3ZY
SCD22U16V3ZY
12
C47 SCD22U16V3ZY
12
C48 SCD22U16V3ZY
12
C49 SCD22U16V3ZY
12
C50 SCD22U16V3ZY
LAYOUT: Place on backside of processor.
C56 SCD22U16V3ZY
1 2
C57 SCD22U16V3ZY
1 2
C58 SCD22U16V3ZY
1 2
12
C59 SC10U10V5ZY
C60 SC10U10V5ZY
12
10u x 2
DY
DY
12
DY
12
C63
C62
SCD22U16V3ZY
SCD22U16V3ZY
12
C64 SCD22U16V3ZY
12
C65 SCD22U16V3ZY
12
C66 SCD22U16V3ZY
2D5V_S3
10u x 1 4.7u x 6
1D25V_S3
12
12
12
C75 SCD22U16V3ZY
C77
C76
SC4D7U10V5ZY
SC4D7U10V5ZY
4.7u x 2
C
12
12
C67 SC10U10V5ZY
10u x 4
12
C51 SC10U10V5ZY
12
C68 SC4D7U10V5ZY
12
C52 SC10U10V5ZY
12
C69 SC4D7U10V5ZY
D
12
C53 SC10U10V5ZY
12
C70 SC4D7U10V5ZY
D
BGA754-SKT-U
C54 SC10U10V5ZY
12
C71 SC4D7U10V5ZY
E
BGA754-SKT-U
12
12
78.47593.411
C72
C73
SC4D7U10V5ZY
SC4D7U10V5ZY
<Variant Name>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
A3
Date: Sheet
CPU(4/4)_Power
Bolsena
758Tuesday, December 28, 2004
E
SA
of
Page 8
A
M_AA0 M_AA1 M_AA2 M_AA3 M_AA4 M_AA5 M_AA6 M_AA7 M_AA8 M_AA9 M_AA10 M_AA11
4 4
3 3
2 2
1 1
M_ARAS#5,9 M_ACAS#5,9 M_AWE#5,9
VREF_DDR_MEM VREF_DDR_MEM
Layout trace 20 mil Layout trace 20 mil
M_AA12 M_ABS#0
M_ABS#1 M_DATA_R_0
M_DATA_R_1 M_DATA_R_2 M_DATA_R_3 M_DATA_R_4 M_DATA_R_5 M_DATA_R_6 M_DATA_R_7 M_DATA_R_8 M_DATA_R_9 M_DATA_R_10 M_DATA_R_11 M_DATA_R_12 M_DATA_R_13 M_DATA_R_14 M_DATA_R_15 M_DATA_R_16 M_DATA_R_17 M_DATA_R_18 M_DATA_R_19 M_DATA_R_20 M_DATA_R_21 M_DATA_R_22 M_DATA_R_23 M_DATA_R_24 M_DATA_R_25 M_DATA_R_26 M_DATA_R_27 M_DATA_R_28 M_DATA_R_29 M_DATA_R_30 M_DATA_R_31 M_DATA_R_32 M_DATA_R_33 M_DATA_R_34 M_DATA_R_35 M_DATA_R_36 M_DATA_R_37 M_DATA_R_38 M_DATA_R_39 M_DATA_R_40 M_DATA_R_41 M_DATA_R_42 M_DATA_R_43 M_DATA_R_44 M_DATA_R_45 M_DATA_R_46 M_DATA_R_47 M_DATA_R_48 M_DATA_R_49 M_DATA_R_50 M_DATA_R_51 M_DATA_R_52 M_DATA_R_53 M_DATA_R_54 M_DATA_R_55 M_DATA_R_56 M_DATA_R_57 M_DATA_R_58 M_DATA_R_59 M_DATA_R_60 M_DATA_R_61 M_DATA_R_62 M_DATA_R_63
12
A
3D3V_S0
C519 SCD1U
TP126 TPAD30
DDR1
112
A0
111
A1
110
A2
109
A3
108
A4
107
A5
106
A6
105
A7
102
A8
101
A9
115
A10 / AP
100
A11
99
A12
117
BA0
116
BA1
5
DQ0
7
DQ1
13
DQ2
17
DQ3
6
DQ4
8
DQ5
14
DQ6
18
DQ7
19
DQ8
23
DQ9
29
DQ10
31
DQ11
20
DQ12
24
DQ13
30
DQ14
32
DQ15
41
DQ16
43
DQ17
49
DQ18
53
DQ19
42
DQ20
44
DQ21
50
DQ22
54
DQ23
55
DQ24
59
DQ25
65
DQ26
67
DQ27
56
DQ28
60
DQ29
66
DQ30
68
DQ31
127
DQ32
129
DQ33
135
DQ34
139
DQ35
128
DQ36
130
DQ37
136
DQ38
140
DQ39
141
DQ40
145
DQ41
151
DQ42
153
DQ43
142
DQ44
146
DQ45
152
DQ46
154
DQ47
163
DQ48
165
DQ49
171
DQ50
175
DQ51
164
DQ52
166
DQ53
172
DQ54
176
DQ55
177
DQ56
181
DQ57
187
DQ58
189
DQ59
178
DQ60
182
DQ61
188
DQ62
190
DQ63
71
CB0
73
CB1
79
CB2
83
CB3
72
CB4
74
CB5
80
CB6
84
CB7
85
NC#85
86
NC#86/(RESET#)
97
NC#97/A13
98
NC#98/BA2
123
NC#123
124
NC#124
200
NC#200
118
/RAS
120
/CAS
119
/WE
1
VREF
2
VREF
197
VDDSPD
199
VDDID
201
GND
SKT-SODIMM200-24
/CS0 /CS1
CKE0 CKE1
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8
CK0
/CK0
CK1
/CK1
CK2
/CK2
SCL SDA
SA0 SA1 SA2
VDD VDD VDD VDD VDD VDD VDD
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
REVERSE TYPE 5.2MM
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS GND
121 122
96 95
11 25 47 61 133 147 169 183 77
12 26 48 62 134 148 170 184 78
35 37 160 158 89 91
195 193
194 196 198
9 10 21 22 33 34 36 45 46 57 58 69 70 81 82 92 93 94 113 114 131 132 143 144 155 156 157 167 168 179 180 191 192
3 4 15 16 27 28 38 39 40 51 52 63 64 75 76 87 88 90 103 104 125 126 137 138 149 150 159 161 162 173 174 185 186
202
B
M_CKE#0
M_DQS_R0 M_DQS_R1 M_DQS_R2 M_DQS_R3 M_DQS_R4 M_DQS_R5 M_DQS_R6 M_DQS_R7
M_ADM_R0 M_ADM_R1 M_ADM_R2 M_ADM_R3
M_ADM_R5 M_ADM_R6 M_ADM_R7
DDR_CLK0 DDR_CLK#0
SMBC_SB SMBD_SB
NOT SUPPORT ECC CHECK AMD suggested pull-low
2D5V_S3
M_ADM#0 M_ADM#1 M_ADM#2 M_ADM#3 M_ADM#4 M_ADM#5 M_ADM#6 M_ADM#7
M_CLK5 5,9 M_CLK#5 5,9 M_CLK7 5,9 M_CLK#7 5,9
62.10017.701
B
C
M_CS#0 5,9 M_CS#1 5,9
M_CKE#0 5,9 M_CKE#1 5,9
M_BRAS#5,9 M_BCAS#5,9 M_BWE#5,9
M_BA0 M_BA1 M_BA2 M_BA3 M_BA4 M_BA5 M_BA6 M_BA7 M_BA8 M_BA9 M_BA10 M_BA11 M_BA12
M_BBS#0 M_BBS#1
M_DATA_R_0 M_DATA_R_1 M_DATA_R_2 M_DATA_R_3 M_DATA_R_4 M_DATA_R_5 M_DATA_R_6 M_DATA_R_7 M_DATA_R_8 M_DATA_R_9 M_DATA_R_10 M_DATA_R_11 M_DATA_R_12 M_DATA_R_13 M_DATA_R_14 M_DATA_R_15 M_DATA_R_16 M_DATA_R_17 M_DATA_R_18 M_DATA_R_19 M_DATA_R_20 M_DATA_R_21 M_DATA_R_22 M_DATA_R_23 M_DATA_R_24 M_DATA_R_25 M_DATA_R_26 M_DATA_R_27 M_DATA_R_28 M_DATA_R_29 M_DATA_R_30 M_DATA_R_31 M_DATA_R_32 M_DATA_R_33 M_DATA_R_34 M_DATA_R_35 M_DATA_R_36 M_DATA_R_37 M_DATA_R_38 M_DATA_R_39 M_DATA_R_40 M_DATA_R_41 M_DATA_R_42 M_DATA_R_43 M_DATA_R_44 M_DATA_R_45 M_DATA_R_46 M_DATA_R_47 M_DATA_R_48 M_DATA_R_49 M_DATA_R_50 M_DATA_R_51 M_DATA_R_52 M_DATA_R_53 M_DATA_R_54 M_DATA_R_55 M_DATA_R_56 M_DATA_R_57 M_DATA_R_58 M_DATA_R_59 M_DATA_R_60 M_DATA_R_61 M_DATA_R_62 M_DATA_R_63
M_BA13M_AA13
12
3D3V_S0
C520 SCD1U
TP127 TPAD30
DDR2
112
A0
111
A1
110
A2
109
A3
108
A4
107
A5
106
A6
105
A7
102
A8
101
A9
115
A10 / AP
100
A11
99
A12
117
BA0
116
BA1
5
DQ0
7
DQ1
13
DQ2
17
DQ3
6
DQ4
8
DQ5
14
DQ6
18
DQ7
19
DQ8
23
DQ9
29
DQ10
31
DQ11
20
DQ12
24
DQ13
30
DQ14
32
DQ15
41
DQ16
43
DQ17
49
DQ18
53
DQ19
42
DQ20
44
DQ21
50
DQ22
54
DQ23
55
DQ24
59
DQ25
65
DQ26
67
DQ27
56
DQ28
60
DQ29
66
DQ30
68
DQ31
127
DQ32
129
DQ33
135
DQ34
139
DQ35
128
DQ36
130
DQ37
136
DQ38
140
DQ39
141
DQ40
145
DQ41
151
DQ42
153
DQ43
142
DQ44
146
DQ45
152
DQ46
154
DQ47
163
DQ48
165
DQ49
171
DQ50
175
DQ51
164
DQ52
166
DQ53
172
DQ54
176
DQ55
177
DQ56
181
DQ57
187
DQ58
189
DQ59
178
DQ60
182
DQ61
188
DQ62
190
DQ63
71
CB0
73
CB1
79
CB2
83
CB3
72
CB4
74
CB5
80
CB6
84
CB7
85
NC#85
86
NC#86/(RESET#)
97
NC#97/A13
98
NC#98/BA2
123
NC#123
124
NC#124
200
NC#200
118
/RAS
120
/CAS
119
/WE
1
VREF
2
VREF
197
VDDSPD
199
VDDID
201
GND
SKT-SODIMM200-6U
C
121
/CS0
122
/CS1
96
CKE0
95
CKE1
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8
CK0
/CK0
CK1
/CK1
CK2
/CK2
SCL SDA
SA0 SA1 SA2
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
REVERSE TYPE 9.2MM
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
GND
11 25 47 61 133 147 169 183 77
12 26 48 62 134 148 170 184 78
35 37 160 158 89 91
195 193
194 196 198
9 10 21 22 33 34 36 45 46 57 58 69 70 81 82 92 93 94 113 114 131 132 143 144 155 156 157 167 168 179 180 191 192
3 4 15 16 27 28 38 39 40 51 52 63 64 75 76 87 88 90 103 104 125 126 137 138 149 150 159 161 162 173 174 185 186
202
M_DQS_R0 M_DQS_R1 M_DQS_R2 M_DQS_R3 M_DQS_R4 M_DQS_R5 M_DQS_R6 M_DQS_R7
M_ADM_R0 M_ADM_R1 M_ADM_R2 M_ADM_R3 M_ADM_R4M_ADM_R4 M_ADM_R5 M_ADM_R6 M_ADM_R7
DDR_CLK1
DDR_CLK#1
62.10017.391
2D5V_S3
D
M_CS#2 5,9 M_CS#3 5,9
M_ADM#0 M_ADM#1 M_ADM#2 M_ADM#3 M_ADM#4 M_ADM#5 M_ADM#6 M_ADM#7
M_CLK4 5,9 M_CLK#4 5,9 M_CLK6 5,9 M_CLK#6 5,9
SMBC_SB 3,21,57 SMBD_SB 3,21,57
1 2
D
?NEED CHANGE LIBRARY
R563
3D3V_S0
4K7R2
DDR_CLK#1 DDR_CLK#0 DDR_CLK1 DDR_CLK0
MD63
DDR1(Reverse 5.2mm)
DDR2(Reverse 9.2mm)
<Variant Name>
Title
Size Document Number Rev
A3
Date: Sheet
E
M_ADM_R[7..0] 9 M_DATA_R_[63..0] 9 M_DQS_R[7..0] 9
M_AA[13..0] 5,9 M_ABS#[1..0] 5,9 M_BA[13..0] 5,9 M_BBS#[1..0] 5,9
2D5V_S3
RN92
SRN10K-2
DY
1 2 3 45
8 7 6
AMD CPU
SMA10
SMA11
Pin 199
Pin 200 Pin 2
Pin 199 Pin 1
Pin 200 Pin 2
(Bottom view)
DDR SO-DIMM SKT
Bolsena
SMA14
SMA0 SMA12
Pin 1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
E
MD0
858Tuesday, December 28, 2004
SA
of
Page 9
A
SERIES DAMPING PARALLEL TERMINATION
PLACE RNs CLOSE TO FIRST DIMM, < 0.75" STRICT EQUAL LENGTH LIMITATION WITH DQS, CB PINS
M_DATA4 M_ADM0
M_DATA6 M_DATA7 M_DATA13 M_DATA12
4 4
M_ADM1
M_DATA1 M_DATA0 M_DQS0 M_DATA2 M_DATA3 M_DATA8 M_DATA9 M_DQS1
M_DATA14 M_DATA_R_14 M_DATA15 M_DATA21 M_DATA20 M_ADM2 M_DATA23 M_DATA_R_23 M_DATA22 M_DATA25 M_DATA_R_25
3 3
M_DATA11 M_DATA10 M_DATA17 M_DATA16 M_DQS2 M_DQS_R2 M_DATA19 M_DATA_R_19 M_DATA18 M_DATA24
M_DATA29 M_DATA28
M_ADM3 M_DATA26 M_DATA27 M_DATA30 M_DATA_R_30 M_DATA31
2 2
SRN10J-3
8 9 7 6 5 4 3 2 1
RN13 SRN10J-3
8 9 7 6 5 4 3 2 1
RN18 SRN10J-3
8 9 7 6 5 4 3 2 1
RN24 SRN10J-3
8 9 7 6 5 4 3 2 1
RN29 SRN10J-3
8 9 7 6 5 4 3 2 1
RN34
10 11 12 13 14 15 16
10 11 12 13 14 15 16
10 11 12 13 14 15 16
10 11 12 13 14 15 16
10 11 12 13 14 15 16
M_DATA_R_4 M_DATA_R_5M_DATA5 M_ADM_R0 M_DATA_R_6 M_DATA_R_7 M_DATA_R_13 M_DATA_R_12 M_ADM_R1
M_DATA_R_1 M_DATA_R_0 M_DQS_R0 M_DATA_R_2 M_DATA_R_3 M_DATA_R_8 M_DATA_R_9 M_DQS_R1
M_DATA_R_15 M_DATA_R_21 M_DATA_R_20 M_ADM_R2
M_DATA_R_22
M_DATA_R_11 M_DATA_R_10 M_DATA_R_17 M_DATA_R_16
M_DATA_R_18 M_DATA_R_24
M_DATA_R_29 M_DATA_R_28 M_DQS_R3M_DQS3 M_ADM_R3 M_DATA_R_26 M_DATA_R_27
M_DATA_R_31
M_DATA32 M_DATA33 M_DATA_R_33 M_DATA_R_33 M_DATA36 M_DATA_R_36
M_DQS4 M_DQS_R4 M_ADM4 M_ADM_R4 M_DATA34 M_DATA39
M_DATA35 M_DATA41 M_DATA40 M_DQS5 M_DATA42 M_DATA43 M_DATA49 M_DATA48
M_DATA38 M_DATA45 M_DATA44 M_ADM5 M_DATA47 M_DATA46 M_DATA53 M_DATA52
M_DQS6 M_DATA50 M_DATA51 M_DATA56 M_DATA57 M_DQS7 M_DATA58 M_DATA59
M_ADM6 M_DATA54 M_DATA55 M_DATA61 M_DATA60 M_ADM7 M_DATA62 M_DATA63
8 9 7 6 5 4 3 2 1
8 9 7 6 5 4 3 2 1
8 9 7 6 5 4 3 2 1
8 9 7 6 5 4 3 2 1
8 9 7 6 5 4 3 2 1
SRN10J-3
RN14 SRN10J-3
RN19 SRN10J-3
RN25 SRN10J-3
RN30 SRN10J-3
RN35
B
M_DATA_R_32 M_DATA_R_32
10 11
M_DATA_R_37M_DATA37 M_DATA_R_37
12 13 14
M_DATA_R_34
15
M_DATA_R_39
16
M_DATA_R_35 M_DATA_R_41
10
M_DATA_R_40
11
M_DQS_R5
12
M_DATA_R_42
13
M_DATA_R_43
14
M_DATA_R_49
15
M_DATA_R_48
16
M_DATA_R_38 M_DATA_R_45
10
M_DATA_R_44
11
M_ADM_R5
12
M_DATA_R_47
13
M_DATA_R_46
14
M_DATA_R_53
15
M_DATA_R_52
16
M_DQS_R6 M_DATA_R_50
10
M_DATA_R_51
11
M_DATA_R_56
12
M_DATA_R_57
13
M_DQS_R7
14
M_DATA_R_58
15
M_DATA_R_59
16
M_ADM_R6 M_DATA_R_54
10
M_DATA_R_55
11
M_DATA_R_61
12
M_DATA_R_60
13
M_ADM_R7
14
M_DATA_R_62
15
M_DATA_R_63
16
M_ADM_R1 M_DATA_R_13 M_DATA_R_12 M_DATA_R_7 M_DATA_R_6 M_ADM_R0 M_DATA_R_5 M_DATA_R_4
M_DATA_R_1 M_DATA_R_0 M_DQS_R0 M_DATA_R_2 M_DATA_R_3 M_DATA_R_8 M_DATA_R_9 M_DQS_R1
M_DATA_R_25
M_DATA_R_23
M_DATA_R_22 M_ADM_R2 M_DATA_R_21 M_DATA_R_20 M_DATA_R_15 M_DATA_R_14
M_DATA_R_11 M_DATA_R_10 M_DATA_R_16 M_DATA_R_17 M_DQS_R2 M_DATA_R_19 M_DATA_R_18 M_DATA_R_24
M_DATA_R_31 M_DATA_R_30 M_DATA_R_26 M_DATA_R_27 M_ADM_R3 M_DQS_R3 M_DATA_R_29 M_DATA_R_28
SRN68J-1
8 9 7 6 5 4 3 2 1
RN15 SRN68J-1
8 9 7 6 5 4 3 2 1
RN20 SRN68J-1
8 9 7 6 5 4 3 2 1
RN26 SRN68J-1
8 9 7 6 5 4 3 2 1
RN31 SRN68J-1
8 9 7 6 5 4 3 2 1
RN36
C
1D25V_S3 1D25V_S3
10 11 12 13 14 15 16
10 11 12 13 14 15 16
10 11 12 13 14 15 16
10 11 12 13 14 15 16
10 11 12 13 14 15 16
SRN68J-1
8 9 7 6 5 4 3 2 1
RN16 SRN68J-1
8 9 7 6 5 4 3 2 1
RN21 SRN68J-1
8 9 7 6 5 4 3 2 1
RN27 SRN68J-1
8 9 7 6 5 4 3 2 1
RN32 SRN68J-1
8 9 7 6 5 4 3 2 1
RN37
10 11 12 13 14 15 16
10 11 12 13 14 15 16
10 11 12 13 14 15 16
10 11 12 13 14 15 16
10 11 12 13 14 15 16
D
PULL HIGH STUBS < 0.8", PLACE RPs CLOSE TO SECOND DM ( DM2 ) NO EQUAL LENGTH LIMITATION
M_DATA_R_36 M_ADM_R4
M_DQS_R4 M_DATA_R_38 M_DATA_R_39
M_DATA_R_48 M_DATA_R_49 M_DATA_R_43 M_DATA_R_42 M_DQS_R5 M_DATA_R_41 M_DATA_R_40 M_DATA_R_34
M_DATA_R_35 M_DATA_R_44 M_DATA_R_45 M_ADM_R5 M_DATA_R_46
M_DATA_R_47 M_DATA_R_52 M_DATA_R_53
M_DATA_R_59 M_DATA_R_58 M_DQS_R7 M_DATA_R_57 M_DATA_R_56 M_DATA_R_51 M_DATA_R_50 M_DQS_R6
M_ADM_R6 M_DATA_R_54 M_DATA_R_55 M_DATA_R_60 M_DATA_R_61 M_ADM_R7 M_DATA_R_62 M_DATA_R_63
M_CKE#0 M_CKE#1
M_BA12 M_AA12
M_AA11 M_AA9 M_AA7 M_AA5 M_AA4 M_AA8 M_AA6 M_AA3
M_CS#3 M_BCAS# M_BRAS# M_BBS#1 M_CS#2 M_BA13 M_BA0 M_BA2
M_AA1 M_AA10 M_AA2 M_AA0 M_ABS#1 M_ARAS# M_AWE# M_ABS#0
M_BA7 M_BA3 M_BA6 M_BA9 M_BA10 M_BA1 M_BBS#0 M_BWE#
M_BA4 M_BA8 M_BA11 M_BA5
M_AA13 M_CS#0 M_ACAS# M_CS#1
SRN47J
1 4 2
RN17 SRN47J
1 4 2
RN22 SRN47J-1-U
8 9 7 6 5 4 3 2 1
RN23 SRN47J-1-U
8 9 7 6 5 4 3 2 1
RN28 SRN47J-1-U
8 9 7 6 5 4 3 2 1
RN33 SRN47J-1-U
8 9 7 6 5 4 3 2 1
RN38
SRN47-1
4 5 3 2 1
RN39
SRN47-1
4 5 3 2 1
RN40
E
M_ADM_R[7..0] 8
3
3
10 11 12 13 14 15 16
10 11 12 13 14 15 16
10 11 12 13 14 15 16
10 11 12 13 14 15 16
6 7 8
6 7 8
M_ADM[7..0] 5 M_DATA[63..0] 5 M_DATA_R_[63..0] 8 M_DQS[7..0] 5 M_DQS_R[7..0] 8
M_AA[13..0] 5,8
M_ABS#[1..0] 5,8
M_BA[13..0] 5,8
M_BBS#[1..0] 5,8
M_AWE# 5,8
M_ACAS# 5,8
M_ARAS# 5,8
M_BWE# 5,8
M_BCAS# 5,8
M_BRAS# 5,8
M_CS#0 5,8
M_CS#1 5,8
M_CS#2 5,8
M_CS#3 5,8
M_CKE#05,8
M_CKE#15,8
05/10 Remove the damping resistor for AMD suggest.
1 1
M_CKE#0 M_CKE#1
R60
1 2
121R3F
R61
1 2
121R3F
R62
1 2
121R3F
R63
1 2
121R3F
A
B
M_CLK7 M_CLK#7
M_CLK6 M_CLK#6
M_CLK5 M_CLK#5
M_CLK4 M_CLK#4
C
M_CLK7 5,8 M_CLK#7 5,8
M_CLK6 5,8 M_CLK#6 5,8
M_CLK5 5,8 M_CLK#5 5,8
M_CLK4 5,8 M_CLK#4 5,8
<Variant Name>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
A3
D
Date: Sheet
DDR DAMPING & TERMINATION
Bolsena
958Tuesday, December 28, 2004
E
of
SA
Place it near CPU
Page 10
A
B
C
D
E
4 4
2D5V_S3
1D25V_S3
12
12
C80 SCD1U
C81 SCD1U
12
C82 SCD1U
DY
12
12
C97 SCD1U
C98 SCD1U
12
C99 SCD1U
DY
3 3
2D5V_S3
1D25V_S3
12
C114 SCD1U
12
12
C122 SCD1U
C123 SCD1U
DY
12
C138 SCD1U
C139 SCD1U
C140 SCD1U
12
12
DY
2 2
LAYOUT:Place altemating caps to GND and 2D5_S3
12
C83 SCD1U
DY
12
C100 SCD1U
DY
12
C124 SCD1U
DY
12
C141 SCD1U
DY
12
12
C84 SCD1U
C85 SCD1U
12
C86 SCD1U
12
12
C87 SCD1U
C88 SCD1U
DY
12
12
12
C101
C102
SCD1U
SCD1U
C103 SCD1U
12
12
C104
C105
SCD1U
SCD1U
DY
C125 SCD1U
C126 SCD1U
C127 SCD1U
12
12
12
12
12
C128 SCD1U
C129 SCD1U
DY
12
12
C142
C143
SCD1U
SCD1U
12
12
C144 SCD1U
C145 SCD1U
12
C146 SCD1U
DY
12
12
C89 SCD1U
DY
12
C106 SCD1U
DY
12
C130 SCD1U
DY
12
C147 SCD1U
DY
12
12
C90 SCD1U
C91 SCD1U
C92 SCD1U
12
C93 SCD1U
DY
12
12
12
C107
C108
SCD1U
SCD1U
C109 SCD1U
12
C110 SCD1U
DY
12
12
C131
C132
SCD1U
SCD1U
12
12
C133 SCD1U
C134 SCD1U
DY
12
12
C148
C149
SCD1U
SCD1U
12
12
C150 SCD1U
C151 SCD1U
DY
12
12
C94 SCD1U
C95 SCD1U
12
C96 SCD1U
DY
12
12
C111 SCD1U
C112 SCD1U
12
C113 SCD1U
DY
12
C135 SCD1U
C136 SCD1U
C137 SCD1U
12
12
DY
12
12
12
C153 SCD1U
C154 SCD1U
C152 SCD1U
1D25V_S3
12
DY
C115 SCD1U
12
12
12
C116 SCD1U
DY
DY
C117 SCD1U
12
C118 SCD1U
DY
DY
C119 SCD1U
12
12
C120
C121
SCD1U
SCD1U
DY
DY
DY
LAYOUT:Place close to Power Pin of DDR socket.
LAYOUT:Place at end of the DIMMs
1D25V_S3
12
TC2 ST100U4VBM-U
12
TC3 ST100U4VBM-1
12
C157 SC22U10V6ZY-U
12
C158 SC22U10V6ZY-U
12
C159 SC22U10V6ZY-U
12
C160 SC22U10V6ZY-U
2D5V_S3 2D5V_S3
C155
1 2
SCD22U16V3ZY C161
1 2
SCD22U16V3ZY C163
1 2
DY
SCD22U16V3ZY C165
1 2
DY
SCD22U16V3ZY C167
1 2
SCD22U16V3ZY
1 2
1 2
1 2
DY
1 2
DY
1 2
C156 SCD22U16V3ZY
C162 SCD22U16V3ZY
C164 SCD22U16V3ZY
C166 SCD22U16V3ZY
C168 SCD22U16V3ZY
0.22u x 10
1 1
A
B
C
D
<Variant Name>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
A3
Date: Sheet of
DDR DECOUPLING
Bolsena
E
10 58Tuesday, December 28, 2004
SA
Page 11
A
4 4
B
C
D
E
CLAW HAMMER TO NB NB TO CLAW HAMMER
CPUCADOUT[15..0]4 CPUCADOUTJ[15..0]4
3 3
1D2V_S0
12
2 2
AROUND NB
C169 SCD1U16V
DY
12
C170 SCD1U16V
CPUHTTCLKOUT14 CPUHTTCLKOUTJ14
CPUHTTCLKOUT04 CPUHTTCLKOUTJ04
CPUHTTCTLOUT04 CPUHTTCTLOUTJ04
1D2V_HT0A_S0
1 2 1 2
CPUCADOUT15 CPUCADOUTJ15 CPUCADOUT14 CPUCADOUTJ14 CPUCADOUT13 CPUCADOUTJ13 CPUCADOUT12 CPUCADOUTJ12 CPUCADOUT11 CPUCADOUTJ11 CPUCADOUT10 CPUCADOUTJ10 CPUCADOUT9 CPUCADOUTJ9 CPUCADOUT8 CPUCADOUTJ8
CPUCADOUT7 CPUCADOUTJ7 CPUCADOUT6 CPUCADOUTJ6 CPUCADOUT5 CPUCADOUTJ5 CPUCADOUT4 CPUCADOUTJ4 CPUCADOUT3 CPUCADOUTJ3 CPUCADOUT2 CPUCADOUTJ2 CPUCADOUT1 CPUCADOUTJ1 CPUCADOUT0 CPUCADOUTJ0
CPUHTTCLKOUT1 CPUHTTCLKOUTJ1
CPUHTTCLKOUT0 CPUHTTCLKOUTJ0
CPUHTTCTLOUT0 CPUHTTCTLOUTJ0
R64 49D9R2F
R65 49D9R2F
HT_RXCALN HT_RXCALP
W25
W24 AA25 AA24 AB26 AA26 AC25 AC24 AD26 AC26
W30
AB29 AA29 AC29 AC28
W26
W29
W28
T26 R26 U25 U24 V26 U26
R29 R28 T30 R30 T28 T29 V29 U29 Y30
Y28 Y29
Y26
P29 N29
D27 E27
U4A
HT_RXCAD15P HT_RXCAD15N HT_RXCAD14P HT_RXCAD14N HT_RXCAD13P HT_RXCAD13N HT_RXCAD12P HT_RXCAD12N HT_RXCAD11P HT_RXCAD11N HT_RXCAD10P HT_RXCAD10N HT_RXCAD9P HT_RXCAD9N HT_RXCAD8P HT_RXCAD8N
HT_RXCAD7P HT_RXCAD7N HT_RXCAD6P HT_RXCAD6N HT_RXCAD5P HT_RXCAD5N HT_RXCAD4P HT_RXCAD4N HT_RXCAD3P HT_RXCAD3N HT_RXCAD2P HT_RXCAD2N HT_RXCAD1P HT_RXCAD1N HT_RXCAD0P HT_RXCAD0N
HT_RXCLK1P HT_RXCLK1N
HT_RXCLK0P HT_RXCLK0N
HT_RXCTLP HT_RXCTLN
HT_RXCALN HT_RXCALP
RS480M-U
PART 1OF6
HYPER TRANSPORT CPU I/F
HT_TXCAD15P HT_TXCAD15N HT_TXCAD14P HT_TXCAD14N HT_TXCAD13P HT_TXCAD13N HT_TXCAD12P HT_TXCAD12N HT_TXCAD11P HT_TXCAD11N HT_TXCAD10P HT_TXCAD10N
HT_TXCAD9P HT_TXCAD9N HT_TXCAD8P HT_TXCAD8N
HT_TXCAD7P HT_TXCAD7N HT_TXCAD6P HT_TXCAD6N HT_TXCAD5P HT_TXCAD5N HT_TXCAD4P HT_TXCAD4N HT_TXCAD3P HT_TXCAD3N HT_TXCAD2P HT_TXCAD2N HT_TXCAD1P HT_TXCAD1N HT_TXCAD0P HT_TXCAD0N
HT_TXCLK1P HT_TXCLK1N
HT_TXCLK0P HT_TXCLK0N
HT_TXCTLP HT_TXCTLN
HT_TXCALP
HT_TXCALN
R24 R25 N26 P26 N24 N25 L26 M26 J26 K26 J24 J25 G26 H26 G24 G25
L30 M30 L28 L29 J29 K29 H30 H29 E29 E28 D30 E30 D28 D29 B29 C29
L24 L25
F29 G29
M29 M28
B28 A28
NB0CADOUT15 NB0CADOUTJ15 NB0CADOUT14 NB0CADOUTJ14 NB0CADOUT13 NB0CADOUTJ13 NB0CADOUT12 NB0CADOUTJ12 NB0CADOUT11 NB0CADOUTJ11 NB0CADOUT10 NB0CADOUTJ10 NB0CADOUT9 NB0CADOUTJ9 NB0CADOUT8 NB0CADOUTJ8
NB0CADOUT7 NB0CADOUTJ7 NB0CADOUT6 NB0CADOUTJ6 NB0CADOUT5 NB0CADOUTJ5 NB0CADOUT4 NB0CADOUTJ4 NB0CADOUT3 NB0CADOUTJ3 NB0CADOUT2 NB0CADOUTJ2 NB0CADOUT1 NB0CADOUTJ1 NB0CADOUT0 NB0CADOUTJ0
NB0HTTCLKOUT1 NB0HTTCLKOUTJ1
NB0HTTCLKOUT0 NB0HTTCLKOUTJ0
NB0HTTCTLOUT NB0HTTCTLOUTJ
HT_TXCALP HT_TXCALN
1 2
NB0CADOUT[15..0] 4 NB0CADOUTJ[15..0] 4
NB0HTTCLKOUT1 4 NB0HTTCLKOUTJ 1 4
NB0HTTCLKOUT0 4 NB0HTTCLKOUTJ 0 4
NB0HTTCTLOUT 4 NB0HTTCTLOUTJ 4
R66 100R2F
1 1
A
B
C
D
<Variant Name>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
A3
Date: Sheet
ATI-RS480M (1 of 4) HT
Bolsena
11 58Tuesday, December 28, 2004
E
of
SA
Page 12
A
B
C
D
E
PEG_TXP[15..0]49 PEG_TXN[15..0]49
PEG_RXP[15..0]49 PEG_RXN[15..0]49
D8 D7 D5 D4 E4 F4 G5 G4 H4
H5 H6 G1 G2 K5 K4
M4
N5 N4 P4 R4 P5 P6 P2 R2 T5 T4 U4
V4 W1 W2
AE1 AE2
AB2 AC2
AB5 AB4
Y4
AA4
AG1 AH1
AC5 AC6
AH3
AJ3
DVO_MDA5215 DVO_MDA4915 DVO_MDA5015 DVO_MDA5115 DVO_MDA3915 DVO_MDA4815 DVO_MDA3815 DVO_MDA3715 DVO_MDA3615 DVO_MDA3515 DVO_MDA3415 DVO_MDA3315
DVO_MDA5315 DVO_MDA5415
DVO_MDA5515
U4B
GFX_RX0P GFX_RX0N GFX_RX1P GFX_RX1N GFX_RX2P GFX_RX2N GFX_RX3P GFX_RX3N GFX_RX4P
J4
GFX_RX4N GFX_RX5P GFX_RX5N GFX_RX6P GFX_RX6N GFX_RX7P GFX_RX7N
L4
GFX_RX8P GFX_RX8N GFX_RX9P GFX_RX9N GFX_RX10P GFX_RX10N GFX_RX11P GFX_RX11N GFX_RX12P GFX_RX12N GFX_RX13P GFX_RX13N GFX_RX14P GFX_RX14N GFX_RX15P GFX_RX15N
GPP_RX0P/SB_RX2P GPP_RX0N/SB_RX2N
GPP_RX1P/SB_RX3P GPP_RX1N/SB_RX3N
GPP_RX2P GPP_RX2N
GPP_RX3P GPP_RX3N
SB_RX0P SB_RX0N
SB_RX1P SB_RX1N
PCE_ISET PCE_TXISET
RS480M-U
PART 2 OF 6
GPP_TX0P/SB_TX2P GPP_TX0N/SB_TX2N
GPP_TX1P/SB_TX3P GPP_TX1N/SB_TX3N
PCIE I/F TO VIDEO
PCIE I/F TO SLOT
PCIE I/F TO SB
DVO_MDA52 DVO_MDA49 DVO_MDA50 DVO_MDA51 DVO_MDA39 DVO_MDA48 DVO_MDA38 DVO_MDA37 DVO_MDA36 DVO_MDA35 DVO_MDA34 DVO_MDA33
DVO_MDA53 DVO_MDA54
DVO_MDA55
GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N GFX_TX8P GFX_TX8N GFX_TX9P
GFX_TX9N GFX_TX10P GFX_TX10N GFX_TX11P GFX_TX11N GFX_TX12P GFX_TX12N GFX_TX13P GFX_TX13N GFX_TX14P GFX_TX14N GFX_TX15P GFX_TX15N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
SB_TX0P SB_TX0N
SB_TX1P SB_TX1N
PCE_PCAL
PCE_NCAL
A7 B7 B6 B5 A5 A4 B3 B2 C1 D1 D2 E2 F2 F1 H2 J2 J1 K1 K2 L2 M2 M1 N1 N2 R1 T1 T2 U2 V2 V1 Y2 AA2
AD2 AD1
AA1 AB1
Y5 Y6
W5 W4
AF2 AG2
AC4 AD4
AH2 AJ2
4 4
3 3
1D8V_S0
12
12
R67 1KR2F
MEM_VREF
R68 1KR2F
IDCKP15
IDCKN15
Connect MEM_VREF to VDD_MEM/2 PA_RS480F1.PDF
1D8V_S0
12
C213 SC1U10V3KX
MEM_CAP1 MEM_CAP2
MEM_VREF MPVDD_PLL
C212
2 2
1D8V_S0
1 2 1 2
DY DY
1 2
SCD47U16V3ZY
C211 SCD47U16V3ZY
L5 0R5J-1
AF17 AK17 AH16
AF16
AJ22
AJ21 AH20 AH21 AK19 AH19
AJ17 AG16 AG17 AH17
AJ18 AG26
AJ29 AE21 AH24 AH12 AG13
AH8 AE8
AF25 AH30 AG20
AJ25 AH13
AF14
AG8
AG25 AH29
AF21 AK25
AJ12
AF13
AK7 AF9
AE17 AH18 AE18
AJ19
AF18 AK16
AJ16
AE28
AJ20
AK20
AJ15
AJ14
AJ7
AJ4
U4C
MEM_A0 MEM_A1 MEM_A2 MEM_A3 MEM_A4 MEM_A5 MEM_A6 MEM_A7 MEM_A8 MEM_A9 MEM_A10 MEM_A11 MEM_A12 MEM_A13 MEM_A14
MEM_DM0 MEM_DM1 MEM_DM2 MEM_DM3 MEM_DM4 MEM_DM5 MEM_DM6 MEM_DM7
MEM_DQS0P MEM_DQS1P MEM_DQS2P MEM_DQS3P MEM_DQS4P MEM_DQS5P MEM_DQS6P MEM_DQS7P
MEM_DQS0N MEM_DQS1N MEM_DQS2N MEM_DQS3N MEM_DQS4N MEM_DQS5N MEM_DQS6N MEM_DQS7N
MEM_RAS# MEM_CAS# MEM_WE# MEM_CS# MEM_CKE
MEM_CKP MEM_CKN
MEM_CAP1 MEM_CAP2
MEM_VMODE
MEM_VREF MPVDD
MPVSS
RS480M-U
PART 3 OF 6
MEM_A I/F
MEM_DQ0 MEM_DQ1 MEM_DQ2 MEM_DQ3 MEM_DQ4 MEM_DQ5 MEM_DQ6 MEM_DQ7 MEM_DQ8
MEM_DQ9 MEM_DQ10 MEM_DQ11 MEM_DQ12 MEM_DQ13 MEM_DQ14 MEM_DQ15 MEM_DQ16 MEM_DQ17 MEM_DQ18 MEM_DQ19 MEM_DQ20 MEM_DQ21 MEM_DQ22 MEM_DQ23 MEM_DQ24 MEM_DQ25 MEM_DQ26 MEM_DQ27 MEM_DQ28 MEM_DQ29 MEM_DQ30 MEM_DQ31 MEM_DQ32 MEM_DQ33 MEM_DQ34 MEM_DQ35 MEM_DQ36 MEM_DQ37 MEM_DQ38 MEM_DQ39 MEM_DQ40 MEM_DQ41 MEM_DQ42 MEM_DQ43 MEM_DQ44 MEM_DQ45 MEM_DQ46 MEM_DQ47 MEM_DQ48 MEM_DQ49 MEM_DQ50 MEM_DQ51 MEM_DQ52 MEM_DQ53 MEM_DQ54 MEM_DQ55 MEM_DQ56 MEM_DQ57 MEM_DQ58 MEM_DQ59 MEM_DQ60 MEM_DQ61 MEM_DQ62 MEM_DQ63
MEM_COMPP MEM_COMPN
AF28 AF27 AG28 AF26 AE25 AE24 AF24 AG23 AE29 AF29 AG30 AG29 AH28 AJ28 AH27 AJ27 AE23 AG22 AF23 AF22 AE20 AG19 AF20 AF19 AH26 AJ26 AK26 AH25 AJ24 AH23 AJ23 AH22 AK14 AH14 AK13 AJ13 AJ11 AH11 AJ10 AH10 AE15 AF15 AG14 AE14 AE12 AF12 AG11 AE11 AJ9 AH9 AJ8 AK8 AH7 AJ6 AH6 AJ5 AG10 AF11 AF10 AE9 AG7 AF8 AF7 AE7
AH5 AD30
LANE REVERSE
DVO_MDA33 DVO_MDA34 DVO_MDA35 DVO_MDA36 DVO_MDA37 DVO_MDA38 DVO_MDA39
DVO_MDA48 DVO_MDA49 DVO_MDA50 DVO_MDA51 DVO_MDA52 DVO_MDA53 DVO_MDA54 DVO_MDA55
MEM_COMPP MEM_COMPN
DY DY
DO NOT SUPPORT SIDEPORT MEMORY DUMMY IT
1 2 1 2
PCIE_RX0P_SB18 PCIE_RX0N_SB18
PCIE_RX1P_SB18 PCIE_RX1N_SB18
1 2 1 2
R74 60D4R2F
R75 60D4R2F
PEG_TXP15 PEG_TXN15 PEG_TXP14 PEG_TXN14 PEG_TXP13 PEG_TXN13 PEG_TXP12 PEG_TXN12 PEG_TXP11 PEG_TXN11 PEG_TXP10 PEG_TXN10 PEG_TXP9 PEG_TXN9 PEG_TXP8 PEG_TXN8 PEG_TXP7 PEG_TXN7 PEG_TXP6 PEG_TXN6 PEG_TXP5 PEG_TXN5 PEG_TXP4 PEG_TXN4 PEG_TXP3 PEG_TXN3 PEG_TXP2 PEG_TXN2 PEG_TXP1 PEG_TXN1 PEG_TXP0 PEG_TXN0
PCIE_RXP057
PCIE_RXN057
PCIE_RXP157
PCIE_RXN157
R69 10KR2
R70 10KR2
2D5V_S3
PCE_ISET PCE_TXISET
When disable local frame buffer, VDD_MEM connect to 2D5V_S3,
1 1
MEM_VMODE connect to GND, MEM_VREF connect to 2D5V_S3, MPVDD connected to 1D8V
?CHECK THESE PINS
DSG-215-RS480-04.PDF
A
B
C
?PLACE THESE CAP CLOSE TO CONNECTOR
PEG_RXP15_NB PEG_RXP15 PEG_RXP14_NB PEG_RXP13_NB
PEG_RXN13_NB PEG_RXP12_NB PEG_RXN12_NB PEG_RXP11_NB PEG_RXN11_NB PEG_RXP10_NB PEG_RXN10_NB PEG_RXP9_NB PEG_RXN9_NB PEG_RXP8_NB PEG_RXN8_NB PEG_RXP7_NB PEG_RXN7_NB PEG_RXP6_NB PEG_RXN6_NB PEG_RXP5_NB PEG_RXN5_NB PEG_RXP4_NB PEG_RXN4_NB PEG_RXP3_NB PEG_RXN3_NB PEG_RXP2_NB PEG_RXN2_NB PEG_RXP1_NB PEG_RXN1_NB PEG_RXP0_NB PEG_RXN0_NB
PCIE_TXP0_NB PCIE_TXN0_NB
PCIE_TXP1_NB PCIE_TXN1_NB
?NEED STRAP FOR MULTI PIN?
D
SB_TX0P SB_TX0N
SB_TX1P SB_TX1N
PCE_PCAL PCE_NCAL
1 2 1 2
1 2 1 2
1 2 1 2
<Variant Name>
Title
Size Document Number Rev
Date: Sheet
C171
1 2
SCD1U16V
C173
1 2
SCD1U16V
C172
1 2
SCD1U16V
C174
1 2
SCD1U16V
C176
1 2
SCD1U16V
C175
1 2
SCD1U16V
C177
1 2
SCD1U16V
C179
1 2
SCD1U16V
C178
1 2
SCD1U16V
C180
1 2
SCD1U16V
C181
1 2
SCD1U16V
C182
1 2
SCD1U16V
C183
1 2
SCD1U16V
C184
1 2
SCD1U16V
C185
1 2
SCD1U16V
C187
1 2
SCD1U16V
C186
1 2
SCD1U16V
C188
1 2
SCD1U16V
C189
1 2
SCD1U16V
C191
1 2
SCD1U16V
C190
1 2
SCD1U16V
C192
1 2
SCD1U16V
C194
1 2
SCD1U16V
C193
1 2
SCD1U16V
C195
1 2
SCD1U16V
C197
1 2
SCD1U16V
C196
1 2
SCD1U16V
C198
1 2
SCD1U16V
C200
1 2
SCD1U16V
C199
1 2
SCD1U16V
C202
1 2
SCD1U16V
C201
1 2
SCD1U16V
C203
1 2
SCD1U16V
C204
1 2
SCD1U16V C205
1 2
SCD1U16V
C206
1 2
SCD1U16V
Dummy when no EZ4
C207 SCD1U16V
C208 SCD1U16V C209 SCD1U16V
C210 SCD1U16V
R71 150R2
R72 100R2
ATI-RS480M (2 of 4) PCIE
A3
PEG_RXN15PEG_RXN15_NB PEG_RXP14 PEG_RXN14PEG_RXN14_NB PEG_RXP13 PEG_RXN13 PEG_RXP12 PEG_RXN12 PEG_RXP11 PEG_RXN11 PEG_RXP10 PEG_RXN10 PEG_RXP9 PEG_RXN9 PEG_RXP8 PEG_RXN8 PEG_RXP7 PEG_RXN7 PEG_RXP6 PEG_RXN6 PEG_RXP5 PEG_RXN5 PEG_RXP4 PEG_RXN4 PEG_RXP3 PEG_RXN3 PEG_RXP2 PEG_RXN2 PEG_RXP1 PEG_RXN1 PEG_RXP0 PEG_RXN0
Dummy when use UMA
PCIE_TXP0 57 PCIE_TXN0 57
PCIE_TXP1 57 PCIE_TXN1 57
PCIE_TX0P_SB 18 PCIE_TX0N_SB 18
PCIE_TX1P_SB 18 PCIE_TX1N_SB 18
1D2V_S0
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Bolsena
12 58Tuesday, December 28, 2004
E
LANE REVERSE
SA
of
Page 13
A
1D8V_S0
1 2
4 4
3 3
1D8V_S0
2 2
AVDDQ
R76 0R3-U
12
C214
DY
R93
1 2
BLM11A121S
12
R96 4K7R2
NB_SUS_STAT#
12
SC10U10V5ZY
C215
SCD1U16V
1D8V_S0
HTPVDD
12
C225 SC10U10V5ZY
UMA_CRMA57
UMA_LUMA57
UMA_COMP57
UMA_R57 UMA_G57 UMA_B57
R88
1 2
BLM11A121S
12
C227 SCD1U16V
12
12
C228 SCD1U16V
1 2
1D8V_S0
R287
R285
R288
150R2F
150R2F
150R2F
1 2
1 2
1 2
Dummy when use Discrete
PLVDD
12
12
C218 SC10U10V5ZY
3D3V_S01D8V_S0
R101 0R2-0
C219
C221
SCD1U16V
SCD1U16V
12
C231 SC1U10V3ZY
3D3VDDR_S0
R95
1 2
0R3-U
DO NOT SUPPORT SIDEPORT MEMORY DO NOT SUPPORT SERIAL STRAP ROM DUMMY IT
DY
3D3V_S5
U5A
ALL_PWROK39
LDT_RST#
1 1
LPC_RST#18,37
A
147
1 2
3
TSLCX08MTC-U
R112
1 2
33R2
AG_RST# 34,49
RS480_RST#
1 2
R292
150R2F
1 2
1 2
1 2
B
AVDD3D3V_S0
R77
1 2
0R3-U
12
C216 SC1U10V3ZY
C220 SC1U10V3ZY
LDT_STP#6,18 ALLOW_LDTSTOP18
RN102
SRN10KJ
LVDS_DIGON
1D8VAVDDD1_S0
14 2
R78
0R3-U
12
C217 SC1U10V3ZY
AVDDQ
R294
R293
CLK14_NB3 SB_OSC_INT21
VGA_SMB_CLK15,49,54 VGA_SMB_DAT49,54
NB_PWRGD
C233 DUMMY-C3
12
DY DY DY
3
LVDS_BLON
150R2F
150R2F
UMA_CRT_DDC_C16 UMA_CRT_DDC_D16
Use CLK GEN REF 14.318M CLK to SB OSCIN DUMMY IT
3D3V_S0
12
B
NB_PWRGD39
1 2
1 2
R828
12
3KR2F
R578
12
3KR2F
R577
12
3KR2F
BMREQ#18
DY
R90 715R3F
12
R97 22R2
TP50 TPAD28
4 5
R113 1KR2
3D3V_S5
UMA_VS16 UMA_HS16
RS480_RST#
NB_SUS_STAT#
NB_OSC_OUT
DFT_GPIO0 DFT_GPIO2
147
3D3V_S5
12 13
C
IRSET_NB
1 2
U5B
6
TSLCX08MTC-U
147
C
B27 C27 D26 D25 C24
B24
E24 D24
B25
A25
A24 C25
A26
B26
A11
B11 C26
E11
F11
A14
B14 M23
L23
D14
B15
B12 C12 AH4
H13 H12
A13
B13
B9
F12
E13 D13
F10 C10 C11 AF4 AE4
R106 0R2-0
DY
U5D
11
TSLCX08MTC-U
U4D
AVDD1 AVDD2 AVSSN1 AVSSN2 AVDDDI AVSSDI
AVDDQ AVSSQ
C Y COMP
RED GREEN BLUE
DAC_VSYNC DAC_HSYNC RSET DAC_SCL DAC_SDA
PLLVDD PLLVSS
HTPVDD HTPVSS
SYSRESET# POWERGOOD LDTSTOP# ALLOW_LDTSTOP SUS_STAT#
VDDR3_1 VDDR3_2
OSCIN OSCOUT
TVCLKIN
DFT_GPIO0/RSV DFT_GPIO1/RSV DFT_GPIO2/RSV
BMREQb I2C_CLK I2C_DATA THERMALDIODE_P THERMALDIODE_N
RS480M-U
LCDVDD_ON
R114
1 2
PART 4 OF 6
CRT/TVOUT
PLL PWR
PM
CLOCKs
MIS.
0R2-0
UMA
TXOUT_U0P TXOUT_U0N TXOUT_U1P TXOUT_U1N TXOUT_U2P TXOUT_U2N TXOUT_U3P TXOUT_U3N
TXOUT_L0P TXOUT_L0N TXOUT_L1P TXOUT_L1N TXOUT_L2P TXOUT_L2N TXOUT_L3P TXOUT_L3N
TXCLK_UP TXCLK_UN
TXCLK_LP
LVDS
TXCLK_LN
LVDDR18D LVDDR18A_1 LVDDR18A_2
LVSSR1 LVSSR2 LVSSR3 LVSSR4 LVSSR5 LVSSR6 LVSSR7 LVSSR8
LVDS_DIGON
LVDS_BLON LVDS_BLEN
GFX_CLKP
GFX_CLKN
HTTSTCLK
HTREFCLK
SB_CLKP SB_CLKN
DFT_GPIO3/RSV DFT_GPIO4/RSV DFT_GPIO5/RSV
TMDS_HPD
STRP_DATA
DDC_DATA TESTMODE
VCC_CORE_S0
BL_ON 34,49
RESISTOR
R503 R504
LPVDD
LPVSS
DY
12
12
D
D18 C18 B19 A19 D19 C19
TXBOUT3+
D20
TXBOUT3-
C20 B16
A16 D16 C16 B17 A17
TXAOUT3+
E17
TXAOUT3-
D17 B20
A20 B18 C17
E18 F17 E19 G20 H20
G19 E20 F20 H18 G18 F19 H19 F18
E14 F14 F13
B8 A8
HTTST_CLK
P23 N23
E8 E7
C13 C14 C15
A10 E10
DDC_DATA
B10
TESTMODE_NB
E12
R107 DUMMY-R2
R110 4K7R2
RS480M MODE
TEST MODE
NORMAL MODE
D
TXBOUT0+ TXBOUT0­TXBOUT1+ TXBOUT1­TXBOUT2+ TXBOUT2-
TXAOUT0+ TXAOUT0­TXAOUT1+ TXAOUT1­TXAOUT2+ TXAOUT2-
TXBCLK+ TXBCLK­TXACLK+ TXACLK-
LVDS_DIGON LVDS_BLON LVDS_BLEN_NB
DFT_GPIO3 DFT_GPIO4DFT_GPIO1 DFT_GPIO5
TP45 TPAD30
TP46 TPAD30
1 2
DDC_DATA 15
E
TXACLK+ TXACLK­TXAOUT2+ TXAOUT2-
TXAOUT1+ TXAOUT1­TXAOUT0+ TXAOUT0-
TXBOUT1+ TXBOUT1­TXBOUT0+ TXBOUT0-
TXBCLK+ TXBCLK­TXBOUT2+ TXBOUT2-
LCDVDD_ON
6 7 8
6 7 8
6 7 8
6 7 8
RN120
RN121
RN122
RN123
R818
12
0R2-0
45 3 2 1
SRN0-1-U
45 3 2 1
SRN0-1-U
45 3 2 1
SRN0-1-U
45 3 2 1
SRN0-1-U
LCD_TXACLK+ 17,54
LCD_TXACLK- 17,54
LCD_TXAOUT2+ 17,54
LCD_TXAOUT2- 17,54
LCD_TXAOUT1+ 17,54
LCD_TXAOUT1- 17,54
LCD_TXAOUT0+ 17,54
LCD_TXAOUT0- 17,54
LCD_TXBOUT1+ 17,54
LCD_TXBOUT1- 17,54
LCD_TXBOUT0+ 17,54
LCD_TXBOUT0- 17,54
LCD_TXBCLK+ 17,54
LCD_TXBCLK- 17,54
LCD_TXBOUT2+ 17,54
LCD_TXBOUT2- 17,54
LCD_VDD_ON 17,54
Dummy when use Discrete
TP47 TPAD30
TP48 TPAD30
1D8VLPVDD_S0
LVDDR18D_S0
LVDDR18A_S0
TP49 TPAD30
NBSRC_CLK 3 NBSRC_CLK# 3
R98 10KR2
HTREF_CLK 3 SBLINK_CLK 3
SBLINK_CLK# 3
DY DY DY
TMDS_UMA_HPD 15
TP52 TPAD28
R825
12
3KR2F R826
12
3KR2F R827
12
3KR2F
<Variant Name>
Title
Size Document Number Rev
Date: Sheet
ATI-RS480M (3 of 4) LVDS CRT
A3
12
C222 SC1U10V3ZY
12
C224 SC1U10V3ZY
12
12
C229 SC1U10V3ZY
DISABLE DEBUG MODE DUMMY IT
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Bolsena
12
12
C230 SCD1U16V
E
C223 SCD1U16V
C226 SCD1U16V
13 58Tuesday, December 28, 2004
1 2
1 2
1 2
of
1D8V_S0
R87 BLM11A121S
R92 BLM11A121S
R94 BLM11A121S
SA
Page 14
A
B
C
D
E
VSS89
H17
H10
H16
H14
E16
D10
E15
F15
U15
V14
R15
T14
N15
V12
N13
P14
U17
T16
R17
P12
T12
R13
W13
W17
P18
V18
M18
U13
N17
W15
V16
T18
M14
M12
M16
P16
U19
AC16
AG18
AC23
AD8
AD11
AD13
AD16
AD19
AD23
AG5
AG6
AG21
AD17
AG15
AG12
AF30
AG24
AG9
AC19
AG27
AC11
AD7
AJ30
AC21
AK5
AK10
AC13
AD21
AK22
AK29
W19
AE26
AE27
T27
R27
AD28
F24
F27
G28
U4F
4 4
VSS108
VSS109
VSS110
VSS111
VSS112
VSS104
VSS105
VSS106
VSS107
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS44
VSS45
VSS46
VSS47
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS30
D15
AD9
G11
F16
G30
AB28
AB25
D12
AD24
AA28
G17
Y23
AC9
R19
Y27
C28
G16
F25
B30
T24
F26
W27
D11
H11
AD25
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
Y24
G13
VSS8
VSS9
VSS10E9VSS11
VSS12D9VSS13
VSS14
G14
G15
VSS7
AC27
VSS6
AD27
VSS5
AD29
VSS4
G12
VSS3
G10
VSS2
VSS1
RS480M-U
PAR 6 OF 6
GROUND
VSSA1
VSSA2
VSSA3
VSSA4N3VSSA5F7VSSA6F5VSSA7R3VSSA8
VSSA22A2VSSA23
VSSA24P8VSSA25J6VSSA26C8VSSA27
VSSA28V8VSSA29F3VSSA30
VSSA31
VSSA32M5VSSA33
VSSA34G3VSSA35B4VSSA36P7VSSA37
VSSA38C9VSSA39C7VSSA40J5VSSA41R6VSSA42J3VSSA43
VSSA44D6VSSA45C4VSSA46K3VSSA47
VSSA48T7VSSA49Y7VSSA50
12
12
12
12
VSSA51K7VSSA52H7VSSA53M3VSSA54V6VSSA55H8VSSA56C2VSSA57
AD6
C240 SCD1U16V
C247 SCD1U16V
12
C273 SCD1U16V
DY
12
C287 SCD1U16V
AB8
12
C256 SCD1U16V
12
C264 SCD1U16V
C274 SCD1U16V
C288 SCD1U16V
AD5
12
L6
1 2
MLB-201209-11
12
C275 SCD1U16V
DY
12
C289 SCD1U16V
AA5
C257 SC22U10V6ZY-U
1D8V_S0
12
D
AB7
1D2V_S0
C276 SCD1U16V
AF3
AE3
AA3
AB3
AD3
VSSA22
<Variant Name>
Title
Size Document Number Rev
Date: Sheet of
ATI-RS480M (4 of 4) PWR, GND
A3
VSSA58L6VSSA59
12
C238 SCD1U16V
12
C263 SCD1U16V
12
C270 SC22U10V6ZY-U
12
C277 SC22U10V6ZY-U
DY
VSSA60M7VSSA61V7VSSA62F6VSSA63E6VSSA64U5VSSA65U6VSSA66E5VSSA67L5VSSA68
VSSA59
12
12
AJ1
12
12
AG3
C239 SCD1U16V
C246 SCD1U16V
C272 SCD1U16V
C286 SCD1U16V
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
F28
T8
12
C255 SC1U10V3KX
1D8V_VDDA
12
C262 SC1U10V3KX
1D2V_S0
C
N28
H24
M27
H9 AA7 G9 U8 N7 N8 U7 F9 AA8 G8 G7 J8 J7 B1 AG4 R8 AC8 AC7 AF6 AE6 L8 W8 W7 L7 R7 AF5 AK2 N16 M13 M15 W16 N18 P19 N12 P15 N14 M17 T19 G22 R12 P13 R14 V19 R18 U16 U12 T13 U14 T17 U18 E22 R16 V13 T15 P17 W18 D22 W12 V15 W14 V17 M19 H22 H21 D21
K28
N19
VDDA12_13
VDDA18_13
M24
H28
P25
P28
E26
K25
V25
V28
U28
R23
1D2V_S0
12
C236 SCD1U16V
12
C244 SCD1U16V
12
C250 SCD1U16V
12
C283 SCD1U16V
1D8VDD_S0
12
C290 SCD1U16V
12
R119 0R5J-1
12
C237 SCD1U16V
12
C245 SCD1U16V
12
C251 SCD1U16V
12
C284 SCD1U16V
12
C291
C292
SCD1U16V
SCD1U16V
1D8V_S0
12
12
12
C293 SC1U10V3KX
1D2V_HT0A_S0
C271
SCD1U16V
C285 SCD1U16V
1D2V_S0
VDDHT30 VDDHT31
B
N27 U27 V27 G27 V24 H27 K24
AB24
P27
AA27
K27
P24 AB27 AB23
V23
G23
E23
W23
K23
H23
U23 AA23
D23
C23
B23
A23
A29 AC30
AK23 AK28 AK11
AK4 AE30 AC14 AD12 AC18 AC20 AD10 AD14 AD15 AD20 AC10 AD18 AC12 AD22 AC22 AH15
H15 AC17 AC15
B21
C21
A22
B22
C22
E21
G21
J27
J23
F23
F21 F22
U4E
RS480M-U
VDD_HT1 VDD_HT2 VDD_HT3 VDD_HT4 VDD_HT5 VDD_HT6 VDD_HT7 VDD_HT8 VDD_HT9 VDD_HT10 VDD_HT11 VDD_HT12 VDD_HT13 VDD_HT14 VDD_HT15 VDD_HT16 VDD_HT17 VDD_HT18 VDD_HT19 VDD_HT20 VDD_HT21 VDD_HT22 VDD_HT23 VDD_HT24 VDD_HT25 VDD_HT26 VDD_HT27 VDD_HT28 VDD_HT29 VDD_HT30 VDD_HT31
VDD_MEM1 VDD_MEM2 VDD_MEM3 VDD_MEM4 VDD_MEM5 VDD_MEM6 VDD_MEM7 VDD_MEM8 VDD_MEM9 VDD_MEM10 VDD_MEM11 VDD_MEM12 VDD_MEM13 VDD_MEM14 VDD_MEM15 VDD_MEM16 VDD_MEM17 VDD_MEM18 VDD_MEMCK
VDD_18_1 VDD_18_2 VDD_18_3
VDD_CORE47 VDD_CORE46 VDD_CORE45 VDD_CORE44 VDD_CORE43 VDD_CORE42 VDD_CORE41 VDD_CORE40 VDD_CORE39
PART 5 OF 6
VDDA_12_14
VDDA_12_1 VDDA_12_2 VDDA_12_3 VDDA_12_4 VDDA_12_5 VDDA_12_6 VDDA_12_7 VDDA_12_8
VDDA_12_9 VDDA_12_10 VDDA_12_11 VDDA_12_12 VDDA_12_13
VDDA_18_1
VDDA_18_2
VDDA_18_3
VDDA_18_4
VDDA_18_5
VDDA_18_6
VDDA_18_7
VDDA_18_8
VDDA_18_9 VDDA_18_10 VDDA_18_11 VDDA_18_12 VDDA_18_13 VDD_CORE1 VDD_CORE2 VDD_CORE3 VDD_CORE4 VDD_CORE5 VDD_CORE6 VDD_CORE7 VDD_CORE8 VDD_CORE9
VDD_CORE10 VDD_CORE11 VDD_CORE12 VDD_CORE13 VDD_CORE14 VDD_CORE15 VDD_CORE16 VDD_CORE17 VDD_CORE18 VDD_CORE19 VDD_CORE20 VDD_CORE21 VDD_CORE22 VDD_CORE23 VDD_CORE24 VDD_CORE25 VDD_CORE26 VDD_CORE27 VDD_CORE28 VDD_CORE29 VDD_CORE30 VDD_CORE31 VDD_CORE32 VDD_CORE33 VDD_CORE34 VDD_CORE35
POWER
VDD_CORE36 VDD_CORE37 VDD_CORE38
12
R117
12
C235 SCD1U16V
0R5J-1
C252 SCD1U16V
3 3
12
12
C234 SC22U10V6ZY-U
DY
12
12
C242 SCD1U16V
C243 SCD1U16V
12
C241 SCD1U16V
12
12
12
12
C253 SCD1U16V
DY
12
C260 SCD1U16V
R118 0R5J-1
C254 SCD1U16V
C261 SCD1U16V
DY
2 2
1 1
3D3V_S0
12
C248 SC22U10V6ZY-U
12
C278 SCD1U16V
1D8V_S0
1 2
U7 BAV99-1
DY
12
12
3
C249 SCD1U16V
C279 SCD1U16V
1 2
12
C266 SCD1U16V
12
C280 SCD1U16V
DY
L7 BLM11A121S
1 2
DY
3
U8 BAV99-1
A
12
12
12
C267 SCD1U16V
12
C281 SCD1U16V
12
12
R120 0R2-0
DY
DY
C268 SCD1U16V
C282 SCD1U16V
DY
12
R121 0R2-0
J28
L27
T23
VSSA9T3VSSA10M6VSSA11C5VSSA12F8VSSA13M8VSSA14Y8VSSA15V3VSSA16C3VSSA17W3VSSA18K8VSSA19D3VSSA20C6VSSA21
V5
R5
VDDA12_13
VSSA22
VDDA18_13
VSSA59
VDDHT30
VSS30
VDDHT31
VSS89
E
AE5
14 58Tuesday, December 28, 2004
12
C258 SC4D7U10V5ZY
12
C259 SC4D7U10V5ZY
12
C265 SC4D7U10V5ZY
12
C269 SC4D7U10V5ZY
AA6
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Bolsena
SA
Page 15
A
B
C
D
E
3D3V_S0
2
14
RN93
4 4
To Discrete
RN91
SRN0-2-U
2 1
DIS_DVI_DDC_D49
DIS_DVI_DDC_C49
3 4
SRN10KJ
3
5 6
34 2 1
U24 2N7002DW
5V_S0
2
14
RN94
SRN10KJ
3
!DEL DVI_VCC
To EZ4 (5V level)
EZ4_DVI_DDC_D 57
EZ4_DVI_DDC_C 57
Dummy when use UMA
3D3V_S0
12
C296 SC2200P50V2KX
12
C305 SC10U10V5ZY
12
C306 SC10U10V5ZY
1 2
C297 SCD1U10V2MX
1 2
C303 SCD1U10V2MX
1 2
C307 SCD1U10V2MX
1 2
To UMA
DDC_DATA13
VGA_SMB_CLK13,49,54
3 3
2 2
3 4
RN41
SRN0-2-U
DY
2 1
3D3V_S0
R128
1 2
BLM11A121S
1 2
1 2
R130 BLM11A121S
R133 BLM11A121S
R126 BLM11A121S
12
C298 SC10U10V5ZY
12
C304 SC2200P50V2KX
12
C308 SC2200P50V2KX
EXT_SWING_1
12
C300
C299
SC2200P50V2KX
SCD1U10V2MX
1 2
3D3V_SII1162_VCC_S0
3D3V_SII1162_PVCC1_S0 3D3V_SII1162_PVCC2_S0
DVO_MDA5212 DVO_MDA4912 DVO_MDA5012 DVO_MDA5112 DVO_MDA3912 DVO_MDA4812 DVO_MDA3812 DVO_MDA3712 DVO_MDA3612 DVO_MDA3512 DVO_MDA3412 DVO_MDA3312
IDCKN12 IDCKP12
DVO_MDA5312
3D3V_S0
DVO_MDA5412 DVO_MDA5512
DVO_MDA52 DVO_MDA49 DVO_MDA50 DVO_MDA51 DVO_MDA39 DVO_MDA48 DVO_MDA38 DVO_MDA37 DVO_MDA36 DVO_MDA35 DVO_MDA34 DVO_MDA33
DVO_MDA53
1 2
DVO_MDA54 DVO_MDA55
R134 5K1R2
1 2
DY
1 2
TMDS_EZ4_TX0- 49,57
TMDS_EZ4_TX0+ 49,57
TMDS_EZ4_TX1- 49,57
TMDS_EZ4_TX1+ 49,57
TMDS_EZ4_TX2- 49,57 TMDS_EZ4_TX2+ 49,57 TMDS_EZ4_TXC- 49,57
TMDS_EZ4_TXC+ 49,57
U9
34
AVCC AVCC
VCC VCC
PVCC1 PVCC2
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
IDCK­IDCK+
DE CTL3/A2
HSYNC VSYNC
EDGE/HTPLG
ISEL/RST#
SDA/DK0 SCL/DK1
MSEN
PD#
VREF
EXT_SWING
TX0-
TX0+
TX1-
TX1+
TX2­TX2+ TXC-
TXC+
PGND PGND
GND GND GND GND
AGND AGND AGND
40 22
3
28 46
18 17 16 15 14 13 10
9 8 7 6 5
11 12
19 24
20 21
TMDS_UMA_HPD
44 25
DDC_DATA
26
VGA_SMB_CLK
27 48
47 2
EXT_SWING EXT_SWING_1
30
TMDS_UMA_TX0-
35
TMDS_UMA_TX0+
36
TMDS_UMA_TX1-
38
TMDS_UMA_TX1+
39 41 42 32 33
29 45
4 1 23 49
43 37 31
R131
1 2
5K1R2
R132
1 2
510R3
TMDS_UMA_TX2­TMDS_UMA_TX2+ TMDS_UMA_TXC­TMDS_UMA_TXC+
PCIRST_BUF# 18,26,2 8,29,31,34,57
2D5V_S3
RN100
1
8
2
7
3
6
4 5
RN101 SRN0-1-U
1
8
2
7
3
6
4 5
SRN0-1-U
DY
1 2
2D5V_S3
R127 1KR2
R129 1KR2
C301 SCD1U10V2MX
SII1162CS48
To Discrete
DVI_HPD49
TMDS_UMA_HPD13
To UMA & SiI1162
1 1
A
B
DY
R135
1 2
0R2-0
Dummy when use UMA
R137
1 2
0R2-0
Dummy when use Discrete
C
TMDS_HPD
C523 SCD1U10V2MX
1 2
R136
1 2
8K2R2
R139 8K2R2
1 2
<Variant Name>
Title
Size Document Number Rev
D
Date: Sheet of
Dummy when use Discrete
DVI_EZ4_HPD 57
Dummy when no EZ4
UMA DVI - SiI 1162
A3
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Bolsena
15 58Tuesday, December 28, 2004
E
SA
Page 16
A
CRT CONN
200mA Rating/Spec 500mA
5V_S0
4 4
DY DY
HSYNC_5_1
14
4
5 6
7
2 3
U10B
TSAHCT125
R144
UMA_HS13 UMA_VS13
1 2
R149
1 2
0R2-0 0R2-0
VSYNC_5_1
Dummy when use Discrete
R153 0R2-0
DIS_HS49 DIS_VS49
1 2
R158 0R2-0
1 2
U10A
14
1
HSYNC_5
TSAHCT125
7
VSYNC_5
Dummy when use UMA
B
To SYS and EZ4 CRT Both
SYS_HS
SYS_VS
1 2 1 2
Dummy when no EZ4
12
12
C309
C310
DUMMY-C2
DUMMY-C2
1 2
1 2
R146 33R2
R150 33R2
R154 0R2-0 R155 0R2-0
UMA_CRT_DDC_D13
UMA_CRT_DDC_C13
EZ4_HS 57
EZ4_VS 57
C
RN98
3 4
Dummy when use Discrete
DIS_CRT_DDC_D49
DIS_CRT_DDC_C49
SRN0-2-U
2
14
RN96
SRN10KJ
3
DY
CRT_DDC_D_1
2
CRT_DDC_C_1
1
RN97
SRN0-2-U
2 1
3 4
Dummy when use UMA
D
3D3V_S0
5V_S0
To SYS and EZ4 CRT Both
2
14
RN95 U25 2N7002DW
34 5 6
2
1
SRN10KJ
3
?ddc channel EZ4,CRT same TIME?
SYS_CRT_DDC_D5 SYS_CRT_DDC_C5
RN99
SRN0-2-U
2 1
3 4
E
EZ4_CRT_DDC_D 57 EZ4_CRT_DDC_C 57
Dummy when no EZ4
3 3
2 2
TV_LUMA_SYS57
TV_COMP_SYS57
1 1
TV_CRMA_SYS57
CRT_R_SYS57
CRT_G_SYS57
CRT_B_SYS57
R296
R298
R295
150R2F
150R2F
150R2F
1 2
1 2
1 2
DY
1 2
1 2
12
C323 SC100P50V2JN
1 2
1 2
12
C325 SC100P50V2JN
1 2
1 2
12
C328
R443
R299
R467
150R2F
150R2F
150R2F
1 2
1 2
1 2
A
SC100P50V2JN
12
C312 SC47P50V2JN
L11 IND-1D2UH
L12 IND-1D2UH
L13 IND-1D2UH
12
DY
C322 SC47P50V2JN
TV_LUMA_CON
12
C330 SC47P50V2JN
TV_COMP_CON
12
C327 SC47P50V2JN
TV_CRMA_CON
12
B
C313 SC47P50V2JN
DY
C324 SC270P50V
C326 SC270P50V
C329 SC270P50V
1 2
1 2
1 2
12
C314 SC47P50V2JN
L8 BLM18BB750SN1D
L9 BLM18BB750SN1D
L10 BLM18BB750SN1D
D8
2
3
DY
1
BAV99-2
D9
2
3
DY
1
BAV99-2
D10
2
3
DY
1
BAV99-2
12
C315 SC2P50V
3D3V_S0
3D3V_S0
3D3V_S0
12
C316 SC2P50V
C
12
C317 SC2P50V
D5
1
BAV99-2
CRT_R
12
12
C318 SC100P50V2JN
SYS_CRT_DDC_D5
SYS_CRT_DDC_C5
12
C319
C320
SC100P50V2JN
SC10P50V2JN-1
12
C321 SC10P50V2JN-1
5V_S0
12
CRT_R
CRT_G CRT_B
C311 SCD01U50V2ZY
CRT_G
D7
1
BAV99-2
SYS_HS
SYS_VS
3
2
5V_S0
CRT_B
3
2
D6
1
BAV99-2
3
2
CRT1
6 1
7 2 8 3 9 4
10
5
VIDEO-15-42
20.20378.015
17
11
12 13 14 15 16
SYS_CRT_DDC_D5 SYS_HS SYS_VS SYS_CRT_DDC_C5
TV CONN
TV1
TV_LUMA_CON
TV_COMP_CON
TV_CRMA_CON
8 4
1 5 2 7 3 6
9
MINDIN7-9
22.10021.B31
D
456
123
7
<Variant Name>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
A3
Date: Sheet of
CRT / TV Bolsena
16 58Tuesday, December 28, 2004
E
SA
Page 17
A
B
C
D
E
NUM_LED#34 CAP_LED#34 MAIL_LED#34 BLT_LED#34 WLAN_LED#34
STDBY_LED#34
CHARGE_LED#34
4 4
NUM_LED# CAP_LED#
MAIL_LED#
Dummy when use IDE
DY
R138
SATA_LED#19
HDD_LED#_525
Dummy when use SATA
CDROM_LED#_525
3 3
3D3V_S0
1 2
1 2
3
1
2
0R2-0 R140
0R2-0
Q7 PDTC144EU
2
1
D11
BAW56
PWRLED#
MEDIA_LED#
3
MEDIA_LED#
WLAN_LED# STDBY_LED#
PWRLED# CHARGE_LED#
BLT_LED#
1 2 3 4 5
1 2 3 4 5
RC15
RC16
1 2
LEDs
SRC100P50V-U
8 7 6
SRC100P50V-U
8 7 6
C714 SC100P50V2JN
NUM_LED#
CAP_LED#
MAIL_LED#
MEDIA_LED#
WLAN_LED#
BLT_LED#
STDBY_LED#
PWRLED#
CHARGE_LED#
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
on KB cover
LED ButtonVV
POWER E-MAIL INTERNE T e-BTN PROGRAM
V VVVV
R566 330R2
R567 330R2
R568 330R2
R572 330R2
R573 330R2
R565 330R2
R569 330R2
R570 330R2
R571 330R2
D_NUM1
1 2
D_CAPS1 LED-G-31
1 2
D_MAIL1
1 2
D_MEDIA1
1 2
D_WLAN1 LED-Y-22
1 2
D_BTH1
1 2
D_STDBY1 L ED-Y-22
1 2
D_PWR1 LED-G-31
1 2
D_CHGR1 LED-Y-22
1 2
CAPS NUM HDD
3D3V_S0
LED-G-31
LED-G-31
LED-G-31
LED-B-13-U
3D3V_S5
VVV
Front panel
LED Button
V
V
VV
V
V
BlutTooth WirelessCharger Power
2 2
LCD POWERLCD CONN
139
1 2
Layout 40 mil
R160 1KR2
12
LCDVDD_ON_1
12
C346
C347
SC1U10V3KX
SCD1U
U11
1
OUT
2
GND ON/OFF#3IN
AAT4280IGU-3-T1
D
3D3V_S0LCDPOWER_S0
6
IN
5
GND
4
<Variant Name>
Title
Size Document Number Rev
Date: Sheet of
12
C348 SC1U10V3KX
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
INV / LCD / LEDs
A3
Bolsena
E
17 58Tuesday, December 28, 2004
SA
12
LCD CONN
2
C344 SCD1U
DY
12
C345 SCD1U
40
LCD_VDD_ON13,54
EVEN CHANNEL
ODD CHANNEL
LCDPOWER_S0
12
LCD1
41
MH1
1
2
3
PANEL_ID037 PANEL_ID137 PANEL_ID237 PANEL_ID337
R888
FPBACK34
BRIGHTNESS34
1 1
1 2
C716
1 2
SC100P50V2JN
10KR2
C715
1 2
SC100P50V2JN
?add net?
MH2
11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
42
5 7 9
ETY-CONN40D-1
4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
DY
C343 SC10U10V5ZY
LCD_TXBCLK+ 13,54 LCD_TXBCLK- 13,54 LCD_TXBOUT2+ 13,54 LCD_TXBOUT2- 13,54 LCD_TXBOUT1+ 13,54 LCD_TXBOUT1- 13,54 LCD_TXBOUT0+ 13,54 LCD_TXBOUT0- 13,54 LCD_TXACLK+ 13,54 LCD_TXACLK- 13,54 LCD_TXAOUT2+ 13,54 LCD_TXAOUT2- 13,54 LCD_TXAOUT1+ 13,54 LCD_TXAOUT1- 13,54 LCD_TXAOUT0+ 13,54 LCD_TXAOUT0- 13,54
20.F0322.040
A
B
C
Page 18
A
3D3V_S0
PCI_REQ#5 PCI_GNT#5
1 2
1 2
DY
NB_EEPROM_WP
R161 1KR2
C349 SCD1U16V
DY
4 4
1D8V_S0
3 3
1D8V_S0 PCIE_VDDR
1 2
1 2
1 2
1 2
C367 SC12P50V2JN-1
2 3
C354 SC22P50V2JN-1
L14 MLB-201209-11
12
L15 0R3-U
12
12
41
X2 XTAL-32D768K-4P
12
C359 SC10U10V5ZY
12
C361 SC22U10V6ZY-U
DY
2 2
A_RST#
1 2
U15
A B GND3Y
NC7SZ32-U
5 6 7 8
12
R170
R169
20MR3
20MR3
PCIE_PVDD
12
C360 SC1U10V3KX
12
C362 SCD1U16V
INT_PIRQA# INT_PIRQB#
INT_PIRQH#
3D3V_S0
5
VCC
4
U12
4
SDA SCL WP VCC
AT24C04N-10SI
DY
32K_X1 32K_X2
GND
3
A2
2
A1
1
A0
SBSRC_CLK3 SBSRC_CLK#3
PCIE_RX0P_SB12 PCIE_RX0N_SB12 PCIE_RX1P_SB12 PCIE_RX1N_SB12
PCIE_TX0P_SB12 PCIE_TX0N_SB12 PCIE_TX1P_SB12 PCIE_TX1N_SB12
MAIN SOURCE: 82.30001.031 EPSON 2ND SOURCE: 82.30001.341 KDS
PCIE_VDDR
C371 SCD1U16V
12
C363 SCD1U16V
5V_S0
RSTDRV#_R
12
C364 SCD1U16V
DY
RP1
1 2 3 4 5 6
SRP10K
C372 SCD1U16V
1 2
R179 33R2
12
10 9 8 7
C373 SCD1U16V
DY
INT_PIRQG# INT_PIRQD#INT_PIRQC# INT_PIRQE# INT_PIRQF#
PCIRST# 3V to 5V level shift for HDD & CDROM
3D3V_S0
147
A_RST#
1 1
12
R184 8K2R2
PCIRST#
1 2
4 5
3D3V_S0
147
U16B
6
TSLCX08-U
A
SB400 asserts PLTRST# to reset devices on the platform.
U16A
3
PLT_RST#_R
TSLCX08-U
PCI_RST#
1 2
1 2
R181 33R2
R186 33R2
LPC_RST# 13,37
PCIRST_BUF# 15,26, 28,29,31,34,57
Secondary PCI Bus reset signal.
ALLOW_LDTSTOP13 SB_CPUPWRGD6
BMREQ#13 LDT_RST#6
B
1 2 1 2
1 2
A11, A12 4K53 1% A21, A22 5K5 1% A23 4K12 1% PA_IXP400AC10.PDF
12
C374 SCD1U16V
DY
3D3V_S0
INT_PIRQE#26 INT_PIRQF#26,31 INT_PIRQG#26 INT_PIRQH#29
RSTDRV#_5 25
B
12
TP55 TP56
LDT_STP#6,13
1 2 1 2 1 2 1 2
R177 150R2F
R173 150R2F R178 4K12R2F
12
C365 SCD1U16V
A_RST#
C368 SCD1U10V2MX
C350 SCD1U10V2MX
C351 SCD1U10V2MX
C352 SCD1U10V2MX
PCIE_PVDD
C366 SCD1U16V
TP65 TPAD30
TP66 TP67
TPAD30 TPAD30
TP69 TPAD30
TP68 TPAD30 TP70 TPAD30
TP71 TPAD30
TP72 TPAD30
TP73 TPAD30
12
PCIE_CALRP PCIE_CALRN
PCIE_CALI
SB_CPUSTP#
SB_PCISTP# INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#
INT_PIRQE#
INT_PIRQF#
INT_PIRQG#
INT_PIRQH#
SB_C29 SB_A28 H_NMI FWH_INIT# SB_D29
SB_B30
H_A20M# H_FERR#
H_DPRSLP#
R162 8K2R2
TX0P TX0N TX1P TX1N
32K_X1
32K_X2
U14A
AH8
A_RST#
L27
PCIE_RCLKP
M27
PCIE_RCLKN
M30
PCIE_TX0P
N30
PCIE_TX0N
K30
PCIE_TX1P
L30
PCIE_TX1N
H30
PCIE_TX2P
J30
PCIE_TX2N
F30
PCIE_TX3P
G30
PCIE_TX3N
M29
PCIE_RX0P
N29
PCIE_RX0N
M28
PCIE_RX1P
N28
PCIE_RX1N
J29
PCIE_RX2P
K29
PCIE_RX2N
J28
PCIE_RX3P
K28
PCIE_RX3N
G27
PCIE_CALRP
H27
PCIE_CALRN
G28
PCIE_CALI
R30
PCIE_PVDD
F26
PCIE_VDDR_1
R29
PCIE_VDDR_2
G26
PCIE_VDDR_3
P26
PCIE_VDDR_4
K26
PCIE_VDDR_5
L26
PCIE_VDDR_6
P28
PCIE_VDDR_7
N26
PCIE_VDDR_8
P27
PCIE_VDDR_9
H28
PCIE_VSS_1
F29
PCIE_VSS_2
H29
PCIE_VSS_3
H26
PCIE_VSS_4
F27
PCIE_VSS_5
G29
PCIE_VSS_6
L29
PCIE_VSS_7
J26
PCIE_VSS_8
L28
PCIE_VSS_9
J27
PCIE_VSS_10
N27
PCIE_VSS_11
M26
PCIE_VSS_12
K27
PCIE_VSS_13
P29
PCIE_VSS_14
P30
PCIE_VSS_15
AJ8
CPU_STP#/DPSLP#
AK7
PCI_STP#
AG5
INTA#
AH5
INTB#
AJ5
INTC#
AH6
INTD#
AJ6
INTE#/GPIO33
AK6
INTF#/GPIO34
AG7
INTG#/GPIO35
AH7
INTH#/GPIO36
B2
X1
B1
X2
C29
CPU_PG
A28
INTR/LINT0
C28
NMI/LINT1
B29
INIT#
D29
SMI#
E4
SLP#/LDT_STP#
B30
IGNNE#
F28
A20M#
E28
FERR#
E29
STPCLK#/ALLOW_LDTSTP
D25
LDT_PG/SSMUXSEL/GPIO0
E27
DPRSLPVR
D27
BMREQ#
D28
LDT_RST#
CHS-215SB400
C
SB400 SB
Part 1 of 4
PCI EXPRESS INTERFACE
PCI INTERFACE
REQ4#/PLL_BP33/PDMA_REQ1#
GNT3#/PLL_BP66/PDMA_GNT0# GNT4#/PLL_BP50/PDMA_GNT1#
LPC
CPU XTAL
RTC_IRQ#/ACPWR_STRAP
RTC
C
PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5 PCICLK6 PCICLK7 PCICLK8 PCICLK9
PCICLK_FB
PCI CLKS
PCIRST# AD0/ROMA18 AD1/ROMA17 AD2/ROMA16 AD3/ROMA15 AD4/ROMA14 AD5/ROMA13 AD6/ROMA12 AD7/ROMA11
AD8/ROMA9
AD9/ROMA8 AD10/ROMA7 AD11/ROMA6 AD12/ROMA5 AD13/ROMA4 AD14/ROMA3 AD15/ROMA2 AD16/ROMD0 AD17/ROMD1 AD18/ROMD2 AD19/ROMD3 AD20/ROMD4 AD21/ROMD5 AD22/ROMD6 AD23/ROMD7
AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
CBE0#/ROMA10
CBE1#/ROMA1
CBE2#/ROMWE#
CBE3#
FRAME#
DEVSEL#/ROMA0
IRDY#
TRDY#/ROMOE#
PAR/ROMA19
STOP# PERR# SERR#
REQ0#
REQ1#
REQ3#/PDMA_REQ0#
REQ2#
REQ5#/GPIO13 REQ6#/GPIO31
GNT0#
GNT1#
GNT2#
GNT5#/GPIO14 GNT6#/GPIO32
CLKRUN#
LOCK#
LAD0 LAD1 LAD2 LAD3
LFRAME#
LDRQ0# LDRQ1#
SERIRQ
RTCCLK
VBAT
RTC_GND
L4 L3 L2 L1 M4 M3 M2 M1 N4 N3 N2
AJ7 W3 Y2 W4 Y3 V1 Y4 V2 W2 AA4 V4 AA3 U1 AA2 U2 AA1 U3 T4 AC1 R2 AD4 R3 AD3 R4 AD2 P2 AE3 P3 AE2 P4 AF2 N1 AF1 V3 AB4 AC2 AE4 T3 AC4 AC3 T2 U4 T1 AB2 AB3 AF4 AF3 AG2 AG3 AH1 AH2 AH3 AJ2 AK2 AJ3 AK3 AG4 AH4 AJ4 AG1 AB1
AG25 AH25 AJ25 AH24 AG24 AH26 AG26
AK27
C2 F3
A2 A1
PCI_CLK1_R PCI_CLK2_R PCI_CLK3_R PCI_CLK4_R PCI_CLK5_R PCI_CLK6_R PCI_CLK7_R PCI_CLK8_R PCI_CLK9_R PCI_CLK9_FB
PCIRST# PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31
PCI_REQ#4
PCI_REQ#5 PCI_REQ#6
PCI_GNT#3 PCI_GNT#4 PCI_GNT#5 PCI_GNT#6
PCI_LOCK#
LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3
LPC_LDRQ1#
VBAT
12
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
1 2
PCI_AD[31..0] 22,26,29,31
PCI_REQ#3
TP62 TPAD30
TP61 TPAD30
TP64 TPAD30
TP63 TPAD30
LPC_LAD[0 . .3 ] 34,37
P_SERIRQ 26,34,37,57
3D3V_AUX_S5
RTC_CLK 22 AUTO_ON# 22
C375 SCD1U16V
12
C376 SC1U10V3KX
RTC_AUX_S5
3
D
32K suspend clock output
PM_SLP_S3#21,34,38,39,43,44,57 RTC_CLK22
R171 22R2
678
4 5
CLK33_CBUS CLK33_LAN CLK33_MINI CLK33_KBC CLK33_SIO CLK33_LPCROM
1 2
12
C355 DUMMY-C2
RN43
123
SRN8K2-1
R175 22R2
R176 22R2
R164 22R2
R165 22R2
R166 22R2
R167 22R2
R168 22R2
R172 22R2
3D3V_S0
RN42
123
SRN8K2-1
LPC_LFRAME# 34,37 LPC_LDRQ0# 37
U106 BAT54C-U
1 2
D
E
5V_S5
U13A
147
PCI_CLK7 22 PCI_CLK8 22
C353 SC100P50V2JN
1 2
3
TSAHCT08-U
CLK33_CBUS CLK33_LAN CLK33_MINI CLK33_KBC CLK33_SIO CLK33_LPCROM
1 2
63.10034.151
R163 10R3
CLK32_G791 23
CLK33_CBUS 26 CLK33_LAN 22,29 CLK33_MINI 22,31 CLK33_KBC 22,34 CLK33_SIO 22,37 CLK33_LPCROM 22
DY
12
12
C369 DUMMY-C2
678
678
RN44
123
4 5
4 5
SRN8K2-1
PM_CLKRUN# 26,29,31,34,37
RTC_AUX_S5
R156 1KR2
1 2
1
2
3 4
<Variant Name>
Title
Size Document Number Rev A3
Date: Sheet
ATI-SB400 (1 of 5) PCI, PCIE
12
C356 DUMMY-C2
678
RN45
12
R174 8K2R2
123
SRN8K2-1
?which is gnd
RTC1 MLXCON2
Bolsena SA
12
12
C358 DUMMY-C2
RN46
1 2 3 4 5
SRN100K
PCI_CBE#0 26,29,31 PCI_CBE#1 26,29,31 PCI_CBE#2 26,29,31 PCI_CBE#3 26,29,31 PCI_FRAME# 26,29,31 PCI_DEVSEL# 26,29,31 PCI_IRDY# 26,29,31 PCI_T R D Y # 26,29,31 PCI_PAR 26,29,31 PCI_STOP# 26 ,29,31 PCI_PERR# 26,29,31 PCI_SERR# 26,29,31
PCI_REQ#0 31 PCI_REQ#1 26 PCI_REQ#2 29
PCI_GNT#0 31 PCI_GNT#1 26 PCI_GNT#2 29
RN47
6 7 8
SRN10K-2
C370 DUMMY-C2
C357 DUMMY-C2
4 5
LPC_LAD0 LPC_LAD3 LPC_LAD1 LPC_LAD2
PCI_GNT#5 PCI_REQ#5 PCI_GNT#6 PCI_REQ#6
Pull up 100k to 3D3V_S0
P_SERIRQ
1 2
LPC_LDRQ1#
1 2
LPC_LDRQ0#
1 2
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
18 58Tuesday, December 28, 2004
E
of
8 7 6
DY
3D3V_S0
45 3 2 1
R180 10KR2 R182 10KR2 R183 10KR2
3D3V_S0
Page 19
A
B
C
D
E
4 4
SATA_TXP025 SATA_TXN025
SATA_RXN025 SATA_RXP025
Close to SouthBridge
1 2 1 2
DY
1 2
DY
1 2
DY DY
C377 SCD01U50V3KX
C378 SCD01U50V3KX C379 SCD01U50V3KX
C380 SCD01U50V3KX
SATA_TP0 SATA_TN0
SATA_RN0 SATA_RP0
?RX NO USED PULL HIGH?
Close to SouthBridge
DY
R187
1 2
1KR2F
C381
1 2
SCD01U50V3KX
SATA_X2
SATA_X1
DY
X3
X-25MHZ-11-U
1 2
SATA_LED#17
C382
1 2
SC27P50V2JN
C383
1 2
SC27P50V2JN
3 3
Dummy when use IDE
R190 0R2-0
1D8V_SATA_S0
12
DY
R189 0R2-0
2 2
SATA_X1
12
DY
Dummy when use SATA
SATA_X1 SATA_X2
1D8V_SP_S0 1D8V_SX_S0 1D8V_SATA_S0
AK22
AJ22
AK21
AJ21
AK19
AJ19
AK18
AJ18
AK14
AJ14
AK13
AJ13
AK11
AJ11
AK10
AJ10 AJ15 AJ16
AK16
AH15 AH16 AG10
AG14 AH12 AG12 AG18 AG21 AH18 AG20
AG9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22
AH9
AG11 AG15 AG17 AG19 AG22 AG23
AH17 AH23 AH13 AH20
AJ12
AK17 AK23 AH10
AJ23
AK8
AF9
AK9
U14B
SATA_TX0+ SATA_TX0-
SATA_RX0­SATA_RX0+
SATA_TX1+ SATA_TX1-
SATA_RX1­SATA_RX1+
SATA_TX2+ SATA_TX2-
SATA_RX2­SATA_RX2+
SATA_TX3+ SATA_TX3-
SATA_RX3­SATA_RX3+
SATA_CAL SATA_X1 SATA_X2 SATA_ACT# PLLVDD_SATA XTLVDD_SATA AVDD_SATA_1
AVDD_SATA_2 AVDD_SATA_3 AVDD_SATA_4 AVDD_SATA_5 AVDD_SATA_6 AVDD_SATA_7 AVDD_SATA_8
AVSS_SATA_1 AVSS_SATA_2 AVSS_SATA_3 AVSS_SATA_4 AVSS_SATA_5 AVSS_SATA_6 AVSS_SATA_7 AVSS_SATA_8 AVSS_SATA_9 AVSS_SATA_10 AVSS_SATA_11 AVSS_SATA_12 AVSS_SATA_13 AVSS_SATA_14 AVSS_SATA_15 AVSS_SATA_16 AVSS_SATA_17 AVSS_SATA_18 AVSS_SATA_19 AVSS_SATA_20 AVSS_SATA_21 AVSS_SATA_22 AVSS_SATA_23 AVSS_SATA_24 AVSS_SATA_25 AVSS_SATA_26 AVSS_SATA_27 AVSS_SATA_28 AVSS_SATA_29 AVSS_SATA_30 AVSS_SATA_31 AVSS_SATA_32
SB400 SB
Part 2 of 4
SERIAL ATA
SERIAL ATA POWER
PIDE_IORDY
PIDE_DACK#
PRIMARY ATA 66/100
SIDE_IORDY
SIDE_DACK#
SIDE_D0/GPIO15 SIDE_D1/GPIO16 SIDE_D2/GPIO17 SIDE_D3/GPIO18 SIDE_D4/GPIO19 SIDE_D5/GPIO20 SIDE_D6/GPIO21 SIDE_D7/GPIO22 SIDE_D8/GPIO23
SIDE_D9/GPIO24 SIDE_D10/GPIO25 SIDE_D11/GPIO26 SIDE_D12/GPIO27 SIDE_D13/GPIO28 SIDE_D14/GPIO29
SECONDARY ATA 66/100
SIDE_D15/GPIO30
AVSS_SATA_33 AVSS_SATA_34 AVSS_SATA_35 AVSS_SATA_36 AVSS_SATA_37 AVSS_SATA_38 AVSS_SATA_39 AVSS_SATA_40 AVSS_SATA_41 AVSS_SATA_42 AVSS_SATA_43 AVSS_SATA_44 AVSS_SATA_45
PIDE_IRQ
PIDE_A0 PIDE_A1 PIDE_A2
PIDE_DRQ
PIDE_IOR# PIDE_IOW# PIDE_CS1# PIDE_CS3#
PIDE_D0 PIDE_D1 PIDE_D2 PIDE_D3 PIDE_D4 PIDE_D5 PIDE_D6 PIDE_D7 PIDE_D8
PIDE_D9 PIDE_D10 PIDE_D11 PIDE_D12 PIDE_D13 PIDE_D14 PIDE_D15
SIDE_IRQ
SIDE_A0
SIDE_A1
SIDE_A2
SIDE_DRQ
SIDE_IOR# SIDE_IOW# SIDE_CS1# SIDE_CS3#
AD30 AE28 AD27 AC27 AD28 AD29 AE27 AE30 AE29 AC28 AC29
AF29 AF27 AG29 AH30 AH28 AK29 AK28 AH27 AG27 AJ28 AJ29 AH29 AG28 AG30 AF30 AF28
V29 T27 T28 U29 T29 V30 U28 W29 W30 R27 R28
V28 W28 Y30 AA30 Y28 AA28 AB28 AB27 AB29 AA27 Y27 AA29 W27 Y29 V27 U27
AG13 AH22 AK12 AH11 AJ17 AH14 AH19 AJ20 AH21 AJ9 AG16 AK15 AK20
PIDE_D0 PIDE_D1 PIDE_D2 PIDE_D3 PIDE_D4 PIDE_D5 PIDE_D6 PIDE_D7 PIDE_D8 PIDE_D9 PIDE_D10 PIDE_D11 PIDE_D12 PIDE_D13 PIDE_D14 PIDE_D15
SIDE_D0 SIDE_D1 SIDE_D2 SIDE_D3 SIDE_D4 SIDE_D5 SIDE_D6 SIDE_D7 SIDE_D8 SIDE_D9 SIDE_D10 SIDE_D11 SIDE_D12 SIDE_D13 SIDE_D14 SIDE_D15
PIDE_IORDY 25 PIDE_IRQ14 25 PIDE_A0 25 PIDE_A1 25 PIDE_A2 25
PIDE_DREQ 25 PIDE_IOR# 25 PIDE_IOW# 25 PIDE_CS#0 25 PIDE_CS#1 25
PIDE_D[15..0] 25
SIDE_IORDY 25 SIDE_IRQ15 25 SIDE_A0 25 SIDE_A1 25 SIDE_A2 25 SIDE_DACK# 25 SIDE_DREQ 25 SIDE_IOR# 25 SIDE_IOW# 25 SIDE_CS#0 25 SIDE_CS#1 25
SIDE_D[15..0] 25
PIDE_DACK# 22,25
also strap function
if no PATA, need strap?
CHS-215SB400
1D8V_S0 1D8V_SATA_S0
R191
1 1
1 2
0R5J-1
A
12
C384 SC10U10V5ZY
12
C385 SCD1U50V5ZY
12
C386 SCD1U50V5ZY
12
C387 SCD1U50V5ZY
12
C388 SCD1U50V5ZY
L16
1 2
0R3-U
Capacitor PLACE NEAR THE ACCORDED BALLS
B
12
C389 SC2D2U16V5ZY
1D8V_S01D8V_S0 1D8V_SX_S01D8V_SP_S0
L17
1 2
0R3-U
12
Capacitor PLACE NEAR THE ACCORDED BALLS
Dummy when use IDE
C390 SC2D2U16V5ZY
C
<Variant Name>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
ATI-SB400 (2 of 5) IDE
Size Document Number Rev A3
D
Date: Sheet
Bolsena
19 58Tuesday, December 28, 2004
E
SA
of
Page 20
A
B
C
D
E
1D8V_S0
12
12
C391 SC22U10V6ZY-U
4 4
12
C392
C393
SC22U10V6ZY-U
SCD1U16V
DY
DY
12
C412 SCD1U16V
12
12
C413 SCD1U16V
C398 SCD1U16V
DY
3D3V_SB_S0
12
12
C401 SC22U10V6ZY-U
3 3
12
C402 SCD1U16V
C416 SCD1U16V
12
12
12
12
C394 SCD1U16V
DY
12
C414 SCD1U16V
DY
C403 SCD1U16V
C395 SCD1U16V
C399 SCD1U16V
12
C417 SCD1U16V
DY
12
12
12
12
C396 SCD1U16V
DY
12
C415 SCD1U16V
DY
C404 SCD1U16V
C397 SCD1U16V
C400 SCD1U16V
12
C405 SCD1U16V
3D3V_S0
R192
12
0R5J-1
DY
12
12
12
C420 SCD1U16V
C428 SCD1U16V
12
C409 SCD1U16V
3D3V_S5
R193
12
0R5J-1
12
C421 SCD1U16V
DY
12
12
12
C419 SCD1U16V
12
C426 SCD1U16V
C408 SCD1U16V
C427 SCD1U16V
DY
12
12
C406 SCD1U16V
DY
3D3V_SB_S5
12
C423 SC22U10V6ZY-U
DY
2 2
12
12
C407 SCD1U16V
DY
12
C424 SCD1U16V
C418 SCD1U16V
C425 SCD1U16V
DY
1D8V_S5 1D8V_S5
12
C429 SC10U10V5ZY
DY
12
12
C430 SCD1U16V
C431 SCD1U16V
DY
12
C432 SCD1U16V
12
C433 SCD1U16V
DY
DY
1 1
A
12
12
C434 SCD1U16V
12
C435
C436
SCD1U16V
SCD1U16V
Vf = 0.38v (@1mA)
C410 SCD1U16V
DY
1D8V_S5
B
12
C411 SCD1U16V
D43
1 2
RB751V-40-U
3D3V_S0
12
C422 SCD1U16V
3D3V_S5
5V_S0
1D8V_S0
12
D42
RB751V-40-U
D12
1 2
RB751V-40-U
1 2
V5_VREF MIN 4.5 NORMAL 5.0 MAX 5.5
R195
1 2
1KR2
L18 MLB-201209-11
12
DY
12
1D2V_S0
1D8VAVDDCK_S0
12
C437 SC10U10V5ZY
V5_VREF
12
C441 SC1U10V3KX
C438 SC1U10V3KX
C442 SCD1U16V
1D8V_S0
3D3V_SB_S5
1D8V_S5
1 2
12
C
3D3V_SB_S0
1D8V_S5
R194 0R2-0
C439 SCD1U16V
CPU_1D2V
V5_VREF
12
C440 SCD1U16V
AA5
AA26
AB5
AC30
AD5
AD26
AE1 AE5
AE26
AF24 AF25
AK1
AK4 AK26 AK30
M12
M13
M18
M19
W12
W13
W18
W19
AG6
A30 D30 E24 E25
U26 U30
V26 Y26
AF6 AF7
N12 N13 N18 N19 V12 V13 V18 V19
E10 E20 E21
E13 E14 E16 E17
C30
A24 B24
A29 B28
E11 E12 E15 E18
J5 K1 K5 N5 P5 R1 U5
V5 Y1
A3 A7 E6 E7 E1
F5 E9
A4 A8
C1 E5 E8
U14C
VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 VDDQ_16 VDDQ_17 VDDQ_18 VDDQ_19 VDDQ_20 VDDQ_21 VDDQ_22 VDDQ_23 VDDQ_24 VDDQ_25 VDDQ_26 VDDQ_27 VDDQ_28 VDDQ_29 VDDQ_30 VDDQ_31 VDDQ_32 VDDQ_33 VDDQ_34
VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDD_10 VDD_11 VDD_12 VDD_13 VDD_14 VDD_15 VDD_16
S5_3.3V_1 S5_3.3V_2 S5_3.3V_3 S5_3.3V_4 S5_3.3V_5 S5_3.3V_6
S5_1.8V_1 S5_1.8V_2 S5_1.8V_3 S5_1.8V_4
USB_PHY_1.8V_1 USB_PHY_1.8V_2 USB_PHY_1.8V_3 USB_PHY_1.8V_4
CPU_PWR V5_VREF AVDDCK
AVSSCK VSS_1
VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11
CHS-215SB400
SB400 SB
Part 3 of 4
POWER
VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98
E19 E22 E23 E26 E30 F1 F4 G5 H5 J1 J4 K4 L5 M5 P1 R5 R26 T5 T26 T30 W1 W5 W26 Y5 AB26 AB30 AC5 AC26 AD1 AF5 AF8 AF23 AF26 AG8 AJ1 AJ24 AJ30 AK5 AK25 M14 M15 M16 M17 N14 N15 N16 N17 P12 P13 P14 P15 P16 P17 P18 P19 R12 R13 R14 R15 R16 R17 R18 R19 T12 T13 T14 T15 T16 T17 T18 T19 U12 U13 U14 U15 U16 U17 U18 U19 V14 V15 V16 V17 W14 W15 W16 W17
<Variant Name>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
ATI-SB400 (3 of 5) POWER
Size Document Number Rev A3
D
Date: Sheet of
Bolsena
20 58Tuesday, December 28, 2004
E
SA
Page 21
A
B
C
D
E
123
PM_THRM#23 PME#_SB29,34
KA20GATE34 KBRCIN#34
ECSWI#
PCIE_WAKE#57
RSMRST#_KBC34 X1_CLK_SB14_1
XO_CLK_SB14_1
SMBC_SB SMBD_SB
678
4 5
GPIO3 GPIO1 GPIO6
PM_SLP_S5#34,44,57 PM_PWRBTN#34 SB_PWRGD39 PM_SUS_STAT#34,37
1 2
1 2 1 2 1 2
B
PM_SLP_S3#_SB
1 2 1 2
R209 0R2-0
R204 0R2-0
R210 0R2-0
R211 0R2-0
DY
TP78 TPAD30
SMBC_SB SMBD_SB DDC1_SCL DDC1_SDA DDC2_SCL DDC2_SDA
1 2 1 2
1 2
GPM6# RI#
R207 10KR2
R208 10KR2
THERMTRIP#_1
ECSCI# ECSMI# S3_STATE SYS_REST
SIO_CLK_SB
GPIO1 GPIO6
PCB_VER0 PCB_VER1
GPIO3
AC_BITCLK
R226 33R2
AC_SDOUT
R225 33R2
AC97_DIN2 AC_SYNC
R227 33R2
U14D
C6
TALERT#/TEMP_ALERT#/GPIO10
D5
BLINK/GPM6#
C4
PCI_PME#/GEVENT4#
D3
RI#/EXTEVNT0#
B4
SLP_S3#
E3
SLP_S5#
B3
PWR_BTN#
C3
PWR_GOOD
D4
SUS_STAT#
F2
TEST1
E2
TEST0
AJ26
GA20IN
AJ27
KBRST#
D6
SMBALERT#/THRMTRIP#/GEVENT2#
C5
LPC_PME#/GEVENT3#
A25
LPC_SMI#/EXTEVNT1#
D8
VOLT_ALERT#/S3_STATE/GEVENT5#
D7
SYS_RESET#/GPM7#
D2
WAKE#/GEVENT8#
D1
RSMRST#
A23
14M_X1/OSC
B23
14M_X2
AK24
SIO_CLK
B25
ROM_CS#/GPIO1
C25
GHI#/GPIO6
C23
VGATE/GPIO7
D24
AGP_STP#/GPIO4
D23
AGP_BUSY#/GPIO5
A27
FANOUT0/GPIO3
C24
SPKR/GPIO2
A26
SCL0/GPOC0#
B26
SDA0/GPOC1#
B27
DDC1_SCL/GPIO9
C26
DDC1_SDA/GPIO8
C27
DDC2_SCL/GPIO11
D26
DDC2_SDA/GPIO12
J2
NC1
K3
NC4
J3
NC3
K2
NC2
G1
AC_BITCLK
G2
AC_SDOUT
H4
AC_SDIN0
G3
AC_SDIN1
G4
AC_SDIN2
H1
AC_SYNC
H3
AC_RST#
H2
SPDIF_OUT
CHS-215SB400
PM_SLP_S3#_SB
SB400 SB
ACPI / WAKE UP EVENTS
CLK / RST
3D3V_S5
147
9
10
Part 4 of 4
USB_OC0#/GPM0# USB_OC1#/GPM1#
USB_OC2#/FANOUT1/GPM2#
USB_OC3#/GPM3# USB_OC4#/GPM4#
USB_OC6#/FAN_ALERT#/GEVENT6#
USB_OC7#/CASE_ALERT#/GEVENT7#
USB_OC5#/GPM5#
USB INTERFACE
GPIOAC97 (NOT USED)
USB PWR
SB
U5C
8
TSLCX08MTC-U
C
48M_X2
AVDDTX_0 AVDDTX_1 AVDDTX_2 AVDDTX_3
AVDDC
AVSSC
A15 B15 C15 D16 C16 D15 B8 C8 C7 B7 B6 A6 B5 A5
A11 B11
A10 B10
A14 B14
A13 B13
A18 B18
A17 B17
A21 B21
A20 B20
C21 C18 D13 D10 D20 D17 C14 C11
A16 B16 A9
A12 A19 A22 B9 B12 B19 B22 C9 C10 C12 C13 C17 C19 C20 C22 D9 D11 D12 D14 D18 D19 D21 D22
USB_PP7 USB_PN7
USB_PP6 USB_PN6
USB_PP5 USB_PN5
USB_PP4 USB_PN4
USB_PP3 USB_PN3
48M_X1/USBCLK
USB_RCOMP
USB_VREFOUT
USB_ATEST1 USB_ATEST0
USB_HSDP7+
USB_HSDM7-
USB_HSDP6+
USB_HSDM6-
USB_HSDP5+
USB_HSDM5-
USB_HSDP4+
USB_HSDM4-
USB_HSDP3+
USB_HSDM3-
USB_HSDP2+
USB_HSDM2-
USB_HSDP1+
USB_HSDM1-
USB_HSDP0+
USB_HSDM0-
AVDDRX_0 AVDDRX_1 AVDDRX_2 AVDDRX_3
AVSS_USB_1 AVSS_USB_2 AVSS_USB_3 AVSS_USB_4 AVSS_USB_5 AVSS_USB_6 AVSS_USB_7 AVSS_USB_8
AVSS_USB_9 AVSS_USB_10 AVSS_USB_11 AVSS_USB_12 AVSS_USB_13 AVSS_USB_14 AVSS_USB_15 AVSS_USB_16 AVSS_USB_17 AVSS_USB_18 AVSS_USB_19 AVSS_USB_20 AVSS_USB_21 AVSS_USB_22 AVSS_USB_23 AVSS_USB_24
PM_SLP_S3# 18,34,38,39,43,44,57
1 2
DY
USB_PCOMP USB_VREFOUT USB_TE1 USB_TE0
USB_OC#2
USB_OC#3
USB_OC#4
BT_EN USB_OC#6 USB_OC#7
R200 0R2-0
1 2
TP75 TP74 TP76
USB_OC#2 24
R203
1 2
USB_PP4 24 USB_PN4 24
TP129 TP130
USB_PP2 24 USB_PN2 24
USB_PP1 24 USB_PN1 24
USB_PP0 24 USB_PN0 24
AVDD_USB
3D3V_AVDDC
D
1 2
DY
R202 11K8R3F
USB_OC#01 24
USB_OC#4 24
ECSWI#
0R2-0
TP77 TP79
USB_PP6 24 USB_PN6 24
TP80 TP122
CLK48_USB 3
R201 0R2-0
RP2
1 2 3 4 5 6
SRP10K
3D3V_S5
USB_OC#3
!To BlueTooth
3D3V_S5
L19
1 2
0R3-U
12
12
C446 SC1U10V3KX
12
C452 SC1U10V3KX
12
C456 SC1U10V3KX
12
12
12
E
C449 SC10U10V5ZY
DY
12
C451 SC10U10V5ZY
3D3V_AVDDC
DY
L20
1 2
MLB-201209-11
12
C455 SC10U10V5ZY
DY
<Variant Name>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev A3
Date: Sheet
ATI-SB400 (4 of 5) USB GPIO
Bolsena
10 9 8 7
C447 SCD1U16V
C450 SCD1U16V
C457 SCD1U16V
21 58Tuesday, December 28, 2004
3D3V_S5
BT_EN
USB_OC#7 USB_OC#6
12
C445 SCD1U16V
12
C453 SCD1U16V
of
AVDD_USB
12
C448 SCD1U16V
12
C454 SCD1U16V
SA
3D3V_S5
678
RN63
4 4
3 3
123
SRN4K7
SB_OSC_CLK3 SB_OSC_INT13
Use CLK GEN REF
14.318M CLK to SB OSCIN DUMMY IT
4 5
678
RN64
123
SRN4K7
PM_SLP_S3#_SB
1 2
DY
1 2
DY
4 5
PM_SLP_S5# PCIE_WAKE# PME#_SB
GPM6# SYS_REST PM_PWRBTN# PM_THRM#
1 2
XI_CLK_SB14
C444 SC33P50V2JN
X4
X-14D318MHZ-1-U1
1 2
XO_CLK_SB14
C443 SC33P50V2JN
DY
R213 0R2-0
DY
12
12
R34810KR2
12
DY
12
12
R19910KR2
R19810KR2
S3_STATE
THERMTRIP#_1 PM_SUS_STAT#
CPU_THERMTRIP#6,23 ECSCI#_KBC34 ECSMI#_KBC34 ECSWI#34
R206
1 2
0R2-0
R217
12
0R2-0
DY
R219 1MR2
R220
12
0R2-0
DY
3D3V_S0
R20510KR2
RN62
SRN10K-2
RI#
DY
VRM_PWRGD39,41
SPKR_SB32
Board Version Setting
12
3D3V_S5
12
12
DY
12
R232 10KR2
AC97_RST#
SMBC_SB3,8,57 SMBD_SB3,8,57
R222 10KR2
R223 10KR2
R221 10KR2
PCB_VER0 PCB_VER1
12
R224 10KR2
AC97_BITCLK_SB32
DY
AC97_DOUT22,24,32 AC97_DIN032 AC97_DIN124
AC97_SYNC24,32 AC97_RST#24,32 SPDIF_OUT_STRAP22
3D3V_S03D3V_S0
2
14
RN103
SRN10KJ
3
0 1 1
4 5
DDC1_SCL DDC1_SDA
DDC2_SCL DDC2_SDA
PCB_VER1
00 1SB
1
A
PCB_VER0
Ver. SA
SC 0
1
2 2
678
RN104
123
SRN10K-2
1 1
Page 22
A
3D3V_S5 3D3V_S0 3D3V_S5 3D3V_S03D3V_S03D3V_S03D3V_S03D3V_S0 3D3V_S0 3D3V_S0 3D3V_S0
B
12
R239 10KR2
12
R240 10KR2
12
R241 10KR2
12
R242 10KR2
C
12
R243 10KR2
12
R244 10KR2
12
R245 10KR2
12
R246 10KR2
D
12
R247 10KR2
12
R248 10KR2
12
R249 10KR2
E
AUTO_ON#18 AC97_DOUT21,24,32 RTC_CLK18
4 4
SPDIF_OUT_STRAP21 CLK33_LAN18,29 CLK33_MINI18,31 CLK33_KBC18,34 CLK33_SIO18,37 CLK33_LPCROM18 PCI_CLK718 PCI_CLK818
12
DY
REQUIRED SYSTEM STRAPS
STRAP
3 3
PIDE_DACK#19,25
PCI_AD3118,26,29,31 PCI_AD3018,26,29,31 PCI_AD2918,26,29,31 PCI_AD2818,26,29,31
2 2
PCI_AD2718,26,29,31 PCI_AD2618,26,29,31 PCI_AD2518,26,29,31 PCI_AD2418,26,29,31 PCI_AD2318,26,29,31
HIGH
STRAP LOW
ACPWRON PCI_CLK5SPDIF_OUT
MANUAL PWR ON
DEFAULT
AUTO PWR ON
3D3V_S0 3D3V_S0 3D3V_S0 3D3V_S03D3V_S03D3V_S03D3V_S0 3D3V_S0 3D3V_S0 3D3V_S0
12
R261 10KR2
DY
12
R250 10KR2
R251 10KR2
AC_SDOUT RTC_ CL K
USE DEBUG STRAPS
IGNORE DEBUG STRAPS
DEFAULT
12
R262 10KR2
DY
INTERNAL RTC
DEFAULT
EXTENNAL RTC (NOT SUPPORTED W/IT8712)
12
R263 10KR2
DY
12
R252 10KR2
12
R253 10KR2
DY
12
R254 10KR2
12
R255 10KR2
DY
SIO 24MHz
SIO 48MHz
DEFAULT
12
R264 10KR2
12
PCI_CLK2
R265 10KR2
48MHZ­Clock Input Buffer
DEFAULT
48MHZ
-Crytsal Pad
PCI_CLK3
USB PHY PWRDOWN DISABLE
DEFAULT
USB PHY PWRDOWN ENABLE
12
R266 10KR2
DY
DY
12
DY
PCI_CLK7
ROM TYPE H,H=PCI (X Bus) ROM H,L=LPC ROM I
L,H=LPC ROM II
L,L=Firmware Hub ROM
12
R270 10KR2
DY
R259 10KR2
DY
12
12
DY
PCI_CLK6
CPU I/F=K8
DEFAULT
CPU I/F=P4
R269 10KR2
R258 10KR2
12
R256 10KR2
12
R257 10KR2
DY
PCI_CLK4
USB INT PLL48
DEFAULT
USB EXT. 48MHZ
12
R267 10KR2
DY
14MHZ OSC MODE
DEFAULT
14MHZ XTAL MODE
12
R268 10KR2
DY
DY
12
PCI_CLK8
R260 10KR2
12
R271 1KR2
DEBUG STRAPS
STRAP
1 1
HIGH
STRAP LOW
DY
USE LONG RESET
DEFAULT
USE SHORT RESET
12
R272 10KR2
DY
12
R273 10KR2
DY
PCI_AD31 PCI _AD30
RESERVED
RESERVED RESERVED RESERVED
12
DY
PCI_AD29
R274 10KR2
12
DY
PCI_AD28
R275 10KR2
12
PCI_AD27
BYPASS PCI PLL
USE PCI PLL
DEFAULT DEFAULT
R276 10KR2
12
R277 10KR2
PCI_AD26
BYPASS ACPI BCLK
USE ACPI BCLK
12
R278 10KR2
PCI_AD25 PCI_AD24PDACK#
BYPASS IDE PLL
USE IDE PLL
DEFAULT
12
R279 10KR2
EEPROM PCIE STRAPS
USE DEFAULT PCIE STRAPS
DEFAULT
12
R280 10KR2
PCI_AD23
RESERVEDUSE
<Variant Name>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
ATI-SB400 STRAPPING(5 of 5)
Size Document Number Rev
A3
Date: Sheet
Bolsena
22 58Tuesday, December 28, 2004
of
SA
Page 23
*Layout* 15 mil
12
C458 SCD1U
5V_S0
R283
1 2
200R3
12
C462 SCD1U
Setting T8 as 100 Degree
V_DEGREE =(((Degree-72)*0.02)+0.34)*VCC
HW thermal shut down tempature setting 95 degree . Put Near CPU .
12
C459 SC10U10V5ZY
12
R284 4K99R3F
12
R290 49K9R3F
5V_G792_S0
V_DEGREE
FAN1_VCC
12
D13
S1N4148-U
1 2
*Layout* 30 mil
5V_S0
12
C463
C464
SC4D7U10V5ZY
SCD1U
RUNPWROK39
ALERT#
12
12
C465 SCD1U
1 2
DY
C460 SC2200P50V2KX
1 2
DY
12
R291 10KR2
R297 0R3-U
5V_S0
12
PR_HW_SDN#
G792_RST#
R289 4K7R2
PM_THRM# 21
R286 10KR2
6
20
7 9
11
ALERT#
15 13
3 2
DXP1:108 Degree DXP2:H/W Setting DXP3:88 Degree
U18
VCC DVCC
DXP1 DXP2 DXP3
ALERT# THERM# THERM_SET RESET#
G792SFX
FAN1
FG1
CLK SDA SCL
DGND DGND
SGND1 SGND2 SGND3
5V_S0
12
R281
*Layout* 15 mil
FAN1_VCC
FAN1_FB
1 4 14 16 18 19
NC
5 17
8 10 12
CLK32_G791 18
SMBD_G792 34
SMBC_G792 34
G1
GAP-CLOSE
1 2
G2
GAP-CLOSE
10KR2
FAN1
1 2
12
12
1 2
3
CON3-4
20.D0012.103
C461 SC1000P50V2KX
12
12
C467 SC2200P50V2KX
C468 SC2200P50V2KX
C466 SC2200P50V2KX
?no need gnd?
THERMDP 6
To CPU
THERMDN 6
VGA_THERM_DP 54
To VGA
VGA_THERM_DN 54
THERM_SYS_DP
THERM_SYS_DN
!MOS DELETED!
3
Q10
1
MMBT3904-U1
3904 on system (Thermal Sensor)
2
3D3V_AUX_S5
12
R305 10KR2
CPU_THERMTRIP#6,21
3
D14
1
BAT54-1
12
2
C471
DY
SCD1U16V
DCBATOUT
DY
DY
12
12
R300 100KR2F
R302 51K1R3F
DY
D16
S1N4148-U
QUICK_SDN# MAX807_VDD
12
U19
1
OUT
2
VDD
3
VSS
S-80840CNMC
DY
2
D15
3
BAW56
Dummy when G792 enhanced T8 function
NC NC
5 4
BL3#
T8_RSET:27K SET TO 80°C T8_RSET:20K SET TO 90°C T8_RSET:15K SET TO 100°C
5V_AUX_S5
12
T8_SET 5V_G709_AUX_S5
12
R303 470KR2
R304 20KR3F
U20
1
SET
2
GND OUT#3HYST
G709T1U
VCC
5 4
5V_AUX_S5
12
R301 150R2
By Sourcer requset: Main souce 74.00709.07F Second souce
74.00710.03P
74.06509.07F
74.06510.A7P
12
C470 SC4D7U10V5ZY
Put under CPU Socket
PURE_THRM_SDN#
1
RSMRST# 34,48
U21
1
A
VCC
S5_ENABLE34
2
B GND3Y
NC7S08-U
5
4
3D3V_AUX_S5
S5PWR_ENABLE 43,44,48
<Variant Name>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
Custom
Date: Sheet
THERMAL G792
Bolsena
of
23 58Tuesday, December 28, 2004
SA
Page 24
100 mil
5V_USB0_S0
12
12
12
TC42
SE150U10VM
100 mil
5V_USB1_S0
TC4
SE150U10VM
12
C341
SCD1U
C342
SCD1U
12
12
100 mil
5V_USB2_S0
12
12
TC14
SE100U10VM
C475
SCD1U
12
C639
SC1000P50V2KX
BLUETOOTH MODULE
U60
BLUETOOTH_EN34
?POWER ?A
2
GND
3
NC
4
ON/OFF#
AAT4250-U
BLUE1
10 8
7 6 5 4 3 2 1
9
MOLEX-CON8-2
3D3V_BT_S0
5
IN
1
OUT
BT_AUX BT_GPIO2 BT_GPIO1 BT_LINK_LED
TP117 TPAD30
20.D0012.108
MDC 1.5 CONNECTOR
AC97_DOUT21,22,32
AC97_SYNC21,32
AC97_DIN121 AC97_RST#21,32
12
C476 SC22P50V2JN-1
R315
AC97_DIN1_MDC
12
33R3
5V_S0
C473
SC1000P50V2KX
C472
SC1000P50V2KX
3D3V_S0
3D3V_BT_S0
TP128 TPAD30
MDC1
13
MH1
1 3
5 7 9
11
MH2 17
16
AMP-CONN12A
USB_OC#421
12
DY
EC80 SC1000P50V2KX
OC1# OUT1 OUT2
5V_USB0_S0
8 7 6 5
U115
1
GND
2
VCC
3
EN1#/EN1 EN2#/EN24OC2#
G5258B2
G5258B2 Active Low 1.5A
U118
1
EN
2
FLG
3
GND NC4NC
G525A2
G525A2 Active Low 1.0A
1 2 1 2
R316
100KR2
R188 0R2-0
R185 0R2-0
12
TP81 TPAD30 TP82 TPAD30
12
C477 SC4D7U10V5ZY
DY
DY
DY
12
DY
EC81 SC1000P50V2KX
15 14 2
4 6 8 10 12
18
5V_USB1_S0
8
OUT
7
IN
6
OUT
5
BT_COEX2 31 BT_COEX1 31
USB_PP6 21 USB_PN6 21
3D3V_LAN_S5
AC97_BITCLK 32
USB PORT
USB_OC#01 21
USB_OC#2 21
5V_S0
5V_USB2_S0
5V_USB0_S0
USB_PN021
1
2
TR1
DY
68.03216.20B
L-63UH
4
3
USB_PP021
RN106
2
3
1
4
SRN0-2-U
USB_PN121
1
TR2
L-63UH
4
USB_PP121
RN107
3 4
SRN0-2-U
USB_PN221
1
TR3
L-63UH
4
USB_PP221
RN108
3 4
SRN0-2-U
USB_PN421
1
TR4
L-63UH
4
USB_PP421
RN109
3 4
SRN0-2-U
Put 0 ohm (x 4 pcs )under each L if possible, (for reduce space)
2
DY
68.03216.20B
3
2 1
2
DY
68.03216.20B
3
2 1
2
DY
68.03216.20B
3
2 1
USB_0-
USB_0+
USB_1-
USB_1+
USB_2-
USB_2+
USB_4-
USB_4+
USB1
56
USB_0­USB_0+
5V_USB0_S0
USB_1­USB_1+
5V_USB1_S0
USB_2­USB_2+
5V_USB2_S0
USB_4­USB_4+
<Variant Name>
Title
USB / MDC / BLUETOOTH
Size Document Number Rev A3
Date: Sheet
Bolsena
1 2 3 4
SKT-USB-39-U
single power, not shared
USB2
56
1 2 3 4
SKT-USB-39-U
USB3
56
1 2 3 4
SKT-USB-39-U
USB4
56
1 2 3 4
SKT-USB-39-U
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
of
24 58Tuesday, December 28, 2004
SA
Page 25
A
B
C
D
E
HDD
?direction ok?
PIDE_D[15..0]19
RSTDRV#_518
4 4
PIDE_DREQ19 PIDE_IOW#19 PIDE_IOR#19 PIDE_IORDY19 PIDE_DACK#19,22 PIDE_IRQ1419 PIDE_A119 PIDE_A019 PIDE_CS#019
HDD_LED#_517
DASP#
5V_S0
3 3
5V_S0
R318 4K7R2
1 2
PIDE_D6 PIDE_D5 PIDE_D4 PIDE_D3 PIDE_D2 PIDE_D1 PIDE_D0
12
C478 SC10U10V5ZY
12
C479 SCD1U
By ME requset change P/N: from 20.F0385.044 to 20.F0385.A44
HDD1
44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10
8 6 4
2
SPD-CONN44D-7-U1
20.80175.044
46 43
PIDE_D8PIDE_D7
41
PIDE_D9
39
PIDE_D10
37
PIDE_D11
35
PIDE_D12
33
PIDE_D13
31
PIDE_D14
29
PIDE_D15
27 25 23 21 19 17 15 13 11 9 7 5 3
1 45
PWR TRACE 100mil
12
12
C480 SCD1U
PIDE_IORDY
PIDE_A2 19
PIDE_CS#1 19
TC6 ST47U6D3V-U1
Dummy when use SATA
21
D17
B240LA
5V_S0
12
5V_S0
R319 4K7R2
SIDE_D[15..0]19
CD_AUDR32
SIDE_DREQ19 SIDE_IOR#19
SIDE_DACK#19
?need bay id?
SIDE_A219 SIDE_CS#119
5V_S0
12
C481 SC10U10V5ZY
SIDE_D8 SIDE_D9
SIDE_D11 SIDE_D12 SIDE_D13 SIDE_D14 SIDE_D15
TP83 TP84
TPAD30 TPAD30
12
C482 SCD1U
CDROM
2 4
6
8 10 12 14 16 18 20 22 24 26 28
BAY_ID0
30
BAY_ID1
32 34 36 38 40 42 44 46 48
12
50
C483 SCD1U
ODD1
51 1
3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 52
STC-CONN50-4R
20.80251.050
CSEL
RSTDRV#_5 SIDE_D7 SIDE_D6SIDE_D10 SIDE_D5 SIDE_D4 SIDE_D3 SIDE_D2 SIDE_D1 SIDE_D0
1 2
CD_AUDL 32 CD_AGND 32
SIDE_IOW# 19 SIDE_IORDY 19 SIDE_IRQ15 19 SIDE_A1 19 SIDE_A0 19 SIDE_CS#0 19
R320 4K7R2
SIDE_IORDY
CDROM_LED#_5 17
5V_S0
5V_S0
12
R321 4K7R2
SATA Connector
DY
5V_S0
12
3D3V_S0
12
C484 SCD1U16V
C486 SCD1U16V
Dummy when use IDE
MH1
MH2
23
1 2
3 4 5 6 7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
24
SATA1
DY
SPD-CON22-220.F0614.022
B
C
2 2
12
TC7 ST22U6D3VBM
DY
SATA_TXP019 SATA_TXN019
SATA_RXN019 SATA_RXP019
12
1 1
D18
SSM24-U
2 1
12
TC8
C485
ST22U10VBM-U1
SCD1U16V
DY
DY
DY
DY
A
PIN 49,50 DON'T USE
D
<Variant Name>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
HDD / CDROM / SATA
Size Document Number Rev
A3
Date: Sheet
Bolsena
25 58Tuesday, December 28, 2004
E
of
SA
Page 26
A
B
C
D
E
1 2
1 2
3
3D3V_S0
R327 100R3
R330 10KR2
R332
12
47KR2
?strap for?
PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0
PCI_CBE#0 PCI_CBE#1 PCI_CBE#2 PCI_CBE#3
7411_IDSELPCI_AD22
4 4
PCI_AD[31..0]18,22,29,31
3 3
PCI_CBE#[3..0]18,29,31
PCI_PAR18,29,31
PCI_FRAME#18,29,31
PCI_TRDY#18,29,31 PCI_IRDY#18,29,31
PCI_STOP#18,29,31
PCI_DEVSEL#1 8 ,29,31
PCI_PERR#18,29,31 PCI_SERR#18,29,31 PCI_REQ#118 PCI_GNT#118
CLK33_CBUS18
3D3V_S0
3D3V_S0
PCIRST_BUF#15,18,28,29,31,34,57
TP85 TPAD30
CB_DATA28
CB_CLOCK28
CB_LATCH28
CB_SPKR32
RN111
2 1 4
SRN10KJ
2 2
?in spec is output, why pull?
CBUS_TP1
1 1
A
TP87 TPAD30 TP89 TPAD30
TP88 TPAD30 TP90 TPAD30
CBUS_TP2 CBUS_TP3
CBUS_TP4
W10
V10 U10 R10 N10 V11 U11 R11
W12
V12 U12 N11
W13 W11
W17
T19 P12
W3
U2 V1 V2 U3
W2
V3 U4 V4 V5 U5 R6 P6
W6
V6 U6 R7 V9 U9 R9 N9
W9 W7 W4
P9 V7 R8 U7
W8
N8
W5
V8 U8 U1
T2 P5 R3
T1
T3
R2 N1
L6 N2
L7
E1 E2
M2 M3
L5
L2 K5 K3 K7
L1
L3
U22A
VCCP VCCP
AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
C/BE0# C/BE1# C/BE2# C/BE3#
PAR FRAME# TRDY# IRDY# STOP# DEVSEL# IDSEL PERR# SERR# REQ# GNT# PCLK PRST# GRST# RI_OUT#/PME#
SUSPEND# DATA
CLOCK LATCH SPKROUT
B_USB_EN# A_USB_EN#
SDA SCL
NC#W17 RSVD TEST0
RSVD RSVD RSVD RSVD RSVD RSVD RSVD
PCI7411
U1-1
CARD BUS
U1-10
U1-5
MS_SDIO(DATA0)/SD_DAT0/SM_D0
U1-6
U1-9
UNUSED TERMINALS
B
1 of 4
U1-7
VDPLL_33
VDPLL_15
1394
U1-8
MS_CLK/SD_CLK/SM_EL_WP#
SD/SDIO
PHY_TEST_MA
PC0(TEST1) PC1(TEST2) PC2(TEST3)
MC_PWR_CTRL_0 MC_PWR_CTRL_1
MS_BS/SD_CMD/SM_WE#
MS_DATA3/SD_DAT3/SM_D3 MS_DATA2/SD_DAT2/SM_D2 MS_DATA1/SD_DAT1/SM_D1
SD_CLK/SM_RE#
SD_CMD/SM_ALE
SD_DAT0/SM_D4 SD_DAT1/SM_D5 SD_DAT2/SM_D6 SD_DAT3/SM_D7
SD_WP/SM_CE
SM_PHYS_WP#
MFUNC0 MFUNC1 MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6
CLK_48
AVDD AVDD AVDD
VSSPLL
VSSPLL
TPBIAS0
TPA0P TPA0N
TPB0P TPB0N
CPS CNA
AGND AGND AGND
TPBIAS1
TPA1P TPA1N
TPB1P TPB1N
SD_CD# MS_CD# SM_CD#
SM_CLE SM_R/B#
R0 R1
XO
XI
N3
INTA#
M5
INTB#
P1
INTC#
P2 P3
INTD#
CB_MFUNC5
N5 R1
M1
R13 R14 V17
VDPLL
V19 P14
7420_FILTER0
T18 T17
1394_R0
U18
1394_R1
U19 U15 V15
W15 V14
W14
1394_PHYTEST
R17 M11 P15
R19 R18
R12 U13 V13
N12 U14 U16
U17 V18
W18 V16
W16
1394_CNA 1394_XO
1394_XI
1394_TPBIAS1
?in spec is output, why pull?
MC_PWR_CTRL-0
F1
MC_PWR_CTRL-1
F2
E3 F5 F6 G5 F3
H5 G3 G2
G1 J5 J3
H3 J6 J1 J2
H7 J7 K1 K2
C
R322
1 2
4K7R2
CLK48_CARDBUS 3
1 2
C487
1 2
SCD1U
R324
1 2
6K34R3
1394_TPBIAS0 28 1394_TPA0P 28
1394_TPA0N 28 1394_TPB0P 28
1394_TPB0N 28
1 2
X5
X-24D576M-2
1 2
12
C495 SCD1U
TP86 TPAD30
SD_CD# 28
MS_CD# 28 SM_CD# 28 MS_CLK 28 MSCBS 28
MS_D3 28 MS_D2 28 MS_D1 28
MSCSDIO 28 SDCCLK 28
SDCCMD 28 SM_D4 28
SM_D5 28 SM_D6 28 SM_D7 28
SD_WP 28 SM_CLE 28 SM_R# 28 SM_PHYS_WP# 28
R323 0R2-0
R325 4K7R2
1 2
82.30023.181
3D3V_PLL_S0
R326 4K7R2
C488
1 2
SC22P50V2JN-1
C492
1 2
SC22P50V2JN-1
MS/MS_pro
INT_PIRQE# 18 INT_PIRQF# 18,31 INT_PIRQG# 18 P_SERIRQ 18,34,37,57
3D3V_S0
PM_CLKRUN# 18,29,31,34,37
3D3V_S0
3D3V_S0
2
14
RN110
SRN10KJ
3
1
G
INTA# CARBUS 1 INTB# CARBUS 2 INTC# 1394 INTD# NO USE
D
Q11 2N7002
S
2 3
XD
MC_PWR_ CTRL 28
MS/MS_pro
SM_D[4..7] 28 MS_D[1..3] 28
D
Bypass/Decupoling Capacitors Should be places as close to PCI7411 as possible
3D3V_S0
12
C489 SC1000P50V2KX
3D3V_S0
12
C493 SC1000P50V2KX
R335
1 2
GAP-CLOSE-PWR
<Variant Name>
Title
TI_PCI7411(1 of 2)
Size Document Number Rev
A3
Date: Sheet
12
C490 SCD1U
12
C494 SCD1U
12
C497 SC10U10V5ZY
Bolsena
12
C491 SCD1U
12
C496 SCD1U
3D3V_PLL_S03D3V_S0
12
C498 SC1000P50V2KX
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
E
12
C499 SC1U10V3KX
26 58Tuesday, December 28, 2004
of
SA
Page 27
A
A5 A11
D1 C1 D3 C2 B1 B4 A4 E6 B5 C6 B6 G9 C7 B7 A7 A10 E11 G11 C11 B11 C12 B12 A12 E12 C13 F12 A13 C14 E13 A14 B14 E14
C5 F9 B10 G12
G10 C8
A8 B8 A9 C9 E10
F10 B3
E7 B9
B2 C3 E9
C4 A6
A2 C15
E5 A3 E8
B13 D2 C10
VCC_ASKT_S0
1 2
1 2
U22B
4 4
U1-2
3 3
A_CSTSCHG/A_BVD1(STSCHG#/RI#)
2 2
PCI7411
2 of 4
A_CAD31/A_D10
A_CAD30/A_D9 A_CAD29/A_D1 A_CAD28/A_D8 A_CAD27/A_D0 A_CAD26/A_A0 A_CAD25/A_A1 A_CAD24/A_A2 A_CAD23/A_A3 A_CAD22/A_A4 A_CAD21/A_A5 A_CAD20/A_A6
A_CAD19/A_A25
A_CAD18/A_A7 A_CAD17/A_A24 A_CAD16/A_A17
A_CAD15/A_IOWR#
A_CAD14/A_A9
A_CAD13/A_IORD#
A_CAD12/A_A11
A_CAD11/A_OE#
A_CAD10/A_CE2#
A_CAD9/A_A10
A_CAD8/A_D15
A_CAD7/A_D7
A_CAD6/A_D13
A_CAD5/A_D6
A_CAD4/A_D12
A_CAD3/A_D5
A_CAD2/A_D11
A_CAD1/A_D4 A_CAD0/A_D3
CARDBUS A
A_CC/BE3#/A_REG#
A_CC/BE2#/A_A12
A_CC/BE1#/A_A8
A_CC/BE0#/A_CE1#
A_CPAR/A_A13
A_CFRAME#/A_A23
A_CTRDY#/A_A22
A_CIRDY#/A_A15
A_CSTOP#/A_A20
A_CDEVSEL#/A_A21
A_CBLOCK#/A_A19
A_CPERR#/A_A14
A_CSERR#/A_WAIT#
A_CREQ#/A_INPACK#
A_CGNT#/A_WE#
A_CCLKRUN#/A_WP(IOIS16#)
A_CCLK/A_A16
A_CINT#/A_READY(IREQ#)
A_CRST#/A_RESET
A_CAUDIO/A_BVD2(SPKR#)
A_CCD1#/A_CD1# A_CCD2#/A_CD2#
A_CVS1/A_VS1# A_CVS2/A_VS2#
A_RSVD/A_D14
A_RSVD/A_D2
A_RSVD/A_A18
VCCA VCCA
B
C500 SCD01U16V2KX
CBB_D10 28 CBB_D9 28 CBB_D1 28 CBB_D8 28 CBB_D0 28 CBB_A0 28 CBB_A1 28 CBB_A2 28 CBB_A3 28 CBB_A4 28 CBB_A5 28 CBB_A6 28 CBB_A25 28 CBB_A7 28 CBB_A24 28 CBB_A17 28
CBB_A9 28 CBB_A11 28
CBB_A10 28 CBB_D15 28 CBB_D7 28 CBB_D13 28 CBB_D6 28 CBB_D12 28 CBB_D5 28 CBB_D11 28 CBB_D4 28 CBB_D3 28
CBB_A12 28 CBB_A8 28
CBB_A13 28 CBB_A23 28
CBB_A22 28 CBB_A15 28 CBB_A20 28 CBB_A21 28 CBB_A19 28
CBB_A14 28
R337 33R2
CBB_D14 28 CBB_D2 28 CBB_A18 28
CBB_IOWR# 28
CBB_IORD# 28
CBB_OE# 28
CBB_CE2# 28
CBB_REG# 28
CBB_CE1# 28
CBB_WAIT# 28 CBB_INPACK# 28
CBB_WE# 28
CBB_BVD1# 28 CBB_WP 28
CBB_A16 28
CBB_RDY 28 CBB_RESET 28
CBB_BVD2# 28 CBB_CD1# 28
CBB_CD2# 28 CBB_VS1# 28 CBB_VS2# 28
CBB_D[0..15] 28 CBB_A[0..25] 28
U22C
U1-3
CARDBUS B
PCI7411
3 of 4
RSVD RSVD
RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
RSVD RSVD RSVD RSVD
RSVD RSVD
RSVD RSVD RSVD RSVD RSVD
RSVD RSVD
RSVD RSVD
RSVD RSVD RSVD
RSVD RSVD RSVD
RSVD RSVD RSVD RSVD
RSVD RSVD RSVD
D19 K19
B15 A16 B16 A17 C16 D17 C19 D18 E17 E19 G15 F18 H14 H15 G17 K17 L13 K18 L15 L17 L18 L19 M17 M14 M15 N19 N18 N15 M13 P18 P17 P19
F15 G18 K14 M18
K13 G19
H17 J13 J17 H19 J19
J18 B18
E18 J15
F14 A18 H18
B19 F17 C17
N13 B17 C18 F19
N17 A15 K15
C
12
3D3V_S0
C501 SCD1U16V
D
4 of 4
M10 M12
H10 H11 H12
K12
G13 H13
K10 K11
L10 L11 L12
U22D
H8
VCC
H9
VCC VCC VCC VCC
J8
VCC
M7
VCC
J12
VCC
M9
VCC VCC VCC
K8
VCC VCC
N7
VCC
G7
GND
G8
GND GND GND
J9
GND
J10
GND
J11
GND
K9
GND GND GND
L8
GND
L9
GND GND GND GND
M8
GND
M19
VR_PORT
H1
VR_PORT
H2
VR_EN#
POWER TERMINALS
U1-4
12
Place it near to chip
12
C502 SCD1U16V
3D3V_S0
C503 SCD1U16V
E
12
R336 10KR2
DY
12
R338 0R2-0
from spec : this pin is active low
PCI7411
1 1
A
B
C
D
<Variant Name>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
TI_PCI7411(2 of 2)
Size Document Number Rev
A3
Date: Sheet
Bolsena
27 58Tuesday, December 28, 2004
E
of
SA
Page 28
A
U
B
C
D
E
PCMCIA Socket
PCH1
1
4 4
VCC_ASKT_S0
12
12
C507
C506
SC10U10V5ZY
SC10U10V5ZY
3 3
CBB_A16
2 2
12
C509 SC1000P50V2KX
VPP_ASKT_S0
12
C511 SCD1U
12
R346 DUMMY-R2
DY
Place close to pin 19.
12
C518 DUMMY-C2
DY
CBB_D3 CBB_D4
CBB_D11 CBB_D5 CBB_D12 CBB_D6 CBB_D13 CBB_D7 CBB_D14
CBB_D15
12
C508 SCD1U
CBB_D0 CBB_D8 CBB_D1 CBB_D9 CBB_D2 CBB_D10
Clock AC termination
CBB_A10
CBB_A11 CBB_A9 CBB_A8
CBB_A17 CBB_A13 CBB_A18 CBB_A14 CBB_A19
CBB_A20 CBB_A21
CBB_A16 CBB_A22 CBB_A15 CBB_A23 CBB_A12 CBB_A24 CBB_A7 CBB_A25 CBB_A6
CBB_A5 CBB_A4 CBB_A3 CBB_A2 CBB_A1 CBB_A0
CBB_CD1#
CBB_CE1#
CBB_CE2# CBB_OE# CBB_VS1#
CBB_IORD# CBB_IOWR#
CBB_WE# CBB_RDY
CBB_VS2# CBB_RESET CBB_WAIT# CBB_INPACK# CBB_REG# CBB_BVD2# CBB_BVD1#
CBB_WP CBB_CD2#
33MHz clock for 32-bit Cardbus card I/F
1 1
A
VCC_ASKT_S0
DY
47K
12
R347 DUMMY-R2
12
C522 SCD01U16V2KX
35
2
36
3
37
4
38
5
39
6
40
7
41
8
42
9 43 10 44 11 45 12 46 13 47 14 48 15 49 16 50 17 51 18 52 19 53 20 54 21 55 22 56 23 57 24 58 25 59 26 60 27 61 28 62 29 63 30 64 31 65 32 66 33 67 34 68
PCMCIA-12-U
62.10024.131
B
Cardbus I/F
CBB_D[0..15] 27 CBB_A[0..25] 27
CBB_IORD# 27 CBB_IOWR# 27 CBB_OE# 27 CBB_WE# 27 CBB_REG# 27
CBB_RESET 27
CBB_WAIT# 27
CBB_INPACK# 27
CBB_CE1# 27 CBB_CE2# 27
CBB_BVD1# 27 CBB_BVD2# 27
CBB_CD1# 27
CBB_CD2# 27 CBB_VS1# 27 CBB_VS2# 27
PC1
1 3
CARDBUS-SKT42
21.H0056.011
MC_PWR_ CTRL26
CBB_RDY 27
CBB_WP 27
2 4
1394 Connector
1394_TPA0P26
1394_TPA0N26
1394_TPB0P26
1394_TPB0N26
1394_TPBIAS026
Power switch
3D3V_S0
POWER SWITCH
U76
2
GND
3
NC
4
ON/OFF#
AAT4250-U
74.04250.03F
C
5V_S0 VPP_ASKT_S0
12
C512 SCD1U16V
12
12
C983 SC1U10V3ZY
MSCSDIO26
IN
OUT
12
R339 56R3F
Close to the cardbus Controller.
CB_DATA26 CB_CLOCK26 CB_LATCH26 PCIRST_BUF#15,18,26,29,31,34,57
5V_S0
12
C513 SC4D7U10V5ZY
12
DY
3D3V_CR_S0
12
C710
C711
SCD1U16V
SCD1U16V
MSCSDIO MS_D1 MS_D2 MS_D3
MS_D1 MS_D2 MS_D3 MSCBS
MS_D1 MS_D2 MS_D3 SM_D4 SM_D5 SM_D6 SM_D7
SM_CD# MSCSDIO
3D3V_S0 3D3V_CR_S0
5 1
12
12
C982 SC1U10V3ZY
12
R340 56R3F
12
C504 SC1U10V3KX
1 2
12
C514 SCD1U16V
C981 SCD1U16V
12
1394_TPBIBS
12
R344 10KR2
C515 SC1U10V3ZY
CARD1
40
XD-VCC
29
S.M-VCC
20
MS-VCC
9
SD-VCC
7
SD-DAT0
6
SD-DAT1
12
SD-DAT2
11
SD-DAT3
15
MS-DATA0
14
MS-DATA1
16
MS-DATA2
18
MS-DATA3
33
S.M/XD-D1
32
S.M/XD-D2
31
S.M/XD-D3
21
S.M/XD-D4
22
S.M/XD-D5
23
S.M/XD-D6
24
S.M/XD-D7
25
S.M-LVD
30
S.M-CD#
34
S.M-D0
SKT-MEMO-9-U1
D
12
R341
R342
56R3F
56R3F
12
C505
R343
SC220P50V2KX-U
4K99R3F
64.49915.651
U23
3
DATA
4
CLOCK
5
LATCH
12
RESET#
21
SHDN#
13
3.3V
1
5V
2
5V
7
12V
20
12V
11
GND
25
GND
TSP2220A
SM-CD-COM
SM-CD-SW
SM-WP-SW
SD-CD-COM
SD-CD-SW
SD-WP-SW
S.M#/XD-CLE
S.M#/XD-ALE S.M#/XD-WE
S.M#/XD-CE S.M#/XD-RE
S.M#/XD-R/B
S.M/XD-WP-IN
TR5
1
2 1
2
ACM2012-900-2P-T
4
TR6
3
ACM2012-900-2P-T
4
3
TPA0+ TPA0­TPB0+ TPB0-
1394
4 3 2 1
AMP-CONN4A
20.90036.001
By ME requset SKT2 P/N: Main 20.90036.001 Second 22.10245.141
VCC_ASKT_S0
9
AVCC
10
AVCC
8
AVPP
15
OC#
24
NC
23
NC
22
NC
19
NC
18
NC
17
NC
16
NC
14
NC
6
NC
2 3 43
13
MS-BS
17
MS-INS
MS-SCLK
RSV#4
XD-CD
SD-CLK
SD-CMD
GND GND GND GND
MS_CLK-R
19 4
39 41
42
SD_WP_R SD_WP
5 8 10
38 37 36 28 27 26 35
46 45 44 1
<Variant Name>
Title
Size Document Number Rev
A3
Date: Sheet
SM_CD#
SM_PHYS_WP#
1 2
1 2
MS_CLK
SDCCMD
MSCBS
1 2
1 2 1 2
DY
PCMCA / 1394 / CARD READER
Bolsena
12
R562 0R2-0
SM_CD# 26
R885 0R2-0
R847 0R2-0
R884 0R2-0
MS_CLK-R
R848 0R2-0
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
C510 SCD1U16V
VCC_ASKT_S0
SD_CD# 26
SM_CLE 26
SD_WP 26 SDCCLK 26 SM_R# 26 SM_PHYS_WP# 26
E
VPP_ASKT_S0
12
MSCBS 26 MS_CD# 26 MS_CLK 26
SM_D[4..7] 26 MS_D[1..3] 26
28 58Tuesday, December 28, 2004
6
5
12
R345 100KR2
C516 SCD1U16V
SDCCMD 26
of
12
SA
C517 SC4D7
DY
Page 29
A
B
C
D
E
B
12
GIGA
123
VSS
CLOSE TO LAN CHIP
12
GIGA
R359 49D9R3F
12
GIGA
C526 SCD01U50V3KX
122
121
XTAL2
R360 49D9R3F
XTAL1
120
AVDDH
118
119
GND
VSSPST
PCI_CBE#[3..0]18,26,31
PCI_AD[31..0]18,22,26,31
10/100
RTL_LED1#
RTL_LED2#
ACT_LED# LDVDD RTL_LED1# RTL_LED2# 1G_LED# LAN_EESK LDVDD LAN_EEDI LAN_EEDO 3D3V_LAN_S5 LAN_EECS_3
PCI_AD0 PCI_AD1
110
EESK
109
VDD18
64
EEDI
105
106
107
108
EECS
EEDO
VDD33
LDVDD PCI_IRDY# PCI_FRAME# PCI_CBE#2 PCI_AD16 PCI_AD17 PCI_AD18
PCI_AD19 LDVDD PCI_AD20
LANWAKE
104
103
PCIAD0
PCIAD1
PCIAD2
VSSPST
GND
VDD18 PCIAD3 PCIAD4 PCIAD5 PCIAD6
VDD33 PCIAD7
CBEB0
VSSPST
PCIAD8 PCIAD9
M66EN
PCIAD10 PCIAD11 PCIAD12
VDD33
PCIAD13 PCIAD14
VSSPST
GND
PCIAD15
VDD18
CBEB1
PAR
SERR#
NC#74
GND
NC#72 VDD33 PERR# STOP#
DEVSEL#
TRDY#
VSSPST
CLKRUN#
111
116
112
117
115
114
113
GND
LED0
LED1
LED2
LED3
VDD18
1
2
3 4
10/100
ACT_LED# 30,57
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
PCI_IRDY# 18,26,31 PCI_FRAME# 18,26,31
3D3V_LAN_S5
C
R834
1 2
0R2-0
GIGA
D3
RB731U
1 2
PCI_AD2
LDVDD PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6
PCI_AD7 PCI_CBE#0
PCI_AD8 PCI_AD9
PCI_AD10 PCI_AD11 PCI_AD12
PCI_AD13 PCI_AD14
PCI_AD15 LDVDD PCI_CBE#1 PCI_PAR PCI_SERR#
PCI_PERR# PCI_STOP#
PCI_DEVSEL# PCI_TRDY#
PM_CLKRUN#
100M_LED#
6
1G_LED#
5
10M_LED#
R835 0R2-0
3D3V_LAN_S5
Dummy when use Giga
CTRL25
CTRL18
3
0R2-0 R409
1 2
1 2
R435 0R2-0
Dummy when use 10/100
PCI_PAR 18,26,31 PCI_SERR# 18,26,31
PCI_PERR# 18,26,31 PCI_STOP# 18 ,26,31 PCI_DEVSEL# 18,26,31 PCI_T R D Y # 18,26,31
PM_CLKRUN# 18,26,31,34,37
GIGALAN: RTL8110SBL 10/100 LAN:RTL8100C
3D3V_S5
1 2
100M_LED# 30
U107
1 2
BAT54C-L
10M_LED# 30,57
3D3V_LAN_S5
3D3V_LAN_S5
1
G3
GAP-CLOSE-PWR
3D3V_LAN_S5 3D3V_LAN_S5
12
C532 SC10U10V5ZY
3
Q12 BCP69T1-U
2
12
C541 SCD1U
3D3V_LAN_S5
DY
R361 10KR2
1 2
12
C533 SCD1U
C542 SCD1U
R362 3K6R3D
1 2
12
12
C543 SCD1U
C534 SCD1U
12
12
C544 SCD1U
12
12
Dummy when use 10/100
<Variant Name>
Title
Size Document Number Rev
A3
D
Date: Sheet
LAN_X2
X6
X-25MHZ-11-U
LAN_EECS_3
LAN_EEDO
12
C537 SCD1U
12
C547 SCD1U
3D3V_LAN_S5
3
Q14
1
BCP69T1-U
2
12
1 2
1 2
12
C551 SC10U10V5ZY
C535 SCD1U
C545 SCD1U
CTRL25
LAN_X1
LAN_EESK LAN_EEDI
12
LDVDD
12
C536 SCD1U
C546 SCD1U
RTL8110SBL/RTL8100C
Bolsena
C527
1 2
SC27P50V2JN
C530
1 2
SC27P50V2JN
3D3V_LAN_S5
U26
1
CS
2
SK
3
DI
4
DO
M93C46-W-3
45 Ohm, 600mA
L21 0R3-U
12
C548 SCD1U
ORG GND
LAVDDH
45 Ohm, 600mA
1 2
C549 SCD1U
VCC
8
12
7
DC
6 5
12
12
C539
C538
SCD1U
SCD1U
LDVDD_A
L22 0R3-U
12
Dummy when use Giga
12
R369 0R3-U
LAVDDL
12
29 58Tuesday, December 28, 2004
C554 SCD1U
12
C555 SCD1U
of
12
12
C552
C553
SCD1U
SCD1U
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
E
C531 SCD1U
12
C550 SCD1U
C540 SCD1U
SA
12
R354 49D9R3F
C525 SCD01U50V3KX
TGP0 TGN0 LAVDDL
TGP1 TGN1 LAVDDL CTRL25
LAVDDH
LV_12P
TGP2 TGN2
LAVDDL TGP3
TGN3 LAVDDL
ISOLATE# LDVDD INT_PIRQH#
CLK33_LAN PCI_GNT#2 PCI_REQ#2 PME#_LAN LDVDD PCI_AD31 PCI_AD30
PCI_AD29 PCI_AD28
R370 100R3
TGP1
12
R355 49D9R3F
MID1XMID0X MID2X MID3X
12
U27
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
RTL8110SBL
3D3V_LAN_S5
LAN_IDSELPCI_AD23
TGP0 TGN0 TGN1
12
R353 49D9R3F
4 4
12
3 3
TGP030
TGN030
TGP130
TGN130
Dummy when use 10/100
LAVDDH
LDVDD
1 2 1 2
R364 0R2-0 R365 0R2-0
Dummy when use Giga
TGP230
TGN230
2 2
3D3V_S0
PME#_SB21,34
1 1
1 2 1 2
INT_PIRQH#18
3D3V_LAN_S5
PCIRST_BUF#15,18,26,28,31,34,57
CLK33_LAN18,22
PCI_GNT#218
PCI_REQ#218
CLK33_LAN
TGP330
TGN330
R366 1KR2 R367 15KR3
1 2
R368 0R2-0
12
C556 SC10P50V2JN-1
1 2
A
12
R356 49D9R3F
C528 SCD01U50V3KX
LAVDDH LAN_X1 LAN_X2 CTRL18 LDVDD_A
1 2
RSET
MDI0+ MDI0­AVDDL VSS MDI1+ MDI1­AVDDL CTRL25 VSS AVDDH HSDAC+ HSDAC­VSS MDI2+ MDI2­AVDDL VSS MDI3+ MDI3­AVDDL VSSPST GND ISOLATE# VDD18 INTA# VDD33 PCIRST# PCICLK GNT# REQ# PME# VDD18 PCIAD31 PCIAD30 GND PCIAD29 PCIAD28 VSSPST
TGP2 TGN2
R363 2D49KR3
128
127
VSS
RSET
PCI_AD27 PCI_AD26
PCI_AD25 PCI_AD24 PCI_CBE#3 LDVDD LAN_IDSEL
PCI_AD23 PCI_AD22 PCI_AD21
TGP3 TGN3
12
12
GIGA
GIGA
R357
R358
49D9R3F
49D9R3F
12
GIGA
C529 SCD01U50V3KX
126
124
125
VSS
CTRL18
AVDD18
PCIAD2739PCIAD2640VDD3341PCIAD2542PCIAD2443CBEB344VDD1845IDSEL46PCIAD2347GND48PCIAD2249PCIAD2150VSSPST51GND52PCIAD2053VDD1854PCIAD1955VDD3356PCIAD1857PCIAD1758PCIAD1659CBEB260FRAME#61GND62IRDY#63VDD18
Page 30
A
Green - 10Mbps/802.11b
Link: YellowActivity:
Orange - 100Mbps/802.11a Yellow - 1Gbps
TIP RING
10M_LED#29,57
3D3V_LAN_S5
4 4
100M_LED#29
3D3V_LAN_S5
ACT_LED#29,57
10M_LED# CONN_PWR
R371
12
470R3
100M_LED# 10M_LED# TDP_RJ45-1 TDN_RJ45-2 RDP_RJ45-3 RJ45-4 RJ45-5 RDN_RJ45-6 RJ45-7 RJ45-8 CONN_PWR_B2
R372
12
470R3
ACT_LED#
RJ11_1 RJ11_2
RJ45_1 RJ45_2 RJ45_3 RJ45_4 RJ45_5 RJ45_6 RJ45_7 RJ45_8
LAN1
9
A1 A2 A3
B1 B2
10
SKT-RJ45+RJ11-2
?LED COLOR?
100M_LED# ACT_LED#
C640
SC1000P50V2KX
22.10177.721
34
MDCW1 MLXCON2
1 2
3 3
L24
1 2
BLM18HG601SN1D
L23
1 2
BLM18HG601SN1D
10/100M Lan Transformer
S_TTGP0 S_TTGN0
MCT3 MCT4 V_DAC
7 8
6 14 11
3
U29
TD+ TD-
CT CT CT CT
XFORM-112
RINGRING_MDC
DY
Dummy when use Giga
2 2
GIGA Lan Transformer
S_TGP3 S_TGN3
S_TGP2 S_TGN2
S_RTGP1 S_RTGN1
Dummy when use 10/100
R373
1 2
LAVDDL
1 1
0R2-0
GIGA
GIGA
12
12
C558 SCD01U50V3KX
For 10/100 Cap. changeto SCD1U
A
S_TTGP0 S_TTGN0 TDN_RJ45-2
V_DAC
GIGA
12
C559 SCD01U50V3KX
12
C560 SCD01U50V3KX
U30
2
TD1+
3
TD1-
5
TD2+
6
TD2-
8
TD3+
9
TD3-
11
TD4+
12
TD4-
1
TCT1
4
TCT2
7
TCT3
10
TCT4
XFORM-114
C561
68.H5015.301
SCD01U50V3KX
Dummy when use 10/100
MX1+
MX1-
MX2+
MX2-
MX3+
MX3-
MX4+
MX4-
MCT1 MCT2 MCT3 MCT4
1 2
C562
12
SC1KP2KV C563
SC1000P50V2KX
B
12
12
C658
TIPTIP_MDC
TX+
TX-
RD+
RD­RX+
RX-
C661
SC1000P50V2KX
SC1000P50V2KX
TDP_RJ45-1
10
TDN_RJ45-2
9
S_RTGP1
1
S_RTGN1
2
RDP_RJ45-3
16
RDN_RJ45-6
15
12
By Sourcer requset change P/N: From 68.H0013.301 To 68.0H80P.301
By Sourcer requset change P/N: From 68.H5015.301 To 68.02402.30A
RJ45-7
23
RJ45-8
22
RJ45-4
20
RJ45-5
19
RDP_RJ45-3
17
RDN_RJ45-6
16
TDP_RJ45-1
14 13
MCT1
24
MCT2
21
MCT3
18
MCT4
15
RN69
123
LAN_TC_GND MCT1 MCT2
SRN75J
DY
B
1.route on bottom as differential pairs.
2.Tx+/Tx- are pairs. Rx+/Rx- are pairs.
3.No vias, No 90 degree bends.
4.pairs must be equal lengths.
5.6mil trace w id th ,1 2mi l separation.
6.36mil between pairs and any other trace.
7.Must not cross ground moat,except RJ-45 moat.
RJ45-7 RJ45-8 RJ45-4 RJ45-5
678
10/100
RN70
123
SRN0-1-U
LAN
4 5
678
4 5
Dummy when use Giga
C
Function An to nB1 An to nB2
TGN029 TGP029 TGN129 TGP129 TGN229 TGP229 TGN329 TGP329
SEL
L H
D
LAN switch
2 4
8 10 15 17 21 23
3
5
7
9 11 13 16 18 20 22 27 30 33 37 40 43 46
U28
A0 A1 A2 A3 A4 A5 A6 A7
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
PI3L301DA
0B1 1B1 2B1 3B1 4B1 5B1 6B1 7B1
0B2 1B2 2B2 3B2 4B2 5B2 6B2 7B2
SEL
VDD VDD VDD VDD VDD
E
S_TTGN0
48
S_TTGP0
47
S_RTGN1
42
S_RTGP1
41
S_TGN2
35
S_TGP2
34
S_TGN3
29
S_TGP3
28
D_TTGN0
45
D_TTGP0
44
D_RTGN1
39
D_RTGP1
38
D_TGN2
32
D_TGP2
31
D_TGN3
26
D_TGP3
25
14
NC
DOCK_ON_1
24
1 6 12 19 36
SYSTEM
3D3V_LAN_S5
12
D_TTGN0 57 D_TTGP0 57 D_RTGN1 57 D_RTGP1 57 D_TGN2 57 D_TGP2 57 D_TGN3 57 D_TGP3 57
DOCK_ON_1 57
C557 SCD1U10V2MX-1
DOCK
Dummy when no EZ4
TGN0 TGP0 TGN1 TGP1 TGN2 TGP2 TGN3 TGP3
RN68
1 2 3 4 5 6 7 8 9
SRN10J-3
DY
16 15 14 13 12 11 10
S_TTGN0 S_TTGP0 S_RTGN1 S_RTGP1 S_TGN2 S_TGP2 S_TGN3 S_TGP3
Dummy when use EZ4
<Variant Name>
Wistron Corporation
DY
Title
LAN CONN
Size Document Number Rev
A3
C
D
Date: Sheet
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Bolsena
E
30 58Tuesday, December 28, 2004
SA
of
Page 31
A
B
C
D
E
MINI-PCI
4 4
3D3V_S0
PCI_AD[31..0]18,22,26,29 PCI_CBE#[3..0]18,26,29
12
C564 SC4D7U10V5ZY
12
DY
MINI1
125 1 2 3
5 7
80211_ACTIVE
H=Enable L=Disable
3 3
BT_COEX224
3D3V_S0
12
R376 10KR2
PCI_PERR#18,26,29
2 2
1 1
A
WIRELESS_EN34
3D3V_S0
CLK33_MINI18,22
PCI_IRDY#18,26,29
PM_CLKRUN#18,26,29,34,37
PCI_SERR#18,26,29
5V_S0
WIRELE SS_EN
TP91
MINI_P_IRQF#
TPAD30
PCI_AD31 PCI_AD29
PCI_AD27 PCI_AD25
PCI_CBE#3 PCI_AD24 PCI_AD23
PCI_AD21
PCI_AD17 PCI_CBE#2
PCI_CBE#1 PCI_AD14
PCI_AD12 PCI_AD10
PCI_AD8 PCI_AD7
PCI_AD5 PCI_AD3 PCI_AD1
B
9
11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97
99 101 103 105 107 109 111 113 115 117 119 121 123
MH1
4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 MH2 126
PCMCIA-SKT-7
62.10071.001
RINGTIP
(VCC)
(M66EN)
5V_S0
MINI_P_IRQF#
PME#_MINI PCI_AD30 PCI_AD28
PCI_AD26 MINI_IDSEL PCI_AD22
PCI_AD20PCI_AD19 PCI_AD18
PCI_AD16
PCI_AD15 PCI_AD13 PCI_AD11
PCI_AD9 PCI_CBE#0
PCI_AD6 PCI_AD4 PCI_AD2 PCI_AD0
12
DY
C568 SC4D7U10V5ZY
1 2
C
R374 0R2-0
12
C565 SCD1U
12
C566 SCD1U
DY
C780
SCD1U
INT_PIRQF# 18,26
PCIRST_BUF# 15,18, 26,28,29,34,57 PCI_GNT#0 18PCI_REQ#018
BT_COEX1 24
TP92 TPAD30
PCI_AD21
R375
1 2
100R3
PCI_PAR 18,26,29
PCI_FRAME# 18,26,29 PCI_T R D Y # 18,26,29 PCI_STOP# 18 ,26,29
PCI_DEVSEL# 18,26,29
12
C567 SCD1U
<Variant Name>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
MINI-PCI
Size Document Number Rev
A3
D
Date: Sheet
Bolsena
31 58Tuesday, December 28, 2004
E
SA
of
Page 32
5
AC97_BITCLK_ALL
R377
AC97_BITCLK_SB21
D D
AC97_BITCLK24
1 2
63.47034.151
1 2
63.47034.151
47R3
R380 47R3
3D3V_S0
12
R382 10KR2
U31
5
VCC
4
Y
NC7SZ08-U
R378
1 2
DUMMY-R3
1
A
2
B
3
GND
BITCLK_BUFF
AC97_RST#
DY
CODECVREF
12
C572 SCD1U
12
C573 SC1000P50V2KX
12
C576 SC1000P50V2KX
12
C577 SCD1U
12
C578 SC1U10V3KX
12
12
C579 SCD1U
VREFOUT2
ADAF2 ADAF1
VREFOUT1
C580 SC10U10V5ZY
4
5V_S0 5V_AUDIO_S0
U32
1
SHDN#
2
GND
3
C570 SC1U10V3KX
AUD_AGND
12
IN
G913C-U
C574 SCD1U
12
C575 SCD1U
12
SET OUT
5V_AUDIO_S0
5 4
3D3V_S05V_AUDIO_S0
12
5VA_SET
12
12
C581 SCD1U
3
12
C571 SC10U10V5ZY
12
C582
C583
SCD1U
SCD1U
12
R379 28K7R3F
C569 SC22P50V2JN-1
12
R381 10KR3F
AUD_AGND
2
1
DY
R383
1 2
1 2
R384 0R3-U
R385
12
22R3 R386 0R2-0
R387
12
33R3 R388 10KR2
0R2-0
C584
1 2
SC22P50V2JN-1
DY
C585
1 2
SC22P50V2JN-1
DY
SPDIF 33,57
C332
1 2
DUMMY-C2
EAPD 33
AC97_DIN0 21 AC97_DOUT 21,22,24
XTSEL HI: USE 24.576M XTAL XTSEL LOW: USE 14.318M CLK FROM CLK GEN
AC97_SYNC 21,24 AC97_RST# 21,24
32
VRDA31VRAD
37
AUD_AGND
28
34
27
VREF
VREFOUT
FRONT-MIC
MONO-OUT-R
CEN-OUT43LFE-OUT
44
PC-BEEP12PHONE
33
NC#33
13
40
NC#40
38
AVDD25AVDD
AGND26AGND
42
9
VDD1VDD
SPDIFI/EAPD
GND4GND
7
XTL-IN
XTL-OUT
SPDIFO
SDIN
SDOUT
JD0/GPIO0
XTLSEL
BITCLK
SYNC
RESET#
XTALIN_CODEC
2
XTALOUT_CODEC
3
SPDIF_OUT
48 47
8 5
45 46
AC97_CBITCLK BITCLK_BUFF
6 10
11
AC97_DATIN
X7
X-24D576MHZ-13
DY
1 2
DY
1 2
1 2
DY
DY
C C
DY
U33
30
AFILT129AFILT2
14
AUX-L
15
AUX-R
16
JD2
17
C587
AUD_LINL33
AUD_LINR33
AUD_LOL33
AUD_LOR33
AUD_MICIN33
B B
1 2
SC1U10V3KX
C586
1 2
SC1U10V3KX
12
C588 SC1000P50V2KX
AUD_AGND AUD_AGND
12
12
AUDLINL AUDLINR
C589 SC1000P50V2KX
C590 SC1U10V3ZY
AUD_MICIN1
JD1/GPIO1
39
SURR-OUT-L
41
SURR-OUT-R
23
LINE-L
24
LINE-R
35
FRONT-OUT-L
36
FRONT-OUT-R
21
MIC1
22
MIC2
ALC655-U
CD-L18CD-R
20
19
CD-GND
CLK14_AUDIO 3
G4
1 2
GAP-CLOSE
G6
1 2
GAP-CLOSE
G5
1 2
GAP-CLOSE
G7
1 2
GAP-CLOSE
AUD_AGND
AUD_AGND
AUD_AGND
AUD_AGND
R392 100KR2
CDAUDL
CDAGND
CDAUDR
12
12
R393 100KR2
AUD_AGND
R394 100KR2
1 2
1 2
1 2
R389
CD_AUDL25
CD_AGND25
CD_AUDR25
A A
1 2
75R3F
R390
1 2
GAP-CLOSE-PWR
R395
1 2
75R3F
5
12
C591 SC1U10V3KX
C592 SC1U10V3KX
C594 SC1U10V3KX
AUD_SYS_BEEP
CDAUD_L
CDAUD_GND
CDAUD_R
AUD_AGND
AUD_PC_BEEP AUD_BEEP AUD_SYS_BEEP
C596
12
SC4D7U10V5ZY
C597
12
SC4D7U10V5ZY
C598
12
SC4D7U10V5ZY
4
12
C593 SCD1U
12
AUD_AGNDAUD_AGND
CB_SPKR 26
SPKR_SB 21
KBC_BEEP 34
3
12
C595
R396
SC2200P50V2KX
2K2R3
R391
12
4K7R2
G8
1 2
GAP-CLOSE
AUD_AGND AUD_AGND
G10
1 2
GAP-CLOSE
<Variant Name>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
AUDIO (1/2) -- CODEC ALC655
Size Document Number Rev
A3
2
Date: Sheet
Bolsena
1
G9
1 2
GAP-CLOSE
G11
1 2
GAP-CLOSE
32 58Tuesday, December 28, 2004
AUD_AGNDAUD_AGND
SA
of
Page 33
12
AUD_AGND
5VA_OP_S0
AUD_AGND
R417
12
10KR2
12
AUD_AGND
A
C599 SC4D7U10V5ZY
12
C609
SC1U10V3KX
C622 SC4D7U10V5ZY
CSOUTL1
C601
1 2
SC10U10V5ZY
CSOUTL2
C603
1 2
SC10U10V5ZY
12
C610 SCD1U
By GMT suggest. Change from
74.01421.01G to 74.01421.A1G
AMP_SHUTDOWN 34
CSOUTR1
C615
1 2
SC10U10V5ZY
CSOUTR2
C619
1 2
SC10U10V5ZY
HP_IN_1 HP_IN
1 2
12
R427
GAP-CLOSE
AUD_AGND
1 2
R405
1 2
15KR3F
HP_L L_BYPASS
AMP_SHUTDOWN HP_IN_1
AUD_AGND
R_BYPASS
HP_R
R419
1 2
15KR3F
R423
1 2
10KR2
R426 DUMMY-R3
R403 10KR2
L_LINE_IN
R_LINE_IN
HP_R
5V_S0 5VA_OP_S0
G12
1 2
GAP-CLOSE-PWR
4 4
AUD_LOL32
12
C608 SC10U10V5ZY
3 3
AUD_AGND
AUD_LOR32
R_BYPASS
L_BYPASS
AUD_AGND
DY
12
C621 SC4D7U10V5ZY
Additional 12dB gain
2 2
12
5VA_OP_S0
C980
DY
SC2D2U10V5MX-U1
12
12
Audio VREF Generator
R822 20KR2
DY
R821 20KR2
DY
AUD_AGNDAUD_AGNDAUD_AGND
U122
1
IN+
2
VSS IN-3OUT
MAX4490AXK-T
DY
5VA_OP_S0
AUD_VREF_S0
5
VDD
4
Microphone External Preamp
R808
1 2
U104
5
VDD
4
OUT
MAX4490AXK-T
1 2
DY
1 2
DY
0R0402-PAD
IN+
VSS
IN-
DY
R798 2K2R3
C973 SC220P50V2JN
AUD_VREF_S0
DY
1 2 3
AUD_AGND
1 2
DY
5VA_OP_S0
12
DY
C974 SC1U10V3ZY
AUD_AGND
1 1
AUD_MICIN32
1 2
A
DY
R795 0R3-U
HP_L
U34
4
LLINEIN
5
LHPIN
6
LBYPASS
7
LVDD
8
SHUTDOWN
2
TJ
17
HP-IN
23
VOL
18
RVDD
19
RBYPASS
20
RHPIN
21
RLINEIN
G1421BF3U
KBC_MUTE34
EAPD32
12
R799 47KR2
MIC_IN_2
R797 5K6R3
DY
AUD_AGND
B
12
C971 SC4D7U10V5ZY
B
C600
1 2
SC220P50V2KX-U
R404
1 2
10KR2
C602
1 2
SC220P50V2KX-U
R406
1 2
18KR3
3
LOUT+
10
LOUT-
14
SE/BTL#
16
HP/LINE#
11
MUTEIN
9
MUTEOUT
1
GND/HS
12
GND/HS
13
GND/HS
24
GND/HS
15
ROUT-
22
ROUT+
GND
25
R415
1 2
18KR3
C616
1 2
SC220P50V2KX-U
R425
1 2
10KR2
C620
1 2
SC220P50V2KX-U
1 2
12
R433 10KR2
AUD_AGND
AUD_AGND
DY
1 2
EXT_MICIN
AUD_AGND
AUD_AGND
1 2 3
5VA_OP_S0
12
12
MIC_IN_1 EXT_MIC_IN
C972
1 2
SC1U10V3ZY
1 2
12
1 2
C986 SC3300P50V2KX
DOCK_EXT_MIC_IN57
DOCK_MIC_JKIN#57
AUD_AGND
U37
A
VCC B GND3Y
NC7SZ32-U
U105
A B GND
R800 1KR2
R796 2K2R2
SPKR_L+ SPKR_L-
HP_IN AUD_MUTE
SPKR_R­SPKR_R+
5
AUD_MUTE
4
5
VCC
4
C
74LVC1G66DBVR
C988 SC4D7U10V5ZY
1 2
AUD_AGND
R805 0R0402-PAD
INT_MIC_IN
R806 0R0402-PAD
DOCK_EXT_MIC_IN
R807 0R0402-PAD
5VA_OP_S0
3 1
1 2
12
AUD_AGND
5V_AUDIO_S0
5VA_OP_S0
K
2222K
R407 100KR2
AUD_AGND
5V_AUDIO_S0
C611 SC4D7U10V5ZY
AUD_AGND
TP120 TPAD30
C
Q16 DTA124EUA-U1
D20
2
5
6
RB731U
1 2
Dummy when use EZ4
SPKR_L+
12
SPKR_R+
R411 1KR2
12
R413 2K2R3
C614 SC3300P50V2KX
2
2222K
C
AUD_MICIN 32
AUD_AGND
12
12
R400
10KR2
34
2
1
R831 0R2-0
R412
1 2
0R2-0
R410
1 2
0R2-0
Dummy when no EZ4
5VA_OP_S0
12
R804 10KR2
DOCK_MIC_JKIN#1
Q49
K
DTA124EUA-U1
3 1
5VA_OP_S0
12
R401 10KR2
DOCK_JACK_IN#
AUD_AGND
DY
Dummy when no EZ4
D
Q48
1
2N7002
G
S
2 3
LINE IN
AUD_LINR32
AUD_LINL32
AUD_AGND
LINE OUT
?spdif led on, delete ic?
SPKR_L+ SPKR_R+
5VA_OP_S0
D41
MIC_JKIN#
2
3
1
BAW56-1
5VA_OP_S0
MIC_JKIN
1
G
OUT
GND
12
12
1 2 1 2
80.10715.591
12
R801 10KR2
12
R809 10KR2
MIC_JKIN#
D
Q51 2N7002
S
2 3
D
Q15
47K
3
R1
2
IN
1
R2
DTC144EUA
SE#_BTL
ENAUDIO# 37
SPKR_L_DOCK 57 SPKR_R_DOCK 57
Dummy when no EZ4
R416
1 2
1KR2 R422
1 2
1KR2
R420
R421
10KR2
10KR2
AUD_AGND
TC9 ST100U6D3VDM-5 TC10 ST100U6D3VDM-5
2222K
2
K
D
?dock jack in high?low?
DOCK_JACK_IN 57
SPKR_L­SPKR_L+ SPKR_R+ SPKR_R-
12
MIC_JKIN = Hi after PLUG-IN
12
12
C613
C612
SC1U10V3ZY
SC1U10V3ZY
AUD_LINE_R
AUD_LINE_L
EXT_MICIN
Internal Speaker
12
12
C605 SC680P50V2KX
5VA_OP_S0
12
AUD_AGND
R424
12
GAP-CLOSE
C606 SC680P50V2KX
MIC_JKIN
12
R414 10KR2
R418 1KR2
12
AUD_AGND
AUD_AGNDAUD_AGND
C604 SC680P50V2KX
DOCK_LIN_R 57 DOCK_LIN_L 57
12
SC680P50V2KX
12
C617
SC100P50V2JN
SE#_BTL= LOW after PLUG-IN
R432 1KR2
OUT
R429 22R3 R430 22R3
IN
3D3V_S0
5 1
SE#_BTL
SPKR_R_A1
12
AUD_AGND
1 2
SPDIF_PWR
SPDIF32,57
AUD_AGND
SPKR_L_A1
12
C623
C624
SC680P50V2KX
SC680P50V2KX
AUD_AGND
If R->L noise
避免
1000P -> 100P
U36
DY
2
GND
3
NC
4
ON/OFF#
HP_IN
AAT4250-U
SPKR_L+1 SPKR_R+1
1 2 1 2
12
12
R431 1KR2
AUD_AGND
AUD_AGND AUD_AGND
Internal Mic
31
Q50 DTC124EUA-U1
INT_MIC
AUD_AGND
AUDIO (2/2)
?which is gnd
MIC1
20.D0012.102
CON2-10-U1
Wistron Corporation
21F, 88, Se c .1, Hsin T ai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Bolsena
LOW OFF
Title
Size Document Number Re v
Custom
Date: Sheet
E
C607
C618 SC100P50V2JN
AUD_AGND
R428 0R3-U
AUD_AGND
33 58Tuesday, December 28, 2004
E
SPK1
5 4 3 2
1 6
ETY-CON4-S
20.D0122.104
LIN1
5 4 3 6 2 1
AUDIO-JK30-U
22.10088.571
LOUT1
9
GND
8
VCC
7
VIN
16
6 5 4 2 3 1
PHONE-JK 150- U 1
22.10133.561
of
SA
Page 34
12
S5_ENABLE RSMRST#_KBC PM_PWRBTN#
AG_RST# AD_IA
RN73
SRN10K-2
RN105
SRN10KJ
R449 DUMMY-R2
R457 10KR2
5
3D3V_AUX_S5
C630 SCD1U16V
LPC_LFRAME#18,37 P_SERIRQ18,26,37,57
TDATA_535 TCLK_535
3D3V_AUX_S5
R452 DUMMY-R2
R460 10KR2
12
C631 SCD1U16V
KBCBIOS_RD# KBCBIOS_WE# KBCBIOS_CS#
A036 A136 A236 A336 A436 A536 A636 A736 A836 A936 A1036 A1136 A1236 A1336 A1436 A1536 A1636 A1736 A1836
12
R453 DUMMY-R2
DY
12
R461 10KR2
LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3
KBC_D0 KBC_D1 KBC_D2 KBC_D3 KBC_D4 KBC_D5 KBC_D6 KBC_D7
KBC_PWRBTN#35
BRIGHTNESS17
12
12
C629
C628
SCD1U16V
SCD1U16V
LPC_LAD[0..3]18,37
CLK33_KBC18,22
KBCBIOS_RD#36 KBCBIOS_WE#36 KBCBIOS_CS#36
TP93TPAD28
KBC_D[0..7]36 BAT_SDA_548
1 2 3 45
TDATA_5
R450 10KR2
12
TCLK_5
R451 10KR2
12
3
12
DY
12
12
DY
R458 DUMMY-R2
12
R459 DUMMY-R2
DY
igh=Test Mode,Low=Normal operation(Recommended)
5
1 2
12
C633 SCD1U16V
15 14 13 10
9
18
7
150 151 173 152
138 139 140 141 144 145 146 147
124 125 126 127 128 131 132 133 143 142 135 134 130 129 121 120 113 112 104 103
117 116 115 114 111 110
ECSWI#21
PM_SLP_S3#18,21,38,39,43,44,57
AC_IN#47
KBC_LID#35
KBC_BEEP32
L25 BLM11P600S
LAD0 LAD1 LAD2 LAD3
LFRAME# LCLK SERIRQ
RD# WR# MEMCS# IOCS#
D0 D1 D2 D3 D4 D5 D6 D7
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
PSDAT3 PSCLK3 PSDAT2 PSCLK2 PSDAT1 PSCLK1
3D3V_AUX_S5
12
12
C626 SCD1U16V
D D
C C
S5_ENABLE3
RSMRST#_KBC21 PM_PWRBTN#21
B B
A1 A4 A5 FAN3PWM FAN3FB
A A
A1 for the internal pull-up resi stors on XIOCS[F:0] pins==>High=enable,Low=Disable A4 for DMRP==>High=Disable,Low=Enable
A5 for EMWB==>High=Enable,Low=Disable
GPIO05 for Clock test mode==>High=test Mode,Low=32KHz clock in normal running(Recommended) GPIO06 for DPLL test mode==> H
AG_RST#13,49
AD_IA47
5V_S0
5V_S0
C627 SCD1U16V
PS2_MDAT57 PS2_MCLK57 PS2_KDAT57 PS2_KCLK57
8 7 6
1 4 2
12
DY
12
4
3D3V_KBC_AUX_S5
12
C632 SCD1U16V
123
136
VCC16VCC34VCC45VCC
VCC
LPC
X-bus ROM
PS/2
PWM743PWM640PWM539PWM438PWM337PWM236PWM133PWM0
KBC_BEEP
ECSWI#
PM_PWRBTN#
RSMRST#_KBC
S5_ENABLE
BRIGHTNESS AG_RST#
4
157
VCC
95
166
VCC
VCCA
32
KCOL1
161
KSO049KSO1
VCCBAT
GPWU02GPWU126GPWU229GPWU330GPWU444GPWU576GPWU6
KBC_PME#
R464
1 2
0R2-0
DY
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
53
KSO556KSO657KSO758KSO859KSO9
60
KSO1061KSO1164KSO1265KSO1366KSO1467KSO1568KSO16
50
KSO251KSO352KSO4
KB Matrix
KB3910
DA099DA1
DA2
DA3
GPWU7
172
176
DA41DA542DA647DA7
100
101
102
GMODULE_RST#
KCOL[1..16] 35 KROW[8..1] 35
KCOL15
KCOL16
153
154
KSO17
AD081AD182AD283AD384AD487AD588AD689AD7
174
AC_VOL_SENSE
BAT_SENSE
AC_VOL_SENSE BAT_SENSE
3
KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KROW7
KSI071KSI172KSI273KSI374KSI477KSI578KSI679KSI7
90
KBC_BB_ENABLE#
AD_IA
AD+ BT+
12
12
3
KROW8
80
ECRST#19ECSCI#
31
EC_RST#
ECSCI#_KBC
R462 100KR2F
R465 13K3R2F
BAT_SCL_5
BAT_SDA_5
KBC_SCL2
KBC_SDA2
164
170
163
169
SCL1
SCL2
SDA1
SDA2
AGND96BATGND
159
KBC_BB_ENABLE# 36
12
R463 560KR2F
12
R466 100KR2F
KBC_XO
1 4
KBC_XI
158
160
XCLKI
XCLKO
GND17GND35GND46GND
122
137
ECSCI#_KBC 21
GND
GND
167
1 2
32
1 2
GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24 GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO09 GPIO08 GPIO07 GPIO06 GPIO05 GPIO04 GPIO03 GPIO02 GPIO01 GPIO00
GPIO0F GPIO0E GPIO0D GPIO0C GPIO0B GPIO0A
GPIO1F GPIO1E GPIO1D GPIO1C GPIO1B GPIO1A
GPIOI2D
GPIO2F GPIO2E GPIO2C GPIO2B GPIO2A
KB3910SF
C636
C625 SC10P50V2JN-1
X8 X-32D768KHZ-12-U
C634 SC10P50V2JN-1
U38
155 149 148 119 118 109 108 107 106 105 86 85 75 70 69 63 62 55 54 48 22 21 20 12 11 8 6 5 4 3
41 28 27 25 24 23
98 97 94 93 92 91
168 175 171 165 162 156
3D3V_AUX_S5
12
12
2
3
SC10U10V5ZY
KBC_SCL2 KBC_SDA2
CHG_ON#
AD_OFF A20 E51TXD E51RXD E51CS#
FAN3FB FAN3PWM
KBCRST# KA20GATE
ECSMI#_KBC WIRELE SS_EN
VCC3VSB
AMP_SHUTDOWN KBC_PCIRST# BL_ON
R454 10KR2
Q21
1
CH3906
2
3D3V_AUX_S5
3
RN71
SRN10KJ
2
1 4
BLT_BTN# 35 CHG_ON# 47 AD_OFF 48
TP94 TPAD28 TP95 TPAD28 TP96 TPAD28
STDBY_LED# 17
INTERNET# 35 MAIL# 35 PM_SLP_S5# 21,44,57
PM_SUS_STAT# 21,37 CAP_LED# 17
PRE_CHG 47
KBC_MUTE 33
KEY5# 35
WIRELESS_BTN# 35
R898
1 2
0R0402-PAD
KA20GATE 21
KEY4# 35
BAT_THERMAL 47,48
DOCK_I N# 56,57
ECSMI#_KBC 21 WIRELESS_EN 31 PM_CLKRUN# 18,26,29,31,37
FPBACK 17
NUM_LED# 17
BLUETOOTH_EN 24
MAIL_LED# 17
BLT_LED# 17
WLAN_LED# 17 MAIL_LED# 17 CHARGE_LED# 17
1 2
R456
12
10KR2
2
1
3D3V_S0
U62 2N7002DW
KBC_SCL2
SMBC_G79223
KBC_SDA2
5 6
3D3V_AUX_S5
34 2 1
12
R434 10KR2
BAT_SCL_548
SMBD_G792 23
?PreCharge ok?pull?
KBC_PWRBTN# AC_IN# KBC_LID#
KBRCIN# 21
1 2 1 2 1 2
?dock in EZ4 changed
3D3V_AUX_S5
12
DOCK_IN#
3D3V_S5
R447 10KR2
D
1 2
3D3V_S5
AMP_SHUTDOWN 33
R897 0R0402-PAD
PCIRST_BUF# 15,18,2 6,28,29,31,57 BL_ON 13,49
12
R445 100KR2
12
C635 SC1U10V3ZY
CHK_PW# 36
KBC_PME#
DY
RSMRST# 23,48
<Variant Name>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev A3
Date: Sheet
KBC KB3910 Bolsena
1 2
1
G
Q20 2N7002
23
S
R455 0R2-0
34 58Tuesday, December 28, 2004
1
SMBC_G792 SMBD_G792
3D3V_AUX_S5
RN72
2 1 4
SRN4D7KJ
R575 10KR2 R574 10KR2 R564 10KR2
R444 10KR2
PME#_SB 21,29
of
5V_S0
3
DY DY DY
2
14
RN65
SRN10KJ
3
SA
Page 35
A
Buttons
4 4
Wireless ON/OFF
WIRELESS_BTN#
BlueTooth ON/OFF
BLT_BTN#
3 3
WLAN1
1 2 3 4
5
MH1 MH2
SW-TACT-44
62.40009.331
BLUE2
1 2 3 4
5
MH1 MH2
SW-TACT-44
62.40009.331
3D3V_AUX_S5
PWRBTN#_CN
12
POWER BUTTON
R471 10KR2
R473
1 2
470R3
12
Power
PWRBTN#_CN
1 2
5
62.40026.071
Internet
Mail
INTERNET#
1 2
5
62.40026.071
1 2
5
MAIL#
C646 SCD1U
PWR1 SW-STS043A
43
NET1 SW-STS043A
43
MAIL1 SW-STS043A
43
KBC_PWRBTN# 34
P1
P2
62.40026.071
RP3
BLT_BTN#
10
9 8 7
SRP10K
3D3V_S5
WIRELESS_BTN#34
BLT_BTN#34
WIRELESS_BTN#
MAIL#
1
KEY4#
2
KEY5#
3
INTERNET#
4 56
1 2
5
62.40026.071
1 2
5
62.40026.071
MAIL# 34 KEY4# 34 KEY5# 34 INTERNET# 34
B
KEY4#
P1 SW-STS043A
43
KEY5#
P2 SW-STS043A
43
INTERNET#
KEY5# KEY4# MAIL#
BLT_BTN#
WIRELESS_BTN#
PWRBTN#_CN
RC1
1 2 3 4 5
SRC100P50V-U RC2
1 2 3 4 5
SRC100P50V-U
C
Cover Up Switch
KBC_LID#34
TOUCH PAD
TDATA_534
8 7 6
8 7 6
TP_SCROLL_LEFT TP _S CROLL_RIGHT
1 2
43
5
TCLK_534
SCRL_L1 SW-STS043A
D
5V_S0
14
RN74
SRN10KJ
1 2
5
TP_SCROLL_DOWN
1 2
5
3D3V_S5
12
12
2
3
1 2 1 2
SCRL_U1 SW-STS043A
43
SCRL_D1 SW-STS043A
43
R468 47KR2
R469
1 2
100R3
C638 SC1000P50V2KX
R472 100R3
R470 100R3
1 2
5
LID_SW
TP_DATA
TP_CLK
C644
12
LID1
CON2-10-U1
20.D0012.102
5V_S0
12
12
C642
C643
SCD1U
SC1U10V3KX
C645
12
SC47P50V2JN
SCRL_R1 SW-STS043A
43
1 2
5
TP_RIGHT TP_SCROLL_UP TP_SCROLL_DOWN TP_SCROLL_LEFTTP_SCROLL_UP TP_SCROLL_RIGHT TP_LEFT
SC47P50V2JN
TP_LEFT TP_RIGHT
LEFT1 SW-STS043A
43
E
13
10 11 12 14
20.K0063.012
1 2
5
TPAD1
1 2
3 4 5 6 7 8 9
MLX-CON12-7
RIGHT1 SW-STS043A
43
EMI Bypass cap.
KCOL1 KCOL2 KCOL3
KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9
KCOL10
KCOL11 KCOL12
KCOL13 KCOL14 KCOL15 KCOL16
KROW[8..1] 34 KCOL[1..16] 34
Pin1 ==>*R01 Pin2 ==>*R02 Pin3 ==>*R03 Pin4 ==> C01 Pin5 ==> C02 Pin6 ==> C03 Pin7 ==>*R04 Pin8 ==> C04 Pin9 ==> C05 Pin10 ==> C06 Pin11 ==> C07 Pin12 ==> C08 Pin13 ==> C09 Pin14 ==>*R05 Pin15 ==> C10 Pin16 ==>*R06 Pin17 ==>*R07 Pin18 ==> C11 Pin19 ==> C12 Pin20 ==>*R08 Pin21 ==> C13 Pin22 ==> C14 Pin23 ==> C15 Pin24 ==> C16 Pin25 ==> NC
C
KCOL9 KCOL10 KCOL11 KCOL12
KCOL5 KCOL6 KCOL7 KCOL8
KCOL1 KCOL2 KCOL3 KCOL4
KROW5 KROW6 KROW7 KROW8
KROW1 KROW2 KROW3 KROW4
KCOL13 KCOL14 KCOL15 KCOL16
RC3
1 2 3 4 5
SRC100P50V-U RC5
1 2 3 4 5
SRC100P50V-U RC7
1 2 3 4 5
SRC100P50V-U RC4
1 2 3 4 5
SRC100P50V-U RC6
1 2 3 4 5
SRC100P50V-U RC8
1 2 3 4 5
SRC100P50V-U
8 7 6
8 7 6
8 7 6
8 7 6
8 7 6
8 7 6
D
<Variant Name>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
BUTTONs / KB / TOUCHPAD
Size Document Number Rev
A3
Date: Sheet
Bolsena
35 58Tuesday, December 28, 2004
E
of
SA
Internal KeyBoard CONN
2 2
KB1
125
........
1 1
A
26
NC#26
1
C01
2
C02
3
C03
4
R01
5
R02
6
R03
7
C04
8
R04
9
R05
10
R06
11
R07
12
R08
13
R09
14
C05
15
R10
16
C06
17
C07
18
R11
19
R12
20
C08
21
R13
22
R14
23
R15
24
R16
25
NC#25
27
NC#27
MLX-CON25
20.K0090.025
B
KROW1 KROW2 KROW3
KROW4
KROW5 KROW6
KROW7
KROW8
Page 36
5
D D
C C
4
KBC_D[0..7] 34
KBCBIOS_WE#34 KBCBIOS_RD#34 KBCBIOS_CS#34
KBC_D034 KBC_D134 KBC_D234 KBC_D334 KBC_D434 KBC_D534 KBC_D634 KBC_D734
A034 A134 A234 A334 A434 A534 A634 A734
3
3D3V_AUX_S5
12
C647 SCD1U16V
U39
13
DQ0
14
DQ1
15
DQ2
17
DQ3
18
DQ4
19
DQ5
20
DQ6
21
DQ7
SST39VF040-70-1
32
VDD
VSS
16
22
31
1
24
CE#
OE#
WE#
A012A111A210A39A48A57A66A7
A162A1730A18
A15 A14 A13 A12 A11 A10
A9 A8
5
2
A18 34 A17 34 A16 34
3 29 28 4 25 23 26 27
A15 34 A14 34 A13 34 A12 34 A11 34 A10 34 A9 34 A8 34
1
ROM SIZE MAX. 512KBYTE
PLCC32 Socket P/N:
3D3V_AUX_S5
SSKT3262.10002.032 SSKT32 62.10005.032
3
B B
3D3V_S0
A A
3
KBC_BB_ENABLE#34 CHK_PW#34
RN75
SRN10KJ
5
2 14
MATRIXID1# MATRIXID2#
RN134
SRN100KJ
2
1 4
KBC_BB_ENABLE# CHK_PW#
SW1
1 2 3 4
SW-2184LPSTR
8 7 6 5
Keyboard matrix ( from vendor )
Low Bit
High Bit
MATRIXID1#
MATRIXID2#
1
4
JapUS
100
01
OtherEur
10
<Variant Name>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev A3
3
2
Date: Sheet
BIOS ROM Bolsena
SA
of
36 58Tuesday, December 28, 2004
1
Page 37
SIO_GPIO20
LPCPD#
SIO_GPIO22 SIO_GPIO03
PANEL_ID2
SIO_GPIO25 SIO_GPIO31 SIO_GPIO24
SIO_GPIO00 SIO_GPIO23 SIO_GPIO21
3D3V_S0
RP4
1 2 3 4 5 6
SRP10K
RP5
1 2 3 4 5 6
SRP10K
RP6
1 2 3 4 5 6
SRP10K RP7
1 2 3 4 5 6
SRP10K
10
PANEL_ID1
9
SIO_GPIO35
8
SIO_GPIO32
7
PANEL_ID0
10 9
SIO_PNF
8
XFD_INST#
7
ENAUDIO#
10
SIO_GPIO01
9
SIO_GPIO26
8
SIO_GPIO27
7
SIO_GPIO30
10
PANEL_ID3
9
SIO_GPIO02
8 7
SIO_GPIO33
?MIC_JKIN in page 33 pull 5V
?no use GPIO, need pull high?
CLK33_SIO18,22
C648
1 2
DUMMY-C2
PCLK_SIO_RC
12
C650 SC1U10V3ZY
PANEL_ID317 PANEL_ID217 PANEL_ID117 PANEL_ID017
12
PCIRST_BUF#_SIO
R475 DUMMY-R2
CLK14_SIO3
CLK14_SIO_RC
C649
1 2
DUMMY-C2
12
C651 SCD1U16V
12
C652 SCD1U16V
SIO_GPIO00 SIO_GPIO01 SIO_GPIO02 SIO_GPIO35 SIO_GPIO03
SIO_GPIO27 SIO_GPIO26 SIO_GPIO25 SIO_GPIO24 SIO_GPIO23 SIO_GPIO22 SIO_GPIO21 SIO_GPIO20
3 2 1
100
99 98 97 96
81 80 79 78 77 76 75 74
86 87 72 91 92 93 94 95
12
R477 DUMMY-R2
3D3V_S0
12
C653 SCD1U16V
GPIO00/XD0/JOYABTN1 GPIO01/XD1/JOYBBTN1 GPI002/XD2/JOYAY GPIO03/XD3/JOYBY GPIO04/XD4/JOYBX GPIO05/XD5/JOYAX GPIO06/XD6/JOYBBTN0 GPIO07/XD7/JOYABTN0
GPIO10/XA12/RI2#/JOYABTN1 GPIO11/XA13/DTR2_BOUT2#/JOYBBTP1 GPIO12/XA14/CTS2#/JOYAY GPIO13/XA15/SOUT2/JOYBY GPIO14/XA16/RTS2#/JOYBX GPIO15/XA17/SIN2/JOYAX GPIO16/XA18/DSR2#/JOYBBTN0 GPIO17/XA19/DCD2#/JOYABTN0
GPIO27/XA7/PIRQB GPIO26/XA6/PIRQA/XSTB2# GPIO25/XCS0#/XRDY/DR1# GPIO24/XA4/XSTB0# GPIO23/XA3 GPIO22/XA2 GPIO21/XA1 GPIO20/XA0
65
88
VDD14VDD39VDD63VDD
IRSL0_3
IRRX_3
IRTX_3
66
69
68
NC
IRRX1
20
67
70
IRRX2_IRSL0
9
IRTX
IRSL1
CLKIN
PWUREQ#/IRSL3
SIO PC87392
LPC_LFRAME#_1 LPC_LAD0_1 LPC_LAD0
1 2
LPCPD#
8
LCLK
LRESET#
12
10
11
LAD015LAD116LAD217LAD3
LDRQ#
SERIRQ
LFRAME#
56
55
57
7
18
60
62
RI1#
SIN1
CTS1#
DSR1#
LPCPD#
DCD1#
GPIO37/DR1#/IRSL2/XIORD#
GPIO36/CLKRUN#
GPIO34/XRD#/WDO#
GPIO33/XA11/MDTX/XIOWR#
GPIO32/XA10/MDRX/XIORD#
GPIO31/XA9/PIRQD/MTR1#
GPIO30/XA8/PIRQC
DTR1_BOUT1/BADDR
SOUT1/XCNF0
XWR#/XCNF1
XSTB1#/XCNF2/NC
XCS1#/MTR1#/DRATEO/XIOWR#
DRATEO/IRSL2
1 2 1 2
R479 DUMMY-R2
GPIO35/SMI#
RTS1#/TEST
RDATA# WDATA# WGATE#
HDSEL#
DIR# STEP# TRK0#
INDEX#
DSKCHG#
WP#
MTR0#
DR0#
DENSEL
R474 33R2
R476 0R2-0
R478 0R2-0
12
LPC_LAD1 LPC_LAD2 LPC_LAD3
U40
71 6 19 5
SIO_GPIO33
82
SIO_GPIO32
83
SIO_GPIO31
84
SIO_GPIO30
85 61
58 59 4
XFD_INST#
90 73
23 27 26 22 29 28 25 32 21 24 31 30 33 34
LPC_RST# 13,18
P_SERIRQ 18,26,34,57 LPC_LDRQ0# 18
LPC_LFRAME# 18,34
LPC_LAD[0 . .3 ] 18,34
PM_SUS_STAT# 21,34
SIN1_5 57
CTS1#_5 57 DSR1#_5 57 DCD1#_5 57
RI1#_5 57
ENAUDIO# 33
PM_CLKRUN# 18,26,29,31,34
?MIC_JIN deleted,what use?
RTS1#_5 57 SOUT1_5 57
3D3V_S0
12
R889 10KR2
!for test, after ok, delete R
DY
DTR1_BOUT1_5 57
PANEL_ID3
0 0 0 0 0 0 0 0 0 0
Note : AU (
PANEL ID DEFINE
PANEL_ID2
PANEL_ID1
0 0 15" SXGA+0
1 0 15" WIDE0 0 0 0
1
1
1
1 1 AU (14")0
友達
),CMO(奇美),** : With Digitizer
PANEL_ID0
Hydis (14")SPWG010
1 1 1
Hitachi (15") AU (15") CMO(15") CMO(14")001
01 1 AU (14")**
No Panel111
VENDORS
SLCT/WGATE#36BUSY_WAIT#/MTR1#40ACK#/DR1#41SLIN_ASTRB#/STEP#47INIT#/DIR#
VSS13VSS38VSS64VSS
89
37
PE/WDATA#
PD0/INDEX#52PD1/TRK0#50PD2/WP#48PD3/RDATA#46PD4/DSKCHG#45PD5/MSEN044PD6/DRATE043PD7/MSEN1
49
42
ERR#/HDSEL#51AFD_DSTRB#/DENSEL/DRATE153STB_WRITE#
54
EZ4_PD7 EZ4_PD6 EZ4_PD5 EZ4_PD4 EZ4_PD3 EZ4_PD2 EZ4_PD1 EZ4_PD0
PNF/XRDY#
35
SIO_PNF
STROB#_5 58
AUTOFD#_5 58
ERROR#_5 58
EZ4_PD[7..0] 58
PRINIT#_5 58 SLCTIN#_5 58 PRNACK#_5 58 BUSY_5 58 PE_5 58 SLCT_5 58
PC87392-U
3D3V_S0
12
C654 SC1U10V3KX
Infineon FIR Module
40mil
12
C655 SC4D7U10V5ZY
<Variant Name>
Title
Size Document Number Rev
A3
Date: Sheet
10mil 10mil 10mil
1 2
R723
DY
SUPER IO NC87392
IRTX_3 IRRX_3 IRSL0_3
IRMODE
10KR3
Bolsena
IR1
1
VCC2/IRED_ANODE
2
IRED_CATHODE
3
TXD
4
RXD
5
SD
6
VCC1
7
MODE
8
GND
FIR-TFDU6102
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
37 58Tuesday, December 28, 2004
SA
of
Page 38
A
B
C
D
E
Run Power
4 4
DCBATOUT
Q25
PM_RUNCTL
R482
1 2
10KR2
R484
330KR3
R491
1 2
63.R0004.151
PM_RUNCTL_G
0R3-U
12
1
G
C660 SC1U10V3KX
1 2
PM_SLP_S3#18,21,34,39,43,44,57
3 3
2 2
TP0610T
12
3 12
2 3
D
S
R485 1KR2
Q28 2N7002
R483 47KR2
1
G
DY
R486
12
12
330KR3 C657
D
Q27
SCD22U25V5ZY
2N7002
S
DY
2 3
21
D21
12
MMGZ5242B
DY
1 2
DY
1 2
0R3-U
R498
R499
1 2
0R3-U
C302 SCD1U
1 2
R481 0R2-0
C333 SCD1U
1 2
R489 0R2-0
C334 SCD1U
DY
1 2
12
12
12
2D5V_S0
12
C335 SCD1U
DY
1 2
12
C656 DUMMY-C2
3D3V_S0
C659 DUMMY-C2
C662 DUMMY-C2
C664 DUMMY-C2
U41
1
S
2
S
3
S
4 5
GD
AO4422
U43
1
S
2
S
3
S
4 5
GD
AO4422
U44
1
S
2
S
3
S
4 5
GD
AO4422
1D8V_S0
5V_S55V_S0
8
D
7
D
6
D
12
3D3V_S5
8
D
7
D
6
D
12
2D5V_S3
8
D
7
D
6
D
12
U45
1
S
2
S
3
S
4 5
GD
AO4422
C78 SCD1U
C79 SCD1U
C294 SCD1U
8
D
7
D
6
D
1D8V_S5
12
C295 SCD1U
1 1
A
B
C
D
<Variant Name>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
PWR CTL LOGIC / PWR PLANE
Size Document Number Rev
A3
Date: Sheet
Bolsena
38 58Tuesday, December 28, 2004
E
of
SA
Page 39
A
B
C
D
E
4 5
12
C994 DUMMY-C3
5V_S5
13 12
1D25V_S3_PG#
12
C671 SCD1U
1D25V_S35V_S5
12
C672 SC1U10V3KX
5V_S5
147
147
73.07408.0JB
1
U13B
6
TSAHCT08-U
73.07408.0JB
SB_PWRGD 21
U13C
11
TSAHCT08-U
5V_S5
12
1D25V_S3_PG
D
G
S
2 3
1D2V_S0_EN
VDDA_2D5_PG
R510 10KR2
Q36 2N7002
ALL_PWROK13
10
9
12
C669 SC1U10V3KX
1D8V_S0_PG
1D2V_S0_EN 44,55
5V_S5
147
73.07408.0JB
D
5V_S5
U13D
VTT_VDDA_PG
8
TSAHCT08-U
PM_SLP_S3#
3D3V_S0
147
12 13
<Variant Name>
Title
Size Document Number Rev
Date: Sheet
1 2
U16D
11
TSLCX08-U
Custom
U47A
147
3
TSAHCT08-U
73.07408.0JB
NB_PWRGD 13
VCORE_EN 41,48
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
POWERGOOD&ENABLES
Bolsena
E
39 58Tuesday, December 28, 2004
SA
of
3D3V_AUX_S5 3D3V_AUX_S5
U46A
147
NB_PWRGD NB_PWRGD_N
4 4
3 3
2 2
1 1
1 2
VTT_VDDA_PG PM_SLP_S3#
TSLCX14MTC-L-U
SB_PWRGD IS 35MS AFTER NB_PWRGD
R514
1 2
27KR3
4 5
A
5V_S5
VRM_PWRGD21,41
1 2
1D8V_PG_SET
12
R515
10KR2
147
R504 270KR3
U47B
6
TSAHCT08-U
73.07408.0JB
12
R505
220KR2J
5V_S5
12
R509 4K7R2
R512 1MR3F
1 2
VTT_1D2V_PG
VRM_PWRGD
12
C665
SC1U10V3ZY
1D8V_S0
1D8V_S0_PG#
12
1D8V_S0_FB
13 12
R513 0R2-0
5V_S5
ALL_PWROK13
12
C668 SCD1U
147
147
3 4
TSLCX14MTC-L-U
1
G
U47C
11
TSAHCT08-U
73.07408.0JB
RUNPWROK23
3D3V_S5
Reduce leakage (WHEN 3D3V_AUX_S5 ON, 3D3V_S0 OFF)
U46B
R124
1KR2
1 2
3D3V_S0
147
9
10
12
R508
10KR2
1D8V_S0_PG
D
Q35 2N7002
S
2 3
U48
1
1OUT
2
1IN-
3
1IN+
4
GND
LM393ADR
5V_S5
5V_S5
U47D
VTT_VRM_PG
B
147
10
9
8
TSAHCT08-U
U16C
8
TSLCX08-U
VCC
2OUT
2IN-
2IN+
1 2
ALL_PWROK
8 7 6 5
R517 47KR2
PM_SLP_S3#18,21,34, 38,43,44,57
1D25V_PG_SET
12
R518 10KR2
12
12
R506 10KR2
C666 SCD1U
C
2D5V_S32D5V_S0
5V_S5
12
VRM_PWRGD
1 2
12
R507 10KR2
2D5V_S3_PG 2D5V_S0_PG
12
C667 SCD1U
R511
1 2
4K7R2
C670 SCD1U
R516
1 2
1MR3F
ALL_PWROK 13
R824 330R2
Page 40
A
CPU_CORE MAX1544ETL
VID0_PWM
VID1_PWM
4 4
VID2_PWM
VID3_PWM
VID4_PWM
VID Setting
VID0(I / 3.3V)
VID1(I / 3.3V)
VID2(I / 3.3V)
VID3(I / 3.3V)
VID4(I / 3.3V)
Input Signal
VCORE_EN
EN (I / 3.3V)
Voltage Sense
COREFB
COREFB#
3 3
VSEN(I / Vcore)
RGND(I / Vcore)
Input Power
DCBATOUT
5V_S0
3D3V_S0
VCC(I)
VCC(I)
VCC(I)
Output Signal
VROK()
Output Power
VCC_CORE_PWR(O)
Max1999 5V/3D3V
2 2
SHUTDOWN_S5 MAX1999_PGD
SHUTDOWN_S5
DCBATOUT
PM_SLP_S3#
Input Signal
ON3
ON5
SHDN#
SKIP#
Input Power
DCBATOUT
1 1
V+
A
Output Signal
PGOOD(OD / 5V)
Output Power
5V(O)
3D3V(O)
LDO5(O)
B
MAX1544_VRM
VCC_CORE_S0(Imax=27.3A)
PM_SLP_S5#
1D2V_S0_EN
S5PWR_ENABLE
GND
DCBATOUT_5130
DCBATOUT_5130
DCBATOUT
5V_S5
5V_AUX_S5
5V_S0
5V_S5 (6A)
3D3V_S5 (4A)
MAX1999_LDO5 (30mA)
MAX1999_LDO3 (30mA)LDO3 (O)
B
TI TPS5130 2D5V/1D2V/1D8V
Input Signal
FOR
SS_STBY1(I / 5V)
SS_STBY2(I / 5V)
SS_STBY3(I / 5V)
STBY_LDO(I / 5V)
STBY_VREF5(I / 28V)
STBY_VREF3.3(I / 28V)
Input Power
VIN (I / 28V)
REG5V_IN(I / 5V)
5V_AUX_S5
For PGOUT
CHARGE_OFF
BT_TH
BAT+SENSE
BT_SCL_5
BT_SDA_5
FLASH_GPIO1
FLASH_GPIO2
AC_IN
AD+
2.5V FOR
1.2V FOR
1.8V
CLS (I / 3.3V)
THM (I / 3.3V)
BATT (I / 3.3V)
SCL (IO / 5V)
SDA (IO / 5V)
RESET#/PB5 (I/5V)
PB0/MOSI/AIN0
PB0/MOSI/AIN0
Input Power
DCIN (I)
C
Output Signal
PGOUT(OD / 5V)
Output Power
2D5(O)
1D2V(O)
1D8V(O)
LDO(O)
Charger_Max8725
Output SignalInput Signal
LDO (O / 5.4V)
XTAL2/PB4 (O/5V)
XTAL1/PB3 (O/5V) BL2#
Output Power
VCC (O)
VCC (O)
C
Pull High (5V)
2D5V (9A)
1D2V (5A)
1D8V (5A)
AD_IN
CHARGE_LED#
DCBATOUT
BT+
D
DCBATOUT
AUX_SD
2D5V_S3
5V_S5
APL5331_1D25V_VREF
5V_S0
DCBATOUT
PM_SLP_S3#
AD_OFF
AD_JK
5V_AUX_S5
(Power Team)
D
E
5V_AUX_S5
INPUT
SD
LP2951ACM
OUT
5V_AUX_S5
1D25V_S3
VIN
1D25V_S0
VCNTL
VOUT
VREF
APL5331KAC
FAN5234_VGA_Core 1D15V or 1D20V
Input Power
VCC
VIN
Input Signal
EN
Output Signal
PG
Output Power
1D15V (O) or 1D20V (O)
1D15V (5.2A) or 1D20V (9A)
Adapter
Input Signal
(I)
Input Power
VCC(I)
VCC(I)
Title
Size Document Number Rev
A3
Date: Sheet
Output Signal
AD_IN
(O)
Output Power
VCC(O)
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
POWER BLOCK DIAGRAM
Bolsena
40 58Tuesday, December 28, 2004
E
AD+
of
SA
Page 41
A
CPU_VCORE VID=1.20V Iomax=27.3A (35W)
4 4
TABLE 1. VOLTAGE IDENTIFICATION CODES VID4 VID3 VID2 VID1 VID0 DAC 0 0 0 0 0 1.550 0 0 0 0 1 1.525 0 0 0 1 0 1.500 0 0 0 1 1 1.475 0 0 1 0 0 1.450 0 0 1 0 1 1.425 0 0 1 1 0 1.400 0 0 1 1 1 1.375 0 1 0 0 0 1.350 0 1 0 0 1 1.325 0 1 0 1 0 1.300 0 1 0 1 1 1.275 0 1 1 0 0 1.250 0 1 1 0 1 1.225 0 1 1 1 0 1.200 0 1 1 1 1 1.175 1 0 0 0 0 1.150 1 0 0 0 1 1.125
3 3
1 0 0 1 0 1.100 1 0 0 1 1 1.075 1 0 1 0 0 1.050 1 0 1 0 1 1.025 1 0 1 1 0 1.000 1 0 1 1 1 0.975 1 1 0 0 0 0.950 1 1 0 0 1 0.925 1 1 0 1 0 0.900 1 1 0 1 1 0.875 1 1 1 0 0 0.850 1 1 1 0 1 0.825 1 1 1 1 0 0.800 1 1 1 1 1 Shutdown
2 2
12
1544_AGND
1544_AGND
VID[4..0]6
R867 60K4R3F
B
DCBATOUT_MAX1544 3D3V_S0
R839 0R3-U
1 2
MAX1544_V+
12
R837 12K7R2F
DY
1 2
1 2
R865 121KR3F
12
1544_AGND
R878 0R0402-PAD
1544_AGND
12
C1037 SC100P
MAX1544_ILIM
MAX1544_VCC
R870 80K6R3F
1 2
R866
12
100KR3F
R869 100KR3
1544_AGND
C637
SC1U25V-U
MAX1544_TIME
MAX1544_OFSMAX1544_REF MAX1544_REF MAX1544_CCI
VID0_PWM VID1_PWM VID2_PWM VID3_PWM VID4_PWM MAX1544_OVP
12
C1038 SCD022U16V2KX-1
12
C641
12
1544_AGND
SC1U10V3KX
12
SC2D2U10V5KX
1 2 3 7 8
14 24
23 22 21 20 19
MAX1544ETL
12
R879 1KR3F
C
C673
U132
TIME TON SUS OFS REF CCI
D0 D1 D2 D3 D4 OVP
12
R873 1K82R3F
5V_S0
12
MAX1544_VCC
10
30
VCC
OAIN-
16
17
MAX1544_OAIN-
12
3
VDD
OAIN+
MAX1544_OAIN+
R836 10R3
MAX1544_V+
36
V+
S04S1
R875 1K82R3F
D45
BAW56-1
12
MAX1544_SKIP#
18
SKIP#
5
12
2
MAX1544_BSTM
1
R864 100KR3
6
38
33
DHS
CMN
SHDN#
GNDS
FB
BSTS
13
15
35
MAX1544_FB
12
12
C1040 SC470P50V
R880 1KR3F
MAX1544_CMP
MAX1544_FB MAX1544_CMN
MAX1544_VCC
37
40
39
CSP
CSN
CMP
GND
PGND31GND
11
41
1544_AGND
MAX1544_GNDS
12
R876 1MR3
1544_AGND
MAX1544_CCI
DLM DHM
LXM BSTM VROK
CCV
DLS
LXS
ILIM
12
C1041
SC1000P25V
12
29 28
27 26 25
12 32 34 9
R877 100R3
R881 0R2-0
D
MAX1544_ILIM
12
1544_AGND
COREFB 6
VCC_CORE_S0
1 2
12
C1039
R871
SC270P50V
24K9R3F
1544_AGND
COREFB# 6
12
R868 100KR3
R863 10KR3
1 2
C1035 SCD22U16V3ZY
3D3V_S0
VCORE_EN 39,48
MAX1544_CMN 42 MAX1544_CMP 42
MAX1544_DLM 42 MAX1544_DHM 42 MAX1544_LXM 42
MAX1544_BSTM
VRM_PWRGD 21,39
E
VID0_PWM
VID1_PWM
VID2_PWM
1 1
VID3_PWM
VID4_PWM
A
1 2
1 2
1 2
1 2
1 2
R883 0R0402-PAD
R890 0R0402-PAD
R894 0R0402-PAD
R895 0R0402-PAD
R896 0R0402-PAD
VID0
VID1
VID2
VID3
VID4
VCC_CORE_S0 feedback
<Variant Name>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
A3
B
C
D
(Power Team)
Date: Sheet
CPU Vcore 1
Bolsena
SA
of
41 58Tuesday, December 28, 2004
E
Page 42
A
4 4
DCBATOUT
MAX1544_DHM41
3 3
MAX1544_LXM41 MAX1544_DLM41
G122
G137
1 2
G142
GAP-OPEN-PWR
1 2
G138
GAP-OPEN-PWR
1 2
G139
GAP-OPEN-PWR
1 2
G140
GAP-OPEN-PWR
1 2
G141
GAP-OPEN-PWR
1 2
GAP-OPEN-PWR
1 2
12
TC11
GAP-OPEN-PWR
SE100U25VM-1-U
B
DCBATOUT_MAX1544
D
U116
1
G
1
G
FDD8880
Id=51A
2 3
Qg=13~17nC
S
Rdson=9~13mohm USD:0.16
D
U129 FDD8896
3 4
S
G
1 2
D
1
3 4
S
1 2
1 2
1 2
U130 FDD8896
C
C1043 SC10U35V0ZY-L
C679 SC10U35V0ZY-L
C680 SC10U35V0ZY-L
C678 DUMMY-C3
D47
DY
SSM54-U
2 1
NC1
L27
1
L-D48UH-U
NC2
2
1 2
R882 D001R7520F
12
R893 0R0402-PAD
VCC_CORE_S0
MAX1544_CMN 41 MAX1544_CMP 41
D
VCC_CORE_S0
12
12
12
TC37
TC33
ST330U2D5VDM-3
ST330U2D5VDM-3
80.3371V.191
80.3371V.191
KEMET 330uF / 2.5V / ESR=9mohm / Iripple=3.7A
7.3/4.3/1.9, NT:9.0
12
TC32 ST330U2D5VDM-3
80.3371V.191
12
TC40
TC38
ST330U2D5VDM-3
ST330U2D5VDM-3
80.3371V.191
80.3371V.191
DY
E
12
TC39 ST330U2D5VDM-3
80.3371V.191
DY
Id=35A Qg=24~32nC Rdson=5.7~6.8mohm USD:0.23
2 2
1 1
(Power Team)
A
B
C
D
<Variant Name>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
A3
Date: Sheet
CPU Vcore 2
Bolsena
42 58Tuesday, December 28, 2004
E
of
SA
Page 43
A
B
G70
C
D
E
G126
G67
DCBATOUT_MAX1999_1
R537 4D7R5
R543
10KR3 R553 DUMMY-R3
C1003 SCD22U16V3ZY
1 2
GAP-OPEN-PWR
G65
1 2
GAP-OPEN-PWR
G66
1 2
GAP-OPEN-PWR
G60
1 2
GAP-OPEN-PWR
1 2
GAP-OPEN-PWR
12
12
R856 300KR3
5130_PGOUT44
S5PWR_ENABLE23,44,48
MAX1999_SHDN#
MAX1999_TON
MAX1999_SKIP#
12
R852 DUMMY-R3
MAX1999_ILIM5_3
MAX1999_LDO5 MAX1999_VCC
R851
1 2
10R3
MAX1999_BST5
U54
17
VCC
14
BST5
16
DH5
MAX1999_LX 5
15
LX5
19
DL5
21
OUT5
9
FB5
10
PRO#
1
NC
MAX1999_ILIM5
11
ILIM5
MAX1999_ILIM3
5
ILIM3
MAX1999_PGD
2
PGOOD
23
GND
LDO5
MAX1999EEI
18
OCP Setting
MAX1999_LDO5MAX1999_LDO3
30mA MAX.30mA MAX.
R789
1 2
0R3-U
12
C699 SC1U25V5ZY
MAX1999_ILIM5
12
R538 10KR3F
MAX1999_DH5
MAX1999_DL5
MAX1999_FB5
MAX1999_PRO#
5V_AUX_S5
20
V+
3
D49
2
BAW56
LDO3
25
12
C700 SC1U25V5ZY
1 2
1
12
12
C697
C698
SC1U25V5ZY
SCD1U
MAX1999_BST3
C1004
R853
SCD1U
GAP-CLOSE-PWR
1 2
MAX1999_BST3_1 MAX1999_BST5_1
28
BST3
26
DH3
27
LX3
24
DL3
22
OUT3
7
FB3
3
ON3
4
ON5
6
SHDN#
13
TON
8
REF
12
SKIP#
Adjust 3V/5V current limit
C
C999 SC1U10V3KX
12
R857
GAP-CLOSE-PWR
1 2
1 2
12
12
R552 8K66R3F
MAX1999_ILIM3
12
R551 10KR3F
C1001 SCD1U
R541 100KR3
DY
1 2
R546 20KR3F
MAX1999_ILIM5_3
SC: 3.3V R186=>20KR3F OCP: Main Source Adapter=10.6A Battery=10.4A Second Source Adapter=9.4A Battery=9.2A
678
U89
DDD
AO4422
SSS
GD
123
4 5
678
U103
DDD
AO4422
SSS
GD
123
4 5
R858
MAX1999_LDO5
10KR3
Open Drian
R549
1 2
GAP-CLOSE-PWR
SC: 5V R214=>40K2R3F OCP: Main Source Adapter=12.6A Battery=11.6A Second Source Adapter=16.4A Battery=14.4A
(Power Team)
D
78.47522.521
DY
84.04422.037
MAX1999_VCC
DCBATOUT_MAX1999
12
12
C996 SC4D7U25V6KX
1 2
68.6R810.10A
12
C695 SC47P50V2JN
MAX1999_LX5_1
DY
12
R540 2MR3
DY
<Variant Name>
Title
Size Document Number Rev
A3
Date: Sheet
12
C1006
C1007
SC10U35V0ZY-U
SCD1U
Imax=6.0A, DCR=25mohm 12*12*3.9
L30 IND-6D8UH-14
12
MAX1999_FB5
12
Max1999 / 3D3V / 5V
12
12
R545 15KR3F
C703 SC100P50V2JN
R548 9K76R3F
MAX1999_SHDN#
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Bolsena
SYSTEM DC/DC 3D3V_S5/5V_S5
4 4
3D3V_DC_S5
3 3
Iomax=4.0A
G109
G127
1 2
GAP-OPEN-PWR
G125
1 2
GAP-OPEN-PWR
G128
1 2
GAP-OPEN-PWR
G129
1 2
GAP-OPEN-PWR
G124
1 2
GAP-OPEN-PWR
1 2
GAP-OPEN-PWR
3D3V_S5
DCBATOUT_MAX1999
12
12
C995
C1000
SCD1U
SC10U35V0ZY-U
DY
U82
SSS
AO4422
123
678
DDD
GD
4 5
DCBATOUT_MAX1999
U88
AO4422
123
84.04422.037
OCP:8A~9.5A
3D3V_DC_S5
L28
1 2
IND-6D8UH-14
68.6R810.10A
12
12
R542 6K65R3F
R547 10K2R3F
Imax=6.0A, DCR=25mohm 12*12*3.9
12
12
C1002 DUMMY-C3
TC24 ST150U6D3VDM-9
80.15715.191
KEMET, NT=6.35 ST150U6D3VDM-9
80.15715.191 ESR=40mohm Iripple=1.7A
2 2
7.3/4.3/1.9
12
C701 SC100P50V2JN
12
C694 SC47P50V2JN
DY
MAX1999_LX3_1
12
R544 2MR3
DY
MAX1999_VCC
Ton = VCC : 200KHz/300KHz Ton = GND : 400KHz/500KHz (5V/3D3V)
MAX1999_VCCMAX1999_VCC
12
R554 100KR3
1 1
MAX1999_SKIP
A
U102 2N7002DW
1 2 3 4
MAX1999_SKIP#
6 5
12
R539 100KR3
PM_SLP_S3# 18,21,34,38,39,44,57
DCBATOUT DCBATOUT_MAX1999 5V_S55V_DC_S5
1 2
678
DDD
84.04422.037
SSS
GD
4 5
MAX1999_DH3 MAX1999_LX 3 MAX1999_DL3
MAX1999_FB3
1 2
1 2
MAX1999_REF
12
B
1 2
GAP-OPEN-PWR
1 2
GAP-OPEN-PWR
1 2
GAP-OPEN-PWR
1 2
GAP-OPEN-PWR
1 2
GAP-OPEN-PWR
1 2
GAP-OPEN-PWR
1 2
GAP-OPEN-PWR
1 2
GAP-OPEN-PWR
Iomax=5A OCP:12~14A
5V_DC_S5
C1005 DUMMY-C3
43 58Tuesday, December 28, 2004
E
G130
G131
G133
G132
G75
G76
G71
12
TC26 ST220U6D3VDM-4
80.22715.191
KEMET, NT:8.22 ESR=25mohm Iripple=2.2A
7.3/4.3/1.9
12
12
C696 SCD1U
of
R550 100KR3
SA
Page 44
5
A
For 1.8V SETTING=1 .8275V
R531
1 2
10KR2F-U
12
R823
R534 10KR2F-U
2KR3
12
C990 SC3900P50V3KX
12
R842 2KR3
12
C987 SC3900P50V3KX
D D
63.20234.151
For 2.5V SETTING=2.516V
1 2
63.20234.151
1 2
5130_INV3 5130_FB3
1 2
5130_INV1 5130_FB1
R849
1 2
680R3F
R525
1 2
11K5R3F
close to IC
R846
1 2
330R2F
R532
1 2
19K6R3F
close to IC
78.56224.2B1
78.56224.2B1
1D8V_PWR
C984 SC5600P50V3KX
2D5V_PWR
C967 SC5600P50V3KX
PWM_SEL
C C
3D3V_AUX_S5
U46E
TSLCX14MTC-L-U
PM_SLP_S5#21,34,57
3D3V_AUX_S5
B B
1D2V_S0_EN39,55
5V_AUX_S5
R526
1 2
100KR2
PM_SLP_S3#18,21,34,38,39,43,57
147
11 10
147
9 8
TPS5130_1D8V_EN#
U46D
TSLCX14MTC-L-U
T(soft)=1.736ms
PM_SLP_S5
5130_SS_STBY2
12
12
C690
SC4700P50V3KX
1D2V_S0_EN#
U53 2N7002DW
3 4 2 1
84.27002.03F
R528
1 2
0R2-0
DY
U51 2N7002DW
5 6
R527 100KR2
5 6
5130_STBY_LDO
12
34 2 1
S5PWR_ENABLE 23,43,48
5130_SS_STBY3
12
78.47224.2B1
R536 0R2-0
5130_SS_STBY1
1D2V_S0_EN#
C976 SC4700P50V3KX
4
TI TPS5130 for 2.5V, 1.2V, 1.8V
Vo=(R1*0.85)/R2+0.85
(2D5V=>CH1 , 1D2V=>CH2 , 1D8V =>CH3)
For 1.2V SETTING=1 .2172V
R530
1 2
10KR2F-U
63.20234.151
C989
SC3300P50V3KX
Condition Voltage
H : Auto PWM/SKIP 2.2V(Min)~
*
L : PWM fixed (300KHz) ~0.3V(Max)
C689
1 2
SC4700P50V3KX
5130_3D3V_LDO
12
R529
100KR2
R535
1 2
DUMMY-R2
ZZ.DUMMY.X02
DCBATOUT_5130
1 2
12
12
R840 2KR3
5130_FLT
12
R816 100KR2
5130_PGOUT43
1 2
close to IC
5130_INV2 5130_FB2
C985 SCD01U16V2KX
5130_FB1 5130_SS_STBY1 5130_INV2 5130_FB2 5130_SS_STBY2 5130_PWMSELPM_SLP_S3# 5130_CT
5130_REF STBY_REF
5130_STBY_LDO
5130_CT
12
C966 SC47P50V2JN
78.47034.1F1
5130_REF
12
C965 SCD1U
R845 680R3F
1 2
1 2
R523 4K32R3F
1 2 3 4 5 6 7 8
9 10 11 12
5130_SS_STBY3 5130_FB3 5130_INV3
5V_S0
12
1D2V_PWR
C968 SC4700P50V3KX
5130_FLT 5130_INV1
FB1 SS_STBY1 INV2 FB2 SS_STBY2 PWM_SEL CT GND REF STBY_VREF5 STBY_VREF3.3 STBY_LDO
R533 10KR2
3
5130_5V_LDO
1
2
D44
83.00054.L03
3
BAT54-1
5130_LH1
1 2
44
45
LL1
LH1
OUT1_D43OUT2_D
OUT1_U
OUTGND142OUTGND2
40
TRIP141TRIP2
VIN_SENSE12
47
46
48
FLT
INV1
TPS5130
FB3
INV3
LH3
TRIP3
VIN_SENSE3
PGOUT16PG_DELAY
18
19
17
5130_PG_DELAY
12
C469 SC2200P50V2KX
OUT3_U
20
21
5130_LH3
3
5130_TRIP3
SS_STBY3
13
14
15
5130_LL1
C992 SCD1U50V3KX
5130_OUT1U 5130_OUT1D
5130_TRIP1 5130_TRIP2
5130_OUT2D
38
39
37
REG5V_IN
LDO_CUR
LDO_GATE
LDO_OUT
INV_LDO
LL3
OUT3_D
OUTGND3
22
23
24
5130_OUT3D 5130_LL3 5130_OUT3U
1 2
D40
BAT54-1
83.00054.L03
5130_LL1 45
5130_OUT1U 45 5130_OUT1D 45
DCBATOUT_5130
U101
36
LL2
35
OUT2_U
34
LH2
33
VIN
32
VREF3.3
31
VREF5
30 29
LDO_IN
28 27 26 25
TPS5130PT-U
C993 SCD1U50V3KX
5130_5V_LDO
1 2
DCBATOUT_5130
5130_5V_LDO
1
2
D48
83.00054.L03
3
BAT54-1
5130_OUT2D 45
5130_LH2
5130_OUT2U
5130_REGIN
5130_3D3V_LDO
LDO SETTING
5130_OUT3D 45 5130_OUT3U 45 5130_LL3 45
2
C970
1 2
SCD1U50V3KX
close to IC
R841
1 2
0R5J-1
2D5V_OCP
1 2
5130_TRIP1
close to IC
1D2V_OCP
1 2
5130_TRIP2
close to IC
1D8V_OCP
1 2
5130_TRIP3
close to IC
5130_LL2
DCBATOUT_5130
5130_OUT2U 45
5V_AUX_S5
PWM_SEL
(Power Team)
1
G57
DCBATOUT_5130DCBATOUT
DCBATOUT_5130
R843 28K7R3F
C991
1 2
1 2
1 2
5130_LL2 45
1 2
5V_S5
1 2
SCD1U
R817 22K1R3F
C969 SCD1U
R844 22K1R3F
C975 SCD1U
C688 SCD1U50V3KX
R803
DUMMY-R3
OCP 12A=>R225=18K 18A=>R225=28K
DCBATOUT_5130
OCP
8.4A=>R226=13K 10A=>R226=22K
DCBATOUT_5130
OCP
8.4A=>R229=12.65K
10A=>R229=22K
C693 SC4D7U10V5ZY
78.47593.411
5130_3D3V_LDO
5130_5V_LDO
12
12
Condition Voltage
H : Auto PWM/SKIP 2.2V(Min)~
*
L : PWM fixed (300KHz) ~0.3V(Max)
<Variant Name>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
TPS5130 1D2V/1D8V2D5V/ (1/2)
Size Document Number Rev
A3
Date: Sheet
Bolsena SA
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
ZZ.CON2C.XX1
C691 SC4D7U10V5ZY
78.47593.411
44 58Tuesday, December 28, 2004
G56
GAP-OPEN-PWR
G61
GAP-OPEN-PWR
G62
GAP-OPEN-PWR
G69
GAP-OPEN-PWR
G68
GAP-OPEN-PWR
G85
GAP-OPEN-PWR
G84
GAP-OPEN-PWR
GAP-OPEN-PWR
G123
GAP-CLOSE
of
A
Page 45
A
TI TPS5130 for 2D5V, 1D2V, 1D8V
5
(2D5V=>CH1 , 1D2V=>CH2 , 1D8V =>CH3)
4
DCBATOUT_5130
3
2
1
D D
5130_OUT1U44 5130_LL144
5130_OUT1D44
5130_OUT1U 5130_LL1
84.04406.037
5130_OUT1D
U58
AO4422
GD
4 5
U55
AO4406
GD
4 5
678
DDD
Imax=9.3A
SSS
Rdson=19.6~24mohm
123
678
DDD
Imax=9.6A
SSS
Rdson=13.5~16.5mohm
123
C C
678
DDD
U86
AO4422
Imax=9.3A
SSS
GD
Rdson=19.6~24mohm
123
4 5
5130_OUT2U44 5130_LL244
B B
5130_OUT2D44
5130_OUT3U44 5130_LL344
5130_OUT3D44
5130_OUT2U
5130_LL2
AO4422
5130_OUT2D
AO4422
5130_OUT3U
5130_LL3
AO4422
5130_OUT3D
678
DDD
U81
SSS
GD
123
4 5
678
DDD
U56
SSS
GD
123
4 5
678
DDD
U57
SSS
GD
123
4 5
Imax=9.3A Rdson=19.6~24mohm
Imax=9.3A Rdson=19.6~24mohm
Imax=9.3A Rdson=19.6~24mohm
12
C676 SCD1U
L32
1 2
IND-2D2UH-6
Imax=8A DCR=20mOhm 7*7*3.0
12
C979 SCD1U
L31
1 2
IND-3D3UH-35
Imax=6A DCR=30mOhm 7*7*3.0
12
C674 SCD1U
L26
1 2
IND-4D7UH-16
Imax=5.5A DCR=40mOhm 7*7*3.0
12
TC25 ST220U4VDM-L3
KEMET, NTD:6.5 (Q1) ESR=40mohm Iripple=1.7A
7.3*4.3*1.2
12
2D5V_S3
12
DCBATOUT_5130
12
1D2V_PWR
12
DCBATOUT_5130
12
1D8V_PWR
12
C675 SC10U35V0ZY-U
2D5V Iomax=9A OCP>18A
TC29 ST330U6D3VDM-7
KEMET, NTD:10.5 (Q1) ESR=25mohm Iripple=2.2A
7.3*4.3*1.9
C978 SC10U35V0ZY-U
1D2V Iomax=5A OCP>10A
TC13 ST220U4VDM-10
KEMET, NTD:7.8 (Q1) ESR=25mohm Iripple=2.2A
7.3*4.3*1.9
C677 SC10U35V0ZY-U
1D8V Iomax=5A OCP>10A
TC23 ST220U4VDM-10
KEMET, NTD:7.8 (Q1) ESR=25mohm Iripple=2.2A
7.3*4.3*1.9
1D2V_PWR 1D2V_S0
G42
G43
1 2
GAP-OPEN-PWR
G53
1 2
GAP-OPEN-PWR
G52
1 2
GAP-OPEN-PWR
G51
1 2
GAP-OPEN-PWR
G55
1 2
GAP-OPEN-PWR
G54
1 2
GAP-OPEN-PWR
1 2
GAP-OPEN-PWR
G44
G45
1 2
GAP-OPEN-PWR
G46
1 2
GAP-OPEN-PWR
G47
1 2
GAP-OPEN-PWR
G48
1 2
GAP-OPEN-PWR
G49
1 2
GAP-OPEN-PWR
G50
1 2
GAP-OPEN-PWR
1 2
GAP-OPEN-PWR
1D8V_S51D8V_PWR
(Power Team)
<Variant Name>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
TPS5130 1D2V/1D8V2D5V/ (2/2)
Size Document Number Rev
A3
Date: Sheet
Bolsena
45 58Tuesday, December 28, 2004
SA
of
A
Page 46
A
4 4
B
C
D
E
3D3V_AUX_S5
Ra
3D3V_AUX_S5
3 3
G150
1 2
GAP-OPEN-PWR
12
12
C963
C964
SC10U10V5ZY
SCD1U
DY
Vout = 1.23 * (Ra / Rb)
1 2
1 2
U49
1
OUT
2
SENSE
3
SD
4
GND
LP2951ACM
R891 169KR2F
C962 SC330P50V2KX
100mA
LP2951ACM_FB3D3V_LP2951_AUX_S5
INPUT
5V/TAP
ERROR
DCBATOUT
8 7
FB
6
12
5
Rb
R892 100KR2F
12
C1042 DUMMY-C5
12
C524
C524 SC1U50V5ZY
78.10594.411 DY
2D5V_S3
12
C687 SC10U10V5ZY
78.10693.411
2 2
1 1
A
12
C686 SC10U10V5ZY
78.10693.411 DY
2D5V_S3
12
R522 1KR3F
APL5331_1D25V_VREF
12
R521 1KR3F
5V_S5
NC NC
B
1D25V_S3 Iomax=1.5A
Vo(cal.)=1.250V
4 8
7 5
12
TC12 ST100U4VBM-1
KEMET 100uF / 4V / B2 Size / NTD:5.615 Iripple=1.1A / ESR=70mohm
12
C682 SCD1U
U50
VIN1VOUT
3
VREF
12
C683 SCD1U
VCNTL6NC
2
GND
9
GND
APL5331KAC-TR
SO-8-P
1 2
1 2
1 2
1 2
12
C685 SC22U10V6ZY-U
78.22693.421
G63
G58
GAP-OPEN-PWR
G59
GAP-OPEN-PWR
G64
GAP-OPEN-PWR
GAP-OPEN-PWR
C
1D25V_S31D25V_LDO
Trace Length=1cm (500mils) Trace Width=8mils Trace Resistance>25mohm
(Power Team)
D
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
1D2V_S3 / 3D3V_AUX
Size Document Number Rev
A3
Date: Sheet of
Bolsena
E
46 58Tuesday, December 28, 2004
SA
Page 47
AC_IN Threshold 2.089V Max. AC_IN > 2.089V --> AC DETECT
ACOK is 17.8V
D33
CH521S-30
MAX1909_REF
12
R600
49K9R2F
Icharge=2.967A
12
R601
51K1R2F
R886 2K8R3F-L
D
Q47 2N7002
S
CHG_ON#34
From KBC
3D3V_AUX_S5
12
R560 100KR3
D
Q44
1
2N7002
G
S
2 3
Pre charge=2.967A
PRE_CHG34
AD+
12
1
G
2 3
?AFTER ADD PRE_CHG,NEED A-D TEST VOLTAGE?
G99
AD_IA34
AC_IN#34
1 2
GAP-CLOSE-PWR
12
12
R599 10KR3F
3D3V_AUX_S5
U46C
147
56
TSLCX14MTC-L-U
AD+
12
12
21
R612 100KR3F
MAX1909_ACIN
R617 13K3R3F
12
C1013 SCD1U
MAX1909_LDO
U79
D
8
D
7
D
6
AO4407
12
12
R609
R602
100KR3
100KR3
CELL is 4 Cell
From Battery Connector
12
R603 10KR3
12
C1010
12
12
R559 31K6R3F
R556 49K9R3F
SCD01U50V3KX
12
C1025 SCD1U16V3KX
MAX1909_LDO
MAX1909_ACOKMAX1909_ACOKMAX1909_ACOKMAX1909_ACOK
12
C704 SC1U10V3KX
C1019 SCD1U16V3KX
S
1
S
2
S
3
GD
45
12
Close to MAX1909 pin 24
MAX1909_PDS AD+_TO_SYS MAX1909_DC_IN
MAX1909_VCTL MAX1909_ICTL MAX1909_MODE
MAX1909_IINP
MAX1909_CLS
MAX1909_ACOK
PKPRES#
MAX1909_CCV
MAX1909_CCI
MAX1909_CCS
C1021 SCD01U50V3KX
12
C1018
SC1U10V3KX
AD+_TO_SYS
C1009 SC1U50V5ZY
12
C1016 SCD1U
U77
27
PDS
24
SRC
1
DCIN
11
VCTL
10
ICTL
7
MODE
3
ACIN
8
IINP
9
CLS
6
ACOK
5
PKPRES
13
CCV
12
CCI
14
CCS
MAX8725ETI
1 2
G110
GAP-CLOSE-PWR
1 2
12
26
CSSP
MAX1909_REF
12
R861 D01R2512F-1
G134
GAP-CLOSE-PWR
1 2
AD+_TO_SYS
C1023
REF
4
SCD1U
25
CSSN
DHIV
LDO
DLOV
DLO
PGND PGND
CSIP
CSIN
BATT
GND
PDL
12
C1011 SCD1U
MAX1909_DHIV
22 28 2
MAX1909_DLOV
21
MAX1909_DHI
23
DHI
MAX1909_DLO
20
19 29 18
17 16 15
V_REF :4.2235V (<500uA)
12
R608 49K9R3F
MAX1909_CLS
12
R607 34K8R3F
ISOURCE_MAX = (0.075/R861)*(VCLS/VREF) TOTAL_POWER : Adapter=65W,Total_Power=58.5W
DCBATOUT
For EMI
12
C1008 SCD1U
DY
MAX1909_LDO
Near MAX1909 Pin 2
C1015
1 2
SC1U10V3KX
12
R620 33R3
Near MAX1909 Pin 21
12
C1026 SC1U10V3KX
G41
1 2
GAP-CLOSE-PWR
BAT+SENSE 48
From Battery Connector
MAX1909_PDL
1 2
45
U112
GD
DDD
AO4411
678
678
U108
DDD
AO4422
GD
4 5
U111
S
1
S
2
S
12
1 2
DY
2 1
3
GD
4 5
AO4407 U109
S
1
S
2
S
3
GD
4 5
AO4407
C1024 SCD1U
L29 IND-15UH-30
BAT_THERMAL34,48
12
R860 DUMMY-R3
R561 DUMMY-R3
123
SSS
PC Id=4.6A Rdson=36~50mohm
CHG_PWR-2 CHG_PWR-3
D50
SSS
123
NC Id=5.0A Rdson=23~30mohm
B220LFA
(Power Team)
DY
12
C1022 SC10U25V6KX
D
8
D
7
D
6
D
8
D
7
D
6
DCBATOUT
1 2
G101
GAP-CLOSE-PWR
1 2
BT+
12
DY
C705 SCD1U
12
C1020 SC10U25V6KX
BT+
R862 D015R2512F-1
DY
12
G100
GAP-CLOSE-PWR
1 2
<Variant Name>
Title
Size Doc u ment Number R ev Custom
Date: Sheet
C1017 SC10U25V6KX
MAX1909_LDO
12
R558 68KR3F
R887
12
0R2-0
12
R555 100KR2
CHARGER MAX8725
Bolsena
12
12
PKPRES#
C1012
C1014
SC10U25V0KX
SC10U25V0KX
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
47 58Tuesday, December 28, 2004
of
SA
Page 48
A
B
C
D
E
Adaptor in to generate DCBATOUT
R900 0R2010
1 2 1 2
Can put under diode (if possible)
DOCK_AD+
4 4
3 3
DC1
DC-JACK75
22.10037.701
12
C339 SCD1U50V3ZY
AD_JK
12
12
C338 SCD1U50V3ZY
1
G
R99 1KR3
4
1
2
3
AD_OFF34
R901 0R2010
2
1
Dummy when no EZ4
AD_OFF#_JK
D
Q42 2N7002
S
2 3
D46
3
SBM1040CT-13
1
DY
DY
D25
3
AD_JK_1
1 2 3
AD+_2
R520 56KR3F
4 5
R519
12
12
100KR3
2
E
Q41
B
PDTA124EU
C
3
C521 SCD1U50V3ZY
12
2
DY
1
PZM24NB1
U52
S
D S S GD
AO4407
8
D
7
D
6
ID = -10A/70deg Rds(ON) = 24mohm SO-8
5V_AUX_S5
AD+
12
C961 SCD1U
BATTERY CONNECTOR
1
D35
1
2
D36
2
3
DY
83.00099.L01
BAV99-2
BAT_SCL_534
12
BAT_SDA_534
BAT_THERMAL34,47
BAT+SENSE47
MAX1999_LDO5
C
D26
3
BAT54-1
R123 0R2-0
1 2
R125 0R2-0
1 2
1 2
DY
2 1
DY
DY
R838 0R0402-PAD
DY
RSMRST# 23,34
VCORE_EN 39,41
S5PWR_ENABLE 23,43,44
12
C789 SCD1U50V3ZY
BT+
2 2
?after add pre-charge, sense need to kbc?
Put close to battery connector
DCBATOUT
SCD1U10V2MX-1
G680LT1
VCC
DY
C474
DY
5 4
HTH
12
DY
R408 1MR2F
U59
HTH
1
HTH
2
GND
12
DY
R402 15KR2F
DY
12
R328 110KR2F
B
LTH3RESET#/RESET
Low3 Circuit :
L3# at 11.25V
1 1
A
1 2
12
3
83.00099.L01
DY
BAV99-2
1 2
R631 27R3F
C790 SCD1U50V3ZY
12
C791 SC1000P50V2KX
12.78V (High) Turn On
11.25V (Low) Turn Off
D
BAT1
1
R632 27R3F
BTSMCLK BTSMDATA
12
C792 SC1000P50V2KX
<Variant Name>
Title
AD/BATT CONN
Size Document Number Rev
A3
Date: Sheet
2 3 4 5 6 7
SYN-CON7-9
20.80269.007
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Bolsena
48 58Tuesday, December 28, 2004
E
of
SA
Page 49
5
Dummy when use UMA (WHOLE PAGE)
PEG_TXP[15..0]12
PEG_TXN[15..0]12 PEG_RXP[15..0]12 PEG_RXN[15..0]12
12
U90
1
XIN/CLKIN
2
XOUT
3
PD#
4
LF
P2779A-08ST
71.02779.00A
C797 SC270P50V
ORIGNAL P2779A-08TT USE W180-01 GEOMETRY
VDD REF
MODOUT
VSS
8 7 6 5
XTALIN_M24
X9
X-27MHZ-7-U
1 2
P2779A_XO
1 2
P2779A_XI
R638 620R2F
12
12
R634
C793
D D
1MR2
12
SC6P50V3DN
C795
SC6P50V3DN
12
C796 SCD01U16V2KX
adjust SWING at 1.2v
PEG_TXP0
PEG_TXN0
PEG_TXP1
PEG_TXN1
PEG_TXP2
PEG_TXN2
PEG_TXP3
R671 150R2F
PEG_TXN3
PEG_TXP4
PEG_TXN4
PEG_TXP5
PEG_TXN5
PEG_TXP6
PEG_TXN6
PEG_TXP7
PEG_TXN7
PEG_TXP8
PEG_TXN8
PEG_TXP9
PEG_TXN9
PEG_TXP10
PEG_TXN10
PEG_TXP11
PEG_TXN11
PEG_TXP12
PEG_TXN12
PEG_TXP13
PEG_TXN13
PEG_TXP14
PEG_TXN14
PEG_TXP15
PEG_TXN15
C C
3D3V_S0
3D3V_S0
12
R652
B B
A A
10KR2
STERE0SYNC PWRGD_MASK
12
R659 DUMMY-R2
12
R653 DUMMY-R2
1D2V_VGA_S0
R660 0R2-0
1 2
The PERSTB must deplay 4ms from M24 bug.
DIS_LUMA57 DIS_CRMA57 DIS_COMP57
12
12
12
R669 150R2F
R670 150R2F
Place them near to chip
5
3D3V_SS_S0 P2779A_REF VGA_GPIO16
1 2 1 2 1 2
1 2
AG_RST#13,34
1 2
VGA_SMB_CLK13,15,54 VGA_SMB_DAT13,54
1 2 1 2
1 2 1 2 1 2
4
3D3V_S0
GFX_CLK3 GFX_CLK#3
R656 150R2F
R658 100R2
R661 10KR2F-U R663 10KR2
R665 715R3
R672 10KR2
R673 10KR2
R675 1KR2
R676 1KR2
R678 1KR2
4
12
12
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
1 2
12
R635 140R3F
R640 105R3F
TP110 TPAD30
TP111 TPAD30
R633 0R5J-1
C794 SCD1U
C798 SCD1U16V
C800 SCD1U16V
C799 SCD1U16V
C801 SCD1U16V
C803 SCD1U16V
C802 SCD1U16V
C822 SCD1U16V
C804 SCD1U16V
C806 SCD1U16V
C805 SCD1U16V
C808 SCD1U16V
C807 SCD1U16V
C809 SCD1U16V
C810 SCD1U16V
C811 SCD1U16V
C813 SCD1U16V
C812 SCD1U16V
C815 SCD1U16V
C814 SCD1U16V
C816 SCD1U16V
C819 SCD1U16V
C818 SCD1U16V
C821 SCD1U16V
C820 SCD1U16V
C823 SCD1U16V
C824 SCD1U16V
C825 SCD1U16V
C826 SCD1U16V
C827 SCD1U16V
C828 SCD1U16V
C829 SCD1U16V
C830 SCD1U16V
PCIE_CALP_VGA PCIE_CALN_VGA PCIE_CALI_VGA
PCIE_TESTIN
VGA_SSIN VGA_SSOUT
PEG_RXP0
PEG_RXN0
PEG_RXP1
PEG_RXN1
PEG_RXP2
PEG_RXN2
PEG_RXP3
PEG_RXN3
PEG_RXP4
PEG_RXN4
PEG_RXP5
PEG_RXN5
PEG_RXP6
PEG_RXN6
PEG_RXP7
PEG_RXN7
PEG_RXP8
PEG_RXN8
PEG_RXP9
PEG_RXN9
PEG_RXP10
PEG_RXN10
PEG_RXP11
PEG_RXN11
PEG_RXP12
PEG_RXN12
PEG_RXP13
PEG_RXN13
PEG_RXP14
PEG_RXN14
PEG_RXP15
PEG_RXN15
PEG_TXP0_VGA
PEG_TXN0_VGA
PEG_TXP1_VGA
PEG_TXN1_VGA
PEG_TXP2_VGA
PEG_TXN2_VGA
PEG_TXP3_VGA
PEG_TXN3_VGA
PEG_TXP4_VGA
PEG_TXN4_VGA
PEG_TXP5_VGA
PEG_TXN5_VGA
PEG_TXP6_VGA
PEG_TXN6_VGA
PEG_TXP7_VGA
PEG_TXN7_VGA
PEG_TXP8_VGA
PEG_TXN8_VGA
PEG_TXP9_VGA
PEG_TXN9_VGA
PEG_TXP10_VGA
PEG_TXN10_VGA
PEG_TXP11_VGA
PEG_TXN11_VGA
PEG_TXP12_VGA
PEG_TXN12_VGA
PEG_TXP13_VGA
PEG_TXN13_VGA
PEG_TXP14_VGA
PEG_TXN14_VGA
PEG_TXP15_VGA
PEG_TXN15_VGA
PWRGD_MASK
XTALIN_M24
TESTEN
STERE0SYNC
AH30 AG30 AG29
AF29 AE29 AE30 AD30 AD29 AC29 AB29 AB30 AA30 AA29
Y29 W29 W30
V30
V29
U29
T29
T30
R30
R29
P29
N29
N30
M30 M29
K29
K30
AF26 AE26 AC25 AB25 AC27 AB27 AC26 AB26
Y25
W25
Y27
W27
Y26
W26
U25 T25 U27 T27 U26 T26 P25 N25 P27 N27 P26 N26
K25 K27 K26
AF27 AE27
AC23 AB24 AB23
AE25 AD25
AD24 AH21 AK21
AJ22
AK22
AJ24
AK24 AG22
AG23
AJ23 AH24
AH28
AJ29
AH27
AF25 AH25
L29
J30
L25 L27 L26
E8 B6
U91A
PCIE_RX0P PCIE_RX0N PCIE_RX1P PCIE_RX1N PCIE_RX2P PCIE_RX2N PCIE_RX3P PCIE_RX3N PCIE_RX4P PCIE_RX4N PCIE_RX5P PCIE_RX5N PCIE_RX6P PCIE_RX6N PCIE_RX7P PCIE_RX7N PCIE_RX8P PCIE_RX8N PCIE_RX9P PCIE_RX9N PCIE_RX10P PCIE_RX10N PCIE_RX11P PCIE_RX11N PCIE_RX12P PCIE_RX12N PCIE_RX13P PCIE_RX13N PCIE_RX14P PCIE_RX14N PCIE_RX15P PCIE_RX15N
PCIE_TX0P PCIE_TX0N PCIE_TX1P PCIE_TX1N PCIE_TX2P PCIE_TX2N PCIE_TX3P PCIE_TX3N PCIE_TX4P PCIE_TX4N PCIE_TX5P PCIE_TX5N PCIE_TX6P PCIE_TX6N PCIE_TX7P PCIE_TX7N PCIE_TX8P PCIE_TX8N PCIE_TX9P PCIE_TX9N PCIE_TX10P PCIE_TX10N PCIE_TX11P PCIE_TX11N PCIE_TX12P PCIE_TX12N PCIE_TX13P PCIE_TX13N PCIE_TX14P PCIE_TX14N PCIE_TX15P PCIE_TX15N
PCIE_REFCLKP PCIE_REFCLKN
PCIE_CALRP PCIE_CALRN PCIE_CALI
PCIE_TESTIN PERSTb
PERSTb_MASK R2SET Y_G
C_R_PR COMP_B_PB
H2SYNC V2SYNC
DDC3CLK DDC3DATA
SSIN SSOUT
XTALIN XTALOUT
TESTEN TEST_YCLK TEST_MCLK PLLTEST
STEREOSYNC
M26-P-1
3
PCI EXPRESS
DAC2
SS
CLK
3
Part 1 of 6
GPIO_PWRCNTL
GPIO_MEMSSIN
DVOMODE
DVPDATA_0 DVPDATA_1 DVPDATA_2 DVPDATA_3 DVPDATA_4 DVPDATA_5 DVPDATA_6 DVPDATA_7 DVPDATA_8
DVPDATA_9 DVPDATA_10 DVPDATA_11 DVPDATA_12
DVO / EXT TMDS / GPIOTMDSDAC1
DVPDATA_13 DVPDATA_14 DPVDATA_15 DVPDATA_16 DVPDATA_17 DVPDATA_18 DVPDATA_19 DVPDATA_20 DVPDATA_21 DVPDATA_22 DVPDATA_23
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCNTL_3
TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
TXOUT_L2N
TXOUT_L2P
TXOUT_L3N
TXOUT_L3P
TXCLK_LN TXCLK_LP
TXOUT_U0N
TXOUT_U0P
TXOUT_U1N
TXOUT_U1P
LVDS
TXOUT_U2N
TXOUT_U2P
TXOUT_U3N
TXOUT_U3P
TXCLK_UN TXCLK_UP
DDC2CLK
DDC2DATA
DDC1DATA
DDC1CLK
GPIO_AUXWIN
THERM
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8
GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14
VREFG
DIGON
BLON TX0M
TX0P
TX1M
TX1P
TX2M
TX2P
TXCM
TXCP
HPD1
HSYNC VSYNC
RSET
DPLUS
DMINUS
R
G
B
VGA_GPIO0
AJ5
VGA_GPIO1
AH5
VGA_GPIO2
AJ4
VGA_GPIO3
AK4
VGA_GPIO4
AH4
VGA_GPIO5
AF4
VGA_GPIO6
AJ3
VGA_GPIO7
AK3
VGA_GPIO8
AH3
VGA_GPIO9
AJ2
VGA_GPIO10
AH2
VGA_GPIO11
AH1
VGA_GPIO12
AG3
VGA_GPIO13
AG1
VGA_ALERT#
AG2 AF3
VGA_GPIO16
AF2
VGA_DVOMODE
AE10 AH6
AJ6 AK6 AH7 AK7 AJ7 AH8 AJ8 AH9 AJ9 AK9 AH10 AE6 AG6 AF6 AE7 AF7 AE8 AG8 AF8 AE9 AF9 AG10 AF10
AJ10 AK10 AJ11 AH11
AG4
AH15 AH16 AJ16 AJ17 AJ18 AK18 AJ20 AJ21 AK19 AJ19 AG16 AG17 AF16 AF17 AE18 AE19 AF19 AF20 AG19 AG20
AE12 AG12
AK13 AJ13 AJ14 AJ15 AK15 AK16 AJ12 AK12
AE13 AE14
AF12 AK27
AJ27 AJ26
AJ25 AK25
AH26 AG25
AF24 AG24
AF11 AE11
1 2 1 2 1 2
DVPDATA_0, 1, 2 0 0 0 64MB Hynix 0 0 1 64MB Samsung 0 1 0 64MB X brand 0 1 1 64MB Y brand 1 0 0 128MB Hynix 1 0 1 128MB Samsung 1 1 0 128MB X brand 1 1 1 128MB Y brand
DVPCNTL0_VGA DVPCNTL1_VGA DVPCNTL2_VGA DVPCNTL3_VGA
VGA_VREFG
ATI_TXAOUT0- 54 ATI_TXAOUT0+ 54 ATI_TXAOUT1- 54 ATI_TXAOUT1+ 54 ATI_TXAOUT2- 54
ATI_TXAOUT3­ATI_TXAOUT3+
ATI_TXBOUT3­ATI_TXBOUT3+
ATI_TXAOUT2+ 54
ATI_LCDVDD_ON 54 BL_ON 13,34
TMDS_DIS_TX0­TMDS_DIS_TX0+ TMDS_DIS_TX1­TMDS_DIS_TX1+ TMDS_DIS_TX2­TMDS_DIS_TX2+ TMDS_DIS_TXC­TMDS_DIS_TXC+
DIS_DVI_DDC_C 15 DIS_DVI_DDC_D 15
VGA_LOCAL_DP VGA_LOCAL_DN
VGA_ALERT# 54
VGA_PWRPLAY
1 2
R637 DUMMY-R2 R639 DUMMY-R2 R641 DUMMY-R2
1 2 1 2 1 2 1 2
TP106 TP107
TPAD30 TPAD30
TP108 TP109
TPAD30 TPAD30
DVI_HPD 15
1 2
1 2
2
TP102
TP103
TP105 TP104
R636 0R2-0
1D8V_S0
1D8V_S0
R642 0R2-0
R643 0R2-0
R644 0R2-0
R646 0R2-0
ATI_TXACLK- 54 ATI_TXACLK+ 54 ATI_TXBOUT0- 54 ATI_TXBOUT0+ 54 ATI_TXBOUT1- 54 ATI_TXBOUT1+ 54 ATI_TXBOUT2- 54 ATI_TXBOUT2+ 54
ATI_TXBCLK- 54 ATI_TXBCLK+ 54
RN118
1 2 3 4 5
SRN0-1-U
Place Near To EZPORT4
DIS_HS 16 DIS_VS 16
R674 499R2F
DIS_CRT_DDC_D 16 DIS_CRT_DDC_C 16
R677 10KR2
VGA_LOCAL_DP 54 VGA_LOCAL_DN 54
2
VGA_GPIO0 VGA_GPIO4
VGA_GPIO2 VGA_GPIO3
MUST TO CHECK
VGA_GPIO5
DVOMODE=VSS 3.3V MODE DVOMODE=VDDC to 1.8V 1.8V MODE DVOMODE=GND NO USE DVPDATA
STRAPS
PLL_CAL_FORCE_EN
3D3V_S0
12
PCIE_MODE(1:0) CAL_OFF BYPASS_PLL
R645 100R3
ICOMP DEBUG_ACCESS
12
12
C817 SCD1U16V
ROMIDCFG(3:0)
R647
MULTIFUNC(1:0)
100R3
VIP_DEVICE DWNGR0
ATI Ref. Datasheets(page 3-32) DOC.NO.:CHS-216M24-03
GPIO[0..13] are internal pull-down.
TMDS_DIS_TX0- TMDS_DIS_TX0+ TMDS_DIS_TX1­TMDS_DIS_TX2­TMDS_DIS_TXC-
M24/M26 POW ER PL AY (GPI O_PWRCNTL) high (3.3V) = set lower core voltage (VDDC = 1.0V) low (0V) = set higher core voltage (VDDC = 1.2V)
8 7 6
RN119
1
8
2
7
3
6
4 5
SRN0-1-U
DIS_R 57 DIS_G 57 DIS_B 57
R667
R668
R666
150R2F
150R2F
150R2F
1 2
1 2
1 2
<Variant Name>
Title
ATI M26 PCIE LVDS (1/3)
Size Document Number Rev
A3
Date: Sheet
Bolsena
1
3D3V_S0
R654
1 2
10KR2
R655
1 2
10KR2 R657
1 2
DUMMY-R2 R662
1 2
DUMMY-R2 R664
1 2
DUMMY-R2
DEFAULTPIN
GPIO0CAL_BG_BACKUP GPIO1
GPIO(3:2)
GPIO4 GPIO5 GPIO6 GPIO8
GPIO(9,13:11)
LCDDATA(17:16) LCDDATA(20) LCDDATA(21)
(internal pull-down)
RN125
1
8
2
7
3
6
4 5
SRN330-1
TMDS_EZ4_TX0- 15,57
TMDS_EZ4_TX0+ 15,57
TMDS_EZ4_TX1- 15,57
TMDS_EZ4_TX1+ 15,57
TMDS_EZ4_TX2- 15,57 TMDS_EZ4_TX2+ 15,57 TMDS_EZ4_TXC- 15,57
TMDS_EZ4_TXC+ 15,57
VGA_PWRPLAY
VGA_GPIO11 VGA_GPIO10
VGA_GPIO9 VGA_GPIO6 VGA_GPIO7
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
49 58Tuesday, December 28, 2004
1
0 0 00 0 0 0 0
0000
00
0 0
TMDS_DIS_TX1+ TMDS_DIS_TX2+ TMDS_DIS_TXC+
RN77
1 2 3 4 5
SRN10K-2 RN78
1 2 3 4 5
SRN10K-2
of
8 7 6
8 7 6
SA
Page 50
A
Dummy when use UMA (WHOLE PAGE)
M26 : VRAM IS 1.8V M24 : VRAM IS 2.5V
C832
12
12
12
C854
C833
12
VGA_MEM_S0
C834
12
12
C855
C835
12
C856
4 4
SCD01U16V2KX
VGA_MEM_S0
12
C843
SCD01U16V2KX
12
SC1U10V3KX
C844
12
SC1U10V3KX
C845
SC1U10V3KX
SCD01U16V2KX
VGA_MEM_S0
12
C846
SCD01U16V2KX
12
SC10U10V5ZY
C863
SCD01U16V2KX
SC10U10V5ZY
SCD01U16V2KX
SCD01U16V2KX
3 3
2D5V_S0
12
C853 SCD1U16V
1D8V_S0
1 2
R682 0R3-U
1D8V_S0
2 2
2D5V_S0
12
12
C884
C883
SC1U10V3KX
SC10U10V5ZY
1D8V_S0
1 1
1 2
1D8V_S0
1D8V_S0
12
1D8V_TVDD_S0
1D8V_LVDDR_S1
R683 0R3-U
12
12
C886
C885
SC1U10V3KX
SC10U10V5ZY
12
C888
C889
SC10U10V5ZY
SC1U10V3KX
12
C881 SC1U10V3KX
12
C873 SC100P50V2JN
12
C882 SC100P50V2JN
VGA_MEM_S0
1D8V_S0
1 2
1D8V_S0
12
C836
SCD01U16V2KX
1D8V_DDQ
R684 0R3-U
B
U91D
Part 4 of 6
VDD15#AC11 VDD15#AC20
VDDR3#AD19 VDDR3#AD21 VDDR3#AC22
VDDR3#AC21 VDDR3#AC19
VDDR4#AC10 VDDR4#AD10
PCIE_VDDR_12#AG26 PCIE_VDDR_12#AK29
PCIE_VDDR_12#AJ30 PCIE_VDDR_12#AG29 PCIE_VDDR_12#AH29
PCIE_PVDD_12#N24 PCIE_PVDD_12#N23
PCIE_PVDD_12#P23
PCIE_PVDD_18#U23
PCIE_PVDD_18#T23 PCIE_PVDD_18#V23
PCIE_PVDD_18#W23
LVSSR#AF18 LVSSR#AH17 LVSSR#AG15 LVSSR#AG18
TXVSSR#AH12 TXVSSR#AG13 TXVSSR#AG14
A2VSSN#AH20
A2VSSN#AG21
I/O POWER
VDDC#AC13 VDDC#AD13 VDDC#AD15 VDDC#AC15 VDDC#AC17
VDD15#P8 VDD15#Y8
VDD15#H20 VDD15#H11 VDD15#M23
VDD15#Y23
VDDR3#AD7
VDDR3#AC8
VDDR4#AG7
VDDR4#AD9 VDDR4#AC9
NC#D9 NC#D13 NC#D19 NC#D25
NC#E4
NC#T4 NC#AB4
AVSSQ
LPVSS
TPVSS
VSSRH0 VSSRH1
A2VSSQ
AVSSN
VSS1DI VSS2DI
PVSS
MPVSS
K23 K24
H10 H13 H15 H17
AA1 AA4 AA7 AA8
A15 A21 A28
B30 D26 D23 D20 D17 D14 D11
E27
G10 G13 G15 G19 G22 G27 H22 H19
AD4
AE16 AE17
AF15
AE15
AH19 AH13
AF13 AF14
AF21
AE20
AF23
AH23
AE23 AE22
AK28
T7 R4 R1 N8 N7
M4
L8
N4
J8 J7 J4 J1
T8 V4 V7 V8
A3 A9
B1
D8 D5
F4
G7
L23
F18
N6
A7
VDDR1#T7 VDDR1#R4 VDDR1#R1 VDDR1#N8 VDDR1#N7 VDDR1#M4 VDDR1#L8 VDDR1#K23 VDDR1#K24 VDDR1#N4 VDDR1#J8 VDDR1#J7 VDDR1#J4 VDDR1#J1 VDDR1#H10 VDDR1#H13 VDDR1#H15 VDDR1#H17 VDDR1#T8 VDDR1#V4 VDDR1#V7 VDDR1#V8 VDDR1#AA1 VDDR1#AA4 VDDR1#AA7 VDDR1#AA8 VDDR1#A3 VDDR1#A9 VDDR1#A15 VDDR1#A21 VDDR1#A28 VDDR1#B1 VDDR1#B30 VDDR1#D26 VDDR1#D23 VDDR1#D20 VDDR1#D17 VDDR1#D14 VDDR1#D11 VDDR1#D8 VDDR1#D5 VDDR1#E27 VDDR1#F4 VDDR1#G7 VDDR1#G10 VDDR1#G13 VDDR1#G15 VDDR1#G19 VDDR1#G22 VDDR1#G27 VDDR1#H22 VDDR1#H19 VDDR1#AD4 VDDR1#L23
LVDDR_25#AE16 LVDDR_25#AE17 LVDDR_18#AF15 LVDDR_18#AE15
LPVDD TPVDD
TXVDDR#AF13 TXVDDR#AF14
VDDRH0 VDDRH1
A2VDD#AF21 A2VDD#AE20
A2VDDQ AVDD
VDD1DI VDD2DI
PVDD MPVDD
M26-P-1
AC13 AD13 AD15 AC15 AC17
P8 Y8 AC11 AC20 H20 H11 M23 Y23
AD7 AD19 AD21 AC22 AC8 AC21 AC19
AG7 AD9 AC9 AC10 AD10
AG26 AK29 AJ30 AG28 AG27
N24 N23 P23
U23 T23 V23 W23
D9 D13 D19 D25 E4 T4 AB4
AD22
AF18 AH17 AG15 AG18
AH18 AH12
AH14 AG13 AG14
F19 M6
AH20 AG21
AF22 AH22
AE24 AE21
AJ28 A6
C
12
3D3V_S0
3D3V_VDDR3
12
3D3V_VDDR4
1D2V_VGA_S0 1D2V_VGA_VDDR
1D8V_DDQ
C857 SC10U10V5ZY
D38
DY
SSM5818SL
2 1
12
C864 SC1U10V3KX
12
12
C831 SCD01U16V2KX
1D5V_VGA_S0
1 2
C847 SC1U10V3KX
12
C851 SC10U10V5ZY
1 2
1 2
R680 0R3-U
C868 SC1U10V3KX
R685 0R3-U
R686 0R3-U
D
VGA_CORE_S0
12
C858 SCD01U16V2KX
3D3V_S0
1 2
1D8V_VGA_PVDD
12
C878 SC10U10V5ZY
12
C887 SC330P50V2KX
12
C890 SC330P50V2KX
12
12
1D2V_VGA_VDDR
ADD ASIC DECOUPLING FOR ALL POWER AS REQUIRED
WITH AS MAN Y AS P OSS IB LE PL A CED UNDER THE ASIC
1D8V_VGA_PVDD
C837
C859
SCD01U16V2KX
SCD01U16V2KX
12
12
12
3D3V_S0
R679 0R3-U
1D2V_VGA_S0 1D2V_VGA_VDDR
12
C869 SC1U10V3KX
1D2V_VGA_VDDR
12
C874 SC10U10V5ZY
C860
C838
SCD01U16V2KX
SCD01U16V2KX
1D5V_VGA_S0
R681
1 2
0R3-U
12
C875 SCD01U16V2KX
12
C879 SCD01U16V2KX
12
12
12
12
12
C839 SCD01U16V2KX
12
C848
C865
SC1U10V3KX
SC1U10V3KX
C852 SC330P50V2KX
12
C870
C871
SCD01U16V2KX
SCD01U16V2KX
12
12
C876 SCD01U16V2KX
C880 SCD01U16V2KX
C840 SCD01U16V2KX
12
C877 SCD01U16V2KX
PLACED CLOSE TO THE POWER/GND PINS
<Variant Name>
Title
Size Document Number Rev
A3
Date: Sheet
12
C841 SCD01U16V2KX
12
C866 SC1U10V3KX
C872 SCD01U16V2KX
PCIE_VDDR_12 PCIE_PVDD_12
PCIE_PVDD_18
E
DIODE SUPPLIES POWER TO VDDC RAIL WHILE VDDC REGULATOR STABALIZES DURING POWER ON
3D3V_S0
12
12
C849 SC1U10V3KX
12
C862
C861
SCD01U16V2KX
SCD01U16V2KX
D37
DY
SSM5818SL
2 1
12
C842 SCD01U16V2KX
VGA_CORE_S0
DIODE SUPPLIES POWER TO VDDC RAIL WHILE VDDC REGULATOR STABALIZES DURING POWER ON
M22 Power UP Squence
3D3_VDDR3 3D3_VDDR4 2D5_VDDR1 1D2_VDDC
VDD_15
T1 < 1mS
T2 < 1mS
T3 < 1uS
T4 < 100nS
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
ATI M26 POWER (2/3)
Bolsena
VGA_CORE_S0
12
C867 SC1U10V3KX
T5 < 100nS
T6 < 1uS
T7 < 100nS
50 58Tuesday, December 28, 2004
12
C850 SC1U10V3KX
of
SA
Page 51
Dummy when use UMA (WHOLE PAGE)
A
MDA[63..0]52
4 4
3 3
MDA0 MDA1 MDA2 MDA3 MDA4 MDA5 MDA6 MDA7 MDA8 MDA9 MDA10 MDA11 MDA12 MDA13 MDA14 MDA15 MDA16 MDA17 MDA18 MDA19 MDA20 MDA21 MDA22 MDA23 MDA24 MDA25 MDA26 MDA27 MDA28 MDA29 MDA30 MDA31 MDA32 MDA33 MDA34 MDA35 MDA36 MDA37 MDA38 MDA39 MDA40 MDA41 MDA42 MDA43 MDA44 MDA45 MDA46 MDA47 MDA48 MDA49 MDA50 MDA51 MDA52 MDA53 MDA54 MDA55 MDA56 MDA57 MDA58 MDA59 MDA60 MDA61 MDA62 MDA63
2 2
U91B
H28
G26 G30
G29 G28
G25
H29
H25 H26
D29 D28 E28 E29
F28 F26
E26 F25 E24 F23 E23 D22 B29 C29 C25 C27 B28 B25 C26 B26 F17 E17 D16 F16 E15 F14 E14 F13 C17 B18 B17 B15 C13 B14 C14 C16 A13 A12 C12 B12 C10
B10 E13 E12 E10 F12 F11
DQA0 DQA1
J28
DQA2
J29
DQA3
J26
DQA4 DQA5 DQA6 DQA7 DQA8 DQA9 DQA10 DQA11 DQA12 DQA13 DQA14 DQA15 DQA16 DQA17 DQA18 DQA19 DQA20 DQA21 DQA22 DQA23 DQA24 DQA25 DQA26 DQA27 DQA28 DQA29 DQA30 DQA31 DQA32 DQA33 DQA34 DQA35 DQA36 DQA37 DQA38 DQA39 DQA40 DQA41 DQA42 DQA43 DQA44 DQA45 DQA46 DQA47 DQA48 DQA49 DQA50 DQA51 DQA52
C9
DQA53
B9
DQA54 DQA55 DQA56 DQA57 DQA58 DQA59 DQA60
E9
DQA61
F9
DQA62
F8
DQA63
M26-P-1
Part 2 of 6
MEMORY INTERFACE A
MEMORY CHANNEL A
MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8
MAA9 MAA10 MAA11 MAA12 MAA13 MAA14
DQMA#0 DQMA#1 DQMA#2 DQMA#3 DQMA#4 DQMA#5 DQMA#6 DQMA#7
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7 RASA# CASA#
WEA# CSA0# CSA1#
CKEA
CLKA0
CLKA0#
CLKA1
CLKA1#
MVREFD MVREFS
DIMA_0 DIMA_1
M22,24,26P :Not connected
E22 B22 B23 B24 C23 C22 F22 F21 C21 A24 C24 A25 E21 B20 C19
J25 F29 E25 A27 F15 C15 C11 E11
J27 F30 F24 B27 E16 B16 B11 F10
A19 E18 E19 E20 F20 B19
B21 C20
C18 A18
B7 B8
D30 B13
B
MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13
DQMA#0 DQMA#1 DQMA#2 DQMA#3 DQMA#4 DQMA#5 DQMA#6 DQMA#7
QSA0 QSA1 QSA2 QSA3 QSA4 QSA5 QSA6 QSA7
CSA#1
ATI_MVREFD
ATI_MVREFS
DIMA_0 DIMA_1
TP115 TP116
TPAD30 TPAD30
RASA# 52 CASA# 52 WEA# 52 CSA#0 52 CSA#1 52 CKEA 52
CLKA0 52 CLKA#0 52
CLKA1 52 CLKA#1 52
12
R698 100R2
DQMA#[7..0] 52
QSA[7..0] 52
12
R691 100R2
MAA[13..0] 52
CKEA
CKEB
VGA_MEM_S0
12
12
12
C893 SCD1U16V
1 2
1 2
R690 100R2
VGA_MEM_S0
C892 SCD1U16V
As close to CHIP as possible
MDB[63..0]53
R687 10KR2
R688 10KR2
12
R693 100R2
C
MDB0 MDB1 MDB2 MDB3 MDB4 MDB5 MDB6 MDB7 MDB8 MDB9 MDB10 MDB11 MDB12 MDB13 MDB14 MDB15 MDB16 MDB17 MDB18 MDB19 MDB20 MDB21 MDB22 MDB23 MDB24 MDB25 MDB26 MDB27 MDB28 MDB29 MDB30 MDB31 MDB32 MDB33 MDB34 MDB35 MDB36 MDB37 MDB38 MDB39 MDB40 MDB41 MDB42 MDB43 MDB44 MDB45 MDB46 MDB47 MDB48 MDB49 MDB50 MDB51 MDB52 MDB53 MDB54 MDB55 MDB56 MDB57 MDB58 MDB59 MDB60 MDB61 MDB62 MDB63
AD6 AD5
AC2 AC3 AD3
AA2 AA6 AA5 AB6 AB5
AE5 AE4 AB2 AB3
AE1 AE2 AE3
U91C
D7
DQB0
F7
DQB1
E7
DQB2
G6
DQB3
G5
DQB4
F5
DQB5
E5
DQB6
C4
DQB7
B5
DQB8
C5
DQB9
A4
DQB10
B4
DQB11
C2
DQB12
D3
DQB13
D1
DQB14
D2
DQB15
G4
DQB16
H6
DQB17
H5
DQB18
J6
DQB19
K5
DQB20
K4
DQB21
L6
DQB22
L5
DQB23
G2
DQB24
F3
DQB25
H2
DQB26
E2
DQB27
F2
DQB28
J3
DQB29
F1
DQB30
H3
DQB31
U6
DQB32
U5
DQB33
U3
DQB34
V6
DQB35
W5
DQB36
W4
DQB37
Y6
DQB38
Y5
DQB39
U2
DQB40
V2
DQB41
V1
DQB42
V3
DQB43
W3
DQB44
Y2
DQB45
Y3
DQB46 DQB47 DQB48 DQB49 DQB50 DQB51 DQB52 DQB53 DQB54 DQB55 DQB56 DQB57 DQB58 DQB59 DQB60 DQB61 DQB62 DQB63
M26-P-1
Part 3 of 6
MEMORY INTERFACE B
MEMVMODE_0 MEMVMODE_1
MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8
MAB9 MAB10 MAB11 MAB12 MAB13 MAB14
DQMB#0 DQMB#1 DQMB#2 DQMB#3 DQMB#4 DQMB#5 DQMB#6 DQMB#7
QSB0 QSB1 QSB2 QSB3 QSB4 QSB5 QSB6
QSB7 RASB# CASB#
WEB# CSB0# CSB1#
CKEB CLKB0
CLKB0#
CLKB1
CLKB1#
DIMB_0 DIMB_1
ROMCS#
MEMTEST
N5 M1 M3 L3 L2 M2 M5 P6 N3 K2 K3 J2 P5 P3 P2
E6 B2 J5 G3 W6 W2 AC6 AD2
F6 B3 K6 G1 V5 W1 AC5 AD1
R2 T5 T6 R5 R6 R3 N1
N2 T2
T3
E3 AA3
AF5 C6
C7 C8
MEMORY CHANNEL B
When select M24 use 45ohm 1% When select M26 use 240ohm 1%
12
MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 MAB13
DQMB#0 DQMB#1 DQMB#2 DQMB#3 DQMB#4 DQMB#5 DQMB#6 DQMB#7
QSB0 QSB1 QSB2 QSB3 QSB4 QSB5 QSB6 QSB7
CSB#1
R694 240R2F
D
RASB# 53 CASB# 53 WEB# 53 CSB#0 53 CSB#1 53 CKEB 53 CLKB0 53
CLKB#0 53 CLKB1 53
CLKB#1 53
TP112 TP113
TPAD30 TPAD30
TP114 TPAD30
12
DY
DQMB#[7..0] 53
QSB[7..0] 53
R696 10KR2
MAB[13..0] 53
VGA_CORE_S0
U91F
P17
VDDC#P17
P18
VDDC#P18
P19
VDDC#P19
U12
VDDC#U12
U13
VDDC#U13
U14
VDDC#U14
U17
VDDC#U17
U18
VDDC#U18
U19
VDDC#U19
V19
VDDC#V19
V18
VDDC#V18
V17
VDDC#V17
V14
VDDC#V14
V13
VDDC#V13
V12
VDDC#V12
N18
VDDC#N18
N17
VDDC#N17
N14
VDDC#N14
W17
VDDC#W17
W18
VDDC#W18
W12
VDDC#W12
W13
VDDC#W13
W14
VDDC#W14
N13
VDDC#N13
N19
VDDC#N19
M19
VDDC#M19
M18
VDDC#M18
M12
VDDC#M12
N12
VDDC#N12
M13
VDDC#M13
M14
VDDC#M14
P12
VDDC#P12
P13
VDDC#P13
P14
VDDC#P14
M17
VDDC#M17
W19
VDDC#W19
1 2
R692 4K7R2
R695 DUMMY-R2
M26-P-1
R689 0R3-U
12
1D8V_S0
VGA_CORE_S0 VGA_CORE_VDDCI
M22,24,26P :Not connected
1 2
DY
1 2
12
R697 DUMMY-R2
When use M26P, pls remove this.
E
VSS#M16
Part 6 of 6
VSS#N16 VSS#N15 VSS#P15 VSS#P16 VSS#R18 VSS#R17 VSS#R16 VSS#R15 VSS#R14 VSS#R13 VSS#R12 VSS#T13 VSS#T14 VSS#T15
VSS#W15
VSS#V16 VSS#V15 VSS#U15 VSS#U16 VSS#T19 VSS#T18 VSS#T17 VSS#T16
CENTER ARRAY
VDDC1#W16
VDDC1#M15 VDDC1#R19
VDDC1#T12
C891 SC330P50V2KX
When use M22/24P
PIN C6 C7
1.8V =
2.5V =
M16 N16 N15 P15 P16 R18 R17 R16 R15 R14 R13 R12 T13 T14 T15 W15 V16 V15 U15 U16 T19 T18 T17 T16
W16 M15 R19 T12
PD PU PU PD
W24
U91E
U8
VSS#U4U4VSS#U8
VSS#W7W7VSS#W8
AC12
AC14
AC16
AC18
AB8
VSS#AB8
AB7
VSS#AB7
AB1
VSS#AB1
AD16
VSS#AC4
VSS#AC12
VSS#AC14
VSS#AC16
VSS#AD16
W8
VSS#Y4
AC4
Y4
L28
M27
M26
M24
M25
K28
AD18
AK2
AJ1
VSS#AJ1
VSS#AK2
VSS#AC18
VSS#AD18
M28
P28
N28
R25
PCIE_VSS#L28
PCIE_VSS#K28
PCIE_VSS#P28
PCIE_VSS#M27
PCIE_VSS#N28
PCIE_VSS#M26
PCIE_VSS#M24
PCIE_VSS#M25
PCIE_VSS#M28
T28
T24
V24
R27
V26
R28
U28
PCIE_VSS#T28
PCIE_VSS#T24
PCIE_VSS#V24
PCIE_VSS#R27
PCIE_VSS#R28
PCIE_VSS#U28
R23
R24
R26
PCIE_VSS#R25
PCIE_VSS#R23
PCIE_VSS#R24
PCIE_VSS#R26
W28
AA26
AA27
AA23
AA24
AA25
AA28
AB28
AE28
AD26
AD27
AC28
AD28
V27
V25
V28
Y28
AH29
AF28
MVDDQ=
1.8v/ 2.5v
PCIE_VSS#V26
PCIE_VSS#V27
PCIE_VSS#V25
PCIE_VSS#V28
PCIE_VSS#Y28
PCIE_VSS#W23
PCIE_VSS#W28
PCIE_VSS#AA26
PCIE_VSS#AA27
PCIE_VSS#AA23
PCIE_VSS#AA24
PCIE_VSS#AA25
PCIE_VSS#AA28
PCIE_VSS#AF28
PCIE_VSS#AB28
PCIE_VSS#AE28
PCIE_VSS#AD26
PCIE_VSS#AD27
PCIE_VSS#AC28
PCIE_VSS#AD28
PCIE_VSS#AH29
CORE GND
Part 5 of 6
1 1
VSS#A2A2VSS#A10
VSS#A16
VSS#A22
VSS#A29
VSS#C1C1VSS#C3C3VSS#C28
VSS#C30
VSS#D27
VSS#D24
VSS#D21
VSS#D18
VSS#D15
VSS#D12
VSS#D10
VSS#D6D6VSS#D4D4VSS#F27
A10
A16
A22
A29
C28
C30
D27
D24
D21
D18
D15
D12
D10
VSS#G9G9VSS#G12
VSS#G16
VSS#G18
VSS#G21
VSS#G24
VSS#H27
VSS#H23
VSS#H21
VSS#H18
VSS#H16
VSS#H14
VSS#H12
VSS#H9H9VSS#H8H8VSS#H4
F27
G12
G16
G18
G21
G24
H27
H23
H21
H18
H16
H14
H12
VSS#AD12
VSS#AG5
VSS#AG9
VSS#J24
VSS#J23
H4
J24
J23
VSS#AG11
R7
AG5
AG9
AD12
AG11
VSS#K8K8VSS#K7K7VSS#K1K1VSS#L4L4VSS#M8M8VSS#M7M7VSS#P4P4VSS#R7
VSS#R8R8VSS#T1
T1
VDDR1 MEMVMODE_0 MEMVMODE_1
1.8V
2.5V
2.8V
+VDDC_CT +VDDC_CT
+VDDC_CTGND
GND+VDDC_CT
<Variant Name>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
A3
Date: Sheet
ATI M26 MEM (3/3)
Bolsena
SA
of
51 58Tuesday, December 28, 2004
Page 52
5
Dummy when use UMA (WHOLE PAGE)
All dampings in this page must near the VRAM.
C901 SCD1U16V
C909 SC330P50V2KX
12
12
12
D D
12
C902 SCD1U16V
C910 SC330P50V2KX
12
C903 SCD1U16V
12
C918 SC330P50V2KX
12
C911 SCD1U16V
12
C912 SC330P50V2KX
12
12
C922 SCD1U16V
12
C914 SC330P50V2KX
12
C906 SCD1U16V
C913 SC330P50V2KX
M26 : VRAM IS 1.8V M24 : VRAM IS 2.5V
RASA#51 CASA#51
WEA#51 CSA#051 CSA#151
MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6
12 12
MAA7 MAA8 MAA9 MAA10 MAA11
MAA12 MAA13
CKEA51 VDDRA_CLK0+
VDDRA_CLK0+ VDDRA_CLK0-
R717
R700
1 2
1 2
60D4R3F
BC751_1
BC751_1
12
C923 SCD1U16V
60D4R3F
C C
CLKA051
CLKA#051
R718 0R3-U
0R3-U
R704
CLOSE TO MEM !!
B B
A A
U110A
M2
RAS#
L2
CAS#
L3
WE#
N2
CS#
M4
NC#M4
N5
A0
N6
A1
M6
A2
N7
A3
N8
A4
M9
A5
N9
A6
N10
A7
N11
A8/AP
M8
A9
L6
A10
M7
A11
L9
NC#L9
N4
BA0
M5
BA1
M10
NC#M10
N12
CKE
M11
CLK
M12
CLK#
F6
VSS_THERMAL
F7
VSS_THERMAL
F8
VSS_THERMAL
F9
VSS_THERMAL
G6
VSS_THERMAL
G7
VSS_THERMAL
G8
VSS_THERMAL
G9
VSS_THERMAL
H6
VSS_THERMAL
H7
VSS_THERMAL
H8
VSS_THERMAL
H9
VSS_THERMAL
J6
VSS_THERMAL
J7
VSS_THERMAL
J8
VSS_THERMAL
J9
VSS_THERMAL
M13
MCL/DSF
HY5DS573222F-U
NC#C4C4NC#C11
NC#H4H4NC#H11
C11
H11
Layout trace 20 mil
5
1 of 5
VDD VDD VDD VDD VDD VDD VDD VDD
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VREF
NC#L12
NC#L13
NC#M3
NC#N3
N3
M3
L12
L13
CLOSE TO MEM
12
12
C905 SC330P50V2KX
D7 D8 E4 E11 L4 L7 L8 L11
C3 C5 C7 C8 C10 C12 E3 E12 F4 F11 G4 G11 J4 J11 K4 K11
B4 B11 D4 D5 D6 D9 D10 D11 E6 E9 F5 F10 G5 G10 H5 H10 J5 J10 K5 K10
E5 E7 E8 E10 K6 K7 K8 K9 L5 L10
N13
VDDR_VREF1
4
C894 SCD1U16V
VGA_MEM_S0
12
12
C895 SCD1U16V
12
C897 SCD1U16V
4
VGA_MEM_S0
12
C907 SCD1U16V
12
C919 SC330P50V2KX
12
C915 SC22U10V6ZY-U
VGA_MEM_S0
12
12
C900 SCD01U16V2KX
C920 SC22U10V6ZY-U
12
R726 1KR3F
12
R710 1KR3F
C908 SCD01U16V2KX
MDA12 MDA11 MDA9 MDA10 MDA13 MDA8 MDA15 MDA14
MEMA_DM1
MEMA_DQS1
MDA21 MDA18 MDA17 MDA22 MDA19 MDA23 MDA16 MDA20
MEMA_DM2
MEMA_DQS2
MDA6 MDA2 MDA0 MDA7 MDA1 MDA4 MDA5 MDA3
MEMA_DM0
MEMA_DQS0
MDA26 MDA31 MDA30 MDA24 MDA27 MDA25 MDA29 MDA28
MEMA_DM3
MEMA_DQS3
3
MDA[63..0]51 MAA[13..0]51 DQMA#[7..0]51 QSA[7..0]51
2 of 5
U110B
B5
DQ3
C6
DQ1
B6
DQ2
B7
DQ0
D2
DQ6
D3
DQ5
C2
DQ4
E2
DQ7
B3
DM0
B2
DQS0
HY5DS573222F-U
3 of 5
U110C
K13
DQ8
G13
DQ12
G12
DQ13
J13
DQ10
F13
DQ14
K12
DQ9
F12
DQ15
J12
DQ11
H12
DM1
H13
DQS1
HY5DS573222F-U
4 of 5
U110D
G3
DQ18
K3
DQ23
J3
DQ20
F3
DQ16
J2
DQ21
G2
DQ19
F2
DQ17
K2
DQ22
H3
DM2
H2
DQS2
HY5DS573222F-U
U110E
5 of 5
D12
DQ26
D13
DQ25
E13
DQ24
C9
DQ30
B10
DQ28
B8
DQ31
C13
DQ27
B9
DQ29
B12
DM3
B13
DQS3
HY5DS573222F-U
DQMA#2 MEMA_DM2
QSA2 MEMA_DQS2
R494
12
15R2J R493
12
15R2J
1 2 1 2
DQMA#5MEMA_DM5
R580 15R2J
R583 15R2J
MDA45 MDA46 MDA43 MDA44 MDA42 MDA40 MDA47 MDA41
MEMA_DM5
MEMA_DQS5
MDA49 MDA53 MDA54 MDA50 MDA52 MDA48 MDA55 MDA51
MEMA_DM6 MEMA_DQS6
MDA37 MDA35 MDA34 MDA39 MDA33 MDA36 MDA38 MDA32
MEMA_DM4
MEMA_DQS4
MDA58 MDA63 MDA61 MDA56 MDA59 MDA57 MDA62 MDA60
MEMA_DM7 MEMA_DQS7
QSA5MEMA_DQS5
DQMA#3 MEMA_DM3
QSA3 MEMA_DQS3
R585 1 5R2J R579 0R2-0
3
12
12
U92B
B5 C6 B6 B7 D2 D3 C2 E2
B3 B2
U92C
K13 G13 G12
J13
F13
K12
F12
J12
H12 H13
U92D
G3
K3
J3
F3
J2
G2
F2 K2
H3 H2
D12 D13 E13
C9
B10
B8
C13
B9
B12 B13
1 2 1 2
C896 SCD1U16V
C925 SC330P50V2KX
2 of 5
DQ3 DQ1 DQ2 DQ0 DQ6 DQ5 DQ4 DQ7
DM0 DQS0
DQ8 DQ12 DQ13 DQ10 DQ14 DQ9 DQ15 DQ11
DM1 DQS1
DQ18 DQ23 DQ20 DQ16 DQ21 DQ19 DQ17 DQ22
DM2 DQS2
CLKA#151
HY5DS573222F-U
3 of 5
HY5DS573222F-U
4 of 5
HY5DS573222F-U
U92E
5 of 5
DQ26 DQ25 DQ24 DQ30 DQ28 DQ31 DQ27 DQ29
DM3 DQS3
HY5DS573222F-U
VGA_MEM_S0
12
C924 SCD1U16V
12
C921 SCD01U16V2KX
R707
CLKA151
0R3-U
R703
12
0R3-U
12
CLOSE TO MEM !!
MEMA_DM4 MEMA_DM6 MEMA_DM7
MEMA_DQS4 MEMA_DQS6 MEMA_DQS7
QSA1 MEMA_DQS1
1 2
DQMA#1 MEMA_DM1
1 2
DQMA#0 MEMA_DM0
1 2
QSA0 MEMA_DQS0
1 2
2
RASA# CASA# WEA# CSA#0 CSA#1
MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11
MAA12 MAA13
CKEA51
VDDRA_CLK1+
VDDRA_CLK1-
R713
R721
60D4R3F
60D4R3F
1 2
1 2
BC752_1
12
C904 SCD1U16V
R584 15R2J
R582 15R2J
R581 15R2J
R586 15R2J
2
R487
12
15R2J
R488
12
15R2J
R480
12
15R2J R495
12
15R2J
R492
12
15R2J
R490
12
15R2J
M10
M11 M12
M13
N10 N11
N12
1
NC#L12
NC#L13
L12
L13
1 of 5
D7
VDD
D8
VDD
E4
VDD
E11
VDD
L4
VDD
L7
VDD
L8
VDD
L11
VDD
C3
VDDQ
C5
VDDQ
C7
VDDQ
C8
VDDQ
C10
VDDQ
C12
VDDQ
E3
VDDQ
E12
VDDQ
F4
VDDQ
F11
VDDQ
G4
VDDQ
G11
VDDQ
J4
VDDQ
J11
VDDQ
K4
VDDQ
K11
VDDQ
B4
VSSQ
B11
VSSQ
D4
VSSQ
D5
VSSQ
D6
VSSQ
D9
VSSQ
D10
VSSQ
D11
VSSQ
E6
VSSQ
E9
VSSQ
F5
VSSQ
F10
VSSQ
G5
VSSQ
G10
VSSQ
H5
VSSQ
H10
VSSQ
J5
VSSQ
J10
VSSQ
K5
VSSQ
K10
VSSQ
E5
VSS
E7
VSS
E8
VSS
E10
VSS
K6
VSS
K7
VSS
K8
VSS
K9
VSS
L5
VSS
L10
VSS
N13
VREF
NC#M3
NC#N3
N3
M3
12
VDDR_VREF2
U92A
M2
RAS#
L2
CAS#
L3
WE#
N2
CS#
M4
NC#M4
N5
A0
N6
A1
M6
A2
N7
A3
N8
A4
M9
A5
N9
A6 A7 A8/AP
M8
A9
L6
A10
M7
A11
L9
NC#L9
N4
BA0
M5
BA1 NC#M10
CKE CLK CLK#
F6
VSS_THERMAL
F7
VSS_THERMAL
F8
VSS_THERMAL
F9
VSS_THERMAL
G6
VSS_THERMAL
G7
VSS_THERMAL
G8
VSS_THERMAL
G9
VSS_THERMAL
H6
VSS_THERMAL
H7
VSS_THERMAL
H8
VSS_THERMAL
H9
VSS_THERMAL
J6
VSS_THERMAL
J7
VSS_THERMAL
J8
VSS_THERMAL
J9
VSS_THERMAL MCL/DSF
HY5DS573222F-U
NC#C4C4NC#C11
NC#H4H4NC#H11
C11
H11
12
DQMA#4 DQMA#6 DQMA#7
QSA4 QSA6 QSA7
<Variant Name>
Title
ATI VRAM (1/2)
Size Document Number Rev
A3
Date: Sheet of
Bolsena
Layout trace 20 mil
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
1
VGA_MEM_S0
12
C916
SC22U10V6ZY-U
C898 SCD1U16V
C899 SCD1U16V
52 58Tuesday, December 28, 2004
12
C917
SC22U10V6ZY-U
VGA_MEM_S0
12
12
R715 1KR3F
R709 1KR3F
SA
Page 53
5
U
Dummy when use UMA (WHOLE PAGE)
All dampings in this page must near the VRAM.
12
D D
12
C936 SCD1U16V
C938 SC330P50V2KX
12
C947 SCD1U16V
12
C951 SC330P50V2KX
12
12
C930 SCD1U16V
C949 SC330P50V2KX
12
C957 SCD1U16V
12
C944 SC330P50V2KX
12
12
C926 SCD1U16V
C952 SC330P50V2KX
12
C928 SCD1U16V
12
C933 SC330P50V2KX
M26 : VRAM IS 1.8V M24 : VRAM IS 2.5V
U114A
RASB#
M2
CASB# WEB# CSB#0 CSB#1
MAB0 MAB1 MAB2
12
MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11
MAB12
MAB13
CKEB
VDDRC_CLK0+ VDDRC_CLK0-
R732
R747
60D4R3F
60D4R3F
1 2
1 2
BC753_1
12
C946 SCD1U16V
5
C C
CLOSE TO MEM !!
R746 0R3-U
R740
12
0R3-U
CLKB051
CLKB#051
B B
A A
RAS#
L2
CAS#
L3
WE#
N2
CS#
M4
NC#M4
N5
A0
N6
A1
M6
A2
N7
A3
N8
A4
M9
A5
N9
A6
N10
A7
N11
A8/AP
M8
A9
L6
A10
M7
A11
L9
NC#L9
N4
BA0
M5
BA1
M10
NC#M10
N12
CKE
M11
CLK
M12
CLK#
F6
VSS_THERMAL
F7
VSS_THERMAL
F8
VSS_THERMAL
F9
VSS_THERMAL
G6
VSS_THERMAL
G7
VSS_THERMAL
G8
VSS_THERMAL
G9
VSS_THERMAL
H6
VSS_THERMAL
H7
VSS_THERMAL
H8
VSS_THERMAL
H9
VSS_THERMAL
J6
VSS_THERMAL
J7
VSS_THERMAL
J8
VSS_THERMAL
J9
VSS_THERMAL
M13
MCL/DSF
HY5DS573222F-U
NC#C4C4NC#C11
NC#H4H4NC#H11
C11
H11
1 of 5
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
VREF
NC#L12
NC#L13
NC#M3
NC#N3
N3
M3
L12
L13
CLOSE TO MEM
Layout trace 20 mil
VDD VDD VDD VDD VDD VDD VDD VDD
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
4
12
12
C929 SC330P50V2KX
D7 D8 E4 E11 L4 L7 L8 L11
C3 C5 C7 C8 C10 C12 E3 E12 F4 F11 G4 G11 J4 J11 K4 K11
B4 B11 D4 D5 D6 D9 D10 D11 E6 E9 F5 F10 G5 G10 H5 H10 J5 J10 K5 K10
E5 E7 E8 E10 K6 K7 K8 K9 L5 L10
N13
VDDR_VREF3
4
C932 SCD1U16V
VGA_MEM_S0
12
12
C939 SCD1U16V
12
C954 SCD1U16V
VGA_MEM_S0
12
C935 SCD1U16V
12
C955 SC330P50V2KX
12
C942 SC22U10V6ZY-U
VGA_MEM_S0
12
12
C943 SCD01U16V2KX
MEMB_DM0 MEMB_DQS0
C950 SC22U10V6ZY-U
MEMB_DM3 MEMB_DQS3
MEMB_DM1 MEMB_DQS1
MEMB_DM2 MEMB_DQS2
12
R745 1KR3F
12
R735 1KR3F
C956 SCD01U16V2KX
MDB7
B5
MDB6
C6
MDB5
B6
MDB4
B7
MDB1
D2
MDB0
D3
MDB2
C2
MDB3
E2
B3 B2
MDB28
K13
MDB29
G13
MDB31
G12
MDB25
J13
MDB26
F13
MDB27
K12
MDB24
F12
MDB30
J12
H12 H13
MDB14
G3
MDB9
K3
MDB11 MDB13 MDB10 MDB15
G2
MDB12 MDB8
K2
H3 H2
MDB20
D12
MDB23
D13
MDB22
E13
MDB16
C9
MDB19
B10
MDB17
B8
MDB21
C13
MDB18
B9
B12 B13
12
12
U114B
DQ3 DQ1 DQ2 DQ0 DQ6 DQ5 DQ4 DQ7
DM0 DQS0
HY5DS573222F-U
U114C
DQ8 DQ12 DQ13 DQ10 DQ14 DQ9 DQ15 DQ11
DM1 DQS1
U114D
DQ18 DQ23
J3
DQ20
F3
DQ16
J2
DQ21 DQ19
F2
DQ17 DQ22
DM2 DQS2
U114E
DQ26 DQ25 DQ24 DQ30 DQ28 DQ31 DQ27 DQ29
DM3 DQS3
HY5DS573222F-U
3
12
C941 SCD1U16V
12
C940 SC330P50V2KX
2 of 5
3 of 5
HY5DS573222F-U
4 of 5
HY5DS573222F-U
5 of 5
3
VGA_MEM_S0
C927 SCD1U16V
C948 SCD01U16V2KX
MDB32 MDB33 MDB34 MDB35 MDB36 MDB38 MDB37 MDB39
MEMB_DM4 MEMB_DQS4
MDB63 MDB59 MDB58 MDB60 MDB56 MDB62 MDB57 MDB61
MEMB_DM7 MEMB_DQS7
MDB43 MDB47 MDB45 MDB42 MDB44 MDB40 MDB41 MDB46
MEMB_DM5 MEMB_DQS5
MDB53 MDB54 MDB52 MDB51 MDB50 MDB49 MDB55 MDB48
MEMB_DM6 MEMB_DQS6
MEMB_DM0 DQMB#0 MEMB_DM3 MEMB_DM1 MEMB_DM2
MEMB_DQS0 MEMB_DQS3 MEMB_DQS1 MEMB_DQS2
G13 G12
K13
F13 K12 F12
H12 H13
D12 D13 E13
B10 C13
B12 B13
J13
J12
G3
G2
B5 C6 B6 B7 D2 D3 C2 E2
B3 B2
K3
J3
F3
J2
F2 K2
H3 H2
C9 B8
B9
U113B
U113C
U113D
MDB[63..0]51 MAB[13..0]51 DQMB#[7..0]51 QSB[7..0]51
2 of 5
DQ3 DQ1 DQ2 DQ0 DQ6 DQ5 DQ4 DQ7
DM0 DQS0
HY5DS573222F-U
DQ8 DQ12 DQ13 DQ10 DQ14 DQ9 DQ15 DQ11
DM1 DQS1
HY5DS573222F-U
DQ18 DQ23 DQ20 DQ16 DQ21 DQ19 DQ17 DQ22
DM2 DQS2
U113E
5 of 5
DQ26 DQ25 DQ24 DQ30 DQ28 DQ31 DQ27 DQ29
DM3 DQS3
HY5DS573222F-U
CLKB151
CLKB#151
3 of 5
4 of 5
HY5DS573222F-U
R500
12
15R2J
R502
12
15R2J
R448
12
15R2J
R497
12
15R2J R496
12
15R2J
R501
12
15R2J
R436
12
15R2J
R446
12
15R2J
DQMB#3 DQMB#1 DQMB#2
QSB0 QSB3 QSB1 QSB2
2
U113A
MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11
MAB12 MAB13
R742 60D4R3F
M2
RAS#
L2
CAS#
L3
WE#
N2
CS#
M4
NC#M4
N5
A0
N6
A1
M6
A2
N7
A3
N8
A4
M9
A5
N9
A6
N10
A7
N11
A8/AP
M8
A9
L6
A10
M7
A11
L9
NC#L9
N4
BA0
M5
BA1
M10
NC#M10
N12
CKE
M11
CLK
M12
CLK#
F6
VSS_THERMAL
F7
VSS_THERMAL
F8
VSS_THERMAL
F9
VSS_THERMAL
G6
VSS_THERMAL
G7
VSS_THERMAL
G8
VSS_THERMAL
G9
VSS_THERMAL
H6
VSS_THERMAL
H7
VSS_THERMAL
H8
VSS_THERMAL
H9
VSS_THERMAL
J6
VSS_THERMAL
J7
VSS_THERMAL
J8
VSS_THERMAL
J9
VSS_THERMAL
M13
MCL/DSF
HY5DS573222F-U
R440
12
15R2J
R398
12
15R2J
R438
12
15R2J
R441
12
15R2J R439
12
15R2J
R399
12
15R2J
R437
12
15R2J
R442
12
15R2J
<Variant Name>
Title
Size Document Number Rev
Date: Sheet
RASB#51 CASB#51
WEB#51 CSB#051 CSB#151
CKEB51
VDDRC_CLK1+
R750
12
0R3-U
VDDRC_CLK1-
R756
12
0R3-U
R728 60D4R3F
1 2
1 2
BC754_1
CLOSE TO MEM !!
12
C937 SCD1U16V
MEMB_DM4
MEMB_DM7
MEMB_DM5
MEMB_DM6
MEMB_DQS4 QSB4
MEMB_DQS7
MEMB_DQS5
MEMB_DQS6
2
1
1 of 5
D7
VDD
D8
VDD
E4
VDD
E11
VDD
L4
VDD
L7
VDD
NC#C4C4NC#C11
NC#H4H4NC#H11
C11
H11
VDD VDD
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VREF
NC#L12
NC#L13
NC#M3
NC#N3
N3
M3
L12
L13
CLOSE TO MEM
L8 L11
C3 C5 C7 C8 C10 C12 E3 E12 F4 F11 G4 G11 J4 J11 K4 K11
B4 B11 D4 D5 D6 D9 D10 D11 E6 E9 F5 F10 G5 G10 H5 H10 J5 J10 K5 K10
E5 E7 E8 E10 K6 K7 K8 K9 L5 L10
N13
VGA_MEM_S0
12
12
C945 SCD1U16V
VDDR_VREF4
12
C931 SCD1U16V
12
C934
C953
SC22U10V6ZY-
SC22U10V6ZY-U
VGA_MEM_S0
12
R739 1KR3F
12
R748 1KR3F
Layout trace 20 mil
DQMB#4 DQMB#7 DQMB#5 DQMB#6
QSB7 QSB5 QSB6
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
ATI VRAM (2/2)
A3
Bolsena
53 58Tuesday, December 28, 2004
1
SA
of
Page 54
5
4
3
2
1
M26 : VRAM IS 1.8V M24 : VRAM IS 2.5V
G114
VGA_MEM_S0 2D5V_S01D8V_S0
D D
C C
1 2
GAP-OPEN-PWR
G113
1 2
GAP-OPEN-PWR
G116
1 2
GAP-OPEN-PWR
G111
1 2
GAP-OPEN-PWR
G118
ONLY 1.8 'OR' 2.5 SHORT
G115
1 2
GAP-OPEN-PWR
G104
1 2
GAP-OPEN-PWR
G121
1 2
GAP-OPEN-PWR
G120
1 2
GAP-OPEN-PWR
G117
SRN0-1-U
ATI_TXBCLK+49 ATI_TXBCLK-49 ATI_TXBOUT2+49 ATI_TXBOUT2-49
ATI_TXBOUT1+49 ATI_TXBOUT1-49 ATI_TXBOUT0+49 ATI_TXBOUT0-49
ATI_TXACLK+49 ATI_TXACLK-49 ATI_TXAOUT2+49 ATI_TXAOUT2-49
ATI_TXAOUT1+49 ATI_TXAOUT1-49 ATI_TXAOUT0+49 ATI_TXAOUT0-49
ATI_LCDVDD_ON49
4 5 3 2 1
RN86 SRN0-1-U
4 5 3 2 1
RN90 SRN0-1-U
4 5 3 2 1
RN84 SRN0-1-U
4 5 3 2 1
RN89
1 2
R802 0R2-0
6 7 8
6 7 8
6 7 8
6 7 8
LCD_TXBCLK+ 13,17 LCD_TXBCLK- 13,17 LCD_TXBOUT2+ 13,17 LCD_TXBOUT2- 13,17
LCD_TXBOUT1+ 13,17 LCD_TXBOUT1- 13,17 LCD_TXBOUT0+ 13,17 LCD_TXBOUT0- 13,17
LCD_TXACLK+ 13,17 LCD_TXACLK- 13,17 LCD_TXAOUT2+ 13,17 LCD_TXAOUT2- 13,17
LCD_TXAOUT1+ 13,17 LCD_TXAOUT1- 13,17 LCD_TXAOUT0+ 13,17 LCD_TXAOUT0- 13,17
LCD_VDD_ON 13,17
Dummy when use UMA
1 2
GAP-OPEN-PWR
G103
1D2V_VGA_S0 1D2V_S0VGA_CORE_S0
B B
A A
GAP-OPEN-PWR
GAP-OPEN-PWR
5
G112
12
12
1 2
GAP-OPEN-PWR
G119
12
G102
GAP-OPEN-PWR
12
GAP-OPEN-PWR
3D3V_S0
VGA_LOCAL_DP49
VGA_LOCAL_DN49
RN48
DY
SRN0-2-U
RN124
SRN0-2-U
2 1
2 1
VGA_THERM_DP23 VGA_THERM_DN23
4
3 4
3 4
12
C232 SC2200P50V2KX
VGA_THERM_DP_1
VGA_THERM_DN_1
3
U63
1
VCC
2
DXP
3
DXN
4
THERM#
12
C331
G781
SCD1U
SMBCLK
SMBDATA
ALERT#
GND
8 7 6 5
VGA_SMB_CLK 13,15,49 VGA_SMB_DAT 13,49
1 2
3D3V_S0
R141 2K2R2
VGA_ALERT# 49
place near GPU
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
SA
of
54 58Tuesday, December 28, 2004
1
2
C725 SC470P50V2KX
31
Q37 S2N3904-U2
12
Dummy when use UMA
Title
VGA SELECTOR
Size Document Number Rev
A3
Bolsena
2
Date: Sheet
Page 55
A
B
C
D
E
DCBATOUT DCBATOUT_5234
FAN5234 FOR VGA_Core
4 4
5V_S5
12
C736 SC4D7U10V5ZY
5V_S0
R792 10KR2
R812 0R3-U
12
R815 DUMMY-R2
5234_VIN
12
C742 SCD01U16V2JX
5234_SS
5234_ILIM
5234_EN
12
R814 40K2R3F
3 3
1D2V_S0_EN39,44
DCBATOUT_5234
2 2
1 2
1 2
5234_VSEN
12
D51
2 1
SSM5818SL
U87
16 15
7 4 3
6 5 1
11
C741 SCD1U25V3KX
12
C737 SCD1U16V
5234_BOOT
9
PGND
FPWM BOOT SS ILIM EN
VSEN VOUT VIN VCC
PWM Mode: FPWM (High)=>Fixed PWM Mode. FPWM (Low)=>Hysteretic Mode.
AGND
ISNS
SW
HDRV
LDRV
PGOOD
FAN5234MTCX
8
12 13
14 10
2
5234_ISEN 5234_SW
5234_HDRV 5234_LDRV
G96
G88
1 2
GAP-OPEN-PWR
G95
1 2
GAP-OPEN-PWR
G94
1 2
GAP-OPEN-PWR
G97
1 2
GAP-OPEN-PWR
G105
1 2
GAP-OPEN-PWR
1 2
GAP-OPEN-PWR
C340
1 2
SCD1U25V3KX
1 2
TP119 TPAD30
R813 1K2R3F
DCBATOUT_5234
678
U85
DDD
AO4422
SSS
GD
123
4 5
1 2
678
DDD
U100
SSS
GD
AO4406
123
4 5
12
C733 SC10U35V0ZY-L
L34 IND-2D2UH-18
12
300KHz
C734 SCD1U
5V_S0
12
12
R794 10KR3
R793 DUMMY-R3
12
C735 SC10U35V0ZY-L
12
C739 SCD01U16V2JX
12
R811 698R3F
12
R810 2KR2F
VGA_CORE_S0
12
C740 SCD1U
KEMET B2 Size 220uF 2.5V ESR=35mohm Iripple=1.6A NTD:6.0
VGA_CORE_PWR VGA_CORE_S0
G146
1 2
GAP-OPEN-PWR
G148
1 2
GAP-OPEN-PWR
G147
1 2
GAP-OPEN-PWR
12
TC31 ST220U2D5VBM-1
DY
G86
1 2
GAP-OPEN-PWR
G87
1 2
GAP-OPEN-PWR
G92
1 2
GAP-OPEN-PWR
G91
1 2
GAP-OPEN-PWR
G108
1 2
GAP-OPEN-PWR
G93
1 2
GAP-OPEN-PWR
G107
1 2
GAP-OPEN-PWR
G98
1 2
GAP-OPEN-PWR
G145
1 2
GAP-OPEN-PWR
G136
1 2
GAP-OPEN-PWR
G144
1 2
GAP-OPEN-PWR
G143
1 2
GAP-OPEN-PWR
1D2V or 1D15V Iomax=10 or 5.2A OCP>20A
VGA_CORE_PWR
12
TC27 ST330U2D5VDM-3
KEMET V Size 330uF 2.5V ESR=9mohm, Ir i p p l e =3.7A NTD:9.0
Rilim=(11.2/Iilim)*((100+Rsense)/Rdson)
3D3V_S0
12
C778 SC10U10V5ZY
1 1
12
C777 SC10U10V5ZY
A
4
2
1
3
FB
BS
VIN
VOUT
NC#88NC#77GND6NC#55GND
VGA
APL5332KAC U35
9
1D5V_VGA_1_S0
12
R557 8K66R3F
DY
12
12
C779
SCD1U
R576 10KR3F
12
TC15 ST100U6D3VBM
B
G21
1 2
G22
GAP-OPEN-PWR
1 2
GAP-OPEN-PWR
1D5V_VGA_S0
C
Vo=1.20V, R811=0.698Kohm(R3F) =>Vo(cal.)=1.2141V for M26/M24
?M24/M26 PO WER P LAY ( GPIO_PWRCNTL) high (3.3V) = set lower core voltage (VDDC = 1.0V) low (0V) = set higher core voltage (VDDC = 1.2V)
<Variant Name>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
VGA CORE 1D2V or 1D0V
Size Document Number Rev
(Power Team)
D
A3
Date: Sheet
Bolsena
E
55 58Tuesday, December 28, 2004
SA
of
Page 56
5
A
4
HOLE2 HOLE
HOLE8 HOLE
3
HOLE5 HOLE
HOLE6 HOLE
HOLE13 HOLE
HOLE14 HOLE
2
HOLE12 HOLE
HOLE15 HOLE
HOLE17 HOLE
HOLE19 HOLE
1
1
D D
HOLE21 HOLE
1
5V_S0 5V_S0
14
10
9 8
7
U10C
TSAHCT125
1
HOLE22 HOLE
1
1
HOLE23 HOLE
1
14
13
12 11
7
1
HOLE24 HOLE
1
U10D
TSAHCT125
HOLE1 HOLE
HOLE4 HOLE
1
1
1
1
C C
3D3V_S5 3D3V_S5
HOLE27 HOLE
HOLE28 HOLE
HOLE7 HOLE
2 3
HOLE3 HOLE
DOCK_IN# DOCK_IN#
U117A
14
1
TSLCX125
7
HOLE9 HOLE
HOLE18 HOLE
12 11
HOLE11 HOLE
14
7
13
HOLE16 HOLE
U117D
TSLCX125
HOLE25 HOLE
DOCK_I N# 34,57
HOLE20 HOLE
1
HOLE29 HOLE
1
HOLE30 HOLE
3D3V_AUX_S5
13 12
1
1
147
1
HOLE10 HOLE
1
U46F
TSLCX14MTC-L-U
1
HOLE26 HOLE
1
B B
1
1
1
1
1
1
1
1
1
1
<Variant Name>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
A3
Bolsena
Date: Sheet
EMI
SA
of
56 58Tuesday, December 28, 2004
A
Page 57
A
EZ4
U93
A
VCC B GND3Y
NC7SZ08-U
125
91 61
92 62 93 63 94 64 95 65 96 66 97 67 98 68 99 69
100
70
101
71
102
72
103
73
104
74
105
75
106
76
107
77
108
78
109
79
110
80
111
81
112
82
113
83
114
84
115
85
116
86
117
87
118
88
119
89
120
90
124 126
FOX-CONN120-8R
3D3V_S5
5
4
?ez4 signal changed
4 4
3 3
2 2
1 1
12
R764 1KR2
DOCK_IN#
TMDS_EZ4_TX1-15,49 TMDS_EZ4_TX2-15,49
TMDS_EZ4_TX1+15,49 TMDS_EZ4_TX2+15,49
TMDS_EZ4_TX0-15,49 TMDS_EZ4_TX0+15,49
TMDS_EZ4_TXC+15,49
EZ4_DVI_DDC_C15
TMDS_EZ4_TXC-15,49
DOCK_MIC_JKIN#33 DOCK_LIN_R33 DOCK_LIN_L33
DOCK_EXT_MIC_IN33 SPKR_R_DOCK33 SPKR_L_DOCK33
EZ4_CRT_DDC_D16 EZ4_CRT_DDC_C16
CLK_PCIE_DOCK13 CLK_PCIE_DOCK1#3
1
G
DVI_EZ4_HPD15
EZ4_DVI_DDC_D15
DOCK_IN#34,56
EZ4_HS16 EZ4_VS16
PCIE_RXP012 PCIE_RXN012
P_SERIRQ18,26,34,37
PCIE_TXP012
PCIE_TXN012
PCIE_RXP112 PCIE_RXN112
3D3V_S5
12
2 3
SMBC_SB3,8,21
SMBD_SB3,8,21
R762 10KR2
D
Q46 2N7002
S
A
TV_COMP_DOCK TV_LUMA_DOCK TV_CRMA_DOCK
CRT_R_DOCK PSLCTIN# CRT_G_DOCK CRT_B_DOCK
EZ_PWROK
PE_REQ1#
TP118 TPAD30
AUD_AGND_EZ4
DOCK_IN
EZ_PWROK
12
R763 1MR2
1 2
B
1 31
2 32 3 33 4 34 5 35 6 36 7 37 8 38 9 39 10 40 11 41 12 42 13 43 14 44 15 45 16 46 17 47 18 48 19 49 20 50 21 51 22 52 23 53 24 54 25 55 26 56 27 57 28 58 29 59 30 60 121 122123
Function SYSTEM L DOCK H
DOCK_ON_1 30
B
D_TTGP0
D_TTGN0
TP121
D_RTGP1
TPAD30
D_TGP2
D_RTGN1
D_TGN2
D_TGP3 10M_LED# D_TGN3 PSTROB#
PAUTOFD# DOCK_JACK_IN PPD0
PERROR# PPD1 PINIT# PPD2
PPD3 PPD4 PPD5 PPD6 PPD7 PACK# PBUSY PPE PSLCT
SUSON MAINON
PCIRST_BUF# 15,18 ,26,28,29,31,34
DOCK_AD+
AUD_AGND_EZ4
LAN
R760
1 2
1MR2
Dummy when no EZ4
PPD[7..0] 58
D_TTGP0 30
ACT_LED# 29,30
D_TTGN0 30
D_RTGP1 30 D_TGP2 30 D_RTGN1 30 D_TGN2 30
D_TGP3 30 10M_LED# 29,30 D_TGN3 30
PSTROB# 58 PAUTOFD# 58
DOCK_JACK_IN 33
SPDIF 32,33
PERROR# 58
RI1#_5 37
DTR1_BOUT1_5 37
PINIT# 58
CTS1#_5 37
SOUT1_5 37
PSLCTIN# 58
RTS1#_5 37
SIN1_5 37 DSR1#_5 37 DCD1#_5 37
PS2_KDAT 34
PACK# 58
PS2_KCLK 34
PBUSY 58
PS2_MDAT 34
PPE 58
PS2_MCLK 34
PSLCT 58
PCIE_WAKE# 21
CLK_PCIE_DOCK2 3
PCIE_TXP1 12
CLK_PCIE_DOCK2# 3
PCIE_TXN1 12
5V_S0
12
R761 10KR2
DOCK_ON_2#
3
Q45
1
MMBT3904-U1
2
C
TV SWITCH
12
C977 SCD1U16V
RN112
DIS_COMP49 DIS_LUMA49 DIS_CRMA49
UMA_COMP13 UMA_LUMA13 UMA_CRMA13
1 2 3 4 5
SRN0-1-U
Dummy when use UMA
RN113
1 2 3 4 5
SRN0-1-U
Dummy when use Discrete
8 7 6
TV_COMP
8
TV_LUMA
7
TV_CRMA
6
1 2
TV_COMP
TV_LUMA
TV_CRMA
R791 0R2-0
DY
CRT SWITCH
12
C959 SCD1U16V
RN114
1
DIS_G49 DIS_B49 DIS_R49
UMA_G13 UMA_B13 UMA_R13
Dummy when use Discrete
CTS1#_5 SIN1_5 DSR1#_5 DCD1#_5
123
45
RC13
678
SRC100P50V-U
8
2
7
3
6
4 5
SRN0-1-U
Dummy when use UMA
RN115
1 2 3 4 5
SRN0-1-U
DOCK_ON_2# DOCK_CRT_ON#
RTS1#_5 RI1#_5 DTR1_BOUT1_5 SOUT1_5
123
45
RC14
678
SRC100P50V-U
Dummy when no EZ4
C
CRT_G_1 CRT_B_1 CRT_R_1
DY
CRT_G_1
8
CRT_B_1
7
CRT_R_1
6
1 2
D
5V_S0
NC7SB3157P6X-U
TV_COMP
TV_CRMA
DOCK_TV_ON#DOCK_ON_2#
TV_COMP TV_LUMA TV_CRMA
CRT_G_1 CRT_G_DOCK
CRT_B_1
CRT_R_1
R790 0R2-0
U96
4
B0
A
5
GND
VCC
6
B1
S
NC7SB3157P6X-U
U97
4
B0
A
5
GND
VCC
6
B1
S
NC7SB3157P6X-U
U98
4
B0
A
5
GND
VCC
6
B1
S
Dummy when no EZ4
1 2 3 4 5
RN117SRN0-1-U
Dummy when use EZ4
5V_S0
4 5 6
4 5 6
4 5 6
Dummy when no EZ4
CRT_G_1 CRT_B_1 CRT_R_1
3 2 1
3 2 1
3 2 1
8 7 6
NC7SB3157P6X-U
U95
A
GND
VCC S
NC7SB3157P6X-U
U94
A
GND
VCC S
NC7SB3157P6X-U
U99
A
GND
VCC S
RN116
1 2 3 4 5
TV_COMP_DOCK
TV_LUMA_DOCKTV_LUMA
TV_CRMA_DOCK
DY
3
B0
2 1
B1
3
B0
2 1
B1
3
B0
2 1
B1
SRN0-1-U
8 7 6
Dummy when use EZ4
3D3V_S5
14
PM_SLP_S5#21,34,44
<Variant Name>
Title
Size Document Number Rev A3
D
Date: Sheet
5 6
7
E
Function A to B0 A to B1
TV_COMP_SYS 16
TV_LUMA_SYS 16
TV_CRMA_SYS 16
Function
CRT
SYSTEM H
LDOCK
CRT_G_SYS 16
CRT_B_DOCK
CRT_B_SYS 16
CRT_R_DOCK
CRT_R_SYS 16
DY
3D3V_S5
PM_SLP_S3#18,21,34,38,39,43,44
DOCK_IN#
4
U117B
SUSON
TSLCX125
DOCK_IN#
14
10
9 8
7
Dummy when no EZ4
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
EASY PORT4 (1/2)
Bolsena SA
E
of
57 58Tuesday, December 28, 2004
S L H
TV
H L
U117C
MAINON
TSLCX125
Page 58
PRINT PORT
PPD[7..0]57
EZ4_PD[7..0]37
EZ4_PD1 EZ4_PD2 PPD2 EZ4_PD3 EZ4_PD4
PRNACK#_537
SLCT_537 BUSY_537 PE_537
STROB#_537
EZ4_PD5 EZ4_PD6
SLCTIN#_537
ERROR#_537
AUTOFD#_537
PRINIT#_537
EZ4_PD7
EZ4_PD0
?remove damping R?
RN80
1 2 3 4 5
1 2 3 4 5
1 2
1 2 3 4 5
1 2 3 4 5
SRN33 RN81
SRN33
RN82
SRN33 RN79
SRN33
R755 33R2
8 7 6
8 7 6
8 7 6
8 7 6
PPD1 PPD3
PPD4
PACK# PSLCT PBUSY PPE
PSTROB#
PPD5 PPD6 PPD7 PSLCTIN#
PERROR# PAUTOFD# PPD0 PINIT#
PACK# 57 PSLCT 57 PBUSY 57 PPE 57
PSTROB# 57
PSLCTIN# 57
PERROR# 57 PAUTOFD# 57
PINIT# 57
5V_S0
EZ4_PD1 ERROR#_5 EZ4_PD0 AUTOFD#_5
PE_5 SLCT_5 BUSY_5 PRNACK#_5
STROB#_5
RP10
1 2 3 4 5 6
SRP1K
RP11
1 2 3 4 5 6
SRP1K
1 2
Place near Dock1
D39
21
CH751H-40-U
R757 1KR2
PRN5V
10 9 8 7
10 9 8 7
1 2
1 2
PRINIT#_5 EZ4_PD2 SLCTIN#_5 EZ4_PD3
EZ4_PD4 EZ4_PD5 EZ4_PD6 EZ4_PD7
C998 SCD1U16V
C997 SCD1U16V
PPD1 PPD2 PPD3 PPD4 PACK# PSLCT PBUSY PPE
PSTROB# PPD5 PPD6 PPD7
PSLCTIN#
PERROR# PAUTOFD# PPD0 PINIT#
123
45
RC9
678
SRC100P50V-U
123
45
RC11
678
SRC100P50V-U
123
45
RC10
678
SRC100P50V-U
12
C958 SC100P50V2JN
123
45
RC12
678
SRC100P50V-U
Place near Dock1
For EMI
Dummy when no EZ4
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev A3
Date: Sheet
EASY PORT4 (2/2)
Bolsena
of
58 58Tuesday, December 28, 2004
SA
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