Acer Aspire 3010, Aspire 5010 Schematics

5

4

3

2

1

Xtal 14.318Mhz

SNIPE Block Diagram

300~400mA

CLK GEN

PCMCIA
SLOT

ICS 951412
IDT CV137

TPS2224AP

D D

C C

Support
TypeII

28

PCMCIA I/F

200Mhz

100/133Mhz

100Mhz

100/133Mhz

3

48Mhz for USB/ Cardbus

AVDDDI , AVDDQ 1.8V S0 ( CRT/TV)

28

CPU clk

NB clk

SB clk

VGA clk

AVDD 3.3 S0( CRT/TV)

TIPWR SW

PCI 7421

2* Slot Cardbus
1* 1394

1394
Conn

28

Mini-PCI

802.11a/b/g

B B

RJ45

31

TXFM

30

30

1000Mb

PCI LAN

Realtek
RTL8110SBL

TXFM

A A

10/100Mb

30

1000/100/10
RTL8100C
100/10

VLDT 1.2V S0

VTT 1.25V S3

Mem Ref 1.25V fr S3

VDDA 2.5V S0

VDD VCC_core S0

VDDIO 2.5V S3

Vcore 1.2V S0

VDD HT 1.2V S0

VDD 1.8V S0

VDD mem 2.5V S3

LVDS 1.8V S0

PLL 1.8V S0
Clock 3.3V S0

Xtal 32.768 Khz

PCIE 1.8V S0

VDDQ 3.3V S0

VDD 1.8V S0

3.3 S5, 1.8 S5

26,27

PCI Bus / 33MHz

29

AMD CPU

Sempron / Athlon K8

4,5,6,7

HyperTransport

6.4GB/S 16b/8b

ATI

AGTL+ CPU I/F + UMA

0.13um, 706 BGA package
31mmx 31mm

1.0~1.2V CMOS technology

RS480M

11,12,13,14

PCI-Express
x2

ATI

SB400

PCI

PIDE

HDD

ACPI 2.0

ATA 133

25

DVD/
CD-RW

18,19,20,21,22

SIDE

25

6xUSB 2.0

6-CH
AC97 2.2

LPC I/F

PCI Express x16

USB x 4

AC97

MODEM
MDC Card

NS SIO

PC87381

DDR 333/400

UMA

Discrete

ATI

0.11um, CSP/ BGA 708Pin
, 31mmx 31mm

1.0~1.3V CMOS technology

M26/M24

VRAM x4

HY5DS573222F

53,54

24

RJ11
CONN

LPC Bus / 33MHz

Thermal
& Fan

G791

37

FIR

TFDU6102

37

50,51,52

4Mx 32 bit x4= 64MB
8Mx 32 bit x4= 128MB
16Mx 32 bit x4= 256MB

29

23

VDD 2.5V S3

Vref DDR 1.25V S3

DDR x2

200-PIN DDR SODIMM

CODEC

ALC655

32

OP AMP

G1421

3324

KBC

KB3910

Touch
Pad

35 35

8,9,10

SVIDEO/COMP

LVDS

RGB CRT

TMDS

Line In
MIC In

Line Out

Int. SPKR

34

Int.
KB

33

33

33

XBUS

ISA ROM

TVOUT

LCD

CRT

DVI-D

PCB Layer Stackup

L1: Signal 1
L2: GND

16

L3: Signal 2
L4: Signal 3
L5: VCC
L6: Signal 4

17

Battery Charger

MAX1909ETI

16

15

INPUTS

AD+
BAT+

SYSTEM DC/DC

INPUT

DCBATOUT

OUTPUTS

DCBATOUT

MAX1999EEI

OUTPUT

5V_S5 ,
3D3V_S5

SYSTEM DC/DC

TPS 5130

INPUT

DCBATOUT 2D5V_S3

OUTPUT

1D8V_S5
1D2V_S0

CPU V_CORE

ISL6559CR

INPUT

DCBATOUT

OUTPUT

VCC_CORE_S0

SYSTEM POWER

LP2951ACM/APL5331KAC-TR

INPUT

2D5V_S3
DCBATOUT

36

OUTPUT

1D25V_S3
5V_AUX_S5

48

44

45,46

42,43

47

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

BLOCK DIAGRAM

BLOCK DIAGRAM

BLOCK DIAGRAM

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

SNIPE

SNIPE

SNIPE

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

156Monday, November 22, 2004

156Monday, November 22, 2004

156Monday, November 22, 2004

1

SA

SA

SA

of

5

4

3

2

1

SA to SB need to check

1. connect G781 Thermal Alert pin to VGA_GPIO14

2. ene KBC P165 LPCRST# , we suggest pull low avoid leakage

3. Clk to NB need to add Cap. when the trace change layer.

4. check page 9. what is the value of R481,R486, R498 and R499 is 100 ohm or 12 ohm.

5. check page 15, if on discrete mode does the 1D8V_S0 power for lvds should dummy or still contect on power plan.

D D

6. check page 19, can the 0 ohm resistance be dummied on P.19 right hand side?

7. check page 20, R203's voltage on pin 2.

8. page 21. check when the unused USB pin should be pull down or floating.

9. Can R471 change to common value?

10. check giga lan and 10/100 connect. Does them the same or can chose a cheaper one?

11. page 38. 12VGATE_S0 can decreased resistance.

12. Does the 1D5V_VGA_S0 can come from TPS5130?

Schematic change:
R659, change from 0R2 to 10Kr2

C C

B B

A A

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

CHANGE HISTORY

CHANGE HISTORY

CHANGE HISTORY

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

SNIPE SA

A3

SNIPE SA

A3

SNIPE SA

A3

of

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet

256Thursday, November 18, 2004

256Thursday, November 18, 2004

256Thursday, November 18, 2004

1

A

3D3V_S0

L8

1 2

0R3-UL80R3-U

4 4

3 3

SB_OSC_CLK21

CLK14_AUDIO32

12

12

C793

C793
SCD1U16V

SCD1U16V

C800

C800
SCD1U16V

SCD1U16V

12

12

C807

C807
SCD1U16V

SCD1U16V

C801

C801
SCD1U16V

SCD1U16V

12

C810

C810
SCD1U16V

SCD1U16V

12

C811

C811
SCD1U16V

SCD1U16V

CLK48_CARDBUS27

CLK48_USB21

SMBC_SB8,21

SMBD_SB8,21

R146 33R2R146 33R2

1 2

R147 33R2R147 33R2

1 2

12

C808

C808
SCD1U16V

SCD1U16V

12

C812

C812
SCD1U16V

SCD1U16V

C206 SC33P50V2JNC206 SC33P50V2JN

1 2

X3

X3

X-14D318MHZ-1-U1

X-14D318MHZ-1-U1

1 2

C227

C227

1 2

SC33P50V2JN

SC33P50V2JN

CLK14_NB13

CLK14_SIO37

B

12

C252

C252

SC22U10V6ZY-U

SC22U10V6ZY-U

3D3V_CLK_VDDA

3D3V_S0 3D3V_CLK_VDD

L22

L22

1 2

0R3-U

0R3-U

SC2D2U16V5ZY

SC2D2U16V5ZY

XI_CLK

XO_CLK

R152 22R2R152 22R2
R151 22R2R151 22R2
R158 0R2-0R158 0R2-0
R159 0R2-0R159 0R2-0

HTREF_CLK13

3D3VDD48_S0

12

C787

C787

12

R145

R145
DUMMY-R3

DUMMY-R3

DY

DY

1 2
1 2
1 2
1 2

R155 33R2R155 33R2

1 2

R162 33R2R162 33R2

1 2

R161 33R2R161 33R2

1 2

12

R170

R170
49D9R2F

49D9R2F

USB_48M
SMBC_CLK
SMBD_CLK

FS2
FS1
FS0

CLK_REF2

CLK_HTT66

IREF_CLKGEN

12

R182

R182

475R2F

475R2F

U28

U28

3

VDD_48

39

VDDA

32

VDD_SRC

21

VDD_SRC

14

VDD_SRC

35

VDD_SRC

56

VDD_REF

51

VDD_PC1

43

VDD_CPU

48

VDD_HTT

1

XIN

2

XOUT

4

USB_48

7

SCL

8

SDA

10

CLKREQ0#

11

CLKREQ1#

9

SEL24/24_48#

53

REF1

54

REF0

52

REF2

47

HTT66

50

PCI0

37

IREF

6

NC#6

IDTCV137PAG

IDTCV137PAG

C

SRCC0
SRCT0
SRCC3
SRCT3
SRCC4
SRCT4
SRCC5
SRCT5
SRCC6
SRCT6
SRCC7
SRCT7

CPUC1
CPUT1
CPUC0
CPUT0

SRCC1
SRCT1
SRCC2
SRCT2

VSS_SRC
VSS_SRC

RESET#

TURBO1

VSS_CPU

VSS_PCI

VSS_HTT

VSS_SRC

VSS_48

VSS_REF

VSSA

33
34
25
24
23
22
19
18
17
16
13
12

40
41
44
45

29
30
28
27

36
20
15
26

42
49
46
31
38
5
55

3D3V_CLK_VDDA3D3V_CLK_VDD

12

C253

C253
SCD1U16V

SCD1U16V

SRC_CLK0#
SRC_CLK0
SRC_CLK3#
SRC_CLK3

CPUCLKJ_CY
CPUCLK_CY

ATI_CLK0#
ATI_CLK0
ATI_CLK1#
ATI_CLK1

D

3D3V_S0

L24

L24

1 2

12

C794

C794

0R3-U

0R3-U

SC22U10V6ZY-U

SC22U10V6ZY-U

RN5 SRN33-2-U2RN5 SRN33-2-U2

2 3
1

1
2 3

4

4

CPUCLK# 6
CPUCLK 6

NBSRC_CLK# 13
NBSRC_CLK 13

GFX_CLK# 449
GFX_CLK 449

RN4 SRN33-2-U2RN4 SRN33-2-U2

R171 15R2JR171 15R2J

1 2

R172 15R2JR172 15R2J

1 2

RN7

RN7

2 3
1

4

SRN33-2-U2

1
2 3

VGA

VGA

SRN33-2-U2

4

SRN33-2-U2

SRN33-2-U2

RN6

RN6

Do not stuff when using UMA

SBLINK_CLK# 13
SBLINK_CLK 13

SBSRC_CLK# 18
SBSRC_CLK 18

SBLINK_CLK#

SBLINK_CLK

SBSRC_CLK#

SBSRC_CLK

GFX_CLK#

GFX_CLK

E

R192 49D9R2FR192 49D9R2F

1 2

R193 49D9R2FR193 49D9R2F

1 2

R190 49D9R2FR190 49D9R2F

1 2

R191 49D9R2FR191 49D9R2F

1 2

R198 49D9R2F

R198 49D9R2F

1 2

R189 49D9R2F

R189 49D9R2F

1 2

VGA

VGA

VGA

VGA

Do not stuff when using UMA

2 2

3D3V_CLK_VDD

1 1

DY

DY

R148 2K2R2

R148 2K2R2

1 2

R149

R149

1 2

DUMMY-R2

DUMMY-R2

DY

DY

R153 2K2R2

R153 2K2R2

DY

DY

1 2

R154

R154

1 2

DUMMY-R2

DUMMY-R2

DY

DY

R169 2K2R2

R169 2K2R2

1 2

R160

R160

1 2

DUMMY-R2

DUMMY-R2

DY

DY

FS0

FS1

DY

DY

A

FS2

B

VGA_CORE_S0

12

C804

C804
SCD1U16V

SCD1U16V

NBSRC_CLK#

NBSRC_CLK

CLKGEN_IDTCV137

CLKGEN_IDTCV137

CLKGEN_IDTCV137

C803

C803
SCD1U16V

SCD1U16V

12

C805

C805
SCD1U16V

SCD1U16V

12

C806

C806
SCD1U16V

SCD1U16V

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet

D

Date: Sheet

12

C

R199 49D9R2FR199 49D9R2F

1 2

R200 49D9R2FR200 49D9R2F

1 2

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

SNIPE

SNIPE

SNIPE

E

SA

SA

of

of

of

356Thursday, November 18, 2004

356Thursday, November 18, 2004

356Thursday, November 18, 2004

SA

A

1D2V_HT0A_S0

B

C

D

E

12

C81

C81
SCD22U16V3ZY

SCD22U16V3ZY

4 4

3 3

12

C67

C67
SCD22U16V3ZY

SCD22U16V3ZY

NB0CADOUT[15..0]11
NB0CADOUTJ[15..0]11

Used SideB Power Plane

2 2

1D2V_HT0A_S0

12

C82

C82
SCD22U16V3ZY

SCD22U16V3ZY

NB0HTTCLKOUT111
NB0HTTCLKOUTJ111
NB0HTTCLKOUT011
NB0HTTCLKOUTJ011

R384 49D9R3FR384 49D9R3F

1 2

R393 49D9R3FR393 49D9R3F

1 2

NB0HTTCTLOUT11
NB0HTTCTLOUTJ11

12

HTT for CPU sideA
Transmit power
and NB sideA Receive
power

1D2V_HT0A_S0

C83

C83
SCD22U16V3ZY

SCD22U16V3ZY

NB0CADOUT15
NB0CADOUTJ15
NB0CADOUT14
NB0CADOUTJ14
NB0CADOUT13
NB0CADOUTJ13
NB0CADOUT12
NB0CADOUTJ12
NB0CADOUT11
NB0CADOUTJ11
NB0CADOUT10
NB0CADOUTJ10
NB0CADOUT9
NB0CADOUTJ9
NB0CADOUT8
NB0CADOUTJ8
NB0CADOUT7
NB0CADOUTJ7
NB0CADOUT6
NB0CADOUTJ6
NB0CADOUT5
NB0CADOUTJ5
NB0CADOUT4
NB0CADOUTJ4
NB0CADOUT3
NB0CADOUTJ3
NB0CADOUT2
NB0CADOUTJ2
NB0CADOUT1
NB0CADOUTJ1
NB0CADOUT0
NB0CADOUTJ0

NB0HTTCLKOUT1
NB0HTTCLKOUTJ1
NB0HTTCLKOUT0
NB0HTTCLKOUTJ0

CPUHTTCTLIN1
CPUHTTCTLINJ1
NB0HTTCTLOUT
NB0HTTCTLOUTJ

D29
D27
D25
C28
C26
B29
B27

T25
R25
U27
U26
V25

U25
W27
W26

AA27
AA26
AB25
AA25
AC27
AC26
AD25
AC25

T27

T28

V29

U29

V27

V28

Y29
W29

AB29
AA29
AB27
AB28
AD29
AC29
AD27
AD28

Y25
W25

Y27

Y28

R27

R26

T29

R29

U13A

U13A

VLDT0_A
VLDT0_A
VLDT0_A
VLDT0_A
VLDT0_A
VLDT0_A
VLDT0_A

L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0

L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0

L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLIN_H0
L0_CTLIN_L0

VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B

L0_CADOUT_H15

L0_CADOUT_L15

L0_CADOUT_H14

L0_CADOUT_L14

L0_CADOUT_H13

L0_CADOUT_L13

L0_CADOUT_H12

L0_CADOUT_L12

L0_CADOUT_H11

L0_CADOUT_L11

L0_CADOUT_H10

L0_CADOUT_L10

L0_CADOUT_H9

L0_CADOUT_L9

L0_CADOUT_H8

L0_CADOUT_L8

L0_CADOUT_H7

L0_CADOUT_L7

L0_CADOUT_H6

L0_CADOUT_L6

L0_CADOUT_H5

L0_CADOUT_L5

L0_CADOUT_H4

L0_CADOUT_L4

L0_CADOUT_H3

L0_CADOUT_L3

L0_CADOUT_H2

L0_CADOUT_L2

L0_CADOUT_H1

L0_CADOUT_L1

L0_CADOUT_H0

L0_CADOUT_L0

L0_CLKOUT_H1

L0_CLKOUT_L1

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CTLOUT_H1

L0_CTLOUT_L1

L0_CTLOUT_H0

L0_CTLOUT_L0

AH29
AH27
AG28
AG26
AF29
AE28
AF25

N26
N27
L25
M25
L26
L27
J25
K25
G25
H25
G26
G27
E25
F25
E26
E27
N29
P29
M28
M27
L29
M29
K28
K27
H28
H27
G29
H29
F28
F27
E29
F29

J26
J27
J29
K29

N25
P25
P28
P27

1D2V_HT0B_S0

CPUCADOUT15
CPUCADOUTJ15
CPUCADOUT14
CPUCADOUTJ14
CPUCADOUT13
CPUCADOUTJ13
CPUCADOUT12
CPUCADOUTJ12
CPUCADOUT11
CPUCADOUTJ11
CPUCADOUT10
CPUCADOUTJ10
CPUCADOUT9
CPUCADOUTJ9
CPUCADOUT8
CPUCADOUTJ8
CPUCADOUT7
CPUCADOUTJ7
CPUCADOUT6
CPUCADOUTJ6
CPUCADOUT5
CPUCADOUTJ5
CPUCADOUT4
CPUCADOUTJ4
CPUCADOUT3
CPUCADOUTJ3
CPUCADOUT2
CPUCADOUTJ2
CPUCADOUT1
CPUCADOUTJ1
CPUCADOUT0
CPUCADOUTJ0

CPUHTTCLKOUT1
CPUHTTCLKOUTJ1
CPUHTTCLKOUT0
CPUHTTCLKOUTJ0

CPUHTTCTLOUT0
CPUHTTCTLOUTJ0

HTT for CPU sideB
Receive power
and NB sideA
Transmit power

12

C536

C536
SC4D7U10V5ZY

SC4D7U10V5ZY

Used SideA Power Plane

CPUHTTCLKOUT1 11
CPUHTTCLKOUTJ1 11
CPUHTTCLKOUT0 11
CPUHTTCLKOUTJ0 11

CPUHTTCTLOUT0 11
CPUHTTCTLOUTJ0 11

LAYOUT: Place bypass cap on topside of board near
HTT power pins that are not connected directly to
downstream HTT device, but connected internally to
other HTT power pins.

CPUCADOUT[15..0] 11
CPUCADOUTJ[15..0] 11

62.10030.041

62.10030.041

BGA754-SKT-U

By ME requset U11 P/N:

1 1

Main 62.10030.041
Second 62.10053.191
Third 62.10053.201

A

B

C

BGA754-SKT-U

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet of

Date: Sheet of

D

Date: Sheet

CPU(1/4)_HyperTransport I/F

CPU(1/4)_HyperTransport I/F

CPU(1/4)_HyperTransport I/F

SNIPE

SNIPE

SNIPE

E

of

456Thursday, November 18, 2004

456Thursday, November 18, 2004

456Thursday, November 18, 2004

SA

SA

SA

A

B

C

D

E

U13B

TP75TP75

4 4

2D5V_S3

VREF_DDR_CLAW

R480 34D8R2FR480 34D8R2F

1 2

R479 34D8R2FR479 34D8R2F

1 2

DDRVTT_SENSE

MEMZN
MEMZP

AE13

AG12

D14
C14

VTT_SENSE

MEMVREF1

MEMZN
MEMZP

VREF_DDR_MEM

NOTE: Test with passive probes only.

M_DATA[63..0]9

2D5V_S3

3 3

NOTE: Install to bypass op-amp

12

12

R235

R235
100R3F

100R3F

R234

R234
100R3F

100R3F

12

C330

C330
SCD1U

SCD1U

12

VREF_DDR_MEM

C329

C329
SCD1U

SCD1U

12

C422

C422
SC1000P50V2KX

SC1000P50V2KX

LAYOUT: Locate close to DIMMs.

NOTE: Remove to bypass op-amp

2 2

VREF_DDR_CLAW

2D5V_S3

12

12

1 1

12

R500

R500
100R3

100R3

R506

R506
100R3

100R3

C671

C671
SCD1U

SCD1U

12

C682

C682
SCD1U

SCD1U

VREF_DDR_CLAW

LAYOUT: Locate close to CPU.

A

12

C693

C693
SC1000P50V2KX

SC1000P50V2KX

M_ADM[7..0]9

M_DQS[7..0]9

B

M_DATA63
M_DATA62
M_DATA61
M_DATA60
M_DATA59
M_DATA58
M_DATA57
M_DATA56
M_DATA55
M_DATA54
M_DATA53
M_DATA52
M_DATA51
M_DATA50
M_DATA49
M_DATA48
M_DATA47
M_DATA46
M_DATA45
M_DATA44
M_DATA43
M_DATA42
M_DATA41
M_DATA40
M_DATA39
M_DATA38
M_DATA37
M_DATA36
M_DATA35
M_DATA34
M_DATA33
M_DATA32
M_DATA31
M_DATA30
M_DATA29
M_DATA28
M_DATA27
M_DATA26
M_DATA25
M_DATA24
M_DATA23
M_DATA22
M_DATA21
M_DATA20
M_DATA19
M_DATA18
M_DATA17
M_DATA16
M_DATA15
M_DATA14
M_DATA13
M_DATA12
M_DATA11
M_DATA10
M_DATA9
M_DATA8
M_DATA7
M_DATA6
M_DATA5
M_DATA4
M_DATA3
M_DATA2
M_DATA1
M_DATA0

M_ADM8
M_ADM7
M_ADM6
M_ADM5
M_ADM4
M_ADM3
M_ADM2
M_ADM1
M_ADM0
M_DQS8
M_DQS7
M_DQS6
M_DQS5
M_DQS4
M_DQS3
M_DQS2
M_DQS1
M_DQS0

A16
B15
A12
B11
A17
A15
C13
A11
A10

C11

AC1
AC3

AC2
AD1
AE1
AE3

AG3

AJ4

AE2

AF1

AH3

AJ3
AJ5
AJ6

AJ7
AH9
AG5
AH5

AJ9

AJ10

AH11

AJ11

AH15

AJ15

AG11

AJ12
AJ14
AJ16

A13

AA1
AG1
AH7

AH13

A14

AB1

AJ2

AJ8

AJ13

B9
C7
A6

A9
A5
B5
C5
A4
E2
E1
A3
B3
E3

F1
G2
G1

L3

L1
G3

J2

L2
M1
W1
W3

W2

Y1

R1

A7

C2

H1

T1

A8

D1

J1

MEMDATA63
MEMDATA62
MEMDATA61
MEMDATA60
MEMDATA59
MEMDATA58
MEMDATA57
MEMDATA56
MEMDATA55
MEMDATA54
MEMDATA53
MEMDATA52
MEMDATA51
MEMDATA50
MEMDATA49
MEMDATA48
MEMDATA47
MEMDATA46
MEMDATA45
MEMDATA44
MEMDATA43
MEMDATA42
MEMDATA41
MEMDATA40
MEMDATA39
MEMDATA38
MEMDATA37
MEMDATA36
MEMDATA35
MEMDATA34
MEMDATA33
MEMDATA32
MEMDATA31
MEMDATA30
MEMDATA29
MEMDATA28
MEMDATA27
MEMDATA26
MEMDATA25
MEMDATA24
MEMDATA23
MEMDATA22
MEMDATA21
MEMDATA20
MEMDATA19
MEMDATA18
MEMDATA17
MEMDATA16
MEMDATA15
MEMDATA14
MEMDATA13
MEMDATA12
MEMDATA11
MEMDATA10
MEMDATA9
MEMDATA8
MEMDATA7
MEMDATA6
MEMDATA5
MEMDATA4
MEMDATA3
MEMDATA2
MEMDATA1
MEMDATA0

MEMDQS17
MEMDQS16
MEMDQS15
MEMDQS14
MEMDQS13
MEMDQS12
MEMDQS11
MEMDQS10
MEMDQS9
MEMDQS8
MEMDQS7
MEMDQS6
MEMDQS5
MEMDQS4
MEMDQS3
MEMDQS2
MEMDQS1
MEMDQS0

U13B

MEMRESET_L

MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4
MEMCLK_H3
MEMCLK_L3
MEMCLK_H2
MEMCLK_L2
MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0

MEMCS_L7
MEMCS_L6
MEMCS_L5
MEMCS_L4
MEMCS_L3
MEMCS_L2
MEMCS_L1
MEMCS_L0

MEMRASA_L
MEMCASA_L

MEMWEA_L

MEMBANKA1
MEMBANKA0

MEMADDA13
MEMADDA12
MEMADDA11
MEMADDA10

MEMADDA9
MEMADDA8
MEMADDA7
MEMADDA6
MEMADDA5
MEMADDA4
MEMADDA3
MEMADDA2
MEMADDA1
MEMADDA0

MEMRASB_L
MEMCASB_L

MEMWEB_L

MEMBANKB1
MEMBANKB0

MEMADDB13
MEMADDB12
MEMADDB11
MEMADDB10

MEMADDB9
MEMADDB8
MEMADDB7
MEMADDB6
MEMADDB5
MEMADDB4
MEMADDB3
MEMADDB2
MEMADDB1
MEMADDB0

MEMCHECK7
MEMCHECK6
MEMCHECK5
MEMCHECK4
MEMCHECK3
MEMCHECK2
MEMCHECK1
MEMCHECK0

C

VTT_A
VTT_A
VTT_A
VTT_A
VTT_B
VTT_B
VTT_B
VTT_B

MEMCKEA
MEMCKEB

NC_E13
NC_C12

NC_E14
NC_D12

D17
A18
B17
C17
AF16
AG16
AH16
AJ17

AG10

AE8
AE7

D10
C10
E12
E11
AF8
AG8
AF10
AE10
V3
V4
K5
K4
R5
P5
P3
P4

D8
C8
E8
E7
D6
E6
C4
E5

H5
D4
G5

K3
H3

E13
C12
E10
AE6
AF3
M5
AE5
AB5
AD3
Y5
AB4
Y3
V5
T5
T3
N5

H4
F5
F4

L5
J5

E14
D12
E9
AF6
AF4
M4
AD5
AC5
AD4
AA5
AB3
Y4
W5
U5
T4
M3

N3
N1
U3
V1
N2
P1
U1
U2

BGA754-SKT-U

BGA754-SKT-U

1D25V_S3

MEMRESET#

M_CKE#0
M_CKE#1

M_CLK7
M_CLK#7
M_CLK6
M_CLK#6
M_CLK5
M_CLK#5
M_CLK4
M_CLK#4

M_CLK1
M_CLK#1
M_CLK0
M_CLK#0

M_CS#7
M_CS#6
M_CS#5
M_CS#4
M_CS#3
M_CS#2
M_CS#1
M_CS#0

M_ARAS#
M_ACAS#
M_AWE#

M_ABS#1
M_ABS#0

RSVD_M_AA15
RSVD_M_AA14
M_AA13
M_AA12
M_AA11
M_AA10
M_AA9
M_AA8
M_AA7
M_AA6
M_AA5
M_AA4
M_AA3
M_AA2
M_AA1
M_AA0

M_BRAS#
M_BCAS#
M_BWE#

M_BBS#1
M_BBS#0

RSVD_M_BA15
RSVD_M_BA14
M_BA13
M_BA12
M_BA11
M_BA10
M_BA9
M_BA8
M_BA7
M_BA6
M_BA5
M_BA4
M_BA3
M_BA2
M_BA1
M_BA0

CB7
CB6
CB5
CB4
CB3
CB2
CB1
CB0

12

For REGISTED DIMM Only
UNBUFFER DIMM NC

12

C114

M_CKE#0 8,9
M_CKE#1 8,9

M_CLK7 8,9
M_CLK#7 8,9
M_CLK6 8,9
M_CLK#6 8,9
M_CLK5 8,9
M_CLK#5 8,9
M_CLK4 8,9
M_CLK#4 8,9

M_CS#3 8,9
M_CS#2 8,9
M_CS#1 8,9
M_CS#0 8,9

M_ARAS# 8,9
M_ACAS# 8,9
M_AWE# 8,9

M_ABS#1 8,9
M_ABS#0 8,9

M_BRAS# 8,9
M_BCAS# 8,9
M_BWE# 8,9

M_BBS#1 8,9
M_BBS#0 8,9

C114
SC1000P50V2KX

SC1000P50V2KX

M_CLK#1
M_CLK#0
M_CLK1
M_CLK0

M_AA[13..0] 8,9

M_BA[13..0] 8,9

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet of

Date: Sheet of

C653

C653
SCD1U

SCD1U

AMD suggested M_AA13
connect to DIMM pin123

AMD suggested M_BA13
connect to DIMM pin123

TP94TP94
TP16TP16
TP95TP95
TP19TP19
TP21TP21
TP22TP22
TP23TP23
TP24TP24

D

2D5V_S3

RN72

RN72

1

8

2

7

3

6

45

SRN10K-2

SRN10K-2

MEMZN
MEMZP
M_DQS8
M_ADM8

MEMRESET#
M_CS#7
M_CS#6
M_CS#5
M_CS#4
RSVD_M_AA15
RSVD_M_AA14
RSVD_M_BA15
RSVD_M_BA14

NOT SUPPORT ECC CHECK
AMD suggested remove
PULL-HI resistor.

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU(2/4)_DDR

CPU(2/4)_DDR

CPU(2/4)_DDR

SNIPE

SNIPE

SNIPE

556Thursday, November 18, 2004

556Thursday, November 18, 2004

556Thursday, November 18, 2004

E

TP69TP69
TP68TP68
TP18TP18
TP17TP17

TP84TP84
TP82TP82
TP81TP81
TP83TP83
TP87TP87
TP73TP73
TP70TP70
TP72TP72
TP71TP71

SA

SA

of

SA

A

B

C

2D5V_CPUA_S0

D

E

DY R360

DY

C520

C520
SC22P50V2JN-1

SC22P50V2JN-1

DY

DY

VDDA1
VDDA2

RESET_L
PWROK
LDTSTOP_L

L0_REF1
L0_REF0

COREFB_H
COREFB_L
CORE_SENSE

VDDIOFB_H
VDDIOFB_L
VDDIO_SENSE

CLKIN_H
CLKIN_L

NC_AJ23
NC_AH23

NC_AE24
NC_AF24

VTT_A
VTT_B

DBRDY

NC_C15

TMS
TCK
TRST_L
TDI

NC_C18

NC_A19

KEY1
KEY0

NC_AE23
NC_AF23
NC_AF22
NC_AF21

NC_C1
NC_J3
NC_R3
NC_AA2
NC_D3
NC_AG2
NC_B18
NC_AH1
NC_AE21
NC_C20
NC_AG4
NC_C6
NC_AG6
NC_AE9
NC_AG9

12

R360

R1

20KR3F

20KR3F

12

R361

R361
20KR3F

20KR3F

Vout = 1.25*(1+ R1/R2)

R2

THERMTRIP#

THERMDA
THERMDC

VID4
VID3
VID2
VID1
VID0

NC_AG18
NC_AH18
NC_AG17

NC_AJ18

A20

A26
A27

AG13
AF14
AG14
AF15
AE15

AG18
AH18
AG17
AJ18

VID4
VID3
VID2
VID1
VID0

NC_AG18
NC_AH18
NC_AG17
NC_AJ18

THERMTRIP_L

THERMDP 23
THERMDN 23

TP62TP62
TP63TP63

VID[4..0] 41

LAYOUT: Route FBCLKOUT_H/L

differentially impedance 80

12

R452

R452
80D6R3F-U

80D6R3F-U

R451

R451

1 2

DUMMY-R3

DUMMY-R3

DY

DY

2D5V_S3

2D5V_S0

12

THERMTRIP#

THERMTRIP#Level shift to SB400

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet of

Date: Sheet of

CPU(3/4)_Control & Debug

CPU(3/4)_Control & Debug

CPU(3/4)_Control & Debug

R427

R427
680R3

680R3

2

SNIPE

SNIPE

SNIPE

3D3V_S5

12

R392

R392
10KR2

10KR2

3

Q26

Q26
MMBT3904-U1

MMBT3904-U1

1

NS3

1 2

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU_THERMTRIP# 21,23

2D5V_S0

R414

R414
1KR3

1KR3

656Thursday, November 18, 2004

656Thursday, November 18, 2004

656Thursday, November 18, 2004

E

of

SA

SA

SA

FBCLKOUT_H

FBCLKOUT_L

DBREQ_L

NC_D20
NC_C21
NC_D18
NC_C19
NC_B19

TDO

NC_AF18

NC_D22
NC_C22

NC_B13

NC_B7
NC_C3
NC_K1
NC_R2

NC_AA3

NC_F3
NC_C23
NC_AG7

NC_AE22

NC_C24
NC_A25

NC_C9

FBCLKOUT

AH19
AJ19

FBCLKOUTJ

DBREQJ

AE19

NC_D20

D20

NC_C21

C21

NC_D18

D18

NC_C19

C19

NC_B19

B19

TDO

A22

AF18

Connect to VDDIO for AMD suggest.

D22
C22

B13
B7
C3
K1
R2
AA3
F3
C23
AG7
AE22
C24
A25
C9

D

12

2D5V_VDDA_VREF

12

C524

C524
SC1U10V3KX

SC1U10V3KX

U13C

U13C

AH25

AJ25

AF20

AE18

AJ27

AF27
AE26

A23
A24
B23

AE12
AF12
AE11

AJ21

AH21

AJ23

AH23

AE24
AF24

C16

AG15

AH17

C15

E20
E17
B21
A21

C18

A19

A28

AJ28

AE23
AF23
AF22
AF21

C1

J3

R3

AA2

D3

AG2

B18

AH1

AE21

C20

AG4

C6
AG6
AE9
AG9

BGA754-SKT-U

BGA754-SKT-U

2D5V_S0

3D3V_S0

12

LDT_RST#13,18
SB_CPUPWRGD18
LDT_STP#13,18

1 2

1 2

C525

C525
SC1U10V3KX

SC1U10V3KX

1D25V_S3

2D5V_S0

LDT_RST#
CLKIN
CLKIN#
CORE_SENSE
VDDIOFB
VDDIOFBJ
VDDIOSENSE
NC_AE24
NC_AF24

2D5V_VDDA_S0

2D5V_S0

4 4

2D5V_CPUA_S0

1 2

12

C544

C544
SC10U10V5ZY

SC10U10V5ZY

R385

R385

0R3-U

0R3-U

1 2

DY

DY

63.R0004.151

63.R0004.151

2D5V_CPUR_S0

R382

R382
0R3-U

0R3-U

12

1 2

TC9

TC9
ST100U4VBM-1

ST100U4VBM-1

AMD SUGGEST TO USE 2D5V_CPUA_S0

KEMET,NT:5.7, B2 size
ST100U4VBM-1 (80.10716.321)

3 3

Iripple=1.1A,ESR=70mohm

SANYO, NT$:6.1
Iripple=1.1A,ESR=70mohm

3.5/2.8/2.0

77.21071.031

HDT Connectors

2D5V_S0

2 2

1 1

12

C518

C518
SCD1U

SCD1U

DBREQJ

DY

DY

DBRDY
TCK
TMS
TDI
TRST_L
TDO

R359 680R3

2D5V_S3

CHANGE FROM 1KR3 TO 680R2 FOR AMD
CHECK LIST

R359 680R3

NC_AG17
NC_AJ18
NC_D18

NC_B19
NC_C19
NC_D20
NC_C21

678

123

DY

DY

1 2

DY

DY

RN70 SRN680-URN70 SRN680-U

1
2
3
4 5

RN3 SRN680-URN3 SRN680-U

1
2
3
4 5

A

4 5

8
7
6

8
7
6

RN66

RN66
SRN680-U

SRN680-U

AMD SUGGEST TO USE 100 ~ 300UH

Change
L270H

L19

L19
0R5J

0R5J

2D5V_VDDA_S0

12

DY

DY

LAYOUT: Route trace 50 mils wide and
500 to 750 mils long between these
caps.

12

C543 SC4D7U10V5ZY

C543 SC4D7U10V5ZY

78.47593.411

78.47593.411

12

R358

R358

R357

R357

680R3

680R3

680R3

680R3

DY

DY

1D2V_HT0A_S0

R389

R389

R388

R388

44D2R3F

44D2R3F

1 2
1 2

44D2R3F

44D2R3F

64.44R25.551

64.44R25.551

AMD suggest voltege
from 2D5V_S0 to 2D5V_S3

differentially impedance 100

Add HDT connector for
AMD suggested

2D5V_S0

12

C519

C519
SCD1U

SCD1U

DY

DY

CN5

CN5

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24
26

SMC-CONN26A-FP

SMC-CONN26A-FP

20.F0357.025

20.F0357.025

DY

DY

LAYOUT: Route VDDA trace approx.
50 mils wide (use 2x25 mil traces to
exit ball field) and 500 mils long.

12

C556

C556
SC3300P50V2KX

SC3300P50V2KX

12

C535

C535
SC1000P50V2KX

SC1000P50V2KX

2D5V_S3

R428 820R3R428 820R3

R415 820R3R415 820R3

LDT_RST#
SB_CPUPWRGD
LDT_STP#

12

C571

C571
SCD22U16V3ZY

SCD22U16V3ZY

12

1 2
1 2

1 2

R441 680R3R441 680R3

1 2

R440 680R3R440 680R3

1 2

R408 680R3R408 680R3

C534

C534
SC1000P50V2KX

SC1000P50V2KX

CPUCLK3

CPUCLK#3

Validation Test Points

LAYOUT: Place close to the CPU.

NC_C15
NC_AE23
NC_AF23
NC_AF22
NC_AF21

B

TP66TP66
TP51TP51
TP52TP52
TP53TP53
TP54TP54

Iomax=120mA

U51

U51

1

SHDN#

2

GND

3

IN

G913C-U

G913C-U

DY

DY

L0_REF1
L0_REF0

123

C

COREFB
COREFB#
CORE_SENSE

VDDIOFB
VDDIOFBJ
VDDIOSENSE

CLKIN

12

R431

R431
169R3F

169R3F

CLKIN#
NC_AJ23
NC_AH23
NC_AE24
NC_AF24

DBRDY

NC_C15

TMS
TCK
TRST_L
TDI

NC_AE23
NC_AF23
NC_AF22
NC_AF21

678

4 5

TP60TP60
TP58TP58
TP59TP59
TP56TP56
TP76TP76
TP77TP77
TP74TP74
TP55TP55
TP57TP57

COREFB41

COREFB#41

C584

C584
SC3900P50V3KX

SC3900P50V3KX

C581

C581
SC3900P50V3KX

SC3900P50V3KX

R89 680R3R89 680R3

1 2

1 2

R88 680R3R88 680R3

SET

OUT

RN67

RN67

SRN680-U

SRN680-U

DY

DY

5

4

NC_C18

NC_A19

U13E

U13E

Y17

VSS

K17

VSS

H17

VSS

F17

VSS

E18

VSS

AJ26

VSS

AE29

VSS

AC16

VSS

AA16

VSS

J16

VSS

G16

VSS

E16

VSS

AH14

4 4

3 3

2 2

1 1

AD15
AB15

K15
E15

D16
AE14
AC14
AA14

G14

AF17
AD13
AB13

Y13
K13
H13

F13
AH12
AC12
AA12

G12

B12
AD11
AB11

Y11

K11

H11

F11
AH10
AC10

W10

U10

R10

N10

G10

B10

AD9

AH8
AC8

AD7

AB7

AH6
AC6

AA6

AH4

AH2
AD2

AB2

C29
AH28

AF28

AC28

W28

R28

J14

L10
J10

Y9
V9
T9
P9

M9

K9
H9
F9

W8

U8
R8
N8
L8
J8

G8

B8

V7
T7
P7

M7

K7
H7
F7

U6
R6
N6
L6
J6

G6

B6

B4

Y2
V2
T2
P2

M2

K2
H2
F2

L28

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BGA754-SKT-U

BGA754-SKT-U

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A

VCC_CORE_S0 2D5V_S3

N20
L20
J20
AF19
AD19
AB19
Y19
K19
H19
F19
D19
AC18
AA18
G18
B16
AD17
AB17
H15
F15
G28
D28
B28
C27
AH26
AF26
AD26
Y26
T26
M26
H26
D26
B26
C25
B25
AJ24
AG24
AC24
AA24
W24
U24
R24
N24
J24
G24
E24
AG23
AD23
AB23
Y23
V23
T23
P23
K23
H23
F23
D23
AJ22
AH22
AG22
AC22
AA22
AG29
U22
R22
N22
L22
J22
G22
E22
B22
AG21
AD21
Y21
V21
T21
P21
M21
K21
H21
F21
D21
AJ20
AG20
AE20
AC20
AA20
W20
U20
R20
G20
J18
AE16
Y15
B14
J12
AA10
AB9
AA8
Y7
W6
AF2
D2
AG27
AG25
L24
M23
W22
AB21
AH20
B2

A

L7

AC15

H18
B20
E21
H22

J23
H24
F26

N7

L9
V10
G13
K14
Y14

AB14

G15

J15

AA15

H16
K16
Y16

AB16

G17

J17
AA17
AC17
AE17

F18
K18

Y18
AB18
AD18
AG19

E19

G19
AC19
AA19

J19
F20
H20
K20
M20
P20
T20
V20
Y20

AB20
AD20

G21

J21

L21
N21
R21
U21

W21
AA21
AC21

F22
K22
M22
P22
T22
V22

Y22
AB22
AD22

E23

G23

L23
N23
R23
U23

W23
AA23
AC23

B24
D24
F24
K24
M24
P24
T24
V24

Y24
AB24
AD24
AH24
AE25

K26

P26

V26

BGA754-SKT-U

BGA754-SKT-U

U13D

U13D

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

E4
G4
J4
L4
N4
U4
W4
AA4
AC4
AE4
D5
AF5
F6
H6
K6
M6
P6
T6
V6
Y6
AB6
AD6
D7
G7
J7
AA7
AC7
AF7
F8
H8
AB8
AD8
D9
G9
AC9
AF9
F10
AD10
D11
AF11
F12
AD12
D13
AF13
F14
AD14
F16
AD16
D15
R4

N28
U28
AA28
AE27
R7
U7
W7
K8
M8
P8
T8
V8
Y8
J9
N9
R9
U9
W9
AA9
H10
K10
M10
P10
T10
Y10
AB10
G11
J11
AA11
AC11
H12
K12
Y12
AB12
J13
AA13
AC13
H14
AB26
E28
J28

B

VCC_CORE_S0

B

VCC_CORE_S0

C107

C107

SCD22U16V3ZY

SCD22U16V3ZY

VCC_CORE_S0

C607

C607

SCD22U16V3ZY

SCD22U16V3ZY

1 2

DY

DY

0.22u x 4

2D5V_S3

12

1D25V_S3

12

0.22u x 2

C

LAYOUT: Place in uPGA socket cavity.

0.22u x 6

12

12

12

C100

C100

SCD22U16V3ZY

SCD22U16V3ZY

SCD22U16V3ZY

SCD22U16V3ZY

C109

C109

12

C101

C101

SCD22U16V3ZY

SCD22U16V3ZY

12

12

C106

C106

SCD22U16V3ZY

SCD22U16V3ZY

SCD22U16V3ZY

SCD22U16V3ZY

LAYOUT: Place on backside of processor.

C634

1 2

SCD22U16V3ZY

SCD22U16V3ZY

DY

DY

DY

DY

12

C177

C177

C164

C164

SCD22U16V3ZY

SCD22U16V3ZY

SCD22U16V3ZY

SCD22U16V3ZY

12

C618

C618

C105

C105

SCD22U16V3ZY

SCD22U16V3ZY

SCD22U16V3ZY

SCD22U16V3ZY

SCD22U16V3ZY

SCD22U16V3ZY

1 2

1 2

SCD22U16V3ZY

SCD22U16V3ZY

DY

DY

12

12

C176

C176
SCD22U16V3ZY

SCD22U16V3ZY

1D25V_S3

12

C175

C175
SCD22U16V3ZY

SCD22U16V3ZY

C104

C104
SC4D7U10V5ZY

SC4D7U10V5ZY

C600

C600

SC10U10V5ZY

SC10U10V5ZY

SC10U10V5ZY

SC10U10V5ZY

10u x 2

12

12

C174

C174
SCD22U16V3ZY

SCD22U16V3ZY

12

C609

C609
SC4D7U10V5ZY

SC4D7U10V5ZY

C635

C635

C731

C731
SCD22U16V3ZY

SCD22U16V3ZY

12

12

C636

C636

C608

C608

C634

4.7u x 2

C

D

10u x 4

C108

C108

2D5V_S3

12

12

C92

C92

SC10U10V5ZY

SC10U10V5ZY

12

C160

C160
SC10U10V5ZY

SC10U10V5ZY

C93

C93

SC10U10V5ZY

SC10U10V5ZY

12

C748

C748
SC4D7U10V5ZY

SC4D7U10V5ZY

SC10U10V5ZY

SC10U10V5ZY

C606

C606
SC4D7U10V5ZY

SC4D7U10V5ZY

C115

C115

C116

C116

SC10U10V5ZY

SC10U10V5ZY

12

C285

C285
SC4D7U10V5ZY

SC4D7U10V5ZY

12

12

12

12

10u x 1 4.7u x 6

D

12

C281

C281

C283

C283

SC4D7U10V5ZY

SC4D7U10V5ZY

SC4D7U10V5ZY

SC4D7U10V5ZY

E

12

C282

C282
SC4D7U10V5ZY

SC4D7U10V5ZY

78.47593.411

78.47593.411

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet of

Date: Sheet of

CPU(4/4)_Power

CPU(4/4)_Power

CPU(4/4)_Power

SNIPE

SNIPE

SNIPE

of

756Thursday, November 18, 2004

756Thursday, November 18, 2004

756Thursday, November 18, 2004

E

SA

SA

SA

A

M_AA0
M_AA1
M_AA2
M_AA3
M_AA4
M_AA6
M_AA5
M_AA7
M_AA8
M_AA9
M_AA10
M_AA11

TP111TP111
TP33TP33
TP110TP110

C304

C304
SCD1U

SCD1U

M_AA12

M_ABS#0
M_ABS#1

M_DATA_R_0
M_DATA_R_1
M_DATA_R_2
M_DATA_R_3
M_DATA_R_4
M_DATA_R_5
M_DATA_R_6
M_DATA_R_7
M_DATA_R_8
M_DATA_R_9
M_DATA_R_10
M_DATA_R_11
M_DATA_R_12
M_DATA_R_13
M_DATA_R_14
M_DATA_R_15
M_DATA_R_16
M_DATA_R_17
M_DATA_R_18
M_DATA_R_19
M_DATA_R_20
M_DATA_R_21
M_DATA_R_22
M_DATA_R_23
M_DATA_R_24
M_DATA_R_25
M_DATA_R_26
M_DATA_R_27
M_DATA_R_28
M_DATA_R_29
M_DATA_R_30
M_DATA_R_31
M_DATA_R_32
M_DATA_R_33
M_DATA_R_34
M_DATA_R_35
M_DATA_R_36
M_DATA_R_37
M_DATA_R_38
M_DATA_R_39
M_DATA_R_40
M_DATA_R_41
M_DATA_R_42
M_DATA_R_43
M_DATA_R_44
M_DATA_R_45
M_DATA_R_46
M_DATA_R_47
M_DATA_R_48
M_DATA_R_49
M_DATA_R_50
M_DATA_R_51
M_DATA_R_52
M_DATA_R_53
M_DATA_R_54
M_DATA_R_55
M_DATA_R_56
M_DATA_R_57
M_DATA_R_58
M_DATA_R_59
M_DATA_R_60
M_DATA_R_61
M_DATA_R_62
M_DATA_R_63

12

A

DM1_RESET#
DM1_A13
DM1_BA2

3D3V_S0

4 4

3 3

2 2

1 1

M_ARAS#5,9
M_ACAS#5,9
M_AWE#5,9

VREF_DDR_MEM VREF_DDR_MEM

Layout trace 20 mil Layout trace 20 mil

DM1

DM1

112

A0

111

A1

110

A2

109

A3

108

A4

107

A5

106

A6

105

A7

102

A8

101

A9

115

A10 / AP

100

A11

99

A12

117

BA0

116

BA1

5

DQ0

7

DQ1

13

DQ2

17

DQ3

6

DQ4

8

DQ5

14

DQ6

18

DQ7

19

DQ8

23

DQ9

29

DQ10

31

DQ11

20

DQ12

24

DQ13

30

DQ14

32

DQ15

41

DQ16

43

DQ17

49

DQ18

53

DQ19

42

DQ20

44

DQ21

50

DQ22

54

DQ23

55

DQ24

59

DQ25

65

DQ26

67

DQ27

56

DQ28

60

DQ29

66

DQ30

68

DQ31

127

DQ32

129

DQ33

135

DQ34

139

DQ35

128

DQ36

130

DQ37

136

DQ38

140

DQ39

141

DQ40

145

DQ41

151

DQ42

153

DQ43

142

DQ44

146

DQ45

152

DQ46

154

DQ47

163

DQ48

165

DQ49

171

DQ50

175

DQ51

164

DQ52

166

DQ53

172

DQ54

176

DQ55

177

DQ56

181

DQ57

187

DQ58

189

DQ59

178

DQ60

182

DQ61

188

DQ62

190

DQ63

71

CB0

73

CB1

79

CB2

83

CB3

72

CB4

74

CB5

80

CB6

84

CB7

85

NC

86

NC/(RESET#)

97

NC/A13

98

NC/BA2

123

NC

124

NC

200

NC

118

/RAS

120

/CAS

119

/WE

1

VREF

2

VREF

197

VDDSPD

199

VDDID

201

GND

DDR-SODIMM-N-U1

DDR-SODIMM-N-U1

/CS0
/CS1

CKE0
CKE1

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8

CK0

/CK0

CK1

/CK1

CK2

/CK2

SCL

SDA

SA0
SA1
SA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

NORMAL TYPE

VDD
VDD
VDD
VDD
VDD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

GND

B

TP41TP41
TP119TP119
TP40TP40

C381

C381
SCD1U

SCD1U

M_BA0
M_BA1
M_BA2
M_BA3
M_BA4
M_BA6
M_BA5
M_BA7
M_BA8
M_BA9
M_BA10
M_BA11
M_BA12

M_BBS#0
M_BBS#1

M_DATA_R_0
M_DATA_R_1
M_DATA_R_2
M_DATA_R_3
M_DATA_R_4
M_DATA_R_5
M_DATA_R_6
M_DATA_R_7
M_DATA_R_8
M_DATA_R_9
M_DATA_R_10
M_DATA_R_11
M_DATA_R_12
M_DATA_R_13
M_DATA_R_14
M_DATA_R_15
M_DATA_R_16
M_DATA_R_17
M_DATA_R_18
M_DATA_R_19
M_DATA_R_20
M_DATA_R_21
M_DATA_R_22
M_DATA_R_23
M_DATA_R_24
M_DATA_R_25
M_DATA_R_26
M_DATA_R_27
M_DATA_R_28
M_DATA_R_29
M_DATA_R_30
M_DATA_R_31
M_DATA_R_32
M_DATA_R_33
M_DATA_R_34
M_DATA_R_35
M_DATA_R_36
M_DATA_R_37
M_DATA_R_38
M_DATA_R_39
M_DATA_R_40
M_DATA_R_41
M_DATA_R_42
M_DATA_R_43
M_DATA_R_44
M_DATA_R_45
M_DATA_R_46
M_DATA_R_47
M_DATA_R_48
M_DATA_R_49
M_DATA_R_50
M_DATA_R_51
M_DATA_R_52
M_DATA_R_53
M_DATA_R_54
M_DATA_R_55
M_DATA_R_56
M_DATA_R_57
M_DATA_R_58
M_DATA_R_59
M_DATA_R_60
M_DATA_R_61
M_DATA_R_62
M_DATA_R_63

DM2_RESET#
DM2_A13
DM2_BA2

M_BA13M_AA13

M_BRAS#
M_BCAS#
M_BWE#

12

3D3V_S0

121
122

M_CKE#0

96
95

M_DQS_R0

11

M_DQS_R1

25

M_DQS_R2

47

M_DQS_R3

61

M_DQS_R4

133

M_DQS_R5 M_DQS_R5

147

M_DQS_R6

169

M_DQS_R7

183
77

M_ADM_R0

12

M_ADM_R1

26

M_ADM_R2

48

M_ADM_R3

62
134

M_ADM_R5 M_ADM_R5

148

M_ADM_R6

170

M_ADM_R7

184
78

35
37
160
158

DDR_CLK0

89

DDR_CLK#0

91

SMBC_SB

195

SMBD_SB

193

194
196
198

9
10
21
22
33
34
36
45
46
57
58
69
70
81
82
92
93
94
113
114
131
132
143
144
155
156
157
167
168
179
180
191
192

3
4
15
16
27
28
38
39
40
51
52
63
64
75
76
87
88
90
103
104
125
126
137
138
149
150
159
161
162
173
174
185
186

202

NOT SUPPORT ECC CHECK
AMD suggested pull-low

B

M_CS#0 5,9
M_CS#1 5,9

M_CKE#0 5,9 M_CKE#1 5,9

M_ADM#0
M_ADM#1
M_ADM#2
M_ADM#3
M_ADM#4
M_ADM#5
M_ADM#6
M_ADM#7

M_CLK5 5,9
M_CLK#5 5,9
M_CLK7 5,9
M_CLK#7 5,9

2D5V_S3

M_BRAS#5,9
M_BCAS#5,9
M_BWE#5,9

C

DM2

DM2

112

A0

111

A1

110

A2

109

A3

108

A4

107

A5

106

A6

105

A7

102

A8

101

A9

115

A10 / AP

100

A11

99

A12

117

BA0

116

BA1

5

DQ0

7

DQ1

13

DQ2

17

DQ3

6

DQ4

8

DQ5

14

DQ6

18

DQ7

19

DQ8

23

DQ9

29

DQ10

31

DQ11

20

DQ12

24

DQ13

30

DQ14

32

DQ15

41

DQ16

43

DQ17

49

DQ18

53

DQ19

42

DQ20

44

DQ21

50

DQ22

54

DQ23

55

DQ24

59

DQ25

65

DQ26

67

DQ27

56

DQ28

60

DQ29

66

DQ30

68

DQ31

127

DQ32

129

DQ33

135

DQ34

139

DQ35

128

DQ36

130

DQ37

136

DQ38

140

DQ39

141

DQ40

145

DQ41

151

DQ42

153

DQ43

142

DQ44

146

DQ45

152

DQ46

154

DQ47

163

DQ48

165

DQ49

171

DQ50

175

DQ51

164

DQ52

166

DQ53

172

DQ54

176

DQ55

177

DQ56

181

DQ57

187

DQ58

189

DQ59

178

DQ60

182

DQ61

188

DQ62

190

DQ63

71

CB0

73

CB1

79

CB2

83

CB3

72

CB4

74

CB5

80

CB6

84

CB7

85

NC

86

NC/(RESET#)

97

NC/A13

98

NC/BA2

123

NC

124

NC

200

NC

118

/RAS

120

/CAS

119

/WE

1

VREF

2

VREF

197

VDDSPD

199

VDDID

202

GND

DDR-SODIMM-R-U2

DDR-SODIMM-R-U2

C

/CS0
/CS1

CKE0
CKE1

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8

CK0

/CK0

CK1

/CK1

CK2

/CK2

SCL
SDA

SA0
SA1
SA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

REVERSE TYPE

VDD
VDD

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

GND

121
122

96
95

11
25
47
61
133
147
169
183
77

12
26
48
62
134
148
170
184
78

35
37
160
158
89
91

195
193

194
196
198

9
10
21
22
33
34
36
45
46
57
58
69
70
81
82
92
93
94
113
114
131
132
143
144
155
156
157
167
168
179
180
191
192

3
4
15
16
27
28
38
39
40
51
52
63
64
75
76
87
88
90
103
104
125
126
137
138
149
150
159
161
162
173
174
185
186

201

M_CS#2 5,9

M_CKE#1

M_DQS_R0
M_DQS_R1
M_DQS_R2
M_DQS_R3
M_DQS_R4

M_DQS_R6
M_DQS_R7

M_ADM_R0
M_ADM_R1
M_ADM_R2
M_ADM_R3
M_ADM_R4M_ADM_R4

M_ADM_R6
M_ADM_R7

DDR_CLK1
DDR_CLK#1

DM2_SA0

M_CS#3 5,9

M_ADM#0
M_ADM#1
M_ADM#2
M_ADM#3
M_ADM#4
M_ADM#5
M_ADM#6
M_ADM#7

M_CLK4 5,9
M_CLK#4 5,9
M_CLK6 5,9
M_CLK#6 5,9

SMBC_SB 3,21
SMBD_SB 3,21

2D5V_S3

1 2

By ME requset DM1 P/N:
Main 62.10017.191
Second 62.10017.381

By ME requset DM2 P/N:
Main 62.10017.201
Second 62.10017.371
Third 62.10017.701

D

M_ADM_R[7..0] 9

M_DATA_R_[63..0] 9

M_DQS_R[7..0] 9

M_AA[13..0] 5,9

M_ABS#[1..0] 5,9

M_BA[13..0] 5,9

M_BBS#[1..0] 5,9

R233

R233

3D3V_S0

4K7R3

4K7R3

RN41

DDR_CLK#1
DDR_CLK#0
DDR_CLK1
DDR_CLK0

8
7
6

RN41

SRN10K-2

SRN10K-2

DY

DY

2D5V_S3

1
2
3
45

E

AMD K8
ClawHummar

MD63

DDR SOCKET PLACEMENT

TOP VIEW PERSPECTIVE DRAWING

DM1

Pin 199

Pin 200 Pin 2

DM2(Reverse)

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet of

Date: Sheet of

D

Date: Sheet

DDR SO-DIMM SKT

DDR SO-DIMM SKT

DDR SO-DIMM SKT

SMA11

SNIPE

SNIPE

SNIPE

SMA10
SMA0

SMA14

SMA12

Pin 200

MD0

Pin 2

Pin 1

Pin 199

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Pin 1

856Thursday, November 18, 2004

856Thursday, November 18, 2004

856Thursday, November 18, 2004

E

SA

SA

of

SA

A

SERIES DAMPING PARALLEL TERMINATION

PLACE RNs CLOSE TO FIRST DM ( DM1 ), < 0.75"
STRICT EQUAL LENGTH LIMITATION WITH DQS,
CB PINS

RN21

M_DATA4

M_ADM0
M_DATA6
M_DATA7
M_DATA13
M_DATA12

4 4

M_ADM1

M_DATA1
M_DATA0
M_DQS0
M_DATA2
M_DATA3
M_DATA8
M_DATA9
M_DQS1

M_DATA15
M_DATA21
M_DATA20
M_ADM2
M_DATA23 M_DATA_R_23
M_DATA22
M_DATA25 M_DATA_R_25

3 3

M_DATA11
M_DATA10
M_DATA17
M_DATA16
M_DQS2 M_DQS_R2
M_DATA19 M_DATA_R_19
M_DATA18
M_DATA24

M_DATA29
M_DATA28

M_ADM3
M_DATA26
M_DATA27
M_DATA30 M_DATA_R_30
M_DATA31

2 2

RN21

1
2
3
4
5
6
7
8 9

SRN10J-3

SRN10J-3

RN34

RN34

1
2
3
4
5
6
7
8 9

SRN10J-3

SRN10J-3

RN20

RN20

1
2
3
4
5
6
7
8 9

SRN10J-3

SRN10J-3

RN33

RN33

1
2
3
4
5
6
7
8 9

SRN10J-3

SRN10J-3

RN19

RN19

1
2
3
4
5
6
7
8 9

SRN10J-3

SRN10J-3

16
15
14
13
12
11
10

16
15
14
13
12
11
10

16
15
14
13
12
11
10

16
15
14
13
12
11
10

16
15
14
13
12
11
10

M_DATA_R_4
M_DATA_R_5M_DATA5
M_ADM_R0
M_DATA_R_6
M_DATA_R_7
M_DATA_R_13
M_DATA_R_12
M_ADM_R1

M_DATA_R_1
M_DATA_R_0
M_DQS_R0
M_DATA_R_2
M_DATA_R_3
M_DATA_R_8
M_DATA_R_9
M_DQS_R1

M_DATA_R_14M_DATA14
M_DATA_R_15
M_DATA_R_21
M_DATA_R_20
M_ADM_R2

M_DATA_R_22

M_DATA_R_11
M_DATA_R_10
M_DATA_R_17
M_DATA_R_16

M_DATA_R_18
M_DATA_R_24

M_DATA_R_29
M_DATA_R_28
M_DQS_R3M_DQS3
M_ADM_R3
M_DATA_R_26
M_DATA_R_27

M_DATA_R_31

M_DATA34
M_DATA32
M_DQS4
M_DATA33
M_DATA36
M_DATA37
M_ADM4
M_DATA39

M_DATA35
M_DATA41
M_DATA40
M_DQS5
M_DATA42
M_DATA43
M_DATA49
M_DATA48

M_DATA38
M_DATA45
M_DATA44
M_ADM5
M_DATA47
M_DATA46
M_DATA53
M_DATA52

M_DQS6
M_DATA50
M_DATA51
M_DATA56
M_DATA57
M_DQS7
M_DATA58
M_DATA59

M_ADM6
M_DATA54
M_DATA55
M_DATA61
M_DATA60
M_ADM7
M_DATA62
M_DATA63

1
2
3
4
5
6
7
8 9

1
2
3
4
5
6
7
8 9

1
2
3
4
5
6
7
8 9

1
2
3
4
5
6
7
8 9

1
2
3
4
5
6
7
8 9

RN18

RN18

SRN10J-3

SRN10J-3

RN28

RN28

SRN10J-3

SRN10J-3

RN17

RN17

SRN10J-3

SRN10J-3

RN27

RN27

SRN10J-3

SRN10J-3

RN16

RN16

SRN10J-3

SRN10J-3

B

16
15
14
13
12
11
10

16
15
14
13
12
11
10

16
15
14
13
12
11
10

16
15
14
13
12
11
10

16
15
14
13
12
11
10

M_DATA_R_34
M_DATA_R_32
M_DQS_R4
M_DATA_R_33
M_DATA_R_36
M_DATA_R_37
M_ADM_R4
M_DATA_R_39

M_DATA_R_35
M_DATA_R_41
M_DATA_R_40
M_DQS_R5
M_DATA_R_42
M_DATA_R_43
M_DATA_R_49
M_DATA_R_48

M_DATA_R_38

M_DATA_R_45

M_DATA_R_44
M_ADM_R5
M_DATA_R_47
M_DATA_R_46
M_DATA_R_53
M_DATA_R_52

M_DQS_R6
M_DATA_R_50
M_DATA_R_51
M_DATA_R_56
M_DATA_R_57
M_DQS_R7
M_DATA_R_58
M_DATA_R_59

M_ADM_R6
M_DATA_R_54
M_DATA_R_55
M_DATA_R_61
M_DATA_R_60
M_ADM_R7
M_DATA_R_62
M_DATA_R_63

M_ADM_R1
M_DATA_R_13
M_DATA_R_12
M_DATA_R_6
M_DATA_R_7
M_ADM_R0
M_DATA_R_5
M_DATA_R_4

M_DATA_R_1
M_DATA_R_0
M_DQS_R0
M_DATA_R_2
M_DATA_R_3
M_DATA_R_8
M_DATA_R_9
M_DQS_R1

M_DATA_R_25
M_DATA_R_22
M_DATA_R_23
M_ADM_R2
M_DATA_R_20
M_DATA_R_21
M_DATA_R_14
M_DATA_R_15

M_DATA_R_11
M_DATA_R_10
M_DATA_R_16
M_DATA_R_17
M_DQS_R2
M_DATA_R_19
M_DATA_R_18
M_DATA_R_24

M_DATA_R_30
M_DATA_R_31
M_DATA_R_26
M_DATA_R_27
M_ADM_R3
M_DQS_R3
M_DATA_R_29
M_DATA_R_28

RN44

RN44

1
2
3
4
5
6
7
8 9

SRN68J-1

SRN68J-1
RN52

RN52

1
2
3
4
5
6
7
8 9

SRN68J-1

SRN68J-1
RN43

RN43

1
2
3
4
5
6
7
8 9

SRN68J-1

SRN68J-1
RN51

RN51

1
2
3
4
5
6
7
8 9

SRN68J-1

SRN68J-1
RN42

RN42

1
2
3
4
5
6
7
8 9

SRN68J-1

SRN68J-1

C

PULL HIGH STUBS < 0.8", PLACE RPs CLOSE TO SECOND DM ( DM2 )

1D25V_S3 1D25V_S3

16
15
14
13
12
11
10

16
15
14
13
12
11
10

16
15
14
13
12
11
10

16
15
14
13
12
11
10

16
15
14
13
12
11
10

RN38

RN38

1
2
3
4
5
6
7
8 9

SRN68J-1

SRN68J-1
RN48

RN48

1
2
3
4
5
6
7
8 9

SRN68J-1

SRN68J-1
RN37

RN37

1
2
3
4
5
6
7
8 9

SRN68J-1

SRN68J-1
RN47

RN47

1
2
3
4
5
6
7
8 9

SRN68J-1

SRN68J-1
RN36

RN36

1
2
3
4
5
6
7
8 9

SRN68J-1

SRN68J-1

NO EQUAL LENGTH LIMITATION

M_DATA_R_36

16

M_DATA_R_32

15

M_DATA_R_37

14

M_DATA_R_33

13

M_ADM_R4

12

M_DQS_R4

11

M_DATA_R_38

10

M_DATA_R_39

M_DATA_R_48

16

M_DATA_R_49

15

M_DATA_R_43

14

M_DATA_R_42

13

M_DQS_R5

12

M_DATA_R_41

11

M_DATA_R_40

10

M_DATA_R_34

M_DATA_R_35

16

M_DATA_R_46

15

M_DATA_R_47

14

M_ADM_R5

13

M_DATA_R_44

12

M_DATA_R_45

11

M_DATA_R_53

10

M_DATA_R_52

M_DATA_R_59

16

M_DATA_R_58

15

M_DQS_R7

14

M_DATA_R_57

13

M_DATA_R_56

12

M_DATA_R_51

11

M_DATA_R_50

10

M_DQS_R6

M_DATA_R_55

16

M_DATA_R_54

15

M_ADM_R6

14

M_DATA_R_60

13

M_DATA_R_61

12

M_ADM_R7

11

M_DATA_R_63

10

M_DATA_R_62

D

M_CKE#1
M_BA12

M_CKE#0
M_AA12

M_AA11
M_AA9
M_AA7
M_AA5
M_AA4
M_AA8
M_AA6
M_AA3

M_CS#3
M_BA13
M_CS#2
M_BRAS#
M_BBS#1
M_BCAS#
M_BA0
M_BA2

M_AA1
M_AA10
M_AA2
M_AA0
M_ABS#1
M_ARAS#
M_AWE#
M_ABS#0

M_BA7
M_BA3
M_BA6
M_BA9
M_BA10
M_BA1
M_BBS#0
M_BWE#

M_BA5
M_BA8
M_BA11
M_BA4

M_AA13
M_CS#0
M_CS#1
M_ACAS#

RN50

RN50

2
1 4

SRN47J

SRN47J
RN32

RN32

2
1 4

SRN47J

SRN47J

RN31

RN31

1
2
3
4
5
6
7
8 9

SRN47J-1-U

SRN47J-1-U
RN39

RN39

1
2
3
4
5
6
7
8 9

SRN47J-1-U

SRN47J-1-U
RN30

RN30

1
2
3
4
5
6
7
8 9

SRN47J-1-U

SRN47J-1-U
RN49

RN49

1
2
3
4
5
6
7
8 9

SRN47J-1-U

SRN47J-1-U

RN40

RN40

1
2
3
4 5

SRN47-1

SRN47-1

RN29

RN29

1
2
3
4 5

SRN47-1

SRN47-1

8
7
6

8
7
6

E

3

3

16
15
14
13
12
11
10

16
15
14
13
12
11
10

16
15
14
13
12
11
10

16
15
14
13
12
11
10

M_ADM_R[7..0] 8

M_ADM[7..0] 5

M_DATA[63..0] 5

M_DATA_R_[63..0] 8

M_DQS[7..0] 5

M_DQS_R[7..0] 8

M_AA[13..0] 5,8

M_ABS#[1..0] 5,8

M_BA[13..0] 5,8

M_BBS#[1..0] 5,8

M_AWE# 5,8
M_ACAS# 5,8
M_ARAS# 5,8

M_BWE# 5,8
M_BCAS# 5,8
M_BRAS# 5,8

M_CS#0 5,8
M_CS#1 5,8
M_CS#2 5,8
M_CS#3 5,8

M_CKE#05,8

M_CKE#15,8

05/10
Remove the damping resistor for AMD suggest.

1 1

M_CKE#0

M_CKE#1

R498

R498

1 2

121R3F

121R3F

R481

R481

1 2

121R3F

121R3F

R499

R499

1 2

121R3F

121R3F

R486

R486

1 2

121R3F

121R3F

A

B

M_CLK7
M_CLK#7

M_CLK6
M_CLK#6

M_CLK5
M_CLK#5

M_CLK4
M_CLK#4

C

M_CLK7 5,8
M_CLK#7 5,8

M_CLK6 5,8
M_CLK#6 5,8

M_CLK5 5,8
M_CLK#5 5,8

M_CLK4 5,8
M_CLK#4 5,8

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet of

D

Date: Sheet of

DDR DAMPING & TERMINATION

DDR DAMPING & TERMINATION

DDR DAMPING & TERMINATION

SNIPE

SNIPE

SNIPE

E

of

956Thursday, November 18, 2004

956Thursday, November 18, 2004

956Thursday, November 18, 2004

SA

SA

SA

Place it near CPU

A

B

C

D

E

4 4

2D5V_S3

1D25V_S3

3 3

1D25V_S3

2 2

12

12

2D5V_S3

12

12

C290

C290

SCD1U

SCD1U

C291

C291

SCD1U

SCD1U

C456

C456

SCD1U

SCD1U

C455

C455

SCD1U

SCD1U

DY

DY

DY

DY

DY

DY

DY

DY

12

12

12

12

12

C436

C436
SCD1U

SCD1U

C435

C435
SCD1U

SCD1U

C419

C419
SCD1U

SCD1U

C418

C418
SCD1U

SCD1U

12

12

12

C438

C438

SCD1U

SCD1U

C437

C437

SCD1U

SCD1U

C458

C458

SCD1U

SCD1U

C457

C457

SCD1U

SCD1U

LAYOUT:Place altemating caps to GND and 2D5_S3

12

12

12

12

C440

C440

SCD1U

SCD1U

C439

C439

SCD1U

SCD1U

C421

C421

SCD1U

SCD1U

C420

C420

SCD1U

SCD1U

12

12

C442

C442

C410

C410
SCD1U

SCD1U

SCD1U

SCD1U

12

12

DY

DY

DY

DY

DY

DY

DY

DY

C441

C441

C409

C409
SCD1U

SCD1U

SCD1U

SCD1U

12

12

C292

C292

C345

C345
SCD1U

SCD1U

SCD1U

SCD1U

12

12

C356

C356

C459

C459
SCD1U

SCD1U

SCD1U

SCD1U

12

12

12

12

C444

C444

SCD1U

SCD1U

C443

C443

SCD1U

SCD1U

C249

C249

SCD1U

SCD1U

C293

C293

SCD1U

SCD1U

12

12

C446

C446

C327

C327
SCD1U

SCD1U

SCD1U

SCD1U

12

DY

DY

DY

DY

DY

DY

DY

DY

12

C445

C445

C328

C328
SCD1U

SCD1U

SCD1U

SCD1U

12

12

12

C228

C228
SCD1U

SCD1U

C254

C254
SCD1U

SCD1U

12

C408

C408

SCD1U

SCD1U

C208

C208

SCD1U

SCD1U

12

12

12

12

C413

C413

SCD1U

SCD1U

C447

C447

SCD1U

SCD1U

C355

C355

SCD1U

SCD1U

C407

C407

SCD1U

SCD1U

12

12

12

12

12

C452

C452

SCD1U

SCD1U

C451

C451

SCD1U

SCD1U

C460

C460

SCD1U

SCD1U

C280

C280

SCD1U

SCD1U

12

C454

C454
SCD1U

SCD1U

12

DY

DY

C453

C453
SCD1U

SCD1U

DY

DY

12

C165

C165
SCD1U

SCD1U

12

DY

DY

C207

C207
SCD1U

SCD1U

DY

DY

1D25V_S3

12

DY

DY

C434

C434
SCD1U

SCD1U

12

12

12

C430

C430

C390

C390

SCD1U

SCD1U

SCD1U

SCD1U

DY

DY

DY

DY

DY

DY

12

12

C263

C263
SCD1U

SCD1U

C248

C248
SCD1U

SCD1U

DY

DY

12

C284

C284

C268

C268

SCD1U

SCD1U

SCD1U

SCD1U

DY

DY

DY

DY

12

12

DY

DY

DY

DY

12

12

DY

DY

DY

DY

C448

C448
SCD1U

SCD1U

C414

C414
SCD1U

SCD1U

C310

C310
SCD1U

SCD1U

C376

C376
SCD1U

SCD1U

12

12

12

C450

C450

SCD1U

SCD1U

C449

C449

SCD1U

SCD1U

C235

C235

SCD1U

SCD1U

C319

C319

SCD1U

SCD1U

12

12

12

C415

C415

SCD1U

SCD1U

C416

C416

SCD1U

SCD1U

C399

C399

SCD1U

SCD1U

C245

C245

SCD1U

SCD1U

12

C324

C324

C379

C379
SCD1U

SCD1U

SCD1U

SCD1U

12

12

DY

DY

DY

DY

DY

DY

DY

DY

C325

C325

C378

C378
SCD1U

SCD1U

SCD1U

SCD1U

12

12

C275

C275

C288

C288
SCD1U

SCD1U

SCD1U

SCD1U

12

12

C423

C423

C269

C269
SCD1U

SCD1U

SCD1U

SCD1U

12

12

LAYOUT:Place close to Power Pin of DDR socket.

LAYOUT:Place at end of the DIMMs

1D25V_S3

12

TC27

TC27
ST100U4VBM-U

ST100U4VBM-U

12

TC28

TC28
ST100U4VBM-1

ST100U4VBM-1

12

C872

C872

SC22U10V6ZY-U

SC22U10V6ZY-U

12

C880

C880

SC22U10V6ZY-U

SC22U10V6ZY-U

12

C925

C925

SC22U10V6ZY-U

SC22U10V6ZY-U

12

C917

C917

SC22U10V6ZY-U

SC22U10V6ZY-U

2D5V_S3 2D5V_S3

C301

C301

SCD22U16V3ZY

SCD22U16V3ZY

1 2

C323

C323

1 2

SCD22U16V3ZY

SCD22U16V3ZY

C380

C380

1 2

DY

DY

SCD22U16V3ZY

SCD22U16V3ZY

C377

C377

SCD22U16V3ZY

SCD22U16V3ZY

1 2

DY

DY

C412

C412

SCD22U16V3ZY

SCD22U16V3ZY

1 2

C302

C302

1 2

1 2

1 2

DY

DY

C411

C411

1 2

DY

DY

C417

C417

1 2

SCD22U16V3ZY

SCD22U16V3ZY

C303

C303
SCD22U16V3ZY

SCD22U16V3ZY

C326

C326
SCD22U16V3ZY

SCD22U16V3ZY

SCD22U16V3ZY

SCD22U16V3ZY

SCD22U16V3ZY

SCD22U16V3ZY

0.22u x 10

1 1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet of

Date: Sheet of

A

B

C

D

Date: Sheet

DDR DECOUPLING

DDR DECOUPLING

DDR DECOUPLING

SNIPE

SNIPE

SNIPE

E

SA

SA

of

10 56Thursday, November 18, 2004

10 56Thursday, November 18, 2004

10 56Thursday, November 18, 2004

SA

A

4 4

B

C

D

E

CLAW HAMMER TO NB NB TO CLAW HAMMER

CPUCADOUT[15..0]4
CPUCADOUTJ[15..0]4

3 3

1D2V_S0

12

SCD1U16V

SCD1U16V

2 2

AROUND NB

C111

C111

12

DY

DY

C715

C715
SCD1U16V

SCD1U16V

CPUHTTCLKOUT14
CPUHTTCLKOUTJ14

CPUHTTCLKOUT04
CPUHTTCLKOUTJ04

CPUHTTCTLOUT04
CPUHTTCTLOUTJ04

1D2V_HT0A_S0

R94 49D9R2FR94 49D9R2F

1 2

R87 49D9R2FR87 49D9R2F

1 2

CPUCADOUT15
CPUCADOUTJ15
CPUCADOUT14
CPUCADOUTJ14
CPUCADOUT13
CPUCADOUTJ13
CPUCADOUT12
CPUCADOUTJ12
CPUCADOUT11
CPUCADOUTJ11
CPUCADOUT10
CPUCADOUTJ10
CPUCADOUT9
CPUCADOUTJ9
CPUCADOUT8
CPUCADOUTJ8

CPUCADOUT7
CPUCADOUTJ7
CPUCADOUT6
CPUCADOUTJ6
CPUCADOUT5
CPUCADOUTJ5
CPUCADOUT4
CPUCADOUTJ4
CPUCADOUT3
CPUCADOUTJ3
CPUCADOUT2
CPUCADOUTJ2
CPUCADOUT1
CPUCADOUTJ1
CPUCADOUT0
CPUCADOUTJ0

CPUHTTCLKOUT1
CPUHTTCLKOUTJ1

CPUHTTCLKOUT0
CPUHTTCLKOUTJ0

CPUHTTCTLOUT0
CPUHTTCTLOUTJ0

HT_RXCALN
HT_RXCALP

W25

W24
AA25
AA24
AB26
AA26
AC25
AC24
AD26
AC26

W30

AB29
AA29
AC29
AC28

W26

W29

W28

T26
R26
U25
U24
V26
U26

R29
R28
T30
R30
T28
T29
V29
U29
Y30

Y28
Y29

Y26

P29
N29

D27
E27

U20A

U20A

HT_RXCAD15P
HT_RXCAD15N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD8P
HT_RXCAD8N

HT_RXCAD7P
HT_RXCAD7N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD0P
HT_RXCAD0N

HT_RXCLK1P
HT_RXCLK1N

HT_RXCLK0P
HT_RXCLK0N

HT_RXCTLP
HT_RXCTLN

HT_RXCALN
HT_RXCALP

RS480M-U

RS480M-U

NB0CADOUT15

PART 1OF6

PART 1OF6

HT_TXCAD15P
HT_TXCAD15N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD10P
HT_TXCAD10N

HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD8P
HT_TXCAD8N

HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD0P
HT_TXCAD0N

HT_TXCLK1P
HT_TXCLK1N

HT_TXCLK0P
HT_TXCLK0N

HT_TXCTLP

HT_TXCTLN

HT_TXCALP
HT_TXCALN

HYPER TRANSPORT CPU I/F

HYPER TRANSPORT CPU I/F

R24
R25
N26
P26
N24
N25
L26
M26
J26
K26
J24
J25
G26
H26
G24
G25

L30
M30
L28
L29
J29
K29
H30
H29
E29
E28
D30
E30
D28
D29
B29
C29

L24
L25

F29
G29

M29
M28

B28
A28

NB0CADOUTJ15
NB0CADOUT14
NB0CADOUTJ14
NB0CADOUT13
NB0CADOUTJ13
NB0CADOUT12
NB0CADOUTJ12
NB0CADOUT11
NB0CADOUTJ11
NB0CADOUT10
NB0CADOUTJ10
NB0CADOUT9
NB0CADOUTJ9
NB0CADOUT8
NB0CADOUTJ8

NB0CADOUT7
NB0CADOUTJ7
NB0CADOUT6
NB0CADOUTJ6
NB0CADOUT5
NB0CADOUTJ5
NB0CADOUT4
NB0CADOUTJ4
NB0CADOUT3
NB0CADOUTJ3
NB0CADOUT2
NB0CADOUTJ2
NB0CADOUT1
NB0CADOUTJ1
NB0CADOUT0
NB0CADOUTJ0

NB0HTTCLKOUT1
NB0HTTCLKOUTJ1

NB0HTTCLKOUT0
NB0HTTCLKOUTJ0

NB0HTTCTLOUT
NB0HTTCTLOUTJ

HT_TXCALP
HT_TXCALN

NB0HTTCLKOUT1 4
NB0HTTCLKOUTJ1 4

NB0HTTCLKOUT0 4
NB0HTTCLKOUTJ0 4

NB0HTTCTLOUT 4

R80 100R2FR80 100R2F

NB0HTTCTLOUTJ 4

1 2

NB0CADOUT[15..0] 4
NB0CADOUTJ[15..0] 4

1 1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet

A

B

C

D

Date: Sheet

NB-RS480M_HT

NB-RS480M_HT

NB-RS480M_HT

SNIPE

SNIPE

SNIPE

SA

SA

of

of

of

11 56Thursday, November 18, 2004

11 56Thursday, November 18, 2004

11 56Thursday, November 18, 2004

E

SA

A

4 4

3 3

2D5V_S3

12

12

R549

R549
1KR2F

1KR2F

MEM_VREF

R550

R550
1KR2F

1KR2F

Connect MEM_VREF to VDD_MEM/2
PA_RS480F1.PDF

SCD47U16V3ZY

1 2
1 2

1 2

L20

L20

1 2

0R5J-1

0R5J-1

SCD47U16V3ZY

SCD47U16V3ZY

SCD47U16V3ZY

C707

2 2

1D8V_S0

C707
C244

C244

R542 1KR2R542 1KR2

NB_MEM_VMODE

12

C784

C784
SC1U10V3KX

SC1U10V3KX

MEM_CAP1
MEM_CAP2

MEM_VREF

MPVDD_PLL

AF17
AK17
AH16

AF16

AJ22

AJ21
AH20
AH21
AK19
AH19

AJ17
AG16
AG17
AH17

AJ18

AG26

AJ29
AE21
AH24
AH12
AG13

AH8
AE8

AF25
AH30
AG20

AJ25
AH13

AF14

AG8

AG25
AH29

AF21
AK25

AJ12

AF13

AK7
AF9

AE17
AH18
AE18

AJ19

AF18

AK16

AJ16

AE28

AJ20

AK20

AJ15

AJ14

AJ7

AJ4

U20C

U20C

MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12
MEM_A13
MEM_A14

MEM_DM0
MEM_DM1
MEM_DM2
MEM_DM3
MEM_DM4
MEM_DM5
MEM_DM6
MEM_DM7

MEM_DQS0P
MEM_DQS1P
MEM_DQS2P
MEM_DQS3P
MEM_DQS4P
MEM_DQS5P
MEM_DQS6P
MEM_DQS7P

MEM_DQS0N
MEM_DQS1N
MEM_DQS2N
MEM_DQS3N
MEM_DQS4N
MEM_DQS5N
MEM_DQS6N
MEM_DQS7N

MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_CS#
MEM_CKE

MEM_CKP
MEM_CKN

MEM_CAP1
MEM_CAP2

MEM_VMODE

MEM_VREF

MPVDD
MPVSS

RS480M-U

RS480M-U

PART 3 OF 6

PART 3 OF 6

B

AF28

MEM_DQ0

AF27

MEM_DQ1

AG28

MEM_DQ2

AF26

MEM_DQ3

AE25

MEM_DQ4

AE24

MEM_DQ5

AF24

MEM_DQ6

AG23

MEM_DQ7

AE29

MEM_DQ8

AF29

MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15
MEM_DQ16
MEM_DQ17
MEM_DQ18
MEM_DQ19
MEM_DQ20
MEM_DQ21
MEM_DQ22
MEM_DQ23
MEM_DQ24
MEM_DQ25
MEM_DQ26
MEM_DQ27
MEM_DQ28
MEM_DQ29
MEM_DQ30
MEM_DQ31
MEM_DQ32
MEM_DQ33
MEM_DQ34
MEM_DQ35
MEM_DQ36
MEM_DQ37
MEM_DQ38
MEM_DQ39
MEM_DQ40
MEM_DQ41
MEM_DQ42
MEM_DQ43

MEM_A I/F

MEM_A I/F

MEM_DQ44
MEM_DQ45
MEM_DQ46
MEM_DQ47
MEM_DQ48
MEM_DQ49
MEM_DQ50
MEM_DQ51
MEM_DQ52
MEM_DQ53
MEM_DQ54
MEM_DQ55
MEM_DQ56
MEM_DQ57
MEM_DQ58
MEM_DQ59
MEM_DQ60
MEM_DQ61
MEM_DQ62
MEM_DQ63

MEM_COMPP
MEM_COMPN

AG30
AG29
AH28
AJ28
AH27
AJ27
AE23
AG22
AF23
AF22
AE20
AG19
AF20
AF19
AH26
AJ26
AK26
AH25
AJ24
AH23
AJ23
AH22
AK14
AH14
AK13
AJ13
AJ11
AH11
AJ10
AH10
AE15
AF15
AG14
AE14
AE12
AF12
AG11
AE11
AJ9
AH9
AJ8
AK8
AH7
AJ6
AH6
AJ5
AG10
AF11
AF10
AE9
AG7
AF8
AF7
AE7

AH5
AD30

LANE REVERSE

PCIE_RX0P_SB18
PCIE_RX0N_SB18

PCIE_RX1P_SB18
PCIE_RX1N_SB18

MEM_COMPP
MEM_COMPN

R559 60D4R2F

R559 60D4R2F

1 2

R115 60D4R2F

R115 60D4R2F

1 2

DO NOT SUPPORT SIDEPORT MEMORY
DUMMY IT

C

PEG_TXP[15..0]449

PEG_TXN[15..0]449

PEG_RXP[15..0]449

PEG_RXN[15..0]449

U20B

U20B

PEG_TXP15
PEG_TXN15
PEG_TXP14
PEG_TXN14
PEG_TXP13
PEG_TXN13
PEG_TXP12
PEG_TXN12
PEG_TXP11
PEG_TXN11
PEG_TXP10
PEG_TXN10
PEG_TXP9
PEG_TXN9
PEG_TXP8
PEG_TXN8
PEG_TXP7
PEG_TXN7
PEG_TXP6
PEG_TXN6
PEG_TXP5
PEG_TXN5
PEG_TXP4
PEG_TXN4
PEG_TXP3
PEG_TXN3
PEG_TXP2
PEG_TXN2
PEG_TXP1
PEG_TXN1
PEG_TXP0
PEG_TXN0

PCE_ISET

R181

R181

1 2

10KR2

10KR2

PCE_TXISET

R167

R167

1 2

10KR2

10KR2

2D5V_S3

DY

DY
DY

DY

D8

GFX_RX0P

D7

GFX_RX0N

D5

GFX_RX1P

D4

GFX_RX1N

E4

GFX_RX2P

F4

GFX_RX2N

G5

GFX_RX3P

G4

GFX_RX3N

H4

GFX_RX4P

J4

GFX_RX4N

H5

GFX_RX5P

H6

GFX_RX5N

G1

GFX_RX6P

G2

GFX_RX6N

K5

GFX_RX7P

K4

GFX_RX7N

L4

GFX_RX8P

M4

GFX_RX8N

N5

GFX_RX9P

N4

GFX_RX9N

P4

GFX_RX10P

R4

GFX_RX10N

P5

GFX_RX11P

P6

GFX_RX11N

P2

GFX_RX12P

R2

GFX_RX12N

T5

GFX_RX13P

T4

GFX_RX13N

U4

GFX_RX14P

V4

GFX_RX14N

W1

GFX_RX15P

W2

GFX_RX15N

AE1

GPP_RX0P/SB_RX2P

AE2

GPP_RX0N/SB_RX2N

AB2

GPP_RX1P/SB_RX3P

AC2

GPP_RX1N/SB_RX3N

AB5

GPP_RX2P

AB4

GPP_RX2N

Y4

GPP_RX3P

AA4

GPP_RX3N

AG1

SB_RX0P

AH1

SB_RX0N

AC5

SB_RX1P

AC6

SB_RX1N

AH3

PCE_ISET

AJ3

PCE_TXISET

RS480M-U

RS480M-U

DO NOT SUPPORT SIDEPORT MEMORY
DUMMY IT

PART 2 OF 6

PART 2 OF 6

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P

GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N

GPP_TX0P/SB_TX2P
GPP_TX0N/SB_TX2N

GPP_TX1P/SB_TX3P
GPP_TX1N/SB_TX3N

PCIE I/F TO VIDEO

PCIE I/F TO VIDEO

PCIE I/F TO SLOT

PCIE I/F TO SLOT

PCIE I/F TO SB

PCIE I/F TO SB

GPP_TX2P

GPP_TX2N

GPP_TX3P

GPP_TX3N

PCE_PCAL

PCE_NCAL

SB_TX0P
SB_TX0N

SB_TX1P
SB_TX1N

D

PEG_RXP15_NB PEG_RXP15

A7
B7

PEG_RXP14_NB

B6
B5

PEG_RXP13_NB

A5

PEG_RXN13_NB

A4

PEG_RXP12_NB

B3

PEG_RXN12_NB

B2

PEG_RXP11_NB

C1

PEG_RXN11_NB

D1

PEG_RXP10_NB

D2

PEG_RXN10_NB

E2

PEG_RXP9_NB

F2

PEG_RXN9_NB

F1

PEG_RXP8_NB

H2

PEG_RXN8_NB

J2

PEG_RXP7_NB

J1

PEG_RXN7_NB

K1

PEG_RXP6_NB

K2

PEG_RXN6_NB

L2

PEG_RXP5_NB

M2

PEG_RXN5_NB

M1

PEG_RXP4_NB

N1

PEG_RXN4_NB

N2

PEG_RXP3_NB

R1

PEG_RXN3_NB

T1

PEG_RXP2_NB

T2

PEG_RXN2_NB

U2

PEG_RXP1_NB

V2

PEG_RXN1_NB

V1

PEG_RXP0_NB

Y2

PEG_RXN0_NB

AA2

AD2
AD1

AA1
AB1

Y5
Y6

W5
W4

AF2
AG2

AC4
AD4

AH2
AJ2

Do not stuff when using M26

SB_TX0P

C798 SCD1U16VC798 SCD1U16V

1 2

SB_TX0N

C799

C799

1 2

SCD1U16V

SCD1U16V

SB_TX1P

C791 SCD1U16VC791 SCD1U16V

1 2

SB_TX1N

C797

C797

1 2

SCD1U16V

SCD1U16V

PCE_PCAL

R157 150R2R157 150R2

PCE_NCAL

1 2

R166 100R2R166 100R2

1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

C132

C132
SCD1U16V

SCD1U16V

C131

C131
SCD1U16V

SCD1U16V

C143

C143
SCD1U16V

SCD1U16V

C142

C142
SCD1U16V

SCD1U16V

C141

C141
SCD1U16V

SCD1U16V

C151

C151
SCD1U16V

SCD1U16V

C156

C156
SCD1U16V

SCD1U16V

C157

C157
SCD1U16V

SCD1U16V

C158

C158
SCD1U16V

SCD1U16V

C159

C159
SCD1U16V

SCD1U16V

C162

C162
SCD1U16V

SCD1U16V

C163

C163
SCD1U16V

SCD1U16V

C169

C169
SCD1U16V

SCD1U16V

C170

C170
SCD1U16V

SCD1U16V

C171

C171
SCD1U16V

SCD1U16V

C172

C172
SCD1U16V

SCD1U16V

C202

C202
SCD1U16V

SCD1U16V

C203

C203
SCD1U16V

SCD1U16V

C173

C173
SCD1U16V

SCD1U16V

C204

C204
SCD1U16V

SCD1U16V

C221

C221
SCD1U16V

SCD1U16V

C222

C222
SCD1U16V

SCD1U16V

C205

C205
SCD1U16V

SCD1U16V

C223

C223
SCD1U16V

SCD1U16V

C224

C224
SCD1U16V

SCD1U16V

C225

C225
SCD1U16V

SCD1U16V

C226

C226
SCD1U16V

SCD1U16V

C232

C232
SCD1U16V

SCD1U16V

C233

C233
SCD1U16V

SCD1U16V

C234

C234
SCD1U16V

SCD1U16V

C240

C240
SCD1U16V

SCD1U16V

C241

C241
SCD1U16V

SCD1U16V

PCIE_TX0P_SB 18
PCIE_TX0N_SB 18

PCIE_TX1P_SB 18
PCIE_TX1N_SB 18

1D2V_S0

PEG_RXN15PEG_RXN15_NB
PEG_RXP14
PEG_RXN14PEG_RXN14_NB
PEG_RXP13
PEG_RXN13
PEG_RXP12
PEG_RXN12
PEG_RXP11
PEG_RXN11
PEG_RXP10
PEG_RXN10
PEG_RXP9
PEG_RXN9
PEG_RXP8
PEG_RXN8
PEG_RXP7
PEG_RXN7
PEG_RXP6
PEG_RXN6
PEG_RXP5
PEG_RXN5
PEG_RXP4
PEG_RXN4
PEG_RXP3
PEG_RXN3
PEG_RXP2
PEG_RXN2
PEG_RXP1
PEG_RXN1
PEG_RXP0
PEG_RXN0

E

LANE REVERSE

When disable local frame buffer,
VDD_MEM connect to 2D5V_S3, MEM_VMODE
connect to GND, MEM_VREF connect to
2D5V_S3, MPVDD connected to 1D8V

1 1

DSG-215-RS480-04.PDF

A

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

NB-RS480M_MEM/PCIE_LINK I/F

NB-RS480M_MEM/PCIE_LINK I/F

NB-RS480M_MEM/PCIE_LINK I/F

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet of

Date: Sheet of

B

C

D

Date: Sheet

SNIPE

SNIPE

SNIPE

of

12 56Thursday, November 18, 2004

12 56Thursday, November 18, 2004

12 56Thursday, November 18, 2004

E

SA

SA

SA

A

Y

Y

1D8V_S0

R450

R450

1 2

0R3-U

0R3-U

4 4

Do not stuff when using M26

3 3

1D8V_S0

2 2

ALL_PWROK39

1 1

12

DY

DY

R98

R98

1 2

BLM11A121S

BLM11A121S

1D8V_S0

12

LDT_RST#6,18

LPC_RST#18,37

AVDDQ

12

C599

C599

C604

C604

SC10U10V5ZY

SC10U10V5ZY

SCD1U16V

SCD1U16V

1D8V_S0

12

R168

R168
4K7R2

4K7R2

NB_SUS_STAT#

LDT_RST#

R101

R101

1 2

BLM11A121S

BLM11A121S

HTPVDD

12

C113

C113

C705

C705

SC10U10V5ZY

SC10U10V5ZY

SCD1U16V

SCD1U16V

DY

DY

R124 0R2-0

R124 0R2-0

A

RS480_TV_CRMA54

RS480_TV_LUMA54

RS480_TV_COMP54

MAIN_CRT_R54
MAIN_CRT_G54

MAIN_CRT_B54

12

12

C118

C118
SCD1U16V

SCD1U16V

1 2

3D3V_S0

12

13

3D3V_S0

1

2

PLVDD

12

C122

C122
SC10U10V5ZY

SC10U10V5ZY

147

TSLCX08MTC-U

TSLCX08MTC-U

147

TSLCX08MTC-U

TSLCX08MTC-U

1 2

1D8V_S0

12

R464

R464

12

75R2F

75R2F

R468

R468

12

75R2F

75R2F

R467

R467
75R2F

75R2F

12

C127

C127

C123

C123

SCD1U16V

SCD1U16V

SCD1U16V

SCD1U16V

3D3V_S0

R514

R514

1 2

0R3-U

0R3-U

DO NOT SUPPORT SIDEPORT MEMORY
DO NOT SUPPORT SERIAL STRAP ROM
DUMMY IT

U19D

U19D

11

U19A

U19A

RS480_RST#_R RS480_RST#

3

R107

R107
33R2

33R2

D

D

AG_RST# 34,449

R106

R106
33R2

33R2

1 2

R70

R70

1 2

0R3-U

0R3-U

12

R477

R477

12

75R2F

75R2F

R478

R478

12

75R2F

75R2F

12

B

AVDD3D3V_S0

R86

R86

1 2

0R3-U

R476

R476
75R2F

75R2F

VGA_CLK_DDC_354
VGA_DAT_DDC_354

0R3-U

12

MAIN_JVGA_VS54
MAIN_JVGA_HS54

C89

C89
SC1U10V3ZY

SC1U10V3ZY

AVDDQ

12

12

C90

C90
SC1U10V3ZY

SC1U10V3ZY

1D8VAVDDD1_S0

C605

C605
SC1U10V3ZY

SC1U10V3ZY

R438 715R3FR438 715R3F
R502 0R2-0R502 0R2-0
R517 0R2-0R517 0R2-0

1 2
1 2
1 2

Do not stuff when using M26

NB_PWRGD39
LDT_STP#6,18
ALLOW_LDTSTOP18

3D3VDDR_S0

CLK14_NB3

C702

C702

SB_OSC_INT21

SC1U10V3ZY

SC1U10V3ZY

12

C121

C121
DUMMY-C3

DUMMY-C3

B

Use CLK GEN
REF 14.318M
CLK to SB
OSCIN
DUMMY IT

R528 3KR2F

R528 3KR2F
R497 3KR2F

R497 3KR2F
R496 3KR2FR496 3KR2F

LVDS_DIGON

RB751V-40-U

RB751V-40-U

NB_PWRGD

RB751V-40-U

RB751V-40-U

LVDS_BLON

1 2

R109 22R2

R109 22R2

12
12
12

DY

DY
DY

DY

BMREQ#18

12

D28

D28

DY

DY

D27

D27

DY

DY

1 2

DY

DY

TPAD28

TPAD28

TPAD28

TPAD28

VGA_SMB_CLK54,449
VGA_SMB_DAT54,449

TP99TP99
TP100TP100

12

TP9

TP9

TP96

TP96

R123

R123
1KR2

1KR2

4

5

3D3V_S0

IRSET_NB
VGA_CLK_DDC_NB
VGA_DAT_DDC_NB

RS480_RST#

NB_SUS_STAT#

NB_OSC_OUT

DFT_GPIO0
DFT_GPIO1
DFT_GPIO2

THERMAL_P_NB
THERMAL_N_NB

R105 0R2-0

R105 0R2-0

147

6

3D3V_S0

147

9

10

DY

DY

1 2

R122 0R2-0

R122 0R2-0

C

B27
C27
D26
D25
C24

B24

E24
D24

B25

A25

A24

C25

A26

B26

A11

B11
C26

E11

F11

A14

B14

M23

L23

D14

B15

B12
C12
AH4

H13
H12

A13

B13

B9

F12

E13
D13

F10
C10
C11
AF4
AE4

1 2

U19B

U19B

TSLCX08MTC-U

TSLCX08MTC-U

U19C

U19C

8

TSLCX08MTC-U

TSLCX08MTC-U

C

U20D

U20D

AVDD1
AVDD2
AVSSN1
AVSSN2
AVDDDI
AVSSDI

AVDDQ
AVSSQ

C
Y
COMP

RED
GREEN
BLUE

DAC_VSYNC
DAC_HSYNC
RSET
DAC_SCL
DAC_SDA

PLLVDD
PLLVSS

HTPVDD
HTPVSS

SYSRESET#
POWERGOOD
LDTSTOP#
ALLOW_LDTSTOP
SUS_STAT#

VDDR3_1
VDDR3_2

OSCIN
OSCOUT

TVCLKIN

DFT_GPIO0/RSV
DFT_GPIO1/RSV
DFT_GPIO2/RSV

BMREQb
I2C_CLK
I2C_DATA
THERMALDIODE_P
THERMALDIODE_N

RS480M-U

RS480M-U

DY

DY

PART 4 OF 6

PART 4 OF 6

CRT/TVOUT

CRT/TVOUT

PLL PWR

PLL PWR

PM

PM

CLOCKs

CLOCKs

DFT_GPIO3/RSV
DFT_GPIO4/RSV
DFT_GPIO5/RSV

MIS.

MIS.

LCDVDD_ON 54

BL_ON 34,449

RESISTOR

R503
R504

TXOUT_U0P

TXOUT_U0N

TXOUT_U1P

TXOUT_U1N

TXOUT_U2P

TXOUT_U2N

TXOUT_U3P

TXOUT_U3N

TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N

TXCLK_UP
TXCLK_UN

TXCLK_LP

LVDS

LVDS

TXCLK_LN

LPVDD

LPVSS

LVDDR18D
LVDDR18A_1
LVDDR18A_2

LVSSR1
LVSSR2
LVSSR3
LVSSR4
LVSSR5
LVSSR6
LVSSR7
LVSSR8

LVDS_DIGON

LVDS_BLON
LVDS_BLEN

GFX_CLKP

GFX_CLKN

HTTSTCLK

HTREFCLK

SB_CLKP
SB_CLKN

TMDS_HPD

STRP_DATA

DDC_DATA

TESTMODE

VCC_CORE_S0

DY

DY

D18
C18
B19
A19
D19
C19
D20
C20

B16
A16
D16
C16
B17
A17
E17
D17

B20
A20
B18
C17

E18
F17
E19
G20
H20

G19
E20
F20
H18
G18
F19
H19
F18

E14
F14
F13

B8
A8

P23
N23

E8
E7

C13
C14
C15

A10

E10

B10

E12

12

R503

R503
DUMMY-R2

DUMMY-R2

12

R504

R504
4K7R2

4K7R2

RS480M MODE

NORMAL MODE

D

TXBOUT3+
TXBOUT3-

TXAOUT3+
TXAOUT3-

LVDS_DIGON
LVDS_BLON
LVDS_BLEN_NB

HTTST_CLK

DFT_GPIO3
DFT_GPIO4
DFT_GPIO5

TP85TP85

DDC_NB_TP

TP7TP7

TESTMODE_NB

STRP_DATA

TEST MODE

D

TP86

TP86
TP80

TP80

TPAD30

TPAD30
TPAD30

TPAD30

TP91

TP91
TP90

TP90

TPAD30

TPAD30
TPAD30

TPAD30

1 2

TP8TP8

R112

R112

2KR2

2KR2

DY

DY

E

3D3V_S0

12

12

R515

12

R515
4K7R2

4K7R2

VGA_SMB_CLK

VGA_SMB_DAT

1D8V_S0

R485

R485

1 2

12

BLM11A121S

BLM11A121S

C667

C667
SCD1U16V

SCD1U16V

R102

R102

1 2

12

BLM11A121S

BLM11A121S

C124

C124
SCD1U16V

SCD1U16V

R85

R85

1 2

BLM11A121S

BLM11A121S

C88

C88
SCD1U16V

SCD1U16V

4

GND

3

A2

2

A1

1

A0

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

SNIPE

SNIPE

SNIPE

13 56Thursday, November 18, 2004

13 56Thursday, November 18, 2004

13 56Thursday, November 18, 2004

E

R516

R516

4K7R2

4K7R2

TXBOUT0+ 54
TXBOUT0- 54
TXBOUT1+ 54
TXBOUT1- 54
TXBOUT2+ 54
TXBOUT2- 54

TXAOUT0+ 54
TXAOUT0- 54
TXAOUT1+ 54
TXAOUT1- 54
TXAOUT2+ 54
TXAOUT2- 54

TXBCLK+ 54
TXBCLK- 54
TXACLK+ 54
TXACLK- 54

1D8VLPVDD_S0

LVDDR18D_S0

LVDDR18A_S0

TP93TP93

NBSRC_CLK 3
NBSRC_CLK# 3

R523

R523
10KR2

10KR2

HTREF_CLK 3

SBLINK_CLK 3
SBLINK_CLK# 3

R505

R505

12

3KR2F

3KR2F
R518

R518

12

3KR2F

3KR2F
R519

R519

12

3KR2F

3KR2F

DY

DY

3D3V_S0

12

12

R114

R114
1KR2

1KR2

1 2

12

DY

DY

DY

DY

R113

R113
2KR2

2KR2

VGA_SMB_CLK

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet

12

C649

C649

SC1U10V3ZY

SC1U10V3ZY

12

C117

C117

SC1U10V3ZY

SC1U10V3ZY

12

C87

C87
SC1U10V3ZY

SC1U10V3ZY

DISABLE DEBUG MODE
DUMMY IT

C678

C678
SCD1U16V

SCD1U16V

U16

U16

5

SDA

6

SCL

7

WP

8

VCC

AT24C04N-10SI

AT24C04N-10SI

DY

DY

NB-RS480M_VIDEO/ CLOCK

NB-RS480M_VIDEO/ CLOCK

NB-RS480M_VIDEO/ CLOCK

SA

SA

of

of

of

SA

A

B

C

D

E

VSS89

H17

H10

H16

H14

E16

D10

E15

F15

U15

V14

R15

T14

N15

V12

N13

P14

U17

T16

R17

P12

T12

R13

W13

W17

P18

V18

M18

U13

N17

W15

V16

T18

M14

M12

M16

P16

U19

AC16

AG18

AC23

AD8

AD11

AD13

AD16

AD19

AD23

AG5

AG6

AG21

AD17

AG15

AG12

AF30

AG24

AG9

AC19

AG27

AC11

AD7

AJ30

AC21

AK5

AK10

AC13

AD21

AK22

AK29

W19

AE26

AE27

T27

R27

AD28

F24

F27

G28

4 4

1D2V_S0

12

12

12

12

C651

C651
SCD1U16V

SCD1U16V

DY

DY

C730

C730
SCD1U16V

SCD1U16V

C769

C769
SCD1U16V

SCD1U16V

C758

C758
SCD1U16V

SCD1U16V

12

12

12

12

12

12

12

R551

R551
0R2-0

0R2-0

DY

DY

R81

R81

0R5J-1

0R5J-1

C668

C668
SCD1U16V

SCD1U16V

C722

C722
SCD1U16V

SCD1U16V

C243

C243
SCD1U16V

SCD1U16V

C746

C746
SCD1U16V

SCD1U16V

12

R552

R552
0R2-0

0R2-0

12

R82

R82

0R5J-1

12

C669

C669
SCD1U16V

SCD1U16V

12

C681

C681
SCD1U16V

SCD1U16V

DY

DY

12

C145

C145
SCD1U16V

SCD1U16V

12

C133

C133
SCD1U16V

SCD1U16V

DY

DY

L21

L21

1 2

BLM11A121S

BLM11A121S

0R5J-1

C706

C706
SCD1U16V

SCD1U16V

C670

C670
SCD1U16V

SCD1U16V

C783

C783
SCD1U16V

SCD1U16V

C757

C757
SCD1U16V

SCD1U16V

DY

DY

DY

DY

3

1 2

U68

U68
BAV99-1

BAV99-1

A

3 3

12

12

C103

C103

SC22U10V6ZY-U

SC22U10V6ZY-U

DY

DY

12

12

C723

C723
SCD1U16V

SCD1U16V

2 2

12

12

C146

C146

SC22U10V6ZY-U

SC22U10V6ZY-U

12

12

C134

C134
SCD1U16V

SCD1U16V

1D8V_S0

1 1

3D3V_S0

3

DY

DY

1 2

U21

U21
BAV99-1

BAV99-1

12

12

12

12

DY

DY

12

C759

C759
SCD1U16V

SCD1U16V

C652

C652
SCD1U16V

SCD1U16V

C721

C721
SCD1U16V

SCD1U16V

C144

C144
SCD1U16V

SCD1U16V

C747

C747
SCD1U16V

SCD1U16V

1D8VDD_S0

C745

C745
SCD1U16V

SCD1U16V

12

12

12

12

12

12

VSS110

VSS111

VSS112

R95

R95

0R5J-1

0R5J-1

C680

C680
SCD1U16V

SCD1U16V

C692

C692
SCD1U16V

SCD1U16V

2D5V_S3

C135

C135
SCD1U16V

SCD1U16V

C729

C729
SCD1U16V

SCD1U16V

C717

C717
SCD1U16V

SCD1U16V

VSS108

VSS109

12

12

12

C774

C774
SC1U10V3KX

SC1U10V3KX

1D2V_S0

VSS107

C760

C760
SCD1U16V

SCD1U16V

C782

C782
SCD1U16V

SCD1U16V

VSS102

VSS103

VSS104

VSS105

VSS106

1D2V_HT0A_S0

VDDHT30
VDDHT31

VSS95

VSS96

VSS97

VSS98

VSS99

VSS100

VSS101

U20E

U20E
RS480M-U

RS480M-U

N27

VDD_HT1

U27

VDD_HT2

V27

VDD_HT3

G27

VDD_HT4

V24

VDD_HT5

H27

VDD_HT6

K24

VDD_HT7

AB24

VDD_HT8

P27

VDD_HT9

J27

VDD_HT10

AA27

VDD_HT11

K27

VDD_HT12

P24

VDD_HT13

AB27

VDD_HT14

AB23

VDD_HT15

V23

VDD_HT16

G23

VDD_HT17

E23

VDD_HT18

W23

VDD_HT19

K23

VDD_HT20

J23

VDD_HT21

H23

VDD_HT22

U23

VDD_HT23

AA23

VDD_HT24

D23

VDD_HT25

F23

VDD_HT26

C23

VDD_HT27

B23

VDD_HT28

A23

VDD_HT29

A29

VDD_HT30

AC30

VDD_HT31

AK23

VDD_MEM1

AK28

VDD_MEM2

AK11

VDD_MEM3

AK4

VDD_MEM4

AE30

VDD_MEM5

AC14

VDD_MEM6

AD12

VDD_MEM7

AC18

VDD_MEM8

AC20

VDD_MEM9

AD10

VDD_MEM10

AD14

VDD_MEM11

AD15

VDD_MEM12

AD20

VDD_MEM13

AC10

VDD_MEM14

AD18

VDD_MEM15

AC12

VDD_MEM16

AD22

VDD_MEM17

AC22

VDD_MEM18

AH15

VDD_MEMCK

H15

VDD_18_1

AC17

VDD_18_2

AC15

VDD_18_3

B21

VDD_CORE47

C21

VDD_CORE46

A22

VDD_CORE45

B22

VDD_CORE44

C22

VDD_CORE43

F21

VDD_CORE42

F22

VDD_CORE41

E21

VDD_CORE40

G21

VDD_CORE39

B

VSS93

VSS94

VSS89

VSS90

VSS91

VSS92

PART 5 OF 6

PART 5 OF 6

VSS85

VSS86

VSS87

VSS88

VSS129

VSS130

VSS131

VSS132

K25

V25

V28

U28

R23

POWER

POWER

VSS83

VSS84

VSS127

VSS128

E26

VDDA_12_14

VDDA_12_1
VDDA_12_2
VDDA_12_3
VDDA_12_4
VDDA_12_5
VDDA_12_6
VDDA_12_7
VDDA_12_8

VDDA_12_9
VDDA_12_10
VDDA_12_11
VDDA_12_12
VDDA_12_13

VDDA_18_1

VDDA_18_2

VDDA_18_3

VDDA_18_4

VDDA_18_5

VDDA_18_6

VDDA_18_7

VDDA_18_8

VDDA_18_9
VDDA_18_10
VDDA_18_11
VDDA_18_12
VDDA_18_13
VDD_CORE1
VDD_CORE2
VDD_CORE3
VDD_CORE4
VDD_CORE5
VDD_CORE6
VDD_CORE7
VDD_CORE8
VDD_CORE9

VDD_CORE10
VDD_CORE11
VDD_CORE12
VDD_CORE13
VDD_CORE14
VDD_CORE15
VDD_CORE16
VDD_CORE17
VDD_CORE18
VDD_CORE19
VDD_CORE20
VDD_CORE21
VDD_CORE22
VDD_CORE23
VDD_CORE24
VDD_CORE25
VDD_CORE26
VDD_CORE27
VDD_CORE28
VDD_CORE29
VDD_CORE30
VDD_CORE31
VDD_CORE32
VDD_CORE33
VDD_CORE34
VDD_CORE35
VDD_CORE36
VDD_CORE37
VDD_CORE38

VSS77

VSS78

VSS79

VSS80

VSS81

VSS82

VSS122

VSS123

VSS124

VSS125

VSS126

L27

P25

P28

H24

N28

M27

H9
AA7
G9
U8
N7
N8
U7
F9
AA8
G8
G7
J8
J7
B1
AG4
R8
AC8
AC7
AF6
AE6
L8
W8
W7
L7
R7
AF5
AK2
N16
M13
M15
W16
N18
P19
N12
P15
N14
M17
T19
G22
R12
P13
R14
V19
R18
U16
U12
T13
U14
T17
U18
E22
R16
V13
T15
P17
W18
D22
W12
V15
W14
V17
M19
H22
H21
D21

VSS76

VSS120

T23

VSS74

VSS75

VSS118

VSS119

K28

N19

VDDA12_13

VDDA18_13

VSS72

VSS73

VSS114

VSS115

VSS116

VSS117

J28

H28

M24

VSS66

VSS67

VSS68

VSS69

VSS70

VSS71

GROUND

GROUND

VSS113

T8

F28

12

1D8V_VDDA

12

1D2V_S0

C

VSS62

VSS63

VSS64

VSS65

12

C728

C728
SC1U10V3KX

SC1U10V3KX

12

C792

C792
SC1U10V3KX

SC1U10V3KX

12

C744

C744

SC22U10V6ZY-U

SC22U10V6ZY-U

12

C112

C112

SC22U10V6ZY-U

SC22U10V6ZY-U

VSS60

VSS61

C727

C727
SCD1U16V

SCD1U16V

C786

C786
SCD1U16V

SCD1U16V

DY

DY

VSS59

VSS58

VSSA60M7VSSA61V7VSSA62F6VSSA63E6VSSA64U5VSSA65U6VSSA66E5VSSA67L5VSSA68

AJ1

VSSA59

12

12

12

12

VSS55

VSS56

VSS57

VSSA58L6VSSA59

AG3

C768

C768
SCD1U16V

SCD1U16V

C781

C781
SCD1U16V

SCD1U16V

C704

C704
SCD1U16V

SCD1U16V

C703

C703
SCD1U16V

SCD1U16V

VSS54

VSS53

12

12

12

12

VSS50

VSS51

VSS52

C756

C756
SCD1U16V

SCD1U16V

C755

C755
SCD1U16V

SCD1U16V

C719

C719
SCD1U16V

SCD1U16V

C650

C650
SCD1U16V

SCD1U16V

VSS48

VSS49

VSSA51K7VSSA52H7VSSA53M3VSSA54V6VSSA55H8VSSA56C2VSSA57

AD6

12

DY

DY

12

VSS46

VSS47

VSSA48T7VSSA49Y7VSSA50

AB8

12

C742

C742
SCD1U16V

SCD1U16V

12

C754

C754
SCD1U16V

SCD1U16V

C767

C767
SCD1U16V

SCD1U16V

C679

C679
SCD1U16V

SCD1U16V

VSS44

VSS45

VSSA44D6VSSA45C4VSSA46K3VSSA47

AD5

12

L23

L23

1 2

MLB-201209-11

MLB-201209-11

12

C743

C743
SCD1U16V

SCD1U16V

DY

DY

12

C720

C720
SCD1U16V

SCD1U16V

VSS42

VSS43

C718

C718

SC22U10V6ZY-U

SC22U10V6ZY-U

VSS40

VSS41

1D8V_S0

VSS37

VSS38

VSS39

VSSA38C9VSSA39C7VSSA40J5VSSA41R6VSSA42J3VSSA43

AA5

12

D

D11

H11

AD25

VSS35

VSS36

1D2V_S0

C716

C716
SCD1U16V

SCD1U16V

VSS30

G10

G12

AD29

AD27

AC27

G15

G14

Y24

G13

D15

AD9

G11

F16

G30

AB28

AB25

D12

AD24

AA28

G17

Y23

AC9

R19

Y27

C28

G16

F25

B30

T24

F26

W27

VSS6

VSS7

VSS8

VSS9

VSS10E9VSS11

VSS12D9VSS13

VSS14

VSS15

VSS16

VSS17

VSS18

VSS19

VSS20

VSS21

VSS22

VSS23

VSS24

VSS25

VSS26

VSS27

VSS28

VSS29

VSS30

VSS31

VSS32

VSS33

VSS34

VSSA22A2VSSA23

VSSA24P8VSSA25J6VSSA26C8VSSA27

VSSA28V8VSSA29F3VSSA30

VSSA31

VSSA32M5VSSA33

VSSA34G3VSSA35B4VSSA36P7VSSA37

AB7

AF3

AE3

AA3

AB3

AD3

VSSA22

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet

NB-RS480M_POWER

NB-RS480M_POWER

NB-RS480M_POWER

VSSA9T3VSSA10M6VSSA11C5VSSA12F8VSSA13M8VSSA14Y8VSSA15V3VSSA16C3VSSA17W3VSSA18K8VSSA19D3VSSA20C6VSSA21

AA6

VDDA12_13

VSSA22

VDDA18_13

VSSA59

VDDHT30

VSS30

VDDHT31

VSS89

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

SNIPE

SNIPE

SNIPE

E

VSS5

VSS4

VSSA4N3VSSA5F7VSSA6F5VSSA7R3VSSA8

V5

VSS2

VSS3

PAR 6 OF 6

PAR 6 OF 6

VSSA2

VSSA3

AE5

14 56Thursday, November 18, 2004

14 56Thursday, November 18, 2004

14 56Thursday, November 18, 2004

VSS1

VSSA1

R5

U20F

U20F
RS480M-U

RS480M-U

12

12

12

12

C150

C150

SC4D7U10V5ZY

SC4D7U10V5ZY

C251

C251

SC4D7U10V5ZY

SC4D7U10V5ZY

C91

C91

SC4D7U10V5ZY

SC4D7U10V5ZY

C129

C129

SC4D7U10V5ZY

SC4D7U10V5ZY

of

SA

SA

SA

A

4 4

TMDS_TXC­TMDS_TXC+
TMDS_TX0­TMDS_TX0+

TMDS_TX1­TMDS_TX1+
TMDS_TX2­TMDS_TX2+

B

TMDS_TXC- 449
TMDS_TXC+ 449
TMDS_TX0- 449
TMDS_TX0+ 449

TMDS_TX1- 449
TMDS_TX1+ 449
TMDS_TX2- 449
TMDS_TX2+ 449

C

DVI_SCL_5

DVI_SDA_5

D

12

R338

R338
8K2R2

8K2R2

12

C493

C493
SC100P50V2JN

SC100P50V2JN

5V_DVI_S0

R339

R339
8K2R2

8K2R2

C494

C494
SC100P50V2JN

SC100P50V2JN

12

12

E

D19

D19

2 1

CH751H-40-U

CH751H-40-U

83.R0304.08F

83.R0304.08F

1 2

5V_S0

F1

F1

FUSE-1A6V

FUSE-1A6V

DVI_VCC

3 3

2 2

DVI_VCC

D1

D1

DVI_HPD449

1 1

1 2

S1N4148-U

S1N4148-U

A

R337

R337

100KR2

100KR2

Do not stuff when using UMA

DVI_SDA449

DVI_SCL449

DVI1

DVI1

TMDS_TX1-

TMDS_TX1+

12

TMDS_TX0-

TMDS_TX0+

TMDS_TXC+

TMDS_TXC­TMDS_HPD

29

17

9

18
10
19
11
20
12
21
13
22
14
23
15
24
16
C3

C4

30

AMP-CONN24-3R

AMP-CONN24-3R

27
MH1

TMDS_TX2-

1

25

TMDS_TX2+

2
3

4

5

DVI_SCL_5

6

DVI_SDA_5

7

8
C1
26
C5C6
C2
MH2
28

B

C

D

3D3V_S0

R351

R351
8K2R2

8K2R2

12

R352

R352

G

G

8K2R2

8K2R2

1

S

S

2 3

Q1

Q1
2N7002LT1

2N7002LT1

D

D

S

S

2 3

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

G

G

1

Q2

Q2
2N7002LT1

2N7002LT1

DVI_SDA_5

D

D

DVI_SCL_5

5V @ ext. CRT side

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

DVI CONNECTOR

DVI CONNECTOR

DVI CONNECTOR

SNIPE

SNIPE

SNIPE

of

of

of

15 56Thursday, November 18, 2004

15 56Thursday, November 18, 2004

15 56Thursday, November 18, 2004

E

SA

SA

SA

12

A

R335

R335

1 2

0R2-0

0R2-0

5V_S0

DY

4 4

CRT_HSYNC54

CRT_VSYNC54

3 3

CRT_RED54

CRT_GREEN54

CRT_BLUE54

DY

14

4

5 6

7

R325

R325

1 2

0R2-0

0R2-0

DY

DY

14

2 3

U47B

U47B

7

TSAHCT125

TSAHCT125

1

U47A

U47A

TSAHCT125

TSAHCT125

12

C477

C477

SC47P50V2JN

SC47P50V2JN

DY

DY

CRT

Signal level need check.

HSYNC_5

VSYNC_5

12

C476

C476
DUMMY-C2

DUMMY-C2

12

C488

C488

SC47P50V2JN

SC47P50V2JN

DY

DY

B

L14

L14

1 2

0R5J-1

0R5J-1

L15

L15

1 2

0R5J-1

0R5J-1

12

C490

C490
DUMMY-C2

DUMMY-C2

L11 BLM18BB750SN1DL11 BLM18BB750SN1D

L12 BLM18BB750SN1DL12 BLM18BB750SN1D

L13 BLM18BB750SN1DL13 BLM18BB750SN1D

12

C489

C489
SC47P50V2JN

SC47P50V2JN

DY

DY

JVGA_HS_1

1 2

1 2

1 2

12

JVGA_VS_1

12

C475

C475
DUMMY-C2

DUMMY-C2

12

1 2

R322 33R2R322 33R2

1 2

R323 33R2R323 33R2

C474

C474
DUMMY-C2

DUMMY-C2

12

C478

C478
SC2P50V

SC2P50V

C479

C479
SC2P50V

SC2P50V

JVGA_HS

JVGA_VS

CRT_R

CRT_G

CRT_B

12

C480

C480
SC2P50V

SC2P50V

C

CRT_R

CRT_G

CRT_B

D

CRT CONN

200mA Rating/Spec 500mA

5V_S0

D15

D15

2

3

1

BAV99-2

BAV99-2
D16

D16

2

3

1

BAV99-2

BAV99-2
D17

D17

2

3

1

BAV99-2

BAV99-2

5V_S0

D18

D18

RB751V-40-U

RB751V-40-U

CRT_R

CRT_G

JVGA_HS
CRT_B

JVGA_VS

SC100P50V2JN

SC100P50V2JN

5V_CRT_S0

R321

R321

2K2R2

2K2R2

C469

C469

SC100P50V2JN

SC100P50V2JN

12

12

R324

R324
2K2R2

2K2R2

12

12

SC10P50V2JN-1

SC10P50V2JN-1

C473

C473

C470

C470

1 2

CRT_DAT_DDC_354

CRT_CLK_DDC_354

F4

F4

1 2

FUSE-1A6V

FUSE-1A6V

12

CRT_VCC

12

C472

C472
SC10P50V2JN-1

SC10P50V2JN-1

12

C471

C471
SCD01U50V2ZY

SCD01U50V2ZY

16

11

12

13

14

10
15

17

E

CRT1

CRT1

6

1
7

2
8

3
9

4

5

VIDEO-15-34

VIDEO-15-34

By ME requset CRT1 P/N:
Main 20.B0026.A15
Second 20.B0034.015

2 2

D21

C500

C500

1 2

SC47P50V2JN

SC47P50V2JN

L17

L17

C515

C515

1 2

IND-1D2UH

IND-1D2UH

12

C516

C516
SC100P50V2JN

SC100P50V2JN

L18

L18
IND-1D2UH

IND-1D2UH

1 2

12

C517

C517
SC100P50V2JN

SC100P50V2JN

1 2

L16

L16

1 2

IND-1D2UH

IND-1D2UH

12

TVLUMA54

TVCOMP54

1 1

TVCRMA54

SC100P50V2JN

SC100P50V2JN

A

TV_LUMA

12

COMP_B

12

C498

C498
SC47P50V2JN

SC47P50V2JN

TV_CRMA

12

B

C499

C499
SC270P50V

SC270P50V

C501

C501
SC270P50V

SC270P50V

C497

C497
SC270P50V

SC270P50V

MH1

8
3
1

5
7

6
2
4
9

TV1

TV1

MINDIN7-8

MINDIN7-8

D21

3

BAV99-2

BAV99-2

DY

DY

3D3V_S0

2

1

By ME requset TV1 P/N:
Main 22.10021.A91
Second 22.10021.B01

D20

D20

2

3

BAV99-2

BAV99-2

DY

DY

3D3V_S0

1

C

COMP_B

TV CONN

D22

D22

2

3

BAV99-2

BAV99-2

DY

DY

3D3V_S0

1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet of

D

Date: Sheet of

CRT / TV

CRT / TV

CRT / TV

SNIPE

SNIPE

SNIPE

SA

SA

of

16 56Thursday, November 18, 2004

16 56Thursday, November 18, 2004

16 56Thursday, November 18, 2004

E

SA

A

B

C

D

E

INVERTER/LED

4 4

Q6

Q6

OUT

OUT

GND

GND

OUT

OUT

GND

GND

OUT

OUT

80211_LED#

GND

GND

CHARGE_LED#

STDBY_LED#

80211_LED# 35

CHARGE_LED#

NUM_LED#34
CAP_LED#34

FPBACK34

FPBACK FPBACK_INV

BRIGHTNESS34

NUM_LED#
CAP_LED#

1 2

R355

R355
10KR3

10KR3

12

C512

C512
SCD1U

SCD1U

MEDIA_LED#

12

C507

C507
SC100P50V2JN

SC100P50V2JN

12

C511

C511
SC100P50V2JN

SC100P50V2JN

CHARGE_LED34

3 3

STDBY_LED34,35

WLAN_LED34

2 2

2

IN

IN

2

IN

IN

2

IN

IN

R2

R2

DTC114EUA-U1

DTC114EUA-U1

Q7

Q7

R1

R1

R2

R2

DTC114EUA-U1

DTC114EUA-U1

Q19

Q19

R1

R1

R2

R2

DTC114EUA-U1

DTC114EUA-U1

1

3

1

3

1

3

R1

R1

Layout trace 20 mil

5V_S5

12

C506

C506
SCD1U

SCD1U

12

C509

C509
SC100P50V2JN

SC100P50V2JN

12

12

C510

C510
SC100P50V2JN

SC100P50V2JN

By ME requset INV1 P/N:
Main 20.F0322.030
Second 20.D0144.215

2

4
6

8
10
12
14
16
18
20
22
24
26
28

C508

C508

30

SC100P50V2JN

SC100P50V2JN

ETY-CONN30D-U

ETY-CONN30D-U

20.F0322.030

20.F0322.030

INV1

INV1

DCBATOUT

31

1

3
5
7
9
11
13
15
17

PWRLED#

19
21
23

(LED USE)

25
27
29

32

12

3

2

12

3D3V_S3

C484

C484
SCD1U16V

SCD1U16V

12

C487

C487
SCD1U16V

SCD1U16V

Q20

Q20
PDTC144EU

PDTC144EU

1

C496

C496
SC10U35V0ZY-U

SC10U35V0ZY-U

STDBY_LED#

3D3V_S0

3D3V_S0

HDD_LED#_525

CDROM_LED#_525

5V_S0

12

C483

C483
SC1U10V3KX

SC1U10V3KX

80211_LED#

12

C485

C485
SC100P50V2JN

SC100P50V2JN

TOP VIEW

1

12

C486

C486
SC100P50V2JN

SC100P50V2JN

INV CONN

D23

D23

2

3

1

BAW56

BAW56

29

302

MEDIA_LED#

TOP VIEW

240

LCD CONN

LCD1

LCD1

42

1

PANEL_ID037
PANEL_ID137
PANEL_ID237
PANEL_ID337

1 1

3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

A

2

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

41

SYN-CONN40A-U

SYN-CONN40A-U

20.F0312.040

20.F0312.040

LCDPOWER_S0

12

C513

C513
SC10U10V5ZY

SC10U10V5ZY

DY

DY

LCD_TXBCLK+ 54
LCD_TXBCLK- 54
LCD_TXBOUT2+ 54
LCD_TXBOUT2- 54
LCD_TXBOUT1+ 54
LCD_TXBOUT1- 54
LCD_TXBOUT0+ 54
LCD_TXBOUT0- 54
LCD_TXACLK+ 54
LCD_TXACLK- 54
LCD_TXAOUT2+ 54
LCD_TXAOUT2- 54
LCD_TXAOUT1+ 54
LCD_TXAOUT1- 54
LCD_TXAOUT0+ 54
LCD_TXAOUT0- 54

12

LCD CONN

1

C514

C514
SCD1U

SCD1U

DY

DY

B

12

C522

C522
SCD1U

SCD1U

39

EVEN CHANNEL

ODD CHANNEL

LCD POWER

LCD_VDD_ON54

1 2

C

R336

R336
1KR3

1KR3

Layout 40 mil

LCDVDD_ON_1

12

12

C491

C491

C492

C492

SC1U10V3KX

SC1U10V3KX

SCD1U

SCD1U

U49

U49

1

OUT

2

GND
ON/OFF#3IN

AAT4280IGU-3-T1

AAT4280IGU-3-T1

D

3D3V_S0LCDPOWER_S0

6

IN

5

GND

4

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet of

12

C523

C523
SC1U10V3KX

SC1U10V3KX

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

INV / LCD

INV / LCD

INV / LCD

A3

A3

A3

SNIPE

SNIPE

SNIPE

E

SA

SA

of

17 56Thursday, November 18, 2004

17 56Thursday, November 18, 2004

17 56Thursday, November 18, 2004

SA