Acer Aspire 1400 Schematics REV 1A
COMPAL CONFIDENTIAL
MODEL NAME :BBR20 LA-1512
REV:1.0
CRT & TV-OUT
LCD
PAGE 18
Pentium4/Northwood
mPGA478 CPU
PAGE 2,3
PSB
CLOCK
ICS950805
PAGE 11
INTERNAL IDE
IDE/CD
/FDD
PAGE 25
USB/BlueTooth
LPT PORT
MDC
ATI
M6P
16MB DDR SDRAM
PIRQA#
Direct CD
Play
PAGE 24
PAGE 27
PAGE 26
PAGE 14,15,16,17
HUB Link
ICH2
FUNC 0: LAN, HUB-TO-PCI ,
PCI-TO-LPC BRIDGE
FUNC 1: IDE Controller
FUNC 2: USB Controller #1
FUNC 3: SM BUS Controller
FUNC 4: USB Controller #2
FUNC 5: AC97 Audio Controller
FUNC 5: AC97 Modem Controller
LPC
SIO
LPC 47N227
PAGE 27
PCI BUS
PAGE 10,11,12
LPC
EC/KBC
PC87591
PAGE 31
BIOS
EC BUFFER
Brookdale
MCH
Host-AGP Bridge
DRAM controller
Hub interface
IDSEL: AD26
MASTER 2
PIRQC#
1394 Controller
TAB43AB22
AC LINK
AC97 Codec
PAGE 31 PAGE 30
PROPRIETARY NOTE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PAGE 19
MDC
Connector
PAGE 29 PAGE 30
Switchs &
Connectors
PAGE 4,5,6
PAGE 25
AMP &
Audio
Jack
MEMORY BUSAGP BUS
CARDBUS
PCMCIA
SOCKET
OZ6933
DDR DIMM*2
IDSEL: AD16
MASTER 3
PIRQA#, PIRQB#
SIRQ
PAGE 20
PAGE 20
PAGE 7,8
LAN Controller
INTEL PHY
PAGE 22
POWER
INTERFACE
PAGE 35
IDSEL: AD27
MASTER 0
PIRQA#,
PIRQD#
Mini PCI
Connector
PAGE 23
DC/DC POWER
+1.5V POWER
+1.8V POWER
+2.5V POWER
+3VALW POWER
+5VALW POWER
+12VALW POWER
CPU_VCC PO WER
PAGE 36,37,38,39,40,41
Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-1512
Size Document Number Rev
B
401225
星期四 九月
Date: Sheet of
1 44, 12, 2002
1A
A
CPU_VCC
1 2
R274 51_1%
1 2
R91 56
1 2
R280 300_1%
1 2
R290 51_1%
4 4
1 8
2 7
3 6
4 5
3 3
CPU_VCC
2 2
1 1
CPURST#
FERR#
CPU_PWRGD
BREQ0#
RP5
ITP_TMS
ITP_TRST#
ITP_TCK
ITP_TDI
8P4R-1K
1 2
R250 51_1%
1 2
R251 51_1%
1 2
R262 51_1%
1 2
R253 51_1%
1 2
R254 51_1%
1 2
R263 51_1%
SELPSB[1:0] STSEM BUS FREQUENCY
00
01
10
11
BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#
CPU_PWRGD10
100MHZ
RESERVED
RESERVED
RESERVED
A
HREQ#04
HREQ#14
HREQ#24
HREQ#34
HREQ#44
ADSTB0#4
ADSTB1#4
BREQ0#4
HLOCK#4
HIT#4
HITM#4
DEFER#4
DRDY#4
CPURST#4
HTRDY#4
CPU_VCC
BSEL013
BSEL113
DBSY#4
CPUSLP#10
HA#[3..31]4
ADS#4
BNR#4
BPRI#4
RS#04
RS#14
RS#24
HA#[3..31]
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
BREQ0#
CPURST#
BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#
TD0
ITP_TDI
ITP_TMS
ITP_TRST#
ITP_TCK
1 2
R82 @62_1%
BSEL0
BSEL1
DBR#
CPU_PWRGD
CPUSLP#
THERMDA
THERMDC
THERMTRIP#
M6
M3
M4
M1
W1
W2
AB1
G1
AC1
AA3
G2
AC3
J26
K25
K26
L25
G4
AB25
G5
AB2
AC6
AB5
AC4
AA5
AB4
AF26
AD6
AD5
AE25
AB23
AB26
K2
K4
L6
K1
L3
L2
N1
N2
N4
N5
T1
R2
P3
P4
R3
T2
U1
P6
U3
T4
V2
R6
T5
U4
V3
Y1
J1
K5
J4
J3
H3
L5
R5
V5
H6
D2
F3
E3
E2
H2
V6
J6
F1
F4
Y6
D5
C1
F7
E6
D4
C3
H5
B3
C4
A2
U23A
A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
A32#
A33#
A34#
A35#
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
ADSTB0#
ADSTB1#
ADS#
AP0#
AP1#
BINIT#
BNR#
IERR#
DP0#
DP1#
DP2#
DP3#
BREQ0#
BPRI#
LOCK#
HIT#
HITM#
DEFER#
DRDY#
MCERR#
RESET#
TRDY#
RS0#
RS1#
RS2#
RSP#
BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#
SKTOCC#
TDO
TDI
TMS
TRST#
TCK
PROCHOT#
BSEL0
BSEL1
DBSY#
DBR#
PWRGOOD
SLP#
THERMDA
THERMDC
THERMTRIP#
mPGA478
B
ADDR GROUP
CONTROL GROUP
THERMAL DIODE
B
Northwood
MISC
PROPRIETARY NOTE
C
HD#[0..63]
HD#0
B21
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
DATA GROUP
HOST CLK
LEGACY CPU
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DBI0#
DBI1#
DBI2#
DBI3#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
BCLK0
BCLK1
ITPCLK0
ITPCLK1
A20M#
FERR#
IGNNE#
INTR/LINT0
NMI/LINT1
INIT#
STPCLK#
SMI#
B22
A23
A25
C21
D22
B24
C23
C24
B25
G22
H21
C26
D23
J21
D25
H22
E24
G23
F23
F24
E25
F26
D26
L21
G26
H24
M21
L22
J24
K23
H25
M23
N22
P21
M24
N23
M26
N26
N25
R21
P24
R25
R24
T26
T25
T22
T23
U26
U24
U23
V25
U21
V22
V24
W26
Y26
W25
Y23
Y24
Y21
AA25
AA22
AA24
E21
G25
P26
V21
E22
K22
R22
W22
F21
J23
P23
W23
AF22
AF23
AC26
AD26
C6
B6
B2
D1
E5
W5
Y4
B5
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
A20M#
FERR#
IGNNE#
INTR
NMI
C
HD#[0..63] 4
SB_A20M#
SB_IGNNE#
SB_INTR
SB_NMI NMI
DBI0# 4
DBI1# 4
DBI2# 4
DBI3# 4
DSTBN0# 4
DSTBN1# 4
DSTBN2# 4
DSTBN3# 4
DSTBP0# 4
DSTBP1# 4
DSTBP2# 4
DSTBP3# 4
HCLK_CPU 13
HCLK_CPU# 13
FERR# 10
CPUINIT# 10
STPCLK# 10
SMI# 10
2200PF
+5VS
1 2
1 2
1 2
1 2
CPU_VCC
CPU_VCC
12
C104
R67 1K
R95
0
R97
0
R66
0
R65
0
1 2
A20M#
IGNNE#
INTR
R92
@0
1 2
R142 56
1 2
R98 56
12
THERMDA
THERMDC
R93
C71
.1UF
@0
1 8
12
THERMTRIP#
D
1617VCC
U5
1
NC
2
VCC
3
DXP
4
DXN
5
NC
6
ADD1
7
GND
8 9
GND NC
MAX1617/MAX6654
RP7
@8P4R_1K
2 7
3 6
4 5
SB_A20M#10
SB_IGNNE#10
SB_INTR10
SB_NMI10
12
12
12
CPURST#4
R96
R94
@0
+3V
R144
1K
1 2
1
C
2
B
E
3
D
NC
STBY
SMBCLK
NC
SMBDATA
ALERT
ADD0
CPU_VCC
@0
1 2
R145
@0
Q8
2SC2411K
+5VS
12
R38
200
16
15
14
13
12
ATF#
11
10
SB_A20M#
SB_IGNNE#
SB_INTR
SB_NMI
1 2
R497
@1K
Compal Electronics, Inc.
Title
Size Document Number Rev
B
Date: Sheet of
EC_SMC2 24,31
EC_SMD2 24,31
12
R39
1K
+5VS
U7
2
3
5
6
11
10
14
13
1
C604
@0.22UF
1 2
RATIO
15X
16X
17X
18X
19X
20X
21X
22X
23X
24X
THERTRIP# 31
VR_ON 31,41
IOA
IOA
IOB
IOB
I1C
I1C
I1D
I1D
S
16
VCC
4
YA
7
YB
9
YC
12
YD
8
GND
15
E#
@QS3257
A20M#
IGNNE#
INTR
NMI
SW1 RATIO SELECT
NMI A20M# IGNNE# INTR
H
L
L
L
L
L
L
L
H
L
SCHEMATIC, M/B LA-1512
401225
星期四 九月
E
+3VS
A20M#
IGNNE#
INTR
NMI
1 2
R61 @1K
45
36
27
18
RP6
@8P4R_330
L
H
H
H
H
L
L
L
H
L
E
C96
1 2
@.1UF
L
H
H
L
L
H
H
L
H
L
CPU_VCC
L
H
L
H
L
H
L
H
L
L
1A
2 44, 12, 2002
A
C28
150U_D
10
9
8
7
6
10
9
8
7
6
+
VCCA
+
VCCIOPLL
CPU_VCC
TESTHI7
TESTHI6
TESTHI5
TESTHI4
TESTHI12
C368
150U_D
VSSA
CPU_VCC
CPU_VCC
12
C365
1UF
AD20
AD22
AE23
A10
A12
A14
A16
A18
A20
AA10
AA12
AA14
AA16
AA18
AA8
AB11
AB13
AB15
AB17
AB19
AB7
AB9
AC10
AC12
AC14
AC16
AC18
AC8
AD11
AD13
AD15
AD17
AD19
AD7
AD9
AE10
AE12
AE14
AE16
AE18
AE20
AE6
AE8
AF11
AF13
AF15
AF17
AF19
AF2
AF21
AF5
AF7
A5
A4
A8
U23B
VCCA
VSSA
VCCIOPLL
VCCSENSE
VSSSENSE
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
CPU_VCC
4 4
3 3
TESTHI0
TESTHI1
TESTHI2
TESTHI3
CPU_VCC
TESTHI8
TESTHI9
TESTHI10
TESTHI11
CPU_VCC
1 2
L6
4.7UH_0805
1 2
L7
4.7UH_0805
RP25
1
2
3
4
5
10P8R-4.7K
RP4
1
2
3
4
5
10P8R-4.7K
CPU_VCC
2 2
R291
49.9_1%
CPU_GTLREF
1 2
12
12
12
R287
100_1%
C388
1UF
C379
220PF
C392
220PF
1 2
CPU_VCC
R62
@49.9_1%
H_GTLREF
1 2
12
12
12
C76
C72
1 1
R60
@100_1%
1 2
@1UF
@220PF
C65
@220PF
CPUVID
CPU_GTLREF
H_GTLREF
R294
51.1_1%
1 2
TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI6
TESTHI7
TESTHI8
TESTHI9
TESTHI10
TESTHI11
TESTHI12
COMP0
COMP1
R59
51.1_1%
1 2
R492
@0
AD24
TESTHI0
AA2
TESTHI1
AC21
TESTHI2
AC20
TESTHI3
AC24
TESTHI4
AC23
TESTHI5
AA20
TESTHI6
AB22
TESTHI7
U6
TESTHI8
W4
TESTHI9
Y3
TESTHI10
A6
TESTHI11
AD25
TESTHI12
AA21
GTLREF
AA6
GTLREF
F20
GTLREF
F6
GTLREF
L24
COMP0
P1
COMP1
A22
RSVD
A7
RSVD
AD2
RSVD
AD3
RSVD
AE21
RSVD
AF3
12
RSVD
AF24
RSVD
AF25
RSVD
mPGA478
A
B
PLL ANALOG VOLTAGE
Northwood
POWER,
GROUND,
RESERVED
SIGNALS
B
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D10
A11
A13
A15
A17
A19
A21
A24
A26
A3
A9
AA1
AA11
AA13
AA15
AA17
AA19
AA23
AA26
AA4
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB21
AB24
AB3
AB6
AB8
AC11
AC13
AC15
AC17
AC19
AC2
AC22
AC25
AC5
AC7
AC9
AD1
AD10
AD12
AD14
AD16
AD18
AD21
AD23
AD4
AD8
AE11
AE13
AE15
AE17
AE19
AE22
AE24
AE26
AE7
AE9
AF1
AF10
AF12
AF14
AF16
AF18
AF20
AF6
AF8
B10
B12
B14
B16
B18
B20
B23
B26
B4
B8
C11
C13
C15
C17
C19
C2
C22
C25
C5
C7
C9
D12
D14
D16
D18
D20
D21
D24
D3
CPU_VCC
CPU_VCC
CPU_VCC
CPU_VCC
CPU_VCC
CPU_VCC
CPU_VCC
CPU_VCC
12
C70
.1UF
12
C107
1UF
12
C35
10UF_1206
12
C32
10UF_1206
12
C372
10UF_1206
12
C445
10UF_1206
12
C450
10UF_1206
12
C145
10UF_1206
C167
+
470U_E
2.5V
C163
+
470U_E
2.5V
12
C66
.1UF
12
C98
1UF
12
C34
10UF_1206
12
C31
10UF_1206
12
C373
10UF_1206
12
C369
10UF_1206
12
C451
10UF_1206
12
C135
10UF_1206
C168
+
470U_E
2.5V
C166
+
470U_E
2.5V
C
12
C73
.1UF
12
C88
1UF
12
C33
10UF_1206
12
C30
10UF_1206
12
C374
10UF_1206
12
C413
10UF_1206
12
C452
10UF_1206
12
C130
10UF_1206
C
12
C77
.1UF
12
C85
1UF
+
+
12
C84
.1UF
12
C78
1UF
12
C29
10UF_1206
12
C367
10UF_1206
12
C446
10UF_1206
12
C423
10UF_1206
12
C118
10UF_1206
C164
470U_E
2.5V
C160
470U_E
2.5V
PROPRIETARY NOTE
12
12
C87
C97
.1UF
.1UF
CPU_VCC
12
12
C74
C67
1UF
1UF
12
C366
10UF_1206
12
C442
10UF_1206
12
C447
10UF_1206
12
C148
10UF_1206
12
C428
10UF_1206
C19
+
470U_E
2.5V
C18
+
470U_E
2.5V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
E
CPU_VCC
12
C106
.1UF
12
C370
10UF_1206
12
C443
10UF_1206
12
C448
10UF_1206
12
C147
10UF_1206
12
C418
10UF_1206
12
.1UF
C103
12
C41
.1UF
12
C371
10UF_1206
12
C444
10UF_1206
12
C449
10UF_1206
12
C146
10UF_1206
12
C410
10UF_1206
CPU_VCC
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPUVID41
CPUVID
12
C40
1UF
AF9
B11
B13
B15
B17
B19
C10
C12
C14
C16
C18
C20
D11
D13
D15
D17
D19
E10
E12
E14
E16
E18
E20
F11
F13
F15
F17
F19
AE5
AE4
AE3
AE2
AE1
AF4
Y25
Y22
W24
W21
V26
V23
U25
U22
VCC
VCC
VCC
VCC
VCC
VCC
B7
VCC
B9
VCC
VCC
VCC
VCC
VCC
VCC
VCC
C8
VCC
VCC
VCC
VCC
VCC
VCC
D7
VCC
D9
VCC
VCC
VCC
VCC
VCC
VCC
VCC
E8
VCC
VCC
VCC
VCC
VCC
VCC
F9
VCC
VID0
VID1
VID2
VID3
VID4
Northwood
POWER, GROUND AND NC
VCCVID
Y5
VSS
VSS
VSS
Y2
VSS
W6
VSS
W3
VSS
VSS
VSS
V4
VSS
VSS
VSS
V1
VSS
U5
VSS
VSS
VSS
mPGA478
VID[0..4]41
CPU_VID[0..4]
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D6
D8
E1
E11
E13
E15
E17
E19
E23
E26
E4
E7
E9
F10
F12
F14
F16
F18
F2
F22
F25
F5
F8
G21
G24
G3
G6
H1
H23
H26
H4
J2
J22
J25
J5
K21
K24
K3
K6
L1
L23
L26
L4
M2
M22
M25
M5
N21
N24
N3
N6
P2
P22
P25
P5
R1
R23
R26
R4
T21
T24
T3
T6
U2
U23C
+3V
RP3
C359
+
330U_E
2.5V
C105
+
470U_E
2.5V
C165
+
470U_E
2.5V
C468
+
330U_E
2.5V
C159
+
470U_E
2.5V
C161
+
470U_E
2.5V
C162
+
470U_E
2.5V
C360
+
330U_E
2.5V
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
1 8
2 7
3 6
4 5
8P4R-1K
R17
1K
12
Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-1512
Size Document Number Rev
B
401225
星期四 九月
D
Date: Sheet of
3 44, 12, 2002
E
1A
A
B
C
D
E
MC-1/3(GTL+,AGP,HUB)
HD#[0..63]2
1 1
2 2
DSTBN0#2
DSTBN1#2
DSTBN2#2
3 3
DSTBN3#2
DSTBP0#2
DSTBP1#2
DSTBP2#2
DSTBP3#2
DBI0#2
DBI1#2
DBI2#2
DBI3#2
CPU_VCC
4 4
HD#[0..63] HA#[3..31]
C81
.1UF
AC5
AD7
AC7
AC6
AC3
AC8
AG5
AG2
AH2
AG3
AH7
AH3
AG8
AG7
AG6
AH5
AC11
AC12
AC9
AE10
AD9
AG9
AC10
AE12
AF10
AG11
AG10
AH11
AG12
AE13
AF12
AG13
AH13
AC14
AF14
AG14
AE14
AG15
AG16
AG17
AH15
AC17
AF16
AE15
AH17
AD17
AE16
AD4
AE11
AC15
AD3
AD11
AC16
AD5
AG4
AH9
AD15
AA2
AB5
AA5
AB3
AB4
AA3
AA6
AE3
AB7
AE2
AE8
AF6
AF3
AE5
AF4
AF8
AE9
AE6
AE7
A
U22A
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
DBI0#
DBI1#
DBI2#
DBI3#
BROOKDALE
MCH_GTLREF
C82
.1UF
HOST
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
ADSTB0#
ADSTB1#
CPURST#
HLOCK#
DEFER#
HTRDY#
RCOMP0
RCOMP1
12
R63
49.9_1%
12
R56
100_1%
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
RS#0
RS#1
RS#2
BCLK#
BCLK
ADS#
BNR#
BPRI#
DBSY#
DRDY#
HIT#
HITM#
BR0#
SWNG0
SWNG1
HVREF
HVREF
HVREF
HVREF
HVREF
SWNG
T4
T5
T3
U3
R3
P7
R2
P4
R6
P5
P3
N2
N7
N3
K4
M4
M3
L3
L5
K3
J2
M5
J3
L2
H4
N5
G2
M6
L7
U6
T7
R7
U5
U2
W2
W7
W6
R5
N6
K8
J8
AE17
W5
Y4
V3
W3
Y7
V5
V4
Y5
Y3
U7
V7
AC2
AC13
AA7
AD13
M7
R8
Y8
AB11
AB17
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
RS#0
RS#1
RS#2
RCOMP0
RCOMP1
CPU_VCC
HA#[3..31] 2
RS#[0..2]
ADSTB0# 2
ADSTB1# 2
CLK_HMCH# 13
CLK_HMCH 13
CPURST# 2
HLOCK# 2
DEFER# 2
ADS# 2
BNR# 2
BPRI# 2
DBSY# 2
DRDY# 2
HIT# 2
HITM# 2
HTRDY# 2
BREQ0# 2
1 2
R270 22
R20 221 2
SWNG
MCH_GTLREF
12
R18
300_1%
12
R19
150_1%
HREQ#[0..4]
C43
0.01UF
B
HREQ#[0..4] 2
RS#[0..2] 2
PROPRIETARY NOTE
GPAR14
SBSTB14
RBF#14
1 2
R273 40.2_1%
C83
0.1UF
GAD[0..31]
GAD0
GAD1
GAD2
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31
GFRAME#
GDEVSEL#
GIRDY#
GTRDY#
GSTOP#
GPAR
GREQ#
GGNT#
PIPE#
AD_STB0
AD_STB0#
AD_STB1
AD_STB1#
SBSTB
SBSTB#
RBF#
WBF#
AGPREF
GRCOMP
CLK_66M_MCH
C116
0.1UF
U22C
R27
G_AD0
R28
G_AD1
T25
G_AD2
R25
G_AD3
T26
G_AD4
T27
G_AD5
U27
G_AD6
U28
G_AD7
V26
G_AD8
V27
G_AD9
T23
G_AD10
U23
G_AD11
T24
G_AD12
U24
G_AD13
U25
G_AD14
V24
G_AD15
Y27
G_AD16
Y26
G_AD17
AA28
G_AD18
AB25
G_AD19
AB27
G_AD20
AA27
G_AD21
AB26
G_AD22
Y23
G_AD23
AB23
G_AD24
AA24
G_AD25
AA25
G_AD26
AB24
G_AD27
AC25
G_AD28
AC24
G_AD29
AC22
G_AD30
AD24
G_AD31
V25
G_C/BE#0
V23
G_C/BE#1
Y25
G_C/BE#2
AA23
G_C/BE#3
Y24
G_FRAME#
W28
G_DEVSEL#
W27
G_IRDY#
W24
G_TRDY#
W23
G_STOP#
W25
G_PAR
AG24
G_REQ#
AH25
G_GNT#
AF22
PIPE#
R24
AD_STB0
R23
AD_STB#0
AC27
AD_STB1
AC28
AD_STB#1
AF27
SB_STB
AF26
SB_STB#
AE22
RBF#
AE23
WBF#
AA21
AGPREF
AD25
GRCOMP
AD26
NC
AD27
NC
P22
66IN
BROOKDALE
12
R347
10
12
C473
10PF
HUBREF
C110
C109
0.1UF
0.1UF
1 2
1 2
1 2
+1_8VS
12
12
AGP
HUB
R73
150_1%
1 2
R69
150_1%
D
TESTIN#
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HI10
HIREF
HISTB
HISTB#
HLRCOMP
SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
RSTIN#
C117
0.01UF
HI0
HI1
HI2
HI3
HI4
HI5
HI6
HI7
HI8
HI9
ST0
ST1
ST2
H26
G9
G10
G16
G17
H6
H7
J23
H27
K23
K25
J25
AC18
AC20
AC21
AC23
AC26
AD6
AD8
AD10
AD12
AD14
AD16
AD19
AD22
AE1
AE4
AE18
AE20
AE29
P25
HL0
HL1
P24
N27
HL2
HL3
P23
M26
HL4
HL5
M25
L28
HL6
HL7
L27
M27
HL8
HL9
N28
M24
HL10
HUBREF
P26
N25
HL_STB
HL_STB#
N24
P27
+GMCH_HLCOMP
AH28
SBA0
SBA1
AH27
AG28
SBA2
SBA3
AG27
AE28
SBA4
SBA5
AE27
AE24
SBA6
SBA7
AE25
ST0
AG25
AF24
ST1
ST2
AG26
J27
1 2
R315
0
ST0
ST1CLK_66M_MCH
GPAR
AD_STB0#
AD_STB1#
SBSTB#
GAD[0..31]14
GC/BE#014
GC/BE#114
GC/BE#214
GC/BE#314
GFRAME#14
GDEVSEL#14
GIRDY#14
GTRDY#14
GSTOP#14
GREQ#14
GGNT#14
AD_STB014
AD_STB0#14
AD_STB114
AD_STB1#14
SBSTB#14
AGPREF14
CLK_66M_MCH13
+1_5VS
12
R57
1K
AGPREF
12
R58
1K
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
HUBREF 10
HL_STB 10
1 2
R304
40.2_1%
R523 2K
R25 @2K
R285 100K
R299 6.8K
R277 6.8K
R275 6.8K
Title
Size Document Number Rev
B
Date: Sheet of
HL_STB# 10
+1_8VS
SBA[0..7]
HL[0..10]
ST0 14
ST1 14
ST2 14
PCIRST# 10,14,19,20,21,23,25,27,31,34
GTRDY#
GIRDY#
12
12
12
12
12
12
GDEVSEL#
GSTOP#
GFRAME#
GREQ#
GGNT#
SBSTB
RBF#
PIPE#
WBF#
AD_STB0
AD_STB1
SBSTB
ST1
Compal Electron ics, Inc.
SCHEMATIC, M/B LA-1512
401225
星期四 九月
E
SBA[0..7] 14
HL[0..10] 10
12
R289 6.8K
12
R281 6.8K
12
R279 6.8K
12
R292 6.8K
12
R278 6.8K
12
R269 6.8K
12
R268 6.8K
12
R272 @6.8K
12
R22 6.8K
12
R21 6.8K
12
R23 6.8K
12
R297 @6.8K
12
R276 @6.8K
12
R271 @6.8K
12
R24 @10K
4 44, 12, 2002
+1_5VS
1A
A
B
C
D
E
MCH-2/3(SDRAM)
G18
G19
G21
G20
G22
G12
G13
G25
G15
G14
G24
G11
G23
H23
C26
C23
D12
C16
D16
C14
C17
C15
D14
E12
F17
E16
E18
F19
F21
F13
E20
E14
F15
J24
G6
G7
E24
H5
F5
F11
G8
E22
F23
E9
F7
F9
E7
F26
B19
C8
C5
E3
E15
B15
B17
G3
H3
U22B
SMAA0
SMAA1
SMAA2
SMAA3
SMAA4
SMAA5
SMAA6
SMAA7
SMAA8
SMAA9
SMAA10
SMAA11
SMAA12
SBS0
SBS1
SCK0
SCK#0
SCK1
SCK#1
SCK2
SCK#2
SCK3
SCK#3
SCK4
SCK#4
SCK5
SCK#5
SRAS#
SCAS#
SWE#
SCKE0
SCKE1
SCKE2
SCKE3
SCS#0
SCS#1
SCS#2
SCS#3
SDQS0
SDQS1
SDQS2
SDQS3
SDQS4
SDQS5
SDQS6
SDQS7
SDQS8
SCB0
SCB1
SCB2
SCB3
SCB4
SCB5
SCB6
SCB7
RCVENIN#
RCVENOUT#
BROOKDALE
G28
F27
C28
E28
H25
G27
F25
B28
E27
C27
B25
C25
B27
D27
D26
E25
D24
E23
C22
E21
C24
B23
D22
B21
C21
D20
C19
D18
C20
E19
C18
E17
E13
C12
B11
C10
B13
C13
C11
D10
E10
C9
D8
E8
E11
B9
B7
C7
C6
D6
D4
B3
E6
B5
C4
E5
C3
D3
F4
F3
B2
C2
E2
G5
J28
J9
J21
DDR_SDQ0
DDR_SDQ1
DDR_SDQ2
DDR_SDQ3
DDR_SDQ4
DDR_SDQ5
DDR_SDQ6
DDR_SDQ7
DDR_SDQ8
DDR_SDQ9
DDR_SDQ10
DDR_SDQ11
DDR_SDQ12
DDR_SDQ13
DDR_SDQ14
DDR_SDQ15
DDR_SDQ16
DDR_SDQ17
DDR_SDQ18
DDR_SDQ19
DDR_SDQ20
DDR_SDQ21
DDR_SDQ22
DDR_SDQ23
DDR_SDQ24
DDR_SDQ25
DDR_SDQ26
DDR_SDQ27
DDR_SDQ28
DDR_SDQ29
DDR_SDQ30
DDR_SDQ31
DDR_SDQ32
DDR_SDQ33
DDR_SDQ34
DDR_SDQ35
DDR_SDQ36
DDR_SDQ37
DDR_SDQ38
DDR_SDQ39
DDR_SDQ40
DDR_SDQ41
DDR_SDQ42
DDR_SDQ43
DDR_SDQ44
DDR_SDQ45
DDR_SDQ46
DDR_SDQ47
DDR_SDQ48
DDR_SDQ49
DDR_SDQ50
DDR_SDQ51
DDR_SDQ52
DDR_SDQ53
DDR_SDQ54
DDR_SDQ55
DDR_SDQ56
DDR_SDQ57
DDR_SDQ58
DDR_SDQ59
DDR_SDQ60
DDR_SDQ61
DDR_SDQ62
DDR_SDQ63
SRCOMP
1 2
R525 0_0603
12
C7220.1U_0402_X7 R
1 2
R524 30_0603_1%
SMD0
SMD1
SMD2
SMD3
SMD4
SMD5
SMD6
SMD7
SMD8
SMD9
SMD10
SMD11
SMD12
SMD13
SMD14
SMD15
SMD16
SMD17
SMD18
SMD19
SMD20
SMD21
SMD22
SMD23
SMD24
SMD25
SMD26
SMD27
SMD28
SMD29
SMD30
SMD31
SMD32
SMD33
DDR-MEMORY
SMD34
SMD35
SMD36
SMD37
SMD38
SMD39
SMD40
SMD41
SMD42
SMD43
SMD44
SMD45
SMD46
SMD47
SMD48
SMD49
SMD50
SMD51
SMD52
SMD53
SMD54
SMD55
SMD56
SMD57
SMD58
SMD59
SMD60
SMD61
SMD62
SMD63
SRCOMP
SDREF
SDREF
DDR_SDQ[0..63]
SDREF
15mil
12mil
DDR_SDQ[0..63] 7
C630
1 2
0.1U_0402_X7 R
+1.25VS
C735
10UF_1206_6.3V
SDREF
+2.5V
VS
15mil
84
5
+
7
6
-
LM358
U60B
84
3
+
1
2
-
LM358
U60A
12
R560
C731
0.1UF_16V
R562
0
R563
0
12
12
12
100K_0.5%
R561
100K_0.5%
C732
0.01UF
12
1 1
2 2
3 3
DDR_SMA[0..12]7
DDR_CB[0..7]7
DDR_SMA[0..12]
DDR_SBS07
DDR_SBS17
DDR_CLK07
DDR_CLK0#7
DDR_CLK17
DDR_CLK1#7
DDR_CLK27
DDR_CLK2#7
DDR_CLK38
DDR_CLK3#8
DDR_CLK48
DDR_CLK4#8
DDR_CLK58
DDR_CLK5#8
DDR_SRAS#7
DDR_SCAS#7
DDR_SWE#7
DDR_CKE07
DDR_CKE17
DDR_CKE28
DDR_CKE38
DDR_SCS#07
DDR_SCS#17
DDR_SCS#28
DDR_SCS#38
DDR_SDQS07
DDR_SDQS17
DDR_SDQS27
DDR_SDQS37
DDR_SDQS47
DDR_SDQS57
DDR_SDQS67
DDR_SDQS77
DDR_SDQS87
DDR_CB[0..7]
Length
must equal
1.0"
DDR_SMA0
DDR_SMA1
DDR_SMA2
DDR_SMA3
DDR_SMA4
DDR_SMA5
DDR_SMA6
DDR_SMA7
DDR_SMA8
DDR_SMA9
DDR_SMA10
DDR_SMA11
DDR_SMA12
DDR_SBS0
DDR_SBS1
DDR_SRAS#
DDR_SCAS#
DDR_SWE#
DDR_CKE0
DDR_CKE1
DDR_CKE2
DDR_CKE3
DDR_SCS#0
DDR_SCS#1
DDR_SCS#2
DDR_SCS#3
DDR_SDQS0
DDR_SDQS1
DDR_SDQS2
DDR_SDQS3
DDR_SDQS4
DDR_SDQS5
DDR_SDQS6
DDR_SDQS7
DDR_SDQS8
DDR_CB0
DDR_CB1
DDR_CB2
DDR_CB3
DDR_CB4
DDR_CB5
DDR_CB6
DDR_CB7
RDCLK
C631
@10P_0402
1 2
4 4
Compal Electron ics, Inc.
Title
PROPRIETARY NOTE
A
B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
SCHEMATIC, M/B LA-1512
Size Document Number Rev
B
401225
星期四 九月
Date: Sheet of
5 44, 12, 2002
E
1A
A
B
C
D
E
MCH-3/3(Power)
U22D
+1_5VS
1 1
+1_8VS
+2.5V
2 2
3 3
CPU_VCC
4 4
A
R22
R29
U22
U26
W22
W29
AA22
AA26
AB21
AC29
AD21
AD23
AE26
AF23
AG29
AJ25
N14
N16
R14
R16
U14
U16
M22
N23
N26
C29
D11
D15
D19
D23
D25
G29
H10
H12
H14
H16
H18
H20
H22
H24
AB18
AB20
AC19
AD18
AD20
AE19
AE21
AF18
AF20
AG19
AG21
AG23
AJ19
AJ21
AJ23
AB19
AB22
AC1
AC4
AF21
AF25
AG1
AG18
AG20
AG22
AH19
AH21
AH23
AJ27
P13
P15
P17
T15
L25
L29
A5
A9
A13
A17
A21
A25
C1
D7
F6
F10
F14
F18
F22
G1
G4
H8
J5
J7
K6
K22
K24
K26
L23
M8
U8
AA9
AB8
AJ3
AJ5
AJ7
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
BROOKDALE
POWER/GND
B
VCC1_5
VCC1_5
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDGND
VCCA0
T13
T17
VCCA1
U13
VSSA0
VSS
VSSA1
U17
VSS
A3
A7
A11
A15
A19
A23
A27
D5
D9
D13
D17
D21
E1
E4
E26
E29
F8
F12
F16
F20
F24
G26
H9
H11
H13
H15
H17
H19
H21
J1
J4
J6
J22
J26
J29
K5
K7
K27
L1
L4
L6
L8
L22
L24
L26
M23
N1
N4
N8
N13
N15
N17
N22
N29
P6
P8
P14
P16
R1
R4
R13
R15
R17
R26
T6
T8
T14
T16
T22
U1
U4
U15
U29
V6
V8
V22
W1
W4
W8
W26
Y6
Y22
AA1
AA4
AA8
AA29
AB6
AB9
AB10
AB12
AB13
AB14
AB15
AB16
AF5
AF7
AF9
AF11
AF13
AF15
AF17
AF19
AJ9
AJ11
AJ13
AJ15AJ17
VCCA0
VSSA0
VCCA1
VSSA1
PROPRIETARY NOTE
1 2
L31 4.7UH_0805
+
C391
33U_D
1 2
L26 4.7UH_0805
+
C378
33U_D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
12
+
C
C86
150UF_E
6.3V
+1_5VS
+1_5VS
CPU_VCC
C42
+
22UF_10V_1206
+2.5V
12
+
+1_5VS
C92
+
22UF_10V_1206
C425
150UF_E
6.3V
.1UF_0402
C123
4.7UF_0805
.1UF_0402
C47
C101
C46
.1UF_0402
C153
.1UF_0402
C95
.1UF_0402
+1_8VS
+
C94
22UF_10V_1206
C48
.1UF_0402
C152
.1UF_0402
C108
.1UF_0402
C68
.1UF_0402
C126
.1UF_0402
C91
.1UF_0402
C120
.1UF_0402
C149
.1UF_0402
D
C57
.1UF_0402
.1UF_0402
C112
.1UF_0402
C114
.1UF_0402
C56
.1UF_0402
C125
C111
.1UF_0402
C113
.1UF_0402
.1UF_0402
C151
.1UF_0402
.1UF_0402
C115
C121
.1UF_0402
.1UF_0402
C59
C69
.1UF_0402
C154
C122
.1UF_0402
C100
C90
.1UF_0402
Title
Size Document Number Rev
B
Date: Sheet of
C124
.1UF_0402
.1UF_0402
Compal Electron ics, Inc.
SCHEMATIC, M/B LA-1512
401225
星期四 九月
C127
.1UF_0402
.1UF_0402
E
C150
C134
.1UF_0402
6 44, 12, 2002
C144
.1UF_0402
1A
A
DDR_SDQ0
DDR_SDQ4
DDR_SDQ5
DDR_SDQ1
DDR_SDQS0
1 1
Layout note
Place these resistor
closely DIMM0,
all trace length<750mil
2 2
3 3
DDR_SDQ[0..63]5
DDR_SDQS[0..8]5
4 4
A
DDR_SDQ6
DDR_SDQ3
DDR_SDQ2
DDR_SDQ7
DDR_SDQ8
DDR_SDQ13
DDR_SDQ12
DDR_SDQ15
DDR_SDQS1
DDR_SDQ9
DDR_SDQ11
DDR_SDQ14
DDR_SDQ10
DDR_SDQ16
DDR_SDQ20
DDR_SDQ21
DDR_SDQ17
DDR_SDQS2
DDR_SDQ18
DDR_SDQ23
DDR_SDQ22
DDR_SDQ19
DDR_SDQ24
DDR_SDQ29
DDR_SDQ25
DDR_SDQ28
DDR_SDQS3
DDR_SDQ[0..63]
DDR_CB[0..7]5
DDR_CB[0..7]
DDR_SDQS[0..8]
DDR_SDQ51
DDR_SDQ59
DDR_SDQ63
DDR_SDQ58
DDR_SDQ62
DDR_SDQS7
DDR_SDQ57
DDR_SDQ61
DDR_SDQ60 DDR_DQ60
DDR_SDQ56 DDR_DQ56
B
RP53 4P2R_33
1 4
2 3
RP55 4P2R_33
1 4
2 3
RP57 4P2R_33
1 4
2 3
RP60 4P2R_33
1 4
2 3
RP63 4P2R_33
1 4
2 3
RP66 4P2R_33
1 4
2 3
RP69 4P2R_33
1 4
2 3
RP72 4P2R_33
1 4
2 3
RP75 4P2R_33
1 4
2 3
RP77 4P2R_33
1 4
2 3
RP79 4P2R_33
1 4
2 3
RP81 4P2R_33
1 4
2 3
RP83 4P2R_33
1 4
2 3
RP85 4P2R_33
1 4
2 3
RP87 4P2R_33
1 4
2 3
RP90 4P2R_33
1 4
2 3
RP95 4P2R_33
1 4
2 3
RP97 4P2R_33
1 4
2 3
RP99 4P2R_33
1 4
2 3
RP101 4P2R_33
1 4
2 3
RP103 4P2R_33
1 4
2 3
B
DDR_DQ0
DDR_DQ4
DDR_DQ5
DDR_DQ1
DDR_DQS0
DDR_DQ6
DDR_DQ3
DDR_DQ2
DDR_DQ7
DDR_DQ8
DDR_DQ13
DDR_DQ12
DDR_DQ15
DDR_DQS1
DDR_DQ9
DDR_DQ11
DDR_DQ14
DDR_DQ10
DDR_DQ16
DDR_DQ20
DDR_DQ21
DDR_DQ17
DDR_DQS2
DDR_DQ18
DDR_DQ23
DDR_DQ22
DDR_DQ19
DDR_DQ24
DDR_DQ29
DDR_DQ25
DDR_DQ28
DDR_DQS3
DDR_DQ51
DDR_DQ59
DDR_DQ63
DDR_DQ58
DDR_DQ62
DDR_DQS7
DDR_DQ57
DDR_DQ61
DDR_SDQ26
DDR_SDQ27
DDR_SDQ30
DDR_SDQ31
DDR_CB5
DDR_CB4
DDR_CB0
DDR_CB2
DDR_SDQS8
DDR_CB6
DDR_CB1
DDR_CB7
DDR_CB3
DDR_SDQ32
DDR_SDQ36
DDR_SDQ37
DDR_SDQ33
DDR_SDQS4
DDR_SDQ39
DDR_SDQ38
DDR_SDQ34
DDR_SDQ44
DDR_SDQ35
DDR_SDQ40
DDR_SDQ41
DDR_SDQ45
DDR_SDQS5
DDR_SDQ42
DDR_SDQ43
DDR_SDQ47
DDR_SDQ46
DDR_SDQ52
DDR_SDQ49
DDR_SDQ48
DDR_SDQ53
DDR_SDQS6
DDR_SDQ55
DDR_SDQ50
DDR_SDQ54
C
RP54 4P2R_33
1 4
2 3
RP56 4P2R_33
1 4
2 3
RP58 4P2R_33
1 4
2 3
RP61 4P2R_33
1 4
2 3
RP64 4P2R_33
1 4
2 3
RP67 4P2R_33
1 4
2 3
RP70 4P2R_33
1 4
2 3
RP73 4P2R_33
1 4
2 3
RP76 4P2R_33
1 4
2 3
RP78 4P2R_33
1 4
2 3
RP80 4P2R_33
1 4
2 3
RP82 4P2R_33
1 4
2 3
RP84 4P2R_33
1 4
2 3
RP86 4P2R_33
1 4
2 3
RP88 4P2R_33
1 4
2 3
RP91 4P2R_33
1 4
2 3
RP93 4P2R_33
1 4
2 3
RP94 4P2R_33
1 4
2 3
RP96 4P2R_33
1 4
2 3
RP98 4P2R_33
1 4
2 3
C
DDR_DQ26
DDR_DQ27
DDR_DQ30
DDR_DQ31
DDR_F_CB5
DDR_F_CB4
DDR_F_CB0
DDR_F_CB2
DDR_DQS8
DDR_F_CB6
DDR_F_CB1
DDR_F_CB7
DDR_F_CB3
DDR_DQ32
DDR_DQ36
DDR_DQ37
DDR_DQ33
DDR_DQS4
DDR_DQ39
DDR_DQ38
DDR_DQ34
DDR_DQ44
DDR_DQ35
DDR_DQ40
DDR_DQ41
DDR_DQ45
DDR_DQS5
DDR_DQ42
DDR_DQ43
DDR_DQ47
DDR_DQ46
DDR_DQ52
DDR_DQ49
DDR_DQ48
DDR_DQ53
DDR_DQS6
DDR_DQ55
DDR_DQ50
DDR_DQ54
D
DDR_DQ4
DDR_DQ5
DDR_DQS0
DDR_DQ3
DDR_DQ7
DDR_DQ12
DDR_DQ15
DDR_DQS1
DDR_DQ11
DDR_DQ10
DDR_CLK15
DDR_CLK1#5
DDR_DQ20
DDR_DQ17
DDR_DQS2
DDR_DQ22
DDR_DQ19
DDR_DQ25
DDR_DQ28
DDR_DQS3
DDR_DQ27
DDR_DQ31
DDR_F_CB4
DDR_F_CB2
DDR_DQS8
DDR_F_CB7
DDR_F_CB3
DDR_CLK05
DDR_CLK0#5
DDR_CKE15
DDR_SCS#05
DDR_CKE1
DDR_F_SMA12
DDR_F_SMA9
DDR_F_SMA7
DDR_F_SMA5
DDR_F_SMA3
DDR_F_SMA1
DDR_F_SMA10
DDR_F_SBS0
DDR_F_SWE#
DDR_SCS#0
DDR_DQ36
DDR_DQ33
DDR_DQS4
DDR_DQ39
DDR_DQ38
DDR_DQ44
DDR_DQ40
DDR_DQS5
DDR_DQ43
DDR_DQ47
DDR_DQ52
DDR_DQ48
DDR_DQS6
DDR_DQ55
DDR_DQ50
DDR_DQ59
DDR_DQ63
DDR_DQS7
DDR_DQ57
DDR_DQ60
DIMM_SMDATA8,13
DIMM_SMCLK8,13
E
+2.5V +2.5V
JP29
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0#
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2#
93
VDD
95
CKE1
97
DU/A13
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE#
121
S0#
123
DU
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
+3VS
197
VDD_SPD
199
VDD_ID
DDR-SODIMM_200_Normal
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
DU/RESET#
VSS
VSS
VDD
VDD
CKE0
DU/BA2
A11
VSS
VDD
BA1
RAS#
CAS#
S1#
DU
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1#
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
DU
F
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
A8
104
106
A6
108
A4
110
A2
112
A0
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DDR_DQ0
DDR_DQ1
DDR_DQ6
DDR_DQ2
DDR_DQ8
DDR_DQ13
DDR_DQ9
DDR_DQ14
DDR_DQ16
DDR_DQ21
DDR_DQ18
DDR_DQ23
DDR_DQ24
DDR_DQ29
DDR_DQ26
DDR_DQ30
DDR_F_CB5
DDR_F_CB0
DDR_F_CB6
DDR_F_CB1
DDR_CKE0
DDR_F_SMA11
DDR_F_SMA8
DDR_F_SMA6
DDR_F_SMA4
DDR_F_SMA2
DDR_F_SMA0
DDR_F_SBS1
DDR_F_SRAS#
DDR_F_SCAS#
DDR_SCS#1
DDR_DQ32
DDR_DQ37
DDR_DQ34
DDR_DQ35
DDR_DQ41
DDR_DQ45
DDR_DQ42
DDR_DQ46
DDR_DQ49
DDR_DQ53
DDR_DQ54
DDR_DQ51
DDR_DQ58
DDR_DQ62
DDR_DQ61
DDR_DQ56
DIMM0(STD)
Top side
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
D
E
F
SDREF_DIMM
12
C632
.1UF_0402
G
R526
DDR_DQ[0..63]
DDR_F_CB[0..7]
DDR_DQS[0..8]
12
SDREF
0_0402
DDR_SMA[0..12] 5
DDR_SMA12
DDR_SMA9
DDR_SMA8
DDR_SMA11
DDR_SMA7
DDR_SMA5
DDR_SMA4
DDR_SMA6
DDR_SMA3
DDR_SMA1
DDR_SMA0
DDR_SMA2
DDR_SMA10 DDR_F_SMA10
H
DDR_DQ[0..63] 8
DDR_F_CB[0..7] 8
DDR_DQS[0..8] 8
RP59 4P2R_0
1 4
2 3
RP62 4P2R_0
1 4
2 3
RP65 4P2R_0
1 4
2 3
RP68 4P2R_0
1 4
2 3
RP71 4P2R_0
1 4
2 3
RP74 4P2R_0
1 4
2 3
R527 0_0402
1 2
DDR_F_SMA[0..12]8
DDR_F_SMA12
DDR_F_SMA9
DDR_F_SMA8
DDR_F_SMA11
DDR_F_SMA7
DDR_F_SMA5
DDR_F_SMA4
DDR_F_SMA6
DDR_F_SMA3
DDR_F_SMA1
DDR_F_SMA0
DDR_F_SMA2
Layout note
DDR_CKE0 5
Place these resistor
closely DIMM0,
all trace length<=750mil
Layout note
Place these resistor
closely DIMM0,
DDR_SCS#1 5
DDR_CLK2# 5
DDR_CLK2 5
R528 0_0402
DDR_SBS15
DDR_SBS05
DDR_SWE#5
DDR_SCAS#5
DDR_SRAS#5
DDR_SBS1 DDR_F_SBS1
RP100 4P2R_0
DDR_SBS0
DDR_SWE#
RP102 4P2R_0
DDR_SCAS#
DDR_SRAS# DDR_F_SRAS#
Title
Size Document Number Rev
401225
星期四 九月
Date: Sheet of
G
all trace length Max=1.3"
DDR_CKE1
DDR_CKE0
DDR_SCS#0
DDR_SCS#1
Layout note
Place these resistor
closely DIMM0,
all trace
length<=750mil
1 2
1 4
DDR_F_SBS0
DDR_F_SWE#
2 3
DDR_F_SCAS#
1 4
2 3
Compal Electron ics, Inc.
SCHEMATIC, M/B LA-1 512
RP89 4P2R_47
1 4
2 3
RP92 4P2R_47
1 4
2 3
DDR_F_SBS1 8
DDR_F_SBS0 8
DDR_F_SWE# 8
DDR_F_SCAS# 8
DDR_F_SRAS# 8
7 44, 12, 2002
H
+1.25VS
1A
A
+1.25VS +1.25VS
RP104 4P2R_47
DDR_DQ4
1 4
2 3
RP107 4P2R_47
1 4
DDR_DQ5
DDR_DQ1
2 3
DDR_DQS0
DDR_DQ6
DDR_DQ3
DDR_DQ2
DDR_DQ7
DDR_DQ8
DDR_DQ12
DDR_DQ13
DDR_DQS1
DDR_DQ15
DDR_DQ11
DDR_DQ9
DDR_DQ10
DDR_DQ14
DDR_DQ20
DDR_DQ16
DDR_DQ17
DDR_DQ21
DDR_DQ18
DDR_DQS2
DDR_DQ22
DDR_DQ23
DDR_DQ19
DDR_DQ24
DDR_DQ25
DDR_DQ29
DDR_DQS3
DDR_DQ28
RP110 4P2R_47
1 4
2 3
RP114 4P2R_47
1 4
2 3
RP118 4P2R_47
1 4
2 3
RP122 4P2R_47
1 4
2 3
RP126 4P2R_47
1 4
2 3
RP130 4P2R_47
1 4
2 3
RP134 4P2R_47
1 4
2 3
RP137 4P2R_47
1 4
2 3
RP140 4P2R_47
1 4
2 3
RP143 4P2R_47
1 4
2 3
RP145 4P2R_47
1 4
2 3
RP147 4P2R_47
1 4
2 3
RP149 4P2R_47
1 4
2 3
RP151 4P2R_47
1 4
2 3
1 1
2 2
3 3
RP105 4P2R_47
DDR_DQ27
14
23
DDR_DQ26
RP108 4P2R_47
14
DDR_DQ31
DDR_DQ30
23
RP111 4P2R_47
DDR_F_CB4
14
23
DDR_F_CB5
RP115 4P2R_47
14
DDR_F_CB2
DDR_F_CB0
23
RP119 4P2R_47
DDR_F_CB6
14
23
DDR_DQS8
RP123 4P2R_47
14
DDR_F_CB1
DDR_F_CB7
23
RP127 4P2R_47
14
23
DDR_F_CB3
RP131 4P2R_47
14
DDR_DQ36
DDR_DQ32
23
RP135 4P2R_47
DDR_DQ37
14
23
DDR_DQ33
RP138 4P2R_47
14
DDR_DQ39
DDR_DQS4
23
RP141 4P2R_47
DDR_DQ38
14
23
DDR_DQ34
RP144 4P2R_47
14
DDR_DQ35
DDR_DQ44
23
RP146 4P2R_47
DDR_DQ41
14
23
DDR_DQ40
RP148 4P2R_47
14
DDR_DQS5
DDR_DQ45
23
RP150 4P2R_47
DDR_DQ42
14
23
DDR_DQ43
RP152 4P2R_47
14
DDR_DQ46
DDR_DQ47
23
RP106 4P2R_47
DDR_DQ49
14
23
DDR_DQ52
RP109 4P2R_47
14
DDR_DQ53
DDR_DQ48
23
RP112 4P2R_47
DDR_DQ55
14
23
DDR_DQS6
RP116 4P2R_47
14
DDR_DQ54
DDR_DQ50
23
RP120 4P2R_47
14
DDR_DQ51
DDR_DQ59
23
RP124 4P2R_47
DDR_DQ58
14
23
DDR_DQ63
RP128 4P2R_47
14
DDR_DQ62
DDR_DQS7
23
RP132 4P2R_47
DDR_DQ61
14
23
DDR_DQ57
RP136 4P2R_47
14
DDR_DQ56
DDR_DQ60
23
Layout note
Place these resistor
closely DIMM1,
all trace
length<=800mil
4 4
B
DDR_F_CB[0..7] 7
DDR_DQ[0..63]DDR_DQ0
DDR_DQS[0..8] 7
DDR_DQ[0..63] 7
DDR_F_SMA[0..12] 7
C
DDR_CLK45
DDR_CLK4 #5
DDR_CLK35
DDR_CLK3 #5
DDR_F_SBS07
DDR_F_SWE#7
DIMM_SMDATA7,13
DIMM_SMCLK7,13
+2.5V +2.5V
JP30
1
VREF
3
VSS
DDR_DQ0 DDR_DQ4
DDR_DQ1
DDR_DQS0
DDR_DQ6
DDR_DQ2
DDR_DQ8
DDR_DQ13
DDR_DQS1
DDR_DQ9
DDR_DQ14
DDR_DQ16
DDR_DQ21
DDR_DQS2
DDR_DQ18
DDR_DQ23
DDR_DQ24
DDR_DQ29
DDR_DQS3
DDR_DQ26
DDR_DQ30
DDR_F_CB5
DDR_F_CB0 DDR_F_CB2
DDR_DQS8
DDR_F_CB6
DDR_F_CB1
DDR_CKE3 DDR_CKE2
DDR_F_SMA12
DDR_F_SMA9
DDR_F_SMA7
DDR_F_SMA5
DDR_F_SMA3
DDR_F_SMA1
DDR_F_SMA10
DDR_F_SBS0
DDR_F_SWE#
DDR_SCS#2 DDR_SCS#3
DDR_DQ32
DDR_DQ37
DDR_DQS4
DDR_DQ34
DDR_DQ35
DDR_DQ41
DDR_DQ45
DDR_DQS5
DDR_DQ42
DDR_DQ46
DDR_DQ49
DDR_DQ53
DDR_DQS6
DDR_DQ54
DDR_DQ51
DDR_DQ58
DDR_DQ62
DDR_DQS7
DDR_DQ61
DDR_DQ56
+3VS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0#
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2#
93
VDD
95
CKE1
97
DU/A13
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE#
121
S0#
123
DU
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
VDD_SPD
199
VDD_ID
DDR-SODIMM_200_Reverse
DIMM1(REV)
Bottem side
D
VREF
DQ12
DQ13
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQ30
DQ31
DU/RESET#
CKE0
DU/BA2
RAS#
CAS#
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQ46
DQ47
CK1#
DQ52
DQ53
DQ54
DQ55
DQ60
DQ61
DQ62
DQ63
DQ4
DQ5
VDD
DM0
DQ6
DQ7
VDD
DM1
VDD
VDD
VDD
DM2
VDD
DM3
VDD
CB4
CB5
DM8
CB6
VDD
CB7
VDD
VDD
VDD
VDD
DM4
VDD
DM5
VDD
CK1
VDD
DM6
VDD
DM7
VDD
E
+3VS
SDREF_DIMM
12
DDR_CKE2 5DDR_CKE35
DDR_F_SBS1 7
DDR_F_SRAS# 7
DDR_F_SCAS# 7
DDR_SCS#3 5DDR_SCS#25
DDR_CLK5# 5
DDR_CLK5 5
C633
.1UF_0402
+1.25VS
RP113 4P2R_56
14
DDR_F_SMA9
DDR_F_SMA12
23
RP117 4P2R_56
DDR_F_SMA8
14
23
DDR_F_SMA11
RP121 4P2R_56
14
DDR_F_SMA5
DDR_F_SMA7
23
RP125 4P2R_56
DDR_F_SMA6
14
23
DDR_F_SMA4
RP129 4P2R_56
14
DDR_F_SMA1
DDR_F_SMA3
23
RP133 4P2R_56
DDR_F_SMA2
14
23
DDR_F_SMA0
R529 56_0402
1 2
DDR_F_SMA10
RP139 4P2R_56
14
DDR_F_SWE#
DDR_F_SBS0
23
RP142 4P2R_56
DDR_F_SRAS#
14
23
DDR_F_SCAS#
R530 56_0402
1 2
DDR_F_SBS1
RP153 4P2R_47
1 4
DDR_CKE2
DDR_CKE3
2 3
RP154 4P2R_47
DDR_SCS#2
1 4
2 3
DDR_SCS#3
Layout note
Place these resistor
closely DIMM1,
all trace length
Max=1.3"
+1.25VS
2
4
VSS
6
8
10
12
14
16
VSS
18
20
22
24
26
28
VSS
30
32
34
36
38
VSS
40
VSS
42
44
46
48
50
52
VSS
54
56
58
60
62
64
VSS
66
68
70
72
74
76
VSS
78
80
82
84
86
88
VSS
90
VSS
92
94
96
98
100
A11
102
A8
104
VSS
106
A6
108
A4
110
A2
112
A0
114
116
BA1
118
120
122
S1#
124
DU
126
VSS
128
130
132
134
136
138
VSS
140
142
144
146
148
150
VSS
152
154
156
158
160
162
VSS
164
166
168
170
172
174
VSS
176
178
180
182
184
186
VSS
188
190
192
194
SA0
196
SA1
198
SA2
200
DU
DDR_DQ5
DDR_DQ3
DDR_DQ7
DDR_DQ12
DDR_DQ15
DDR_DQ11
DDR_DQ10
DDR_DQ20
DDR_DQ17
DDR_DQ22
DDR_DQ19
DDR_DQ25
DDR_DQ28
DDR_DQ27
DDR_DQ31
DDR_F_CB4
DDR_F_CB7
DDR_F_CB3
DDR_F_SMA11
DDR_F_SMA8
DDR_F_SMA6
DDR_F_SMA4
DDR_F_SMA2
DDR_F_SMA0
DDR_F_SBS1
DDR_F_SRAS#
DDR_F_SCAS#
DDR_DQ36
DDR_DQ33
DDR_DQ39
DDR_DQ38
DDR_DQ44
DDR_DQ40
DDR_DQ43
DDR_DQ47
DDR_DQ52
DDR_DQ48
DDR_DQ55
DDR_DQ50
DDR_DQ59
DDR_DQ63
DDR_DQ57
DDR_DQ60
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
A
B
C
D
Title
Size Document Number Rev
Date: Sheet of
Compal Electron ics, Inc.
SCHEMATIC, M/B LA-1 512
401225
星期四 九月
8 44, 12, 2002
E
1A
A
Layout note :
Distribute as close as possible
to DDR-SODIMM.
B
C
D
E
+2.5V
1 1
12
C651
.1UF_0402_X5R
12
C652
.1UF_0402_X5R
12
C653
.1UF_0402_X5R
12
C654
.1UF_0402_X5R
12
C655
.1UF_0402_X5R
12
C656
.1UF_0402_X5R
12
C657
.1UF_0402_X5R
12
C658
.1UF_0402_X5R
12
C659
.1UF_0402_X5R
+2.5V +2.5V
12
C660
.1UF_0402_X5R
Layout note :
Place one cap close to every 2 pull up resistors termination to
+1.25V
2 2
+1.25VS
12
C668
.1UF_0402_X5R
12
C661
.1UF_0402_X5R
12
C669
.1UF_0402_X5R
12
C662
.1UF_0402_X5R
12
C670
.1UF_0402_X5R
12
C663
.1UF_0402_X5R
12
C671
.1UF_0402_X5R
12
C664
.1UF_0402_X5R
12
C672
.1UF_0402_X5R
12
C665
.1UF_0402_X5R
12
C673
.1UF_0402_X5R
12
+
C666
150UF_D2_6.3V
12
C674
.1UF_0402_X5R
12
+
C667
150UF_D2_6.3V
12
C675
.1UF_0402_X5R
12
C676
.1UF_0402_X5R
12
C677
.1UF_0402_X5R
+1.25VS
12
C678
.1UF_0402_X5R
12
C679
.1UF_0402_X5R
12
C680
.1UF_0402_X5R
12
C681
.1UF_0402_X5R
12
C682
.1UF_0402_X5R
12
C683
.1UF_0402_X5R
12
C684
.1UF_0402_X5R
12
C685
.1UF_0402_X5R
12
C686
.1UF_0402_X5R
12
C687
.1UF_0402_X5R
+1.25VS
12
C688
3 3
.1UF_0402_X5R
12
C689
.1UF_0402_X5R
12
C690
.1UF_0402_X5R
12
C691
.1UF_0402_X5R
12
C692
.1UF_0402_X5R
12
C693
.1UF_0402_X5R
12
C694
.1UF_0402_X5R
12
C695
.1UF_0402_X5R
12
C696
.1UF_0402_X5R
12
C697
.1UF_0402_X5R
+1.25VS
12
C698
.1UF_0402_X5R
12
C699
.1UF_0402_X5R
12
C700
.1UF_0402_X5R
12
C701
.1UF_0402_X5R
12
C702
.1UF_0402_X5R
12
C703
.1UF_0402_X5R
12
C704
.1UF_0402_X5R
12
C705
.1UF_0402_X5R
12
C706
.1UF_0402_X5R
12
C707
.1UF_0402_X5R
+1.25VS
12
C708
.1UF_0402_X5R
12
C709
.1UF_0402_X5R
12
C710
.1UF_0402_X5R
12
C711
.1UF_0402_X5R
12
C712
.1UF_0402_X5R
12
C713
.1UF_0402_X5R
12
C714
.1UF_0402_X5R
12
C715
.1UF_0402_X5R
12
C716
.1UF_0402_X5R
12
C717
.1UF_0402_X5R
+1.25VS
4 4
12
C718
4.7UF_10V_0805
12
C719
4.7UF_10V_0805
A
12
+
C720
150UF_D2_6.3V
12
C721
.1UF_0402_X5R
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
B
C
D
Title
Size Document Number Rev
Date: Sheet of
Compal Electron ics, Inc.
SCHEMATIC, M/B LA-1 512
401225
星期四 九月
9 44, 12, 2002
1A
E
A
1 1
B
C
D
AD[0..31]19,20,23
2 2
C/BE#019,20,23
C/BE#119,20,23
C/BE#219,20,23
C/BE#319,20,23
DEVSEL#19,20,23
FRAME#19,20,23
TRDY#19,20,23
PCIRST#4,14,19,20,21,23,25,27,31,34
PLOCK#20
SERR#19,20,23
PCI Pullups
3 3
+3VS
+3VS
PERR#
REQA#
STOP#
SERR#
IRDY#
TRDY#
FRAME#
RP35
1
2
3
4
5
10P8R-8.2K
RP34
1
2
3
4
5
10P8R-8.2K
10
9
8
7
6
10
9
8
7
6
PIRQA#
PIRQB#
REQ#4
PIRQC#
PIRQD#DEVSEL#
SIRQ
PLOCK#
+3VS
+3VS
PERR#19,20,23
PME# has internal PU
PIDERST#25
PCLK_ICH13
REQ#0
REQ#1
REQ#2
REQ#3
REQ#4
+3VS
RP37
1 8
4 4
2 7
3 6
4 5
8P4R-8.2K
1 2
R350 8.2K
1 2
R349 @1K
REQ#0
REQ#1
REQ#2
REQ#3
GPI1
GNTA#
GNTA# Strapping for "A16 swap override" : "0" -> Enable
A
AD[0..31]
DEVSEL#
FRAME#
IRDY#19,20,23
STOP#19,20,23
REQ#023
REQ#219
REQ#320
IRDY#
TRDY#
STOP#
PAR19,20,23
PCIRST#
PLOCK#
SERR#
PERR#
REQA#
GNTA#
PCLK_ICH
REQ#0
REQ#1
REQ#2
REQ#3
REQ#4
GPI1
PCI REQ ASSIGMENT
WLAN
NC
1394
PCMCIA CONTROLLER
NC
B
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
PROPRIETARY NOTE
ICH-2
(FW82801BA)
U33A
AA4
AD0
AB4
AD1
Y4
AD2
W5
AD3
W4
AD4
Y5
AD5
AB3
AD6
AA5
AD7
AB5
AD8
Y3
AD9
W6
AD10
W3
AD11
Y6
AD12
Y2
AD13
AA6
AD14
Y1
AD15
V2
AD16
AA8
AD17
V1
AD18
AB8
AD19
U4
AD20
W9
AD21
U3
AD22
Y9
AD23
U2
AD24
AB9
AD25
U1
AD26
W10
AD27
T4
AD28
Y10
AD29
T3
AD30
AA10
AD31
AA3
C/BE0#
AB6
C/BE1#
Y8
C/BE2#
AA9
C/BE3#
AB7
DEVSEL#
V3
FRAME#
W8
IRDY#
V4
TRDY#
W1
STOP#
W2
PAR
AA15
PCIRST#
AA7
PLOCK#
W7
SERR#
Y7
PERR#
Y15
PME#
M3
GPI0/REQA#
L2
GPO16/GNTA#
W11
PCICLK
R2
REQ0#
R3
REQ1#
T1
REQ2#
AB10
REQ3#
P4
REQ4#
L3
GPI1/REQB#/REQ5#
ICH-2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCI
PCLK_ICH
CPU
HUB
IRQ
GPO17/GNTB#/GNT5#
12
12
A20M#
CPUSLP#
FERR#
IGNNE#
INIT#
INTR
NMI
SMI#
STPCLK#
RCIN#
A20GATE
CPUPWRGD
HL0
HL1
HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9
HL10
HL11
HL_STB
HL_STB#
HLCOMP
HUBREF
PIRQA#
PIRQB#
PIRQC#
PIRQD#
IRQ14
IRQ15
APICCLK
APICD0
APICD1
SERIRQ
GPI2/PIRQE#
GPI3/PIRQF#
GPI4/PIRQG#
GPI5/PIRQH#
GNT0#
GNT1#
GNT2#
GNT3#
GNT4#
R154
@33
C222
@22PF
D11
A12
R22
FERR#
A11
C12
CPUINIT#
C11
B11
SMI#
B12
C10
STPCLK#
RC#
B13
C13
GATEA20
CPU_PWRGD
A13
A4
HL0
HL1
B5
A5
HL2
HL3
B6
B7
HL4
HL5
A8
B8
HL6
HL7
A9
C8
HL8
HL9
C6
C7
HL10
HL11
C5
A6
HL_STB
HL_STB#
A7
A3
+ICH_HLCOMP
HUBREF
B4
P1
PIRQA#
PIRQB#
P2
P3
PIRQC#
PIRQD#
N4
F21
IRQ14
IRQ15
C16
N20
CLK_APIC_ICH
PICD0
P22
N19
PICD1
SIRQ
N21
GPI2
N3
N2
GPI3
GPI4
N1
M4
GPI5
PIN N3, M4 can not use GPIO.
M2
GNT#0
M1
R4
GNT#2
GNT#3
T2
R1
SIDERST#
L4
1 2
R383 0
C484 .1UF
C
HL_STB 4
HL_STB# 4
12
HUBREF 4
PIRQA# 14,20,23
PIRQB# 20
PIRQC# 19
PIRQD# 23
IRQ14 25
IRQ15 24
SIRQ 20,27,31
GNT#0 23
GNT#2 19
GNT#3 20
SIDERST# 25
HL[0..10]
SB_A20M# 2
CPUSLP# 2
FERR# 2
SB_IGNNE# 2
CPUINIT# 2
SB_INTR 2
SB_NMI 2
SMI# 2
STPCLK# 2
RC# 31
GATEA20 31
CPU_PWRGD 2
HL[0..10] 4
+1_8VS
D
1 2
R357 @10K
1 2
R354 40.2_1%
1 2
R351 @8.2K
1 2
R410 10K
1 2
R390 10K
RP36
1 8
2 7
3 6
4 5
8P4R-100K
12
R414 10K
12
R409 10K
1 2
R415 0
10 44, 12, 2002
+3VS
HL11
+ICH_HLCOMP
SIDERST#
IRQ14
IRQ15
GPI4
GPI3
GPI2
GPI5
PICD0
PICD1
CLK_APIC_ICH
Compal Electron ics, Inc.
Title
SCHEMATIC, M/B LA-1512
Size Document Number Rev
B
401225
星期四 九月
Date: Sheet of
1A
A
1 2
+3V
R403 10K
21
LLBATT#31
D38 RB751V
1 2
+3V
ON/OFF31,34
+3V
ACIN31,34,36,39
+3V
ECSMI#31
+3V
ECSCI#31
+3V
+RTCVCC
1 2
INTRUDER#
SMLINK0
SMLINK1
OVCUR#2
VGATE
CLKRUN#
LDRQ#1
DSCACHE#
ICH_AC_SDOUT
RSMRST#
IAC_BITCLK
IAC_SDATAI
IAC_SDATAI1
SPKR
R380 10K
D34 RB751V
D22 RB751V
D21 @RB751V
1 2
R388 10K
D36 RB751V
1 2
R370 10K
D33 RB751V
1 2
R362 10K
1 2
R384 10K
D35 RB751V
R190
1 2
15K
1UF_25V_0805
R191
1K
EC_LID_OUT#31
PBTN_OUT#31
1 1
EC_RIOUT#31
2 2
+RTCVCC
1 2
R183 10K
+3V
3 3
1 2
R175 10K
1 2
R184 10K
1 2
R178 10K
+3VS
1 2
R386 100K
1 2
R436 10K
1 2
R356 @10K
12
R355 10K
1 2
R179 @10K
AC_SDOUT Strapping: "1" -> Safe Mode Boot
4 4
R168 100K
R169 10K
R404 10K
R405 10K
R407 1K
12
12
12
12
12
SPKR Strapping: "0" -> No Reboot
A
BATTLOW#
21
LID#
PBTN#
21
21
21
ICH_ACIN
21
EXT_SMI#
21
SCI#
21
ICH_RI#
12
C303
1 2
+R_VBAIS
C282
.047UF
12
1 2
R479
22M
R480
2.4M
1 2
CLKRUN# 19,20,23,27,31
R392
1 2
1K
R181
10M
C538
12PF
J1
JOPEN
1 2
R406 10M
32.768KHZ
12
IAC_BITCLK
USBP2USBP2+
USBP0USBP0+
CP5
8P4C-22PF
1 8
2 7
3 6
12
X3
12
C539
12PF
1 2
R158 @10K
12
R170
@33
C543
@33PF
RP41
1 8
2 7
3 6
4 5
8P4R-15
4 5
B
USB0_D- 28
C293
22PF
12
AA13
D14
W16
AB18
R20
W21
AA17
R21
W15
AA18
C14
AA16
AB16
AB17
U19
U22
R19
W22
N22
AA11
W14
AB15
AB14
AA14
W12
AB13
AB12
W13
AB11
AA12
W17
AB19
AA19
W18
AB20
AA20
W19
W20
Y11
A15
V21
Y17
T19
V20
T20
T21
T22
V22
P19
P21
Y22
Y14
L1
Y12
Y13
Y18
Y19
Y20
Y21
USB0_D+ 28
1 2
R408 22
1 2
R180 22
U33B
THRM#
GPO19
SLP_S3#
SLP_S5#
PWROK
PWRBTN#
RI#
RSMRST#
GPIO25
SUSCLK
GPI6
GPO18
GPO20
GPIO24
SUSSTAT#
INTRUDER#
SMBDATA
SMBCLK
SMBALERT#/GPI11
SMLINK0
SMLINK1
RTCRST#
VBIAS
RTCX1
RTCX2
AC_RST#
AC_SYNC
AC_BIT_CLK
AC_SDOUT
AC_SDIN0
AC_SDIN1
SPKR
GPI8
GPI7
GPI12
GPI13
GPO21
GPIO27
GPIO28
LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3
LDRQ0#
LDRQ1#
LFRAME#/FWH4
FSO
USBP0+
USBP0USBP1+
USBP1USBP2+
USBP2USBP3+
ICH-2
USBP3OC0#
OC1#
OC2#
OC3#
SYSTEM
AC97
GPIO
LPC
USB
ICH_AC_SYNC
ICH_AC_SDOUT
182736
45
RP40
8P4R-15K
ATF_INT#31
SLP_S3#31
SLP_S5#31
SYS_PWROK35
RSMRST#12,35
FLASH#32
RTCCLK20,21
SUS_STAT#14,27,34
SDAP413
SCKP413
IAC_RST#26,29 PDD[0..15] 25
IAC_BITCLK26,29
IAC_SDATAI29
IAC_SDATAI126
SPKR30
USB_EN#28
LAD027,31
LAD127,31
LAD227,31
LAD327,31
LDRQ#031
LDRQ#127
LFRAME#27,31
OVCUR#028
OVCUR#128
OVCUR#328
IAC_SYNC26,29
IAC_SDATAO26,29
PROPRIETARY NOTE
B
ATF_INT#
SLP_S3#
SLP_S5#
SYS_PWROK
PBTN#
ICH_RI#
RSMRST#
BATTLOW#
INTRUDER#
SDAP4
SCKP4
ICH_ACIN
SMLINK0
SMLINK1
+RTCRST#
+VBIAS
RTCX1
RTCX2
ICH_AC_SYNC
IAC_BITCLK
ICH_AC_SDOUT
IAC_SDATAI
IAC_SDATAI1
SPKR
EXT_SMI#
DSCACHE#
SCI#
LID#
LAD0
LAD1
LAD2
LAD3
LDRQ#0
LDRQ#1
LFRAME#
USBP0+
USBP0USBP1+
USBP1USBP2+
USBP2USBP3+
USBP3-
OVCUR#0
OVCUR#1
OVCUR#2
OVCUR#3
12
C544
22PF
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
USBP3USBP3+
USBP1USBP1+
CP6
8P4C-22PF
TP0
GPO22
GPO23
VGATE/VRMPWRGD
CLK48
CLK14
CLK66
PDA0
PDA1
PDA2
PDCS1#
PDCS3#
PDREQ
PDDACK#
PDIOR#
PDIOW#
PIORDY
PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
IDE
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15
SDA0
SDA1
SDA2
SDCS1#
SDCS3#
SDDREQ
SDDACK#
SDIOR#
SDIOW#
SIORDY
SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15
C
U20
B14
A14
B15
P20
M19
D4
F20
F19
E22
E21
E19
G22
F22
G19
G21
G20
H19
H22
J19
J22
K21
L20
M21
M22
L22
L21
K22
K20
J21
J20
H21
H20
A16
D16
B16
C15
D15
B18
B17
D17
C17
A17
D18
B19
D19
A20
C20
C21
D22
E20
D21
C22
D20
B20
C19
A19
C18
A18
1 8
2 7
RP44
1 8
2 7
3 6
4 5
8P4R-15
RP43
8P4R-15K
3 6
4 5
R400 1K
1 2
VGATE
1 2D32 RB751V
R478 0
CLK_USB_ICH
CLK_14M_ICH
CLK_HUB_ICH
PDA0
PDA1
PDA2
PDCS1#
PDCS3#
PDDREQ
PDDACK#
PDIOR#
PDIOW#
PDIORDY
PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15
SDA0
SDA1
SDA2
SDCS1#
SDCS3#
SDDREQ
SDDACK#
SDIOR#
SDIOW#
SDIORDY
SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15
182736
45
+3V
CLK_USB_ICH 13
CLK_14M_ICH 13
CLK_66M_ICH 13
PDA0 25
PDA1 25
PDA2 25
PDCS1# 25
PDCS3# 25
PDDREQ 25
PDDACK# 25
PDIOR# 25
PDIOW# 25
PDIORDY 25
PDD[0..15]
SDA0 24
SDA1 24
SDA2 24
SDCS1# 24
SDCS3# 24
SDDREQ 24
SDDACK# 24
SDIOR# 24
SDIOW# 24
SDIORDY 24
SDD[0..15]
D
ICH2-B(IDE,LPC,GPIO)
USB3_D- 28
USB3_D+ 28
USB1_D- 28
USB1_D+ 28
V_GATE 41
SDD[0..15] 24
1 2
PDIORDY
R416 4.7K
1 2
SDIORDY
R394 4.7K
CLK_USB_ICH CLK_14M_ICH CLK_HUB_ICH
12
R166
22
12
C270
10PF_0402
Compal Electron ics, Inc.
Title
SCHEMATIC, M/B LA-1512
Size Document Number Rev
B
401225
星期四 九月
Date: Sheet of
12
R162
10
12
C245
10PF_0402
D
+5VS
12
R149
10
12
C198
10PF
11 44, 12, 2002
1A
A
B
C
D
ICH2-C(LAN,Power)
+1_8VS
1 1
2 2
+3V
12
C216
.1UF_0402
12
C247
+
4.7UF_10V_0805
3 3
12
C230
.1UF_0402
12
12
C250
.1UF_0402
.1UF_0402
12
+
+1_8V
12
12
C251
.1UF_0402
12
C238
.1UF_0402
C208
4.7UF_10V_0805
C227
.1UF_0402
12
12
C244
.1UF_0402
12
C209
.1UF_0402
CPU_VCC
12
C242
.1UF_0402
12
12
C229
.1UF_0402
12
C243
.1UF_0402
C221
.1UF_0402
C212
.1UF_0402
12
12
C253
.1UF_0402
12
C213
.1UF_0402
C252
.1UF_0402
12
12
C249
.1UF_0402
C224
.1UF_0402
12
C214
1000PF_0402
12
C246
1000PF_0402
+3VS
12
+1_8VS
12
C215
1000PF_0402
C225
1000PF_0402
D10
M10
M11
M12
M13
M14
N10
N11
N12
N14
N13
AA21
AA22
AB21
AB22
K19
L19
D2
A10
B10
C2
C3
C4
C9
D5
D6
D7
D8
D9
J10
J11
J12
J13
J14
K10
K11
K12
K13
K14
L10
L11
L12
L13
L14
M9
P14
P13
P12
P11
P10
N9
A21
A22
B21
B22
AA1
AA2
AB1
AB2
D3
E5
P5
V9
A1
A2
B1
B2
B3
B9
E6
E7
E8
E9
J9
K9
L9
P9
K1
U33C
VCC1_8_1
VCC1_8_2
VCC1_8_3
VCC1_8_4
VCC1_8_5
VCC1_8_6
VCC1_8_7
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND41
GND42
GND43
GND44
GND45
GND46
GND47
GND48
GND49
GND50
GND51
GND52
GND53
GND54
GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64
GND65
GND66
GND67
GND68
GND69
GND70
GND71
ICH-2
VCC3_3_1
VCC3_3_2
VCC3_3_3
VCC3_3_4
VCC3_3_5
VCC3_3_6
VCC3_3_7
VCC3_3_8
VCC3_3_9
VCC3_3_10
VCC3_3_11
VCC3_3_12
VCC3_3_13
VCC3_3_14
VCC3_3_15
VCC3_3_16
VCC3_3_17
VCC3_3_18
V5REF1
V5REF2
VCCSUS1_8_1
VCCSUS1_8_2
VCCSUS1_8_3
VCCSUS1_8_4
VCCSUS1_8_5
VCCSUS3_3_1
VCCSUS3_3_2
VCCSUS3_3_3
VCCSUS3_3_4
VCCSUS3_3_5
VCCSUS3_3_6
V_CPU_IO_1
V_CPU_IO_2
VCCRTC
V5REF_SUS
EEPROM
EE_CS
EE_SHCLK
EE_DOUT
EE_DIN
LAN
LAN_CLK
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
LAN_RSTSYNC
RSM_PWROK
+3VS
E14
E15
E16
E17
E18
F18
G18
H18
J18
P18
R18
R5
T5
U5
V5
V6
V7
V8
K2
+VCC5REF
M20
V14
V15
V16
H5
J5
T18
U18
F5
G5
V17
V18
D12
D13
U21
V19
K4
J3
J4
K3
R353 @10K
G3
G2
G1
H1
LANTXD0
F3
F2
LANTXD1
LANTXD2
F1
H2
Y16
+1_8V
+3V
CPU_VCC
VCCRTC
+3V
LAN_EECS
LAN_EECLK
LAN_EEDI
LAN_EEDO
1 2C231
LAN_CLK
R100 331 2
1 2
R101 33
R102 331 2
1 2
R99 33
1 2
R167 0
LAN_CLK
1
2
3
4
1 2
R182 1K
C540 .1UF
U29
CS
SK
DI
DO
9346
D12
1SS355
12
C197
1UF_0805
1 2
8
VCC
7
NC
6
NC
5
GND
LAN_CLK 22
LAN_RXD0 22
LAN_RXD1 22
LAN_RXD2 22
LAN_TXD0 22
LAN_TXD1 22
LAN_TXD2 22
LAN_RST 22
RSMRST# 11,35
12
R86
@33
12
C136
@22PF
+3VS
21
12
+5VS
12
C292
.1UF
+RTCVCC
+3V
12
C476
.1UF
R140
1K
4 4
Compal Electron ics, Inc.
Title
PROPRIETARY NOTE
A
B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
SCHEMATIC, M/B LA-1512
Size Document Number Rev
B
401225
星期四 九月
Date: Sheet of
D
12 44, 12, 2002
1A
A
B
C
D
E
F
G
H
Clock Generator
+3VS
SEL2 SEL1 SEL0 CPUCLKC[0..2] CPUCLKT[0..2]
0 0 0 66.67 66.67
0 0 1 100.00 100.00
0 1 0 200.00 200.00
0 1 1 133.33 133.33
1 1
+3VS +3VS
12
12
R326
R328
1K
@1K
BSEL02
BSEL12
2 2
1 2
R547 @0
CPU_VCC
12
12
R545
R546
@1K
1K
+3VS
1 2
R346 220
R338 10K
1 2
2
B
+3VS
1
C
Q40
2SC2411K
E
3
CLK_USB_ICH11
C169 10PF
1 2
1 2
1 2
R323 1K
1 2
R339 1K
R317 1K1 2
1 2
R327 1K
+3VS
1 2
R324 220
1 2
R107 33
C176
10PF
1 2
R325 10K
DIMM_SMDATA
DIMM_SMCLK
XTALIN
12
XTALOUT
Y2
14.318MHZ
L11
CHB2012U121
1 2
L12
CHB2012U121
1 2
2
40
55
54
25
34
53
28
43
29
30
33
35
42
39
38
1 2
CLK_14M_ICH11
14.3M_SIO27
3 3
12
C133
R109 33
1 2
R110 33
56
@10PF
+3V_CLK
U9
XTAL_IN
SEL2
SEL1
SEL0
PWR_DWN#
PCI_STOP#
CPU_STOP#
VTT_PWRGD#
MULT0
SDATA
SCLK
3V66_0/DRCG
3V66_1/VCH_CLK
IREF
48MHZ_USB
48MHZ_DOT
REF
ICS950805
Width=40 mils
181419323746
VDD_PCI
VDD_PCI
VDD_REF
VDD_3V66
VDD_3V66
66MHZ_OUT2/3V66_4
66MHZ_OUT1/3V66_3
66MHZ_OUT0/3V66_2
GND_REF
GND_PCI
GND_PCI
GND_3V66
GND_3V66
491520313641
12
+
C139
22UF_16V_1206
50
VDD_CPU
VDD_CPU
VDD_CORE
VDD_48MHZ
GND_COREXTAL_OUT
CPUCLKT2
CPU_CLKC2
CPUCLKT1
CPUCLKC1
CPUCLKT0
CPUCLKC0
66MHZ_IN/3V66_5
PCICLK_F2
PCICLK_F1
PCICLK_F0
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
GND_48MHZ
GND_IREF
GND_CPU
47
26
273
45
44
49
48
52
51
24
23
22
21
7
6
5
18
17
16
13
12
11
10
CLK_BCLK
CLK_BCLK#
12
12
C140
.01UF_0402
+3V_VDD
12
+
C175
.01UF_0402
CLK_MCH
CLK_MCH#
66M_MC H
1 2
R131 33
R134 331 2
1 2
R521 33
R133 331 2
1 2
R132 33
R122 331 2
12
C141
C142
.01UF_0402
.01UF_0402
L14
CHB2012U121
1 2
12
C177
22UF_16V_1206
R105 271 2
1 2
R106 27
1 2
R103 27
R104 271 2
R125 331 2
1 2
R124 33
R123 331 2
12
12
C143
C172
.01UF_0402
.01UF_0402
+3VS
1 2
R87 49.9_1%
R88 49.9_1%1 2
1 2
R89 49.9_1%
1 2
R90 49.9_1%
12
C157
.01UF_0402
12
C182
@10PF
12
C174
.01UF_0402
12
C183
@10PF
12
C171
.01UF_0402
HCLK_CPU 2
HCLK_CPU# 2
CLK_HMCH 4
CLK_HMCH# 4
12
C184
@10PF
CLK_66M_AGP 14
CLK_66M_ICH 11
CLK_66M_MCH 4
PCLK_ICH 10
PCLK_PCM 20
PCLK_1394 19
PCLK_SIO 27
PCLK_EC 31
PCLK_MINI 23
+3V
+5VS
R321
4.7K
1 2
+3V
R322
4 4
SCKP411
4.7K
1 2
2
G
1 3
D
Q61 2N7002
+5VS
2
G
1 3
D
DIMM_SMDATA
S
DIMM_SMCLK
S
DIMM_SMDATA 7,8SDAP411
DIMM_SMCLK 7,8
Q62 2N7002
Compal Electron ics, Inc.
Title
PROPRIETARY NOTE
A
B
C
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
E
F
SCHEMATIC, M/B LA-1512
Size Document Number Rev
B
401225
星期四 九月
Date: Sheet of
G
13 44, 12, 2002
H
1A
1
2
3
4
5
6
7
8
GPIO0
GPIO1
GPIO2
GPIO3
ENVDD
BLON#
DDCSCL
DDCSDA
M_SEN#
R49 01 2
R51 10K1 2
RSET
(10 mil)(10 mil)
Option Strap Pins
R71 @10K1 2
R70 @10K1 2
R74 @10K1 2
R75 @10K1 2
TXOUT0- 18
TXOUT0+ 18
TXOUT1- 18
TXOUT1+ 18
TXOUT2- 18
TXOUT2+ 18
TXCLKO- 18
TXCLKO+ 18
TZOUT0- 18
TZOUT0+ 18
TZOUT1- 18
TZOUT1+ 18
TZOUT2- 18
TZOUT2+ 18
TZCLKO- 18
TZCLKO+ 18
R 18
G 18
B 18
HSYNC1 18
VSYNC1 18
499_1%1 2R52
R50
SUS_STAT#
6
12
(10 mil)
R54
@20K
GAD[0:31]
GC/BE#[0:3]
1 2
+3VS
+3VS
SBA[0:7]
C158 .1UF1 2
12
12
R47
150
3
R4910
1 2
C393 10PF
1 2
1 2 R7220K
R115 47_1%1 2
R53 101 2
R37
@20K
12
C75
@15PF
1 2
845_1%
R6820K
R55 1K
CRMA18
LUMA18
COMPS18
LCD_CLK18
LCD_DATA18
GAD0
GAD1
GAD2
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31
GC/BE#0
GC/BE#1
GC/BE#2
GC/BE#3
GREQ#
GGNT#
GINTA#
GPAR
GSTOP#
GDEVSEL#
GTRDY#
GIRDY#
GFRAME#
1 2
R30110
RBF#
ADSTBA
ADSTBA#
ADSTBB
ADSTBB#
ST0
ST1
ST2
SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
SBSTB
SBSTB#
OSCLIN
1 2
R2SET
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
GAD[0:31]4
A A
GC/BE#[0:3]4
CLK_66M_AGP13
R40
@0
R41
0
FREQOUT
GREQ#4
GGNT#4
PIRQA#10,20,23
GPAR4
GSTOP#4
GDEVSEL#4
GTRDY#4
GIRDY#4
GFRAME#4
PCIRST#4,10,19,20,21,23,25,27,31,34
RBF#4
AD_STB04
AD_STB0#4
AD_STB14
AD_STB1#4
ST04
ST14
ST24
SBA[0:7]4
SBSTB4
SBSTB#4
AGPREF4
1 2
R494 22
1 2
R46 120
B B
+3V_VGA
L47
BLM21P300S_0805
12
C102
C602
10UF_1206
C C
D D
.1UF
12
12
R43
R44
0
@0
12
12
R42
R45
@0
@0
+3V_VGA
2
U6
1
X1/CLK
6
S1
3
12
R64
10K
12
C93
.1UF
VDD
CLK
PD#S0
LEE
GND
MK1709
X1
4
VDD
1
ST
OSC_27MHz
12
12
R550
@0
4
87
5
12
3
OUT
2
GND
Divider circuit for 1.8Vdc XTALIN from 3.3Vdc OSC out
1
2
4
D24
C26
D25
D26
G23
G25
G24
G26
H24
H26
H25
M26
M24
N25
M25
N26
R25
R24
R26
N23
AA25
AA24
AA23
AA26
W24
AB25
AB26
W26
N24
W25
U26
U24
U25
C25
AF25
AF26
AC6
AF16
AF15
AF14
AE14
AF13
AE16
E23
E25
E24
E26
F26
L23
L26
L24
P23
P26
P24
T23
T25
F23
J25
L25
Y24
J23
J24
J26
K24
K26
K25
F25
F24
P25
Y26
Y23
Y25
V24
V26
V23
T26
T24
V25
B26
AE6
AE7
Y3
AF6
AF7
U8A
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C/BE#0
C/BE#1
C/BE#2
C/BE#3
REQ#
GNT#
INTA#
PAR
STOP#
DEVSEL#
TRDY#
IRDY#
FRAME#
RST#
PCICLK
SERR#
STP_AGP#
AGP_BUSY#
RBF#
AD_STB0
ADSTRB0#
AD_STB1
ADSTRB1#
ST0
ST1
ST2
SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
SB_STB
SB_STB#
AGPTEST
AGPREF
SSIN
SSOUT
XTALIN
XTALOUT
TESTEN
ROMCS#
C_R
Y_G
COMP_B
H2SYNC
V2SYNC
CRT2DDCCLK
CRT2DDCDATA
R2SET
M6-P
GPIO /
ROM
ZV_LCDDATA0
ZV_LCDDATA1
ZV_LCDDATA2
ZV_LCDDATA3
ZV_LCDDATA4
ZV_LCDDATA5
ZV_LCDDATA6
ZV_LCDDATA7
ZV_LCDDATA8
ZV_LCDDATA9
ZV_LCDDATA10
ZV_LCDDATA11
ZV_LCDDATA12
ZV_LCDDATA13
ZV_LCDDATA14
ZV_LCDDATA15
ZV_LCDDATA16
ZV_LCDDATA17
ZV_LCDDATA18
ZV_LCDDATA19
ZV_LCDDATA20
ZV_LCDDATA21
ZV_LCDDATA22
ZV_LCDDATA23
ZV PORT / EXT
TMDS
ZV_LCDCNTL0
ZV_LCDCNTL1
ZV_LCDCNTL2
ZV_LCDCNTL3
TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
TXOUT_L2N
TXOUT_L2P
PCI/AGP HOST BUS
INTERFACE
TXOUT_L3N
TXOUT_L3P
TXCLK_LN
TXCLK_LP
TXOUT_U0N
TXOUT_U0P
TXOUT_U1N
TXOUT_U1P
LVDSTMDSDAC
TXOUT_U2N
TXOUT_U2P
TXOUT_U3N
TXOUT_U3P
TXCLK_UN
TXCLK_UP
SSCDAC2
DVIDDCCLK
DVIDDCDATA
CLK
VGADDCCLK
VGADDCDATA
SUS_STAT#
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
LTGIO0
LTGIO1
LTGIO2
DIGON
BLON#
TX0M
TX0P
TX1M
TX1P
TX2M
TX2P
TXCM
TXCP
HPD
HSYNC
VSYNC
MONID0
MONID1
AUXWIN
RSET
5
Y2
Y1
W3
W2
W1
V4
V3
V2
V1
U3
U2
U1
T4
T3
AA4
AB1
AB2
AB3
AB4
AC1
AC2
AC3
AD1
AD2
AD3
AE1
AE2
AF1
AF2
AF3
AE3
AF4
AE4
AD4
AF5
AE5
AD5
AC5
Y4
AA1
AA2
AA3
AC8
AD8
AC9
AD9
AE8
AF8
AC10
AD10
AE9
AF9
AD11
AC11
AE11
AF11
AD12
AC12
AD13
AE13
AE12
AF12
AD7
AD6
AC7
AB10
AB9
AE19
AF19
AE20
AF20
AE21
AF21
AE18
AF18
AD20
AC20
AD21
AF24
R
AF23
G
AF22
B
AE24
AE23
AC25
AC26
AD24
AD25
AE25
AC22
AE22
Strap-G
Strap-H
Strap-J
Strap-K
M_SEN# 18
DDC_MD2 18
+3V_VGA
+3V_VGA
ENVDD 18
BLON# 18
DDC_CLK 18
DDC_DATA 18
SUS_STAT# 11,27,34
HOST INTERFACE
SUS_STAT#
1 2
R48 10K
Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-1512
Size Document Number Rev
401225
Custom
星期四 九月
Date: Sheet of
7
+3V
14 44, 12, 2002
8
1A
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