Acer A715-71 Schematics

1 1

2 2

Compal Confidential

C5MMH MB Schematic Document

LA-E911P

3 3

Rev:1A

2017.04.11

4 4

Security Classification

Issued Date

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/01/29 2017/01/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Cover Sheet

Size Document Number Rev

Custom

C5PM2_LA-E361P

Date: Sheet of

164Tuesday, April 11, 2017

Fan Control*2

USB 3.0 Type -C x2

USB/B

Interleaved Memory

(port 3,4)

page 36

Int. Speaker

260 pin DDR4-SO-DIMM X1

BANK 0, 1, 2, 3

260pin DDR4-SO-DIMM X1

BANK 4, 5, 6, 7

CMOS Camera

USB (port 9)

USB2.0

USB/B (port 5,6)

page 33

page 30

HDA Codec

ALC255

page 40

Int. DMIC

page 40

Title

Size Document Number Rev

Custom

Date: Sheet

on Camera

page 30 page 33

Compal Electronics, Inc.

Block Diagrams

C5MMH M/B LA-E911P

eDP

Memory BUS

1 1

2 2

3 3

HDMI

CONN

NGFF

WLAN

USB port 7

RTC CKT.

page 31

HDMI x 4 lanes

page 37

PCIE 2.0 5GT/s

port 3

LAN(GbE)/CardReader

Realtek 8411H

Card Reader

page 21

page 34

PCIE 3.0 x4 8GT/s

Port 9-12

page 32

PCIE 2.0 5GT/s

port 4

RJ45 conn.

page 32.

Nvidia N17P-GX with gDDR5 x4

page 23~29

page 38

Sub Board

LS-E911P Hall sensor/B

page 33

page 30

eDP

PEG x16 8GT/s

Flexible IO

page 38

SATA3.0

6.0 Gb/s

port 3

SATA Re-Driver

PA R A D E P S 8 5 2 7

SATA HDD Conn.

Touch Pad Int. KBD

PS2 / I2C

Kabylake H PROCESSOR BGA1440 (42X28) (SKL-H_4+2)

Processor

X4 DMI

page 06~13

Skylake PCH - H FCBGA(23X23)

837pin FCBGA

LPC/eSPI BUS

CLK=24MHz

ENE KB9022/9032

page 39

TPM

page 41

page 16~22

Power On/Off CKT.

page 41

DC/DC Interface CKT.

4 4

page 43

Power Circuit DC/DC

page 44~61

LS-E912P USB2/B

page 33

page 41

www.schematic-x.blogspot.com

Security Classification

Issued Date

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/01/29 2017/01/10

Dual Channel

1.2V DDR4 1333/1600

USBx8

48MHz

HD Audio

SPI

SPI ROM x1

page 17

Compal Secret Data

Deciphered Date

USB 3.0 conn

USB (port 2)

page 35

3.3V 24MHz

page 42

page 14

page 15

Finger Print

USB (port 10)

page 42

UAJ

on Sub/B

264Tuesday, April 11, 2017

1 1

CPU_XDP_TMS<9,18> CPU_XDP_TDI<9,18>

CPU_XDP_TDO<9,18> CPU_XDP_TCK0<9,18> PCH_JTAG_TCK1<18>

If need debug from usb port. this cmc@ need pop

+1.0VS_VCCSTG

TMS/TDI pin CPU on-die termination

2 2

Place to PCH side

+1.0VS_VCCSTG

Place to CPU side

CPU_XDP_TMS CPU_XDP_TDI

CPU_XDP_TDO CPU_XDP_TCK0 PCH_JTAG_TCK1

RC5 51_0402_5%CMC@

RC6 51_0402_5%CMC@

1 2

RC7 100_0402_1%CMC@

RC14 51_0402_5%@

1 2

RC8 100_0402_1%CMC@

RC13 51_0402_1%CMC@

UC1D

K36

DDI1_TXP[0]

K37

DDI1_TXN[0]

J35

DDI1_TXP[1]

J34

DDI1_TXN[1]

H37

DDI1_TXP[2]

H36

DDI1_TXN[2]

J37

DDI1_TXP[3]

J38

DDI1_TXN[3]

D27

DDI1_AUXP

E27

DDI1_AUXN

H34

DDI2_TXP[0]

H33

DDI2_TXN[0]

F37

CPU_XDP_TMS

CPU_XDP_TDI

CPU_XDP_TDO

PCH_JTAG_TCK1

CPU_XDP_TDO

CPU_XDP_TCK0

DDI2_TXP[1]

G38

DDI2_TXN[1]

F34

DDI2_TXP[2]

F35

DDI2_TXN[2]

E37

DDI2_TXP[3]

E36

DDI2_TXN[3]

F26

DDI2_AUXP

E26

DDI2_AUXN

C34

DDI3_TXP[0]

D34

DDI3_TXN[0]

B36

DDI3_TXP[1]

B34

DDI3_TXN[1]

F33

DDI3_TXP[2]

E33

DDI3_TXN[2]

C33

DDI3_TXP[3]

B33

DDI3_TXN[3]

A27

DDI3_AUXP

B27

DDI3_AUXN

SKL-H_BGA1440

SKYLAKE_HALO

BGA144 0

4 OF 14

EDP_TXP[0] EDP_TXN[0] EDP_TXP[1] EDP_TXN[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXP EDP_AUXN

EDP_DISP_UTIL

EDP_RCOMP

PROC_AUDIO_CLK

PROC_AUDIO_SDI

PROC_AUDIO_SDO

?REV = 1

D29 E29 F28 E28 B29 A29 B28 C28

C26 B26

A33

EDP_COMP

D37

G27 G25

CPU_DISPA_SDI

G29

EDP_TXP0 <30> EDP_TXN0 <30> EDP_TXP1 <30> EDP_TXN1 <30> EDP_TXN2 <30> EDP_TXP2 <30> EDP_TXN3 <30> EDP_TXP3 <30>

EDP_AUXP <30>

EDP_AUXN <30>

CAD note: Trace width=20 mils,Spacing=25mil,Max length=100mils

RC2

20_0402_5%

Close to CPU

<eDP>

+1.0VS_VCCIO

RC124.9_0402_1%

CPU_DISPA_BCLK <18> CPU_DISPA_SDO <18>

CPU_DISPA_SDI_R <18>

1.0 Modify

3 3

UC1

SR32S@

S IC CL8067702870309 SR32S B0 2.5G ABO!

SA0000AD850

UV1

G0@

S IC N17P-G0-A1 FCBGA 908P GPU 1706

SA0000A0540

UC1

SR32Q@

S IC CL8067702870109 SR32Q B0 2.8G ABO!

SA0000AD750

UV1

G1@

S IC N17P-G1-A1 FCBGA 908P GPU 1707

SA0000A0660

UH1

SR30W@

S IC GL82HM175 SR30W D1 FCBGA PCH-H ABO!

SA0000ADB30

1.A Modify

ZZZ

DAZ@

PCB C5MMH LA-E911P LS-E911P/E912P

DAZ20Z00102

1A Modify

4 4

Security Classification

2016/11/03 2017/01/10

Issued Date

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/11/03 2017/01/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

SKL-H(1/9)DDI,EDP

C5MMH M/B LA-E911P

664Tuesday, April 11, 2017

Interleaved Memory

DDR_A_D[0..15]<14>

1 1

DDR_A_D[16..31]<14>

DDR_A_D[32..47]<14>

2 2

DDR_A_D[48..63]<14>

3 3

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

UC1A

BR6

DDR0_DQ[0]

BT6

DDR0_DQ[1]

BP3

DDR0_DQ[2]

BR3

DDR0_DQ[3]

BN5

DDR0_DQ[4]

BP6

DDR0_DQ[5]

BP2

DDR0_DQ[6]

BN3

DDR0_DQ[7]

BL4

DDR0_DQ[8]

BL5

DDR0_DQ[9]

BL2

DDR0_DQ[10]

BM1

DDR0_DQ[11]

BK4

DDR0_DQ[12]

BK5

DDR0_DQ[13]

BK1

DDR0_DQ[14]

BK2

DDR0_DQ[15]

BG4

DDR0_DQ[16]/DDR0_DQ[32]

BG5

DDR0_DQ[17]/DDR0_DQ[33]

BF4

DDR0_DQ[18]/DDR0_DQ[34]

BF5

DDR0_DQ[19]/DDR0_DQ[35]

BG2

DDR0_DQ[20]/DDR0_DQ[36]

BG1

DDR0_DQ[21]/DDR0_DQ[37]

BF1

DDR0_DQ[22]/DDR0_DQ[38]

BF2

DDR0_DQ[23]/DDR0_DQ[39]

BD2

DDR0_DQ[24]/DDR0_DQ[40]

BD1

DDR0_DQ[25]/DDR0_DQ[41]

BC4

DDR0_DQ[26]/DDR0_DQ[42]

BC5

DDR0_DQ[27]/DDR0_DQ[43]

BD5

DDR0_DQ[28]/DDR0_DQ[44]

BD4

DDR0_DQ[29]/DDR0_DQ[45]

BC1

DDR0_DQ[30]/DDR0_DQ[46]

BC2

DDR0_DQ[31]/DDR0_DQ[47]

AB1

DDR0_DQ[32]/DDR1_DQ[0]

AB2

DDR0_DQ[33]/DDR1_DQ[1]

AA4

DDR0_DQ[34]/DDR1_DQ[2]

AA5

DDR0_DQ[35]/DDR1_DQ[3]

AB5

DDR0_DQ[36]/DDR1_DQ[4]

AB4

DDR0_DQ[37]/DDR1_DQ[5]

AA2

DDR0_DQ[38]/DDR1_DQ[6]

AA1

DDR0_DQ[39]/DDR1_DQ[7]

DDR0_DQ[40]/DDR1_DQ[8]

DDR0_DQ[41]/DDR1_DQ[9]

DDR0_DQ[42]/DDR1_DQ[10]

DDR0_DQ[43]/DDR1_DQ[11]

DDR0_DQ[44]/DDR1_DQ[12]

DDR0_DQ[45]/DDR1_DQ[13]

DDR0_DQ[46]/DDR1_DQ[14]

DDR0_DQ[47]/DDR1_DQ[15]

DDR0_DQ[48]/DDR1_DQ[32]

DDR0_DQ[49]/DDR1_DQ[33]

DDR0_DQ[50]/DDR1_DQ[34]

DDR0_DQ[51]/DDR1_DQ[35]

DDR0_DQ[52]/DDR1_DQ[36]

DDR0_DQ[53]/DDR1_DQ[37]

DDR0_DQ[54]/DDR1_DQ[38]

DDR0_DQ[55]/DDR1_DQ[39]

DDR0_DQ[56]/DDR1_DQ[40]

DDR0_DQ[57]/DDR1_DQ[41]

DDR0_DQ[58]/DDR1_DQ[42]

DDR0_DQ[59]/DDR1_DQ[43]

DDR0_DQ[60]/DDR1_DQ[44]

DDR0_DQ[61]/DDR1_DQ[45]

DDR0_DQ[62]/DDR1_DQ[46]

DDR0_DQ[63]/DDR1_DQ[47]

BA2

DDR0_ECC[0]

BA1

DDR0_ECC[1]

AY4

DDR0_ECC[2]

AY5

DDR0_ECC[3]

BA5

DDR0_ECC[4]

BA4

DDR0_ECC[5]

AY1

DDR0_ECC[6]

AY2

DDR0_ECC[7]

DDR CHANNEL A

SKL-H_BGA1440

REV = 1

SKYLAKE_HALO

BGA1440

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]

DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#

DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSN[7]/DDR1_DQSN[5]

1 OF 14

DDR0_CKP[0] DDR0_CKN[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CLKP[2]

DDR0_CLKN[2]

DDR0_CLKP[3]

DDR0_CLKN[3]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0] DDR0_CS#[1] DDR0_CS#[2] DDR0_CS#[3]

DDR0_ODT[0] DDR0_ODT[1] DDR0_ODT[2] DDR0_ODT[3]

DDR0_MA[3] DDR0_MA[4]

DDR0_PAR

DDR0_ALERT#

DDR0_DQSN[0] DDR0_DQSN[1]

DDR0_DQSP[0] DDR0_DQSP[1]

DDR0_DQSP[8] DDR0_DQSN[8]

AG1 AG2 AK1 AK2 AL3 AK3 AL2 AL1

AT1 AT2 AT3 AT5

AD5 AE2 AD2 AE5

AD3 AE4 AE1 AD4

AH5 AH1 AU1

AH4 AG4 AD1

AH3 AP4 AN4 AP5 AP2 AP1 AP3 AN1 AN3 AT4 AH2 AN2 AU4 AE3 AU2 AU3

AG3 AU5

BR5 BL3 BG3 BD3 AB3 V3 R3 M3

BP5 BK3 BF3 BC3 AA3 U3 P3 L3

AY3 BA3

DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK#1 DDR_A_CLK1

DDR_A_CKE0 DDR_A_CKE1

DDR_A_CS#0 DDR_A_CS#1

DDR_A_ODT0 DDR_A_ODT1

DDR_A_BA0 DDR_A_BA1 DDR_A_BG0

DDR_A_MA16 DDR_A_MA14 DDR_A_MA15

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_BG1 DDR_A_ACT#

DDR_A_PARITY DDR_A_ALERT#

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_CLK0 <14> DDR_A_CLK#0 <14> DDR_A_CLK#1 <14> DDR_A_CLK1 <14>

DDR_A_CKE0 <14> DDR_A_CKE1 <14>

DDR_A_CS#0 <14> DDR_A_CS#1 <14>

DDR_A_ODT0 <14> DDR_A_ODT1 <14>

DDR_A_BA0 <14> DDR_A_BA1 <14> DDR_A_BG0 <14>

DDR_A_MA16 <14> DDR_A_MA14 <14> DDR_A_MA15 <14>

DDR_A_MA0 <14 > DDR_A_MA1 <14 > DDR_A_MA2 <14 > DDR_A_MA3 <14 > DDR_A_MA4 <14 > DDR_A_MA5 <14 > DDR_A_MA6 <14 > DDR_A_MA7 <14 > DDR_A_MA8 <14 > DDR_A_MA9 <14 > DDR_A_MA10 <14> DDR_A_MA11 <14> DDR_A_MA12 <14> DDR_A_MA13 <14> DDR_A_BG1 <14> DDR_A_ACT# <14>

DDR_A_PARITY <14> DDR_A_ALERT# <14>

DDR_A_DQS#0 <14> DDR_A_DQS#1 <14> DDR_A_DQS#2 <14> DDR_A_DQS#3 <14> DDR_A_DQS4 <14> DDR_A_DQS5 <14> DDR_A_DQS6 <14> DDR_A_DQS7 <14>

DDR_A_DQS0 <14> DDR_A_DQS1 <14> DDR_A_DQS2 <14> DDR_A_DQS3 <14> DDR_A_DQS#4 <14> DDR_A_DQS#5 <14> DDR_A_DQS#6 <14> DDR_A_DQS#7 <14>

DDR_B_D[0..15]<15>

DDR_B_D[16..31]<15>

DDR_B_D[32..47]<15>

DDR_B_D[48..63]<15>

close to CPU

DDR CHANNEL B

SKYLAKE_HALO

BGA1440

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]

DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]

DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#

DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSN[5]/DDR1_DQSN[3]

DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSP[5]/DDR1_DQSP[3]

2 OF 14

DDR1_CKP[0] DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[1]

DDR1_CLKP[2]

DDR1_CLKN[2]

DDR1_CLKP[3]

DDR1_CLKN[3]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]

DDR1_CS#[0] DDR1_CS#[1] DDR1_CS#[2] DDR1_CS#[3]

DDR1_ODT[0] DDR1_ODT[1] DDR1_ODT[2] DDR1_ODT[3]

DDR1_MA[3] DDR1_MA[4]

DDR1_PAR

DDR1_ALERT#

DDR1_DQSN[6] DDR1_DQSN[7]

DDR1_DQSP[6] DDR1_DQSP[7]

DDR1_DQSP[8] DDR1_DQSN[8]

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

AM9 AN9 AM8 AM7 AM11 AM10 AJ10 AJ11

AT8 AT10 AT7 AT11

AF11 AE7 AF10 AE10

AF7 AE8 AE9 AE11

AH10 AH11 AF8

AH8 AH9 AR9

AJ9 AK6 AK5 AL5 AL6 AM6 AN7 AN10 AN8 AR11 AH7 AN11 AR10 AF9 AR7 AT9

AJ7 AR8

BP9 BL9 BG9 BC9 AC9 W9 R9 M9

BR9 BJ9 BF9 BB9 AA9 V9 P9 L9

AW9 AY9

BN13 BP13 BR13

DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK#1 DDR_B_CLK1

DDR_B_CKE0 DDR_B_CKE1

DDR_B_CS#0 DDR_B_CS#1

DDR_B_ODT0 DDR_B_ODT1

DDR_B_MA16 DDR_B_MA14 DDR_B_MA15

DDR_B_BA0 DDR_B_BA1 DDR_B_BG0

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_BG1 DDR_B_ACT#

DDR_B_PARITY DDR_B_ALERT#

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

+0.6V_VREFCA

+0.6V_B_VREFDQ

DDR_B_CLK0 <15> DDR_B_CLK#0 <15> DDR_B_CLK#1 <15> DDR_B_CLK1 <15>

DDR_B_CKE0 <15> DDR_B_CKE1 <15>

DDR_B_CS#0 <15> DDR_B_CS#1 <15>

DDR_B_ODT0 <15> DDR_B_ODT1 <15>

DDR_B_MA16 <15> DDR_B_MA14 <15> DDR_B_MA15 <15>

DDR_B_BA0 <15> DDR_B_BA1 <15> DDR_B_BG0 <15>

DDR_B_MA0 <15> DDR_B_MA1 <15> DDR_B_MA2 <15> DDR_B_MA3 <15> DDR_B_MA4 <15> DDR_B_MA5 <15> DDR_B_MA6 <15> DDR_B_MA7 <15> DDR_B_MA8 <15> DDR_B_MA9 <15> DDR_B_MA10 <15> DDR_B_MA11 <15> DDR_B_MA12 <15> DDR_B_MA13 <15> DDR_B_BG1 <15> DDR_B_ACT# <15>

DDR_B_PARITY <15> DDR_B_ALERT# <15>

DDR_B_DQS#0 <15> DDR_B_DQS#1 <15> DDR_B_DQS#2 <15> DDR_B_DQS#3 <15> DDR_B_DQS#4 <15> DDR_B_DQS#5 <15> DDR_B_DQS#6 <15> DDR_B_DQS#7 <15>

DDR_B_DQS0 <15> DDR_B_DQS1 <15> DDR_B_DQS2 <15> DDR_B_DQS3 <15> DDR_B_DQS4 <15> DDR_B_DQS5 <15> DDR_B_DQS6 <15> DDR_B_DQS7 <15>

+0.6V_VREFCA

+0.6V_B_VREFDQ

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

SM_RCOMP0

RC17121_0402_1%

SM_RCOMP1

RC1875_0402_1%

SM_RCOMP2

RC19100_0402_1%

UC1B

BT11

DDR1_DQ[0]/DDR0_DQ[16]

BR11

DDR1_DQ[1]/DDR0_DQ[17]

BT8

DDR1_DQ[2]/DDR0_DQ[18]

BR8

DDR1_DQ[3]/DDR0_DQ[19]

BP11

DDR1_DQ[4]/DDR0_DQ[20]

BN11

DDR1_DQ[5]/DDR0_DQ[21]

BP8

DDR1_DQ[6]/DDR0_DQ[22]

BN8

DDR1_DQ[7]/DDR0_DQ[23]

BL12

DDR1_DQ[8]/DDR0_DQ[24]

BL11

DDR1_DQ[9]/DDR0_DQ[25]

BL8

DDR1_DQ[10]/DDR0_DQ[26]

BJ8

DDR1_DQ[11]/DDR0_DQ[27]

BJ11

DDR1_DQ[12]/DDR0_DQ[28]

BJ10

DDR1_DQ[13]/DDR0_DQ[29]

BL7

DDR1_DQ[14]/DDR0_DQ[30]

BJ7

DDR1_DQ[15]/DDR0_DQ[31]

BG11

DDR1_DQ[16]/DDR0_DQ[48]

BG10

DDR1_DQ[17]/DDR0_DQ[49]

BG8

DDR1_DQ[18]/DDR0_DQ[50]

BF8

DDR1_DQ[19]/DDR0_DQ[51]

BF11

DDR1_DQ[20]/DDR0_DQ[52]

BF10

DDR1_DQ[21]/DDR0_DQ[53]

BG7

DDR1_DQ[22]/DDR0_DQ[54]

BF7

DDR1_DQ[23]/DDR0_DQ[55]

BB11

DDR1_DQ[24]/DDR0_DQ[56]

BC11

DDR1_DQ[25]/DDR0_DQ[57]

BB8

DDR1_DQ[26]/DDR0_DQ[58]

BC8

DDR1_DQ[27]/DDR0_DQ[59]

BC10

DDR1_DQ[28]/DDR0_DQ[60]

BB10

DDR1_DQ[29]/DDR0_DQ[61]

BC7

DDR1_DQ[30]/DDR0_DQ[62]

BB7

DDR1_DQ[31]/DDR0_DQ[63]

AA11

DDR1_DQ[32]/DDR1_DQ[16]

AA10

DDR1_DQ[33]/DDR1_DQ[17]

AC11

DDR1_DQ[34]/DDR1_DQ[18]

AC10

DDR1_DQ[35]/DDR1_DQ[19]

AA7

DDR1_DQ[36]/DDR1_DQ[20]

AA8

DDR1_DQ[37]/DDR1_DQ[21]

AC8

DDR1_DQ[38]/DDR1_DQ[22]

AC7

DDR1_DQ[39]/DDR1_DQ[23]

DDR1_DQ[40]/DDR1_DQ[24]

DDR1_DQ[41]/DDR1_DQ[25]

V10

DDR1_DQ[42]/DDR1_DQ[26]

V11

DDR1_DQ[43]/DDR1_DQ[27]

W11

DDR1_DQ[44]/DDR1_DQ[28]

W10

DDR1_DQ[45]/DDR1_DQ[29]

DDR1_DQ[46]/DDR1_DQ[30]

DDR1_DQ[47]/DDR1_DQ[31]

R11

DDR1_DQ[48]

P11

DDR1_DQ[49]

DDR1_DQ[50]

DDR1_DQ[51]

R10

DDR1_DQ[52]

P10

DDR1_DQ[53]

DDR1_DQ[54]

DDR1_DQ[55]

L11

DDR1_DQ[56]

M11

DDR1_DQ[57]

DDR1_DQ[58]

DDR1_DQ[59]

L10

DDR1_DQ[60]

M10

DDR1_DQ[61]

DDR1_DQ[62]

DDR1_DQ[63]

AW11

DDR1_ECC[0]

AY11

DDR1_ECC[1]

AY8

DDR1_ECC[2]

AW8

DDR1_ECC[3]

AY10

DDR1_ECC[4]

AW10

DDR1_ECC[5]

AY7

DDR1_ECC[6]

AW7

DDR1_ECC[7]

DDR_RCOMP[0]

DDR_RCOMP[1]

DDR_RCOMP[2]

SKL-H_BGA1440

REV = 1 ?

4 4

Security Classification

Security Classificati on

Issued Date

THIS S HEET OF ENGINEER ING D RAWING IS THE PROPRI ETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS S HEET OF ENGINEER ING D RAWING IS THE PROPRI ETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORM ATION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORM ATION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORM ATION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/11/03 2017/01/10

Compal Secret Data

Deciphered Date

Deciphered Dat e

Compal Electronics, Inc.

Titl e

Size Document Number Rev

Custom

Date: Sheet of

SKL-H(2/9)DDRIII

C5MMH M/B LA-E911P

Tuesday, April 11, 2017

1 1

1 2

PEG_GTX_HRX_P15<23> PEG_GTX_HRX_N15<23>

PEG_GTX_HRX_P14<23> PEG_GTX_HRX_N14<23>

PEG_GTX_HRX_P13<23> PEG_GTX_HRX_N13<23>

PEG_GTX_HRX_P12<23> PEG_GTX_HRX_N12<23>

PEG_GTX_HRX_P11<23> PEG_GTX_HRX_N11<23>

PEG_GTX_HRX_P10<23> PEG_GTX_HRX_N10<23>

PEG_GTX_HRX_P9<23> PEG_GTX_HRX_N9<23>

PEG_GTX_HRX_P8<23>

2 2

3 3

PEG_GTX_HRX_N8<23>

PEG_GTX_HRX_P7<23> PEG_GTX_HRX_N7<23>

PEG_GTX_HRX_P6<23> PEG_GTX_HRX_N6<23>

PEG_GTX_HRX_P5<23> PEG_GTX_HRX_N5<23>

PEG_GTX_HRX_P4<23> PEG_GTX_HRX_N4<23>

PEG_GTX_HRX_P3<23> PEG_GTX_HRX_N3<23>

PEG_GTX_HRX_P2<23> PEG_GTX_HRX_N2<23>

PEG_GTX_HRX_P1<23> PEG_GTX_HRX_N1<23>

PEG_GTX_HRX_P0<23> PEG_GTX_HRX_N0<23>

CC6 0.22U_0201_6.3V6KVGA@

1 2

CC8 0.22U_0201_6.3V6KVGA@

1 2

CC10 0.22U_0201_6.3V6KVGA@

1 2

CC12 0.22U_0201_6.3V6KVGA@

1 2

CC14 0.22U_0201_6.3V6KVGA@

1 2

CC15 0.22U_0201_6.3V6KVGA@

1 2

CC3 0.22U_0201_6.3V6KVGA@

1 2

CC17 0.22U_0201_6.3V6KVGA@

1 2

CC19 0.22U_0201_6.3V6KVGA@

1 2

CC21 0.22U_0201_6.3V6KVGA@

1 2

CC5 0.22U_0201_6.3V6KVGA@

1 2

CC23 0.22U_0201_6.3V6KVGA@

1 2

CC25 0.22U_0201_6.3V6KVGA@

1 2

CC27 0.22U_0201_6.3V6KVGA@

1 2

CC29 0.22U_0201_6.3V6KVGA@

1 2

CC31 0.22U_0201_6.3V6KVGA@

1 2

CC33 0.22U_0201_6.3V6KVGA@

1 2

CC35 0.22U_0201_6.3V6KVGA@

1 2

CC37 0.22U_0201_6.3V6KVGA@

1 2

CC39 0.22U_0201_6.3V6KVGA@

1 2

CC41 0.22U_0201_6.3V6KVGA@

1 2

CC43 0.22U_0201_6.3V6KVGA@

1 2

CC45 0.22U_0201_6.3V6KVGA@

1 2

CC47 0.22U_0201_6.3V6KVGA@

1 2

CC49 0.22U_0201_6.3V6KVGA@

1 2

CC51 0.22U_0201_6.3V6KVGA@

1 2

CC53 0.22U_0201_6.3V6KVGA@

1 2

CC55 0.22U_0201_6.3V6KVGA@

1 2

CC57 0.22U_0201_6.3V6KVGA@

1 2

CC59 0.22U_0201_6.3V6KVGA@

1 2

CC61 0.22U_0201_6.3V6KVGA@

1 2

CC63 0.22U_0201_6.3V6KVGA@

+1.0VS_VCCIO

CAD note: Trace width =12 mi ls,Sp acing =15mi l,Max length =400mils

DMI_CRX_PTX_P0<16> DMI_CRX_PTX_N0<16>

DMI_CRX_PTX_P1<16> DMI_CRX_PTX_N1<16>

DMI_CRX_PTX_P2<16> DMI_CRX_PTX_N2<16>

DMI_CRX_PTX_P3<16> DMI_CRX_PTX_N3<16>

1 2

RC20 24.9_0402_1%

PEG_GTX_C_HRX_P15 PEG_GTX_C_HRX_N15

PEG_GTX_C_HRX_P14 PEG_GTX_C_HRX_N14

PEG_GTX_C_HRX_P13 PEG_GTX_C_HRX_N13

PEG_GTX_C_HRX_P12 PEG_GTX_C_HRX_N12

PEG_GTX_C_HRX_P11 PEG_GTX_C_HRX_N11

PEG_GTX_C_HRX_P10 PEG_GTX_C_HRX_N10

PEG_GTX_C_HRX_P9 PEG_GTX_C_HRX_N9

PEG_GTX_C_HRX_P8 PEG_GTX_C_HRX_N8

PEG_GTX_C_HRX_P7 PEG_GTX_C_HRX_N7

PEG_GTX_C_HRX_P6 PEG_GTX_C_HRX_N6

PEG_GTX_C_HRX_P5 PEG_GTX_C_HRX_N5

PEG_GTX_C_HRX_P4 PEG_GTX_C_HRX_N4

PEG_GTX_C_HRX_P3 PEG_GTX_C_HRX_N3

PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_N2

PEG_GTX_C_HRX_P1 PEG_GTX_C_HRX_N1

PEG_GTX_C_HRX_P0 PEG_GTX_C_HRX_N0

PEG_RCOMP

DMI_CRX_PTX_P0 DMI_CRX_PTX_N0

DMI_CRX_PTX_P1 DMI_CRX_PTX_N1

DMI_CRX_PTX_P2 DMI_CRX_PTX_N2

DMI_CRX_PTX_P3 DMI_CRX_PTX_N3

E25 D25

E24 F24

E23 D23

E22 F22

E21 D21

E20 F20

E19 D19

E18 F18

D17 E17

F16 E16

D15 E15

F14 E14

D13 E13

F12 E12

D11 E11

F10 E10

D8 E8

E6 F6

D5 E5

J8 J9

UC1C

PEG_RXP[0] PEG_RXN[0]

PEG_RXP[1] PEG_RXN[1]

PEG_RXP[2] PEG_RXN[2]

PEG_RXP[3] PEG_RXN[3]

PEG_RXP[4] PEG_RXN[4]

PEG_RXP[5] PEG_RXN[5]

PEG_RXP[6] PEG_RXN[6]

PEG_RXP[7] PEG_RXN[7]

PEG_RXP[8] PEG_RXN[8]

PEG_RXP[9] PEG_RXN[9]

PEG_RXP[10] PEG_RXN[10]

PEG_RXP[11] PEG_RXN[11]

PEG_RXP[12] PEG_RXN[12]

PEG_RXP[13] PEG_RXN[13]

PEG_RXP[14] PEG_RXN[14]

PEG_RXP[15] PEG_RXN[15]

PEG_RCOMP

DMI_RXP[0] DMI_RXN[0]

DMI_RXP[1] DMI_RXN[1]

DMI_RXP[2] DMI_RXN[2]

DMI_RXP[3] DMI_RXN[3]

SKL-H_BGA1440

REV = 1

SKYLAKE_HALO

BGA144 0

3 OF 14

PEG_TXP[0] PEG_TXN[0]

PEG_TXP[1] PEG_TXN[1]

PEG_TXP[2] PEG_TXN[2]

PEG_TXP[3] PEG_TXN[3]

PEG_TXP[4] PEG_TXN[4]

PEG_TXP[5] PEG_TXN[5]

PEG_TXP[6] PEG_TXN[6]

PEG_TXP[7] PEG_TXN[7]

PEG_TXP[8] PEG_TXN[8]

PEG_TXP[9] PEG_TXN[9]

PEG_TXP[10] PEG_TXN[10]

PEG_TXP[11] PEG_TXN[11]

PEG_TXP[12] PEG_TXN[12]

PEG_TXP[13] PEG_TXN[13]

PEG_TXP[14] PEG_TXN[14]

PEG_TXP[15] PEG_TXN[15]

DMI_TXP[0] DMI_TXN[0]

DMI_TXP[1] DMI_TXN[1]

DMI_TXP[2] DMI_TXN[2]

DMI_TXP[3] DMI_TXN[3]

B25 A25

B24 C24

B23 A23

B22 C22

B21 A21

B20 C20

B19 A19

B18 C18

A17 B17

C16 B16

A15 B15

C14 B14

A13 B13

C12 B12

A11 B11

C10 B10

B8 A8

C6 B6

B5 A5

D4 B4

PEG_HTX_GRX_P15 PEG_HTX_GRX_N15

PEG_HTX_GRX_P14 PEG_HTX_GRX_N14

PEG_HTX_GRX_P13 PEG_HTX_GRX_N13

PEG_HTX_GRX_P12 PEG_HTX_GRX_N12

PEG_HTX_GRX_P11 PEG_HTX_GRX_N11

PEG_HTX_GRX_P10 PEG_HTX_GRX_N10

PEG_HTX_GRX_P9 PEG_HTX_GRX_N9

PEG_HTX_GRX_P8 PEG_HTX_GRX_N8

PEG_HTX_GRX_P7 PEG_HTX_GRX_N7

PEG_HTX_GRX_P6 PEG_HTX_GRX_N6

PEG_HTX_GRX_P5 PEG_HTX_GRX_N5

PEG_HTX_GRX_P4 PEG_HTX_GRX_N4

PEG_HTX_GRX_P3 PEG_HTX_GRX_N3

PEG_HTX_GRX_P2 PEG_HTX_GRX_N2

PEG_HTX_GRX_P1 PEG_HTX_GRX_N1

PEG_HTX_GRX_P0 PEG_HTX_GRX_N0

DMI_CTX_PRX_P0 DMI_CTX_PRX_N0

DMI_CTX_PRX_P1 DMI_CTX_PRX_N1

DMI_CTX_PRX_P2 DMI_CTX_PRX_N2

DMI_CTX_PRX_P3 DMI_CTX_PRX_N3

12 12

DMI_CTX_PRX_P0 <16> DMI_CTX_PRX_N0 <16>

DMI_CTX_PRX_P1 <16> DMI_CTX_PRX_N1 <16>

DMI_CTX_PRX_P2 <16> DMI_CTX_PRX_N2 <16>

DMI_CTX_PRX_P3 <16> DMI_CTX_PRX_N3 <16>

CC70.22U_0201_6.3V6K VGA@ CC90.22U_0201_6.3V6K VGA@

CC110.22U_0201_6.3V6K VGA@ CC130.22U_0201_6.3V6K VGA@

CC10.22U_0201_6.3V6K VGA@ CC20.22U_0201_6.3V6K VGA@

CC160.22U_0201_6.3V6K VGA@ CC180.22U_0201_6.3V6K VGA@

CC200.22U_0201_6.3V6K VGA@ CC40.22U_0201_6.3V6K VGA@

CC220.22U_0201_6.3V6K VGA@ CC240.22U_0201_6.3V6K VGA@

CC260.22U_0201_6.3V6K VGA@ CC280.22U_0201_6.3V6K VGA@

CC300.22U_0201_6.3V6K VGA@ CC320.22U_0201_6.3V6K VGA@

CC340.22U_0201_6.3V6K VGA@ CC360.22U_0201_6.3V6K VGA@

CC380.22U_0201_6.3V6K VGA@ CC400.22U_0201_6.3V6K VGA@

CC420.22U_0201_6.3V6K VGA@ CC440.22U_0201_6.3V6K VGA@

CC460.22U_0201_6.3V6K VGA@ CC480.22U_0201_6.3V6K VGA@

CC500.22U_0201_6.3V6K VGA@ CC520.22U_0201_6.3V6K VGA@

CC540.22U_0201_6.3V6K VGA@ CC560.22U_0201_6.3V6K VGA@

CC580.22U_0201_6.3V6K VGA@ CC600.22U_0201_6.3V6K VGA@

CC620.22U_0201_6.3V6K VGA@ CC640.22U_0201_6.3V6K VGA@

PEG_HTX_C_GRX_P15 <23> PEG_HTX_C_GRX_N15 <23>

PEG_HTX_C_GRX_P14 <23> PEG_HTX_C_GRX_N14 <23>

PEG_HTX_C_GRX_P13 <23> PEG_HTX_C_GRX_N13 <23>

PEG_HTX_C_GRX_P12 <23> PEG_HTX_C_GRX_N12 <23>

PEG_HTX_C_GRX_P11 <23> PEG_HTX_C_GRX_N11 <23>

PEG_HTX_C_GRX_P10 <23> PEG_HTX_C_GRX_N10 <23>

PEG_HTX_C_GRX_P9 <23> PEG_HTX_C_GRX_N9 <23>

PEG_HTX_C_GRX_P8 <23> PEG_HTX_C_GRX_N8 <23>

PEG_HTX_C_GRX_P7 <23> PEG_HTX_C_GRX_N7 <23>

PEG_HTX_C_GRX_P6 <23> PEG_HTX_C_GRX_N6 <23>

PEG_HTX_C_GRX_P5 <23> PEG_HTX_C_GRX_N5 <23>

PEG_HTX_C_GRX_P4 <23> PEG_HTX_C_GRX_N4 <23>

PEG_HTX_C_GRX_P3 <23> PEG_HTX_C_GRX_N3 <23>

PEG_HTX_C_GRX_P2 <23> PEG_HTX_C_GRX_N2 <23>

PEG_HTX_C_GRX_P1 <23> PEG_HTX_C_GRX_N1 <23>

PEG_HTX_C_GRX_P0 <23> PEG_HTX_C_GRX_N0 <23>

4 4

Security Classification

2016/11/03 2017/01/10

Issued Date

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/11/03 2017/01/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-H(3/9) PEG,DMI

Size Document Number Rev

Size Document Number Rev Custom

Custom

C5MMH M/B LA-E911P

Date: Sheet of

864Tuesday, April 11, 2017

SVID Alert / Data

1 1

Place the PU resistors close to CPU

1 2

+1.0V_VCCST

From EC(open-drain)

2 2

From EC OD output

3 3

1.0 Modify

RC34 56_0402_5%

CPU_SVID_ALERT#

CPU_SVID_DAT

EC_VCCST_PG_R<39,43>

PM_DOWN_R<17>

+1.0V_VCCST

1 2

RC36 220_0402_5%

1 2

RC38 100_0402_1%

1K_0402_5%

H_PROCHOT#<39,46>

1K_0402_5%

1 2

RC28 1K_0402_5%

CH65 .1U_0402_16V7K

XEMC@

1 2

CH1 .1U_0402_16V7K

EMC@

1 2

CH2 1000P_0402_50V7K

XEMC@

1 2

CH3 .1U_0402_16V7K

EMC@

1 2

CH67 1000P_0402_50V7K

+1.0VS_VCCSTG

RC31

+1.0V_VCCST

RC27

1 2

XEMC@

1 2

499_0402_1%

1 2

RC29

60.4_0402_1%

1 2

20_0402_1%

RC32

1K_0402_5%

(To VR)

CPU_SVID_ALERT#_R <52>

(To VR)

CPU_SVID_DAT <52>

RC33

H_PROCHOT#_R

EC_VCCST_PG

RC30

H_PROCHOT#_R

EC_VCCST_PG

THERMTRIP#

H_PECI

H_CPUPWRGD

THERMTRIP#

PM_DOWN

H_SKTOCC#<18>

CPU_BCLK<19> CPU_BCLK#<19>

CPU_PCIBCLK<19> CPU_PCIBCLK#<19>

CPU_24M<19> CPU_24M#<19>

CPU_SVID_CLK<52>

H_CPUPWRGD<18> PLTRST_CPU#<17> H_PM_SYNC<17>

H_PECI<17,39>

THERMTRIP#<17>

1 2

RC21 0_0402_5%@

RC22

0_0402_5%

FLOAT FOR SKL GND FOR CNL

DDR_VTT_CNTL to DDR VTT supplied ramped <35uS (tCPU18)

DDR_PG_CTRL

1 2

CPU_SVID_ALERT# CPU_SVID_CLK CPU_SVID_DAT H_PROCHOT#_R

DDR_PG_CTRL

EC_VCCST_PG

H_CPUPWRGD PLTRST_CPU# H_PM_SYNC PM_DOWN H_PECI

THERMTRIP#

H_SKTOCC#_R SKL_CNL_N

T3 PAD

CPU_BCLK CPU_BCLK#

CPU_PCIBCLK CPU_PCIBCLK#

CPU_24M CPU_24M#

H_CATERR#

NC1VCC

GND

74AUP1G07GW_TSSOP5

B31 A32

D35 C36

E31 D31

BH31 BH32 BH29 BR30

BT13

H13

BT31 BP35 BM34 BP31

BT34

BR33

BN1

BM30

J31

UC1E

BCLKP BCLKN

PCI_BCLKP PCI_BCLKN

CLK24P CLK24N

VIDALERT# VIDSCK VIDSOUT PROCHOT#

DDR_VTT_CNTL

VCCST_PWRGD

PROCPWRGD RESET# PM_SYNC PM_DOWN PECI THERMTRIP#

SKTOCC# PROC_SELECT#

CATERR#

SKL-H_BGA1440

UC2

ESD Reserve ,pleace close to cpu

SKYLAKE_HALO

BGA144 0

PROC_TDO

PROC_TMS

PROC_TCK

PROC_TRST# PROC_PREQ# PROC_PRDY#

CFG_RCOMP

5 OF 14

REV = 1 ?

+1.2V_VDDQ

+3VS

CC650.1U_0201_10V6K

RC35 220K_0402_5%

RC37 2M_0402_5%@

1 2

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8]

CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]

CFG[17] CFG[16] CFG[19] CFG[18]

BPM#[0] BPM#[1] BPM#[2] BPM#[3]

PROC_TDI

BN25

CFG0

BN27 BN26

CFG2

BN28 BR20

CFG4

BM20

CFG5

BT20 BP20

CFG7

BR23 BR22 BT23 BT22 BM19 BR19 BP19 BT19

BN23 BP23 BP22 BN22

BR27 BT27 BM31 BT30

CPU_XDP_TDO

BT28

CPU_XDP_TDI

BL32

CPU_XDP_TMS

BP28

CPU_XDP_TCK0

BR28

BP30 BL30 BP27

CFG_RCOMP

BT25

SM_PG_CTRL <48>

@ RC23 1K_0402_1%

T1PAD

T2PAD

CFG4

CFG5

CFG2

PCIE port assign

1 x 16 1 x 16

reverse

2 x 8 2 x 8

reverse 1 x 8 + 2 x 4 1x8+2x4 reverse

RC24

49.9_0402_1%

CPU_XDP_TDO <6,18> CPU_XDP_TDI <6,18> CPU_XDP_TMS <6,18> CPU_XDP_TCK0 <6,18>

1 2

RC25 1K_0402_1%@

1 2

RC26 1K_0402_1%

Config. Signals

111

000

Reference SKL EDS 0.85 Table 6-8 CFG signals internal PH default value = 1

Description

Stall reset sequence after PCU PLL

CFG[0]

CFG[4]

CFG[7]

CFG[1]

CFG[3]

CFG[8:19]

lock until de-asserted — 1 = (Default) Normal Operation;

No stall. — 0 = Stall.

Enable eDP — 1 = Disabled. — 0 = Enabled.

PEG Training: — 1 = (default) PEG Train immediately

following RESET# de assertion. — 0 = PEG Wait for BIOS for training

Reserved configuration lane.

CFG[2]CFG[5]CFG[6]

4 4

Security Classification

2016/11/03 2017/01/10

Issued Date

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/11/03 2017/01/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-H(4/9)CLK,GPIO

Size Document Number Rev

Custom

C5MMH M/B LA-E911P

Date: Sheet of

964Tuesday, April 11, 2017

+VCC_CORE +VCC_CORE

1 1

2 2

3 3

4 4

AA13 AA31 AA32 AA33 AA34 AA35 AA36 AA37 AA38 AB29 AB30 AB31 AB32 AB35 AB36 AB37 AB38 AC13 AC14 AC29 AC30 AC31 AC32 AC33 AC34 AC35 AC36 AD13 AD14 AD31 AD32 AD33 AD34 AD35 AD36 AD37 AD38 AE13 AE14 AE30 AE31 AE32 AE35 AE36 AE37 AE38

AF35 AF36 AF37 AF38

K13 K14

N13 N14 N30 N31 N32 N35 N36 N37 N38 P13

L13

SKYLAKE_HALO

UC1G

BGA144 0

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

7 OF 14

SKL-H_BGA1440

REV = 1 ?

VCC_SENSE VSS_SENSE

V32 V33 V34 V35 V36 V37 V38 W13 W14 W29 W30 W31 W32 W35 W36 W37 W38 Y29 Y30 Y31 Y32 Y33 Y34 Y35 Y36 L14 P29 P30 P31 P32 P33 P34 P35 P36 R13 R31 R32 R33 R34 R35 R36 R37 R38 T29 T30 T31 T32 T35 T36 T37 T38 U29 U30 U31 U32 U33 U34 U35 U36 V13 V14 V31 P14

Trace Length < 25 mils

AG37 AG38

PH/PL on pwr side 10/07 Dan

H-4+2/68A H-4+2/55A

+VCC_GT +VCC_GT

SKYLAKE_HALO

UC1H

SKL-H_BGA1440

BGA144 0

REV = 1

8 OF 14

VCCSENSE <52>

VSSSENSE <52>

BG34 BG35 BG36 BH33 BH34 BH35 BH36 BH37 BH38

BJ37 BJ38 BL36

BL37 BM36 BM37 BN36 BN37 BN38 BP37 BP38 BR37

BT37 BE38

BF13

BF14

BF29

BF30

BF31

BF32

BF35

BF36

BF37

BF38 BG29 BG30 BG31 BG32 BG33 BC36 BC37 BC38 BD13 BD14 BD29 BD30 BD31 BD32 BD33 BD34 BD35 BD36 BE31 BE32 BE37

AV29 AV30 AV31 AV32 AV33 AV34 AV35 AV36 AW14 AW31 AW32 AW33 AW34 AW35 AW36 AW37 AW38 AY29 AY30 AY31 AY32 AY35 AY36 AY37 AY38 BA13 BA14 BA29 BA30 BA31 BA32 BA33 BA34 BA35 BA36 BB13 BB14 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BC29 BC30 BC31 BC32 BC35 BE33 BE34 BE35 BE36

EDS:Rail is unconnected for Processors without GT3/4.

+VCC_GT

AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 AJ35

AJ36 AK31 AK32 AK33 AK34 AK35 AK36 AK37 AK38

AL13

AL29

AL30

AL31

AL32

AL35

AL36

AL37

AL38 AM13 AM14 AM29 AM30 AM31 AM32 AM33 AM34 AM35 AM36 AN13 AN14 AN31 AN32 AN33 AN34 AN35 AN36 AN37 AN38 AP13 AP14 AP29 AP30 AP31 AP32 AP35 AP36 AP37 AP38 AR29 AR30 AR31 AR32 AR33 AR34 AR35 AR36

AT14

AT31

AT32

AT33

AT34

AT35

AT36

AT37

AT38 AU14 AU29 AU30 AU31 AU32 AU35 AU36 AU37 AU38

UC1N

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

SKL-H_BGA1440

SKYLAKE_HALO

BGA144 0

14 OF 14

VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX

VCCGT_SENSE

VSSGTX_SENSE

VSSGT_SENSE

VCCGTX_SENSE

AF29 AF30 AF31 AF32 AF33 AF34 AG13 AG14 AG31 AG32 AG33 AG34 AG35 AG36 AH13 AH14 AH29 AH30 AH31 AH32 AJ13 AJ14

AH38 AH35 AH37 AH36

VCCGT_SENSE

VSSGT_SENSE

Trace Length < 25 mils

VCCGT_SENSE <52>

VSSGT_SENSE <52>

Security Classification

2016/11/03 2017/01/10

Issued Date

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/11/03 2017/01/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

SKL-H(5/9)Power,SVID

C5MMH M/B LA-E911P

10 64Tuesday, April 11, 2017

CC69

+VDDQ_CLK

(1.35V)

+1.0V_VCCST

BSC Side

10U_0603_6.3V6M

CC70

+VCCSFR_OC_1

+VCCSFR_OC_2

1U_0402_6.3V6K

CC71

Place at Back Side

CC67 1U_0402_6.3V6K

Place at Back Side

1U_0402_6.3V6K

CC72

+1.2V_VDDQ_CPU

For Power consumption

VCCSA_SENSE VSSSA_SENSE

VCCIO_SENSE VSSIO_SENSE

Measure ment

JUMP_43X118

+VDDQ_CLK

+VCCSFR_OC_1 +VCCSFR_OC_2

+1.0V_VCCST

+1.0VS_VCCSTG

+1.0V_VCCSFR

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VDDQC

VCCPLL_OC VCCPLL_OC

VCCST

VCCSTG

VCCPLL VCCPLL

VCCSA_SENSE VSSSA_SENSE

VCCIO_SENSE

VSSIO_SENSE

DDR4/2.8A

AA6 AE12 AF5 AF6 AG5 AG9 AJ12 AL11 AP6 AP7 AR12 AR6 AT12 AW6 AY6 J5 J6 K12 K6 L12 L6 R6 T6 W6

Y12

BH13 G11

H30

H29

G30

H28 J28

M38 M37

H14 J14

20mA

150mA

SKYLAKE_HALO

K29 K30 K31 K32 K33 K34 K35

M29 M30 M31 M32 M33 M34 M35 M36

AG12

G15 G17 G19 G21 H15 H16 H17 H19 H20 H21 H26 H27

UC1I

J30

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

L31

VCCSA

L32

VCCSA

L35

VCCSA

L36

VCCSA

L37

VCCSA

L38

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

J15

VCCIO

J16

VCCIO

J17

VCCIO

J19

VCCIO

J20

VCCIO

J21

VCCIO

J26

VCCIO

J27

VCCIO

BGA144 0

RVP11 47u*1,10u*7,1u*3 CAP place on PWR side.

1 1

RVP11 PWR NEED PROVIDE

0.95V FOR VCCIO

+VCC_SA

H-4+2/11.1A

+1.0VS_VCCIO

H /5.5A

2 2

+1.2V_VDDQ

JPC1

JPC2

130mA

VCCSA_SENSE <52> VSSSA_SENSE <52>

VCCIO_SENSE <51> VSSIO_SENSE <51>

+1.2V_VDDQ_CPU

RC40

1 2

0_0603_5%

Place at Back Side

+1.2V_VDDQ

1 2

RC41 0_0402_5%

1 2

RC42 0_0402_5%

NOTE: VCCPLL_OC is allowed to be turned off during S3 & DS3 if it is not powered directly from VDDQ

+1.0VS_VCCSTG

(1.0VS)

1U_0402_6.3V6K

CC68

9 OF 14

SKL-H_BGA1440

REV = 1

3 3

+1.2V_VDDQ_CPU

10U_0603_6.3V6M

CC73

4 4

CPU_CORE/VCCGT/VCCSA decoupling capacitor place to PWR side

10U_0603_6.3V6M

CC74

CC75

10U_0603_6.3V6M

CC76

+1.2V_VDDQ_CPU : 10UF/6.3V/0603 *10 22UF/6.3V/0603 * 4 update CRB cap QTY

CC77

10U_0603_6.3V6M

CC79

CC78

+1.0VS_VCCIO

22U_0603_6.3V6M

10U_0603_6.3V6M

CC80

10U_0603_6.3V6M

CC81

CC82

22U_0603_6.3V6M

CC83

CC84

Place at Back Side

Security Classification

Issued Date

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/11/03 2017/01/10

22U_0603_6.3V6M

CC86

CC85

Place at Back Side

Compal Secret Data

Deciphered Date

10U_0603_6.3V6M

CC91

10U_0603_6.3V6M

CC92

+1.0V_VCCST

10U_0603_6.3V6M

CC89

+1.0V_VCCSFR

1 2

RC39 0_0402_5%@

22U_0603_6.3V6M

CC90

CC87

CC88

1 2

CC66 1U_0402_6.3V6K

22U_0603_6.3V6M

CC93

Follow ORB 3/20

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

SKL-H(6/9)POWER

C5MMH M/B LA-E911P

11 64Tuesday, April 11, 2017

BM9 BM6 BM2

C17 C13

BT9 BT5

BR7

BP7

BN9 BN7 BN4 BN2

BH9 BH8 BH5 BH4 BH1

BE6 BD9

SKYLAKE_HALO

UC1L

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKL-H_BGA1440

REV = 1

BGA144 0

12 OF 14

NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS

C25 C23 C21 C19 C15 C11 C8 C5 BM29 BM25 BM18 BM11 BM8 BM7 BM5 BM3 BL38 BL35 BL13 BL6 BK25 BK22 BK13 BK6 BJ30 BJ29 BJ15 BJ12 BH11 BH10 BH7 BH6 BH3 BH2 BG37 BG14 BG6 BF34 BF6 BE30 BE5 BE4 BE3 BE2 BE1 BD38 BD37 BD12 BD11 BD10 BD8 BD7 BD6 BC33 BC14 BC13 BC6 BB30 BB29 BB6 BB5

C2 BT36 BT35 BT4 BT3 BR38

SKYLAKE_HALO

UC1J

REV = 1

BGA144 0

10 OF 14

BJ17

VCCOPC

BJ19

VCCOPC

BJ20

VCCOPC

BK17

VCCOPC

BK19

VCCOPC

BK20

VCCOPC

BL16

1 1

EDRAM

CRB EDRAM

2 2

3 3

T4 @ T5 @ T6 @

OPC_RCOMP OPCE_RCOMP OPCE_RCOMP2

BL17 BL18 BL19 BL20

BL21 BM17 BN17

BJ23

BJ26

BJ27 BK23 BK26 BK27

BL23

BL24

BL25

BL26

BL27

BL28 BM24

BL15 BM16

BL22 BM22

BP15 BR15

BT15

BP16 BR16

BT16

BN15 BM15

BP17 BN16

BM14

BL14

BJ35

BJ36

AT13

AW13

AU13 AY13

BT29 BR25 BP25

VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC

RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

VCCOPC_SENSE VSSOPC_SENSE

RSVD RSVD

VCCEOPIO VCCEOPIO VCCEOPIO

RSVD RSVD RSVD

VCCEOPIO_SENSE VSSEOPIO_SENSE

RSVD RSVD

VCC_OPC_1P8 VCC_OPC_1P8

RSVD RSVD

ZVM# MSM#

ZVM2# MSM2#

OPC_RCOMP OPCE_RCOMP OPCE_RCOMP2

SKL-H_BGA1440

Y38 Y37 Y14 Y13 Y11 Y10

W34 W33 W12

V30 V29 V12

U38 U37

T34 T33 T14 T13 T12 T11 T10

R30 R29 R12

P38

P37

P12

N34 N33 N12

N11 N10

M14 M13 M12

L34

L33

L30

L29

K38

K11

K10

Y9 Y8 Y7

W5 W4 W3 W2 W1

T9 T8 T7

T4 T3 T2 T1

N9 N8 N7 N6 N5 N4 N3 N2 N1

K9 K8 K7 K5 K4 K3 K2

SKL-H_BGA1440

UC1F

SKYLAKE_HALO

BGA144 0

6 OF 14

NCTFVSS

SKYLAKE_HALO

UC1M

SKL-H_BGA1440

REV = 1

BGA144 0

13 OF 14

NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS

AK30 AK29 AK4 AJ38 AJ37 AJ6 AJ5 AJ4 AJ3 AJ2 AJ1 AH34 AH33 AH12 AH6 AG30 AG29 AG11 AG10 AG8 AG7 AG6 AF14 AF13 AF12 AF4 AF3 AF2 AF1 AE34 AE33 AE6 AD30 AD29 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AC38 AC37 AC12 AC6 AC5 AC4 AC3 AC2 AC1 AB34 AB33 AB6 AA30 AA29 AA12 A30 A28 A26 A24 A22 A20 A18 A16 A14 A12 A10 A9 A6

B37 B3 A34 A4 A3

BT32 BT26 BT24 BT21 BT18 BT14 BT12

BR36 BR34 BR29 BR26 BR24 BR21 BR18 BR14 BR12

BP34 BP33 BP29 BP26 BP24 BP21 BP18 BP14 BP12

BN34 BN31 BN30 BN29 BN24 BN21 BN20 BN19 BN18 BN14 BN12

BM38 BM35 BM28 BM27 BM26 BM23 BM21 BM13 BM12

BL29 BK29 BK15 BK14

BJ32 BJ31 BJ25

BJ22 BH14 BH12

BG38 BG13 BG12 BF33 BF12 BE29

BC34 BC12 BB12

BA38 BA37 BA12 BA11 BA10

AY34 AY33 AY14

AY12 AW30 AW29 AW12

AW5 AW4 AW3 AW2

AW1 AV38 AV37 AU34 AU33 AU12 AU11 AU10

AT30 AT29

AR38 AR37 AR14 AR13

AP34 AP33 AP12 AP11 AP10

AN30 AN29 AN12

AM38 AM37 AM12

AM5 AM4 AM3 AM2

AM1 AL34 AL33 AL14 AL12 AL10

BB4 BB3 BB2 BB1

BA9 BA8 BA7 BA6

AU9 AU8 AU7 AU6

AT6

AR5 AR4 AR3 AR2 AR1

AP9 AP8

AN6 AN5

AL9 AL8 AL7 AL4

K1 J36 J33 J32 J25 J22 J18 J10 J7 J4 H35 H32 H25 H22 H18 H12 H11 G28 G26 G24 G23 G22 G20 G18 G16 G14 G12 G10 G9 G8 G6 G5 G4 F36 F31 F29 F27 F25 F23 F21 F19 F17 F15 F13 F11 F9 F8 F5 F4 F3 F2 E38 E35 E34 E9 E4 D33 D30 D28 D26 D24 D22 D20 D18 D16 D14 D12 D10 D9 D6 D3 C37 C31 C29 C27

D38

?REV = 1

4 4

Security Classification

2016/11/03 2017/01/10

Issued Date

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/11/03 2017/01/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

SKL-H(8/9)GND

C5MMH M/B LA-E911P

12 64Tuesday, April 11, 2017

+1.0VALW TO +1.0V_VCCST

1 1

+1.0VALW

+5VALW

CC98 1U_0402_6.3V6K

1.0 Modify

UC1K

RSVD_TP

BR1

RSVD_TP

BT2

RSVD_TP

BN35

RSVD

J24

2 2

PROC_TRIGIN_R<22>

PROC_TRIGOUT_R<22>

3 3

1 2

RC44

30_0402_1%

PROC_TRIGIN_R PROC_TRIGOUT

BN33

BL34

AE29 AA14

BR35 BR31 BH30

H24

N29 R14

A36 A37

H23

F30 E30

B30 C30

J23

RSVD RSVD RSVD RSVD

RSVD RSVD

PROC_TRIGIN PROC_TRIGOUT

RSVD RSVD

RSVD RSVD RSVD

SKL-H_BGA1440

SKYLAKE_HALO

BGA144 0

11 OF 14

Rev_0.53

RSVD_TP RSVD_TP

RSVD RSVD

VSS

RSVD_TP RSVD_TP

RSVD RSVD

VSS

RSVD_TP RSVD_TP

RSVD RSVD RSVD

NCTF NCTF NCTF NCTF NCTF NCTF

RC43

0_0402_5%

BM33 BL33

BJ14 BJ13

BK28 BJ28

BJ18

BJ16 BK16

BK24 BJ24

BK21 BJ21

BT17 BR17

BK18

BJ34 BJ33

G13 AJ8 BL31

NCTF_0

NCTF_1

B38

NCTF_2

BP1

NCTF_3

BR2

NCTF_4

NCTF_5

C38

?REV = 1

T7 PAD@ T8 PAD@ T9 PAD@ T10 PAD@ T11 PAD@ T12 PAD@

SYSON<39,43,48,50>

SUSP#<39,43,46,48,50,51>

0.1U_0201_10V6K

SUSP#

EN_1.0V_VCCSTU

CC95 1U_0402_6.3V6K

+1.0VALW TO +1.0VS_VCCSTG

VCCSTG and VCCIO SLEW RATE <=65us

+5VALW

CC99

RC46

0_0402_5%

1.0 Modify

CC94 1U_0402_6.3V6K

UC3

VBIAS

VCC_PAD

GND

AOZ1334DI-01_DFN8-7_3X3

+1.0V_VCCST: 60mA R ON = 4.5mΩ VDROP= 1.32mV Delay time: 270us

+1.0VALW

CC100 1U_0402_6.3V6K

UC4

VBIAS

VCC_PAD

AOZ1334DI-01_DFN8-7_3X3

CC102 1U_0402_6.3V6K@

+1.0VS_VCCSTG: 60mA R ON = 4.4mΩ VDROP= 11mV Delay time: 9.3us

OUT

GND

+1.0V_VCCST_L

+1.0VALW

7 5

1.0 Modify

+1.0VS_VCCSTG_IO

+1.0VALW

+1.0V_VCCST

JC1

112

JUMP_43X79

RH169 0_0805_5%@

RC45 0_0805_5%

CC96

0.1U_0201_10V6K

UNPOP Default use POWER side

+1.0VS_VCCIO

1 2

+1.0VS_VCCSTG

1 2

CC101

0.1U_0201_10V6K

4 4

Security Classification

2016/11/03 2017/01/10

Issued Date

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/11/03 2017/01/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

SKL-H(9/9)RSVD

C5MMH M/B LA-E911P

13 64Tuesday, April 11, 2017

DDR_A_DQS#[0..7]<7>

DDR_A_D[0..63]<7>

DDR_A_DQS[0..7]<7>

DDR_A_MA[0..16]<7>

DDR_A_BA0<7>

DDR_A_BA1<7>

DDR_A_BG0<7>

CD4

10U_0603_6.3V6M

DDR_A_BG1<7>

DDR_A_CLK0<7> DDR_A_CLK#0<7> DDR_A_CLK1<7>

DDR_A_CLK#1<7>

DDR_A_CKE0<7>

DDR_A_CKE1<7>

DDR_A_CS#0<7>

DDR_A_CS#1<7>

D_CK_SDATA<15,18,38> D_CK_SCLK<15,18,38>

DDR_A_ODT0<7>

DDR_A_ODT1<7>

1U_0402_6.3V6K

CD28

CD5

CD19

10U_0603_6.3V6M

+0.6VS_VTT

1U_0402_6.3V6K

CD29

CD6

10U_0603_6.3V6M

CD20

1U_0402_6.3V6K

+3VS

1 1

Layout Note: Place near JDIMM1

2 2

+1.2V_VDDQ

1U_0402_6.3V6K

+1.2V_VDDQ

10U_0603_6.3V6M

CD18

3 3

4 4

Layout Note: Place near JDIMM1.258

Layout Note: Place near JDIMM1.255

DDR_A_BA0 DDR_A_BA1 DDR_A_BG0 DDR_A_BG1

DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1

DDR_A_CKE0 DDR_A_CKE1 DDR_A_CS#0 DDR_A_CS#1

D_CK_SDATA D_CK_SCLK

DDR_A_ODT0 DDR_A_ODT1

Note: place caps close to DIMM 4 on each side of DIMM

1U_0402_6.3V6K

CD21

CD30

0_0402_5%

1U_0402_6.3V6K

CD8

CD7

10U_0603_6.3V6M

CD22

1U_0402_6.3V6K

CD31

RD8

1U_0402_6.3V6K

CD9

10U_0603_6.3V6M

CD23

10U_0603_6.3V6M

CD32

Place Holder

CD35

0.1U_0201_10V6K

1U_0402_6.3V6K

CD10

10U_0603_6.3V6M

CD24

10U_0603_6.3V6M

CD33

+3VS_DIMMA

CD36

2.2U_0402_6.3V6M

+1.2V_VDDQ

1U_0402_6.3V6K

CD11

CD25

CD12

Follow MA51

CD26 330U_D2_2V_Y

SGA00009S00 330U 2V H1.9 9mohm POLY

+0.6V_DDRA_VREFCA

CPU Side

+0.6V_VREFCA

CD2

0.022U_0402_16V7K

RD4

24.9_0402_1%

Place near to SO-DIMM connector.

CD13

0.1U_0201_10V6K

CD38

CD37

0.1U_0201_10V6K

2.2U_0402_6.3V6M

Layout Note: Place near JDIMM1.257/259

Layout Note: Place near JDIMM1.164 within 200mils

RD2 2_0402_1%

1U_0402_6.3V6K

+1.2V_VDDQ

RD1

1 2

RD3

1 2

+2.5V

CD15

CD14

1U_0402_6.3V6K

DDR_DRAMRST#<18>

*2015MOW02, Can't install Cap on DRAMRST

Layout Note: Place near JDIMM1.164

CD1

1K_0402_1%

0.1U_0201_10V6K

CD3

1K_0402_1%

0.1U_0201_10V6K

CD17

CD16

10U_0603_6.3V6M

XEMC@

CD34

100P_0402_50V8J

Dimm1 Side

+0.6V_DDRA_VREFCA

+1.2V_VDDQ

RD7

0_0402_5%

Layout NOTE PLACE THE CAP within 200mil from Pin108

#543016 PDG 1.0164 20mils wide & spacing

DDR_A_ACT#<7>

DDR_A_PARITY<7> DDR_A_ALERT#<7>

1 2

RD5 240_0402_1%

SPD Address for CHANNEL0 Write Adress 0xA0 Read Address 0xA1 SA0=0;SA1 =0;SA2=0

+1.2V_VDDQ

RD6 470_0402_5%

1 2

CD27

0.1U_0201_10V6K

Security Classifica tion

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAIN S

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAIN S

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAIN S MAY BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1

DDR_A_CKE0 DDR_A_CKE1

DDR_A_CS#0 DDR_A_CS#1

DDR_A_ODT0 DDR_A_ODT1

DDR_A_BG0 DDR_A_BG1 DDR_A_BA0 DDR_A_BA1

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 DDR_A_MA16

DDR_A_ACT#

DDR_A_PARITY DDR_A_ALERT# DDR_A_EVENT# DDR_DRAMRST#_R

D_CK_SDATA D_CK_SCLK

DDR_A_SA2 DDR_A_SA1 DDR_A_SA0

+1.2V_VDDQ

DDR_DRAMRST#_R <15>

2016/11/03 2017/01/10

JDIMM1A

REVERSE

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

133

132

131

128

126

127

122

125

121

146

A10_AP

120

A11

119

A12

158

A13

151

A14_WE#

156

A15_CAS#

152

A16_RAS#

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

CB0_NC

CB1_NC

101

CB2_NC

105

CB3_NC

CB4_NC

CB5_NC

100

CB6_NC

104

CB7_NC

DQS8(T)

DQS8#(C)

DM0#/DBI0#

DM1#/DBI1#

DM2#/DBI2#

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7#

DM8#/DBI8#

LOTES_ADDR0206-P001A

CONN@

Compal S ecret Data

Deciphered Date

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

DQS0(T)

DQS0#(C)

DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

DQS1(T)

DQS1#(C)

DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23

DQS2(T)

DQS2#(C)

DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS3(T)

DQS3#(C)

DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39

DQS4(T)

DQS4#(C)

DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47

DQS5(T)

DQS5#(C)

DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55

DQS6(T)

DQS6#(C)

DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

DQS7(T)

DQS7#(C)

8 7 20 21 4 3 16 17 13 11

28 29 41 42 24 25 38 37 34 32

50 49 62 63 46 45 58 59 55 53

70 71 83 84 66 67 79 80 76 74

174 173 187 186 170 169 183 182 179 177

195 194 207 208 191 190 203 204 200 198

216 215 228 229 211 212 224 225 221 219

237 236 249 250 232 233 245 246 242 240

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_DQS0 DDR_A_DQS#0

DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_DQS1 DDR_A_DQS#1

DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_DQS2 DDR_A_DQS#2

DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_DQS3 DDR_A_DQS#3

DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_DQS4 DDR_A_DQS#4

DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_DQS5 DDR_A_DQS#5

DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_DQS6 DDR_A_DQS#6

DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 DDR_A_DQS7 DDR_A_DQS#7

+1.2V_VDDQ +1.2V_VDDQ

+0.6V_DDRA_VREFCA

+3VS_DIMMA

Interleaved Memory

Title

Size Document Number Rev

Custom

Date: Sheet of

Reverse Type-4H

2-3A to 1 DIMMs/channel

JDIMM1B

REVERSE

111

VDD1

112

VDD2

117

VDD3

118

VDD4

123

VDD5

124

VDD6

129

VDD7

130

VDD8

135

VDD9

136

VDD10

255

VDDSPD

164

VREFCA

VSS

262

GND

LOTES_ADDR0206-P001A

CONN@

Compal Electronics, Inc.

DDR4_DIMMA

C5MMH M/B LA-E911P

VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19

VPP1 VPP2

GND

VTT

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

141 142 147 148 153 154 159 160 163

+0.6VS_VTT

258

257 259

99 102 103 106 107 167 168 171 172 175 176 180 181 184 185 188 189 192 193 196 197 201 202 205 206 209 210 213 214 217 218 222 223 226 227 230 231 234 235 238 239 243 244 247 248 251 252

261

+2.5V

14 64Tuesday, April 11, 2017

DDR_B_DQS#[0..7]<7>

DDR_B_D[0..63]<7>

DDR_B_DQS[0..7]<7>

DDR_B_MA[0..16]<7>

DDR_B_BA0<7> DDR_B_BA1<7>

1 1

Layout Note: Place near JDIMM2

2 2

+1.2V_VDDQ

10U_0603_6.3V6M

3 3

Layout Note: Place near JDIMM2.258

4 4

Layout Note: Place near JDIMM1.255

DDR_B_BG0<7> DDR_B_BG1<7>

DDR_B_CLK0<7> DDR_B_CLK#0<7> DDR_B_CLK1<7> DDR_B_CLK#1<7>

DDR_B_CKE0<7> DDR_B_CKE1<7> DDR_B_CS#0<7> DDR_B_CS#1<7>

D_CK_SDATA<14,18,38> D_CK_SCLK<14,18,38>

DDR_B_ODT0<7> DDR_B_ODT1<7>

1U_0402_6.3V6K

CD56

CD42

10U_0603_6.3V6M

1U_0402_6.3V6K

CD66

CD43

CD57

10U_0603_6.3V6M

+0.6VS_VTT

1U_0402_6.3V6K

CD67

CD44

10U_0603_6.3V6M

CD58

DDR_B_BA0 DDR_B_BA1 DDR_B_BG0 DDR_B_BG1

DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK1 DDR_B_CLK#1

DDR_B_CKE0 DDR_B_CKE1

DDR_B_CS#0

DDR_B_CS#1

D_CK_SDATA DDR_B_MA2 D_CK_SCLK

DDR_B_ODT0 DDR_B_ODT1

Note: place caps close to DIMM 4 on each side of DIMM

+1.2V_VDDQ

1U_0402_6.3V6K

CD72

CD48

10U_0603_6.3V6M

CD62

10U_0603_6.3V6M

CD71

CD49

CD63

+3VS_DIMMB

CD73

2.2U_0402_6.3V6M

+3VS

1U_0402_6.3V6K

CD59

CD68

CD45

10U_0603_6.3V6M

1U_0402_6.3V6K

RD15

0_0402_5%

1U_0402_6.3V6K

CD46

10U_0603_6.3V6M

CD60

CD69

Place Holder

1U_0402_6.3V6K

CD47

10U_0603_6.3V6M

CD61

10U_0603_6.3V6M

CD70

0.1U_0201_10V6K

CPU Side

+0.6V_B_VREFDQ +0.6V_DDRB_VREFCA

CD40

0.022U_0402_16V7K

RD12

24.9_0402_1%

Place near to SO-DIMM connector.

CD50

CD51

0.1U_0201_10V6K

Follow MA51

CD64 330U_D2_2V_Y

SGA00009S00 330U 2V H1.9 9mohm POLY

+0.6V_DDRB_VREFCA

CD74

+1.2V_VDDQ

CD39

RD9

1K_0402_1%

RD11

1K_0402_1%

1U_0402_6.3V6K

1 2

CD53

CD52

1U_0402_6.3V6K

RD10 2_0402_1%

Layout Note: Place near JDIMM2.257/259

0.1U_0201_10V6K

+2.5V

0.1U_0201_10V6K

Dimm2 Side

Layout Note: Place near JDIMM2.164

20mils wide & spacing

CD41

0.1U_0201_10V6K

CD54

CD55

10U_0603_6.3V6M

Layout NOTE PLACE THE CAP within 200mil from Pin108

+1.2V_VDDQ

DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK1 DDR_B_CLK#1

DDR_B_CKE0 DDR_B_CKE1

DDR_B_CS#0 DDR_B_CS#1

DDR_B_ODT0 DDR_B_ODT1

DDR_B_ACT#<7>

DDR_B_PARITY<7> DDR_B_ALERT#<7>

1 2

RD13 240_0402_1%

+3VS

1 2

SPD Address for CHANNELB Write Adress 0xA4 Read Address 0xA3 SA0=0;SA1 =1;SA2=0

From CPU to CHB

CD65

0.1U_0201_10V6K

DDR_B_ACT#

DDR_B_PARITY DDR_B_ALERT# DDR_B_EVENT# DDR_DRAMRST#_R

D_CK_SDATA D_CK_SCLK

RD14

0_0402_5%

+1.2V_VDDQ

DDR_DRAMRST#_R <14>

DDR_B_BG0 DDR_B_BG1 DDR_B_BA0 DDR_B_BA1

DDR_B_MA0 DDR_B_MA1

DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 DDR_B_MA16

DDR_B_SA2 DDR_B_SA1 DDR_B_SA0

JDIMM2A

RESERVE

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

133

132

131

128

126

127

122

125

121

146

A10_AP

120

A11

119

A12

158

A13

151

A14_WE#

156

A15_CAS#

152

A16_RAS#

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

CB0_NC

CB1_NC

101

CB2_NC

105

CB3_NC

CB4_NC

CB5_NC

100

CB6_NC

104

CB7_NC

DQS8(T)

DQS8#(C)

DM0#/DBI0#

DM1#/DBI1#

DM2#/DBI2#

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7#

DM8#/DBI8#

LOTES_ADDR0070-P009A

CONN@

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

DQS0(T)

DQS0#(C)

DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

DQS1(T)

DQS1#(C)

DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23

DQS2(T)

DQS2#(C)

DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS3(T)

DQS3#(C)

DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39

DQS4(T)

DQS4#(C)

DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47

DQS5(T)

DQS5#(C)

DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55

DQS6(T)

DQS6#(C)

DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

DQS7(T)

DQS7#(C)

8 7 20 21 4 3 16 17 13 11

28 29 41 42 24 25 38 37 34 32

50 49 62 63 46 45 58 59 55 53

70 71 83 84 66 67 79 80 76 74

174 173 187 186 170 169 183 182 179 177

195 194 207 208 191 190 203 204 200 198

216 215 228 229 211 212 224 225 221 219

237 236 249 250 232 233 245 246 242 240

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_DQS0 DDR_B_DQS#0

DDR_B_D8 DDR_B_D9 DDR_B_D11 DDR_B_D15 DDR_B_D14 DDR_B_D10 DDR_B_D12 DDR_B_D13 DDR_B_DQS1 DDR_B_DQS#1

DDR_B_D16 DDR_B_D17 DDR_B_D19 DDR_B_D20 DDR_B_D22 DDR_B_D18 DDR_B_D23 DDR_B_D21 DDR_B_DQS2 DDR_B_DQS#2

DDR_B_D30 DDR_B_D25 DDR_B_D26 DDR_B_D24 DDR_B_D28 DDR_B_D27 DDR_B_D29 DDR_B_D31 DDR_B_DQS3 DDR_B_DQS#3

DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D32 DDR_B_D39 DDR_B_D38 DDR_B_D37 DDR_B_D33 DDR_B_DQS4 DDR_B_DQS#4

DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_DQS5 DDR_B_DQS#5

DDR_B_D48 DDR_B_D52 DDR_B_D50 DDR_B_D55 DDR_B_D51 DDR_B_D54 DDR_B_D49 DDR_B_D53 DDR_B_DQS6 DDR_B_DQS#6

DDR_B_D61 DDR_B_D57 DDR_B_D60 DDR_B_D56 DDR_B_D62 DDR_B_D59 DDR_B_D63 DDR_B_D58 DDR_B_DQS7 DDR_B_DQS#7

+1.2V_VDDQ

+0.6V_DDRB_VREFCA

Reverse Type-8H

2-3A to 1 DIMMs/channel

JDIMM2B

RESERVE

111

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10

VDDSPD

VREFCA

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

GND

VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19

VPP1 VPP2

GND

+3VS_DIMMB

112 117 118 123 124 129 130 135 136

255

164

1 2 5 6

9 10 14 15 18 19 22 23 26 27 30 31 35 36 39 40 43 44 47 48 51 52 56 57 60 61 64 65 68 69 72 73 77 78 81 82 85 86 89 90 93 94 98

262

LOTES_ADDR0070-P009A

CONN@

VTT

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

+1.2V_VDDQ

141 142 147 148 153 154 159 160 163

+0.6VS_VTT

258

257 259

99 102 103 106 107 167 168 171 172 175 176 180 181 184 185 188 189 192 193 196 197 201 202 205 206 209 210 213 214 217 218 222 223 226 227 230 231 234 235 238 239 243 244 247 248 251 252

261

+2.5V

*2015MOW02, Can't install Cap on DRAMRST

CD75

Layout Note:

0.1U_0201_10V6K

Place near JDIMM1.164

2.2U_0402_6.3V6M

within 200mils

Security Classifica tion

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAIN S

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAIN S

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAIN S MAY BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/11/03 2017/01/10

Compal S ecret Data

Deciphered Date

Interleaved Memory

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

DDR4_DIMMB

C5MMH M/B LA-E911P

15 64Tuesday, April 11, 2017

UH1F

C11

USB3_1_TXN

B11

USB3_1_TXP

USB3_1_RXN

USB3_1_RXP

USB3_PTX_DRX_N2<35> USB3_PTX_DRX_P2<35>

1 2

USB3_PRX_DTX_N2<35> USB3_PRX_DTX_P2<35>

USB3_PTX_DRX_N5<33> USB3_PTX_DRX_P5<33> USB3_PRX_DTX_N5<33> USB3_PRX_DTX_P5<33>

USB3_PTX_DRX_P3<36> USB3_PTX_DRX_N3<36> USB3_PRX_DTX_P3<36> USB3_PRX_DTX_N3<36>

USB3_PTX_DRX_P4<36> USB3_PTX_DRX_N4<36> USB3_PRX_DTX_P4<36> USB3_PRX_DTX_N4<36>

DMI_CTX_PRX_N0 DMI_CTX_PRX_P0 DMI_CRX_PTX_N0 DMI_CRX_PTX_P0 DMI_CTX_PRX_N1 DMI_CTX_PRX_P1 DMI_CRX_PTX_N1 DMI_CRX_PTX_P1 DMI_CTX_PRX_N2 DMI_CTX_PRX_P2 DMI_CRX_PTX_N2 DMI_CRX_PTX_P2 DMI_CTX_PRX_N3 DMI_CTX_PRX_P3 DMI_CRX_PTX_N3 DMI_CRX_PTX_P3

PCIE_RCOMPN PCIE_RCOMPP

PCIE_PRX_DTX_N3

PCIE_PRX_DTX_P3

12 12

PCIE_PTX_DRX_N3

PCIE_PTX_DRX_P3

PCIE_PRX_DTX_N4

PCIE_PRX_DTX_P4

PCIE_PTX_DRX_N4

PCIE_PTX_DRX_P4

1 1

USB3 MB

USB3 SUB

USB3 Type C

2 2

DMI_CTX_PRX_N0<8> DMI_CTX_PRX_P0<8> DMI_CRX_PTX_N0<8> DMI_CRX_PTX_P0<8> DMI_CTX_PRX_N1<8> DMI_CTX_PRX_P1<8> DMI_CRX_PTX_N1<8> DMI_CRX_PTX_P1<8> DMI_CTX_PRX_N2<8> DMI_CTX_PRX_P2<8> DMI_CRX_PTX_N2<8> DMI_CRX_PTX_P2<8> DMI_CTX_PRX_N3<8> DMI_CTX_PRX_P3<8> DMI_CRX_PTX_N3<8> DMI_CRX_PTX_P3<8>

RH6 100_0402_1%

#546884 P.231 PCIE_RCOMPN/PCIE_RCOMPP BO=4 W=12~15 S=12 R=100ohm

3 3

NGFF WL+BT(KEY E)

GLAN

PCIE_PRX_DTX_N3<37>

PCIE_PRX_DTX_P3<37> PCIE_PTX_C_DRX_N3<37> PCIE_PTX_C_DRX_P3<37>

PCIE_PRX_DTX_N4<32>

PCIE_PRX_DTX_P4<32>

PCIE_PTX_C_DRX_N4<32>

PCIE_PTX_C_DRX_P4<32>

CH5 .1U_0402_16V7K CH6 .1U_0402_16V7K

CH7 .1U_0402_16V7K CH8 .1U_0402_16V7K

B12

USB3_2_TXN/SSIC_1_TXN

A12

USB3_2_TXP/SSIC_1_TXP

USB3_2_RXN/SSIC_1_RXN

USB3_2_RXP/SSIC_1_RXP

B15

USB3_6_TXN

C15

USB3_6_TXP

K15

USB3_6_RXN

K13

USB3_6_RXP

B14

USB3_5_TXN

C14

USB3_5_TXP

G13

USB3_5_RXN

H13

USB3_5_RXP

D13

USB3_3_TXP/SSIC_2_TXP

C13

USB3_3_TXN/SSIC_2_TXN

USB3_3_RXP/SSIC_2_RXP

B10

USB3_3_RXN/SSIC_2_RXN

B13

USB3_4_TXP

A14

USB3_4_TXN

G11

USB3_4_RXP

E11

USB3_4_RXN

SKL-H-PCH_BGA837

L27 N27 C27

B27

E24 G24

B28

A28 G27

E26

B29 C29

L29

K29

B30

A30

B18 C17

H15 G15

A16

B16

B19 C19

E17 G17

L17

K17

B20 C20

E20 G19

B21

A21

K19

L19 D22 C22 G22

E22

B22

A23

L22

K22 C23

B23

K24

L24 C24

B24

SPT-H_PCH

LPC/eSPI

USB

REV = 1.3

UH1B

DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0 DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1 DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2 DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3

PCIE_RCOMPN PCIE_RCOMPP

PCIE1_RXN/USB3_7_RXN PCIE1_RXP/USB3_7_RXP PCIE1_TXN/USB3_7_TXN PCIE1_TXP/USB3_7_TXP PCIE2_TXN/USB3_8_TXN PCIE2_TXP/USB3_8_TXP PCIE2_RXN/USB3_8_RXN PCIE2_RXP/USB3_8_RXP PCIE3_RXN/USB3_9_RXN PCIE3_RXP/USB3_9_RXP PCIE3_TXN/USB3_9_TXN PCIE3_TXP/USB3_9_TXP PCIE4_RXN/USB3_10_RXN PCIE4_RXP/USB3_10_RXP PCIE4_TXN/USB3_10_TXN PCIE4_TXP/USB3_10_TXP PCIE5_RXN PCIE5_RXP PCIE5_TXN PCIE5_TXP PCIE6_RXN PCIE6_RXP PCIE6_TXN PCIE6_TXP PCIE7_RXN PCIE7_RXP PCIE7_TXN PCIE7_TXP PCIE8_RXN PCIE8_RXP PCIE8_TXN PCIE8_TXP

SKL-H-PCH_BGA837

REV = 1.3

GPP_A1/LAD 0/ESPI_IO0 GPP_A2/LAD 1/ESPI_IO1 GPP_A3/LAD 2/ESPI_IO2 GPP_A4/LAD 3/ESPI_IO3

GPP_A5/LFR AME#/ESPI_CS0#

GPP_A6/SER IRQ/ESPI_CS1#

GPP_A7/PIRQA #/ESPI_ALERT0#

GPP_A0/RCIN #/ESPI_ALERT1#

GPP_A14/SU S_STAT#/ESPI_RE SET#

GPP_A9/CLK OUT_LPC0/ESPI_CL K

GPP_A10/CLK OUT_LPC1

GPP_G19/SMI# GPP_G18/NMI#

GPP_E6/DEV SLP2 GPP_E5/DEV SLP1 GPP_E4/DEV SLP0

USB 2.0

2 OF 12

GPP_F9/DEV SLP7 GPP_F8/DEV SLP6 GPP_F7/DEV SLP5 GPP_F6/DEV SLP4 GPP_F5/DEV SLP3

GPP_E9/USB 2_OC0# GPP_E10/US B2_OC1# GPP_E11/US B2_OC2# GPP_E12/US B2_OC3#

GPP_F15/US B2_OCB_4 GPP_F16/US B2_OCB_5 GPP_F17/US B2_OCB_6 GPP_F18/US B2_OCB_7

USB2_VBUSSENSE

SATA

6 OF 12

SPT-H_PCH

DMI

PCIe/USB 3

USB2N_1 USB2P_1 USB2N_2 USB2P_2 USB2N_3 USB2P_3 USB2N_4 USB2P_4 USB2N_5 USB2P_5 USB2N_6 USB2P_6 USB2N_7 USB2P_7 USB2N_8 USB2P_8 USB2N_9

USB2P_9 USB2N_10 USB2P_10 USB2N_11 USB2P_11 USB2N_12 USB2P_12 USB2N_13 USB2P_13 USB2N_14 USB2P_14

USB2_COMP

RSVD_AB13

USB2_ID

GPD7/RSVD

AT22 AV22 AT19 BD16

BE16 BA17 AW17 AT17 BC18

BC17 AV19

M45 N43

AE45 AG43 AG42 AB39 AB36 AB43 AB42 AB41

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

LPC_FRAME# TPM_SERIRQ LPC_PIRQA#

ESPI_RST#

CLK_LPC CLK_LPC_TPM

SSD_DEVSLP0

AF5 AG7

USB20_N2

AD5

USB20_P2

AD7

USB20_N3

AG8

USB20_P3

AG10 AE1 AE2

USB20_N5

AC2

USB20_P5

AC3

USB20_N6

AF2

USB20_P6

AF3

USB20_N7

AB3

USB20_P7

AB2

USB20_N8

AL8

USB20_P8

AL7

USB20_N9

AA1

USB20_P9

AA2

USB20_N10

AJ8

USB20_P10

AJ7 W2 W3 AD3 AD2 V2 V1 AJ11 AJ13

AD43 AD42 AD39 AC44 Y43 Y41 W44 W43

AG3 AD10 AB13 AG2

BD14

CHECK ACER DVR for port use 12/08 Change Port, follow DVR1044_R1.03

USB_OC0# USB_OC1# USB_OC2# USB_OC3# USB_OC4 USB_OC5 USB_OC6 USB_OC7

USB2_COMP USB2_VBUSSENSE

USB2_ID

546765_2015WW10_Skylake_MOW_Rev _1_0 05/19 RH150

LPC_AD0 <39,41> LPC_AD1 <39,41> LPC_AD2 <39,41> LPC_AD3 <39,41>

LPC_FRAME# <39,41> TPM_SERIRQ <39,41>

ESPI_RST# <39>

RH3 22_0402_5% RH4 22_0402_5%TPM @

12 12

SSD_DEVSLP0 <34>

USB20_N2 <35> USB20_P2 <35> USB20_N3 <36> USB20_P3 <36>

USB20_N5 <33> USB20_P5 <33> USB20_N6 <33> USB20_P6 <33> USB20_N7 <37> USB20_P7 <37> USB20_N8 <30> USB20_P8 <30> USB20_N9 <30> USB20_P9 <30> USB20_N10 <42> USB20_P10 <42>

USB_OC1# <35>

1 2

RH7 113_0402_1%

1 2

RH8 0_0402_5%@

1 2

RH9 0_0402_5%@

LPC Bus

LPC : +3.3V

To TPM

CLK_LPC_R <39> CLK_LPC_TPM_R <41>

USB3 MB

TYPE C

USB2 (SUB/B)

Camera

FingerPrin t

To EC

TPM_SERIRQ

DG requierment 8.2k PH +3VS CRB 10K PH +3vs

LPC_PIRQA#

1 2

RH1 10K_0402_5%

RH5 10K_0402_5%

1.0 Modify

USB_OC0#

EMC@

1 2

CH68 1000P_0402_50V7K

reference PDG1.0 50-30

USB_OC0# USB_OC1# USB_OC3# USB_OC2#

USB_OC5 USB_OC4 USB_OC6 USB_OC7

RPH1

18 27 36 45

10K_0804_8P4R_5%

RPH2

18 27 36 45

10K_0804_8P4R_5%

+3VS

+3VALW_PCH_PRIM

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/11/03 2017/01/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PCH(1/7)DMI,PCIE,USB

Size Document Number Rev

Custom

Date: Sheet of

PCH(1/7)DMI,PCIE,USB

C5MMH M/B LA-E911P

16 64Tuesday, April 11, 2017

Buf f er

1 2

EC_PME#<32,39>

1 1

SPI ROM

+3VALW_PCH_PRIM

RH42

10K_0402_5%

DIS,Optimus10

2 2

M.2 SSD PCIE L2

M.2 SSD PCIE L3

3 3

SPI ROM ( 8MByte )

PCH_SPI_CS#0

PCH_SPI_IO2_0_R

4 4

UMA@

RH43

VGA@

UMA

1.A Modify

PCH_SPI_CLK_0_R

DGPU_PRSNT#

GPP_F13

DGPU_PRSNT#

UH3

/CS

DO(IO1)

/WP(IO2)

GND

W25Q64FVSSIQ_SO8

SA000039A40

1 2

RH44 0_0402_5%

PCIE_PTX_DRX_P11<34> PCIE_PTX_DRX_N11<34>

PCIE_PRX_DTX_P11<34> PCIE_PRX_DTX_N11<34>

PCIE_PTX_DRX_P12<34> PCIE_PTX_DRX_N12<34> PCIE_PRX_DTX_P12<34> PCIE_PRX_DTX_N12<34>

VCC

/HOLD(IO3)

DI(IO0)

CLK

+3VALW_SPI

CH17 0.1U_0201_10V6K

PCH_SPI_IO3_0_RPCH_SPI_SO_0_R

PCH_SPI_CLK_0_R

PCH_SPI_SI_0_R

1 2

CH19 68P_0402_50V8J

1 2

RH10 0_0402_5%

PCH_SPI_SI PCH_SPI_SO PCH_SPI_CS#0 PCH_SPI_CLK

PCH_SPI_IO2 PCH_SPI_IO3

PCIE_PTX_DRX_P11 PCIE_PTX_DRX_N11 PCIE_PRX_DTX_P11 PCIE_PRX_DTX_N11

DGPU_PRSNT#

PCIE_PTX_DRX_P12 PCIE_PTX_DRX_N12 PCIE_PRX_DTX_P12 PCIE_PRX_DTX_N12

DVT modify

EC_PME#_R

BD17

AG15 AG14 AF17 AE17

AR19 AN17

BB29 BE30 BD31 BC31

AW31

BC29 BD30 AT31

AN36

AL39 AN41 AN38 AH43 AG44

UH1C

AV2

CL_CLK

AV3

CL_DATA

AW2

CL_RST#

R44

GPP_G8/FAN_ PWM_0

R43

GPP_G9/FAN_ PWM_1

U39

GPP_G10/FAN _PWM_2

N42

GPP_G11/FAN _PWM_3

U43

GPP_G0/FAN_ TACH_0

U42

GPP_G1/FAN_ TACH_1

U41

GPP_G2/FAN_ TACH_2

M44

GPP_G3/FAN_ TACH_3

U36

GPP_G4/FAN_ TACH_4

P44

GPP_G5/FAN_ TACH_5

T45

GPP_G6/FAN_ TACH_6

T44

GPP_G7/FAN_ TACH_7

B33

PCIE11_TXP

C33

PCIE11_TXN

K31

PCIE11_RXP

L31

PCIE11_RXN

AB33

GPP_F10/SC LOCK

AB35

GPP_F11/SLOA D

AA44

GPP_F13/SD ATAOUT0

AA45

GPP_F12/SD ATAOUT1

B38

PCIE14_TXN/SATA1B_TXN

C38

PCIE14_TXP/SATA1B_TXP

D39

PCIE14_RXN/SATA1B_RXN

E37

PCIE14_RXP/SATA1B_RXP

C36

PCIE13_TXN/SATA0B_TXN

B36

PCIE13_TXP/SATA0B_TXP

G35

PCIE13_RXN/SATA0B_RXN

E35

PCIE13_RXP/SATA0B_RXP

A35

PCIE12_TXP

B35

PCIE12_TXN

H33

PCIE12_RXP

G33

PCIE12_RXN

J45

PCIE20_TXP/SATA7_TXP

K44

PCIE20_TXN/SATA7_TXN

N38

PCIE20_RXP/SATA7_RXP

N39

PCIE20_RXN/SATA7_RXN

H44

PCIE19_TXP/SATA6_TXP

H43

PCIE19_TXN/SATA6_TXN

L39

PCIE19_RXP/SATA6_RXP

L37

PCIE19_RXN/SATA6_RXN

SKL-H-PCH_BGA837

Single SPI ROM_CS0#

UH1A

GPP_A11/PM E#

RSVD RSVD RSVD RSVD

TP2 TP1

SPI0_MOSI SPI0_MISO SPI0_CS0# SPI0_CLK SPI0_CS1# SPI0_IO2 SPI0_IO3 SPI0_CS2#

GPP_D1/SPI1 _CLK GPP_D0/SPI1 _CS# GPP_D3/SPI1 _MOSI GPP_D2/SPI1 _MISO GPP_D22/SP I1_IO3 GPP_D21/SP I1_IO2

SKL-H-PCH_BGA837

REV = 1.3

To SPI ROM

SPT-H_PCH

CLINK

FAN

PCH_SPI_CS#0

PCH_SPI_SI_0_R PCH_SPI_SO_0_R PCH_SPI_IO3_0_R PCH_SPI_CLK_0_R

GPP_B13/PLT RST#

GPP_G16/GSXC LK

GPP_G12/GSXD OUT

GPP_G13/GSXSL OAD

GPP_G14/GSXD IN

GPP_G15/GSXSR ESET#

GPP_E3/CPU _GP0 GPP_E7/CPU _GP1 GPP_B3/CPU _GP2 GPP_B4/CPU _GP3

GPP_H18/SM L4ALERT#

GPP_H17/SM L4DATA

GPP_H16/SM L4CLK

GPP_H15/SM L3ALERT#

GPP_H14/SM L3DATA

GPP_H13/SM L3CLK

GPP_H12/SM L2ALERT#

GPP_H11/SM L2DATA

GPP_H10/SM L2CLK

1 OF 12

PCIE9_RXN/SATA0A_RXN

PCIE9_RXP/SATA0A_RXP PCIE9_TXN/SATA0A_TXN

PCIE9_TXP/SATA0A_TXP

PCIE10_RXN/SATA1A_RXN PCIE10_RXP/SATA1A_RXP

PCIE10_TXN/SATA1A_TXN PCIE10_TXP/SATA1A_TXP

PCIE15_RXN/SATA2_RXN PCIE15_RXP/SATA2_RXP

PCIE15_TXN/SATA2_TXN PCIE15_TXP/SATA2_TXP

PCIe/SATA

PCIE16_RXN/SATA3_RXN PCIE16_RXP/SATA3_RXP

PCIE16_TXN/SATA3_TXN PCIE16_TXP/SATA3_TXP

PCIE17_RXN/SATA4_RXN PCIE17_RXP/SATA4_RXP

PCIE17_TXN/SATA4_TXN PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN PCIE18_RXP/SATA5_RXP

PCIE18_TXN/SATA5_TXN PCIE18_TXP/SATA5_TXP

GPP_E0/SAT AXPCIE0/SATAGP0 GPP_E1/SAT AXPCIE1/SATAGP1 GPP_E2/SAT AXPCIE2/SATAGP2 GPP_F0/SAT AXPCIE3/SATAGP3 GPP_F1/SAT AXPCIE4/SATAGP4 GPP_F2/SAT AXPCIE5/SATAGP5 GPP_F3/SAT AXPCIE6/SATAGP6 GPP_F4/SAT AXPCIE7/SATAGP7

GPP_F21/ED P_BKLTCTL

HOST

3 OF 12

1 2

RH35 4.7K_0402_5%

RPH3 and close UH6

RPH3

1 8 2 7 3 6 4 5

15_0804_8P4R_5%

1 2

RH38 15_0402_5%

PLT_RST#

BB27

P43 R39 R36 R42 R41

AF41 AE44 BC23 BD24

BC36 BE34 BD39 BB36 BA35 BC35 BD35 AW35 BD34

BE11

INTRUDER #

GPP_E8/SAT ALED#

GPP_F20/ED P_BKLTEN

GPP_F19/ED P_VDDEN

THERMTRIP#

PECI

PM_SYNC

PLTRST_PROC#

PM_DOWN

+3VALW_SPI

TP_INT#

for server and WS use

SM_INTRUDER#

G31 H31 C31 B31

G29 E29 C32 B32

F41 E41 B39 A39

D43 E42 A41 A40

H42 H40 E45 F45

K37 G37 G45 G44

AD44 AG36 AG35 AG39 AD35 AD31 AD38 AC43 AB44

W36 W35 W42

AJ3 AL3 AJ4 AK2 AH2

PLT_RST# <23,39,41>

DH1 RB751V-40_SOD323-2

T14

PAD

RH12

1M_0402_5%

1 2

PCIE_PRX_DTX_N9 PCIE_PRX_DTX_P9 PCIE_PTX_DRX_N9 PCIE_PTX_DRX_P9

PCIE_PRX_DTX_N10 PCIE_PRX_DTX_P10 PCIE_PTX_DRX_N10 PCIE_PTX_DRX_P10

SATA_PRX_DTX_N2 SATA_PRX_DTX_P2 SATA_PTX_DRX_N2 SATA_PTX_DRX_P2

+3VS

1 2

RH19 10K_0402_5%

1 2

RH20 10K_0402_5% RH21 1K_0402_1%

1 2

RH22 10K_0402_5% RH24 10K_0402_5%

FOR SERVER & WS ONLY

PCH_BKL_PWM ENBKL

PCH_ENVDD

PCH_THERMTRIP# PCH_PECI H_PM_SYNC_R PLTRST_CPU#

EC_TP_INT# <39,41>

+RTCVCC

M.2 SSD PCIE L0

PCIE_PRX_DTX_N9 <34> PCIE_PRX_DTX_P9 <34> PCIE_PTX_DRX_N9 <34>

M.2 SSD PCIE L1

RH16 10K_0402_5%

SATA_GP0

@ @ PBA@ @ @

PCH_BKL_PWM <30> ENBKL <39> PCH_ENVDD <30>

1 2

RH25 620_0402_5%

1 2

RH26 12.1_0402_1%@ RH27 30_0402_1%

PLTRST_CPU# <9>

PM_DOWN_R <9>

PCIE_PTX_DRX_P9 <34>

PCIE_PRX_DTX_N10 <34> PCIE_PRX_DTX_P10 <34> PCIE_PTX_DRX_N10 <34>

PCIE_PTX_DRX_P10 <34>

SATA_PRX_DTX_N2 <38>

SATA_PRX_DTX_P2 <38> SATA_PTX_DRX_N2 <38> SATA_PTX_DRX_P2 <38>

M.2 SSD PCIE/SATA select pin

SATA_GP0 <34>

Follow MOW 2015WW09

PCH_SPI_IO2

PCH_SPI_SI PCH_SPI_SO PCH_SPI_IO3 PCH_SPI_CLK

PCH_SPI_IO2PCH_SPI_IO2_0_R

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PCH_SPI_IO3

Follow MOW WW36 pull down with pre-ES1/ES1 samples

2016/11/03 2017/01/10

1 2

RH36 1K_0402_1%@

1 2

RH40 1K_0402_1%@

Compal Secret Data

Deciphered Date

HDD

THERMTRIP# <9> H_PECI <9,39> H_PM_SYNC <9>

+3VALW_SPI

PLT_RST#

TP_INT#

SPI0_MOSI int. PH This strap should sample HIGH. There should NOT be any on-board device driving it to opposite direction during strap sampling.

SPI0_MISO int. PH This strap should sample HIGH. There should NOT be any on-board device driving it to opposite direction during strap sampling.

SPI0_IO2 int. PH This strap should sample HIGH. There should NOT be any on-board device driving it to opposite direction during strap sampling.

SPI0_IO3 int. PH This strap should sample HIGH. There should NOT be any on-board device driving it to opposite direction during strap sampling.

GPP_H12 int. PD This strap should sample LOW.

PCH_BKL_PWM ENBKL

PCH_PECI

PCH PLTRST

IN1

MC74VHC1G08DFT2G_SC70-5

IN2

+3VS

1 2

RH13 100K_0402_5%

1 2

RH31 100K_0402_5%

1 2

RH32 100K_0402_5%

1 2

RH33 10K_0402_5%@

1 2

RH34 10K_0402_5%

+3VS

CH16 0.1U_0201_10V6K

1 2

UH2

PLT_RST_BUF#

Compal Electronics, Inc.

Title

PCH(2/7)SPI,SATA,XDP

Size Document Number Rev

Custom

Date: Sheet of

PCH(2/7)SPI,SATA,XDP

C5MMH M/B LA-E911P

RH28 100K_0402_5%

+1.0VALW_PRIM

PLT_RST_BUF# <32,34,37>

17 64Tuesday, April 11, 2017

HDA for AUDIO

1 2

ME_EN<39>

HDA_SDOUT_R<40> HDA_RST_AUDIO#<40> HDA_SYNC_R<40> HDA_BIT_CLK_R<40>

+3VALW_PCH_PRIM

+3VALW_DSW

HDA_SDIN0<40>

RPH7

10K_0804_8P4R_5%

1 1

Follow 543016_SKL_U_Y_PDG_0_9

+3VALW_DSW

1 2

RH49 10K_0402_5%

1 2

RH50 10K_0402_5%@

1 2

RH51 1K_0402_5%

WAKE # (DS X wa ke ev ent ) 10 KΩ pull - up t o Vcc DS W3_3 The pull-up is required even if PCIe* interface

+RTCVCC

is not used on the plat f or m.

1 2

RH60 20K_0402_5%

1 2

CH21 1U_0402_6.3V6K

2 2

RH47 0_0402_5%

RPH6

1 8 2 7 3 6 4 5

33_0804_8P4R_5%

SYS_RESET#

PCH_PWROK

EC_RSMRST#

LAN_WAKE#

.1U_0402_16 V7K

HDA_SDOUT HDA_RST# HDA_SYNC HDA_BIT_CLK

HDA_SDIN0

CH64

XEMC@

PM_BATLOW#

AC_PRESENT_R

WAKE#

PCH_SRTCRST#

CH62

0.047U_0402_16V7K

XEMC@

CPU_DISPA_SDO<6>

CPU_DISPA_SDI_R<6>

CPU_DISPA_BCLK<6>

PCH_DMIC_DATA0<40> PCH_DMIC_CLK0<40>

Remove CLR ME

PCH_PWROKSYS_PWROK

1.0 Modify

PCH_SML0CLK

PCH_SML0DATA

EC_SMB_DA2 EC_SMB_CK2 PCH_SML1CLK PCH_SML1DATA

PCH_SMBDATA PCH_SMBCLK D_CK_SCLK D_CK_SDATA

PCH_RTCRST#

CLR CMOS

PCH_SMBALERT#

PCH_SML0ALERT# PCH_SML1ALERT#

(SO-DIMM,G-sensor)

DMN65D8LDW-7_SOT363-6

PCH_SMBCLK

DMN65D8LDW-7_SOT363-6

PCH_SMBDATA

DMN65D8LDW-7_SOT363-6

PCH_SML1CLK

DMN65D8LDW-7_SOT363-6

PCH_SML1DATA

1 2

RH63 20K_0402_5%

1 2

CH23 1U_0402_6.3V6K

1 2

JCMOS1 0_0603_5%@

Place at RAM DOOR

3 3

+3VALW_PCH_PRIM

4 4

EC_RSMRST# PCH_DPWROK

+3VALW_PCH_PRIM

RH64 4.7K_0402_5%

RH167 4.7K_0402_5%@ RH168 4.7K_0402_5%@

+3VALW_PCH_PRIM

RH65 499_0402_1%

RH66 499_0402_1%

+3VS

2.2K_0804_8P4R_5%

+3VALW_PCH_PRIM

+3VS

2.2K_0804_8P4R_5%

PDG_0_71 requirement PH to +3V_PCH 10/14 Dan

RH54 0_0402_5%

RH57 0_0402_5%

1 2

1 2 1 2

1 2

RPH8

18 27 36 45

RPH9

18 27 36 45

close to PCH

T203 T204

HDMI_HPD_PCH<23,31>

PCH_EDP_HPD<30>

PCH_RTCRST#<39>

PCH_PWROK<39,43> EC_RSMRST#<39>

T15

RH56

30_0402_1%

CPU_DISPA_SDO_R

1 2

CPU_DISPA_BCLK_R

1 2

RH58 30_0402_1%

PCH_DMIC_DATA0 PCH_DMIC_CLK0 PCH_DMIC_DATA1

PAD

PCH_DMIC_CLK1

PAD

T24

PAD

T25

PAD

T27

PAD

(VGA, EC, RTD2168)

+3VS

QH1A

3 4

+3VS

3 4

D_CK_SCLK

D_CK_SDATA

EC_SMB_CK2

EC_SMB_DA2

6 1

QH1B

QH2A

6 1

QH2B

HDMI_HPD_PCH

EC_SCI#_I3

PAD@

PCH_EDP_HPD

HDA_BIT_CLK HDA_RST# HDA_SDIN0

HDA_SDOUT HDA_SYNC

CPU_DISPA_SDI_R

PCH_RTCRST# PCH_SRTCRST#

PCH_PWROK EC_RSMRST#

PCH_DPWROK PCH_SMBALERT# PCH_SMBCLK PCH_SMBDATA PCH_SML0ALERT# PCH_SML0CLK PCH_SML0DATA PCH_SML1ALERT# PCH_SML1CLK PCH_SML1DATA

(DDR,G-Sensor)

D_CK_SCLK <14,15,38>

D_CK_SDATA <14,15,38>

(EC, VGA)

EC_SMB_CK2 <23,33,39>

UH1E

AW4

GPP_I0/DDPB _HPD0

AY2

GPP_I1/DDPC _HPD1

AV4

GPP_I2/DDPD _HPD2

BA4

GPP_I3/DDPE _HPD3

BD7

GPP_I4/EDP_ HPD

SKL-H-PCH_BGA837

REV = 1.3

UH1D

BA9

HDA_BCLK

BD8

HDA_RST#

BE7

HDA_SDI0

BC8

HDA_SDI1

BB7

HDA_SDO

BD9

HDA_SYNC

BD1

RSVD_BD1

BE2

RSVD_BE2

AM1

DISPA_SDO

AN2

DISPA_SDI

AM2

DISPA_BCLK

AL42

GPP_D8/I2S0_ SCLK

AN42

GPP_D7/I2S0_ RXD

AM43

GPP_D6/I2S0_ TXD

AJ33

GPP_D5/I2S0_ SFRM

AH44

GPP_D20/DM IC_DATA0

AJ35

GPP_D19/DM IC_CLK0

AJ38

GPP_D18/DM IC_DATA1

AJ42

GPP_D17/DM IC_CLK1

BC10

RTCRST#

BB10

SRTCRST#

AW11

PCH_PWROK

BA11

RSMRST#

AV11

DSW_PWROK

BB41

GPP_C2/SMB ALERT#

AW44

GPP_C0/SMB CLK

BB43

GPP_C1/SMB DATA

BA40

GPP_C5/SML 0ALERT#

AY44

GPP_C3/SML 0CLK

BB39

GPP_C4/SML 0DATA

AT27

GPP_B23/SM L1ALERT#/PCHH OT#

AW42

GPP_C6/SML 1CLK

AW45

GPP_C7/SML 1DATA

SKL-H-PCH_BGA837

REV = 1.3

EC_SMB_DA2 <23,33,39>

AUDIO

SPT-H_PCH

5 OF 12

GPP_I7/DDPC _CTRLCLK

GPP_I8/DDPC _CTRLDATA

GPP_I5/DDPB _CTRLCLK

GPP_I6/DDPB _CTRLDATA

GPP_I9/DDPD _CTRLCLK

GPP_I10/DDP D_CTRLDATA

SPT-H_PCH

GPP_A12/BM BUSY#/ISH_GP6/SX_EX IT_HOLDOFF#

GPP_A13/SU SWARN#/SUSP WRDNACK

SMBUS

JTAG

4 OF 12

BB3 BD6 BA5 BC4 BE5 BE6

Y44

GPP_F14

V44

GPP_F23

W39

GPP_F22

L43

GPP_G23

L44

GPP_G22

U35

GPP_G21

R35

GPP_G20

BD36

GPP_H23

GPP_B2/VRA LERT#

GPP_G17/ADR _COMPLETE

GPP_A15/SU SACK#

GPP_A8/CLK RUN#

GPD11/LANP HYPC

GPD9/SLP_W LAN#

GPP_B12/SLP _S0#

GPD10/SLP_S 5#

GPD0/BATLOW #

GPD2/LAN_W AKE# GPD1/ACPR ESENT

GPD3/PWR BTN#

DRAM_RESET#

GPP_B1 GPP_B0

GPP_B11

SYS_PWROK

WAKE#

GPD6/SLP_A #

SLP_LAN#

GPD4/SLP_S 3# GPD5/SLP_S 4#

GPD8/SUSC LK

SLP_SUS#

SYS_RESET#

GPP_B14/SPK R

PROCPWRGD

ITP_PMODE

JTAGX JTAG_TMS JTAG_TDO

JTAG_TDI

JTAG_TCK

BB17 AW22

AR15

AV13

BC14 BD23 AL27 AR27 N44 AN24 AY1

BC13 BC15 AV15 BC26 AW15 BD15 BA13

AN15 BD13 BB19 BD19

BD11 BB15 BB13 AT13 AW1 BD26

H_CPUPWRGD

AM3

AT2 AR3 AR2 AP1 AP2 AN3

H_SKTOCC# <9>

PM_CLKRUN#

SLP_WLAN#

DDR_DRAMRST# PCH_VRALERT# TYPEC_3A_1P5A# LAN_GPO

SYS_PWROK

WAKE# PM_SLP_A#

SLP_LAN# PM_SLP_S0#_R PM_SLP_S3# PM_SLP_S4# PM_SLP_S5#

SUSCLK PM_BATLOW#

1 2

RH62 0_0402_5%

LAN_WAKE# AC_PRESENT_R PM_SLP_SUS# PBTN_OUT#_R SYS_RESET#

PCH_SPKR

XDP_ITP_PMODE CPU_XDP_TCK0 CPU_XDP_TMS CPU_XDP_TDO CPU_XDP_TDI PCH_JTAG_TCK1

PM_CLKRUN# <41>

PAD

DDR_DRAMRST# <14>

TYPEC_3A_1P5A# <36> LAN_GPO <32>

SYS_PWROK <39,43>

PAD

PM_SLP_S3# <39,43> PM_SLP_S4# <39,43> @

PAD

SUSCLK <34,37>

PAD

PCH_SPKR <40>

H_CPUPWRGD <9>

PAD

CPU_XDP_TCK0 <6,9> CPU_XDP_TMS <6,9> CPU_XDP_TDO <6,9> CPU_XDP_TDI <6,9> PCH_JTAG_TCK1 <6>

Functional Strap Definitions

SMBALERT# / GPP_C2 int. PD 0 = Disable Intel ME (TLS) (Default) 1 = Enable Intel ME (TLS)

SML0ALERT# / GPP_C5 int. PD 0 = LPC Is selected for EC. (Default) 1 = eSPI Is selected for EC.

SML1ALERT# / PCHHOT# / GPP_B23 int. PD

SPKR / GPP_B14 int. PD 0 = Disable Top Swap mode. (Default) 1 = Enable Top Sw ap mode.

HDA_SDO int. PD 0 = Enable security measures defined in the Flash Descriptor. (Default) 1 = Disable Flash Descriptor Security (override).

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/11/03 2017/01/10

Compal Secret Data

Deciphered Date

PM_CLKRUN#

PCH_VRALERT#

T16

T17 T18

T21

T22

PAD

SUSPWRDNACK <39>

T23

T26

DDPB_CTRLDATA / GPP_I6 int. PD 0 = Port B is not detected. 1 = Port B i s detected. (Default)

DDPC_CTRLDATA / GPP_I8 int. PD 0 = Port C is not detected. 1 = Port C i s detected. (Default)

DDPD_CTRLDATA / GPP_I10 int. PD 0 = Port D i s not detected. (Default) 1 = Port D i s detected.

Title

Size Document Number Rev

Custom

Date: Sheet of

PBTN_OUT#_R

AC_PRESENT_R

PM_SLP_S3#

PM_SLP_S4#

PM_SLP_S0#_R

SYS_PWROK

SYS_RESET#

Compal Electronics, Inc.

PCH(3/7)GPIO,SMBUS

C5MMH M/B LA-E911P

CRB 8.2K

1 2

RH48 10K_0402_5%

+3VALW_PCH_PRIM

RH55

0_0402_5%

RH59

0_0402_5%

RH166

1 2

XEMC@

1 2

CH22 .1U_0402_16 V7K

XEMC@

PAD

18 64Tuesday, April 11, 2017

+3VALW_DSW

PBTN_OUT# <39>

AC_PRESENT <39>

T19

T20

PM_SLP_S0# <39>

RH52 10K_0402_5%@

RH53 100K_0402_5%

1 2

0_0402_5%

1 2

RH61 10K_0402_5%

CH61 .1U_0402_16V7K

+3VS

1B Modify

XTAL24_OUT

1 2

EMC@

RH164 33_0402_1%

XTAL24_IN

1 2

EMC@

RH165 33_0402_1%

18P_0402_50V8J

CH25

24M X'tal

1 2

RH72 1M_0402_5%

YH2

1 1

24MHZ_18PF_XRCGB24M000F2P51R0

33P_0402_50V8J

CH24

1B Modify

RTC X'tal

RTCX1

1 2

RH71 10M_0402_5%

YH1

1 2

32.768KHZ_9PF_CM7V-T1A9.0PF20PPM

8.2P_0402_50V8D

CH26

2 2

Follow PDG 0.71Table 52-17 10/13 Dan CHECK NEEDED IF UNUSE?

3 3

4 4

+3VS

RPH10

10K_0804_8P4R_5%

RPH11

10K_0804_8P4R_5%

RPH12

10K_0804_8P4R_5%

RPH13

10K_0804_8P4R_5%

+3VS

RH68 10K_0402_5%@

18 27 36 45

RTCX2

8.2P_0402_50V8D

CH27

CLKREQ_PCIE#3

LAN_CLKREQ# VGA_CLKREQ# WLAN_CLKREQ# NGFF_CLKREQ#

CLKREQ_PCIE#12 CLKREQ_PCIE#7 CLKREQ_PCIE#10 CLKREQ_PCIE#5

CLKREQ_PCIE#9 CLKREQ_PCIE#8 CLKREQ_PCIE#6 CLKREQ_PCIE#13

CLKREQ_PCIE#14 CLKREQ_PCIE#11 CLKREQ_PCIE#15

VGA_CLKREQ# <23>

+1.0VALW_VCCCLK5

CPU_24M<9> CPU_24M#<9>

CPU_BCLK<9> CPU_BCLK#<9>

LAN_CLKREQ#<32> WLAN_CLKREQ#<37>

XTAL24_OUT XTAL24_IN

RH67

2.7K_0402_1%

NGFF_CLKREQ#<34>

XCLK_BIASREF

RTCX1 RTCX2

VGA_CLKREQ# LAN_CLKREQ# WLAN_CLKREQ# CLKREQ_PCIE#3 NGFF_CLKREQ# CLKREQ_PCIE#5 CLKREQ_PCIE#6 CLKREQ_PCIE#7 CLKREQ_PCIE#8 CLKREQ_PCIE#9 CLKREQ_PCIE#10 CLKREQ_PCIE#11 CLKREQ_PCIE#12 CLKREQ_PCIE#13 CLKREQ_PCIE#14 CLKREQ_PCIE#15

UH1G

AR17

GPP_A16/CLKOUT_48

CLKOUT_CPUNSSC_P

CLKOUT_CPUNSSC_N

CLKOUT_CPUBCLK_P

CLKOUT_CPUBCLK_N

XTAL24_OUT

XTAL24_IN

XCLK_BIASREF

BC9

RTCX1

BD10

RTCX2

BC24

GPP_B5/SRCCLKREQ0#

AW24

GPP_B6/SRCCLKREQ1#

AT24

GPP_B7/SRCCLKREQ2#

BD25

GPP_B8/SRCCLKREQ3#

BB24

GPP_B9/SRCCLKREQ4#

BE25

GPP_B10/SRCCLKREQ5#

AT33

GPP_H0/SRCCLKREQ6#

AR31

GPP_H1/SRCCLKREQ7#

BD32

GPP_H2/SRCCLKREQ8#

BC32

GPP_H3/SRCCLKREQ9#

BB31

GPP_H4/SRCCLKREQ10#

BC33

GPP_H5/SRCCLKREQ11#

BA33

GPP_H6/SRCCLKREQ12#

AW33

GPP_H7/SRCCLKREQ13#

BB33

GPP_H8/SRCCLKREQ14#

BD33

GPP_H9/SRCCLKREQ15#

R13

CLKOUT_PCIE_N15

R11

CLKOUT_PCIE_P15

CLKOUT_PCIE_N14

CLKOUT_PCIE_P14

CLKOUT_PCIE_N13

CLKOUT_PCIE_P13

CLKOUT_PCIE_N12

CLKOUT_PCIE_P12

SKL-H-PCH_BGA837

REV = 1.3

SPT-H_PCH

CLKOUT_CPUPCIBCLK_N

CLKOUT_CPUPCIBCLK_P

7 OF 12

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0

CLKOUT_PCIE_N1 CLKOUT_PCIE_P1

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3

CLKOUT_PCIE_N4 CLKOUT_PCIE_P4

CLKOUT_PCIE_N5 CLKOUT_PCIE_P5

CLKOUT_PCIE_N6 CLKOUT_PCIE_P6

CLKOUT_PCIE_N7 CLKOUT_PCIE_P7

CLKOUT_PCIE_N8 CLKOUT_PCIE_P8

CLKOUT_PCIE_N9 CLKOUT_PCIE_P9

CLKOUT_PCIE_N10

CLKOUT_PCIE_P10

CLKOUT_PCIE_N11

CLKOUT_PCIE_P11

L1 L2 J1 J2

N7 N8

L7 L5

D3 F2

E5 G4

D5 E6

D8 D7

R8 R7

U5 U7

W10 W11

N3 N2

P3 P2

R3 R4

CLK_CPU_ITP# CLK_CPU_ITP CPU_PCIBCLK# CPU_PCIBCLK

CLK_PEG_VGA#

CLK_PEG_VGA

CLK_PCIE_LAN#

CLK_PCIE_LAN

CLK_PCIE_WLAN#

CLK_PCIE_WLAN

CLK_PCIE_NGFF#

CLK_PCIE_NGFF

PAD

T28

PAD

T29

CPU_PCIBCLK# <9> CPU_PCIBCLK <9>

CLK_PEG_VGA# <23> CLK_PEG_VGA < 23>

CLK_PCIE_LAN# <32>

CLK_PCIE_LAN <32>

CLK_PCIE_WLAN# <37>

CLK_PCIE_WLAN <37>

CLK_PCIE_NGFF# <34> CLK_PCIE_NGFF <34>

DGPU

GLAN

NGFF WL+BT(KEY E)

M2 SSD

Security Classification

2016/11/03 2017/01/10

Issued Date

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/11/03 2017/01/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

PCH(4/7)CLK

C5MMH M/B LA-E911P

19 64Tuesday, April 11, 2017

Functional Strap Definitions

GSPI1_MOSI / GPP_B22 int. PD Boot BIOS Destination 0 = SPI (Default) 1 = LPC

1 1

2 2

GSPI0_MOSI / GPP_B18 int. PD 0 = Disable No Reboot mode. (Default) 1 = Enable No Reboot mode (PCH will disable the TCO Timer system reboot featu re).

+3VS

RH14 10K_0402_5%@

+3VS

RH73 49.9K_0402_1%

RH74 49.9K_0402_1%

RH76 49.9K_0402_1%@

RH75 49.9K_0402_1%@

PCH internal PU 20K

UART_2_CRXD_DTXD

UART_2_CTXD_DRXD

UART_2_CCTS_DRTS

UART_2_CRTS_DCTS

EC_SCI#

DGPU_AC_DETECT<23,39>

EC_SCI# <39>

UH1K

AT29

GPP_B22/GSPI1_MOSI

AR29

EC_SCI#

GC6_FB_EN

PAD

T37

PCH_AC_DET

GPU_EVENT_R#

DGPU_HOLD_RST# DGPU_PWR_EN

UART_2_CCTS_DRTS UART_2_CRTS_DCTS UART_2_CTXD_DRXD UART_2_CRXD_DTXD

I2C_ 1_SCL I2C_ 1_SDA

PCH_GPP_D4

1 2

RH77 0_0402_5%

DGPU_HOLD_RST#<23>

DGPU_PWR_EN<23,27>

UART_2_CTXD_DRXD<37>

UART_2_CRXD_DTXD<37>

I2C_ 1_SCL<41> I2C_ 1_SDA<41>

GPP_B21/GSPI1_MISO

AV29

GPP_B20/GSPI1_CLK

BC27

GPP_B19/GSPI1_CS#

BD28

GPP_B18/GSPI0_MOSI

BD27

GPP_B17/GSPI0_MISO

AW27

GPP_B16/GSPI0_CLK

AR24

GPP_B15/GSPI0_CS#

AV44

GPP_C9/UART0_TXD

BA41

GPP_C8/UART0_RXD

AU44

GPP_C11/UART0_CTS#

AV43

GPP_C10/UART0_RTS#

AU41

GPP_C15/UART1_CTS#/ISH_UART1_CTS#

AT44

GPP_C14/UART1_RTS#/ISH_UART1_RTS#

AT43

GPP_C13/UART1_TXD/ISH_UART1_TXD

AU43

GPP_C12/UART1_RXD/ISH_UART1_RXD

AN43

GPP_C23/UART2_CTS#

AN44

GPP_C22/UART2_RTS#

AR39

GPP_C21/UART2_TXD

AR45

GPP_C20/UART2_RXD

AR41

GPP_C19/I2C1_SCL

AR44

GPP_C18/I2C1_SDA

AR38

GPP_C17/I2C0_SCL

AT42

GPP_C16/I2C0_SDA

AM44

GPP_D4/ISH_I2C2_SDA/ISH_I2C3_SDA

AJ44

GPP_D23/ISH_I2C2_SCL/ISH_I2C3_SCL

SKL-H-PCH_BGA837

REV = 1.3

SPT-H_PCH

GPP_D9 GPP_D10 GPP_D11 GPP_D12

GPP_D16/ISH_UART0_CTS#

11 OF 12

GPP_D15/ISH_UART0_RTS#

GPP_H20/ISH_I2C0_SCL GPP_H19/ISH_I2C0_SDA

GPP_H22/ISH_I2C1_SCL GPP_H21/ISH_I2C1_SDA

GPP_A23/ISH_GP5 GPP_A22/ISH_GP4 GPP_A21/ISH_GP3 GPP_A20/ISH_GP2 GPP_A19/ISH_GP1 GPP_A18/ISH_GP0 GPP_A17/ISH_GP7

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C2_SDA

VGA_ID1

AL44

VGA_ID2

AL36

PROJECT_ID0

AL35

PROJECT_ID1

AJ39

AJ43 AL43 AK44

SUB_DET

AK45

BC38 BB38

BD38 BE39

BC22 BD18 BE21 BD22 BD21 BB22 BC19

PAD PAD

PAD

@ @

SUB_DET <33>

T30 T31

T32 T33

T34 T35

G_INT

T36

+3VALW_PCH_PRIM

1 2

RH80 2.2K_0402_5%

1 2

RH81 2.2K_0402_5%

3 3

+3VS

RH83 10K_0402_5%VGA@

RH85 10K_0402_5%VGA@

I2C_ 1_SCL

I2C_ 1_SDA

DGPU_PWR_EN

DGPU_HOLD_RST#

VGA_ID1

VGA_ID2

VGA ID

1 2

G1@

RH88

1 2

G0@

RH90 10K_0402_5%

1 2

RH92

1 2

RH94 10K_0402_5%VGA@

VGA_ID2 VGA_ID1 GPP_D10 GPP_D9

N17P-G0

1 2

TO DGPU

4 4

GPU_EVENT#<23>

GC6_FB_EN3V3<23>

GC6_FB_EN3V3 GC6_FB_EN

RH86 0_0402_5%

1 2

RH87 0_0402_5%

GPU_EVENT_R#GPU_EVENT#

N17P-G1 N17E-G1 Reserved

Security Classification

Issued Date

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VALW_PCH_PRIM

1K_0402_1%

1 01 11

Compal Secret Data

2016/11/03 2017/01/10

Compal Secret Data

Deciphered Date

PROJECT_ID0

PROJECT_ID1

Project ID

C5MMH C5PRH Reserved Reserved

1 2

RH89

1 2

RH91 10K_0402_5%

1 2

RH93

1 2

RH95 10K_0402_5%

+3VALW_PCH_PRIM

1K_0402_1%

Project_ID0Project_ID1

GPP_D11GPP_D12

00 0 1

1 0

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

PCH(5/7)UART,I2C,GPIO

C5MMH M/B LA-E911P

+3VS

1 2

RH82

10K_0402_5%

G_INT

RH84

100K_0402_5%

G_INT <38>

20 64Tuesday, April 11, 2017

1.0 Modify

JC2

JUMP_43X118

1 2

RH98 0_0805_5%@

1 1

+1.0VALW_PCH

2 2

RH101 for Deep SX

1 2

RH101 0_0402_5%

RH103

1 2

0_0603_5%

LH1

FBMA-L11-160808-800LMT_0603

1 2

22U_0603_6.3V6M

+1.0VALW_PRIM+1.0VALW

+1.0VALW_PCH

+1.0VALW_DCPDSW

Near PIN BA29

CH28 1U_0402_6.3V6K

+1.0VALW_VCCCLK

CH30

+1.0VALW_VCCCLK5

22U_0603_6.3V6M

CH31

Near PIN K2,K3

CH32 1U_0402_6.3V6K

modify follow PDG 05/18

RH104

1 2

0_0603_5%

NO USE MPHYGT ON H CHANGE TO +1.0VALW_MPHY

LH2

3 3

4 4

1 2

FBMA-L11-160808-800LMT_0603

LH3

1 2

FBMA-L11-160808-800LMT_0603

1 2

RH106 0_0402_5%

1 2

RH107 0_0402_5%

+1.0VALW_MPHY

CH39

22U_0603_6.3V6M

Near PIN U21,U23,U25,U26,V26

CH47

22U_0603_6.3V6M

+1.0VALW_AUSB_AZP LL

CH53

22U_0603_6.3V6M

+1.0VALW_PRIMAL22

+1.0VALW_PRIMAD15

modify follow PDG 05/18

1U_0402_6.3V6K

CH40

+1.0VALW_AMPHYPLL

22U_0603_6.3V6M

CH48

Near PIN AJ5,AL5

CH54 22U_0603_6.3V6M

EMC@

CH71 1000P_0402_50V7K

1U_0402_6.3V6K

CH41

Near PIN V28 Near PIN AC17

Near PIN A42,A43,B43

CH49 1U_0402_6.3V6K

1U_0402_6.3V6K

CH42

+1.0VALW_AUSB_AZP LL

Sensitive net cap for AD15

+1.0VALW_PRIM

+1.0VALW_DCPDSW

+1.0VALW_VCCCLK

+1.0VALW_VCCCLK5

+1.0VALW_MPHY

+1.0VALW_AMPHYPLL

+1.0VALW_MPHY

+3VALW_HDA +3VALW_DSW

Near PIN W15 Add 05/18

VCCMPHY power defined by HSIO lane qty.

1.0 Modify

+1.0VALW_MPHY +1.0VALW_MPHY

EMC@

CH69 1000P_0402_50V7K

Sensitive net cap for V28,AC171.0 Modify

2.899A

0.0454A

0.021A

0.050A

0.024A

0.137A

0.006A

1.307A

0.110A

0.030A

0.533A

0.012A

0.033A

0.075A

CH44 1U_0402_6.3V6K

CH70 1000P_0402_50V7K

PCH_EDS Table10-4 12/30 J

AA23 AA26 AA28 AC23 AC26 AC28 AE23 AE26

Y23 Y25

BA29

N17 R19 U20 V17 R17

K2 K3

U21 U23 U25 U26 V26 A43 B43 C44 C45 V28

AC17

AJ5 AL5

AN19

BA15

W15

EMC@

UH1H

VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 DCPDSW_1P0

VCCCLK1 VCCCLK3 VCCCLK4 VCCCLK2 VCCCLK2 VCCCLK5 VCCCLK5

VCCMPHY_1P0 VCCMPHY_1P0 VCCMPHY_1P0 VCCMPHY_1P0 VCCMPHY_1P0 VCCMPHYPLL_1P0 VCCMPHYPLL_1P0 VCCPCIE3PLL_1P0 VCCPCIE3PLL_1P0 VCCAPLLEBB_1P0 VCCPRIM_1P0 VCCUSB2PLL_1P0 VCCUSB2PLL_1P0 VCCHDAPLL_1P0

VCCHDA VCCDSW_3P3

SKL-H-PCH_BGA837

REV = 1.3

SPT-H_PCH

CORE

MPHY

USB

VCCGPIO

VCCRTCPRIM_3P3

8 OF 12

+3VALW_PCH_PRIM

22U_0603_6.3V6M

+3VALW

1 2

RH97 0_0603_5%@

1.0 Modify

1 2

RH99 0_0805_5%@

1 2

RH100 0_0603_5%

+3VALW_PCH_PRIM +3VALW_SPI

1 2

RH102 0_0603_5%

AL22

VCCPRIM_1P0

VCCDSW_3P3

VCCPGPPA

VCCPGPPBCH VCCPGPPBCH

VCCPGPPEF VCCPGPPEF

VCCPGPPG

VCCPRIM_3P3

VCCPRIM_1P0

VCCATS

VCCRTC DCPRTC

VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0

VCCPGPPD VCCPGPPD VCCPGPPD VCCPGPPD

VCCPRIM_3P3 VCCPRIM_3P3 VCCPRIM_3P3

1U_0402_6.3V6K

CH51

22U_0603_6.3V6M

CH55

VCCSPI VCCSPI VCCSPI

CH57

BA24 BA31

BC42 BD40 AJ41 AL41 AD41 AN5

AD15 AD13 BA20 BA22 BA26

AJ20 AJ21 AJ23 AJ25

BE41 BE43 BE42 BC44 BA45 BC45 BB45

BD3 BE3 BE4

+1.0VALW_PRIM

0.0908A

0.195A

0.082A

0.2726A

0.1410A

0.1318A

0.2875A

0.0061A

0.007A

0.0002A

0.029A

0.078A

0.117A

+1.0VALW_PRIM

1U_0402_6.3V6K

CH52

22U_0603_6.3V6M

CH56

22U_0603_6.3V6M

CH58

+3VALW_DSW

+3VALW_PCH_PRIM

+3VALW_HDA

+1.0VALW_PRIMAL22

+3VALW_DSW +3VALW_PCH_PRIM

+1.0VALW_PRIMAD15 +3VS_VCCATS +3VALW_PCH_PRIM +RTCVCC

CH34 0.1U_0201_10V6K

+1.0VALW_PRIM

+3VALW_SPI

+3VALW_PCH_PRIM

CH66

0.1U_0201_10V6K

Near PIN BA26

1 2

RTC Battery

0.1U_0201_10V6K

CH60

Power Rail Volt age

+CHGRTC

BAT54C( VF)

+3VL_RTC

3.383V( MAX)

240 mV

3.143V

+RTCBATT

Result : Pass

Security Classification

Security Classificati on

Issued Date

THIS S HEET OF ENGINEER ING D RAWING IS THE PROPRI ETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS S HEET OF ENGINEER ING D RAWING IS THE PROPRI ETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORM ATION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORM ATION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORM ATION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/01/29 2017/01/10

Compal Secret Data

Deciphered Date

Deciphered Dat e

+3VALW_PCH_PRIM

+RTCVCC

1U_0402_6.3V6K

JRTC1

GND

ACES_50271-0020N-001

CONN@

SP02000RO00

RH105 0_0402_5%

CH59

1 2

CH29 1U_04 02_6.3V6K

1 2

CH33 1U_04 02_6.3V6K

1 2

CH35 0. 1U_0201_10V6K

1 2

CH36 1U_04 02_6.3V6K

1 2

CH37 0. 1U_0201_10V6K

1 2

CH38 0. 1U_0201_10V6K

1 2

CH43 0. 1U_0201_10V6K

1 2

CH45 0. 1U_0201_10V6K

1 2

CH46 1U_04 02_6.3V6K

1 2

BAV70W_SOT323-3

RH163 10K_0402_5%

DH3

W=20mils

PN : SC600000B00

Near PIN BA22 09/26 dan

Near PIN BD3,BE3,BE4

Near PIN BA20

Near PIN AN5

No requirment Near PIN BC44

Near PIN BC42,BD40

Near PIN AJ41 , AL41

Near PIN AD41

Near PIN BA20

+3VS_VCCATS+3VS

CH50 1U_0402_6. 3V6K

1 2

Near PIN AD13

+CHGRTC

1 2

Titl e

Size Document Number Rev

Custom

Date: Sheet of

+RTCBATT

Compal Electronics, Inc.

PCH(6/7)POWER

C5MMH M/B LA-E911P

21 64Tuesday, April 11, 2017

+ 39 hidden pages

Acer A715-71 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual