Acer 7736 Schematics

5

JV71-MV DDR3 Madison Block

JV71-MV DDR3 Madison BlockJV71-MV DDR3 Madison Block

D D

Diagram

DiagramDiagram

CLK GEN.

ICS9LPRS365B

3

DDR3

1066 MHz

16,17

DDR3

1066 MHz

C C

LINE IN

29

Int MIC

18

MIC In

29

INT.SPKR

1.5W

B B

29

LINE OUT

29

RJ11

Codec

ALC888S

OP AMP

MAX9789A

MODEM

MDC Card

16,17

27

30

4

AZALIA

HDD SATA

ODD SATA

Mobile CPU

Penryn

HOST BUS 667/800/1066MHz@1.05V

Cantiga

AGTL+ CPU I/F DDR Memory I/F

INTEGRATED GRAHPICS

X4 DMI 400MHz

LVDS, CRT I/F

6,7,8,9,10,11

C-Link0

ICH9M

6 PCIe ports

PCI/PCI BRIDGE

ACPI 2.0 4 SATA

12 USB 2.0/1.1 ports

ETHERNET (10/100/1000MbE)

High Definition Audio

LPC I/F

Serial Peripheral I/F

Matrix Storage Technology(DO)

Active Managemnet Technology(DO)

12,13,14,15

SATA

21

SATA

22

Mini USB Blue Tooth

Finger Printer

23

37

4, 5

USB

Camera

PCIex16

USB

PCIe

LPC BUS

USB 4 Port

3

SMSC

EMC2102

24

34

VRAM

64MbX16X8 1024M

VGA

Madison / M96

CardBus

RTS5159

LAN

Giga LAN

BCM5784

KBC

Winbond

WPCE773

Touch Pad

37 35

52~57

31

25

Mini 1 Card Wire LAN

SPI

35

INT. KB

MS/MS Pro/xD /MMC/SD

33

BIOS (2MB)

36

MEDIA KEY

38

2

Project code: 91.4FX01.001 PCB P/N : 48.4FX01.01M REVISION : 09924 -1

TOP

GND

S S

GND

BOTTOM

HDMI

LCD

CRT

TXFM RJ45

26 26

LPC

DEBUG

36

CONN.

PCB STACKUP

20

18

19

1

SYSTEM DC/DC

ISL62392

INPUTS

DCBATOUT

L1

L2

L3 L4

L5

L6

SYSTEM DC/DC

TPS51124

INPUTS OUTPUTS

DCBATOUT

RT9026

1D5V_S3

RT9018

1D5V_S3 1D1V_S0(2A)

TPS51117

DCBATOUT FBVDD(4A)

CHARGER

ISL88731A

CPU DC/DC

ISL6266A

INPUTS

DCBATOUT

VGA_CORE

RT8202A

INPUTS

DCBATOUT

GFXCORE

ISL6263A

INPUTS

DCBATOUT

OUTPUTS

5V_S5(6A) 3D3V_S5(7A) 5V_AUX_S5 3D3V_AUX_S5

1D05V_S0(9A) 1D5V_S3(12A)

DDR_VREF_S3 (1.2A)

OUTPUTSINPUTS

BT+DCBATOUT

OUTPUTS

VCC_CORE 38A

OUTPUTS

VGA_CORE 13A

OUTPUTS

VCC_GFXCORE (7A)

42

43

44

45

47

41

47

46

A A

JV71-MV DDR 3 Madison

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O.C .

Taipei Hsie n 221, Taiwan, R.O.C .

Title

BLOCK DIAGRAM

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

JV71-MV DDR3 Madison

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C .

1

-1

1 62Wednesd ay, October 28, 2009

-1

A

ICH9M Functional Strap Definitions

Signal

HDA_SDOUT

HDA_SYNC

4 4

GNT2#/ GPIO53

GPIO20 GNT1#/

GPIO51

GNT3#/ GPIO55

GNT0#: SPI_CS1#/ GPIO58

SPI_MOSI

3 3

GPIO49

SATALED#

SPKR

TP3

GPIO33/ HDA_DOCK _EN#

Usage/When Sampled

XOR Chain Entrance/ PCIE Port Config1 bit1, Rising Edge of PWROK

PCIE config1 bit0, Rising Edge of PWROK.

PCIE config2 bit2, Rising Edge of PWROK.

Reserved ESI Strap (Server Only)

Rising Edge of PWROK

Top-Block Swap Override. Rising Edge of PWROK.

Boot BIOS Destination Selection 0:1. Rising Edge of PWROK.

Integrated TPM Enable, Rising Edge of CLPWROK

DMI Termination Voltage, Rising Edge of PWROK.

PCI Express Lane Reversal. Rising Edge of PWROK.

No Reboot. Rising Edge of PWROK.

XOR Chain Entrance. Rising Edge of PWROK.

Flash Descriptor Security Override Strap Rising Edge of PWROK

Allows entrance to XOR Chain testing when TP3 pulled low.When TP3 not pulled low at rising edge of PWROK,sets bit1 of RPC.PC(Config Registers: offset 224h). This signal has weak internal pull-down

This signal has a weak internal pull-down. Sets bit0 of RPC.PC(Config Registers:Offset 224h)

This signal has a weak internal pull-up. Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) This signal should not be pulled high.

ESI compatible mode is for server platforms only. This signal should not be pulled low for desttop and mobile.

Sampled low:Top-Block Swap mode(inverts A16 for all cycles targeting FWH BIOS space). Note: Software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3# being pulled down.

Controllable via Boot BIOS Destination bit (Config Registers:Offset 3410h:bit 11:10). GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC.

Sample low: the Integrated TPM will be disabled. Sample high: the MCH TPM enable strap is sampled low and the TPM Disable bit is clear, the Integrated TPM will be enable.

The signal is required to be low for desktop applications and required to be high for mobile applications.

Signal has weak internal pull-up. Sets bit 27 of MPC.LR(Device 28:Function 0:Offset D8)

If sampled high, the system is strapped to the "No Reboot" mode(ICH9 will disable the TCO Timer system reboot feature). The status is readable via the NO REBOOT bit.

This signal should not be pull low unless using XOR Chain testing.

Sampled low:the Flash Descriptor Security will be overridden. If high,the security measures will be in effect.This should only be enabled in manufacturing environments using an external pull-up resister.

ICH9 EDS 642879 Rev.1.5

Comment

2 2

B

ICH9M Integrated Pull-up

page 92

and Pull-down Resistors

SIGNAL Resistor Type/Value

CL_CLK[1:0] CL_DATA[1:0] CL_RST0# DPRSLPVR/GPIO16 ENERGY_DETECT HDA_BIT_CLK HDA_DOCK_EN#/GPIO33 HDA_RST# HDA_SDIN[3:0] HDA_SDOUT HDA_SYNC GLAN_DOCK#

GNT[3:0]#/GPIO[55,53,51]

GPIO[20] GPIO[49] LDA[3:0]#/FHW[3:0]# LAN_RXD[2:0] LDRQ[0] LDRQ[1]/GPIO23 PME# PWRBTN# SATALED#

SPI_CS1#/GPIO58/CLGPIO6

SPI_MOSI SPI_MISO SPKR TACH_[3:0] TP[3] USB[11:0][P,N]

C

Cantiga chipset and ICH9M I/O controller Hub strapping configuration

ICH9 EDS 642879 Rev.1.5

PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-DOWN 20K PULL-DOWN 20K PULL-DOWN 20K

The pull-up or pull-down active when configured for native GLAN_DOCK# functionality and determined by LAN controller

PULL-DOWN 20K

PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 15K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-UP 20K PULL-DOWN 15K

D

Montevina Platform Design guide 22339 0.5

Pin Name

CFG[2:0]

CFG[4:3] CFG8 CFG[15:14] CFG[18:17]

CFG5 CFG6

CFG7

CFG9

CFG10 PCIE Loopback enable

CFG[13:12]

CFG16

CFG19

CFG20

SDVO_CTRLDATA

NOTE:

1. All strap signals are sampled with respect to the leading edge of the (G)MCH Power OK (PWROK) signal.

2. iTPM can be disabled by a 'Soft-Strap' option in the Flash-decriptor section of the Firmware. This 'Soft-Strap' is activated only after enabling iTPM via CFG6. Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time.

Strap Description

FSB Frequency Select

Reserved

DMI x2 Select iTPM Host

Interface

Intel Management engine Crypto strap

PCIE Graphics Lane

XOR/ALL

FSB Dynamic ODT

DMI Lane Reversal

1 = Reverse Lanes DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3) DMI x2 mode[MCH -> ICH]:(3->0,2->1)

Digital Display Port (SDVO/DP/iHDMI) Concurrent with PCIe

SDVO Present

Local Flat Panel (LFP) Present

Configuration

000 = FSB1067 011 = FSB667 010 = FSB800 others = Reserved

0 = DMI x2

1 = DMI x4

0= The iTPM Host Interface is enabled(Note2)

1=The iTPM Host Interface is disalbed(default)

0 = Transport Layer Security (TLS) cipher suite with no confidentiality

1 = TLS cipher suite with confidentiality (default)

0 = Reverse Lanes,15->0,14->1 ect..

1= Normal operation(Default):Lane Numbered in order

0 = Enable (Note 3)

1= Disabled (default)

00 = Reserve 10 = XOR mode Enabled 01 = ALLZ mode Enabled (Note 3)

11 = Disabled (default)

0 = Dynamic ODT Disabled

1 = Dynamic ODT Enabled 0 = Normal operation(Default):

Lane Numbered in Order

0 = Only Digital Display Port or PCIE is operational (Default)

1 =Digital display Port and PCIe are operting simulataneously via the PEG port

0 =No SDVO Card Present (Default)

1 = SDVO Card Present

0 = LFP Disabled (Default)

1= LFP Card Present; PCIE disabledL_DDC_DATA

E

page 218

(Default)

JV71-MV DDR3 Madison

1 1

JV71-MV DDR3 Madison

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet of

Date: Sheet of

Reference

JV71-MV DDR3 Madison

Taipei Hsien 221, Taiwan, R.O.C.

2 62Wednesday, October 28, 2009

-1

A

3D3V_S0

R554

1 2

0R0603-PAD

4 4

3 3

2 2

CPU_SEL24,7

CLK_ICH1413

CLK48_ICH13

PCLK_KBC34 PCLK_ICH13

3D3V_VDD48_S0

12

C456

3D3V_S0

12

C457

SC4D7U6D3V3KX-GP

DY

3D3V_S0

RN48

6 7 8

SRN10KJ-6-GP

RN46

1 2 3 4 5

SRN33J-7-GP

12

C455

SC1U16V3ZY-GP

DY

12

R260

R260 10KR2J-3-GP

10KR2J-3-GP

DIS

PCLKCLK4

12

R254

R254 10KR2J-3-GP

10KR2J-3-GP

UMA

PCLKCLK2

45

CPU_SEL2_R

3 2

PCLKCLK5

1

CPU_SEL2_R

8

CLK48

7

PCLKCLK4

6

PCLKCLK5

CLK48_5158E CLK_ICH14 PCLK_FW H PCLK_ICH PCLK_KBC CLK48_ICH

SCD1U16V2ZY-2GP

EC46 SC33P50V2JN-3GP

EC46 SC33P50V2JN-3GP EC25 SC33P50V2JN-3GP

EC25 SC33P50V2JN-3GP EC24 SC33P50V2JN-3GP

EC24 SC33P50V2JN-3GP EC23 SC33P50V2JN-3GP

EC23 SC33P50V2JN-3GP EC39 SC33P50V2JN-3GP

EC39 SC33P50V2JN-3GP EC48 SC33P50V2JN-3GP

EC48 SC33P50V2JN-3GP

1 2 1 2

DY

1 2

DY

1 2

DY

1 2

DY

1 2

DY

DY DY

DY

1D05V_S0

CPU_SEL04,7 CLK48_5158E31

modify by RF

EMI capacitor for Antenna team suggestion

ICS9LPRS365YGLFT setting table

PIN NAME DESCRIPTION

Byte 5, bit 7 0 = PCI0 enabled (default)

PCI0/CR#_A

PCI1/CR#_B

PCI2/TME PCI3

1 1

PCI4/27M_SEL PCI_F5/ITP_EN

SRCT3/CR#_C

1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair Byte 5, bit 6 0 = CR#_A controls SRC0 pair (default), 1= CR#_A controls SRC2 pair

Byte 5, bit 5 0 = PCI1 enabled (default) 1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair Byte 5, bit 4 0 = CR#_B controls SRC1 pair (default) 1= CR#_B controls SRC4 pair

0 = Overclocking of CPU and SRC Allowed 1 = Overclocking of CPU and SRC NOT allowed

0 = Pin17 as SRC-1, Pin18 as SRC-1#, Pin13 as DOT96, Pin14 as DOT96# 1 = Pin17 as 27MHz, Pin 18 as 27MHz_SS, Pin13 as SRC-0, Pin14 as SRC-0#

0 =SRC8/SRC8# 1 = ITP/ITP#

Byte 5, bit 3 0 = SRC3 enabled (default) 1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair Byte 5, bit 2 0 = CR#_C controls SRC0 pair (default), 1= CR#_C controls SRC2 pair

A

B

CL=20pF±0.2pF

C453

C453 SC33P50V2JN-3GP

SC33P50V2JN-3GP

1 2

C452

2nd = 82.30005.951

1 2

SC27P50V2JN-2-GP

CLK48_5158E

C451

PCLK_FW H35

B

3D3V_S0

DY

12

SC47P50V2JN-3GP

R255 33R2J-2-GPR255 33R2J-2-GP

SCD1U16V2ZY-2GP

12

C450

DY

GEN_XTAL_OUT

X5

X5 X-14D31818M-35GP

X-14D31818M-35GP

82.30005.891

GEN_XTAL_IN

R251 2K2R2J-2-GPR251 2K2R2J-2-GP

R253 33R2J-2-GPR253 33R2J-2-GP

12

C417

PM_STPCPU#13

12

C435

12 12

PM_STPPCI#13

SMBC_ICH15,16,17

SMBD_ICH15,16,17

CLK_PW RGD13

R24910KR2J-3-GPDYR24910KR2J-3-GP

12

SCD1U16V2ZY-2GP

SC4D7U6D3V3KX-GP

SCD1U16V2ZY-2GP

DY

12

TP158TPAD14-GP TP158TPAD14-GP

CPU_SEL14,7

CPU_SEL2_R

PIN NAME DESCRIPTION

SRCC3/CR#_D

SRCC7/CR#_E

SRCT7/CR#_F

SRCC11/CR#_G

SRCT11/CR#_H

12

C444

CLK48

PCLKCLK0 PCLKCLK1 PCLKCLK2 PCLKCLK3

1

PCLKCLK4 PCLKCLK5

C

SCD1U16V2ZY-2GP

12

C436

3 2

17

45 44

7 6

63

8 10 11 12 13 14

64

5 55

SCD1U16V2ZY-2GP

12

C416

3D3V_S0 1D05V_S0

U24

X1 X2

USB_48MHZ/FSLA

PCI_STOP# CPU_STOP#

SCLK SDATA

CK_PWRGD/PD#

PCI0/CR#_A PCI1/CR#_B PCI2/TME PCI3 PCI4/27_SELECT PCI_F5/ITP_EN

FSLB/TEST_MODE REF0/FSLC/TEST_SEL

NC#55

3D3V_VDD48_S0

4

9

16

23

46

62

VDD48

VDDPCI

VDDREF

VDDSRC

VDDCPU

GNDREF

GNDPCI

GND48

1

15

18

22

SATACLKREQ#13 CLK_MCH_OE#7 LAN_CLKREQ#25 WLAN_CLKREQ#32

Byte 5, bit 1 0 = SRC3 enabled (default) 1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair Byte 5, bit 0 0 = CR#_D controls SRC1 pair (default) 1= CR#_D controls SRC4 pair

Byte 6, bit 7 0 = SRC7# enabled (default) 1= CR#_F controls SRC6

Byte 6, bit 6 0 = SRC7 enabled (default) 1= CR#_F controls SRC8

Byte 6, bit 5 0 = SRC11# enabled (default) 1= CR#_G controls SRC9

Byte 6, bit 4 0 = SRC11 enabled (default) 1= CR#_H controls SRC10

C

D

SCD1U16V2ZY-2GP

SC4D7U6D3V3KX-GP

12

C419

R694

1 2

UMA

1 2 3

4

UMA

12

C445

0R2J-2-GP

4

1 23

SEL2 FSC

12

C430

DY

19

27

33

43

52

56

61

VDDPLL3

VDD96_IO

VDDSRC_IO

VDDCPU_IO

VDDPLL3_IO

27MHZ_NONSS/SRCT1/SE1

27MHZ_SS/SRCC1/SE2

GND

GNDSRC

GNDCPU

GND

ICS9LPRS365BKLFT-GP-U

26

30

36

49

59

65

71.09365.A03

2nd = 71.09365.A03 71.08513.003

CPUT0 CPUC0

CPUT1_F

CPUC1_F

CPUT2_ITP/SRCT8

CPUC2_ITP/SRCC8

SRCT7/CR#_F

SRCC7/CR#_E

SRCT6 SRCC6

SRCT10 SRCC10

SRCT11/CR#_H

SRCC11/CR#_G

SRCT9 SRCC9

SRCT4 SRCC4

SRCT3/CR#_C

SRCC3/CR#_D

SRCT2/SATAT

SRCC2/SATAC

SRCT0/DOTT_96

SRCC0/DOTC_96

RN45

1

8

2

7

3

6

4 5

DY

SRN470J-3-GP

60 58

57 54

53

51 50

48 47

41 42

40 39

37 38

34 35

31 32

28 29

24 25

20 21

PCLKCLK0 PCLKCLK1 CR#_H CR#_G

CR#_H CR#_G

ATI-ES

DREFSSCLK_1 DREFSSCLK_1#

DREFCLK_1 DREFCLK_1#

3D3V_S0

123

45

678

SB 1008

RN47

RN47 SRN10KJ-6-GP

SRN10KJ-6-GP

DY

1 0

12

C448

RN76

RN76 SRN0J-6-GP

SRN0J-6-GP RN44

RN44 SRN0J-6-GP

SRN0J-6-GP

SCD1U16V2ZY-2GP

12

C454

SEL1 FSB

0 1 0 1

SCD1U16V2ZY-2GP

CLK_CPU_BCLK 4 CLK_CPU_BCLK# 4

CLK_MCH_BCLK 6 CLK_MCH_BCLK# 6

CLK_PCIE_ICH 13 CLK_PCIE_ICH# 13

CLK_PCIE_PEG 52 CLK_PCIE_PEG# 52

CLK_PCIE_LAN 25 CLK_PCIE_LAN# 25

CLK_PCIE_MINI1 32 CLK_PCIE_MINI1# 32

CLK_MCH_3GPLL 7 CLK_MCH_3GPLL# 7

CLK_PCIE_SATA 12 CLK_PCIE_SATA# 12 JTAG_TCK 53

DREFSSCLK 7 DREFSSCLK# 7

DREFCLK 7 DREFCLK# 7

SEL0 FSA

0 1 0 0 0 0

JV71-MV DDR3 Madison

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet of

Clock Generator

JV71-MV DDR3 Madison

E

3D3V_S0

SCD1U16V2ZY-2GP

12

C418

DY

CPU NB SB DMI

NEWCARD GPU LAN

WLAN NB CLK

SB SATA

NB NB

CPU

FSB

100M 133M

1 01

166M 200M

533M 667M 800M

1067M266M

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

3 62Wednesday, October 28, 2009

E

X

-1

A

B

C

D

E

1

A

H_A#[35..3]

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

1 OF 4

CPU1A

J4

A3#

L5

A4#

L4

A5#

K5

A6#

M3

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L2

A13#

P4

A14#

P1

A15#

R1

A16#

M1

ADSTB0#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L1

REQ4#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U1

A23#

R4

A24#

T5

A25#

T3

A26#

W2

A27#

W5

A28#

Y4

A29#

U2

A30#

V4

A31#

W3

A32#

AA4

A33#

AB2

A34#

AA3

A35#

V1

ADSTB1#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD#M4

N5

RSVD#N5

T2

RSVD#T2

V3

RSVD#V3

B2

RSVD#B2

C3

RSVD#C3

D2

RSVD#D2

D22

RSVD#D22

D3

RSVD#D3

F6

RSVD#F6

B1

KEY_NC

BGA479-SKT6-GPU7

62.10079.001

2nd = 62.10053.401

H_DINV#[3..0]

TP74 TPAD14-GPTP74 TPAD14-GP

1

H1

ADS#

E2

BNR#

ADDR GROUP 0

ADDR GROUP 1

XDP/ITP SIGNALS CONTROL

XDP/ITP SIGNALS CONTROL THERMAL

THERMAL

PROCHOT#

ICH

THERMTRIP#

HCLK

RESERVED

BPRI#

DEFER#

DRDY# DBSY#

BR0#

IERR#

INIT#

LOCK#

RESET#

RS0# RS1# RS2#

TRDY#

HIT#

HITM#

BPM0# BPM1# BPM2# BPM3# PRDY# PREQ#

TCK

TDO TMS

TRST#

DBR#

THRMDA THRMDC

BCLK0 BCLK1

TDI

G5 H5

F21 E1

F1 D20

B3 H4 C1

F3 F4 G3 G2

G6 E4

XDP_BPM#0

AD4

XDP_BPM#1

AD3

XDP_BPM#2

AD1

XDP_BPM#3

AC4

XDP_BPM#4

AC2

XDP_BPM#5

AC1

XDP_TCK

AC5

XDP_TDI

AA6

XDP_TDO

AB3

XDP_TMS

AB5

XDP_TRST#

AB6

XDP_DBRESET#

C20

D21 A24 B25

C7

A22 A21

H_RS#0 H_RS#1 H_RS#2

H_ADS# 6 H_BNR# 6 H_BPRI# 6

H_DEFER# 6 H_DRDY# 6 H_DBSY# 6

H_BREQ#0 6

H_IERR#

H_INIT# 12 H_LOCK# 6

H_CPURST# 6,50

H_TRDY# 6 H_HIT# 6

H_HITM# 6

TP28 TPAD14-GPTP28 TPAD14-GP

1

TP27 TPAD14-GPTP27 TPAD14-GP

1

TP26 TPAD14-GPTP26 TPAD14-GP

1

TP32 TPAD14-GPTP32 TPAD14-GP

1

TP29 TPAD14-GPTP29 TPAD14-GP

1

TP30 TPAD14-GPTP30 TPAD14-GP

1

TP34 TPAD14-GPTP34 TPAD14-GP

1

TP50 TPAD14-GPTP50 TPAD14-GP

1

TP31 TPAD14-GPTP31 TPAD14-GP

1

TP49 TPAD14-GPTP49 TPAD14-GP

1

TP33 TPAD14-GPTP33 TPAD14-GP

1

TP88 TPAD14-GPTP88 TPAD14-GP

1

CPU_PROCHOT#_1 H_THERMDA 33

H_THERMDC 33

H_CPURST#

1 2

EC75 SC33P50V2JN-3GP

DY

EMI capacitor

XDP_TMS XDP_TDI XDP_BPM#5 XDP_TDO H_CPURST#

XDP_DBRESET#

XDP_TCK XDP_TRST#

B

R54 54D9R2F-L1-GPR54 54D9R2F-L1-GP R55 54D9R2F-L1-GPR55 54D9R2F-L1-GP R46 54D9R2F-L1-GPR46 54D9R2F-L1-GP R47 54D9R2F-L1-GP

R47 54D9R2F-L1-GP R113 51R2F-2-GP

R113 51R2F-2-GP

R105 1KR2J-1-GP

R32 54D9R2F-L1-GPR32 54D9R2F-L1-GP R33 54D9R2F-L1-GPR33 54D9R2F-L1-GP

All place within 2" to CPU

1D05V_S0

12

R88

R88 56R2J-4-GP

56R2J-4-GP

SC47P50V2JN-3GP

H_RS#[2..0] 6

1D05V_S0

12

PM_THRMTRIP-A# 7,12,38

CLK_CPU_BCLK 3 CLK_CPU_BCLK# 3

1 2 1 2 1 2 1 2

DY

1 2

DY

1 2

DY

1 2 1 2

Place testpoint on H_IERR# with a GND

0.1" away

C104

DY

1 2

modify by RF

H_THERMDA

H_THERMDC

Close to CPU

R89

R89 68R2-GP

68R2-GP

R97

1 2

DY

0R2J-2-GP

0R2J-2-GP C90 SC47P50V2JN-3GP

C90 SC47P50V2JN-3GP

1 2

DY

PH @ page48

Layout Note: "CPU_GTLREF0"

0.5" max length.

1D05V_S0

3D3V_S0

CPU_PROCHOT#_R 40

should connect toPM_THRMTRIP# without T-ingICH9 and MCH

1D05V_S0

R309

2KR2F-3-GP

1 2

R119 1KR2J-1-GP

1 2

R114 1KR2J-1-GP

12

C116

C116 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

DY

modify by RF

1KR2F-3-GP

1KR2F-3-GP R312

R312

1 2 12

DY

C525

12

DY

SCD1U10V2KX-4GP

C

SC1KP50V2KX-1GP

TEST1

TEST2

TEST4

12

DY

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8

H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14

H_DSTBN#06 H_DSTBP#06 H_DINV#06

H_DSTBN#16 H_DSTBP#16 H_DINV#16

CPU_GTLREF0

C526

TP87TPAD14-GP TP87TPAD14-GP TP25TPAD14-GP TP25TPAD14-GP

TP180TPAD14-GP TP180TPAD14-GP

CPU_SEL03,7 CPU_SEL13,7 CPU_SEL23,7

Net "TEST4" as short as possible, make sure "TEST4" routing is reference to GND and away other noisy signals

Place these TP on button-side, easy to measure.

H_D#15

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31

TEST1 TEST2

RSVD_CPU_12

1

TEST4 RSVD_CPU_13

1

RSVD_CPU_14RSVD_CPU_11

1

H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGD H_CPUSLP# H_INIT# H_CPURST#

CPU1B

E22

D0#

F24

D1#

E26

D2#

G22

D3#

F23

D4#

G25

D5#

E25

D6#

E23

D7#

K24

D8#

G24

D9#

J24

D10#

J23

D11#

H22

D12#

F26

D13#

K22

D14#

H23

D15#

J26

DSTBN0#

H26

DSTBP0#

H25

DINV0#

N22

D16#

K25

D17#

P26

D18#

R23

D19#

L23

D20#

M24

D21#

L22

D22#

M23

D23#

P25

D24#

P23

D25#

P22

D26#

T24

D27#

R24

D28#

L25

D29#

T25

D30#

N25

D31#

L26

DSTBN1#

M26

DSTBP1#

N24

DINV1#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

B22

BSEL0

B23

BSEL1

C21

BSEL2

BGA479-SKT6-GPU7

TP76 TPAD14-GPTP76 TPAD14-GP

1

TP95 TPAD14-GPTP95 TPAD14-GP

1

TP114 TPAD14-GPTP114 TPAD14-GP

1

TP81 TPAD14-GPTP81 TPAD14-GP

1

TP78 TPAD14-GPTP78 TPAD14-GP

1

TP92 TPAD14-GPTP92 TPAD14-GP

1

TP86 TPAD14-GPTP86 TPAD14-GP

1

2 OF 4

D

DATA GRP0 DATA GRP1

MISC

DATA GRP2DATA GRP3

DSTBN2# DSTBP2#

DSTBN3# DSTBP3#

COMP2 COMP3

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

H_DSTBN#[3..0] H_DSTBP#[3..0] H_D#[63..0]

H_D#32

Y22

D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47#

DINV2#

D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63#

DINV3# COMP0

COMP1

SLP#

PSI#

Comp0, 2 connect with Zo=27.4 ohm, make trace length shorter than 0.5" . Comp1, 3 connect with Zo=55 ohm, make trace length shorter than 0.5" .

JV71-MV DDR3 Madison

Title

Size Document Number Rev

Date: Sheet of

AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22

AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20

R26 U26 AA1 Y1

E5 B5 D24 D6 D7 AE6

H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

COMP0 COMP1 COMP2 COMP3

Layout Note:

JV71-MV DDR3 Madison

H_DINV#[3..0] 6 H_DSTBN#[3..0] 6 H_DSTBP#[3..0] 6 H_D#[63..0] 6

H_DSTBN#2 6 H_DSTBP#2 6 H_DINV#2 6

H_DSTBN#3 6 H_DSTBP#3 6 H_DINV#3 6

R71 27D4R2F-L1-GPR71 27D4R2F-L1-GP

1 2

R67 54D9R2F-L1-GPR67 54D9R2F-L1-GP

1 2

R57 27D4R2F-L1-GPR57 27D4R2F-L1-GP

1 2

R60 54D9R2F-L1-GPR60 54D9R2F-L1-GP

1 2

H_DPRSTP# 7,12,40 H_DPSLP# 12 H_DPWR# 6

H_CPUSLP# 6 H_PSI# 40

CPU (1 of 2)

12

C102

DY

SC100P50V2JN-3GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

E

H_PWRGD 12,50

4 62Wednesday, October 28, 2009

-1

H_A#[35..3]6

4 4

H_ADSTB#06 H_REQ#[4..0]6

3 3

H_ADSTB#16

H_A20M#12

H_FERR#12

H_IGNNE#12

H_STPCLK#12

H_INTR12 H_NMI12 H_SMI#12

2 2

TP97TPAD14-GP TP97TPAD14-GP

1 1

A

VCC_CORE

B

VCC_CORE

C

D

E

12

C86

C56

SCD1U10V2KX-4GP

VCC_CORE

4 4

3 3

2 2

1 1

CPU1C

A7

VCC

A9

VCC

A10

VCC

A12

VCC

A13

VCC

A15

VCC

A17

VCC

A18

VCC

A20

VCC

B7

VCC

B9

VCC

B10

VCC

B12

VCC

B14

VCC

B15

VCC

B17

VCC

B18

VCC

B20

VCC

C9

VCC

C10

VCC

C12

VCC

C13

VCC

C15

VCC

C17

VCC

C18

VCC

D9

VCC

D10

VCC

D12

VCC

D14

VCC

D15

VCC

D17

VCC

D18

VCC

E7

VCC

E9

VCC

E10

VCC

E12

VCC

E13

VCC

E15

VCC

E17

VCC

E18

VCC

E20

VCC

F7

VCC

F9

VCC

F10

VCC

F12

VCC

F14

VCC

F15

VCC

F17

VCC

F18

VCC

F20

VCC

AA7

VCC

AA9

VCC

AA10

VCC

AA12

VCC

AA13

VCC

AA15

VCC

AA17

VCC

AA18

VCC

AA20

VCC

AB9

VCC

AC10

VCC

AB10

VCC

AB12

VCC

AB14

VCC

AB15

VCC

AB17

VCC

AB18

VCC

BGA479-SKT6-GPU7

3 OF 4

VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP

VCCA VCCA

VID0 VID1 VID2 VID3 VID4 VID5 VID6

VCCSENSE

VSSSENSE

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26 C26

AD6 AF5 AE5 AF4 AE3 AF3 AE2

AF7

AE7

VCC_CORE

H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6

1D05V_S0_CPU

C57

SCD1U10V2KX-4GP

12

G2

1 2

GAP-CLOSE-PWR

C58

SCD1U10V2KX-4GP

12

H_VID[6..0] 40

VCC_CORE

12

R25

12

R24

100R2F-L1-GP-U

12

C55

C85

SCD1U10V2KX-4GP

1D05V_S0

SCD1U10V2KX-4GP

layout note: "1D5V_VCCA_S0" as short as possible

1D5V_VCCA_S0

12

C603

SCD01U16V2KX-3GP

Layout Note:

VCCSENSE and VSSSENSE lines should be of equal length.

Layout Note: Provide a test point (with no stub) to connect a differential probe between VCCSENSE and VSSSENSE at the location where the two 54.9ohm resistors terminate the 55 ohm transmission line.

12

C89

C87

SC10U6D3V5MX-3GP

DY

FCM1608KF-1-GP

1 2

L18

68.00217.161

C606

2nd = 68.00248.061

SC10U6D3V5MX-3GP

VCC_SENSE 40

VSS_SENSE 40

SC10U6D3V5MX-3GP

1D5V_S0

12

C88

C53

SC10U6D3V5MX-3GP

12

C50

SC10U6D3V5MX-3GP

1D05V_S0

12

C51

DY

12

C67

SCD1U10V2KX-4GP

12

C553

C52

SC10U6D3V5MX-3GP

DY

12

C75

C79

SCD1U10V2KX-4GP

12

C552

C538

SC10U6D3V5MX-3GP

DY

12

C83

C80

SC4D7U6D3V3KX-GP

SCD1U10V2KX-4GP

DY

12

C539

SC10U6D3V5MX-3GP

12

C84

SCD1U50V3KX-GP

12

C548

C547

SC10U6D3V5MX-3GP

DY

12

C537

C536

SC10U6D3V5MX-3GP

4 OF 4

CPU1D

A4

VSS

A8

VSS

A11

VSS

A14

VSS

A16

DY

1

TP_AF2_CPU

TP23TPAD14-GP TP23TPAD14-GP

VSS

A19

VSS

A23

VSS

AF2

VSS

B6

VSS

B8

VSS

B11

VSS

B13

VSS

B16

VSS

B19

VSS

B21

VSS

B24

VSS

C5

VSS

C8

VSS

C11

VSS

C14

VSS

C16

VSS

C19

VSS

C2

VSS

C22

VSS

C25

VSS

D1

VSS

D4

VSS

D8

VSS

D11

VSS

D13

VSS

D16

VSS

D19

VSS

D23

VSS

D26

VSS

E3

VSS

E6

VSS

E8

VSS

E11

VSS

E14

VSS

E16

VSS

E19

VSS

E21

VSS

E24

VSS

F5

VSS

F8

VSS

F11

VSS

F13

VSS

F16

VSS

F19

VSS

F2

VSS

F22

VSS

F25

VSS

G4

VSS

G1

VSS

G23

VSS

G26

VSS

H3

VSS

H6

VSS

H21

VSS

H24

VSS

J2

VSS

J5

VSS

J22

VSS

J25

VSS

K1

VSS

K4

VSS

K23

VSS

K26

VSS

L3

VSS

L6

VSS

L21

VSS

L24

VSS

M2

VSS

M5

VSS

M22

VSS

M25

VSS

N1

VSS

N4

VSS

N23

VSS

N26

VSS

P3

VSS

BGA479-SKT6-GPU7

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

TP_AE26_CPU TP_A2_CPU

TP_A25_CPU

1 1

1

TP174 TPAD14-GPTP174 TPAD14-GP TP98 TPAD14-GPTP98 TPAD14-GP

TP181 TPAD14-GPTP181 TPAD14-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

JV71-MV DDR3 Madison

Date: Sheet of

A

B

C

D

Date: Sheet of

JV71-MV DDR3 Madison

Taipei Hsien 221, Taiwan, R.O.C.

CPU (2 of 2)

E

-1

5 62Wednesday, October 28, 2009

-1

5

H_SWING

C619

SCD1U10V2KX-4GP

H_RCOMP

1D05V_S0

12

R381

R381 221R2F-2-GP

221R2F-2-GP

12

R382

R382 100R2F-L1-GP-U

100R2F-L1-GP-U

D D

H_SWING routing Trace width and Spacing use 10 / 20 mil

H_SWING Resistors and Capacitors close MCH 500 mil ( MAX )

12

C C

H_RCOMP routing Trace width and Spacing use 10 / 20 mil

1 2

24D9R2F-L-GP

R380

Place them near to the chip ( < 0.5")

B B

H_CPURST#

1 2

EC76 SC33P50V2JN-3GP

DY

EMI capacitor

1D05V_S0

1 2

12

R370

R370 1KR2F-3-GP

1KR2F-3-GP

R389

R389 2KR2F-3-GP

2KR2F-3-GP

4

H_AVREF

H_D#[63..0]

SCD1U16V2ZY-2GP

12

C614

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_SWING H_RCOMP

H_CPURST#4,50 H_CPUSLP#4

M11

N12

P13

N10

AD14

Y10 Y12 Y14

AA8

AA13

AA9 AA11 AD11 AD10 AD13 AE12

AE9

AA2

AD8

AA3

AD3

AD7 AE14

AF3

AC1

AE3

AC3 AE11

AE8

AG2

AD6

C12

E11

A11

B11

F2

G8

F8 E6

G2

H6 H2 F6 D4 H3

M9

J1 J2

J6 P2 L2 R2 N9 L6

M5

J3 N2 R1 N5 N6

N8 L7

M3

Y3 Y6

Y7

W2

Y9

C5 E3

H_D#[63..0]4

3

NB1A

H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63

H_SWING H_RCOMP

H_CPURST# H_CPUSLP#

H_AVREF H_DVREF

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

HOST

1 OF 10

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS# H_ADSTB#_0 H_ADSTB#_1

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#

H_HITM#

H_LOCK#

H_TRDY#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

H_REQ#_0 H_REQ#_1

H_REQ#_2 H_REQ#_3

H_REQ#_4

H_RS#_0 H_RS#_1 H_RS#_2

A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20

H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9

J8 L3 Y13 Y1

L10 M7 AA5 AE6

L9 M8 AA6 AE5

B15 K13 F13 B13 B14

B6 F12 C8

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3

H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_RS#0 H_RS#1 H_RS#2

2

H_A#[35..3]

H_ADS# 4 H_ADSTB#0 4 H_ADSTB#1 4 H_BNR# 4

H_BPRI# 4

H_BREQ#0 4

H_DEFER# 4

H_DBSY# 4

CLK_MCH_BCLK 3 CLK_MCH_BCLK# 3

H_DPWR# 4

H_DRDY# 4 H_HIT# 4 H_HITM# 4

H_LOCK# 4 H_TRDY# 4

H_DINV#[3..0]

H_DSTBN#[3..0]

H_DSTBP#[3..0]

1

H_A#[35..3] 4

H_DINV#[3..0] 4

H_DSTBN#[3..0] 4

H_DSTBP#[3..0] 4

H_REQ#[4..0] 4

H_RS#[2..0] 4

A A

5

4

3

2

JV71-MV DDR3 Madison

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

JV71-MV DDR3 Madison

Date: Sheet of

JV71-MV DDR3 Madison

Taipei Hsien 221, Taiwan, R.O.C.

Cantiga (1 of 6)

6 62Wednesday, October 28, 2009

1

-1

5

D D

CPU_SEL03,4

R192

1 2

0R0402-PAD

R195

1 2

0R0402-PAD

12

R203100R2J-2- GP R203100R 2J-2-GP C324

C324

DY

CPU_SEL13,4 CPU_SEL23,4

PM_EXTTS#0 PM_EXTTS#1

RSTIN# NB_THERMT RIP# PM_DPRSLPVR _MCH

12

PM_DPRSLPVR _MCH

CFG9

CFG16

CFG20

C C

1D5V_S3

12

R443

3D3V_S0

R193 4K02R2F-GP

1 2

DY

R385 2K21R2F-GP

1 2

DY

R556 2K21R2F-GP

1 2

DY

B B

PWROK

1 2

EC77 SC33P50V2JN-3GP

CFG20

CFG9

CFG16

DY

R443 80D6R2F-L-G P

80D6R2F-L-G P

12

R442

80D6R2F-L-G P

PM_THRMTR IP-A#4,12,38

PM_DPRSLPVR13,40

M_RCOMPP

M_RCOMPN

PLT_RST1#13,25,31,32,34,35,52

PM_SYNC#13 H_DPRSTP#4,12,40 PM_EXTTS#016,17

PWROK13,33

SC100P50V2JN-3 GP

EMI capacitor

A A

RN34

LCTLA_CLK LCTLB_DATA

PM_EXTTS#0 PM_EXTTS#1

5

RN34

4

SRN10KJ-5-G P

RN35

4

SRN10KJ-5-G P

UMA

AH10 AH12 AH13

AL34

AK34 AN35 AM35

AY21

BG23

BF23 BH18

BF18

AT40

AT11

BG48

BF48 BD48 BC48 BH47 BG47

BE47 BH46

BF46 BG45 BH44 BH43

3D3V_S0

1 23

NB1B

M36

RESERVED#M36

N36

RESERVED#N36

R33

RESERVED#R33

T33

RESERVED#T33

AH9

RESERVED#AH9 RESERVED#AH10 RESERVED#AH12 RESERVED#AH13

K12

RESERVED#K12 RESERVED#AL34 RESERVED#AK34 RESERVED#AN35 RESERVED#AM35

T24

RESERVED#T24

B31

RESERVED#B31

B2

RESERVED#B2

M1

RESERVED#M1

RESERVED#AY21

RESERVED#BG23 RESERVED#BF23 RESERVED#BH18 RESERVED#BF18

T25

CFG_0

R25

CFG_1

P25

CFG_2

P20

CFG_3

P24

CFG_4

C25

CFG_5

N24

CFG_6

M24

CFG_7

E21

CFG_8

C23

CFG_9

C24

CFG_10

N21

CFG_11

P21

CFG_12

T21

CFG_13

R20

CFG_14

M20

CFG_15

L21

CFG_16

H21

CFG_17

P29

CFG_18

R28

CFG_19

T28

CFG_20

R29

PM_SYNC#

B7

PM_DPRSTP#

N33

PM_EXT_TS#_0

P32

PM_EXT_TS#_1 PWROK RSTIN#

T20

THERMTRIP#

R32

DPRSLPVR

NC#BG48 NC#BF48 NC#BD48 NC#BC48 NC#BH47 NC#BG47 NC#BE47 NC#BH46 NC#BF46 NC#BG45 NC#BH44 NC#BH43

BH6

NC#BH6

BH5

NC#BH5

BG4

NC#BG4

BH3

NC#BH3

BF3

NC#BF3

BH2

NC#BH2

BG2

NC#BG2

BE2

NC#BE2

BG1

NC#BG1

BF1

NC#BF1

BD1

NC#BD1

BC1

NC#BC1

F1

NC#F1

A47

NC#A47

CANTIGA-GM- GP-U-NF

71.CNTIG.00U

4

1D05V_S0

MCH_TSATN #

GFXVR_EN

RSVD

CFG

PM

NC

DY

SM_RCOMP_VOH SM_RCOMP_VOL

DDR CLK/ CONTROL/COMPENSATION

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLK

DMI

GRAPHICS VID

MEHDA

DDPC_CTRLDATA SDVO_CTRLDATA

MISC

12

R387

56R2J-4-GP

R178

R178 100KR2F-L1-GP

100KR2F-L1-GP

1 2

2 OF 10

SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1

SA_CK#_0 SA_CK#_1 SB_CK#_0

SB_CK#_1

SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1

SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1

SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_VREF

SM_PWROK

SM_REXT

SM_DRAMRST# DPLL_REF_CLK

DPLL_REF_CLK#

PEG_CLK

PEG_CLK#

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST# CL_VREF

DDPC_CTRLCLK SDVO_CTRLCLK

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCLK HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

GFXVR_EN 45

AP24 AT21 AV24 AU20

AR24 AR21 AU24 AV20

BC28 AY28 AY36 BB36

BA17 AY16 AV16 AR13

BD17 AY17 BF15 AY13

M_RCOMPP

BG22

M_RCOMPN

BH21

SM_RCOMP_VOH

BF28

SM_RCOMP_VOL

BH28 AV42

DDR2 : connect to GND

AR36

SM_REXT

BF17

DDR3_DR AMRST#

BC36 B38

A38 E41 F41

F43 E43

AE41 AE37 AE47 AH39

AE40 AE38 AE48 AH40

AE35 AE43 AE46 AH42

AD35 AE44 AF46 AH43

B33 B32 G33 F33 E33

GFXVR_EN

C34

AH37 AH36 AN36 AJ35

MCH_CLVRE F

AH34

for HDMI port C

N28 M28 G36 E36

CLK_MCH_OE#

K36 H36

MCH_TSATN #

B12

HDA_BCLK

B28

HDA_RST#

B30

HDA_SDI

B29

HDA_SDO

C29

HDA_SYNC

A28

M_CLK_DDR0 1 6 M_CLK_DDR1 1 6 M_CLK_DDR2 1 7 M_CLK_DDR3 1 7

M_CLK_DDR#0 16 M_CLK_DDR#1 16 M_CLK_DDR#2 17 M_CLK_DDR#3 17

M_CKE0 16 M_CKE1 16 M_CKE2 17 M_CKE3 17

M_CS0# 16 M_CS1# 16 M_CS2# 17 M_CS3# 17

M_ODT0 16 M_ODT1 16 M_ODT2 17 M_ODT3 17

R444 499R2F -2-GPR444 499R2F- 2-GP

1 2

DREFCLK# 3

DREFSSCLK # 3

CLK_MCH_3GPL L 3

CLK_MCH_3GPL L# 3

DMI_TXN0 13 DMI_TXN1 13 DMI_TXN2 13 DMI_TXN3 13

DMI_TXP0 13 DMI_TXP1 13 DMI_TXP2 13 DMI_TXP3 13

DMI_RXN0 13 DMI_RXN1 13 DMI_RXN2 13 DMI_RXN3 13

DMI_RXP0 13 DMI_RXP1 13 DMI_RXP2 13 DMI_RXP3 13

GFX_VID0 GFX_VID1 GFX_VID2 GFX_VID3 GFX_VID4

HDA_SYNC HDA_RST# HDA_SDO

DDR3_DR AMRST# 16,17

DREFCLK 3

DREFSSCLK 3

GFX_VID[4..0] 45

CL_CLK0 13

CL_DATA0 13 PWROK 13,33 CL_RST#0 13

GMCH_HDMI_C LK 20

GMCH_HDMI_D ATA 20 CLK_MCH_OE# 3 MCH_ICH_SYNC # 13

R419

1 2

UMA

33R2J-2-GP

33R2J-2-GP RN36

RN36

1

8

2

7

3

6

4 5

UMA

SRN33J-4-G P

R445 1KR2F-3- GPR445 1K R2F-3-GP

12

R441

R441 3K01R2F-3-GP

3K01R2F-3-GP

R446

R446 1KR2F-3-GP

1KR2F-3-GP

1 2

3

DDR_VREF _S3_1

1D05V_S0

12

C288

SCD1U10V2KX-4GP

ACZ_SDIN3

ACZ_BIT_CLKHDA_BCLK ACZ_SYNC_R ACZ_RST#_R ACZ_SDATAO UT_R

1D5V_S3

12

C756

C756 SCD01U16V2KX- 3GP

SCD01U16V2KX- 3GP

12

C757

C757 SCD01U16V2KX- 3GP

SCD01U16V2KX- 3GP

3

SM_PWROK 38

0.75V

12

C335

SCD1U10V2KX-4GP

GMCH_BLUE19

GMCH_GREE N19

GMCH_RED19

GMCH_DDC CLK19 GMCH_DDC DATA19

GMCH_HSYNC19 GMCH_VSYNC19

R201

R201 1KR2F-3-GP

1KR2F-3-GP

1 2

12

R200

499R2F-2-GP

FOR Cantiga:500 ohm Teenah: 392 ohm

ACZ_SDIN3 12

ACZ_BIT_CLK 12 ACZ_SYNC_R 12 ACZ_RST#_R 12 ACZ_SDATAO UT_R 12

SM_RCOMP_VOH

12

C759

C759 SC2D2U6D3V 3MX-1-GP

SC2D2U6D3V 3MX-1-GP

SM_RCOMP_VOL

12

C760

C760 SC2D2U6D3V 3MX-1-GP

SC2D2U6D3V 3MX-1-GP

layout take note

CLK_DDC_ED ID18 DAT_DDC _EDID18

GMCH_LCDV DD_ON18

R183

0R0402-PAD

L_BKLTCTL18 GMCH_BL_ON34

12

GMCH_TXAC LK-18 GMCH_TXAC LK+18 GMCH_TXBC LK-18 GMCH_TXBC LK+18

GMCH_TXAOU T0-18 GMCH_TXAOU T1-18 GMCH_TXAOU T2-18

GMCH_TXAOU T0+18 GMCH_TXAOU T1+18 GMCH_TXAOU T2+18

GMCH_TXBOU T0-18 GMCH_TXBOU T1-18 GMCH_TXBOU T2-18

GMCH_TXBOU T0+18 GMCH_TXBOU T1+18 GMCH_TXBOU T2+18

1 2

R161 1K02R 2F-1-GP

L32

G32

LCTLA_CLK

M32

LCTLB_DATA

M33

CLK_DDC_ED ID

K33

DAT_DDC _EDID

LIBG L_LVBG LVDS_VREF

TV_DACA TV_DACB TV_DACC

GMCH_HS

GMCH_VS

CRT_IREF

EC79 SC12P50V2JN-3GP

EC78 SC12P50V2JN-3GP

EC21 SC12P50V2JN-3GP

J33

M29 C44 B43 E37 E38 C41 C40 B37 A37

H47 E46 G40 A40

H48 D45

F40

B40 A41

H38 G37

J37

B42 G38

F37

K37

F25 H25 K25

H24

C31 E32

E28 G28

J28 G29 H32

J32

J29 E29

L29

1 2

GMCH_LCDV DD_ON

TP189TPAD14-GP TP189TPAD14-GP

1

GMCH_BLUE GMCH_GREE N GMCH_RED

GMCH_DDC CLK GMCH_DDC DATA

R189

1 2

0R0402-PAD

R188

1 2

0R0402-PAD

UMA

FOR Cantiga: 1.02k_1% ohm Teenah: 1.3k ohm

CRT_IREF routing Trace width use 20 mil

Remove RN88 & RN89

NB1C

L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK

L_CTRL_DATA L_DDC_CLK L_DDC_DATA

L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK

LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3

LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3

LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3

LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3

TVA_DAC TVB_DAC TVC_DAC

TV_RTN

TV_DCONSEL_0 TV_DCONSEL_1

CRT_BLUE CRT_GREEN CRT_RED CRT_IRTN CRT_DDC_CLK

CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC

CANTIGA-GM- GP-U-NF

71.CNTIG.00U

ACZ_BIT_CLK

DY

ACZ_RST#_R

DY

HDA_BCLK

DY

2

LVDS

TV VGA

PCI-EXPRESS GRAPHICS

PEG_TXN0_L PEG_TXP0_L

PEG_TXN1_L PEG_TXP1_L

PEG_TXN2_L PEG_TXP2_L

PEG_TXN3_L PEG_TXP3_L

PEG_RXP3 HDMI_DETECT #_L

GMCH_RED GMCH_GREE N GMCH_BLUE

FOR UMA,change to 150 ohm (66.15156.08L)

FOR Discrete change RN to 0 ohm (66.R0036.A8L)

FOR UMA,change to 75 ohm (66.75036.08L)

2

PEG_COMPI

PEG_COMPO

PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8

PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8

PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9

PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

1 2

UMA

1 2

UMA

1 2

UMA

1 2

UMA

1 2

UMA

1 2

UMA

1 2

UMA

1 2

UMA

1 2

RN31

6 7 8

SRN0J-7-GP

3 OF 10

T37 T36

H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39

H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40

J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46

J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 AA39 AD42 AD46

C600 SCD1U 10V2KX-5GP

C600 SCD1U 10V2KX-5GP C605 SCD1U 10V2KX-5GP

C605 SCD1U 10V2KX-5GP

C596 SCD1U 10V2KX-5GP

C596 SCD1U 10V2KX-5GP C598 SCD1U 10V2KX-5GP

C598 SCD1U 10V2KX-5GP

C589 SCD1U 10V2KX-5GP

C589 SCD1U 10V2KX-5GP C592 SCD1U 10V2KX-5GP

C592 SCD1U 10V2KX-5GP

C568 SCD1U 10V2KX-5GP

C568 SCD1U 10V2KX-5GP C561 SCD1U 10V2KX-5GP

C561 SCD1U 10V2KX-5GP

R555

UMA

0R2J-2-GP

RN30

1 2 3 4 5

SRN0J-7-GP

45 3 2 1

8 7 6

TV_DACC TV_DACB TV_DACA

PEG_CMP

modify by RF

PEG_RXN[15..0] 52

PEG_RXP[15..0] 52

1 2 3

HDMI_DETECT # 20

GMCH_BL_ON GMCH_LCDV DD_ON

LIBG

CRT_IREF

GMCH_VS GMCH_HS

Cantiga (2 of 6)

1

RN82

4

SRN0J-10-G P-U

RN83

4

SRN0J-10-G P-U

RN84

4

SRN0J-10-G P-U

4

SRN0J-10-G P-U

SRN0J-10-G P-U RN85

RN85

1

1D05V_S0

12

R196 49D9R2F -GPR196 49D9R2F-GP

C270 SC47P50V2J N-3GP

PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8 PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15

PEG_RXP0 PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8 PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15

PEG_TXN0_L PEG_TXN1_L PEG_TXN2_L PEG_TXN3_L PEG_TXN4_L PEG_TXN5_L PEG_TXN6_L PEG_TXN7_L PEG_TXN8_L PEG_TXN9_L PEG_TXN10_L PEG_TXN11_L PEG_TXN12_L PEG_TXN13_L PEG_TXN14_L PEG_TXN15_L

PEG_TXP0_L PEG_TXP1_L PEG_TXP2_L PEG_TXP3_L PEG_TXP4_L PEG_TXP5_L PEG_TXP6_L PEG_TXP7_L PEG_TXP8_L PEG_TXP9_L PEG_TXP10_L PEG_TXP11_L PEG_TXP12_L PEG_TXP13_L PEG_TXP14_L PEG_TXP15_L

Close to GMCH as 500 mils.

12

DY

C220 SCD1U10V 2KX-5GP

1 2

DIS

C648 SCD1U10V 2KX-5GP

1 2

DIS

C654 SCD1U10V 2KX-5GP

1 2

DIS

C228 SCD1U10V 2KX-5GP

1 2

DIS

C233 SCD1U10V 2KX-5GP

1 2

DIS

C658 SCD1U10V 2KX-5GP

1 2

DIS

C237 SCD1U10V 2KX-5GP

1 2

DIS

C239 SCD1U10V 2KX-5GP

1 2

DIS

C265 SCD1U10V 2KX-5GP

1 2

DIS

C264 SCD1U10V 2KX-5GP

1 2

DIS

C269 SCD1U10V 2KX-5GP

1 2

DIS

C660 SCD1U10V 2KX-5GP

1 2

DIS

C671 SCD1U10V 2KX-5GP

1 2

DIS

C666 SCD1U10V 2KX-5GP

1 2

DIS

C680 SCD1U10V 2KX-5GP

1 2

DIS

C679 SCD1U10V 2KX-5GP

1 2

DIS

C213 SCD1U10V 2KX-5GP

1 2

DIS

C647 SCD1U10V 2KX-5GP

1 2

DIS

C651 SCD1U10V 2KX-5GP

1 2

DIS

C222 SCD1U10V 2KX-5GP

1 2

DIS

C229 SCD1U10V 2KX-5GP

1 2

DIS

C663 SCD1U10V 2KX-5GP

1 2

DIS

C234 SCD1U10V 2KX-5GP

1 2

DIS

C245 SCD1U10V 2KX-5GP

1 2

DIS

C259 SCD1U10V 2KX-5GP

1 2

DIS

C253 SCD1U10V 2KX-5GP

1 2

DIS

C266 SCD1U10V 2KX-5GP

1 2

DIS

C657 SCD1U10V 2KX-5GP

1 2

DIS

C667 SCD1U10V 2KX-5GP

1 2

DIS

C664 SCD1U10V 2KX-5GP

1 2

DIS

C672 SCD1U10V 2KX-5GP

1 2

DIS

C686 SCD1U10V 2KX-5GP

1 2

DIS

PEG_TXN0_L_1

UMA

PEG_TXP0_L_1

PEG_TXN1_L_1

UMA

PEG_TXP1_L_1

PEG_TXN2_L_1

UMA

PEG_TXP2_L_1

PEG_TXN3_L_1

UMA

PEG_TXP3_L_1

R61

UMA

1 2

0R2J-2-GP

Title

Size Document Numb er Rev

JV71-MV DDR3 Madison

Date: Sheet of

UMA

DIS

UMA

DIS

4

7 62Wednesd ay, October 28, 2009

PEG_TXN[15..0] 52

PEG_TXP[15..0] 52

HDMI_DATA2- 20,53 HDMI_DATA2+ 20,53

HDMI_DATA1- 20,53 HDMI_DATA1+ 20,53

HDMI_DATA0- 20,53 HDMI_DATA0+ 20,53

HDMI_CLK- 20,53 HDMI_CLK+ 20,53

PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15

PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15

RN32

2 3 1

SRN100KJ-6-G P

1 2

R384 2K37R2F -GP

1 2

R162 0R2J-2- GP

RN33

2 3 1

SRN0J-10-G P-U

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O.C .

Taipei Hsie n 221, Taiwan, R.O.C .

-1

5

NB1D

M_A_DQ[63..0]16

D D

C C

B B

M_A_DQ[63..0]

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

NB1D

AJ38

SA_DQ_0

AJ41

SA_DQ_1

AN38

SA_DQ_2

AM38

SA_DQ_3

AJ36

SA_DQ_4

AJ40

SA_DQ_5

AM44

SA_DQ_6

AM42

SA_DQ_7

AN43

SA_DQ_8

AN44

SA_DQ_9

AU40

SA_DQ_10

AT38

SA_DQ_11

AN41

SA_DQ_12

AN39

SA_DQ_13

AU44

SA_DQ_14

AU42

SA_DQ_15

AV39

SA_DQ_16

AY44

SA_DQ_17

BA40

SA_DQ_18

BD43

SA_DQ_19

AV41

SA_DQ_20

AY43

SA_DQ_21

BB41

SA_DQ_22

BC40

SA_DQ_23

AY37

SA_DQ_24

BD38

SA_DQ_25

AV37

SA_DQ_26

AT36

SA_DQ_27

AY38

SA_DQ_28

BB38

SA_DQ_29

AV36

SA_DQ_30

AW36

SA_DQ_31

BD13

SA_DQ_32

AU11

SA_DQ_33

BC11

SA_DQ_34

BA12

SA_DQ_35

AU13

SA_DQ_36

AV13

SA_DQ_37

BD12

SA_DQ_38

BC12

SA_DQ_39

BB9

SA_DQ_40

BA9

SA_DQ_41

AU10

SA_DQ_42

AV9

SA_DQ_43

BA11

SA_DQ_44

BD9

SA_DQ_45

AY8

SA_DQ_46

BA6

SA_DQ_47

AV5

SA_DQ_48

AV7

SA_DQ_49

AT9

SA_DQ_50

AN8

SA_DQ_51

AU5

SA_DQ_52

AU6

SA_DQ_53

AT5

SA_DQ_54

AN10

SA_DQ_55

AM11

SA_DQ_56

AM5

SA_DQ_57

AJ9

SA_DQ_58

AJ8

SA_DQ_59

AN12

SA_DQ_60

AM13

SA_DQ_61

AJ11

SA_DQ_62

AJ12

SA_DQ_63

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

DDR SYSTEM MEMORY A

4 OF 10

SA_BS_0 SA_BS_1 SA_BS_2

SA_RAS# SA_CAS#

SA_WE#

SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6

SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14

4

BD21 BG18 AT25

BB20 BD20 AY20

AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5

AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8

BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6

M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8

M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14

M_A_DM[7..0]

M_A_DQS[7..0]

M_A_DQS#[7..0]

M_A_A[14..0]

M_A_BS#0 16 M_A_BS#1 16 M_A_BS#2 16

M_A_RAS# 16

M_A_CAS# 16

M_A_WE# 16

M_A_DM[7..0] 16

M_A_DQS[7..0] 16

M_A_DQS#[7..0] 16

M_A_A[14..0] 16

3

NB1E

M_B_DQ[63..0]17

M_B_DQ[63..0]

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

NB1E

AK47

SB_DQ_0

AH46

SB_DQ_1

AP47

SB_DQ_2

AP46

SB_DQ_3

AJ46

SB_DQ_4

AJ48

SB_DQ_5

AM48

SB_DQ_6

AP48

SB_DQ_7

AU47

SB_DQ_8

AU46

SB_DQ_9

BA48

SB_DQ_10

AY48

SB_DQ_11

AT47

SB_DQ_12

AR47

SB_DQ_13

BA47

SB_DQ_14

BC47

SB_DQ_15

BC46

SB_DQ_16

BC44

SB_DQ_17

BG43

SB_DQ_18

BF43

SB_DQ_19

BE45

SB_DQ_20

BC41

SB_DQ_21

BF40

SB_DQ_22

BF41

SB_DQ_23

BG38

SB_DQ_24

BF38

SB_DQ_25

BH35

SB_DQ_26

BG35

SB_DQ_27

BH40

SB_DQ_28

BG39

SB_DQ_29

BG34

SB_DQ_30

BH34

SB_DQ_31

BH14

SB_DQ_32

BG12

SB_DQ_33

BH11

SB_DQ_34

BG8

SB_DQ_35

BH12

SB_DQ_36

BF11

SB_DQ_37

BF8

SB_DQ_38

BG7

SB_DQ_39

BC5

SB_DQ_40

BC6

SB_DQ_41

AY3

SB_DQ_42

AY1

SB_DQ_43

BF6

SB_DQ_44

BF5

SB_DQ_45

BA1

SB_DQ_46

BD3

SB_DQ_47

AV2

SB_DQ_48

AU3

SB_DQ_49

AR3

SB_DQ_50

AN2

SB_DQ_51

AY2

SB_DQ_52

AV1

SB_DQ_53

AP3

SB_DQ_54

AR1

SB_DQ_55

AL1

SB_DQ_56

AL2

SB_DQ_57

AJ1

SB_DQ_58

AH1

SB_DQ_59

AM2

SB_DQ_60

AM3

SB_DQ_61

AH3

SB_DQ_62

AJ3

SB_DQ_63

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

2

5 OF 10

BC16

SB_BS_0

BB17

SB_BS_1

BB33

SB_BS_2

AU17

SB_RAS#

BG16

SB_CAS#

BF14

SB_WE#

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9

M_B_DM[7..0]

M_B_DQS[7..0]

M_B_DQS#[7..0]

M_B_A[14..0]

DDR SYSTEM MEMORY B

SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6

SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14

AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2

AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5

AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33

M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14

1

M_B_RAS# 17 M_B_CAS# 17 M_B_WE# 17

M_B_DQS[7..0] 17

M_B_DQS#[7..0] 17

M_B_A[14..0] 17

M_B_BS#0 17 M_B_BS#1 17 M_B_BS#2 17

M_B_DM[7..0] 17

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

JV71-MV DDR3 Madison

Date: Sheet of

5

4

3

2

Date: Sheet of

JV71-MV DDR3 Madison

Taipei Hsien 221, Taiwan, R.O.C.

Cantiga (3 of 6)

8 62Wednesday, October 28, 2009

1

-1

5

4

3

2

1

7 OF 10

VCC GFX NCTF

7 OF 10

VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF

VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF

VCC SM LF

W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16

AV44 BA37 AM40 AV21 AY5 AM10 BB13

SM_LF1_GMCH SM_LF2_GMCH SM_LF3_GMCH SM_LF4_GMCH SM_LF5_GMCH SM_LF6_GMCH SM_LF7_GMCH

1 2

0R5J-6-GP

VCC_GFXCO RE

12

1D5V_S3

D D

VCC_GFXCO RE

C C

B B

VCC_AXG_SEN SE45 VSS_AXG_SENSE45

VCC_AXG_SEN SE VSS_AXG_SENSE

U60(ISL6263ACRZ-T-GP) place near Cantiga

NB1G

AP33

VCC_SM

AN33

VCC_SM

BH32

VCC_SM

BG32

VCC_SM

BF32

VCC_SM

BD32

VCC_SM

BC32

VCC_SM

BB32

VCC_SM

BA32

VCC_SM

AY32

VCC_SM

AW32

VCC_SM

AV32

VCC_SM

AU32

VCC_SM

AT32

VCC_SM

AR32

VCC_SM

AP32

VCC_SM

AN32

VCC_SM

BH31

VCC_SM

BG31

VCC_SM

BF31

VCC_SM

BG30

VCC_SM

BH29

VCC_SM

BG29

VCC_SM

BF29

VCC_SM

BD29

VCC_SM

BC29

VCC_SM

BB29

VCC_SM

BA29

VCC_SM

AY29

VCC_SM

AW29

VCC_SM

AV29

VCC_SM

AU29

VCC_SM

AT29

VCC_SM

AR29

VCC_SM

AP29

VCC_SM

BA36

VCC_SM/NC

BB24

VCC_SM/NC

BD16

VCC_SM/NC

BB21

VCC_SM/NC

AW16

VCC_SM/NC

AW13

VCC_SM/NC

AT13

VCC_SM/NC

Y26

VCC_AXG

AE25

VCC_AXG

AB25

VCC_AXG

AA25

VCC_AXG

AE24

VCC_AXG

AC24

VCC_AXG

AA24

VCC_AXG

Y24

VCC_AXG

AE23

VCC_AXG

AC23

VCC_AXG

AB23

VCC_AXG

AA23

VCC_AXG

AJ21

VCC_AXG

AG21

VCC_AXG

AE21

VCC_AXG

AC21

VCC_AXG

AA21

VCC_AXG

Y21

VCC_AXG

AH20

VCC_AXG

AF20

VCC_AXG

AE20

VCC_AXG

AC20

VCC_AXG

AB20

VCC_AXG

AA20

VCC_AXG

T17

VCC_AXG

T16

VCC_AXG

AM15

VCC_AXG

AL15

VCC_AXG

AE15

VCC_AXG

AJ15

VCC_AXG

AH15

VCC_AXG

AG15

VCC_AXG

AF15

VCC_AXG

AB15

VCC_AXG

AA15

VCC_AXG

Y15

VCC_AXG

V15

VCC_AXG

U15

VCC_AXG

AN14

VCC_AXG

AM14

VCC_AXG

U14

VCC_AXG

T14

VCC_AXG

AJ14

VCC_AXG_SENSE

AH14

VSS_AXG_SENSE

CANTIGA-GM- GP-U-NF

71.CNTIG.00U

POWER

VCC SMVCC GFX

place near Cantiga

VCC_GFXCO RE

R438

DIS

0R5J-6-GP

0R5J-6-GP R439

R439

DIS

SC4D7U6D3V3KX-GP

12

TC18

ST220U2D5VBM-2GP

DY

UMA

12

C292

C277

DY

SC4D7U6D3V3KX-GP

12

SC4D7U6D3V3KX-GP

UMA

SC4D7U6D3V3KX-GP

12

C282

C302

UMA

SC4D7U6D3V3KX-GP

12

C273

C276

UMA

DY

Place on the Edge Coupling CAP

SCD1U10V2KX-4GP

C361

C367

12

DY

SCD47U16V3ZY-3GP

12

C347

C290

C350

SCD1U10V2KX-4GP

SCD22U10V2KX-1GP

12

C329

SCD22U10V2KX-1GP

C320

C298

C340

SC1U10V3KX-3GP

SC4D7U6D3V3KX-GP

12

C285

UMA

FOR VCC SM

SCD1U10V2KX-4GP

C359

12

80.3371V.12L

SC4D7U6D3V3KX-GP

12

C275

DY

12

TC22

DY

Place on the Edge

ST330U2D5VBM-GP

UMA

1D05V_S0

12

1

C271

C286

2

UMA

SCD47U6D3V2KX-GP

SC4D7U6D3V3KX-GP

12

C349

C323

12

C279

C278

SCD1U10V2KX-4GP

SC1U10V3ZY-6GP

12

C308

SCD1U10V2KX-4GP

DY

UMA

1D5V_S3

SC4D7U6D3V3KX-GP

12

C348

FOR VCC CORE

SC4D7U6D3V3KX-GP

12

C291

C287

Coupling CAP 370 mils from the Edge

SC4D7U6D3V3KX-GP

12

C249

C274

DY

12

C612

SC10U6D3V5MX-3GP

Coupling CAP

12

C284

C281

SCD22U10V2KX-1GP

12

C284

C280

SCD1U10V2KX-4GP

DY

C289

SCD1U10V2KX-4GP

NB1F

AG34

VCC

AC34

VCC

AB34

VCC

AA34

VCC

Y34

VCC

V34

VCC

U34

VCC

AM33

VCC

AK33

VCC

AJ33

VCC

AG33

VCC

AF33

VCC

AE33

VCC

AC33

VCC

AA33

VCC

Y33

VCC

W33

VCC

V33

VCC

U33

VCC

AH28

VCC

AF28

VCC

AC28

VCC

AA28

VCC

AJ26

VCC

AG26

VCC

AE26

VCC

AC26

VCC

AH25

VCC

AG25

VCC

AF25

VCC

AG24

VCC

AJ23

VCC

AH23

VCC

AF23

VCC

T32

VCC

CANTIGA-GM- GP-U-NF

71.CNTIG.00U

VCC CORE

6 OF 10

1D05V_S0

AM32

VCC_NCTF

AL32

VCC_NCTF

AK32

VCC_NCTF

AJ32

VCC_NCTF

POWER

VCC NCTF

VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF

AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23

A A

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O.C .

Taipei Hsie n 221, Taiwan, R.O.C .

Title

Size Document Num ber Rev

JV71-MV DDR3 Madison

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C .

Cantiga (4 of 6)

9 62Wednesd ay, October 28, 2009

1

9 62Wednesd ay, October 28, 2009

-1

5

5V_S0

SC1U16V3ZY-GP

12

D D

1D05V_S0

12

C C

2nd = 68.00248.061

FCM1608KF-1-GP

120ohm 100MHz

2nd = 68.00248.061

1D05V_S0

B B

2nd = 68.00119.111

1D5V_S0

A A

2nd = 68.00214.101

Imax = 300 mA

UMA

U13

1

VIN

2

GND EN3NC#4

G9091-330T11U-GP

BC2

74.09091.J3F

UMA

2nd = 74.09198.Q7F

65mA

R371

12

0R0603-PAD

65mA

R399

12

0R0603-PAD

R430

R430 0R0603-PAD

0R0603-PAD

1D05V_SUS_MCH_PLL2

FCM1608KF-1-GP

1 2

L22

68.00217.161

1 2

L21

68.00217.161

L20

1 2

FCM1608CF-221T02-GP

68.00217.521

220ohm 100MHz

R156

1 2

0R0603-PAD

L6

UMA

1 2

PBY160808T-181Y-GP

68.00206.041

VOUT

SC10U6D3V5MX-3GP

12

C642

DY

3D3V_S0_DAC

5 4

BC1

SC1U16V3ZY-GP

DY

M_VCCA_DPLLA

SCD1U10V2KX-4GP

12

C622

C624

UMA

DY

M_VCCA_DPLLB

SCD1U10V2KX-4GP

12

C644

UMA

M_VCCA_HPLL

SC4D7U6D3V3KX-GP

12

C687

M_VCCA_MPLL

SC10U6D3V5MX-3GP

12

C694

1D05V_RUN_PEGPLL

12

C691

C691 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

1D5VRUN_TVDAC

12

C243

SCD01U16V2KX-3GP

DY

1D5VRUN_QDAC

12

C247

SCD01U16V2KX-3GP

12

C141

SC22U6D3V5MX-2GP

UMA

12

R390

R390 0R2J-2-GP

0R2J-2-GP

DY

12

R400

R400 0R2J-2-GP

0R2J-2-GP

DY

24mA

C692

C692 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

139.2mA

12

C697

C697 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

58.7mA

12

C174

SCD1U10V2KX-4GP

12

C188

SCD1U10V2KX-4GP

1D05V_S0

R159

0R2J-2-GP

3D3V_S0_DAC

R447

R447 0R0603-PAD

0R0603-PAD

480mA

1D05V_S0

3D3V_S0_DAC

R374

1 2

0R0603-PAD

12

C755

R202

R202 0R0603-PAD

0R0603-PAD

24mA

1D5V_S0

R375

1 2

0R0603-PAD

UMA

1D05V_SUS_MCH_PLL2

C715

60.3mA

C625

UMA

1D5V_S0

12

180ohm 100MHz

UMA

5

DIS

R378

R378 0R0603-PAD

0R0603-PAD

12

SCD01U16V2KX-3GP

SC4D7U6D3V3KX-GP

12

C753

DY

12

C294

DY

12

C205

SCD1U10V2KX-4GP

1D8V_NB_S0

4

73mA

12

C206

12

UMA

5mA

C207

12

UMA

SCD1U10V2KX-4GP

1D8V_TXLVDS_S0

C636

R421

1 2

0R0603-PAD

SC4D7U6D3V3KX-GP

12

C754

SC4D7U6D3V3KX-GP

12

C295

DY

3D3V_S0_DAC

DY

R153

R153 0R0603-PAD

0R0603-PAD

4

C636

SC4D7U6D3V3KX-GP

12

R383

0R2J-2-GP

SC27P50V2JN-2-GP

1 2

SCD01U16V2KX-3GP

SCD1U10V2KX-4GP

C617

12

UMA

12

R168

R168 0R2J-2-GP

0R2J-2-GP

DY

12

13.2mA

VCCA_PEG_BG

12

C704

C704 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

C306

SC4D7U6D3V3KX-GP

12

C752

DY

SC2D2U6D3V3MX-1-GP

12

C313

C293

R377

1 2

0R0603-PAD

0R0603-PAD R386

R386

0R2J-2-GP

DY

C690

50mA

1D8V_SUS_DLVDS

C235

SCD1U10V2KX-4GP

UMA

12

3D3V_CRTDAC_S0

12

R379

R379 0R2J-2-GP

0R2J-2-GP

DY

M_VCCA_DAC_BG

M_VCCA_DPLLA M_VCCA_DPLLB M_VCCA_HPLL M_VCCA_MPLL

1D05V_RUN_PEGPLL

C309

SC1U10V3KX-3GP

C309

SC1U10V3KX-3GP

SC4D7U6D3V3KX-GP

12

1D05V_SM_CK

SCD1U10V2KX-4GP

3D3V_S0_DAC_1

12

VCC_HDA

1D5VRUN_TVDAC 1D5VRUN_QDAC

1D05V_RUN_PEGPLL

12

SCD1U10V2KX-4GP

12

C175

UMA

SC4D7U6D3V3KX-GP

50mA

1D05V_SM

C305

SC1U10V3KX-3GP

C305

SC1U10V3KX-3GP

12

C186

SC4D7U6D3V3KX-GP

12

DY

SB 1202

R167

R167 0R2J-2-GP

0R2J-2-GP

NB1H

B27

VCCA_CRT_DAC

A26

VCCA_CRT_DAC

A25

VCCA_DAC_BG

B25

VSSA_DAC_BG

F47

VCCA_DPLLA

L48

VCCA_DPLLB

AD1

VCCA_HPLL

AE1

VCCA_MPLL

J48

VCCA_LVDS

J47

VSSA_LVDS

AD48

VCCA_PEG_BG

AA48

VCCA_PEG_PLL

AR20

VCCA_SM

AP20

VCCA_SM

AN20

VCCA_SM

AR17

VCCA_SM

AP17

VCCA_SM

AN17

VCCA_SM

AT16

VCCA_SM

AR16

VCCA_SM

AP16

VCCA_SM

AP28

VCCA_SM_CK

AN28

VCCA_SM_CK

AP25

VCCA_SM_CK

AN25

VCCA_SM_CK

AN24

VCCA_SM_CK

AM28

VCCA_SM_CK_NCTF

AM26

VCCA_SM_CK_NCTF

AM25

VCCA_SM_CK_NCTF

AL25

VCCA_SM_CK_NCTF

AM24

VCCA_SM_CK_NCTF

AL24

VCCA_SM_CK_NCTF

AM23

VCCA_SM_CK_NCTF

AL23

VCCA_SM_CK_NCTF

B24

VCCA_TV_DAC

A24

VCCA_TV_DAC

A32

VCC_HDA

M25

VCCD_TVDAC

L28

VCCD_QDAC

AF1

VCCD_HPLL

AA47

VCCD_PEG_PLL

M38

VCCD_LVDS

L37

VCCD_LVDS

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

3

8 OF 10

U13

VTT

T13

VTT

U12

VTT

T12

VTT

U11

VTT

T11

VTT

U10

VTT

T10

VTT

U9

CRTPLLA PEGA SM

A LVDS

VTT

T9

VTT

U8

VTT

T8

VTT

U7

VTT

T7

VTT

U6

VTT

T6

VTT

U5

VTT

T5

VTT

V3

VTT

U3

VTT

V2

VTT

U2

VTT

T2

VTT

V1

VTT

U1

VTT

322mA

POWER

B22

VCC_AXF

B21

VCC_AXF

A21

VCC_AXF

AXF

VCC_HV VCC_HV VCC_HV

VCC_PEG VCC_PEG VCC_PEG VCC_PEG VCC_PEG

VCC_DMI VCC_DMI VCC_DMI VCC_DMI

VTTLF VTTLF VTTLF

BF21 BH20 BG20 BF20

K47 C35

B35 A35

V48 U48 V47 U47 U46

AH48 AF48 AH47 AG47

A8 L1 AB2

106mA

VTTLF1 VTTLF2 VTTLF3

VCC_SM_CK

A CK

TV

HDA

D TV/CRT

LVDS

3

VCC_SM_CK VCC_SM_CK VCC_SM_CK

SM CK

VCC_TX_LVDS

HV

PEG

DMI

VTTLF

12

C250

SC1U10V3KX-3GP

12

C616

1D8V_TXLVDS_S0

3D3V_HV_S0

1

C676

2

SCD47U6D3V2KX-GP

2

12

SC4D7U6D3V3KX-GP

12

C251

DY

12

C283

1

2

12

C267

SC4D7U6D3V3KX-GP

1D05V_S0

SC4D7U6D3V3KX-GP

12

C272

DY

200mA

C750

12

1782mA

SC4D7U6D3V3KX-GP

456mA157.2mA

1

C620

C650

2

SCD47U6D3V2KX-GP

1

1D05V_S0

852mA

12

C670

C662

SC2D2U6D3V3MX-1-GP

SC4D7U6D3V3KX-GP

1D05V_S0

1

2

BAT54-5-GP

83.BAT54.D81

2nd = 83.BAT54.X81

SC4D7U6D3V3KX-GP

1D5V_SUS_SM_CK

SCD1U10V2KX-4GP

SC4D7U6D3V3KX-GP

12

C751

C635

SC1KP50V2KX-1GP

C635

SC1KP50V2KX-1GP

12

SC10U6D3V5MX-3GP

12

C739

DY

SCD1U10V2KX-4GP

12

C712

SCD47U6D3V2KX-GP

Title

Size Document Number Rev

Date: Sheet of

1

C268

2

D5

12

C758

DY

UMA

1D05V_S0

DY

12

C263

SCD1U10V2KX-4GP

SCD47U6D3V2KX-GP

3D3V_S0 3D3V_HV_S0

1D05V_HV_S0

3

U66

VIN

VOUT

GND

G1117-18T63UF-GP

74.G1117.B3C

UMA

R448

12

0R0603-PAD

SC4D7U6D3V3KX-GP

119mA

C634

SC1U10V3KX-3GP

C634

SC1U10V3KX-3GP

12

SC10U6D3V5MX-3GP

12

C675

12

C732

DY

12

SC10U6D3V5MX-3GP

JV71-MV DDR3 Madison

R106

10R2J-2-GP

I=1A

3 2 1

UMA

1D5V_S3

R396

R396 0R0603-PAD

0R0603-PAD

12

R398

0R2J-2-GP

UMA

DY

SCD1U10V2KX-4GP

C678

1D05V_S0

SC10U6D3V5MX-3GP

12

C722

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Cantiga (5 of 6)

12

C876

SC1U10V2ZY-GP

1 2

1

R376

1 2

0R0603-PAD

UMA

1D8V_NB_S0

12

C621

SCD1U10V2KX-4GP

3D3V_S0 1D8V_NB_S0

C877

SC1U10V2ZY-GP

1 2

-1

10 62Wednesday, October 28, 2009

-1

5

NB1I

AU48

VSS

AR48

VSS

AL48

VSS

BB47

VSS

AW47

VSS

AN47

VSS

AJ47

VSS

AF47

VSS

AD47

VSS

AB47

VSS

D D

C C

B B

A A

5

Y47

VSS

T47

VSS

N47

VSS

L47

VSS

G47

VSS

BD46

VSS

BA46

VSS

AY46

VSS

AV46

VSS

AR46

VSS

AM46

VSS

V46

VSS

R46

VSS

P46

VSS

H46

VSS

F46

VSS

BF44

VSS

AH44

VSS

AD44

VSS

AA44

VSS

Y44

VSS

U44

VSS

T44

VSS

M44

VSS

F44

VSS

BC43

VSS

AV43

VSS

AU43

VSS

AM43

VSS

J43

VSS

C43

VSS

BG42

VSS

AY42

VSS

AT42

VSS

AN42

VSS

AJ42

VSS

AE42

VSS

N42

VSS

L42

VSS

BD41

VSS

AU41

VSS

AM41

VSS

AH41

VSS

AD41

VSS

AA41

VSS

Y41

VSS

U41

VSS

T41

VSS

M41

VSS

G41

VSS

B41

VSS

BG40

VSS

BB40

VSS

AV40

VSS

AN40

VSS

H40

VSS

E40

VSS

AT39

VSS

AM39

VSS

AJ39

VSS

AE39

VSS

N39

VSS

L39

VSS

B39

VSS

BH38

VSS

BC38

VSS

BA38

VSS

AU38

VSS

AH38

VSS

AD38

VSS

AA38

VSS

Y38

VSS

U38

VSS

T38

VSS

J38

VSS

F38

VSS

C38

VSS

BF37

VSS

BB37

VSS

AW37

VSS

AT37

VSS

AN37

VSS

AJ37

VSS

H37

VSS

C37

VSS

BG36

VSS

BD36

VSS

AK15

VSS

AU36

VSS

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

VSS

9 OF 10

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

4

AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23 AJ6

4

3

10 OF 10

NB1J

BG21

VSS

L12

VSS

AW21

VSS

AU21

VSS

AP21

VSS

AN21

VSS

AH21

VSS

AF21

VSS

AB21

VSS

R21

VSS

M21

VSS

J21

VSS

G21

VSS

BC20

VSS

BA20

VSS

AW20

VSS

AT20

VSS

AJ20

VSS

AG20

VSS

Y20

VSS

N20

VSS

K20

VSS

F20

VSS

C20

VSS

A20

VSS

BG19

VSS

A18

VSS

BG17

VSS

BC17

VSS

AW17

VSS

AT17

VSS

R17 M17 H17

C17 BA16 AU16

AN16

N16

K16

G16

E16

BG15

AC15

W15

A15

BG14

AA14

C14

BG13

BC13 BA13

AN13

AJ13

AE13

N13

L13 G13 E13

BF12 AV12 AT12

AM12

AA12

J12 A12

BD11 BB11 AY11 AN11 AH11

Y11 N11 G11 C11

BG10

AV10 AT10

AJ10 AE10 AA10

M10 BF9 BC9 AN9

AM9

AD9

G9

B9 BH8 BB8 AV8 AT8

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

3

VSS VSS VSS VSS

VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

NCTF_VSS_SCB#BH48

NCTF TEST PIN:

A3,C1,A48,BH1,BH48

NCTF TEST PIN:

A3,C1,A48,BH1,BH48

VSS SCB

10 OF 10

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS

VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF

VSS NCTF

VSS_NCTF VSS_NCTF

NCTF_VSS_SCB#BH1 NCTF_VSS_SCB#A48

NCTF_VSS_SCB#C1

NCTF_VSS_SCB#A3

NC#E1 NC#D2 NC#C3 NC#B4 NC#A5

NC#A6 NC#A43 NC#A44 NC#B45 NC#C46

NC

NC#D47 NC#B47 NC#A46 NC#F48 NC#E48 NC#C48 NC#B48

2

AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4

BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1

U24 U28 U25 U29

AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17

NCTF_VSS_SCB#BH48

BH48

NCTF_VSS_SCB#BH1

BH1

NCTF_VSS_SCB#A48

A48

NCTF_VSS_SCB#C1

C1

NCTF_VSS_SCB#A3

A3 E1

D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48

2

1

TP201 TPAD14-GPTP201 TPAD14-GP

1

TP202 TPAD14-GPTP202 TPAD14-GP

1

TP188 TPAD14-GPTP188 TPAD14-GP

1

TP190 TPAD14-GPTP190 TPAD14-GP

1

TP187 TPAD14-GPTP187 TPAD14-GP

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

JV71-MV DDR3 Madison

Date: Sheet of

JV71-MV DDR3 Madison

Taipei Hsien 221, Taiwan, R.O.C.

Cantiga (6 of 6)

11 62Wednesday, October 28, 2009

1

-1

5

4

C386

1 2

SC7P50V2DN-2GP

RTC_X1

3

2

1

4

1

TP204TPAD14-GP TP204TPAD14-GP

1 2

R213

SATA_RXN021

SATA_RXP021 SATA_TXN021 SATA_TXP021

SATA_RXN122

SATA_RXP122 SATA_TXN122 SATA_TXP122

12

R215

R215 10MR2J-L-GP

10MR2J-L-GP

RTC_X2 RTC_RST#

SRTC_RST# INTRUDER#

INTVRMEN LAN100_SLP

TP_LAN_RSTSYNC

1

HDMI_EN

GLAN_COMP

24D9R2F-L-GP

ACZ_BIT_CLK ACZ_SYNC_R

ACZ_RST#_R ACZ_SDATAIN0

ACZ_SDATAIN1 ACZ_SDIN3 ACZ_SDATAOUT_R

HDA_DOCK_RST#

1

ACZ_BTCLK_MDC30 ACZ_SYNC_MDC30 ACZ_RST#_MDC30 ACZ_SDATAOUT_MDC30

ACZ_BITCLK_AUDIO27 ACZ_SYNC_AUDIO27 ACZ_RST#_AUDIO27 ACZ_SDATAOUT_AUDIO27

X4

3D3V_AUX_S5

D D

RTC1

RTC_BAT

R414

10KR2J-3-GP

RTC_AUX_S5

12

LAN100_SLP

1 2

R228 1KR2J-1-GPR228 1KR2J-1-GP

MEDIA_LED#

R229

R229 330KR2F-L-GP

330KR2F-L-GP

INTVRMEN

1

PWR

2

GND

NP1

NP2

BAT-CON2-1-GP-U

62.70001.011

2nd =

C C

3D3V_S5

12

R218

R218 10KR2J-3-GP

10KR2J-3-GP

B B

A A

12

R217

R217 10KR2J-3-GP

10KR2J-3-GP

DY

3D3V_S0

RTC_AUX_S5

12

R265

HDMI_EN

1 2

330KR2F-L-GP

D12

2

1

BAS40CW -GP

2nd = 83.00040.M81

83.00040.E81

RTC_BAT_R

modify by RF

SC47P50V2JN-3GP

D12

21

G17

GAP-OPEN

1D5V_S0

C381

3

RN39

RN39 SRN20KJ-GP-U

SRN20KJ-GP-U

2 3 1

1 2

R230

R230 1MR2J-1-GP

1MR2J-1-GP

12

DY

RTC_AUX_S5

SC1U16V3ZY-GP

12

4

C402

12

C397

SC1U16V3ZY-GP

close to SB1

ACZ_BIT_CLK7 ACZ_SYNC_R7

ACZ_RST#_R7 ACZ_SDATAIN027

ACZ_SDATAIN130 ACZ_SDIN37 ACZ_SDATAOUT_R7

EC22 SC12P50V2JN-3GP

EC22 SC12P50V2JN-3GP EC45 SC22P50V3JN-GP

EC45 SC22P50V3JN-GP

integrated VccSus1_05,VccSus1_5,VccCL1_5

INTVRMEN

High=Enable Low=Disable

X-32D768KHZ-34GPU

12

C396

MEDIA_LED#37

1 2

DY

1 2

DY

X4

C385

1 2

SC7P50V2DN-2GP

SC1U16V3ZY-GP

GLAN_COMP place within 500 mil of ICH9M

HDD ODD

ACZ_BTCLK_MDC ACZ_BITCLK_AUDIO

2 3

TP197TPAD14-GP TP197TPAD14-GP

integrated VccLan1_05VccCL1_05

LAN100_SLP

5

High=Enable Low=Disable

4

82.30001.661

2nd = 82.30001.B21

SB1A

C23

RTCX1

C24

RTCX2

A25

RTCRST#

F20

SRTCRST#

C22

INTRUDER#

B22

INTVRMEN

A22

LAN100_SLP

E25

GLAN_CLK

C13

LAN_RSTSYNC

F14

LAN_RXD0

G13

LAN_RXD1

D14

LAN_RXD2

D13

LAN_TXD0

D12

LAN_TXD1

E13

LAN_TXD2

B10

GLAN_DOCK#/GPIO56

B28

GLAN_COMPI

B27

GLAN_COMPO

AF6

HDA_BIT_CLK

AH4

HDA_SYNC

AE7

HDA_RST#

AF4

HDA_SDIN0

AG4

HDA_SDIN1

AH3

HDA_SDIN2

AE5

HDA_SDIN3

AG5

HDA_SDOUT

AG7

HDA_DOCK_EN#/GPIO33

AE8

HDA_DOCK_RST#/GPIO34

AG8

SATALED#

AJ16

SATA0RXN

AH16

SATA0RXP

AF17

SATA0TXN

AG17

SATA0TXP

AH13

SATA1RXN

AJ13

SATA1RXP

AG14

SATA1TXN

AF14

SATA1TXP

ICH9M-GP-NF

71.ICH9M.00U

RN37

1 2 3 4 5

SRN33J-4-GP

SRN33J-4-GP RN68

RN68

1 2 3 4 5

SRN33J-4-GP

3

RTCLAN / GLAN

LPCCPU

RTCLAN / GLAN

LPCCPU

IHDA

SATA

ACZ_BIT_CLK

8

ACZ_SYNC_R

7

ACZ_RST#_R

6

ACZ_SDATAOUT_R

ACZ_BIT_CLK

8

ACZ_SYNC_R

7

ACZ_RST#_R

6

ACZ_SDATAOUT_R

1 OF 6

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

FWH4/LFRAME#

LDRQ0#

LDRQ1#/GPIO23

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

CPUPWRGD

IGNNE#

INIT#

INTR

RCIN#

NMI

SMI#

STPCLK#

THRMTRIP#

PECI

SATA4RXN SATA4RXP SATA4TXN

SATA4TXP

SATA5RXN SATA5RXP SATA5TXN

SATA5TXP

SATA_CLKN SATA_CLKP

SATARBIAS#

SATARBIAS

K5 K4 L6 K2

K3

LDRQ0#

J3

3D3V_LDRQ1_S0

J1 N7

AJ27

H_DPRSTP#

AJ25 AE23

H_FERR#_R

AJ26

H_PWRGD

AD22 AF25 AE22

AG25 L3

AF23 AF24

AH27 AG26

ICH_TP8

AG27

AH11 AJ11 AG12 AF12

AH9 AJ9 AE10 AF10

AH18 AJ18

SATARBIAS

AJ7 AH7

24D9R2F-L-GP

Place within 500 mils of ICH9 ball

LPC_LAD0 34,35 LPC_LAD1 34,35 LPC_LAD2 34,35 LPC_LAD3 34,35

LPC_LFRAME# 34,35

TP200 TPAD14-GPTP200 TPAD14-GP

1

TP144 TPAD14-GPTP144 TPAD14-GP

1

KA20GATE 34 H_A20M# 4

H_DPRSTP# 4,7,40 H_DPSLP# 4

H_PWRGD 4,50 H_IGNNE# 4 H_INIT# 4

H_INTR 4 KBRCIN# 34

H_NMI 4 H_SMI# 4

H_STPCLK# 4

H_THERMTRIP_R

TP195 TPAD14-GPTP195 TPAD14-GP

1

DY

modify by RF

CLK_PCIE_SATA# 3

CLK_PCIE_SATA 3

12

R194

H_INIT# FWH_INIT#

2

1D05V_S0

RN71

1 2 3

SRN56J-4-GP

1D05V_S0 1D05V_S0

12

R413

R413 56R2J-4-GP

56R2J-4-GP

H_DPRSTP# H_PWRGD

4

H_FERR# 4

12

DY

C683

DY

12

R424

R424 56R2J-4-GP

56R2J-4-GP

12

SC47P50V2JN-3GP

modify by RF

R411

1 2

56R2J-4-GP

1 2

R410 54D9R2F-L1-GP

DY

12

C673

SC47P50V2JN-3GP

1D05V_S0 3D3V_S0

1

23

DY

RN70

RN70 SRN10KJ-5-GP

SRN10KJ-5-GP

4

H_INIT#_G

B

DY

C

E

Q14

Q14 MMBT3904-4-GP

MMBT3904-4-GP

84.T3904.C11

JV71-MV DDR3 Madison

Title

Size Document Number Rev

Date: Sheet of

1

ICH9-M (1 of 4)

JV71-MV DDR3 Madison

1D05V_S0

PM_THRMTRIP-A# 4,7,38

Layout note: R373 needs to placed within 2" of ICH9, R379 must be placed within 2" of R373 w/o stub

TP116 TPAD14-GPTP116 TPAD14-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

12 62Wednesday, October 28, 2009

1

DY

C706

DY

SC47P50V2JN-3GP

-1

5

2 OF 6

PCI

12 12

USB_OC#0 USB_OC#1

USB_OC#3 USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7 USB_OC#8 USB_OC#9 USB_OC#10 USB_OC#11

REQ0#

GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55

C/BE0# C/BE1# C/BE2# C/BE3#

IRDY#

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#

STOP#

TRDY#

FRAME#

PLTRST#

PCICLK

PME#

PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4

N29

N28

TXN1

P27

TXP1

P26 L29

L28

TXN2

M27

TXP2

M26

J29 J28 K27 K26

G29

G28

H27

H26

E29 E28 F27 F26

C29

C28

D27

D26

D23

D24

F23

D25

E23

N4 N5 N6

M1 N2 M4 M3 N3 N1

AG2

AG1

2 OF 6

PCI_REQ#0

F1 G4

PCI_REQ#1

B6 A7

PCI_REQ#2

F13 F12

PCI_REQ#3

E6 F6

D8 B4 D6 A5

PCI_IRDY#

D3 E3

PAR

R1

PCI_DEVSEL#

C6

PCI_PERR#

E4

PCI_LOCK#

C2

PCI_SERR#

J4

PCI_STOP#

A4

PCI_TRDY#

F5

PCI_FRAME#

D7

PLT_RST#_R

C14 D4 R2

H4 K6 F2 G2

SB1D

PERN1 PERP1 PETN1 PETP1

PERN2 PERP2 PETN2 PETP2

PERN3 PERP3 PETN3 PETP3

PERN4 PERP4 PETN4 PETP4

PERN5 PERP5 PETN5 PETP5

PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP

SPI_CLK SPI_CS0# SPI_CS1#/GPIO58/CLGPIO6

SPI_MOSI SPI_MISO

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41

P6

OC3#/GPIO42 OC4#/GPIO43 OC5#/GPIO29 OC6#/GPIO30 OC7#/GPIO31 OC8#/GPIO44 OC9#/GPIO45

P5

OC10#/GPIO46

P3

OC11#/GPIO47 USBRBIAS

USBRBIAS#

ICH9M-GP-NF

71.ICH9M.00U

INT_PIRQF# INT_PIRQG# INT_PIRQH#

USB

R216

1 2

0R0402-PAD

PCLK_ICH 3

DMI0RXN DMI0RXP DMI0TXN DMI0TXP

DMI1RXN DMI1RXP DMI1TXN DMI1TXP

DMI2RXN DMI2RXP DMI2TXN DMI2TXP

DMI3RXN DMI3RXP DMI3TXN DMI3TXP

DMI_CLKN

PCI-Express

DMI_CLKP

Direct Media Interface

DMI_ZCOMP

DMI_IRCOMP

USBP0N USBP1N USBP2N USBP3N USBP4N USBP5N

SPI

USBP6N USBP7N USBP8N USBP9N

USBP10N USBP10P USBP11N USBP11P

4 OF 6

USBP0P USBP1P USBP2P USBP3P USBP4P USBP5P USBP6P USBP7P USBP8P USBP9P

1 2

C388 SC100P50V2JN -3GP

DY

V27 V26 U29 U28

Y27 Y26 W29 W28

AB27 AB26 AA29 AA28

AD27 AD26 AC29 AC28

T26 T25

AF29 AF28

AC5 AC4 AD3 AD2 AC1 AC2 AA5 AA4 AB2 AB3 AA1 AA2 W5 W4 Y3 Y2 W1 W2 V2 V3 U5 U4 U1 U2

SB1B

D11

AD0

C8

AD1

D9

AD2

E12

AD3

E9

AD4

C9

AD5

E10

AD6

B7

AD7

C7

AD8

C5

PCI_GNT#0 and SPI_CS1# have weak internal Pull up

D D

INT_PIRQA# INT_PIRQE# INT_PIRQB# INT_PIRQC# INT_PIRQD#

C C

B B

PCIE_RXN125

PCIE_RXP125 PCIE_TXN125 PCIE_TXP125

LAN

PCIE_RXN232

PCIE_RXP232 PCIE_TXN232 PCIE_TXP232

MINICARD1

These R need close SB within 600 mils

C363 SCD1U10V 2KX-5GPC363 SC D1U10V2KX-5GP C360 SCD1U10V 2KX-5GPC360 SC D1U10V2KX-5GP

C369 SCD1U10V 2KX-5GPC369 SC D1U10V2KX-5GP C365 SCD1U10V 2KX-5GPC365 SC D1U10V2KX-5GP

USB_OC#024 USB_OC#124

USB_OC#924

AD9

G11

AD10

F8

AD11

F11

AD12

E7

AD13

A3

AD14

D2

AD15

F10

AD16

D5

AD17

D10

AD18

B3

AD19

F7

AD20

C3

AD21

F3

AD22

F4

AD23

C1

AD24

G7

AD25

H7

AD26

D1

AD27

G5

AD28

H6

AD29

G1

AD30

H3

AD31

Interrupt I/F

J5

PIRQA#

E1

PIRQB#

J6

PIRQC# PIRQD#C4PIRQH#/GPIO5

ICH9M-GP-NF

71.ICH9M.00U

12

R415 22D6R2F -L1-GPR415 22D6R2F -L1-GP

SPI_ICH_CS1#

USB_RBIAS_PN

4

PLT_RST1# 7,2 5,31,32,34,35,52

GPIO49 should be pulled down to GND only when using Teenah. When using Cantiga, this ball should be left as No Connect.

DMI_RXN0 7 DMI_RXP0 7 DMI_TXN0 7 DMI_TXP0 7

DMI_RXN1 7 DMI_RXP1 7 DMI_TXN1 7 DMI_TXP1 7

DMI_RXN2 7 DMI_RXP2 7 DMI_TXN2 7 DMI_TXP2 7

DMI_RXN3 7 DMI_RXP3 7 DMI_TXN3 7 DMI_TXP3 7

CLK_PCIE_ICH# 3 CLK_PCIE_ICH 3

DMI_IRCOMP_R

USBPN0 24 USBPP0 24 USBPN1 24 USBPP1 24 USBPN2 24 USBPP2 24 USBPN3 32 USBPP3 32

USBPN4 18 USBPP4 18

USBPN6 36 USBPP6 36 USBPN7 23 USBPP7 23

USBPN9 24 USBPP9 24

USBPN11 31 USBPP11 31

EMI capacitor

1D5V_S0

12

USB

Pair

0 1 2 3 4 5 6 7 8 9 USB1 10 11

SMB_CLK15,25,32 SMB_DATA15,25,32

VGATE_PW RGD33,40

3D3V_S0

10KR2J-3-GP

12

R404

GAP-OPEN

21

G78

SATACLKREQ #3

MCH_ICH_SYNC #7

1 2

EC81 SC12P50V2JN-3GP

DY

1 2

EC80 SC12P50V2JN-3GP

DY

R417

R417 24D9R2F-L-G P

24D9R2F-L-G P

Device USB2 USB3 USB4 MINI1 CCD NC Finger Print Blue Tooth NC

NC Cardreader

SMB_LINK_ALERT#

PM_RI# PM_SUS_STAT#

TP199TPAD14-GP TP199TPAD14-GP

1

PM_SYNC#7

PM_STPPCI#3 PM_STPCPU#3

PM_CLKRUN #34

PCIE_WAKE#25

INT_SERIRQ34

ACZ_SPKR27

VGATE_PW RGD

CLK_PWR GD

DBRESET#

SMB_ALERT#

THRM#33

ICH_TP7

1 2

DY

0R2J-2-GP

R221

FP_ID

TP193TPAD14-GP TP193TPAD14-GP

1

EC_TMR34

ECSCI#_134

ECSWI#34

PSW_CLR # ICH9_GPIO20

TP196TPAD14-GP TP196TPAD14-GP

1

CLK_SEL1

TP122TPAD14-GP TP122TPAD14-GP

1

SATACLKREQ # PCB_VER0_SB

1

PCB_VER1_SB

TP198TPAD14-GP TP198TPAD14-GP

1

MIC_SEL_1

TP194TPAD14-GP TP194TPAD14-GP

NO_iTPM

ICH_TP3

1

TP205TPAD14-GP TP205TPAD14-GP

No Reboot Strap

SPKR LOW = Defaule

High=No Reboot

DY

MIC_SEL_1 ACZ_SPKR

NO_iTPM PWROK

DY

1 2

R405 10KR2J-3-GP

1 2

R434 1KR2J-1-GP

DY

1 2 3

G16 A13 E17 C17 B18

F19

G19

A17 A14

E19

E20

AJ23

D21 A20

AG19 AH21 AG21

A21 C12 C21

AE18

AF8

AJ22

D19

AE19

AG22

AF21

AH24

AJ24

B21

AH20

AJ20 AJ21

RN38

SRN10KJ-5-G P

R4

M6

L4

M5

K1

A9 L1

A8 M7

3

SB1C

SMBCLK SMBDATA LINKALERT#/GPIO60/CLGPIO4 SMLINK0 SMLINK1

RI# SUS_STAT#/LPCPD#

SYS_RESET# PMSYNC#/GPIO0 SMBALERT#/GPIO11 STP_PCI#

STP_CPU# CLKRUN# WAKE#

SERIRQ THRM#

VRMPWRGD SST TACH1/GPIO1

TACH2/GPIO6 TACH3/GPIO7 GPIO8 LAN_PHY_PWR_CTRL/GPIO12 ENERGY_DETECT/GPIO13 TACH0/GPIO17 GPIO18 GPIO20 SCLOCK/GPIO22 GPIO27 GPIO28 SATACLKREQ#/GPIO35 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 GPIO49 GPIO57/CLGPIO5

SPKR MCH_SYNC# TP3 PWM0 PWM1 PWM2

ICH9M-GP-NF

71.ICH9M.00U

PM_RI# PM_BATLOW #_R ECSWI# PCIE_WAKE#

3D3V_S5

PCI_TRDY# INT_PIRQG# PCI_REQ#0 INT_PIRQH#

3D3V_S0

INT_PIRQD# PCI_LOCK#

PCI_FRAME#

3D3V_S0

INT_PIRQC# INT_PIRQF#

PM_CLKRUN #

3D3V_S0

BOOT BIOS Strap

0 1 SPI

3D3V_S0

A16 swap override strap

PCI_GNT#3

4

SATA0GP/GPIO21 SATA1GP/GPIO19 SATA4GP/GPIO36 SATA5GP/GPIO37

SATA

GPIO

SATA

GPIO

SMB

Clocks

S4_STATE#/GPIO26

DPRSLPVR/GPIO16

SYS GPIO

Power MGTController Link

GPIO

GPIO24/MEM_LED

GPIO10/SUS_PWR_ACK

GPIO14/AC_PRESENT

GPIO9/WOL_EN

MISC

RP1

1 2 3 4 5 6

SRN10KJ-L3-G P

RP3

SRN8K2J-2-G P-U

RP4

SRN8K2J-2-G P-U

RP2

SRN8K2J-2-G P-U

10

DBRESET#

9

SMB_LINK_ALERT#

8

SUSPWR ACK

7

SMB_ALERT#

10

INT_PIRQB#

9

PCI_PERR#

8

PCI_REQ#3

7

PCI_IRDY#

10

PCI_REQ#2

9

PCI_DEVSEL#

8

PCI_REQ#1

7

PCI_STOP#

10

PCI_SERR#

9

INT_PIRQA#INT_SERIRQ

8

INT_PIRQE#

7

ECSCI#_1

SPI_CS#1 BOOT BIOS LocationPCI_GNT#0

01

PCI

11

low = A16 swap override enable high = default

SPI_ICH_CS1#

LPC(Default)

DY

1 2

R225 1KR2J- 1-GP

3 OF 6

CLK14 CLK48

SUSCLK

SLP_S3# SLP_S4# SLP_S5#

PWROK

BATLOW# PWRBTN#

LAN_RST#

RSMRST#

CK_PWRGD

CLPWROK

SLP_M#

CL_CLK0 CL_CLK1

CL_DATA0 CL_DATA1

CL_VREF0 CL_VREF1

CL_RST0# CL_RST1#

3D3V_S5

3D3V_S0

AH23 AF19 AE21 AD20

H1 AF3

P1 C16

E16

PM_SLP_S5#

G17

S4_STATE#

C10 G20

PM_DPRSLPVR _1

M2

PM_BATLOW #_R

B13

PWRBTN #_ICH

R3 D20 D22 R5 R6

PM_SLP_M#

B16 F24

B19 F22

C19 C25

A19 F21

D18

ICH_GPIO24

A16

SUSPWR ACK

C18

AC_PRESENT

C11 C20

3D3V_S5

SATA0GP SATA1GP ICH_GPIO36 ICH_GPIO37

RSMRST#_SB

CL_VREF0_ICH

ICH_GPIO9

100KR2J-1-GP

12

R220

CLK_ICH14 3 CLK48_ICH 3

PM_SUS_CLK 33

PM_SLP_S3# 27,33,34,38,43,45,48,51

1

TP203 TPAD14-GPTP203 TPAD14-GP

1

TP207 TPAD14-GPTP207 TPAD14-GP

PWROK 7,33

CLK_PWR GD 3 PWROK 7,33

TP148 TPAD14-GPTP148 TPAD14-GP

1

CL_CLK0 7

CL_DATA0 7

CL_RST#0 7

TP153 TPAD14-GPTP153 TPAD14-GP

1

TP206 TPAD14-GPTP206 TPAD14-GP

1

3D3V_S5

RSMRST#_KBC34

2

RN72

6 7 8

SRN10KJ-6-G P

PM_SLP_S4# 34,38,42,44

R211 100R2J-2-G PR211 100R 2J-2-GP

12

R212

1 2

DY

100KR2J-1-GP

D8

BAS16-1-GP

1

3

83.00016.B112nd = 83.00016.F11

2

3K24R2F-GP

12

RN73

USB_OC#0

8

USB_OC#1

7

USB_OC#3

6

SRN10KJ-6-G P

RP5

USB_OC#4

1

USB_OC#9

2

USB_OC#5 USB_OC#6

3

USB_OC#8

4 5 6

R222

1 2

1KR2F-3-GP

3

BAT54-5-GP

83.BAT54.D81

2nd = 83.BAT54.X81

3D3V_AUX_S5

12

R699

R699 10KR2J-3-GP

10KR2J-3-GP

Q43_6

SRN10KJ-L3-G P

3D3V_S5

D11

1

DY

2

Q43

6

2N7002KDW -GP

10 9 8 7

45 3 2 1

PM_DPRSLPVR 7,40

PM_PWRBT N# 3 4,50

3D3V_S0

12

R226

12

R227

R227 453R2F-1-GP

453R2F-1-GP

C409

SCD1U10V2KX-4GP

3D3V_S5

1 2 3 45

USB_OC#7 USB_OC#10

USB_OC#11

12

R702

R702 10KR2J-3-GP

10KR2J-3-GP

AC_PRESENT RSMRST#_SB

12

R224

R224 100KR2J-1-GP

100KR2J-1-GP

RSMRST#_SB

2345 1

3D3V_S5

RSMRST#_SB

12

R700

R700 100KR2J-1-GP

100KR2J-1-GP

3D3V_S5

12

R701

R701 10KR2J-3-GP

10KR2J-3-GP

DY

3V/5V_PWRG D 41

1

SB 1007

A A

JV71-MV DDR 3 Madison

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O.C .

Taipei Hsie n 221, Taiwan, R.O.C .

Title

Size Document Num ber Rev

JV71-MV DDR3 Madison

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C .

ICH9-M (2 of 4)

1

-1

13 62Wednesd ay, October 28, 2009

-1

5

D D

2mA

C C

V5REF_S0

Layout Note: Place near ICH9

2mA

V5REF_S5

B B

12

C742

C737

SCD1U10V2KX-4GP

*Within a given well, 5VREF needs to be up before the corresponding 3.3V rail

C742

SCD1U10V2KX-4GP

DY

D10

D10 RB751V-40-2-GP

RB751V-40-2-GP

83.R2004.B8F

K A

2nd = 83.R0304.A8F

12

C387

SCD1U16V2ZY-2GP

D7

D7 RB751V-40-2-GP

RB751V-40-2-GP

83.R2004.B8F

K A

2nd = 83.R0304.A8F

12

C699

SCD1U16V2ZY-2GP

12

DY

5V_S0

5V_S53D3V_S5

12

R223

R223 100R2J-2-GP

100R2J-2-GP

12

R423

R423 100R2J-2-GP

100R2J-2-GP

12

C382

C252

SC4D7U6D3V3KX-GP

DY

RTC_AUX_S5

1D5V_S0

12

SC4D7U6D3V3KX-GP

1 2

2nd = 68.1R220.10B

C724

SCD1U10V2KX-4GP

L8

IND-1D2UH-10-GP

68.1R220.10D

1D5V_S0

12

C412

SCD1U10V2KX-4GP

47mA

1.64A

12

C681

SCD1U10V2KX-4GP

USBPLL=11mA

12

C700

C720

SCD1U10V2KX-4GP

3D3V_S0

19mA in S0;78mA in S3/S4/S5

12

C389

SCD1U10V2KX-4GP

A A

SC4D7U6D3V3KX-GP

5

1D5V_S0

80mA

C719

R219

1 2

0R0603-PAD

12

C718

SCD1U10V2KX-4GP

23mA

12

C394

12

C393

SC1U16V3ZY-GP

4

6uA in G3

12

C413

SCD1U10V2KX-4GP

DY

12

C733

C703

DY

C693

SC1U16V3ZY-GP

SC4D7U6D3V3KX-GP

SC2D2U10V3KX-1GP

SCD1U10V2KX-4GP

1D5V_APLL_S01D5V_S03D3V_S0

12

C241

C242

SC4D7U6D3V3KX-GP

12

C674

SC1U16V3ZY-GP

12

C705

SCD1U10V2KX-4GP

12

C682

SCD1U10V2KX-4GP

C390

12

C392

DY

SCD1U50V3KX-GP

4

V5REF_S0 V5REF_S5

646mA

12

C261

SC1U16V3ZY-GP

12

C689

SC4D7U6D3V3KX-GP

C383

DY

SCD1U50V3KX-GP

12

DY

VCCLAN_1D05V_INT_ICH

12

SCD1U10V2KX-4GP

1D5VGLANPLL_ICH

3D3V_S0

1mA

A23

AE1

AA24 AA25 AB24 AB25 AC24 AC25 AD24 AD25 AE25 AE26 AE27 AE28 AE29

G25 H24 H25

K24 K25

M24 M25 N23 N24 N25 P24 P25 R24 R25 R26 R27

U24 U25 V24 V25

U23 W24 W25

K23

Y24

Y25

AJ19

AC16 AD15 AD16 AE15 AF15 AG15 AH15

AJ15

AC11 AD11 AE11 AF11 AG10 AG11 AH10

AJ10

AC9

AC18 AC19

AC21

G10

AC12 AC13 AC14

AA7

AB6

AB7

AC6

AC7

A10

A11

A12

B12

A27

D28

D29

E26

E27

A26

A6

F25

J24 J25

L23 L24 L25

T24 T27 T28 T29

G9

AJ5

SB1F

VCCRTC V5REF V5REF_SUS VCC1_5_B

VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B

VCCSATAPLL VCC1_5_A

VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A

VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A

VCC1_5_A VCC1_5_A

VCC1_5_A VCC1_5_A VCC1_5_A

VCC1_5_A VCC1_5_A

VCCUSBPLL VCC1_5_A

VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A

VCCLAN1_05 VCCLAN1_05

VCCLAN3_3 VCCLAN3_3

VCCGLANPLL VCCGLAN1_5

VCCGLAN1_5 VCCGLAN1_5 VCCGLAN1_5

VCCGLAN3_3

ICH9M-GP-NF

71.ICH9M.00U

3

6 OF 6

A15

VCC1_05

B15

VCC1_05

C15

VCC1_05

D15

VCC1_05

E15

VCC1_05

F15

VCC1_05

L11

VCC1_05

L12

VCC1_05

L14

VCC1_05

L16

VCC1_05

L17

VCC1_05

L18

VCC1_05

M11

VCC1_05

M18

VCC1_05

P11

VCC1_05

P18

VCC1_05

T11

VCC1_05

T18

VCC1_05

U11

VCC1_05

U18

VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05

VCCDMI VCCDMI

V_CPU_IO V_CPU_IO

VCC3_3 VCC3_3 VCC3_3 VCC3_3

VCC3_3 VCC3_3 VCC3_3

VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3

VCCHDA

VCCCL1_5 VCCCL3_3

VCCCL3_3

V11 V12 V14 V16 V17 V18

R29 W23

Y23 AB23

AC23 AG29 AJ6 AC10 AD19

AF20 AG24 AC20

B9

C395

F9 G3 G6 J2 J7 K7

AJ4 AJ3 AC8

F17 AD8 F18

A18 D16 D17 E22

AF1 T1

T2 T3 T4 T5 T6 U6 U7 V6 V7 W6 W7 Y6 Y7 T7

G22 G23 A24

B24

SCD1U10V2KX-4GP

TP_VCCSUS1D05V_ICH_1

VCCSUS1D5V_INT_ICH

SCD1U10V2KX-4GP

CORE

VCCDMIPLL

VCCA3GP ATXARX USB CORE

VCCP_CORE

PCI

VCCSUSHDA

VCCSUS1_05 VCCSUS1_05

VCCSUS1_5 VCCSUS1_5

VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3

VCCPSUSVCCPUSB

VCCSUS3_3 VCCSUS3_3

VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3

VCCCL1_05

Place near ICH9MLayout Note:

1.16A

12

SCD1U10V2KX-4GP

C744

C736

C677

SCD1U10V2KX-4GP

1D5V_DMIPLL_ICH_S0

SCD01U16V2KX-3GP

1D05V_DMI_ICH_S0

SCD1U10V2KX-4GP

12

C731

12

C688

C688 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

VCC3_3=308mA

3D3V_S0

12

C743

12

C730

VCCCL1D05V_INT_ICH VCCCL1D5V_INT_ICH

C721

SCD1U10V2KX-4GP

12

C734

DY

12

C398

3D3V_S0

12

C735

DY

12

C723

12

C256

DY

3D3V_S0

C374

SCD1U10V2KX-4GP

VCCHDA_ICH VCCSUSHDA_ICH

C407

C407 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

212mA

SCD1U10V2KX-4GP

19mA

GLAN POWER

3

1D05V_S0

12

SCD1U10V2KX-4GP

12

SC4D7U6D3V3KX-GP

12

C728

DY

3D3V_S0

C698

12

C408

C408 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

3D3V_S5

12

C726

SCD1U10V2KX-4GP

3D3V_S5

12

C327

DY

SCD1U10V2KX-4GP

12

C404

DY

2

12

C745

C384

C713

C713 SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

12

SCD1U10V2KX-4GP

R433

R433 0R0603-PAD

0R0603-PAD

12

C729

SC4D7U6D3V3KX-GP

DY

32mA

12

C661

SCD1U10V2KX-4GP

32mA

12

C405

DY

2

1

12

C746

C391

SCD1U10V2KX-4GP

23mA

L9

1 2

IND-1D2UH-10-GP

68.1R220.10D

2nd = 68.1R220.10B

12

41mA

12

C707

C707 SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

DY

1D05V_S0

2mA

12

SCD1U10V2KX-4GP

12

DY

12

C717

C716

SCD1U10V2KX-4GP

C406

C717

C738

SCD1U10V2KX-4GP

SC4D7U6D3V3KX-GP

DY

12

C669

SCD1U10V2KX-4GP

Title

Size Document Number Rev

Date: Sheet of

SC4D7U6D3V3KX-GP

DIS

R403 0R2J-2-GP

1 2

R402 0R2J-2-GP

1 2

UMA

DIS

R408 0R2J-2-GP

1 2

R409 0R2J-2-GP

1 2

UMA

ICH9-M (3 of 4)

JV71-MV DDR3 Madison

3D3V_S0 1D5V_S0

3D3V_S5 1D5V_S0

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

1D5V_S0

14 62Wednesday, October 28, 2009

-1

A

SB1E

AA26

VSS

AA27

VSS

AA3

VSS

AA6

VSS

AB1

VSS

AA23

VSS

AB28

VSS

AB29

VSS

AB4

VSS

AB5

VSS

AC17

VSS

4 4

3 3

2 2

1 1

AC26

VSS

AC27

VSS

AC3

VSS

AD1

VSS

AD10

VSS

AD12

VSS

AD13

VSS

AD14

VSS

AD17

VSS

AD18

VSS

AD21

VSS

AD28

VSS

AD29

VSS

AD4

VSS

AD5

VSS

AD6

VSS

AD7

VSS

AD9

VSS

AE12

VSS

AE13

VSS

AE14

VSS

AE16

VSS

AE17

VSS

AE2

VSS

AE20

VSS

AE24

VSS

AE3

VSS

AE4

VSS

AE6

VSS

AE9

VSS

AF13

VSS

AF16

VSS

AF18

VSS

AF22

VSS

AH26

VSS

AF26

VSS

AF27

VSS

AF5

VSS

AF7

VSS

AF9

VSS

AG13

VSS

AG16

VSS

AG18

VSS

AG20

VSS

AG23

VSS

AG3

VSS

AG6

VSS

AG9

VSS

AH12

VSS

AH14

VSS

AH17

VSS

AH19

VSS

AH2

VSS

AH22

VSS

AH25

VSS

AH28

VSS

AH5

VSS

AH8

VSS

AJ12

VSS

AJ14

VSS

AJ17

VSS

AJ8

VSS

B11

VSS

B14

VSS

B17

VSS

B2

VSS

B20

VSS

B23

VSS

B5

VSS

B8

VSS

C26

VSS

C27

VSS

E11

VSS

E14

VSS

E18

VSS

E2

VSS

E21

VSS

E24

VSS

E5

VSS

E8

VSS

F16

VSS

F28

VSS

F29

VSS

G12

VSS

G14

VSS

G18

VSS

G21

VSS

G24

VSS

G26

VSS

G27

VSS

G8

VSS

H2

VSS

H23 H28 H29

A

NCTF TEST PIN:

VSS VSS VSS

ICH9M-GP-NF

71.ICH9M.00U

A1,A2,B1,A28,A29,B29

AH1,AJ1,AJ2,AH29,AJ28,AJ29

A1,A2,B1,A28,A29,B29

AH1,AJ1,AJ2,AH29,AJ28,AJ29

5 OF 6

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

NCTF_VSS#A1 NCTF_VSS#A2

NCTF_VSS#B1 NCTF_VSS#A29 NCTF_VSS#A28 NCTF_VSS#B29 NCTF_VSS#AJ1 NCTF_VSS#AJ2

NCTF_VSS#AH1 NCTF_VSS#AJ28 NCTF_VSS#AJ29

NCTF_VSS#AH29

H5 J23 J26 J27 AC22 K28 K29 L13 L15 L2 L26 L27 L5 L7 M12 M13 M14 M15 M16 M17 M23 M28 M29 N11 N12 N13 N14 N15 N16 N17 N18 N26 N27 P12 P13 P14 P15 P16 P17 P2 P23 P28 P29 P4 P7 R11 R12 R13 R14 R15 R16 R17 R18 R28 T12 T13 T14 T15 T16 T17 T23 B26 U12 U13 U14 U15 U16 U17 AD23 U26 U27 U3 V1 V13 V15 V23 V28 V29 V4 V5 W26 W27 W3 Y1 Y28 Y29 Y4 Y5 AG28 AH6 AF2 B25

A1 A2 B1 A29 A28 B29 AJ1 AJ2 AH1 AJ28 AJ29 AH29

TP_A1 TP_A2 TP_B1 TP_A29 TP_A28 TP_B29 TP_AJ1 TP_AJ2 TP_AH1 TP_AJ28 TP_AJ29 TP_AH29

B

C

SMB_CLK13,25,32

SMB_DATA13,25,32

D

3D3V_S5 3D3V_S0

SRN4K7J-10-GP

678

RN41

123

4 5

3D3V_S0

Q15

3 4 2

5

1

6

2N7002KDW-GP

84.2N702.A3F

E

SMBC_ICH 3,16,17

SMBD_ICH 3,16,17

SMBUS

TP152 TPAD14-GPTP152 TPAD14-GP

1

TP151 TPAD14-GPTP151 TPAD14-GP

1

TP147 TPAD14-GPTP147 TPAD14-GP

1

TP149 TPAD14-GPTP149 TPAD14-GP

1

TP150 TPAD14-GPTP150 TPAD14-GP

1

TP146 TPAD14-GPTP146 TPAD14-GP

1

TP120 TPAD14-GPTP120 TPAD14-GP

1

TP121 TPAD14-GPTP121 TPAD14-GP

1

TP130 TPAD14-GPTP130 TPAD14-GP

1

TP119 TPAD14-GPTP119 TPAD14-GP

1

TP118 TPAD14-GPTP118 TPAD14-GP

1

TP129 TPAD14-GPTP129 TPAD14-GP

1

B

C

D

Title

Size Document Number Rev

JV71-MV DDR3 Madison

Date: Sheet of

JV71-MV DDR3 Madison

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

ICH9-M (4 of 4)

E

-1

15 62Wednesday, October 28, 2009

-1

A

B

C

D

E

DDR3 SOCKET_1

DM1

4 4

3 3

2 2

0818 delete pull-up resistor(RN88~RN94),C400,C426

M_A_A[14..0]8

TP154TPAD14-GP TP154TPAD14-GP

1

M_A_BS#28 M_A_BS#08

M_A_BS#18

M_A_DQ[63..0]8

M_A_DQS#[7..0]8

Decoupling Capacitor

Layout Note

1 1

DDR_VREF _S3_1

C878

SC2D2U6D3V3MX-1-GP



Near Pin 1

DDR_VREF _S3_1

C468

SC2D2U6D3V3MX-1-GP

A



Near Pin 126

12

C879

C879 SCD1U16V2ZY-2 GP

SCD1U16V2ZY-2 GP

12

C461

C461 SCD1U16V2ZY-2 GP

SCD1U16V2ZY-2 GP

M_A_DQS[7..0]8

DDR_VREF _S3

12

C880

0818 add the net(DDR3_DRAMRST#) 0818 modify the net(DDR_VREF_S3_1)

B

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

M_ODT07 M_ODT17

DDR_VREF _S3_1 DDR_VREF _S3_1

DDR3_DR AMRST#7,17

12

C881

SC10U6D3V5MX-3GP

SCD1U16V2ZY-2GP

DM1

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P- 45-GP

62.10017.P01

High 9.2mm

RAS# CAS# CS0#

CS1# CKE0

CKE1

CK0#

CK1#

EVENT#

VDDSPD

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

NORMAL TYPE

NP1

NP2

110 113

WE#

115 114

121 73

74 101

CK0

103 102

CK1

104

M_A_DM0

11

DM0

M_A_DM1

28

DM1

M_A_DM2

46

DM2

M_A_DM3

63

DM3

M_A_DM4

136

DM4

M_A_DM5

153

DM5

M_A_DM6

170

DM6

M_A_DM7

187

DM7

200

SDA

202

SCL

198 199

DDRA_SA0

197

SA0

DDRA_SA1

201

SA1

77 122

1D5V_S3

125 75

76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

C

M_A_RAS# 8 M_A_WE# 8 M_A_CAS# 8

M_CS0# 7 M_CS1# 7

M_CKE0 7 M_CKE1 7

M_CLK_DDR0 7 M_CLK_DDR#0 7

M_CLK_DDR1 7 M_CLK_DDR#1 7

M_A_DM[7..0] 8

SMBD_ICH 3,15,17 SMBC_ICH 3,15,17

PM_EXTTS#0 7,17

10KR2J-3-GP

R748

12 12

R749 10KR2J-3-G PR749 10KR2J-3-G P

1D5V_S3

3D3V_S0

12

C434

C433

SC2D2U6D3V2MX-GP

SCD1U16V2ZY-2GP

DY

12

C442

C441

SC4D7U6D3V3KX-GP

SCD1U16V2ZY-2GP

12

C437

D

12

C463

C465

C440

SC4D7U6D3V3KX-GP

DY

SCD1U16V2ZY-2GP

12

C439

Title

Size Document Num ber Rev

Date: Sheet of

C465

SC4D7U6D3V3KX-GP

DY

SCD1U16V2ZY-2GP

12

C466

C458

DY

JV71-MV DDR3 Madison

12

C464

TC8

SC4D7U6D3V3KX-GP

TC8

SC4D7U6D3V3KX-GP

ST330U6VDM-2-GP

DY

SCD1U16V2ZY-2GP

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O.C .

Taipei Hsie n 221, Taiwan, R.O.C .

DDR3 Socket

E

2nd = 77.23371.12L

16 62Wednes day, October 28, 2009

-1

A

B

C

D

E

DDR3 SOCKET_2

DM2

4 4

TP157TPAD14-GP TP157TPAD14-GP

3 3

Layout Note

2 2

Layout Note

DDR_VREF _S3_1

1 1

DDR_VREF _S3_1

C882

SC2D2U6D3V3MX-1-GP

12

C423

SC2D2U6D3V3MX-1-GP



Near Pin 126

12

C883

C883 SCD1U16V2ZY-2 GP

SCD1U16V2ZY-2 GP



Near Pin 1

12

C424

C424 SCD1U16V2ZY-2 GP

SCD1U16V2ZY-2 GP

A

M_B_A[14..0]8

1

M_B_BS#28 M_B_BS#08

M_B_BS#18

M_B_DQ[63..0]8

M_B_DQS#[7..0]8

M_B_DQS[7..0]8

DDR_VREF _S3

0818 add the net(DDR3_DRAMRST#) 0818 modify the net(DDR_VREF_S3_1) 0824 modify DM2 pin 203,204 to (DDR_VREF_S3)

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

M_ODT27 M_ODT37

DDR_VREF _S3_1 DDR_VREF _S3_1

DDR3_DR AMRST#7,16

12

C771

C770

SC10U6D3V5MX-3GP

SCD1U16V2ZY-2GP

B

DM2

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P- 46-GP

62.10017.P11

High 5.2mm

RAS# CAS# CS0#

CS1# CKE0

CKE1

CK0#

CK1#

EVENT# VDDSPD

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

NORMAL TYPE

NP1

NP2

110 113

WE#

115 114

121 73

74 101

CK0

103 102

CK1

104

M_B_DM0

11

DM0

M_B_DM1

28

DM1

M_B_DM2M_B_DQ0

46

DM2

M_B_DM3

63

DM3

M_B_DM4

136

DM4

M_B_DM5

153

DM5

M_B_DM6

170

DM6

M_B_DM7

187

DM7

200

SDA

202

SCL

198 199

DDRB_SA0

197

SA0

DDRB_SA1

201

SA1

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

1D5V_S3

M_B_RAS# 8 M_B_WE# 8 M_B_CAS# 8

M_CS2# 7 M_CS3# 7

M_CKE2 7 M_CKE3 7

M_CLK_DDR2 7 M_CLK_DDR#2 7

M_CLK_DDR3 7 M_CLK_DDR#3 7

M_B_DM[7..0] 8

SMBD_ICH 3,15,16 SMBC_ICH 3,15,16

PM_EXTTS#0 7,16

10KR2J-3-GP

R750

R750 R751 10K R2J-3-GPR 751 10KR 2J-3-GP

0818 add R642

C

0818 add the net(PM_EXTTS#0)

3D3V_S0

12 12

12

C399

C400

SCD1U16V2ZY-2GP

DY

SC2D2U6D3V2MX-GP

1D5V_S3

12

C766

12

C768

D

12

C763

SC10U6D3V5MX-3GP

DY

SCD1U16V2ZY-2GP

12

C767

C426

SC10U6D3V5MX-3GP

SCD1U16V2ZY-2GP

12

C421

C769

DY

Title

DDR3 Socket2

Size Document Num ber Rev

Date: Sheet of

12

C428

SC4D7U6D3V3KX-GP

SCD1U16V2ZY-2GP

JV71-MV DDR3 Madison

12

C429

TC10

SC4D7U6D3V3KX-GP

12

C422

ST330U6VDM-2-GP

DY

SCD1U16V2ZY-2GP

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O.C .

Taipei Hsie n 221, Taiwan, R.O.C .

17 62Wednes day, October 28, 2009

E

2nd = 77.23371.12L

-1

USBPN4 USBPP4

LCD: DCBATOUT 2 pins LED: DCBATOUT 3 pins

1 2

SC22P50V2JN-4G P

1 2

SC22P50V2JN-4G P

EC27

EC27 EC26

EC26

DY

DY DY

DY

DCBATOUT

1 2

POLYSW-1D1 A24V-GP

69.50007.A31

2nd = 69.50007.A41

LCD/INVERTER/CCD CONN

LCD1

41

LCD_CB_SEL34

USBPP413 USBPN413

DBC_EN34

3D3V_S0

LCD_EDID_CLK LCD_EDID_DAT

BRIGHTNESS_C N BLON_OUT_1

F1

C2

SC10U35V0ZY-GPC2SC10U35V0ZY-GP

GMCH_LCDV DD_ON7

DCBATOUT _LCD1

12

ATI_LCDVDD_O N53

40 39422

38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

BRIGHTNESS_C N BLON_OUT_1

ACES-CON N40C-4-GP

20.F1296.040

2nd = 20.F1557.040

SC100P50V2JN-3GPC6SC100P50V2JN-3GP

UMA

1 2

R6 0R2J-2-GP

12

C6

R5

R5 10KR2J-3-GP

10KR2J-3-GP

LCDVDD

SCD1U16V2ZY-2GPC1SCD1U16V2ZY-2GP

12

C1

1

3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

SC100P50V2JN-3GPC4SC100P50V2JN-3GP

CCD_PW R LCD_TXBCLK + LCD_TXBCLK LCD_TXBOU T2+ LCD_TXBOU T2LCD_TXBOU T1+ LCD_TXBOU T1LCD_TXBOU T0+ LCD_TXBOU T0LCD_TXACLK + LCD_TXACLK LCD_TXAOU T2+ LCD_TXAOU T2LCD_TXAOU T1+ LCD_TXAOU T1LCD_TXAOU T0+ LCD_TXAOU T0-

R752

DY

33R2J-2-GP

12

R3

UMA

33R2J-2-GP

12

R1

DIS

33R2J-2-GP

12

1 2

1KR2F-3-GPR41KR2F-3-GP

12

C4

12

DIS

R4 R2 10KR2J-3-GPR210KR2J-3-GP

LCDVDD

U1

Layout 40 mil

12

C7

C3

SC4D7U6D3V3KX-GPC3SC4D7U6D3V3KX-GP

SCD1U16V2ZY-2GP

DY

U1

1

EN

2

GND OUT3IN#4

G5285T11U-GP

74.05285.07F

2nd = 74.09724.09F

ATI_BRIGHTNESS 53

L_BKLTCTL 7 BRIGHTNESS 34 BLON_OUT 34

3D3V_S0

5

IN#5

4

RN61

LCD_TXAOU T1LCD_TXAOU T1+ LCD_TXAOU T2LCD_TXAOU T2+

LCD_TXACLK LCD_TXACLK + LCD_TXAOU T0LCD_TXAOU T0+

LCD_TXBOU T1LCD_TXBOU T1+ LCD_TXBOU T2LCD_TXBOU T2+

LCD_TXBCLK LCD_TXBCLK + LCD_TXBOU T0LCD_TXBOU T0+

LCD_TXAOU T1LCD_TXAOU T1+ LCD_TXAOU T2LCD_TXAOU T2+

LCD_TXACLK LCD_TXACLK + LCD_TXAOU T0LCD_TXAOU T0+

LCD_TXBOU T1LCD_TXBOU T1+ LCD_TXBOU T2LCD_TXBOU T2+

LCD_TXBCLK LCD_TXBCLK + LCD_TXBOU T0LCD_TXBOU T0+

12

C5

SC4D7U6D3V3KX-GPC5SC4D7U6D3V3KX-GP

1 2 3 4 5

UMA

SRN0J-7-GP

1 2 3 4 5

UMA

SRN0J-7-GP

1 2 3 4 5

UMA

SRN0J-7-GP

1 2 3 4 5

UMA

SRN0J-7-GP

1 2 3 4 5

DIS

SRN0J-7-GP

1 2 3 4 5

DIS

SRN0J-7-GP

1 2 3 4 5

DIS

SRN0J-7-GP

1 2 3 4 5

DIS

SRN0J-7-GP

RN61

8

GMCH_TXAOU T1- 7

7

GMCH_TXAOU T1+ 7

6

GMCH_TXAOU T2- 7

8 7 6

GMCH_TXAOU T2+ 7

GMCH_TXAC LK- 7 GMCH_TXAC LK+ 7

GMCH_TXAOU T0- 7

GMCH_TXAOU T0+ 7

GMCH_TXBOU T1- 7

GMCH_TXBOU T1+ 7

GMCH_TXBOU T2- 7

GMCH_TXBOU T2+ 7

GMCH_TXBC LK- 7 GMCH_TXBC LK+ 7

GMCH_TXBOU T0- 7

GMCH_TXBOU T0+ 7

GPU_TXAOUT 1- 53 GPU_TXAOUT 1+ 53 GPU_TXAOUT 2- 53 GPU_TXAOUT 2+ 53

GPU_TXACLK- 53 GPU_TXACLK+ 53 GPU_TXAOUT 0- 53 GPU_TXAOUT 0+ 53

GPU_TXBOUT 1- 53 GPU_TXBOUT 1+ 53 GPU_TXBOUT 2- 53 GPU_TXBOUT 2+ 53

GPU_TXBCLK- 53 GPU_TXBCLK+ 53 GPU_TXBOUT 0- 53 GPU_TXBOUT 0+ 53

RN60

RN18

RN15

RN24

RN22

RN59

RN58

need confirm with VGA co-layout

INT_MIC127

Internal Mic

INT_MIC1_1

1 2

R580 0R 2J-2-GPR580 0R2J-2-GP

12

L35

MLVS0603M04-1-GP

DY

AMIC1

4 2

1 3

ACES-CON 2-17-GP

2nd 20.F1561.002

CCD_PW R

12

C498

SRN2K2J-1-G P

UMA

DIS

RN88

1 2 3

3D3V_VGA

1

23

4

SRN0J-10-G P-U

RN1

CCD_PW R

12

C499

SC4D7U10V5ZY-3GP

DY

F2

1 2

SCD1U16V2ZY-2GP

69.50007.721

2nd = 69.50007.981

FUSE-1A6V-2- GP

3D3V_S0

LCD_EDID_CLK53 LCD_EDID_DAT53

CLK_DDC_ED ID7 DAT_DDC _EDID7

SRN2K2J-1-G P

4

UMA

3D3V_S0

1

23

RN2

4

LCD_EDID_CLK LCD_EDID_DAT

JV71-MV DDR 3 Madison

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O.C .

Taipei Hsie n 221, Taiwan, R.O.C .

Title

Size Document Num ber Rev

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C .

LCD CONN

JV71-MV DDR3 Madison

18 62Wednesd ay, October 28, 2009

-1

Layout Note: Place these resistors close to the CRT-out connector

CRT_RED53

4 4

CRT_GREEN53

CRT_BLUE53

A

123

678

4 5

UMA

1 2 3 4 5

RN25

RN25 SRN150F-1-GP

SRN150F-1-GP

RN26

SRN0J-7-GP

12

C158

DY

Close to MXM card

8 7 6

SC3P50V2CN-1-GP

GMCH_BLUE 7

12

C137

DY

GMCH_RED 7

GMCH_GREEN 7

12

C109

DY

SC3P50V2CN-1-GP

Layout Note: * Must be a ground return path between this ground and the ground on the VGA connector. Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT CONN. RGB will hit 75 Ohm first, pi-filter, then CRT CONN.

3 3

B

Ferrite bead impedance: 10 ohm@100MHz

L5

1 2

FCB1608CF-GP

68.00230.021

2nd =

L4

1 2

FCB1608CF-GP

68.00230.021

2nd =

L3

1 2

FCB1608CF-GP

68.00230.021

2nd =

SC3P50V2CN-1-GP

12

C165

SC2D2P50V2CC-GP

C151

C

D

E

Hsync & Vsync level shift

4

U18B

73.74125.L13

5V_S0

12

C107

C107 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

14

1

2 3

U18A

7

TSAHCT125PW-GP

73.74125.L13

2nd = 73.74125.L12

CRT_HSYNC1_1

CRT_VSYNC1_1

5V_S0 5V_S0

14

9 8

7

2nd = 73.74125.L12

R558

1 2

0R0402-PAD

R559

1 2

0R0402-PAD

10

U18C

TSAHCT125PW-GP

73.74125.L13

CRT_HSYNC1

CRT_VSYNC1

12 11

14

13

U18D

7

TSAHCT125PW-GP

73.74125.L13

2nd = 73.74125.L12

CRT_R

CRT_G

DIS

CRT_B

12

C108

SC2D2P50V2CC-GP

CRT_HSYNC53,56 CRT_VSYNC53,56

GMCH_HSYNC7 GMCH_VSYNC7

DIS

2 3 1

RN63

RN63 SRN0J-10-GP-U

SRN0J-10-GP-U

UMA

1 2 3

RN62

RN62 SRN0J-10-GP-U

SRN0J-10-GP-U

12

C632

DY

HSYNC_1

14

VSYNC_1

5 6

7

TSAHCT125PW-GP

2nd = 73.74125.L12

SC47P50V2JN-3GP

12

C633

DY

2nd = 73.74125.L12

4

SC47P50V2JN-3GP

DDC_CLK & DATA level shift

5V_CRT_S0

5V_S0 5V_S0 5V_S0

D23

D24

CRT_R CRT_G CRT_B

3

BAV99PT-GP-U

1

DY

2

CRT I/F & CONNECTOR

2 2

CRT_R

CRT_G CRT_B

CRT_IN#_R

12

C128SC100P50V2JN-3GPDYC128SC100P50V2JN-3GP

DY

12

SC18P50V2JN-1-GP

C115

12

C105

12

DY

SC100P50V2JN-3GP

DAT_DDC1_5 CRT_HSYNC1 CRT_VSYNC1 CLK_DDC1_5

C93

CRT1

16

1

2 3 4

5

17

2nd = 20.20764.015

6 11

7 12 8 13 9 14 10 15

VIDEO-15-47-GP-U

20.20392.015

D23

3

DY

BAV99PT-GP-U

DAT_DDC1_5 CRT_HSYNC1 CRT_VSYNC1 CLK_DDC1_5

1

2

5V_CRT_S0

D22

1

3

DY

BAV99PT-GP-U

C602

C602 SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

2

FUSE-1D1A6V-4GP-U

69.50007.691

2nd = 69.50007.771

UMA

3D3V_S0

4

RN66

RN66 SRN2K2J-1-GP

SRN2K2J-1-GP

1

2 3

DAT_DDC1_5_Q

CLK_DDC1_5_Q

84.2N702.A3F

2N7002KDW-GP

5 6

U42

3D3V_VGA

RN112

RN112 SRN2K2J-1-GP

SRN2K2J-1-GP

DIS

CRT_DDCDATA53 CRT_DDCCLK53

GMCH_DDCDATA7 GMCH_DDCCLK7

2 3 1

RN57

RN57 SRN0J-10-GP-U

SRN0J-10-GP-U

UMA

1 2 3

RN53

RN53 SRN0J-10-GP-U

SRN0J-10-GP-U

4

1

2 3

4

12

F3

5V_CRT_DDC

34 2 1

5V_S0

D4

D4 CH551H-30PT-GP

CH551H-30PT-GP

83.R5003.C8F

2 1

500mA

2nd = 83.R5003.H8H

678

RN20

SRN10KJ-6-GP

123

4 5

3D3V_S0

CRT_IN#_R

DAT_DDC1_5

CLK_DDC1_5

6 1

R93

1 1

7 2 8

CRT_DEC#34

3 9 4 10 5

A

R93

470R2J-2-GP

SC100P50V2JN-3GP

JV71-MV DDR3 Madison

CRT_IN#_R

12

C98

CRT_IN#_R

B

D21

3

DY

BAV99PT-GP-U

5V_S0

1

2

C

D

JV71-MV DDR3 Madison

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CRT CONN

Size Document Number Rev

Date: Sheet of

CRT CONN

JV71-MV DDR3 Madison

Taipei Hsien 221, Taiwan, R.O.C.

19 62Wednesday, October 28, 2009

E

-1