Acer 0917 Schematics

A

B

C

D

E

Model Name:
PCB NO:
BOM P/N:

1 1

KML50 DIS
LA-4595PR04
DA80000DR00

Half Penny Bridge 15.4

2 2

Compal Confidential

Schematic Document

Cantiga + ICH9

2009 / 02 / 17

3 3

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev:1.0(A00)

Compal Secret Data

Compal Secret Data

2007/1/15 2008/1/15

2007/1/15 2008/1/15

2007/1/15 2008/1/15

C

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

Cover Sheet

Cover Sheet

LA-4595P

LA-4595P

LA-4595P

E

1 49Tuesday, February 17, 2009

1.0

1.0

1.0

of

of

of

1 49Tuesday, February 17, 2009

1 49Tuesday, February 17, 2009

A

B

C

D

E

Compal confidential

Half Penny Bridge 15.4 DIS

File Name : LA-4595P

ZZZ1

ZZZ1

PCB

PCB

1 1

CRT

+CRT_VCC

P.16

LVDS Panel Interface

+B+
+3VS
+LCDVDD

P.16

Thermal Sensor
EMC1402-2-ACZL-TR

+3VS

Fan conn

+5VS

P.4

P.4

nVidia
NB9M-GS

+VGA_CORE

VRAM x 2

+1.8VS +USB_BS +USB_CS

2 2

P.35

CardBus Controller

O2MICRO OZ888

+1.8VS_CB

+3VS_PHY

1394

+1.1V_GFX_PCIE

+1.8VS

+3VS

P.30

Media Card

+3VS_CR

P.31,32,33,34

PCI -E BUS

DMI X4

PCI-E BUS

Penryn -4MB (Socket P)

+CPU_CORE

+VCCP

+1.5VS

uFCPGA-478 CPU

P.4,5,6

H_A#(3..35)

H_D#(0..63)

FSB

800/1066MHz 1.05V

Intel Cantiga MCH

+VCCP

+1.05VS_DPLLA

+1.05VS_DPLLB

+1.8V_TXLVDS

1329pin BGA

+3VS_DAC_CRT

+3VS_DAC_BG

Intel ICH9-M

+RTCVCC

+1.5VS

+VCCP
+3VALW

676pin BGA

P.17,18,19,20

P.7,8,9,10,11,12

C-Link

DDR2 667/800MHz 1.8V

Dual Channel

USB2.0

Azalia

SATA 0

SATA 1

DDR2-SO-DIMM X2

BANK 0, 1, 2, 3

+1.8V

+0.9VS

P.13,14

USB conn x 4

+USB_AS

FingerPrinter

+3VS

Felica Conn

+5VS

BT Conn

+3VS

Camera

+3VS +5VS

P.29

P.29

P.29

P.16

CK505

Clock Generator
ICS9LPRS387AKLFT

+1.05VS_CK505

+3VS_CK505

P.29

TSSOP-64

P.15

10/100/1000 LAN

REALTEK
RTL8111DL

+LAN_IO

3 3

RJ45/11 CONN

P.21

P.21

Mini-Card-2
(WLAN)

+1.5VS

+3VS

P.23 P.23 P.26

Mini-Card-1
(WWAN)

+1.5VS

+3VS

SIM CON

+UIM_PWR

Express Card

+1.5VS

+3VS

LPC BUS

Express Card

+3VS +1.5VS

Mini-Card-1

Mini-Card-2

+1.5VS+3VS

+1.5VS+3VS

P.26

P.23

P.23

Digi Mic

P.16

+3VS

Audio Jack

+MIC1_VREFO

P.24

Mini-Card-2

+1.5VS+3VS

P.23

ENE KB926

+3VALW

+EC_AVCC

P.27

TPM

SLB 9635

+3VALW

+3VS

P.28

Audio CODEC
IDT92HD81

+5VS +3VS

P.24

SATA HDD Connector

Power On/Off CKT.

+3VALW

4 4

DC/DC Interface CKT.

+3VS

+5VS

P.28

P.36

RTC CKT.

+RTCVCC

P.18

Power Circuit DC/DC

P.39~P.49

A

Touch Pad CONN. Int.KBD

+5VS

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

BIOS(System/EC)

+3VALW

2007/1/15 2008/1/15

2007/1/15 2008/1/15

2007/1/15 2008/1/15

C

P.27P.28P.28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

+5VS

CDROM Conn.

+5VS

D

P.22

P.22

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Block diagram

Block diagram

Block diagram

LA-4595P

LA-4595P

LA-4595P

E

of

of

of

2 49Tuesday, February 17, 2009

2 49Tuesday, February 17, 2009

2 49Tuesday, February 17, 2009

1.0

1.0

1.0

Voltage Rails

power
plane

State

O MEANS ON X MEANS OFF

+5VALW

+B

+3VALW

+1.8V

+5VS

+3VS

+1.5VS

+0.9VS

+VCCP

+CPU_CORE

+VGA_CORE

+1.8VS

+1.1V_GFX_PCIEP

A

Symbol Note :

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build

CON@ : means ME connectors

TPM@ : means TPM function

PCI EXPRESS

DESTINATION

SATA

DESTINATION

Lane 1

Lane 2

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

1 1

USB PORT#

O

O

O

O

O

X

0

1

2

3

ICH9-M

4

5

6

7

9

O

O

O

O

X

O

X X

X

X X X

DESTINATION

JUSBP1

CAMERA

JUSBP3 TOP

Felica

Blue Tooth

Finger Printer

JMINI2-WLAN

Express card

JUSBP3 BOT8

JMINI1-WWAN

JUSBP410

OO

OO

X

Lane 3

Lane 4

Lane 5

Lane 6

X

SMBUS Control Table

SMB_EC_CK1
SMB_EC_DA1

SMB_EC_CK2
SMB_EC_DA2

SMB_CK_CLK1
SMB_CK_DAT1 ICH9

LCD_CLK
LCD_DAT

I2C / SMBUS ADDRESSING

DEVICE

DDR SO-DIMM 0

DDR SO-DIMM 1

CLOCK GENERATOR (EXT.)

LED panel 58 0 1 0 1 1 0 0 0

MINI CARD-1 WWAN

GLAN RTL8111DL

MINI CARD-2 WLAN

EXPRESS CARD

CARD READER OZ888

NA

SOURCE

KB926

KB926

INVERTER BATT EEPROM

X
X

X

Cantiga

X X

HEX

A0

D2

SERIAL SENSOR

V V

X X

X

X

X X

ADDRESS

1 0 1 0 0 0 0 0

1 0 1 0 0 1 0 0A4

1 1 0 1 0 0 1 0

THERMAL

(CPU)

X X

V

X

Lane 0

Lane 1

Lane 4

Lane 5 NA

SODIMM CLK CHIP

X

X

X

V V

X X

HDD

ODD

NA

MINI CARD

X X
X

X

X

LCD

X

X

V

11

NA

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2005/03/10 2006/03/10

2005/03/10 2006/03/10

2005/03/10 2006/03/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Notes List

Notes List

Notes List

LA-4595P

LA-4595P

LA-4595P

3 49Tuesday, February 17, 2009

3 49Tuesday, February 17, 2009

3 49Tuesday, February 17, 2009

of

of

of

1.0

1.0

1.0

5

D D

CONN@

H_A#[3..16]< 7>

H_ADSTB#0<7>

H_REQ#0<7>
H_REQ#1<7>
H_REQ#2<7>
H_REQ#3<7>
H_REQ#4<7>

C C

B B

A A

H_A#[17..35]<7>

H_ADSTB#1<7>

H_A20M#<18>
H_FERR#<18>
H_IGNNE#<18>

H_STPCLK#<18>
H_INTR<18>
H_NMI<18>
H_SMI#<18>

+VCCP

B

B

E

H_PROCHOT# OCP#

H_IERR#

E

3 1

Q2

@

Q2

@

MMBT3904_SOT23

MMBT3904_SOT23

+VCCP

12

@

@

R17

R17
56_0402_5%

56_0402_5%

2

C

C

R18

R18
56_0402_5%

56_0402_5%

1 2

5

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

H_A20M#
H_FERR#
H_IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

CONN@

JCPU1A

JCPU1A

J4

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

V1

ADSTB[1]#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD[01]

N5

RSVD[02]

T2

RSVD[03]

V3

RSVD[04]

B2

RSVD[05]

D2

RSVD[06]

D22

RSVD[07]

D3

RSVD[08]

F6

RSVD[09]

Penryn

Penryn

OCP# <19>

ADDR GROUP_0

ADDR GROUP_0

ADDR GROUP_1

ADDR GROUP_1

THERMAL

THERMAL

ICH

ICH

THERMTRIP#

RESERVED

RESERVED

ADS#
BNR#

BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

CONTROL

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TRST#

DBR#

XDP/ITP SIGNALS

XDP/ITP SIGNALS

PROCHOT#

THERMDA
THERMDC

H CLK

H CLK

BCLK[0]
BCLK[1]

TCK

TDO
TMS

H1
E2
G5

H5
F21
E1

F1

D20
B3

H4

C1
F3
F4
G3
G2

G6
E4

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6

TDI

AB3
AB5
AB6
C20

D21
A24
B25

C7

A22
A21

4

H_ADS#
H_BNR#
H_BPRI#

H_DEFER#
H_DRDY#
H_DBSY#

H_BR0#

H_IERR#
H_INIT#

H_LOCK#

H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#

H_HIT#
H_HITM#

XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#

H_PROCHOT#

H_THERMDC_R

H_THERMTRIP#

CLK_CPU_BCLK
CLK_CPU_BCLK#

4

H_ADS# <7>
H_BNR# <7>
H_BPRI# <7>

H_DEFER# <7>
H_DRDY# <7>
H_DBSY# <7>

H_BR0# <7>

H_INIT# <18>

H_LOCK# <7>

H_RESET# <7>
H_RS#0 <7>
H_RS#1 <7>
H_RS#2 <7>
H_TRDY# <7>

H_HIT# <7>
H_HITM# <7>

T84T84

XDP_DBRESET# <19>

R146

68_0402_1%~D

R146

R57 100_0402_5%R57 100_0402_5%
R53 100_0402_5%R53 100_0402_5%

H_THERMTRIP# <7,18>

CLK_CPU_BCLK <15>
CLK_CPU_BCLK# <15>

68_0402_1%~D

1 2
1 2

H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil

+VCCP

H_THERMDAH_THERMDA_R
H_THERMDC

3

C5

C5

1 2

+3VS

+3VS

1

C13

C13

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2200P_0402_50V7K

2200P_0402_50V7K

R16

R16

1 2

10K_0402_5%

10K_0402_5%

2

H_THERMDA

H_THERMDC

L_THERM#

FAN Control circuit

C94

C94

2

EN_DFAN1

+3VS

12

2

1

EN_DFAN1<27>

FAN_SPEED1<27>

0.01U_0402_16V7K

0.01U_0402_16V7K

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

2006/02/13 2006/03/10

2006/02/13 2006/03/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

1

XDP_TDI

XDP_TMS

XDP_TRST#

XDP_TCK

R5 54.9_0402_1%R5 54.9_0402_1%

1 2

R4 54.9_0402_1%R4 54.9_0402_1%

1 2

R11 54.9_0402_1%R11 54.9_0402_1%

1 2

R35 54.9_0402_1%R35 54.9_0402_1%

1 2

This shall place near CPU

Thermal Sensor EMC1402-1-ACZL-TR

U2

1

2

3

EMC1402-2-ACZL-TR MSOP 8P

EMC1402-2-ACZL-TR MSOP 8P

Address:100_11000

R61

R61

10K_0402_5%

10K_0402_5%

3

U2

VDD

SCLK

D+

SDATA

ALERT#

D-

THERM#4GND

C76

C76

10U_1206_16V4Z~N

10U_1206_16V4Z~N

C88

C88

1000P_0402_50V7K~N

1000P_0402_50V7K~N

FAN1_POWER

2

D61

D61
PJSOT24C_SOT23-3

PJSOT24C_SOT23-3

@

@

1

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

EC_SMB_CK2

8

EC_SMB_DA2

7

6

5

12

+5VS

1 2

12

40mil

LA-4595P

LA-4595P

LA-4595P

C77 10U_1206_16V4Z~NC77 10U_1206_16V4Z~N

U3

U3

1

VEN

2

VIN

3

VO

4

VSET

RT9027BPS SO 8P

RT9027BPS SO 8P

JFAN1

JFAN1

1

1

2

2

3

3

4

GND

5

GND

ACES_85205-03001

ACES_85205-03001

conn@

conn@

FAN1

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Penryn(1/3)-AGTL+/ITP-XDP

Penryn(1/3)-AGTL+/ITP-XDP

Penryn(1/3)-AGTL+/ITP-XDP

EC_SMB_CK2 <16,27,31>

EC_SMB_DA2 <16,27,31>

8

GND

7

GND

6

GND

5

GND

1

+VCCP

4 49Tuesday, February 17, 2009

4 49Tuesday, February 17, 2009

4 49Tuesday, February 17, 2009

1.0

1.0

1.0

of

of

of

5

4

3

2

1

CONN@

H_D#[0..15]<7>

D D

H_DSTBN#0<7>
H_DSTBP#0<7>
H_DINV#0<7>
H_D#[16..31]<7>

C C

H_DSTBN#1<7>
H_DSTBP#1<7>
H_DINV#1<7>

T50T50
T51T51
T2T2
T3T3
T4T4
T5T5

T6T6

CPU_BSEL0<15>
CPU_BSEL1<15>
CPU_BSEL2<15>

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1

+V_CPU_GTLREF

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

layout note: Rout H_DPRSTP# from ICH9 to IMVP6 then to GMCH & CPU

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

CPU_BSEL CPU_BSEL2 CPU_BSEL1

B B

166

200

0 1

0

1

CONN@

JCPU1B

JCPU1B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

C3

TEST7

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

Penryn

Penryn

CPU_BSEL0

H_D#32

Y22

MISC

MISC

DATA GRP 0

DATA GRP 0

DATA GRP 1

DATA GRP 1

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#

DATA GRP 2DATA GRP 3

DATA GRP 2DATA GRP 3

D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#

COMP[0]
COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#
DPWR#

PWRGOOD

SLP#

PSI#

AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3

COMP0
COMP1
COMP2
COMP3

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#

1

H_D#[32..47] <7>

H_DSTBN#2 <7>
H_DSTBP#2 <7>
H_DINV#2 <7>
H_D#[48..63] <7>

H_DSTBN#3 <7>
H_DSTBP#3 <7>
H_DINV#3 <7>

H_DPRSTP# <7,18,47>
H_DPSLP# <18>

H_DPWR# <7>

H_PWRGOOD <18>
H_CPUSLP# <7>

H_PSI# <47>

R23

12

54.9_0402_1%

54.9_0402_1%

Resistor p laced with in

0.5" of CP U pin.Trac e
should be at least 2 5
mils away from any o ther
toggling s ignal.
COMP[0,2] trace widt h is
18 mils. C OMP[1,3] t race
width is 4

12

12

54.9_0402_1%

54.9_0402_1%

27.4_0402_1%

27.4_0402_1%

27.4_0402_1%

27.4_0402_1%

R25

R25

R24

R24

R23

0

+CPU_CORE +CPU_CORE

R26

R26

12

AA7

AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20

AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18

CONN@

CONN@

JCPU1C

JCPU1C

A7

VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]

Penryn

Penryn

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VCCSENSE

VSSSENSE

A9
A10
A12
A13
A15
A17
A18
A20

B7

B9
B10
B12
B14
B15
B17
B18
B20

C9
C10
C12
C13
C15
C17
C18

D9
D10
D12
D14
D15
D17
D18

E7

E9
E10
E12
E13
E15
E17
E18
E20

F7

F9
F10
F12
F14
F15
F17
F18
F20

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

VCCSENSE

VSSSENSE

CPU_VID0 <47>
CPU_VID1 <47>
CPU_VID2 <47>
CPU_VID3 <47>
CPU_VID4 <47>
CPU_VID5 <47>
CPU_VID6 <47>

VCCSENSE <47>

VSSSENSE <47>

220U_D2_4VY_R15M

220U_D2_4VY_R15M

+VCCP

C10

C10

10U_0805_6.3V6M

10U_0805_6.3V6M

1

+

+

2

1

C12

C12

2

+1.5VS

1

C11

C11

2

0.01U_0402_16V7K

0.01U_0402_16V7K

Near pin B26

266 0 0 0

+VCCP

12

R27

R27
1K_0402_1%

1K_0402_1%

12

R29

R29
2K_0402_1%

2K_0402_1%

+V_CPU_GTLREF

Close to CPU pin AD26

For 8 layer condition
Length match within 25 mils.Z0=27.4 ohm
The trace width/space/other is 20/7/25.

+CPU_CORE

R28 100_0402_1%R28 100_0402_1%

1 2

R30 100_0402_1%R30 100_0402_1%

1 2

VCCSENSE

VSSSENSE

within 500mils.

A A

Close to CPU pin
within 500mils.

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

2006/02/13 2006/03/10

2006/02/13 2006/03/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Penryn(2/3)-AGTL+/ITP-XDP

Penryn(2/3)-AGTL+/ITP-XDP

Penryn(2/3)-AGTL+/ITP-XDP

LA-4595P

LA-4595P

LA-4595P

1

1.0

1.0

1.0

of

of

of

5 49Tuesday, February 17, 2009

5 49Tuesday, February 17, 2009

5 49Tuesday, February 17, 2009

5

High Frequence Decoupling

10uF 0805 X5R -> 85 degree.

Place these caps inside
the CPU socket cavity.

( Left side on Top ).

D D

C C

B B

CONN@

CONN@

JCPU1D

JCPU1D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]
VSS[081]P3VSS[162]

Penryn

Penryn

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]

VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

.

.

Place these caps inside
the CPU socket cavity.

( Right side on Top side).

Place these caps inside
the CPU socket cavity.

( Left side on Bottom ).

Place these caps inside
the CPU socket cavity.

( Right side on Bottom ).

Place these caps inside
the CPU socket.

+VCCP

1

C213

C213

0.1U_0402_10V6K

0.1U_0402_10V6K

2

4

+CPU_CORE

+CPU_CORE

+CPU_CORE

+CPU_CORE

+CPU_CORE

C196

C196

1

C209

C209

0.1U_0402_10V6K

0.1U_0402_10V6K

2

1

C204

C204
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C178

C178
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C501

C501
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C502

C502
10U_0805_6.3V6M

10U_0805_6.3V6M

2

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

1

+

+

2

C198

C198

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

1

+

+

2

1

2

1

C205

C205
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C202

C202
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C508

C508
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C510

C510
10U_0805_6.3V6M

10U_0805_6.3V6M

2

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

1

C259

C259

+

+

2

C212

C212

0.1U_0402_10V6K

0.1U_0402_10V6K

1

C529

C529
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C254

C254
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C514

C514
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C515

C515
10U_0805_6.3V6M

10U_0805_6.3V6M

2

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

Place these caps inside

1

C255

C255

the CPU socket.

+

+

( Right side on Top side).( Left side on Top ).

2

1

C185

C185

0.1U_0402_10V6K

0.1U_0402_10V6K

2

3

1

C232

C232
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C190

C190
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C519

C519
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C520

C520
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C183

C183

0.1U_0402_10V6K

0.1U_0402_10V6K

2

1

C258

C258
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C203

C203
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C522

C522
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C526

C526
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C505

C505
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C200

C200
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C533

C533
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C532

C532
10U_0805_6.3V6M

10U_0805_6.3V6M

2

ESR <= 1.5m ohm

Capacitor > 880 uF

Place these inside
socket cavity on L8
(North side
Secondary)

1

C184

C184

0.1U_0402_10V6K

0.1U_0402_10V6K

2

2

1

C504

C504
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C182

C182
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C257

C257
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C199

C199
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C261

C261
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C208

C208
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

Place these caps inside
the CPU socket.

1

( Left side on Top ).

C214

C214
10U_0805_6.3V6M

10U_0805_6.3V6M

2

Place these caps inside
the CPU socket.

1

( Right side on Top ).

C226

C226
10U_0805_6.3V6M

10U_0805_6.3V6M

2

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

2006/02/13 2006/03/10

2006/02/13 2006/03/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Penryn(3/3)-AGTL+/ITP-XDP

Penryn(3/3)-AGTL+/ITP-XDP

Penryn(3/3)-AGTL+/ITP-XDP

LA-4595P

LA-4595P

LA-4595P

1

1.0

1.0

1.0

of

of

of

6 49Tuesday, February 17, 2009

6 49Tuesday, February 17, 2009

6 49Tuesday, February 17, 2009

5

U4A

24.9_0402_1%

24.9_0402_1%

F2

G8

F8

E6
G2
H6
H2

F6
D4
H3
M9

M11

J1
J2

N12

J6
P2
L2

R2
N9

L6

M5

J3

N2
R1
N5
N6

P13

N8

L7

N10

M3

Y3

AD14

Y6

Y10
Y12
Y14

Y7

W2

AA8

Y9

AA13

AA9
AA11
AD11
AD10
AD13
AE12

AE9

AA2

AD8

AA3

AD3

AD7
AE14

AF3

AC1

AE3

AC3
AE11

AE8

AG2

AD6

C5

E3

C12

E11

A11

B11

H_RCOMP

12

R324

R324

U4A

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

H_SWING
H_RCOMP

H_CPURST#
H_CPUSLP#

H_AVREF
H_DVREF

CANTIGA_1p0

CANTIGA_1p0

+VCCP

221_0603_1%

221_0603_1%

100_0402_1%

100_0402_1%

H_ADSTB#_0
H_ADSTB#_1

H_DEFER#

HPLL_CLK

HPLL_CLK#

H_DPWR#

HOST

HOST

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

12

R322

R322

H_SWNG

12

1

C386

C386

R323

R323

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

H_D#[0..63]<5>

D D

C C

H_RESET#<4>

H_CPUSLP#<5>

B B

H_RCOMP Dual core 24.9 ohm_1% pull down
Quad core 16.9 ohm_1% pull down
H_SWNG Dual core 100 ohm_1% pull down
Quad core 75 ohm_1% pull down

Layout Not e:
H_RCOMP / H_VREF / H_SWNG

trace wid th and spa cing is 10 /20

+VCCP

12

R45

R45

1K_0402_1%

1K_0402_1%

A A

12

R46

2K_0402_1%

2K_0402_1%

R46

0.1U_0402_16V4Z

0.1U_0402_16V4Z

H_SWNG
H_RCOMP

H_RESET#
H_CPUSLP#

+H_VREF

+H_VREF

@

@

1

C391

C391

2

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

Near B3 pinwithin 100 mils from NB

CRB-no stuff
Checklist-no

5

10/16

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31

H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_BNR#
H_BPRI#

H_BREQ#

H_DBSY#

H_DRDY#

H_HIT#

H_HITM#
H_LOCK#
H_TRDY#

H_RS#_0

H_RS#_1

H_RS#_2

4

H_A#3

A14

H_A#4

C15

H_A#5

F16

H_A#6

H13

H_A#7

C18

H_A#8

M16

H_A#9

J13

H_A#10

P16

H_A#11

R16

H_A#12

N17

H_A#13

M13

H_A#14

E17

H_A#15

P17

H_A#16

F17

H_A#17

G20

H_A#18

B19

H_A#19

J16

H_A#20

E20

H_A#21

H16

H_A#22

J20

H_A#23

L17

H_A#24

A17

H_A#25

B17

H_A#26

L16

H_A#27

C21

H_A#28

J17

H_A#29

H20

H_A#30

B18

H_A#31

K17

H_A#32

B20

H_A#33

F21

H_A#34

K21

H_A#35

L20

H_ADS#

H12

H_ADSTB#0

B16

H_ADSTB#1

G17

H_BNR#

A9

H_BPRI#

F11

H_BR0#

G12

H_DEFER#

E9

H_DBSY#

B10

CLK_MCH_BCLK

AH7

CLK_MCH_BCLK#

AH6

H_DPWR#

J11

H_DRDY#

F9

H_HIT#

H9

H_HITM#

E12

H_LOCK#

H11

H_TRDY#

C9

H_DINV#0

J8

H_DINV#1

L3

H_DINV#2

Y13

H_DINV#3

Y1

H_DSTBN#0

L10

H_DSTBN#1

M7

H_DSTBN#2

AA5

H_DSTBN#3

AE6

H_DSTBP#0

L9

H_DSTBP#1

M8

H_DSTBP#2

AA6

H_DSTBP#3

AE5

H_REQ#0

B15

H_REQ#1

K13

H_REQ#2

F13

H_REQ#3

B13

H_REQ#4

B14

H_RS#0

B6

H_RS#1

F12

H_RS#2

C8

ICH_PWROK<19,27>

VGATE<19,27,47>

Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.

+V_DDR_MCH_REF<13,14>

4

H_A#[3..35] <4>

+SMRCOMP_VOH

H_ADS# <4>
H_ADSTB#0 <4>
H_ADSTB#1 <4>
H_BNR# <4>
H_BPRI# < 4>
H_BR0# <4>
H_DEFER# <4>
H_DBSY# <4>
CLK_MCH_BCLK <15>
CLK_MCH_BCLK# <15>
H_DPWR# <5>
H_DRDY# <4>
H_HIT# <4>
H_HITM# <4>
H_LOCK# <4>
H_TRDY# <4>

H_DINV#0 <5>
H_DINV#1 <5>
H_DINV#2 <5>
H_DINV#3 <5>

H_DSTBN#0 <5>
H_DSTBN#1 <5>
H_DSTBN#2 <5>
H_DSTBN#3 <5>

H_DSTBP#0 <5>
H_DSTBP#1 <5>
H_DSTBP#2 <5>
H_DSTBP#3 <5>

H_REQ#0 <4>
H_REQ#1 <4>
H_REQ#2 <4>
H_REQ#3 <4>
H_REQ#4 <4>

H_RS#0 <4>
H_RS#1 <4>
H_RS#2 <4>

PLT_RST#<17,27,30,31>

H_THERMTRIP#<4,18>

DPRSLPVR<19,47>

1 2

R408 0_0402_5%R408 0_0402_5%

1 2

R407 0_0402_5%@R407 0_0402_5%@

+V_DDR_MCH_REF

0.1U_0402_16V4Z

0.1U_0402_16V4Z

3

T7T7
T11T11
T12T12

+1.8V

1

1

12

R331

C398

C398

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

2

1

C403

C403

2

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

1

C121

C121

2

R331

C400

C400

1K_0402_1%

1K_0402_1%

0.01U_0402_25V7K

0.01U_0402_25V7K

2

12

R332

R332

3.01K_0402_1%

3.01K_0402_1%

12

R333

R333

1

1K_0402_1%

1K_0402_1%

C404

C404

2

0.01U_0402_25V7K

0.01U_0402_25V7K

R82

R82

PM_EXTTS#0

PM_EXTTS#1

PM_PWROK_R

+1.8V

12

R42

R42
1K_0402_1%

1K_0402_1%

12

R43

R43
1K_0402_1%

1K_0402_1%

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

10K_0402_5%

10K_0402_5%

R83

R83

1 2

10K_0402_5%

10K_0402_5%

MCH_CLKSEL0<15>
MCH_CLKSEL1<15>
MCH_CLKSEL2<15>

CFG16<9>

CFG19<9>
CFG20<9>

PM_BMBUSY#<19>

H_DPRSTP#<5,18,47>
PM_EXTTS#0<13>
PM_EXTTS#1<14>

1 2

R523 100_0402_5%R523 100_0402_5%

3

T13T13
T14T14
T15T15
T16T16
T17T17
T18T18
T19T19
T20T20
T21T21
T22T22
T24T24

T25T25
T26T26
T27T27

T28T28

T41T41
T44T44
T73T73
T74T74

+3VS

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2

T8PAD T8PAD

T9PAD T9PAD

CFG5<9>
CFG6<9>
CFG7<9>

CFG9<9>

CFG5
CFG6
CFG7

T37PAD T37PAD

CFG9

T65PAD T65PAD

T40PAD T40PAD

CFG12

T67PAD T67PAD

CFG13

T47PAD T47PAD

T10PAD T10PAD

T66PAD T66PAD

CFG16

T68PAD T68PAD

T39PAD T39PAD

CFG19
CFG20

PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1

PM_PWROK_R

PLT_RST#_NBPLT_RST#
H_THERMTRIP#
DPRSLPVR

2008/09/24 2006/03/10

2008/09/24 2006/03/10

2008/09/24 2006/03/10

U4B

U4B

M36

RSVD1

N36

RSVD2

R33

RSVD3

T33

RSVD4

AH9

RSVD5

AH10

RSVD6

AH12

RSVD7

AH13

RSVD8

K12

RSVD9

AL34

RSVD10

AK34

RSVD11

AN35

RSVD12

AM35

RSVD13

T24

RSVD14

B31

RSVD15

B2

RSVD16

M1

RSVD17

AY21

RSVD20

BG23

RSVD22

BF23

RSVD23

BH18

RSVD24

BF18

RSVD25

T25

CFG_0

R25

CFG_1

P25

CFG_2

P20

CFG_3

P24

CFG_4

C25

CFG_5

N24

CFG_6

M24

CFG_7

E21

CFG_8

C23

CFG_9

C24

CFG_10

N21

CFG_11

P21

CFG_12

T21

CFG_13

R20

CFG_14

M20

CFG_15

L21

CFG_16

H21

CFG_17

P29

CFG_18

R28

CFG_19

T28

CFG_20

R29

PM_SYNC#

B7

PM_DPRSTP#

N33

PM_EXT_TS#_0

P32

PM_EXT_TS#_1

AT40

PWROK

AT11

RSTIN#

T20

THERMTRIP#

R32

DPRSLPVR

BG48

NC_1

BF48

NC_2

BD48

NC_3

BC48

NC_4

BH47

NC_5

BG47

NC_6

BE47

NC_7

BH46

NC_8

BF46

NC_9

BG45

NC_10

BH44

NC_11

BH43

NC_12

BH6

NC_13

BH5

NC_14

BG4

NC_15

BH3

NC_16

BF3

NC_17

BH2

NC_18

BG2

NC_19

BE2

NC_20

BG1

NC_21

BF1

NC_22

BD1

NC_23

BC1

NC_24

F1

NC_25

A47

NC_26

CANTIGA_1p0

CANTIGA_1p0

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

RSVD

RSVD

NC

NC

2

SM_RCOMP_VOH

SM_RCOMP_VOL

DDR CLK/ CONTROL/COMPENSATION

DDR CLK/ CONTROL/COMPENSATION

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLK

CLK

CFG

CFG

DMI

DMI

PM

PM

GRAPHICS VID

GRAPHICS VID

MEHDA

MEHDA

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

MISC

MISC

2

SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1

SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1

SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1

SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1

SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_VREF

SM_PWROK

SM_REXT

SM_DRAMRST#

DPLL_REF_CLK

PEG_CLK

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST#
CL_VREF

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCLK

HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

1

M_CLK_DDR0

AP24

M_CLK_DDR1

AT21

M_CLK_DDR2

AV24

M_CLK_DDR3

AU20

M_CLK_DDR#0

AR24

M_CLK_DDR#1

AR21

M_CLK_DDR#2

AU24

M_CLK_DDR#3

AV20

DDR_CKE0_DIMMA

BC28

DDR_CKE1_DIMMA

AY28

DDR_CKE2_DIMMB

AY36

DDR_CKE3_DIMMB

BB36

DDR_CS0_DIMMA#

BA17

DDR_CS1_DIMMA#

AY16

DDR_CS2_DIMMB#

AV16

DDR_CS3_DIMMB#+SMRCOMP_VOL

AR13

M_ODT0

BD17

M_ODT1

AY17

M_ODT2

BF15

M_ODT3

AY13

SMRCOMP

BG22

SMRCOMP#

BH21

+SMRCOMP_VOH

BF28

+SMRCOMP_VOL

BH28

+V_DDR_MCH_REF

AV42
AR36

SM_REXT

BF17

TP_SM_DRAMRST#

BC36

B38
A38
E41
F41

CLK_MCH_3GPLL

F43

CLK_MCH_3GPLL#

E43

DMI_MRX_ITX_N0

AE41

DMI_MRX_ITX_N1

AE37

DMI_MRX_ITX_N2

AE47

DMI_MRX_ITX_N3

AH39

DMI_MRX_ITX_P0

AE40

DMI_MRX_ITX_P1

AE38

DMI_MRX_ITX_P2

AE48

DMI_MRX_ITX_P3

AH40

DMI_MTX_IRX_N0

AE35

DMI_MTX_IRX_N1

AE43

DMI_MTX_IRX_N2

AE46

DMI_MTX_IRX_N3

AH42

DMI_MTX_IRX_P0

AD35

DMI_MTX_IRX_P1

AE44

DMI_MTX_IRX_P2

AF46

DMI_MTX_IRX_P3

AH43

B33
B32
G33
F33
E33

C34

AH37
AH36
AN36
AJ35
AH34

N28
M28
G36
E36
K36
H36

B12

B28
B30
B29
C29
A28

T30T30
T31T31
T32T32
T33T33
T34T34

T35T35

CL_CLK0
CL_DATA0
M_PWROK
CL_RST#
+CL_VREF

CLKREQ#_7
MCH_ICH_SYNC#

R1071

R1071

12

56_0402_5%

56_0402_5%

T99T99
T100T100
T101T101
T102T102
T103T103

Title

Title

Title

Cantiga(1/6)-AGTL/DMI/DDR

Cantiga(1/6)-AGTL/DMI/DDR

Cantiga(1/6)-AGTL/DMI/DDR

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA-4595P

LA-4595P

LA-4595P

Date: Sheet

Date: Sheet

Date: Sheet

M_CLK_DDR0 <13>
M_CLK_DDR1 <13>
M_CLK_DDR2 <14>
M_CLK_DDR3 <14>

M_CLK_DDR#0 <13>
M_CLK_DDR#1 <13>
M_CLK_DDR#2 <14>
M_CLK_DDR#3 <14>

DDR_CKE0_DIMMA <13>
DDR_CKE1_DIMMA <13>
DDR_CKE2_DIMMB <14>
DDR_CKE3_DIMMB <14>

DDR_CS0_DIMMA# <13>
DDR_CS1_DIMMA# <13>
DDR_CS2_DIMMB# <14>
DDR_CS3_DIMMB# <14>

M_ODT0 <13>
M_ODT1 <13>
M_ODT2 <14>
M_ODT3 <14>

R328 80.6_0402_1%

R328 80.6_0402_1%

1 2

R329 80.6_0402_1%R329 80.6_0402_1%

1 2

R40 499_0402_1%R40 499_0402_1%

1 2

T29 PADT29 PAD

CLK_MCH_3GPLL <15>
CLK_MCH_3GPLL# <15>

DMI_MTX_IRX_N0 <19>
DMI_MTX_IRX_N1 <19>
DMI_MTX_IRX_N2 <19>
DMI_MTX_IRX_N3 <19>

CL_CLK0 <19>
CL_DATA0 <19>
M_PWROK <19>
CL_RST# <19>

0.1U_0402_16V4Z

0.1U_0402_16V4Z

T36T36
T48T48
T63T63
T64T64

CLKREQ#_7 <15>
MCH_ICH_SYNC# <19>

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

DMI_MRX_ITX_N0 <19>
DMI_MRX_ITX_N1 <19>
DMI_MRX_ITX_N2 <19>
DMI_MRX_ITX_N3 <19>

DMI_MRX_ITX_P0 <19>
DMI_MRX_ITX_P1 <19>
DMI_MRX_ITX_P2 <19>
DMI_MRX_ITX_P3 <19>

DMI_MTX_IRX_P0 <19>
DMI_MTX_IRX_P1 <19>
DMI_MTX_IRX_P2 <19>
DMI_MTX_IRX_P3 <19>

1

C181

C181

2

+VCCP

1

+VCCP

7 49Tuesday, February 17, 2009

7 49Tuesday, February 17, 2009

7 49Tuesday, February 17, 2009

+1.8V

12

R100

R100
1K_0402_1%

1K_0402_1%

12

R99

R99
511_0402_1%

511_0402_1%

of

of

of

1.0

1.0

1.0

5

D D

DDR_A_D[0..63]<13>

C C

B B

DDR_A_D0 DDR_B_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

AJ38

AJ41
AN38
AM38

AJ36

AJ40

AM44
AM42

AN43
AN44
AU40
AT38
AN41
AN39
AU44
AU42
AV39
AY44
BA40
BD43
AV41
AY43
BB41
BC40
AY37
BD38
AV37
AT36
AY38
BB38
AV36

AW36

BD13
AU11
BC11
BA12
AU13
AV13
BD12
BC12

AU10

BA11

AN10

AM11

AM5

AN12

AM13

AJ11

AJ12

BB9
BA9

AV9

BD9
AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6
AT5

AJ9
AJ8

U4D

U4D

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

CANTIGA_1p0

CANTIGA_1p0

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_BS_0
SA_BS_1
SA_BS_2

SA_RAS#
SA_CAS#

SA_WE#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6

SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14

4

DDR_A_BS#0

BD21
BG18
AT25

BB20
BD20
AY20

AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5

AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7
AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8

BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25

DDR_A_BS#1
DDR_A_BS#2

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2

DDR_A_DQS#3

DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

DDR_A_BS#0 <13>
DDR_A_BS#1 <13>
DDR_A_BS#2 <13>

DDR_A_RAS# <13>
DDR_A_CAS# <13>
DDR_A_WE# <13>

DDR_A_DM[0..7] <13>

DDR_A_DQS[0..7] <13>

DDR_A_DQS#[0..7] <13>

DDR_A_MA[0..14] <13>

3

DDR_B_D[0..63]<14>

DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

AK47
AH46
AP47
AP46

AJ46

AJ48
AM48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11

BG8
BH12
BF11

BF8

BG7

BC5

BC6

AY3

AY1

BF6

BF5

BA1

BD3

AV2

AU3

AR3

AN2

AY2

AV1

AP3

AR1

AH1

AM2

AM3

AH3

AL1
AL2
AJ1

AJ3

U4E

U4E

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

CANTIGA_1p0

CANTIGA_1p0

2

DDR_B_BS#0

BC16

SB_BS_0
SB_BS_1
SB_BS_2

SB_RAS#
SB_CAS#

SB_WE#

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6

SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

BB17
BB33

AU17
BG16
BF14

AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2

AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5

AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33

DDR_B_BS#1
DDR_B_BS#2

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14

1

DDR_B_BS#0 <14>
DDR_B_BS#1 <14>
DDR_B_BS#2 <14>

DDR_B_RAS# <14>
DDR_B_CAS# <14>

DDR_B_WE# <14>

DDR_B_DM[0..7] <14>

DDR_B_DQS[0..7] <14>

DDR_B_DQS#[0..7] <14>

DDR_B_MA[0..14] <14>

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

2006/02/13 2006/03/10

2006/02/13 2006/03/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Cantiga(2/6)-DDR2 A/B CH

Cantiga(2/6)-DDR2 A/B CH

Cantiga(2/6)-DDR2 A/B CH

LA-4595P

LA-4595P

LA-4595P

1

1.0

1.0

1.0

of

of

of

8 49Tuesday, February 17, 2009

8 49Tuesday, February 17, 2009

8 49Tuesday, February 17, 2009

5

D D

T38T38

T46T46

T49T49

C C

L32
G32
M32

M33

K33

J33

M29
C44

B43

E37

E38
C41
C40

B37

A37

H47

E46
G40

A40

H48
D45

F40

B40

A41
H38
G37

J37

B42
G38

F37

K37

F25
H25

K25

H24

C31

E32

E28

G28

J28

G29

H32

J32

J29

E29

L29

4

U4C

U4C

L_BKLT_CT RL
L_BKLT_EN
L_CTRL_C LK

L_CTRL_D ATA
L_DDC_CL K
L_DDC_DATA

L_VDD_EN
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK

LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA#_3

LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSA_DATA_3

LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA#_3

LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
LVDSB_DATA_3

TVA_DAC
TVB_DAC
TVC_DAC

TV_RTN

TV_DCONSEL_0
TV_DCONSEL_1

CRT_BLUE

CRT_GREEN

CRT_RED

CRT_IRTN

CRT_DDC_ CLK
CRT_DDC_ DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC

CANTIGA_1p0

CANTIGA_1p0

3

R56 within 500 mils from
pin T37,T36

PEGCOMP

T37

PEG_COMPI

T36

PEG_COMPO

H44

PEG_RX#_0

J46

PEG_RX#_1

L44

PEG_RX#_2

L40

PEG_RX#_3

N41

PEG_RX#_4

P48

PEG_RX#_5

N44

PEG_RX#_6

T43

PEG_RX#_7
PEG_RX#_8

PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8

PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39

H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40

J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46

J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46

LVDS

LVDS

TV

TV

PCI-EXPRESS GRAPHICS

PCI-EXPRESS GRAPHICS

VGA

VGA

R95

R95

1 2

49.9_0402_1%

49.9_0402_1%

PEG_NRX_GTX_N0
PEG_NRX_GTX_N1
PEG_NRX_GTX_N2
PEG_NRX_GTX_N3
PEG_NRX_GTX_N4
PEG_NRX_GTX_N5
PEG_NRX_GTX_N6
PEG_NRX_GTX_N7
PEG_NRX_GTX_N8
PEG_NRX_GTX_N9
PEG_NRX_GTX_N10
PEG_NRX_GTX_N11
PEG_NRX_GTX_N12
PEG_NRX_GTX_N13
PEG_NRX_GTX_N14
PEG_NRX_GTX_N15

PEG_NRX_GTX_P0
PEG_NRX_GTX_P1
PEG_NRX_GTX_P2
PEG_NRX_GTX_P3
PEG_NRX_GTX_P4
PEG_NRX_GTX_P5
PEG_NRX_GTX_P6
PEG_NRX_GTX_P7
PEG_NRX_GTX_P8
PEG_NRX_GTX_P9
PEG_NRX_GTX_P10
PEG_NRX_GTX_P11
PEG_NRX_GTX_P12
PEG_NRX_GTX_P13
PEG_NRX_GTX_P14
PEG_NRX_GTX_P15

PEG_TXN0

C568 0.1U_0402_16V7KC568 0.1U_0402_16V7K

PEG_TXN1

C537 0.1U_0402_16V7KC537 0.1U_0402_16V7K

PEG_TXN2

C538 0.1U_0402_16V7KC538 0.1U_0402_16V7K

PEG_TXN3

C539 0.1U_0402_16V7KC539 0.1U_0402_16V7K

PEG_TXN4

C540 0.1U_0402_16V7KC540 0.1U_0402_16V7K

PEG_TXN5 PEG_NTX_GRX_N5

C541 0.1U_0402_16V7KC541 0.1U_0402_16V7K

PEG_TXN6

C542 0.1U_0402_16V7KC542 0.1U_0402_16V7K

PEG_TXN7

C543 0.1U_0402_16V7KC543 0.1U_0402_16V7K

PEG_TXN8

C544 0.1U_0402_16V7KC544 0.1U_0402_16V7K

PEG_TXN9

C545 0.1U_0402_16V7KC545 0.1U_0402_16V7K

PEG_TXN10

C546 0.1U_0402_16V7KC546 0.1U_0402_16V7K
C547 0.1U_0402_16V7KC547 0.1U_0402_16V7K

PEG_TXN12

C548 0.1U_0402_16V7KC548 0.1U_0402_16V7K

PEG_TXN13

C549 0.1U_0402_16V7KC549 0.1U_0402_16V7K

PEG_TXN14

C550 0.1U_0402_16V7KC550 0.1U_0402_16V7K

PEG_TXN15

C551 0.1U_0402_16V7KC551 0.1U_0402_16V7K

PEG_TXP0

C552 0.1U_0402_16V7KC552 0.1U_0402_16V7K

PEG_TXP1

C553 0.1U_0402_16V7KC553 0.1U_0402_16V7K

PEG_TXP2

C554 0.1U_0402_16V7KC554 0.1U_0402_16V7K

PEG_TXP3

C555 0.1U_0402_16V7KC555 0.1U_0402_16V7K

PEG_TXP4

C556 0.1U_0402_16V7KC556 0.1U_0402_16V7K

PEG_TXP5

C557 0.1U_0402_16V7KC557 0.1U_0402_16V7K

PEG_TXP6

C558 0.1U_0402_16V7KC558 0.1U_0402_16V7K

PEG_TXP7

C559 0.1U_0402_16V7KC559 0.1U_0402_16V7K

PEG_TXP8

C560 0.1U_0402_16V7KC560 0.1U_0402_16V7K

PEG_TXP9

C561 0.1U_0402_16V7KC561 0.1U_0402_16V7K

PEG_TXP10

C562 0.1U_0402_16V7KC562 0.1U_0402_16V7K

PEG_TXP11

C563 0.1U_0402_16V7KC563 0.1U_0402_16V7K

PEG_TXP12

C564 0.1U_0402_16V7KC564 0.1U_0402_16V7K

PEG_TXP13

C565 0.1U_0402_16V7KC565 0.1U_0402_16V7K

PEG_TXP14

C566 0.1U_0402_16V7KC566 0.1U_0402_16V7K

PEG_TXP15

C567 0.1U_0402_16V7KC567 0.1U_0402_16V7K

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

PEG_NRX_GTX_N[0..15]

PEG_NRX_GTX_P[0..15]

+VCC_PEG

PEGCOMP trace width
and spacing is 20/25 mils.

PEG_NRX_GTX_N[0..15] <31>

PEG_NRX_GTX_P[0..15] <31>

PEG_NTX_GRX_N0
PEG_NTX_GRX_N1
PEG_NTX_GRX_N2
PEG_NTX_GRX_N3
PEG_NTX_GRX_N4

PEG_NTX_GRX_N6
PEG_NTX_GRX_N7
PEG_NTX_GRX_N8

PEG_NTX_GRX_N9
PEG_NTX_GRX_N10
PEG_NTX_GRX_N11PEG_TXN11
PEG_NTX_GRX_N12
PEG_NTX_GRX_N13
PEG_NTX_GRX_N14
PEG_NTX_GRX_N15

PEG_NTX_GRX_P0

PEG_NTX_GRX_P1

PEG_NTX_GRX_P2

PEG_NTX_GRX_P3

PEG_NTX_GRX_P4

PEG_NTX_GRX_P5

PEG_NTX_GRX_P6

PEG_NTX_GRX_P7

PEG_NTX_GRX_P8

PEG_NTX_GRX_P9
PEG_NTX_GRX_P10
PEG_NTX_GRX_P11
PEG_NTX_GRX_P12
PEG_NTX_GRX_P13
PEG_NTX_GRX_P14
PEG_NTX_GRX_P15

PEG_NTX_GRX_N[0..15] <31>

PEG_NTX_GRX_P[0..15] <31>

2

1

Strap Pin Table

CFG[2:0] FSB Freq select

CFG[4:3] Rese rved

CFG5 (DMI select)

CFG6

CFG6

CFG7 (Intel Management

Engine Crypto strap)

CFG8

CFG9

(PCIE Graphics Lane Reversal)

CFG10 (PCIE Lookback enable)

CFG11

CFG[13:12] (XOR/ALLZ)

CFG16 (FSB Dynamic ODT)

CFG19 (DMI Lane Reversal)

CFG20 (PCIE/SDVO concurrent)

CFG5<7>

CFG6<7>

CFG7<7>

CFG9<7>

CFG16<7>

000 = FSB 1066MHz
010 = FSB 800MHz
011 = FSB 667MHz
Others = Reserved

0 = DMI x 2
1 = DMI x 4
0 = The iTPM Host Interface is enable

1 = The iTPM Host Interface is disable

0 =(TLS)chiper suite with no confidential ity

1 =(TLS)chiper suite with confidentiality

*

Reserved

0 = Reverse Lane,15->0, 14->1

1 = Normal Operation,Lane Number in order

0 = Enable

1 = Disable

*

Reserved

00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled

ReservedCFG[15:14]

0 = Disabled

1 = Enabled

*

ReservedCFG[18:17]

0 = Normal Operation

(Lane number in Order)

1 = Reverse Lane

0 = Only PCIE or SDVO is operational.

1 = PCIE/SDVO are operating simu.

R66 2.21K_0402_1%~D@R66 2.21K_0402_1%~D@

1 2

R58 2.21K_0402_1%~D@R58 2.21K_0402_1%~D@

1 2

R59 2.21K_0402_1%~D@R59 2.21K_0402_1%~D@

1 2

R55 2.21K_0402_1%~D@R55 2.21K_0402_1%~D@

1 2

R70 2.21K_0402_1%~D@R70 2.21K_0402_1%~D@

1 2

*

*

*

(Default)11 = Normal Operation

*

*

*

CFG[5:16] have internal pullup

R72 4.02K_0402_1%~D@R72 4.02K_0402_1%~D@

CFG19<7>

B B

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CON FIDENTIAL
AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D

AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D

AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMEN T EXCEPT AS AUT HORIZED BY COMPA L ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INF ORMATION IT CONT AINS

DEPARTMEN T EXCEPT AS AUT HORIZED BY COMPA L ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INF ORMATION IT CONT AINS

DEPARTMEN T EXCEPT AS AUT HORIZED BY COMPA L ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INF ORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, IN C.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, IN C.

5

4

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, IN C.

3

2006/02/13 2006/03/10

2006/02/13 2006/03/10

2006/02/13 2006/03/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

CFG20<7>

CFG[19:20] have internal pulldown

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

1 2

R73 4.02K_0402_1%~D@R73 4.02K_0402_1%~D@

1 2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Compal Electronics, Inc.

Cantiga(3/6)-VGA/LVDS/TV

Cantiga(3/6)-VGA/LVDS/TV

Cantiga(3/6)-VGA/LVDS/TV

LA-4595P

LA-4595P

LA-4595P

+3VS

1.0

1.0

9 49Tuesday, February 17, 2009

9 49Tuesday, February 17, 2009

1

9 49Tuesday, February 17, 2009

1.0

5

4

3

2

1

U4H

U4H

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

AXF

AXF

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

SM CK

SM CK

VCC_TX_LVDS

HV

HV

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5

PEG

PEG

VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VCC_DMI_4

DMI

DMI

VTTLF

VTTLF

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8

VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15

VTT

VTT

VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25

VCC_HV_1
VCC_HV_2
VCC_HV_3

VTTLF1
VTTLF2
VTTLF3

73mA

B27

VCCA_CRT_DAC_1

A26

VCCA_CRT_DAC_2

2.68mA

A25

VCCA_DAC_BG

B25

D D

64.8mA

64.8mA

+1.05VS_HPLL

+1.05VS_MPLL

139.2mA

13.2mA

+1.5VS_PEG_BG

+1.5VS

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C175

C175

+1.05VS_PEGPLL

2

720mA

+VCCP

C C

100U_D2E_6.3VM_R15M~D

100U_D2E_6.3VM_R15M~D

R71

R71

1 2

0_0603_5%

0_0603_5%

R50 0_0805_5%

R50 0_0805_5%

1 2

1

C68

C68

+

+

2

+1.05VS_A_SM

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

C82

C82

1

2

4.7U_0805_10V4Z

4.7U_0805_10V4Z

+1.05VS_A_SM_CK

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

C104

C104

1

2

HDMI disable connected to GND

1U_0603_10V4Z~D

1U_0603_10V4Z~D

1

1

C83

C83

2

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C123

C123

TVA 24.15mA
TVB 39.48mA
TVX 24.15mA

C72

C72

2

50mA

58.67mA

C233 0.1U_0402_16 V4Z C233 0.1U_0402_16 V4Z

48.363mA

157.2mA

60.31mA

2

1

50mA

B B

+1.05VS_HPLL

C251 0.1U_0402_16 V4Z C251 0.1U_0402_16 V4Z

2

1

+1.5VS_QDAC

+1.05VS_PEGPLL

VSSA_DAC_BG

F47

VCCA_DPLLA

L48

VCCA_DPLLB

24mA

AD1

VCCA_HPLL

AE1

VCCA_MPLL

J48

VCCA_LVDS

J47

VSSA_LVDS

414uA

AD48

VCCA_PEG_BG

50mA

AA48

VCCA_PEG_PLL

AR20

VCCA_SM_1

AP20

VCCA_SM_2

AN20

VCCA_SM_3

AR17

VCCA_SM_4

AP17

VCCA_SM_5

AN17

VCCA_SM_6

AT16

VCCA_SM_7

AR16

VCCA_SM_8

AP16

VCCA_SM_9

26mA 321.35mA

AP28

VCCA_SM_CK_1

AN28

VCCA_SM_CK_2

AP25

VCCA_SM_CK_3

AN25

VCCA_SM_CK_4

AN24

VCCA_SM_CK_5

AM28

VCCA_SM_CK_NCTF_1

AM26

VCCA_SM_CK_NCTF_2

AM25

VCCA_SM_CK_NCTF_3

AL25

VCCA_SM_CK_NCTF_4

AM24

VCCA_SM_CK_NCTF_5

AL24

VCCA_SM_CK_NCTF_6

AM23

VCCA_SM_CK_NCTF_7

AL23

VCCA_SM_CK_NCTF_8

B24

VCCA_TV_DAC_1

A24

VCCA_TV_DAC_2

A32

VCC_HDA

M25

VCCD_TVDAC

L28

VCCD_QDAC

AF1

VCCD_HPLL

AA47

VCCD_PEG_PLL

M38

VCCD_LVDS_1

L37

VCCD_LVDS_2

CANTIGA_1p0

CANTIGA_1p0

CRTPLLA PEGA SM

CRTPLLA PEGA SM

A LVDS

A LVDS

POWER

POWER

A CK

A CK

TV

TV

HDA

HDA

D TV/CRT

D TV/CRT

LVDS

LVDS

852mA

U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1

B22
B21
A21

124mA

BF21
BH20
BG20
BF20

118.8mA

K47

C35
B35
A35

V48
U48
V47
U47
U46

AH48
AF48
AH47
AG47

A8
L1
AB2

+VCCP

1732mA

456mA

20mils

0.47U_0603_10V7K

0.47U_0603_10V7K

C382

C382

220U_D2_4VY_R15M

220U_D2_4VY_R15M

+V1.05VS_AXF

+1.8V_SM_CK

105.3mA

+VCC_PEG

+1.05VS_DMI

0.47U_0603_10V7K

0.47U_0603_10V7K

C385

C385

1

2

4.7U_0805_10V4Z

1

C370

C370

2

1

C383

C383

2

C65

C65

1

2

4.7U_0805_10V4Z

C384

C384

1

+

+

2

2.2U_0603_10V7K~D

1

2

+3VS

2.2U_0603_10V7K~D

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

C56

C56

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

+1.5VS_QDAC

0.01U_0402_25V7K~N

0.01U_0402_25V7K~N

C97

C97

C98

C98

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

+1.05VS_HPLL

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C388

C388

1

2

+1.05VS_MPLL

1

C63

C63

2

+1.05VS_PEGPLL

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C176

C176

1

2

R69

R69

BLM18PG181SN1_0603~D

BLM18PG181SN1_0603~D

L29

L29

1 2

MBK2012121YZF_0805

MBK2012121YZF_0805

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

C387

C387

2

L9

L9

1 2

0_0603_5%

0_0603_5%

LQH32CNR15M33L_1210~D

LQH32CNR15M33L_1210~D

R74

R74

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

1 2

C62

C62

1

2

L12

L12

1_0402_5%~D

1_0402_5%~D

1 2

BLM21PG221SN1D_0805~D

BLM21PG221SN1D_0805~D

R123

R123

C179

C179

1

10U_0805_4VAM~D

10U_0805_4VAM~D

2

+1.5VS

12

+VCCP

+VCCP

+VCCP

0.47U_0603_10V7K

0.47U_0603_10V7K

C373

C373

C410

C410

0.47U_0603_10V7K

0.47U_0603_10V7K

1

2

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

1

2

+V1.05VS_AXF

10U_0805_4VAM~D

10U_0805_4VAM~D

1

2

+1.8V_SM_CK

1_0402_5%~D

1_0402_5%~D

1

10U_0805_4VAM~D

10U_0805_4VAM~D

2

+VCC_PEG

C117

C117

1

+

+

C95

C95

2

+1.05VS_DMI

1

2

C113

C113

R124

R124

C96

C96

220U_D2_4VY_R15M

220U_D2_4VY_R15M

C116

C116

C389

C389

R112

R112

1 2

0_0805_5%

0_0805_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0603_10V4Z

1U_0603_10V4Z

C69

C69

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C102

C102

1

2

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

2

+VCC_PEG

R101

R101

1 2

0_0805_5%

0_0805_5%

R102

R102

1 2

0_0805_5%

0_0805_5%

PJP13

PJP13
JUMP_43X39

JUMP_43X39

112

+VCCP

2

+VCCP

+1.8V

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

2006/02/13 2006/03/10

2006/02/13 2006/03/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Cantiga(4/6)-PWR

Cantiga(4/6)-PWR

Cantiga(4/6)-PWR

LA-4595P

LA-4595P

LA-4595P

1

1.0

1.0

10 49Tuesday, February 17, 2009

10 49Tuesday, February 17, 2009

10 49Tuesday, February 17, 2009

1.0

of

of

of

5

U4F

AG34
AC34
AB34
AA34

AM33
AK33

AJ33
AG33
AF33

AE33
AC33
AA33

W33

AH28
AF28
AC28
AA28

AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24

AJ23
AH23
AF23

Y34
V34
U34

Y33

V33
U33

T32

U4F

VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34

VCC_35

CANTIGA_1p0

CANTIGA_1p0

+VCCP

D D

0.22U_0402_10V4Z

0.22U_0402_10V4Z

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

220U_D2_4VY_R15M

220U_D2_4VY_R15M

1

C118

C118

1

+

+

C374

C374

2

2

C C

B B

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z

C143

C143

1

2

C120

C120

C119

C119

1

1

2

2

4

Extnal Graphic: 1210.34mA
integrated Graphic: 1930.4mA

VCC CORE

VCC CORE

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6

POWER

POWER

VCC_NCTF_7
VCC_NCTF_8

VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31

VCC NCTF

VCC NCTF

VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44

AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23

+VCCP

+1.8V

3

U4G

U4G

AP33

VCC_SM_1

AN33

VCC_SM_2

C148 330U_V_ 2.5VM

C148 330U_V_ 2.5VM

1

+

+

2

C147

22U_0805_6.3V6M~D

C147

22U_0805_6.3V6M~D

C165

22U_0805_6.3V6M~D

C165

22U_0805_6.3V6M~D

2

1

1

1

2

2

T42PAD T42PAD
T43PAD T43PAD

BH32

VCC_SM_3

BG32

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

C164

C164

BF32
BD32
BC32
BB32
BA32
AY32

AW32

AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29

AW29

AV29
AU29
AT29
AR29
AP29

BA36
BB24
BD16

BB21
AW16
AW13

AT13

AE25

AB25

AA25

AE24

AC24

AA24

AE23

AC23

AB23

AA23

AJ21
AG21
AE21
AC21
AA21

AH20
AF20
AE20
AC20
AB20
AA20

AM15

AL15
AE15

AJ15
AH15
AG15
AF15
AB15
AA15

AN14

AM14

AJ14
AH14

Y26

Y24

Y21

T17
T16

Y15
V15
U15

U14
T14

VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35

VCC_SM_36/NC
VCC_SM_37/NC
VCC_SM_38/NC
VCC_SM_39/NC
VCC_SM_40/NC
VCC_SM_41/NC
VCC_SM_42/NC

6326.84mA

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42

VCC_AXG_SENSE
VSS_AXG_SENSE

3000mA

2

W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16

AV44
BA37
AM40
AV21
AY5
AM10
BB13

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

1

2

VCC SMVCC GFX

VCC SMVCC GFX

VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22

POWER

POWER

VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56

VCC GFX NCTF

VCC GFX NCTF

VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

VCC SM LF

VCC SM LF

1

C70 0.1U_0402_16V4ZC70 0.1U_0402 _16V4Z

1

2

C81 0.22U_0603_10V7KC81 0.22U_0603_10V7K

C67 0.22U_0603_10V7KC67 0.22U_0603_10V7K

C71 0.1U_0402_16V4ZC71 0.1U_0402 _16V4Z

1

1

2

2

C145 1U_0603_10V4ZC145 1U_0603_10V 4Z

C163 1U_0603_10V4ZC163 1U_0603_10V 4Z

C146 0.47U_0402_6.3V6KC14 6 0.47U_0402_6.3V6K

1

1

1

2

2

2

A A

CANTIGA_1p0

CANTIGA_1p0

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

2006/02/13 2006/03/10

2006/02/13 2006/03/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Cantiga(5/6)-PWR/GND

Cantiga(5/6)-PWR/GND

Cantiga(5/6)-PWR/GND

LA-4595P

LA-4595P

LA-4595P

1

1.0

1.0

1.0

of

of

of

11 49Tuesday, February 17, 2009

11 49Tuesday, February 17, 2009

11 49Tuesday, February 17, 2009

5

U4I

U4I

AU48

VSS_1

AR48

VSS_2

AL48

VSS_3

BB47

VSS_4

AW47

VSS_5

AN47

VSS_6

AJ47

VSS_7

AF47

D D

C C

B B

A A

AD47
AB47

BD46
BA46
AY46
AV46
AR46
AM46

BF44
AH44
AD44
AA44

M44

BC43
AV43
AU43
AM43

BG42
AY42
AT42
AN42

AJ42

AE42

BD41
AU41
AM41
AH41
AD41
AA41

M41

BG40
BB40
AV40
AN40

AT39
AM39

AJ39

AE39

BH38
BC38
BA38
AU38
AH38
AD38
AA38

BF37
BB37

AW37

AT37
AN37

AJ37

BG36
BD36
AK15
AU36

N47

G47

V46
R46
P46
H46
F46

Y44
U44
T44

F44

C43

N42

Y41
U41
T41

G41
B41

H40
E40

N39

B39

Y38
U38
T38

F38
C38

H37
C37

Y47
T47

L47

J43

L42

L39

J38

VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

CANTIGA_1p0

CANTIGA_1p0

VSS

VSS

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199

4

AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6

3

U4J

U4J

BG21

VSS_199

L12

VSS_200

AW21

VSS_201

AU21

VSS_202

AP21

VSS_203

AN21

VSS_204

AH21

VSS_205

AF21

VSS_206

AB21

VSS_207

R21

VSS_208

M21

VSS_209

J21

VSS_210

G21

VSS_211

BC20

VSS_212

BA20

VSS_213

AW20

VSS_214

AT20

VSS_215

AJ20

VSS_216

AG20

VSS_217

Y20

VSS_218

N20

VSS_219

K20

VSS_220

F20

VSS_221

C20

VSS_222

A20

VSS_223

BG19

VSS_224

A18

VSS_225

BG17

VSS_226

BC17

VSS_227

AW17

VSS_228

AT17

VSS_229

BA16

AU16
AN16

BG15

AC15

W15

BG14

AA14

BG13

BC13
BA13

AN13

AJ13

AE13

BF12
AV12
AT12

AM12

AA12

BD11
BB11
AY11
AN11
AH11

BG10

AV10
AT10

AJ10
AE10
AA10

AM9

R17
M17
H17
C17

N16
K16
G16
E16

A15

C14

N13

G13
E13

A12

Y11
N11
G11
C11

M10
BF9
BC9
AN9

AD9

BH8
BB8
AV8
AT8

L13

J12

G9

B9

VSS_230
VSS_231
VSS_232
VSS_233

VSS_235

VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252

VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273

VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296

CANTIGA_1p0

CANTIGA_1p0

VSS

VSS

VSS NCTF

VSS NCTF

VSS SCB

VSS SCB

NC

NC

VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325

VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350

VSS_351
VSS_352
VSS_353
VSS_354

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16

VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5

NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42

2

AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4

BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1

U24
U28
U25
U29

AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17

BH48
BH1
A48
C1
A3

E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48

1

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

2006/02/13 2006/03/10

2006/02/13 2006/03/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Cantiga(6/6)-PWR/GND

Cantiga(6/6)-PWR/GND

Cantiga(6/6)-PWR/GND

LA-4595P

LA-4595P

LA-4595P

1

1.0

1.0

1.0

of

of

of

12 49Tuesday, February 17, 2009

12 49Tuesday, February 17, 2009

12 49Tuesday, February 17, 2009

5

DDR_A_DQS#[0..7]<8>

DDR_A_D[0..63]<8>

DDR_A_DM[0..7]<8>

DDR_A_DQS[0..7]<8>

DDR_A_MA[0..13]<8>

D D

Layout Note:
Place near JDIM1

+1.8V

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

1

2

C106

C106

C124

C124

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C125

C125

RP14

RP14

RP13

RP13

RP7

RP7

RP6

RP6

RP5

RP5

RP1

RP1

R96 56_0402_5%

R96 56_0402_5%

2.2U_0603_6.3V6K

C149

C149

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C126

C126

1 4
2 3

56_0404_4P2R_5%

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

56_0404_4P2R_5%

2 3
1 4

56_0404_4P2R_5%

56_0404_4P2R_5%

1 2

C105

C105

1

2

Layout Note:

C C

Place one cap close to every 2 pullup
resistors terminated to +0.9V

+0.9VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

B B

DDR_A_MA5
DDR_A_MA8

DDR_A_MA1
DDR_A_MA3

DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_BS#0

A A

DDR_A_MA10

DDR_A_CAS#
DDR_A_WE#

DDR_CS1_DIMMA#
M_ODT1

DDR_CKE1_DIMMA

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

C166

C166

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C127

C127

+0.9VS

5

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C169

C169

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C150

C150

C151

C151

RP22 56_0404_4P2R_5%RP22 56_0404_4P2R_5%

DDR_A_MA12

14

DDR_CKE0_DIMMA

23

RP17 56_0404_4P2R_5%RP17 56_0404_4P2R_5%

DDR_A_MA7

14

DDR_A_MA6

23

RP15 56_0404_4P2R_5%RP15 56_0404_4P2R_5%

DDR_A_MA9

14

DDR_A_BS#2

23

RP16 56_0404_4P2R_5%RP16 56_0404_4P2R_5%

DDR_A_MA4

14

DDR_A_MA2

23

RP8 56_0404_4P2R_5%RP8 56_0404_4P2R_5%

DDR_A_MA0

14

DDR_A_BS#1

23

RP2 56_0404_4P2R_5%RP2 56_0404_4P2R_5%

M_ODT0

14

DDR_A_MA13

23

RP23 56_0404_4P2R_5%RP23 56_0404_4P2R_5%

DDR_A_MA14

14

DDR_A_MA11

23

C154

C154

1

2

1

2

C167

C167

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C130

C130

C131

C131

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C107

C107

C128

C128

330U 2.5V Y D2

330U 2.5V Y D2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C108

C108

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C129

C129

C152

C152

Layout Note:
Place these resistor
closely JP41,all
trace length Max=1.5"

4

1

C84

C84

+

+

@

@

2

DDR_CKE0_DIMMA<7>

DDR_A_BS#2<8>

DDR_A_BS#0<8>

DDR_A_WE#<8>

DDR_A_CAS#<8>

DDR_CS1_DIMMA#<7>

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C153

C153

1

1

2

2

C234

C234

C168

C168

M_ODT1<7>

ICH_SM_DA<14,15,19>

ICH_SM_CLK<14,15,19>

+3VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+1.8V

DDR_A_D4
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D14

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D29
DDR_A_D24

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS#2

DDR_A_MA12

DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1

DDR_A_D37
DDR_A_D36

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D35
DDR_A_D34

DDR_A_D40
DDR_A_D44

DDR_A_DM5

DDR_A_D41
DDR_A_D46

DDR_A_D49
DDR_A_D48

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D54
DDR_A_D50

DDR_A_D61
DDR_A_D60

DDR_A_DM7

DDR_A_D59
DDR_A_D58

ICH_SM_DA
ICH_SM_CLK

1

C58

C58

2

3

1

C59

C59

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2

JDIM2

JDIM2

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_ASOA426-M2RN-7F

FOX_ASOA426-M2RN-7F

SO-DIMM A

REVERSE

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

BA1
RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SA0

SA1

2

1

Close to VREF pins of SO-DIMM

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2.2U_0805_16V4Z

2

DDR_A_D5

4

DDR_A_D0

6
8

DDR_A_DM0

10
12

DDR_A_D6

14

DDR_A_D7

16
18

DDR_A_D13

20

DDR_A_D12

22
24

DDR_A_DM1

26
28

M_CLK_DDR0

30

M_CLK_DDR#0

32
34

DDR_A_D11

36

DDR_A_D10DDR_A_D15

38
40

42

DDR_A_D20

44

DDR_A_D21

46
48
50

NC

A11

A7
A6

A4
A2
A0

S0#

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_A_DM2

DDR_A_D23
DDR_A_D22

DDR_A_D28
DDR_A_D25

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D31
DDR_A_D30

DDR_CKE1_DIMMA

DDR_A_MA14

DDR_A_MA11

DDR_A_MA7DDR_A_MA9

DDR_A_MA6

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#DDR_A_WE#

M_ODT0
DDR_A_MA13

DDR_A_D32
DDR_A_D33

DDR_A_DM4

DDR_A_D39
DDR_A_D38

DDR_A_D45
DDR_A_D47

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D43
DDR_A_D42

DDR_A_D52
DDR_A_D53

M_CLK_DDR1
M_CLK_DDR#1

DDR_A_DM6

DDR_A_D51
DDR_A_D55

DDR_A_D57
DDR_A_D56

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D62
DDR_A_D63

12

R31

R31

R32

R32

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

12

2.2U_0805_16V4Z

C201

C201

1

2

M_CLK_DDR0 <7>
M_CLK_DDR#0 <7>

PM_EXTTS#0 <7>

DDR_CKE1_DIMMA <7>

DDR_A_MA14 <8>

DDR_A_BS#1 <8>
DDR_A_RAS# <8>
DDR_CS0_DIMMA# <7>

M_ODT0 <7>

M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>

C220

C220

1

2

+V_DDR_MCH_REF <7,14>

Bottom side

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/1/15 2008/1/15

2007/1/15 2008/1/15

2007/1/15 2008/1/15

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

DDR2 SO-DIMM I

DDR2 SO-DIMM I

DDR2 SO-DIMM I

LA-4595P

LA-4595P

LA-4595P

1.0

1.0

1.0

of

of

of

13 49Tuesday, February 17, 2009

13 49Tuesday, February 17, 2009

13 49Tuesday, February 17, 2009

1

5

DDR_B_DQS#[0..7]<8>

DDR_B_D[0..63]<8>

DDR_B_DM[0..7]<8>

DDR_B_DQS[0..7]<8>

DDR_B_MA[0..13]<8>

D D

Layout Note:
Place near JDIM2

+1.8V

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

C160

C160

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C156

C156

C135

C135

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

5

2.2U_0603_6.3V6K

C138

C138

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C157

C157

+0.9VS

RP24 56_0404_4P2R_5%RP24 56_0404_4P2R_5%

RP26 56_0404_4P2R_5%RP26 56_0404_4P2R_5%

RP19 56_0404_4P2R_5%RP19 56_0404_4P2R_5%

RP21 56_0404_4P2R_5%RP21 56_0404_4P2R_5%

RP20 56_0404_4P2R_5%RP20 56_0404_4P2R_5%

RP4 56_0404_4P2R_5%RP4 56_0404_4P2R_5%

RP25

RP25

56_0404_4P2R_5%

56_0404_4P2R_5%

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C177

C177

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C170

C170

DDR_B_MA9

14
23

DDR_B_MA14

14

DDR_B_MA11

23

DDR_B_MA5

14

DDR_B_MA8

23

DDR_B_MA7

14

DDR_B_MA6

23

DDR_B_MA4

14

DDR_B_MA2

23

DDR_B_MA13

14

M_ODT2

23

DDR_B_BS#2

14

DDR_CKE2_DIMMB

23

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C132

C132

C109

C109

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

1

2

2

C171

C171

2

C111

C111

C136

C136

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

C C

+0.9VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

B B

DDR_B_MA1
DDR_B_MA3 DDR _B_MA12

DDR_B_MA10
DDR_B_BS#0

DDR_B_BS#1
DDR_B_MA0

DDR_B_RAS#
DDR_CS2_DIMMB#

A A

DDR_B_CAS#
DDR_B_WE#

DDR_CS3_DIMMB#
M_ODT3

DDR_CKE3_DIMMB

C112

C112

1

2

1

2

C110

C110

C139

C139

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C134

C134

RP18

RP18

RP10

RP10

RP12

RP12

RP11

RP11

RP9

RP9

RP3

RP3

R335 56_0402_5%

R335 56_0402_5%

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

2 3
1 4

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C133

C133

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C158

C158

4

330U 2.5V Y D2

330U 2.5V Y D2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Layout Note:
Place these resistor
closely JP42,all
trace length Max=1.5"

1

C189

C189

C155

C155

1

+

+

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C172

C172

C137

C137

4

3

+1.8V

JDIM1

JDIM1

1

VREF

3

DDR_B_D0
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D17
DDR_B_D20

DDR_B_DQS#2

@

@

DDR_CKE2_DIMMB<7>

DDR_B_BS#2<8>

DDR_B_BS#0<8>

DDR_B_CAS#<8>

DDR_CS3_DIMMB#<7>

1

2

C159

C159

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

ICH_SM_DA<13,15,19>

ICH_SM_CLK<13,15,19>

Issued Date

Issued Date

Issued Date

M_ODT3<7>

DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D28
DDR_B_D25

DDR_B_DM3

DDR_B_D30
DDR_B_D31

DDR_CKE2_DIMMB

DDR_B_BS#2

DDR_B_MA12
DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_DM5

DDR_B_D42
DDR_B_D43

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D51
DDR_B_D50

DDR_B_D56
DDR_B_D61

DDR_B_DM7

DDR_B_D59
DDR_B_D58

ICH_SM_DA
ICH_SM_CLK

+3VS

C61

C61

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C60

C60

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2

2

2007/1/15 2008/1/15

2007/1/15 2008/1/15

2007/1/15 2008/1/15

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_AS0A426-NARN-7F~N

FOX_AS0A426-NARN-7F~N

SO-DIMM B
REVERSE

Bottom side

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

BA1
RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

SA1

NC

A11

A7
A6

A4
A2
A0

S0#

NC

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

2

+V_DDR_MCH_REF

DDR_B_D5
DDR_B_D4

DDR_B_DM0

DDR_B_D6
DDR_B_D7

DDR_B_D12
DDR_B_D13

DDR_B_DM1

M_CLK_DDR2
M_CLK_DDR#2

DDR_B_D14
DDR_B_D15

DDR_B_D21
DDR_B_D16

DDR_B_DM2

DDR_B_D22
DDR_B_D23

DDR_B_D29
DDR_B_D24

DDR_B_DQS#3
DDR_B_DQS3

DDR_B_D26
DDR_B_D27

DDR_CKE3_DIMMB

DDR_B_MA14

DDR_B_MA11

DDR_B_MA7

DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B_D36
DDR_B_D37

DDR_B_DM4

DDR_B_D39
DDR_B_D38

DDR_B_D44
DDR_B_D45

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D46
DDR_B_D47

DDR_B_D52
DDR_B_D53

M_CLK_DDR3
M_CLK_DDR#3

DDR_B_DM6

DDR_B_D54
DDR_B_D55

DDR_B_D60
DDR_B_D57

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

10K_0402_5%

10K_0402_5%

2

1

Close to VREF pins of SO-DIMM

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

1

1

C222

C222

C221

C221

2

2

M_CLK_DDR2 <7>
M_CLK_DDR#2 <7>

PM_EXTTS#1 <7>

DDR_CKE3_DIMMB <7>

DDR_B_MA14 <8>

DDR_B_BS#1 <8>
DDR_B_RAS# <8>
DDR_CS2_DIMMB# <7>DDR_B_WE#<8>

M_ODT2 <7>

M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>

R33

R33

1 2

12

10K_0402_5%

10K_0402_5%

R34

R34

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

+3VS

Compal Electronics, Inc.

DDR2 SO-DIMM II

DDR2 SO-DIMM II

DDR2 SO-DIMM II

LA-4595P

LA-4595P

LA-4595P

+V_DDR_MCH_REF <7,13>

1

1.0

1.0

1.0

of

of

of

14 49Tuesday, February 17, 2009

14 49Tuesday, February 17, 2009

14 49Tuesday, February 17, 2009

5

PCI

SRC

CPU

CLKSEL1

0

FSA

CLKSEL0

MHz

266

MHz

1000

MHz

MHz

33.30

14.318 96.0 48.0

DOT_96
MHz

FSC FSB REF

CLKSEL2

0 1000 13 3 33.31 14.318 96.0 48.0

0 1001 20 0 33.30 14.318 96.0 48.0

D D

0 1001 16 6 33.31 14.318 96.0 48.0

1 1000 33 3 33.30 14.318 96.0 48.0

1 1000 10 0 33.31 14.318 96.0 48.0

1 1001 40 0 33.30 14.318 96.0 48.0

1 1 1

R37

R983

R983

FSA

1 2

2.2K_0402_5%

2.2K_0402_5%

CPU_BSEL0<5>

C C

R37

1 2

1K_0402_1%

1K_0402_1%

Reserved

MCH_CLKSEL0 <7>

For SED TEST

CLK_14M_ICH<19>

R39

CPU_BSEL1

CPU_BSEL1<5>

R39

1 2

1K_0402_1%

1K_0402_1%

SB, MINI PCI

MCH_CLKSEL1 <7>

CLK_DEBUG_PORT<23>
CLK_PCI_EC<27>
CLK_PCI_TPM<28>
PCI_CLK<17>

For SED TEST

R47

B B

CPU_BSEL2<5>

FSC

R1016

R1016

1 2

10K_0402_5%

10K_0402_5%

R47

1 2

1K_0402_1%

1K_0402_1%

MCH_CLKSEL2 <7>

VGA (Discrete)

CK_PWRGD<19>

4

USB
MHz

NB

CPU

22P_0402_50V8J

22P_0402_50V8J

ICH_SM_DA<13,14,19>

ICH_SM_CLK<13,14,19>

2

C120622P_0402_50V8J@C120622P_0402_50V8J

C120522P_0402_50V8J@C120522P_0402_50V8J

1

@

CLK_PCIE_VGA<31>
CLK_PCIE_VGA#<31 >

Routing the trace at least 10mil

*

C1196

C1196

22P_0402_50V8J

22P_0402_50V8J

CLK_MCH_BCLK#<7>
CLK_MCH_BCLK<7>
CLK_CPU_BCLK#<4>
CLK_CPU_BCLK<4>

C1209

@C1209

@

12

R991 33_0402_1%R991 33_0402_1%

1 2

R1001 33_0402_1%R1001 33_0402_1%

1 2

R1004 33_0402_1%R1004 33_0402_1%

1 2

R1006 33_0402_1%

R1006 33_0402_1%

1 2

R1008 33_0402_1%R1008 33_0402_1%

2

2

C120722P_0402_50V8J@ C120722P_0402_50V8J

1

1

@

CLK_48M_ICH<19>

CLKREQ#_7<7>

C120822P_0402_50V8J@C120822P_0402_50V8J

@

1 2

2

1

@

C1251

CLK_XTAL_OUT

CLK_XTAL_IN

14.31818MHZ_16P

14.31818MHZ_16P
R986

R986

0_0402_5%

0_0402_5%

1 2

Y7

Y7

12

2

2

1

T120PAD T120PAD

12

22P_0402_50V8J

22P_0402_50V8J

R1013 33_0402_1%R1013 33_0402_1%

R1024 0_0402_5%R1024 0_0402_5%
R1026 0_0402_5%R1026 0_0402_5%

C1197

C1197

22P_0402_50V8J

22P_0402_50V8J

1

R976 0_0402_5%

R976 0_0402_5%

1 2

R978 0_0402_5%

R978 0_0402_5%
R980 0_0402_5%

R980 0_0402_5%
R982 0_0402_5%

R982 0_0402_5%

ICH_SM_DA
ICH_SM_CLK

@C1251

@

1 2

12
12

+3VS_CK505

CK_PWRGD
CPU_BSEL1

CLK_XTAL_OUT
CLK_XTAL_IN

FSC

PCI2_TME
R_CLK_PCI_EC
27_SEL
ITP_EN

1 2

1 2

R51 475_0402_1%~DR51 475_0402_1%~D

12
12

3

R_MCH_BCLK#
R_MCH_BCLK
R_CPU_BCLK#
R_CPU_BCLK

U55

U55

1

CKPWRGD/PD#

2

FS_B/TEST_MODE

3

VSS_REF

4

XTAL_OUT

5

XTAL_IN

6

VDD_REF

7

REF_0/FS_C/TEST_

8

REF_1

9

SDA

10

SCL

11

NC

12

VDD_PCI

13

PCI_1

14

PCI_2

15

PCI_3

16

PCI_4/SEL_LCDCL

17

PCIF_5/ITP_EN

18

VSS_PCI

+3VS_CK505

FSA

R_CLKREQ#_7

+1.05VS_CK505

R_MCH_DREFCLK
R_MCH_DREFCLK#

+3VS_CK505

R971

R971

1 2

+3VS

0_0805_5%

0_0805_5%

+1.05VS_CK505

+3VS_CK505

71

68

73

72

70

69

GND

CPU_0

CPU_0#

VSS_CPU

VDD_CPU

VDD_4819USB_0/FS_A20USB_1/CLKREQ_A#21VSS_4822VDD_IO23SRC_0/DOT_9624SRC_0#/DOT_96#25VSS_IO26VDD_PLL327LCDCLK/27M28LCDCLK#/27M_SS29VSS_PLL330VDD_PLL3_IO31SRC_232SRC_2#33VSS_SRC34SRC_335SRC_3#

61

64

67

66

62

65

63

CPU_1

CPU_1#

CLKREQ_7#

VDD_CPU_IO

VDD_SRC_IO

SRC_8/CPU_ITP

SRC_8#/CPU_ITP#

1

C1189

C1189

10U_0805_10V4Z

10U_0805_10V4Z

2

0905 Connect to +VCCP

MEDIA_REQ#32

57

60

58

59

SRC_7

SRC_7#

VSS_SRC

CLKREQ_6#

SSCDREFCLK#
SSCDREFCLK

1

C1190

C1190

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

+VCCP

R972

R972

1 2

0_0805_5%

0_0805_5%

EXPCARD_REQ#16
R_PCIE_EXPR
R_PCIE_EXPR#

56

55

SRC_6

SRC_6#

VDD_SRC

36

+1.05VS_CK505

R979 0_0402_5%

R979 0_0402_5%
R981 0_0402_5%

R981 0_0402_5%

+3VS_CK505

PCI_STOP#

CPU_STOP#

VDD_SRC_IO

SRC_10#

SRC_10

CLKREQ_10#

SRC_11

SRC_11#

CLKREQ_11#

SRC_9#

SRC_9

CLKREQ_9#

VSS_SRC

CLKREQ_4#

SRC_4#

SRC_4

VDD_SRC_IO

CLKREQ_3#

S IC ICS9LPRS387AKLFT MLF 72P CLK GEN

S IC ICS9LPRS387AKLFT MLF 72P CLK GEN

R_PCIE_ICH#
R_PCIE_ICH

R_MCH_3GPLL#
R_MCH_3GPLL

2

1

C1191

C1191

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

Place close to U55

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C1198

C1198

2

10U_0805_10V4Z

10U_0805_10V4Z

R1019 0_0402_5%

R1019 0_0402_5%

1 2

R1021 0_0402_5%

R1021 0_0402_5%

1 2

1 2
1 2

+1.05VS_CK505

H_STP_PCI#

54

H_STP_CPU#

53
52

R_CLK_WWA N#

51

R_CLK_WWA N

50

WWAN_RE Q#10

49

R_PCIE_SATA

48

R_PCIE_SATA#

47

R_CLKSATAREQ#

46

R_CLK_PCIE_LAN#

45

R_CLK_PCIE_LAN

44

GLAN_REQ#9

43
42

WLAN_REQ#4

41

R_CLK_PCIE_MCARD#

40

R_CLK_PCIE_MCARD

39
38
37

R1010 0_0402_5%

R1010 0_0402_5%

1 2

R1012 0_0402_5%

R1012 0_0402_5%

1 2

R1015 0_0402_5%R1015 0_0402_5%

1 2

R1018 0_0402_5%R1018 0_0402_5%

1 2

R1067 33_0402_1%R1067 33_0402_1%

1 2

R1195 33_0402_1%R1195 33_0402_1%

1 2

1

C1192

C1192

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1

1

2

C1200

C1200

C1199

C1199

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

MEDIA_REQ#32 <30>
CLK_PCIE_Media <30>
CLK_PCIE_Media# <30>

EXPCARD_REQ#16 <26>
CLK_PCIE_EXPR <26>
CLK_PCIE_EXPR# <26>

H_STP_PCI# <19>

H_STP_CPU# <19>

R988 0_0402_5%

R988 0_0402_5%

1 2

R989 0_0402_5%

R989 0_0402_5%

1 2

R992 0_0402_5%R9 92 0_0402_5%

1 2

R994 0_0402_5%R9 94 0_0402_5%

1 2

R56 475_0402_1%~DR56 475_0402_1%~D

1 2

R996 0_0402_5%R9 96 0_0402_5%

1 2

R997 0_0402_5%R9 97 0_0402_5%

1 2

R1005 0_0402_5%R1005 0_0402_5%

1 2

R1007 0_0402_5%R1007 0_0402_5%

1 2

1

C1193

C1193

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

10U_0805_10V4Z

10U_0805_10V4Z

1

C1201

C1201

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

CardBus OZ888

Express Card

CPU_STP

CLK_PCIE_ICH# <19>
CLK_PCIE_ICH <19>

CLK_MCH_3GPLL# <7>
CLK_MCH_3GPLL <7>

CLK_NVSS_27M <31>
CLK_NV_27M <31>

1

C1194

C1194

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C1202

C1202

C1203

C1203

2

CLK_PCIE_WW AN# <23>
CLK_PCIE_WW AN <23>

WWAN_RE Q#10 <23>
CLK_PCIE_SATA <18>
CLK_PCIE_SATA# <18>
CLKSATAREQ# <19>
CLK_PCIE_LAN# <21>
CLK_PCIE_LAN <21>
GLAN_REQ#9 <21>

WLAN_REQ#4 <23>
CLK_PCIE_MCARD# <23>
CLK_PCIE_MCARD <23>

ICH

NB_3GPLL

VGA_27M (DIS)

1

+1.05VS_CK505

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C1195

C1195

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

C1204

C1204

MiniCard_WWAN

ICH_SATA

GLAN

MiniCard_WLAN

ITP_EN

27_SEL

PCI2_TME

A A

12

R1032

R1032
10K_0402_5%

10K_0402_5%

5

0 = SRC8/SRC8#

*

1 = ITP/ITP#

0 = Enable DOT96 & SRC1(UMA)

1 = Enable SRC0 & 27MHz(DIS)

*

0 = Overclocking of CPU and SRC Allowed

1 = Overclocking of CPU and SRC NOT allowed

*

+3VS_CK505

12

R1030

R1030
10K_0402_5%

10K_0402_5%

ITP_EN 27_SEL

+3VS_CK505

1 2

PCI2_TME

R1031

R1031
10K_0402_5%

10K_0402_5%

EXPCARD_REQ#16

WWAN_RE Q#10

CLKSATAREQ#

GLAN_REQ#9

WLAN_REQ#4

CLKREQ#_7

MEDIA_REQ#32

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

2006/02/13 2006/03/10

2006/02/13 2006/03/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Clock Generator CK505

Clock Generator CK505

Clock Generator CK505

1 2

R90 10K_0402_5%R90 10K_0402_5%

1 2

R89 10K_0402_5%R89 10K_0402_5%

1 2

R88 10K_0402_5%R88 10K_0402_5%

1 2

R87 10K_0402_5%R87 10K_0402_5%

1 2

R85 10K_0402_5%R85 10K_0402_5%

1 2

R60 10K_0402_5%R60 10K_0402_5%

1 2

R80 10K_0402_5%R80 10K_0402_5%

LA-4595P

LA-4595P

LA-4595P

1

+3VS

1.0

1.0

1.0

of

15 49Tuesday, February 17, 2009

of

15 49Tuesday, February 17, 2009

of

15 49Tuesday, February 17, 2009