Acer Aspire 4735, 4736z, Compal LA-4491P, Aspire 4736, Aspire 4935 Schematics

A

B

C

D

E

1 1

Compal Confidential

2 2

KAL90 M/B Schematics Document

Intel Penryn Processor with Cantiga + DDRII + ICH9M

3 3

2008-10-30

REV:1.0

4 4

A

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/03/28 2008/09/20

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,A4491

401597

152Thursday, October 30, 2008

E

of

C

A

B

C

D

E

Compal Confidential

Model Name : KAL90 File Name : LA-4491P

1 1

HDMI Conn.

page 24

Fan Control

LCD Conn.

page 22

page 40

CRT Conn.

page 23

LVDS

LVDSTMDS

PCI-Express

Card Reader JMB385

page 30

2 2

LAN(GbE)

ATHEROS AR8121

page 31

MINI Card x2

WLAN, Robson2

page 33

New Card Socket

page 34

VGA

page 17,18,19,20,21

port 2

16X

PCI-Express

port 1 port 0

Intel Penryn Processor

uPGA-478 Package

(Socket P)

H_A#(3..35) H_D#(0..63)

667/800/1066MHz

page 4,5,6

FSB

Intel Cantiga

uFCBGA-1329

page 7,8,9,10,11,12,13

DMI

C-Link

Intel ICH9-M

S-ATA

BGA-676

page 25,26,27,28

Thermal Sensor

EMC 1402

page 4

Memory BUS(DDRII)

Dual Channel

1.8V DDRII 533/667

USB conn x3

USB port 0, 2, 5

page 33 page 22

3.3V 48MHz

3.3V 24.576MHz/48Mhz

USB

GMCH HDA

page 08

Clock Generator

ICS9LPRS387

page 16

200pin DDRII-SO-DIMM X2

BANK 0, 1, 2, 3

Bluetooth Conn

page 34

MDC 1.5 Conn

page 37

HD Audio

page 14,15

CMOS Camera

HDA Codec

ALC888S-VC

page 38

LS-4494P

Finger Print

AES1610

VGA HDA

page 18

RJ45

page 32

3 3

ESATA Conn.

page 34

CDROM Conn.

page 29

SATA HDD Conn.

page 29

LPC BUS

ENE KB926

page 35

Audio AMP

page 39

Phone Jack x3

page 39

RTC CKT.

page 37

Power On/Off CKT.

page 37

DC/DC Interface CKT.

page 44

Power Circuit DC/DC

4 4

page 44,45,46,47,48 ,49,50,51

POWER SW

Page 42

A

LS-4493P

Media/B Conn.

LS-4498P

FUN Conn.

LS-4492P

E_KEY/B Conn.

LS-4495P

USB/B Conn.

USB port 1

Touch Pad

page 36

EC I/O Buffer

page 36

CIR

page 37

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Int.KBD

page 36

BIOS

page 36

Compal Secret Data

2008/03/28 2008/09/20

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,A4491

401597

of

252Thursday, October 30, 2008

E

C

A

Voltage Rails

Power Plane Description

VIN

1 1

2 2

B+ +CPU_CORE +0.9VS 0.9V switched power rail for DDR terminator +1.05VS +1.25VS 1.25V switched power rail ON OFF OFF +1.5V 1.5V power rail for HDA ON ON OFF +1.5VS +1.8V +1.8VS 1.8V switched power rail +1.1VS +3VALW +3V +3V_LAN +3VS +5VALW +5VS +VSB VSB always on power rail ON ON* +RTCVCC RTC power +VGA_CORE

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Adapter power supply (19V) AC or battery power rail for power circuit. Core voltage for CPU

1.05V switched power rail

1.5V switched power rail

1.8V power rail for DDR

1.1V switched power rail

3.3V always on power rail

3.3V power rail for SB

3.3V power rail for LAN

3.3V switched power rail 5V always on power rail 5V switched power rail

Core voltage for GPU

External PCI Devices

Device IDSEL# REQ#/GNT# Interrupts

EC SM Bus1 address

3 3

Device

Smart Battery MEDIA CONSOLE

Address Address

1010 000X b

EC SM Bus2 address

ADI ADT7421

NB9M THERMAL SENSOR

S1 S3 S5

N/A N/A N/A

ON OFF ON OFF ON OFF OFF

ON OFF OFF ON ON ON ON ON ON ON ONXX ON ON

ON ON ON OFF OFF

Device

B

N/AN/AN/A OFF OFF

ON

OFF OFF

OFF

ON ON*

OFF

ON*

ON

OFFON

OFF

ONON

1001 100X b0001 011X b

C

STATE

SIGNAL

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SLP_S1# SLP_S3#

SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH HIGH HIGH HIGH

LOW

LOW LOW LOW LOW

HIGH

LOWLOWLOW

D

HIGHHIGHHIGH

HIGH

ON

OFF

ON ON

ON

OFF

ON

Board ID / SKU ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0 1 2 3 4 5 6 7NC

100K +/- 5%Ra/Rc/Re

Rb / Rd / Rf V min

0

8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

V typ

AD_BID

V

AD_BID

0 V 0 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

2.200 V

3.300 V

2.341 V

3.300 V

max

BOARD ID Table BTO Option Table

Board ID

0 1 2 3 4 5 6 7

PCB Revision

0.1

0.2

0.3

1.0 1A

BTO Item BOM Structure

JAL90@JAL90 JAW50@JAW50

UMA

GM@

JAL90GM@JAL90-UMA JAW50 Discrete Discrete ALC888VC ALC888VB

GLPM@

PM@

888VC@

888VB@ AR8121 8121@ AR8112 8112@ ALC268

268@

E

LOW

OFF

BOM Configuration Table

ICH9M SM Bus address

Device

Clock Generator (ICS9LPRS387, SLG8SP556V)

DDR DIMM0 DDR DIMM2

4 4

Address

1101 001Xb

1001 000Xb 1001 010Xb

A

B

Project BOM Configuration KAL90-UMA

XXXXXXXXXX:JAL90GM@/JAL90@/GM@/888VC@/8121@/ESATA@

KAL90-Dis XXXXXXXXXX:PM@/JAL90@/GLPM@/888VC@/8121@/ESATA@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/03/28 2008/09/20

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,A4491

401597

of

352Thursday, October 30, 2008

E

C

5

4

3

2

1

H_A#[3..35]<7>

H_REQ#[0..4]<7>

H_RS#[0..2]<7>

D D

C C

B B

BSEL2 BSEL1 BSEL0 BCLK

000266 010200

A A

H_A#[3..35] H_REQ#[0..4] H_RS#[0..2]

JCPU1A

AA4 AB2 AA3

D22

J4 L5 L4 K5

M3

N2

J1 N3 P5 P2 L2 P4 P1 R1

M1

K3 H2 K2

J3 L1

Y2 U5 R3

W6

U4 Y5 U1 R4 T5 T3

W2 W5

Y4 U2 V4

W3

V1 A6

A5 C4

D5 C6 B4 A3

M4

N5 T2 V3 B2 D2

D3 F6

16601

JCPU1A

A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]#

REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]#

A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]#

A20M# FERR# IGNNE#

STPCLK# LINT0 LINT1 SMI#

RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09]

Penryn

CONN@

ADDR GROUP_0

ADS# BNR#

BPRI#

DEFER#

DRDY# DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]# RS[1]# RS[2]#

TRDY#

HIT#

HITM#

ADDR GROUP_1

BPM[0]# BPM[1]# BPM[2]# BPM[3]#

PRDY# PREQ#

TCK

TDI TDO TMS

TRST#

DBR#

XDP/ITP SIGNALS

THERMAL

PROCHOT#

THERMDA THERMDC

ICH

THERMTRIP#

H CLK

BCLK[0] BCLK[1]

RESERVED

H_PROCHOT#

H1 E2 G5

H5 F21 E1

F1

H_IERR#

D20 B3

H4

H_RESET#

C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3 G2

G6 E4

AD4 AD3 AD1 AC4 AC2

XDP_BPM#5

AC1

XDP_TCK

AC5

XDP_TDI

AA6 AB3

XDP_TMS

AB5

XDP_TRST#

AB6

XDP_DBRESET#

C20

H_PROCHOT#

D21

H_THERMDA

A24

H_THERMDC

B25 C7

A22 A21

Layout Note: H_THERMDA&H_THERMDC Trace / Space = 10 / 10 mil

+1.05VS

12

R17

R17 56_0402_5%

56_0402_5%

B

2

@

E

3 1

C

Q1

Q1 MMBT3904_SOT23-3

MMBT3904_SOT23-3

@

4

H_ADS# <7> H_BNR# <7> H_BPRI# <7>

H_DEFER# <7> H_DRDY# <7> H_DBSY# <7>

H_BR0# <7>

H_INIT# <26> H_LOCK# <7> H_RESET# <7>

H_TRDY# <7> H_HIT# <7>

H_HITM# <7>

XDP_DBRESET# <27>

H_THERMTRIP# <8,26>

CLK_CPU_BCLK <16> CLK_CPU_BCLK# <16>

OCP# <27>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

XDP_TDI

XDP_TMS XDP_BPM#5

H_PROCHOT# H_IERR#

XDP_TRST#

XDP_TCK

+3VS

0.1U_0402_16V4Z

1 2

H_THERMDA

1

C3

2200P_0402_50V7K

2

H_THERMDC

Compal Secret Data

2008/03/28 2008/09/20

3

Compal Secret Data

Deciphered Date

1 2 3 4

R2 54.9_0402_1%R2 54.9_0402_1%

1 2

R3 54.9_0402_1%R3 54.9_0402_1%

1 2

R5 54.9_0402_1%

1 2

@

R13 56_0402_5%R13 56_0402_5% R18 56_0402_5%R18 56_0402_5%

R7 54.9_0402_1%R7 54.9_0402_1% R8 54.9_0402_1%R8 54.9_0402_1%

C2

U1

VDD DP DN THERM#

EMC1402-1-ACZL-TR_MSOP8

2

1 2

12 12

12

8

SMCLK

7

SMDATA

6

ALERT#

5

GND

Title

Size Document Number Rev

B

Date: Sheet

+1.05VS

left NC if no ITP 39Ohm

1 2

R1133

R1133 10K_0402_5%

10K_0402_5%

401597

EC_SMB_CK2 <18,35> EC_SMB_DA2 <18,35>

+3VS

Compal Electronics, Inc.

SCHEMATIC,A4491

452Thursday, October 30, 2008

1

C

of

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15

H_ADSTB#0<7>

H_ADSTB#1<7>

H_A20M#<26>

H_FERR#<26>

H_IGNNE#<26>

H_STPCLK#<26>

H_INTR<26>

H_NMI<26>

H_SMI#<26>

H_A#16

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

1

5

4

3

2

1

JCPU1B

G22 G25

G24

H22

H23 H26

H25

N22

R23 M24 M23

R24

N25 M26

N24

AD26

C23 D25 C24

AF26

AF1

C21

E22 F24 E26

F23 E25

E23 K24

J24 J23

F26 K22

J26

K25 P26

L23 L22 P25

P23 P22 T24

L25 T25

L26

A26 B22

B23

C3

JCPU1B

D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]#

D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]#

GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL[0] BSEL[1] BSEL[2]

Penryn

CONN@

DATA GRP 0

MISC

DATA GRP 1

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]#

DATA GRP 2DATA GRP 3

D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]#

DSTBN[2]#

DSTBP[2]#

DINV[2]#

D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]#

DSTBN[3]#

DSTBP[3]#

DINV[3]# COMP[0]

COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

H_D#0

PAD

PAD PAD

PAD

@

@ @

@

H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31

GTL_REF0

TEST1 TEST2 TEST3 TEST4 TEST5 TEST6

D D

H_DSTBN#0<7> H_DSTBN#2 <7> H_DSTBP#0<7> H_DSTBP#2 <7>

H_DINV#0<7>

C C

Trace Close CPU < 0.5'

Width=4 mil , Spacing: 15mil (55Ohm)

B B

R27

R27 1K_0402_1%

1K_0402_1%

R29

R29 2K_0402_1%

2K_0402_1%

+1.05VS

H_DSTBN#1<7> H_DSTBN#3 <7>

1 2

H_DSTBP#1<7> H_DSTBP#3 <7>

H_DINV#1<7>

R21 1K_0402_5%

R21 1K_0402_5% R22 1K_0402_5%

R22 1K_0402_5%

@

C1477 0.1U_0402_16V4Z

1 2

@

12 12

T1

T1 T2

T2

@

T3

CPU_BSEL0<16> CPU_BSEL1<16> CPU_BSEL2<16>

H_D#32

Y22

H_D#33

AB24

H_D#34

V24

H_D#35

V26

H_D#36

V23

H_D#37

T22

H_D#38

U25

H_D#39

U23

H_D#40

Y25

H_D#41

W22

H_D#42

Y23

H_D#43

W24

H_D#44

W25

H_D#45

AA23

H_D#46

AA24

H_D#47

AB25 Y26 AA26 U22

H_D#48

AE24

H_D#49

AD24

H_D#50

AA21

H_D#51

AB22

H_D#52

AB21

H_D#53

AC26

H_D#54

AD20

H_D#55

AE22

H_D#56

AF23

H_D#57

AC25

H_D#58

AE21

H_D#59

AD21

H_D#60

AC22

H_D#61

AD23

H_D#62

AF22

H_D#63

AC23 AE25 AF24 AC20

COMP0

R26

COMP1

U26

COMP2

AA1

COMP3

Y1 E5

B5 D24

H_PWRGOOD

D6

H_CPUSLP#

D7 AE6

TRACE CLOSELY CPU < 0.5'

COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms) COMP1, COMP3 layout : Width 4mils and Space 25mils (55Ohms)

H_D#[0..63]

H_DINV#2 <7>

R26 27.4_0402_1%R26 27.4_0402_1% R25 54.9_0402_1%R25 54.9_0402_1% R24 27.4_0402_1%R24 27.4_0402_1% R23 54.9_0402_1%R23 54.9_0402_1%

H_DINV#3 <7>

1 2 1 2 1 2 1 2

H_DPRSTP# <8,26,49> H_DPSLP# <26> H_DPWR# <7> H_PWRGOOD <26> H_CPUSLP# <7> PSI# <49>

H_D#[0..63] <7>

+CPU_CORE

A10 A12 A13 A15 A17 A18 A20

B10 B12 B14 B15 B17 B18 B20

C10 C12 C13 C15 C17 C18

D10 D12 D14 D15 D17 D18

E10 E12 E13 E15 E17 E18 E20

F10 F12 F14 F15 F17 F18 F20 AA7

AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20

AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18

A7 A9

B7 B9

C9

D9

E7 E9

F7 F9

JCPU1C

VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067]

Penryn

CONN@

VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]

VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]

VCCA[01] VCCA[02]

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

VCCSENSE

VSSSENSE

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26 C26

AD6 AF5 AE5 AF4 AE3 AF3 AE2

AF7

AE7

.

+CPU_CORE

VCCSENSE

VSSSENSE

C7

CPU_VID0 <49> CPU_VID1 <49> CPU_VID2 <49> CPU_VID3 <49> CPU_VID4 <49> CPU_VID5 <49> CPU_VID6 <49>

R28 100_0402_1%R28 100_0402_1%

R30 100_0402_1%R30 100_0402_1%

0.01U_0402_16V7K

1 2

C7

+1.05VS

20mils

1

C8

2

10U_0805_10V4Z

VCCSENSE <49>

VSSSENSE <49>

+1.5VS

1

2

+CPU_CORE

A A

5

4

Security Classification

2008/03/28 2008/09/20

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/03/28 2008/09/20

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

B

401597

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,A4491

552Thursday, October 30, 2008

of

1

of

C

5

JCPU1D

D D

C C

B B

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080] VSS[081]P3VSS[162]

Penryn

CONN@

VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161]

VSS[163]

.

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

4

+CPU_CORE

1

C416

2

10U_0805_6.3V6M

+CPU-CORE Decoupling SPCAP,Polymer

MLCC 0805 X5R

+1.05VS

1

330U_D2E_2.5VM_R15

2

+

C1478

0.1U_0402_16V4Z

1

2

3

+CPU_CORE

1

2

+

C55

C55 900P_PFAF250E128MNTTE_2.5VM

900P_PFAF250E128MNTTE_2.5VM

3 4

1

2

C426

C425

2

10U_0805_6.3V6M

C,uF ESR, mohm ESL,nH 4X330uF 6m ohm/4 1.8nH/6

32X22uF 3m ohm/32 0.6nH/32 32X10uF 3m ohm/32 0.6nH/32

1

C45

C46

0.1U_0402_16V4Z

2

1

C427

2

10U_0805_6.3V6M

1

C47

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

C428

2

10U_0805_6.3V6M

1

C48

2

0.1U_0402_16V4Z

1

C429

2

10U_0805_6.3V6M

1

C49

0.1U_0402_16V4Z

2

1

C430

2

10U_0805_6.3V6M

1

C50

2

1

C431

2

1

A A

5

4

Security Classification

2008/03/28 2008/09/20

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/03/28 2008/09/20

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,A4491

401597

652Thursday, October 30, 2008

of

1

of

C

5

4

3

2

1

U2A

D D

+1.05VS

12

R47

R47 221_0402_1%

221_0402_1%

H_SWING

width=10mil

C C

1 2

12

B B

width:spacing=10mil:20mil (<0.5")

R55

R55 100_0402_1%

100_0402_1%

H_RCOMP

R54

24.9_0402_1%

+1.05VS

1

C59

0.1U_0402_16V4Z

2

width=10mil

R46

R46 1K_0402_1%

1K_0402_1%

1 2 12

R52

R52 2K_0402_1%

2K_0402_1%

1

2

@

H_D#[0..63]<5>

H_RESET#<4>

H_CPUSLP#<5>

C58

0.1U_0402_16V4Z

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_SWING H_RCOMP

H_RESET# H_CPUSLP#

H_AVREF

U2A

F2

H_D#_0

G8

H_D#_1

F8

H_D#_2

E6

H_D#_3

G2

H_D#_4

H6

H_D#_5

H2

H_D#_6

F6

H_D#_7

D4

H_D#_8

H3

H_D#_9

M9

H_D#_10

M11

H_D#_11

J1

H_D#_12

J2

H_D#_13

N12

H_D#_14

J6

H_D#_15

P2

H_D#_16

L2

H_D#_17

R2

H_D#_18

N9

H_D#_19

L6

H_D#_20

M5

H_D#_21

J3

H_D#_22

N2

H_D#_23

R1

H_D#_24

N5

H_D#_25

N6

H_D#_26

P13

H_D#_27

N8

H_D#_28

L7

H_D#_29

N10

H_D#_30

M3

H_D#_31

Y3

H_D#_32

AD14

H_D#_33

Y6

H_D#_34

Y10

H_D#_35

Y12

H_D#_36

Y14

H_D#_37

Y7

H_D#_38

W2

H_D#_39

AA8

H_D#_40

Y9

H_D#_41

AA13

H_D#_42

AA9

H_D#_43

AA11

H_D#_44

AD11

H_D#_45

AD10

H_D#_46

AD13

H_D#_47

AE12

H_D#_48

AE9

H_D#_49

AA2

H_D#_50

AD8

H_D#_51

AA3

H_D#_52

AD3

H_D#_53

AD7

H_D#_54

AE14

H_D#_55

AF3

H_D#_56

AC1

H_D#_57

AE3

H_D#_58

AC3

H_D#_59

AE11

H_D#_60

AE8

H_D#_61

AG2

H_D#_62

AD6

H_D#_63

C5

H_SWING

E3

H_RCOMP

C12

H_CPURST#

E11

H_CPUSLP#

A11

H_AVREF

B11

H_DVREF

CANTIGA ES_FCBGA1329

GM@

H_ADSTB#_0 H_ADSTB#_1

H_BREQ#

H_DEFER#

HOST

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HITM# H_LOCK# H_TRDY#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4

H_RS#_0

H_RS#_1

H_RS#_2

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_HIT#

A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20

H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9

J8 L3 Y13 Y1

L10 M7 AA5 AE6

L9 M8 AA6 AE5

B15 K13 F13 B13 B14

B6 F12 C8

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BR0# H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3

H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_RS#0 H_RS#1 H_RS#2

H_A#[3..35] <4>

H_ADS# <4> H_ADSTB#0 <4> H_ADSTB#1 <4> H_BNR# <4> H_BPRI# <4> H_BR0# <4> H_DEFER# <4> H_DBSY# <4> CLK_MCH_BCLK <16> CLK_MCH_BCLK# <16> H_DPWR# <5> H_DRDY# <4> H_HIT# <4> H_HITM# <4> H_LOCK# <4> H_TRDY# <4>

H_DINV#0 <5> H_DINV#1 <5> H_DINV#2 <5> H_DINV#3 <5>

H_DSTBN#0 <5> H_DSTBN#1 <5> H_DSTBN#2 <5> H_DSTBN#3 <5>

H_DSTBP#0 <5> H_DSTBP#1 <5> H_DSTBP#2 <5> H_DSTBP#3 <5>

H_REQ#[0..4] <4>

H_RS#[0..2] <4>

within 100mil to Ball A11,B11

A A

5

4

Security Classification

2008/03/28 2008/09/20

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/03/28 2008/09/20

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,A4491

401597

752Thursday, October 30, 2008

of

1

of

C

5

D D

All RSVD balls on GMCH should be left No Connect.

C C

MCH_CLKSEL0<16> MCH_CLKSEL1<16> MCH_CLKSEL2<16>

PM_EXTTS#0

VGATE<16,27,49>

+1.05VS

12

R1150

54.9_0402_1%

54.9_0402_1% R1152

R1152

1 2

330_0402_5%

1 2

R38 10K_0402_5%R38 10K_0402_5% R39 10K_0402_5%R39 10K_0402_5% R40 10K_0402_5%R40 10K_0402_5%

H_THERMTRIP#<4,26> PM_DPRSLPVR<27,49>

PM_EXTTS#1

1 2

MCH_CLKREQ#

1 2

Use VGATE for GMCH_PWROK

VGATE

1 2

R1139 0_0402_5%

ICH_PWROK

1 2

@

R1140 0_0402_5%R1140 0_0402_5%

PM_SYNC#<27> H_DPRSTP#<5,26,49> PM_EXTTS#0<14> PM_EXTTS#1<15>

PLT_RST#<17,25,27,30,31,35>

5

R1141 0_0402_5%R1141 0_0402_5% R1142 0_0402_5%R1142 0_0402_5%

R1143 100_0402_5%R1143 100_0402_5% R1144 0_0402_5%R1144 0_0402_5% R1145 0_0402_5%R1145 0_0402_5%

+3VS

12

R1148

R1148 1K_0402_5%

1K_0402_5%

C

Q76

2

B

MMBT3904_SOT23-3

E

3 1

1 2 1 2

1 2 1 2 1 2

+3VS

2

B

E

GMCH_PWROK

12

R1147

R1147 1K_0402_5%

1K_0402_5%

C

Q75

Q75 MMBT3904_SOT23-3

MMBT3904_SOT23-3

3 1

+3VS

ICH_PWROK<27>

B B

A A

MCH_TSATN#

MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2

MCH_CFG_5 MCH_CFG_6 MCH_CFG_7

MCH_CFG_9 MCH_CFG_10

MCH_CFG_12 MCH_CFG_13

MCH_CFG_16

MCH_CFG_19 MCH_CFG_20

PM_SYNC#_R PM_DPRSTP#_R PM_EXTTS#0 PM_EXTTS#1 GMCH_PWROK MCH_RSTIN# THERMTRIP#_R DPRSLPVR_R

MCH_TSATN_EC# <35>

4

U2B

M36

RSVD1

N36

RSVD2

R33

RSVD3

T33

RSVD4

AH9

RSVD5

AH10

RSVD6

AH12

RSVD7

AH13

RSVD8

K12

RSVD9

AL34

RSVD10

AK34

RSVD11

AN35

RSVD12

AM35

RSVD13

T24

RSVD14

B31

RSVD15

B2

RSVD16

M1

RSVD17

AY21

RSVD20

BG23

RSVD22

BF23

RSVD23

BH18

RSVD24

BF18

RSVD25

T25

CFG_0

R25

CFG_1

P25

CFG_2

P20

CFG_3

P24

CFG_4

C25

CFG_5

N24

CFG_6

M24

CFG_7

E21

CFG_8

C23

CFG_9

C24

CFG_10

N21

CFG_11

P21

CFG_12

T21

CFG_13

R20

CFG_14

M20

CFG_15

L21

CFG_16

H21

CFG_17

P29

CFG_18

R28

CFG_19

T28

CFG_20

R29

PM_SYNC#

B7

PM_DPRSTP#

N33

PM_EXT_TS#_0

P32

PM_EXT_TS#_1

AT40

PWROK

AT11

RSTIN#

T20

THERMTRIP#

R32

DPRSLPVR

BG48

NC_1

BF48

NC_2

BD48

NC_3

BC48

NC_4

BH47

NC_5

BG47

NC_6

BE47

NC_7

BH46

NC_8

BF46

NC_9

BG45

NC_10

BH44

NC_11

BH43

NC_12

BH6

NC_13

BH5

NC_14

BG4

NC_15

BH3

NC_16

BF3

NC_17

BH2

NC_18

BG2

NC_19

BE2

NC_20

BG1

NC_21

BF1

NC_22

BD1

NC_23

BC1

NC_24

F1

NC_25

A47

NC_26

CANTIGA ES_FCBGA1329

GM@

4

RSVD CFG PM NC

DDR CLK/ CONTROL/ COMPENSATIONHDA

CLKDMIGRAPHICS VIDMEMISC

3

AP24

SA_CK_0

AT21

SA_CK_1

AV24

SB_CK_0

AU20

SB_CK_1

AR24

SA_CK#_0

AR21

SA_CK#_1

AU24

SB_CK#_0

AV20

SB_CK#_1

BC28

SA_CKE_0

AY28

SA_CKE_1

AY36

SB_CKE_0

BB36

SB_CKE_1

BA17

SA_CS#_0

AY16

SA_CS#_1

AV16

SB_CS#_0

AR13

SB_CS#_1

BD17

SA_ODT_0

AY17

SA_ODT_1

BF15

SB_ODT_O

AY13

SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH SM_RCOMP_VOL

SM_VREF

SM_PWROK

SM_REXT

SM_DRAMRST#

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST# CL_VREF

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCLK HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

BG22 BH21

BF28 BH28

AV42 AR36 BF17 BC36

B38 A38 E41 F41

F43 E43

AE41 AE37 AE47 AH39

AE40 AE38 AE48 AH40

AE35 AE43 AE46 AH42

AD35 AE44 AF46 AH43

B33 B32 G33 F33 E33

C34

AH37 AH36 AN36 AJ35 AH34

N28 M28 G36 E36 K36 H36

B12

B28 B30 B29 C29 A28

Issued Date

SMRCOMP SMRCOMP#

SM_RCOMP_VOH SM_RCOMP_VOL

SM_PWROK SM_REXT

CLK_DREF_96M CLK_DREF_96M# CLK_DREF_SSC CLK_DREF_SSC#

CLK_MCH_3GPLL CLK_MCH_3GPLL#

DMI_ITX_MRX_N0 DMI_ITX_MRX_N1 DMI_ITX_MRX_N2 DMI_ITX_MRX_N3

DMI_ITX_MRX_P0 DMI_ITX_MRX_P1 DMI_ITX_MRX_P2 DMI_ITX_MRX_P3

DMI_MTX_IRX_N0 DMI_MTX_IRX_N1 DMI_MTX_IRX_N2 DMI_MTX_IRX_N3

DMI_MTX_IRX_P0 DMI_MTX_IRX_P1 DMI_MTX_IRX_P2 DMI_MTX_IRX_P3

ICH_PWROK CL_VREF

MCH_CLKREQ#

MCH_TSATN#

Notice: Please check HDA power rail to select HDA controller.

3

DDRA_CLK0 <14> DDRA_CLK1 <14> DDRB_CLK0 <15> DDRB_CLK1 <15>

DDRA_CLK0# <14> DDRA_CLK1# <14> DDRB_CLK0# <15> DDRB_CLK1# <15>

DDRA_CKE0 <14> DDRA_CKE1 <14> DDRB_CKE0 <15> DDRB_CKE1 <15>

DDRA_SCS0# <14> DDRA_SCS1# <14> DDRB_SCS0# <15> DDRB_SCS1# <15>

DDRA_ODT0 <14> DDRA_ODT1 <14> DDRB_ODT0 <15> DDRB_ODT1 <15>

R34 80.6_0402_1%R34 80.6_0402_1%

1 2

R35 80.6_0402_1%R35 80.6_0402_1%

1 2

SM_VREF

R36 0_0402_5%R36 0_0402_5%

1 2

R37 499_0402_1%R37 499_0402_1%

1 2

CLK_DREF_96M <16> CLK_DREF_96M# <16> CLK_DREF_SSC <16> CLK_DREF_SSC# <16>

CLK_MCH_3GPLL <16> CLK_MCH_3GPLL# <16>

DMI_ITX_MRX_N0 <27> DMI_ITX_MRX_N1 <27> DMI_ITX_MRX_N2 <27> DMI_ITX_MRX_N3 <27>

DMI_ITX_MRX_P0 <27> DMI_ITX_MRX_P1 <27> DMI_ITX_MRX_P2 <27> DMI_ITX_MRX_P3 <27>

DMI_MTX_IRX_N0 <27> DMI_MTX_IRX_N1 <27> DMI_MTX_IRX_N2 <27> DMI_MTX_IRX_N3 <27>

DMI_MTX_IRX_P0 <27> DMI_MTX_IRX_P1 <27> DMI_MTX_IRX_P2 <27> DMI_MTX_IRX_P3 <27>

CL_CLK0 <27> CL_DATA0 <27>

CL_RST#0 <27>

PAD

T34

PAD

T35

@

MCH_CLKREQ# <16>

@

MCH_ICH_SYNC# <27>

Compal Secret Data

2008/03/28 2008/09/20

Compal Secret Data

SM_DRAMRST# would be needed for DDR3 only

For Cantiga 80 Ohm

+1.8V +1.8V

20mil

C57

0.1U_0402_16V4Z

C56

0.1U_0402_16V4Z

Deciphered Date

1 2

@

1

2

1 2

@

+1.05VS

R43

1K_0402_1%

1 2

R44

1

2

R44

511_0402_1%

1 2

2

+1.8V

R31

R31 1K_0402_1%

1K_0402_1%

R32

3.01K_0402_1%

R33

R33 1K_0402_1%

1K_0402_1%

R45

1K_0402_1%

1 2

R1135

R1135 0_0402_5%

0_0402_5%

R48

1K_0402_1%

+DIMM_VREF

Strap Pin Table

CFG[2:0]

CFG5 CFG6 CFG9 CFG10

CFG[13:12]

CFG16 CFG19

CFG20

(PCIE/SDVO select)

SDVO_CTRLDATA L_DDC_DATA DDPC_CTRLDATA

2

1

12

SM_RCOMP_VOH

12

1

C52

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K 2

1

C54

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K 2

CLK_DREF_96M CLK_DREF_96M#

CLK_DREF_SSC CLK_DREF_SSC#

1

C51

0.01U_0402_16V7K

2

SM_RCOMP_VOL

1

C53

0.01U_0402_16V7K

2

R1134 0_0402_5%

1 2

R1136 0_0402_5%

1 2

PM@

PM@ PM@

PM@

R1137 0_0402_5%

1 2

R1138 0_0402_5%

1 2

PM@

PM@ PM@

PM@

as close as possible to the related balls

011 = FSB667 010 = FSB800 000 = FSB1067

0 = DMI x 2 1 = DMI x 4

0 = iTPM Host Interface is enabled

1 = iTPM Host Interface is Disabled 0 = Lane Reversal Enable

1 = Normal Operation (Default)

0 = PCIe Loopback Enable 1 = Disable

00 = Reserved 01 = XOR Mode Enabled 10 = All Z Mode Enabled 11 = Normal Operation

0 = Dynamic ODT Disabled 1 = Dynamic ODT Enabled

0 = Normal Operation 1 = DMI Lane Reversal Enable

0 = Only PCIE or SDVO is operational. 1 = PCIE/SDVO are operating simu.

0 = No SDVO Card Present 1 = SDVO Card Present

0 = LFP Disable 1 = LFP Card Present; PCIE disable

0 = Digital DisplayPort Disable 1 = Digital DisplayPort Device Present

MCH_CFG_5 MCH_CFG_6 MCH_CFG_7 MCH_CFG_9 MCH_CFG_10 MCH_CFG_12 MCH_CFG_13 MCH_CFG_16

MCH_CFG_19 MCH_CFG_20

Title

Size Document Number Rev

Custom

401597

Date: Sheet

*

(Default)

*

(Default)

*

(Default)

*

* *

*

(Default)

R1146 2.21K_0402_1%

R1146 2.21K_0402_1% R79 4.02K_0402_1%

R79 4.02K_0402_1% R81 2.21K_0402_1%

R81 2.21K_0402_1% R84 2.21K_0402_1%

R84 2.21K_0402_1% R86 2.21K_0402_1%

R86 2.21K_0402_1% R77 2.21K_0402_1%

R77 2.21K_0402_1% R78 2.21K_0402_1%

R78 2.21K_0402_1% R1149 2.21K_0402_1%

R1149 2.21K_0402_1%

R73 4.02K_0402_1%

R73 4.02K_0402_1% R75 4.02K_0402_1%

R75 4.02K_0402_1%

Compal Electronics, Inc.

SCHEMATIC,A4491

12 12

@

12

@

12

@

12

@

12

@

12

@

12

@

@ @

@

12 12

@

@ @

@

1

(Default)

* * *

(Default)

*

(Default) (Default) (Default)

+3VS

852Thursday, October 30, 2008

C

of

5

4

3

2

1

DDRA_SDQ[0..63]<14>

D D

DDRA_SDM[0..7]<14>

DDRA_SMA[0..14]<14>

DDRA_SDQ[0..63] DDRA_SDM[0..7] DDRA_SMA[0..14]

DDRB_SDQ[0..63]<15>

DDRB_SDM[0..7]<15>

DDRB_SMA[0..14]<15>

DDRB_SDQ[0..63] DDRB_SDM[0..7] DDRB_SMA[0..14]

U2D DDRA_SDQ0 DDRA_SDQ1 DDRA_SDQ2 DDRA_SDQ3 DDRA_SDQ4 DDRA_SDQ5 DDRA_SDQ6 DDRA_SDQ7 DDRA_SDQ8 DDRA_SDQ9 DDRA_SDQ10 DDRA_SDQ11 DDRA_SDQ12 DDRA_SDQ13 DDRA_SDQ14 DDRA_SDQ15 DDRA_SDQ16 DDRA_SDQ17

C C

B B

DDRA_SDQ18 DDRA_SDQ19 DDRA_SDQ20 DDRA_SDQ21 DDRA_SDQ22 DDRA_SDQ23 DDRA_SDQ24 DDRA_SDQ25 DDRA_SDQ26 DDRA_SDQ27 DDRA_SDQ28 DDRA_SDQ29 DDRA_SDQ30 DDRA_SDQ31 DDRA_SDQ32 DDRA_SDQ33 DDRA_SDQ34 DDRA_SDQ35 DDRA_SDQ36 DDRA_SDQ37 DDRA_SDQ38 DDRA_SDQ39 DDRA_SDQ40 DDRA_SDQ41 DDRA_SDQ42 DDRA_SDQ43 DDRA_SDQ44 DDRA_SDQ45 DDRA_SDQ46 DDRA_SDQ47 DDRA_SDQ48 DDRA_SDQ49 DDRA_SDQ50 DDRA_SDQ51 DDRA_SDQ52 DDRA_SDQ53 DDRA_SDQ54 DDRA_SDQ55 DDRA_SDQ56 DDRA_SDQ57 DDRA_SDQ58 DDRA_SDQ59 DDRA_SDQ60 DDRA_SDQ61 DDRA_SDQ62 DDRA_SDQ63

AJ38

AJ41 AN38 AM38

AJ36

AJ40 AM44 AM42 AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36

AW36

BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12

BB9 BA9

AU10

AV9

BA11

BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6

AT5 AN10 AM11

AM5

AN12 AM13

AJ11 AJ12

AJ9 AJ8

U2D

SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63

BD21

SA_BS_0

BG18

SA_BS_1

AT25

SA_BS_2

BB20

SA_RAS#

BD20

SA_CAS#

AY20

SA_WE#

DDRA_SDM0

AM37

SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7

SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3

DDR SYSTEM MEMORY A

SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329 GM@

GM@

AT41 AY41 AU39 BB12 AY6 AT7 AJ5

AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7

AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8

BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25

DDRA_SDM1 DDRA_SDM2 DDRA_SDM3 DDRA_SDM4 DDRA_SDM5 DDRA_SDM6 DDRA_SDM7

DDRA_SDQS0 DDRA_SDQS1 DDRA_SDQS2 DDRA_SDQS3 DDRA_SDQS4 DDRA_SDQS5 DDRA_SDQS6 DDRA_SDQS7

DDRA_SDQS0# DDRA_SDQS1# DDRA_SDQS2# DDRA_SDQS3# DDRA_SDQS4# DDRA_SDQS5# DDRA_SDQS6# DDRA_SDQS7#

DDRA_SMA0 DDRA_SMA1 DDRA_SMA2 DDRA_SMA3 DDRA_SMA4 DDRA_SMA5 DDRA_SMA6 DDRA_SMA7 DDRA_SMA8 DDRA_SMA9 DDRA_SMA10 DDRA_SMA11 DDRA_SMA12 DDRA_SMA13 DDRA_SMA14

DDRA_SBS0# <14> DDRA_SBS1# <14> DDRA_SBS2# <14>

DDRA_SRAS# <14> DDRA_SCAS# <14> DDRA_SWE# <14>

DDRA_SDQS0 <14> DDRA_SDQS1 <14> DDRA_SDQS2 <14> DDRA_SDQS3 <14> DDRA_SDQS4 <14> DDRA_SDQS5 <14> DDRA_SDQS6 <14> DDRA_SDQS7 <14>

DDRA_SDQS0# <14> DDRA_SDQS1# <14> DDRA_SDQS2# <14> DDRA_SDQS3# <14> DDRA_SDQS4# <14> DDRA_SDQS5# <14> DDRA_SDQS6# <14> DDRA_SDQS7# <14>

DDRB_SDQ0 DDRB_SDQ1 DDRB_SDQ2 DDRB_SDQ3 DDRB_SDQ4 DDRB_SDQ5 DDRB_SDQ6 DDRB_SDQ7 DDRB_SDQ8 DDRB_SDQ9 DDRB_SDQ10 DDRB_SDQ11 DDRB_SDQ12 DDRB_SDQ13 DDRB_SDQ14 DDRB_SDQ15 DDRB_SDQ16 DDRB_SDQ17 DDRB_SDQ18 DDRB_SDQ19 DDRB_SDQ20 DDRB_SDQ21 DDRB_SDQ22 DDRB_SDQ23 DDRB_SDQ24 DDRB_SDQ25 DDRB_SDQ26 DDRB_SDQ27 DDRB_SDQ28 DDRB_SDQ29 DDRB_SDQ30 DDRB_SDQ31 DDRB_SDQ32 DDRB_SDQ33 DDRB_SDQ34 DDRB_SDQ35 DDRB_SDQ36 DDRB_SDQ37 DDRB_SDQ38 DDRB_SDQ39 DDRB_SDQ40 DDRB_SDQ41 DDRB_SDQ42 DDRB_SDQ43 DDRB_SDQ44 DDRB_SDQ45 DDRB_SDQ46 DDRB_SDQ47 DDRB_SDQ48 DDRB_SDQ49 DDRB_SDQ50 DDRB_SDQ51 DDRB_SDQ52 DDRB_SDQ53 DDRB_SDQ54 DDRB_SDQ55 DDRB_SDQ56 DDRB_SDQ57 DDRB_SDQ58 DDRB_SDQ59 DDRB_SDQ60 DDRB_SDQ61 DDRB_SDQ62 DDRB_SDQ63

AK47 AH46 AP47 AP46 AJ46 AJ48

AM48

AP48 AU47 AU46

BA48

AY48

AT47 AR47

BA47 BC47 BC46 BC44 BG43

BF43

BE45 BC41

BF40

BF41 BG38

BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11

BG8

BH12

BF11

BF8 BG7 BC5 BC6

AY3

AY1

BF6

BF5 BA1 BD3 AV2 AU3 AR3 AN2

AY2 AV1 AP3 AR1

AL1

AL2

AJ1 AH1 AM2 AM3 AH3

AJ3

U2E

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

BC16

SB_BS_0

BB17

SB_BS_1

BB33

SB_BS_2

AU17

SB_RAS#

BG16

SB_CAS#

BF14

SB_WE#

DDRB_SDM0

AM47

SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7

SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0 SB_MA_1 SB_MA_2

DDR SYSTEM MEMORY B

SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329 GM@

GM@

AY47 BD40 BF35 BG11 BA3 AP1 AK2

AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6

AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5

AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33

DDRB_SDM1 DDRB_SDM2 DDRB_SDM3 DDRB_SDM4 DDRB_SDM5 DDRB_SDM6 DDRB_SDM7

DDRB_SDQS0 DDRB_SDQS1 DDRB_SDQS2 DDRB_SDQS3 DDRB_SDQS4 DDRB_SDQS5 DDRB_SDQS6 DDRB_SDQS7

DDRB_SDQS0# DDRB_SDQS1# DDRB_SDQS2# DDRB_SDQS3# DDRB_SDQS4# DDRB_SDQS5# DDRB_SDQS6# DDRB_SDQS7#

DDRB_SMA0 DDRB_SMA1 DDRB_SMA2 DDRB_SMA3 DDRB_SMA4 DDRB_SMA5 DDRB_SMA6 DDRB_SMA7 DDRB_SMA8 DDRB_SMA9 DDRB_SMA10 DDRB_SMA11 DDRB_SMA12 DDRB_SMA13 DDRB_SMA14

DDRB_SBS0# <15> DDRB_SBS1# <15> DDRB_SBS2# <15>

DDRB_SRAS# <15> DDRB_SCAS# <15> DDRB_SWE# <15>

DDRB_SDQS0 <15> DDRB_SDQS1 <15> DDRB_SDQS2 <15> DDRB_SDQS3 <15> DDRB_SDQS4 <15> DDRB_SDQS5 <15> DDRB_SDQS6 <15> DDRB_SDQS7 <15>

DDRB_SDQS0# <15> DDRB_SDQS1# <15> DDRB_SDQS2# <15> DDRB_SDQS3# <15> DDRB_SDQS4# <15> DDRB_SDQS5# <15> DDRB_SDQS6# <15> DDRB_SDQS7# <15>

A A

5

4

Security Classification

2008/03/28 2008/09/20

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/03/28 2008/09/20

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,A4491

401597

952Thursday, October 30, 2008

of

1

of

C

5

ENBKL<18,35>

D D

C C

DPST_PWM<22>

1 2

R1154 0_0402_5%

GM@

GMCH_LCD_CLK<22>

GMCH_LCD_DATA<22>

GMCH_ENVDD<22>

1 2

R1155 2.37K_0402_1%

GMCH_TXCLK-<22> GMCH_TXCLK+<22>

GMCH_TXOUT0-<22> GMCH_TXOUT1-<22> GMCH_TXOUT2-<22>

GMCH_TXOUT0+<22> GMCH_TXOUT1+<22> GMCH_TXOUT2+<22>

Change to 0Ohm when use PM chip

GMCH_TV_CRMA

R93

R108

1 2

75_0402_1%

R93

1 2

75_0402_1%

GM@

GMCH_CRT_HSYNC<23>

GMCH_CRT_VSYNC<23>

GMCH_LCD_CLK GMCH_LCD_DATA LCTLB_DATA LCTLA_CLK GMCH_CRT_CLK GMCH_CRT_DATA

1 2

TV_DCONSEL_0 TV_DCONSEL_1

Change to 0Ohm when use PM chip

R1159 150_0402_1%

R1159 150_0402_1% R1160 150_0402_1%

R1160 150_0402_1% R1161 150_0402_1%

R1161 150_0402_1%

12 12

GM@

12

GM@

GM@ GM@

GM@

GMCH_CRT_CLK<23> GMCH_CRT_DATA<23>

R1162 0_0402_5%

PM@

R1163 0_0402_5%

PM@

R107

75_0402_1%

GM@

GMCH_CRT_B<23> GMCH_CRT_G<23> GMCH_CRT_R<23>

B B

+3VS

R1164 2.2K_0402_5%

1 2

R1166 2.2K_0402_5%

1 2

GM@

R1167 10K_0402_5%

1 2

GM@

R1168 10K_0402_5%

1 2

GM@

R1169 2.2K_0402_5%

1 2

GM@

R1170 2.2K_0402_5%

1 2

GM@

GM@ GM@

GM@

12

4

LBKLT_EN LCTLA_CLK LCTLB_DATA GMCH_LCD_CLK GMCH_LCD_DATA

LVDS_IBG

R1153

R1153 0_0402_5%

0_0402_5%

GMCH_TXCLKGMCH_TXCLK+

GMCH_TXOUT0GMCH_TXOUT1GMCH_TXOUT2-

GMCH_TXOUT0+ GMCH_TXOUT1+ GMCH_TXOUT2+

GMCH_TV_COMPS GMCH_TV_LUMA

12

GM@

GMCH_CRT_CLK GMCH_CRT_DATA

CRT_IREF

R1165

1.02K_0402_1%

1 2

GM@

G32 M32 M33 K33

M29 C44

B43 E37 E38

C41 C40 B37 A37

H47 E46 G40 A40

H48 D45

B40 A41

H38 G37

B42 G38

K37

H25 K25

H24

C31 E32

E28 G28

G29 H32

E29

U2C

L32

J33

F40

J37

F37

F25

J28

J32 J29

L29

GM@

L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN

LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL

LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK

LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3

LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3

LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3

LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3

TVA_DAC TVB_DAC TVC_DAC

TV_RTN

TV_DCONSEL_0 TV_DCONSEL_1

CRT_BLUE CRT_GREEN CRT_RED CRT_IRTN CRT_DDC_CLK

CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF

CRT_VSYNC

3

PEG_COMP

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9

PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9

T37 T36

PCIE_GTX_C_MRX_N0

H44

PCIE_GTX_C_MRX_N1

J46

PCIE_GTX_C_MRX_N2

L44

PCIE_GTX_C_MRX_N3

L40

PCIE_GTX_C_MRX_N4

N41

PCIE_GTX_C_MRX_N5

P48

PCIE_GTX_C_MRX_N6

N44

PCIE_GTX_C_MRX_N7

T43

PCIE_GTX_C_MRX_N8

U43

PCIE_GTX_C_MRX_N9

Y43

PCIE_GTX_C_MRX_N10

Y48

PCIE_GTX_C_MRX_N11

Y36

PCIE_GTX_C_MRX_N12

AA43

PCIE_GTX_C_MRX_N13

AD37

PCIE_GTX_C_MRX_N14

AC47

PCIE_GTX_C_MRX_N15

AD39

PCIE_GTX_C_MRX_P0

H43

PCIE_GTX_C_MRX_P1

J44

PCIE_GTX_C_MRX_P2

L43

PCIE_GTX_C_MRX_P3

L41

PCIE_GTX_C_MRX_P4

N40

PCIE_GTX_C_MRX_P5

P47

PCIE_GTX_C_MRX_P6

N43

PCIE_GTX_C_MRX_P7

T42

PCIE_GTX_C_MRX_P8

U42

PCIE_GTX_C_MRX_P9

Y42

PCIE_GTX_C_MRX_P10

W47

PCIE_GTX_C_MRX_P11

Y37

PCIE_GTX_C_MRX_P12

AA42

PCIE_GTX_C_MRX_P13

AD36

PCIE_GTX_C_MRX_P14

AC48

PCIE_GTX_C_MRX_P15

AD40

PCIE_MTX_GRX_N0

J41

PCIE_MTX_GRX_N1

M46

PCIE_MTX_GRX_N2

M47

PCIE_MTX_GRX_N3

M40

PCIE_MTX_GRX_N4

M42

PCIE_MTX_GRX_N5

R48

PCIE_MTX_GRX_N6

N38

PCIE_MTX_GRX_N7

T40

PCIE_MTX_GRX_N8

U37

PCIE_MTX_GRX_N9

U40

PCIE_MTX_GRX_N10

Y40

PCIE_MTX_GRX_N11

AA46

PCIE_MTX_GRX_N12

AA37

PCIE_MTX_GRX_N13

AA40

PCIE_MTX_GRX_N14

AD43

PCIE_MTX_GRX_N15

AC46

PCIE_MTX_GRX_P0

J42

PCIE_MTX_GRX_P1

L46

PCIE_MTX_GRX_P2

M48

PCIE_MTX_GRX_P3

M39

PCIE_MTX_GRX_P4

M43

PCIE_MTX_GRX_P5

R47

PCIE_MTX_GRX_P6

N37

PCIE_MTX_GRX_P7

T39

PCIE_MTX_GRX_P8

U36

PCIE_MTX_GRX_P9

U39

PCIE_MTX_GRX_P10

Y39

PCIE_MTX_GRX_P11

Y46

PCIE_MTX_GRX_P12

AA36

PCIE_MTX_GRX_P13

AA39

PCIE_MTX_GRX_P14

AD42

PCIE_MTX_GRX_P15

AD46

PEG_COMPI

PEG_COMPO

PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9

LVDS TV VGA

PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8

PCI-EXPRESS GRAPHICS

PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

PEG_TX_10

PEG_TX_11

PEG_TX_12

PEG_TX_13

PEG_TX_14

PEG_TX_15

CANTIGA ES_FCBGA1329

10mils

2

1 2

R57 49.9_0402_1%R57 49.9_0402_1%

PCIE_MTX_C_GRX_N[0..15] PCIE_MTX_C_GRX_P[0..15]

PCIE_GTX_C_MRX_N[0..15] PCIE_GTX_C_MRX_P[0..15]

C1290 0.1U_0402_16V7K

1 2

C1292 0.1U_0402_16V7K

1 2

PM@

C1294 0.1U_0402_16V7K

1 2

PM@

C1296 0.1U_0402_16V7K

1 2

PM@

C1298 0.1U_0402_16V7K

1 2

PM@

C1300 0.1U_0402_16V7K

1 2

PM@

C1302 0.1U_0402_16V7K

1 2

PM@

C1304 0.1U_0402_16V7K

1 2

PM@

PM@ PM@

PM@

C1306 0.1U_0402_16V7K

1 2

C1308 0.1U_0402_16V7K

1 2

PM@

C1310 0.1U_0402_16V7K

1 2

PM@

C1312 0.1U_0402_16V7K

1 2

PM@

C1314 0.1U_0402_16V7K

1 2

PM@

C1316 0.1U_0402_16V7K

1 2

PM@

C1318 0.1U_0402_16V7K

1 2

PM@

C1320 0.1U_0402_16V7K

1 2

PM@

PM@ PM@

PM@

+1.05VS

PCIE_MTX_C_GRX_N[0..15] <17> PCIE_MTX_C_GRX_P[0..15] <17>

PCIE_GTX_C_MRX_N[0..15] <17>

PCIE_GTX_C_MRX_P[0..15] <17>

C1289 0.1U_0402_16V7K

1 2

C1291 0.1U_0402_16V7K

1 2

PM@

C1293 0.1U_0402_16V7K

1 2

PM@

C1295 0.1U_0402_16V7K

1 2

PM@

C1297 0.1U_0402_16V7K

1 2

PM@

C1299 0.1U_0402_16V7K

1 2

PM@

C1301 0.1U_0402_16V7K

1 2

PM@

C1303 0.1U_0402_16V7K

1 2

PM@

PM@ PM@

PM@

C1305 0.1U_0402_16V7K

1 2

C1307 0.1U_0402_16V7K

1 2

PM@

C1309 0.1U_0402_16V7K

1 2

PM@

C1311 0.1U_0402_16V7K

1 2

PM@

C1313 0.1U_0402_16V7K

1 2

PM@

C1315 0.1U_0402_16V7K

1 2

PM@

C1317 0.1U_0402_16V7K

1 2

PM@

C1319 0.1U_0402_16V7K

1 2

PM@

PM@ PM@

PM@

1

PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_N1 PCIE_MTX_C_GRX_N2 PCIE_MTX_C_GRX_N3 PCIE_MTX_C_GRX_N4 PCIE_MTX_C_GRX_N5 PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_N7 PCIE_MTX_C_GRX_N8 PCIE_MTX_C_GRX_N9 PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_N11 PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_N13 PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_N15

PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_P1 PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_P3 PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_P5 PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_P7 PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_P9 PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_P11 PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_P13 PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_P15

A A

R1173 100K_0402_5%R1173 100K_0402_5%

1 2

5

LBKLT_EN

4

Security Classification

2008/03/28 2008/09/20

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/03/28 2008/09/20

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,A4491

401597

10 52Thursday, October 30, 2008

of

1

of

C

5

U2F

+1.8V

D D

Reference PILLAR_ROCK CRB Rev1.0

Pins BA36, BB24, BD16, BB21, AW16, AW13, AT13 could be left NC for DDR2 board.

C C

B B

T4

T4 T5

T5

A A

PAD

PAD PAD

PAD

@

@ @

@

VCC_SM_BA36 VCC_SM_BB24 VCC_SM_BD16

VCC_SM_AW16 VCC_SM_AT13

+VGFX_CORE

VCC_AXG_SENSE VSS_AXG_SENSE

5

U2F

2600mA

AP33

VCC_SM_1

AN33

VCC_SM_2

BH32

VCC_SM_3

BG32

VCC_SM_4

BF32

VCC_SM_5

BD32

VCC_SM_6

BC32

VCC_SM_7

BB32

VCC_SM_8

BA32

VCC_SM_9

AY32

VCC_SM_10

AW32

VCC_SM_11

AV32

VCC_SM_12

AU32

VCC_SM_13

AT32

VCC_SM_14

AR32

VCC_SM_15

AP32

VCC_SM_16

AN32

VCC_SM_17

BH31

VCC_SM_18

BG31

VCC_SM_19

BF31

VCC_SM_20

BG30

VCC_SM_21

BH29

VCC_SM_22

BG29

VCC_SM_23

BF29

VCC_SM_24

BD29

VCC_SM_25

BC29

VCC_SM_26

BB29

VCC_SM_27

BA29

VCC_SM_28

AY29

VCC_SM_29

AW29

VCC_SM_30

AV29

VCC_SM_31

AU29

VCC_SM_32

AT29

VCC_SM_33

AR29

VCC_SM_34

AP29

VCC_SM_35

BA36

VCC_SM_36/NC

BB24

VCC_SM_37/NC

BD16

VCC_SM_38/NC

BB21

VCC_SM_39/NC

AW16

VCC_SM_40/NC

AW13

VCC_SM_41/NC

AT13

VCC_SM_42/NC

Y26

VCC_AXG_1

AE25

VCC_AXG_2

AB25

VCC_AXG_3

AA25

VCC_AXG_4

AE24

VCC_AXG_5

AC24

VCC_AXG_6

AA24

VCC_AXG_7

Y24

VCC_AXG_8

AE23

VCC_AXG_9

AC23

VCC_AXG_10

AB23

VCC_AXG_11

AA23

VCC_AXG_12

AJ21

VCC_AXG_13

AG21

VCC_AXG_14

AE21

VCC_AXG_15

AC21

VCC_AXG_16

AA21

VCC_AXG_17

Y21

VCC_AXG_18

AH20

VCC_AXG_19

AF20

VCC_AXG_20

AE20

VCC_AXG_21

AC20

VCC_AXG_22

AB20

VCC_AXG_23

AA20

VCC_AXG_24

T17

VCC_AXG_25

T16

VCC_AXG_26

AM15

VCC_AXG_27

AL15

VCC_AXG_28

AE15

VCC_AXG_29

AJ15

VCC_AXG_30

AH15

VCC_AXG_31

AG15

VCC_AXG_32

AF15

VCC_AXG_33

AB15

VCC_AXG_34

AA15

VCC_AXG_35

Y15

VCC_AXG_36

V15

VCC_AXG_37

U15

VCC_AXG_38

AN14

VCC_AXG_39

AM14

VCC_AXG_40

U14

VCC_AXG_41

T14

VCC_AXG_42

AJ14

VCC_AXG_SENSE

AH14

VSS_AXG_SENSE

CANTIGA ES_FCBGA1329

GM@

VCC_AXG_NTCF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8

VCC SM

VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43

VCC GFX NCTF

VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52

POWER

VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60

VCC GFX

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

VCC SM LF

W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16

AV44 BA37 AM40 AV21 AY5 AM10 BB13

4

+VGFX_CORE

VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7

C139

0.1U_0402_16V7K

+1.05VS

1

2

C140

0.1U_0402_16V7K

Place close to the GMCH

220U_D2_4VM_R15

J1

J1 JUMP_43X79

JUMP_43X79

112

1 2

R1174 0_0805_5%

GM@

GM@ @

@

112

J2

J2 JUMP_43X79

JUMP_43X79

@

+VGFX_CORE

2

C126

330U_D2E_2.5VM_R15

R1175

R1175 0_0402_5%

0_0402_5%

PM@

C1485

330U_D2E_2.5VM_R15

+1.8V

1

+

2

Reference PILLAR_ROCK CRB Rev1.0

VCC_SM_BA36 VCC_SM_BB24 VCC_SM_BD16 VCC_SM_AW16 VCC_SM_AT13

1

C1486

0.1U_0402_16V7K

0.1U_0402_16V7K 2

@

1

C141

0.22U_0402_6.3V6K

2

1

C142

C143

0.47U_0603_16V4Z

2

0.22U_0402_6.3V6K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

VCC: 1930.4mA (GMCH), 1210.34mA (MCH)

+1.05VS

(270UF*1, 22UF*1, 0.22UF*2, 0.1UF*1)

1

+

C131

2

10U_0805_10V4Z

C124

0.22U_0402_6.3V6K

C132

0.22U_0402_6.3V6K

C133

0.1U_0402_16V4Z

Cavity Capacitors

VCC_AXG: 6326.84mA (330UF*2, 22UF*1, 10UF*1, 1U*1, 0.47U*1, 0.1UF*2)

C1482

1

2

1U_0402_6.3V6K

GM@

1

C130

2

0.1U_0402_16V4Z

C1482

1

10U_0805_10V4Z

2

GM@

Cavity Capacitors

1

C123

2

C1483

10U_0805_10V4Z

GM@

C1481

C1479

0.47U_0603_16V4Z

GM@

1

+

2

GM@

Place close to the GMCH

VCC_SM: 2600mA (330UF*1, 22UF*2, 0.1UF*1)

1

C122

10U_0805_10V4Z

2

10U_0805_10V4Z

Place on the edge

1

C1487

2

0.1U_0402_16V7K

@

1

C144

2

1U_0402_6.3V6K

3

C1488

0.1U_0402_16V7K

@

1

2

1

2

1

C1490

0.1U_0402_16V7K

0.1U_0402_16V7K 2

@

Compal Secret Data

1

C1489

2

0.1U_0402_16V7K

@

1

C145

C145 1U_0402_6.3V6K

1U_0402_6.3V6K

2

2008/03/28 2008/09/20

1

C125

2

C1484

1

0.1U_0402_16V4Z

2

Deciphered Date

GM@

1

2

C1480

1

2

0.1U_0402_16V4Z

GM@

2

+1.05VS

2

U2G

AG34

VCC_1

AC34

VCC_2

AB34

VCC_3

AA34

VCC_4

Y34

VCC_5

V34

VCC_6

U34

VCC_7

AM33

VCC_8

AK33

VCC_9

AJ33

VCC_10

AG33

VCC_11

AF33

VCC_12

AE33

VCC_13

AC33

VCC_14

AA33

VCC_15

Y33

VCC_16

W33

VCC_17

V33

VCC_18

U33

VCC_19

AH28

VCC_20

AF28

VCC_21

AC28

VCC_22

AA28

VCC_23

AJ26

VCC_24

AG26

VCC_25

AE26

VCC_26

AC26

VCC_27

AH25

VCC_28

AG25

VCC_29

AF25

VCC_30

AG24

VCC_31

AJ23

VCC_32

AH23

VCC_33

AF23

VCC_34

T32

VCC_35

CANTIGA ES_FCBGA1329

GM@

1

VCC CORE

POWER

+1.05VS

VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8

VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28

VCC NCTF

VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,A4491

401597

AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23

1

of

11 52Thursday, October 30, 2008

C

5

4

3

2

1

L16

+1.05VS

VCCA_HPLL: 24mA

Please check Power source if want support IAMT

D D

(4.7UF*1, 0.1UF*1)

VCCA_MPLL: 139.2mA (22UF*1, 0.1UF*1)

1 2

MBK1608121YZF_0603

120Ohm@100MHz

L19

1 2

MBK1608121YZF_0603

VCCA_CRT_DAC: 73mA (0.1UF*1, 0.01UF*1)

1 2

+3VS

L20

L20 MBK1608301YZF_0603

MBK1608301YZF_0603

1

GM@

+

C1501

C1501 GM@

GM@ 220U_D2_4VM_R15

220U_D2_4VM_R15

2

C C

VCCA_DAC_BG: 2.6833333mA (0.1UF*1, 0.01UF*1)

1 2

+3VS

L23

L23 MBK1608221YZF_0603

MBK1608221YZF_0603

GM@

VCCA_TV_DAC: 40mA (0.1UF*1,

+3VS

180Ohm@100MHz

+1.5VS

L25

MBK1608221YZF_0603

180Ohm@100MHz

0.01UF*1 for each DAC)

L24

L24 MBK1608221YZF_0603

MBK1608221YZF_0603

VCCD_TVDAC: 58.696mA (0.1UF*1, 0.01UF*1)

1 2

R1193

R1193 100_0603_1%

100_0603_1%

5

B B

A A

+1.5VS

+1.05VS_HPLL

1

C1491

4.7U_0805_10V4Z

4.7U_0805_10V4Z 2

+1.05VS_MPLL

12

R1177

0.5_0603_1%

1

C1498

C1498 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

C1502

C1500

0.1U_0402_16V4Z

Close to Ball A26, B27

C1509

0.1U_0402_16V4Z

GM@

Close to Ball A25

1 2

GM@

0.1U_0402_16V4Z

VCCD_QDAC: 48.363mA (0.1UF*1, 0.01UF*1)

0.1U_0402_16V4Z

2

0.01U_0402_16V7K

GM@

1

C1510

2

0.01U_0402_16V7K

GM@

1

C1517

0.1U_0402_16V4Z

0.1U_0402_16V4Z 2

GM@

1

C1520

C1521

2

0.022U_0402_16V7K

1

C1525

C1524

2

0.01U_0402_16V7K

2

Please check Power source if want support IAMT

10U_0805_6.3V6M

0.01U_0402_16V7K

1

C1492

2

0.1U_0402_16V4Z

Please check Power source if want support IAMT

1

C1495

2

0.1U_0402_16V4Z

+3VS_CRTDAC

12

R1179

R1179 0_0402_5%

0_0402_5%

PM@

+3VS_DACBG

1

C1511

2

@

PM@

+3VS_TVDAC

1

C1516

2

PM@

GM@

+1.5VS_TVDAC

1

Also power for internal Thermal Sensor

2

+1.5VS_QDAC

1

12

2

@

+1.5VS

+1.05VS

12

R1184

R1184 0_0402_5%

0_0402_5%

12

R1187

R1187 0_0402_5%

0_0402_5%

R1195

R1195 0_0402_5%

0_0402_5%

+1.05VS

+3VS

C94

C94 220U_D2_4VM_R15

220U_D2_4VM_R15

1 2

L17

L17 0_1210_5%

0_1210_5%

GM@

VCCA_DPLLA VCCA_DPLLB: 64.8mA (220UF*1, 0.1UF*1)

1 2

L18

L18 0_1210_5%

0_1210_5%

GM@

R96

R96 0_0402_5%

0_0402_5%

1 2

R97

R97 0_0402_5%

0_0402_5%

1 2

@

Please check Power source if want support IAMT

+1.05VS

12

C1503

10U_0805_6.3V6M

1 2

R100

1

0_0805_5%

+

2

@

Please check Power source if want support IAMT

+1.05VS

+1.5VS

Please check Power source if want support IAMT

4

+1.05VS_DPLLA

C1493

C1493 220U_D2_4VM_R15

220U_D2_4VM_R15

+1.05VS_DPLLB

C1496

C1496 10U_0805_10V4Z

10U_0805_10V4Z

+1.8V_TX_LVDS

+VCCA_PEG_BG

1

C89

0.1U_0402_16V4Z

0.1U_0402_16V4Z 2

No CIS Symbol

L21

1 2

MBK1608221YZF_0603

1 2

R1181

R1181 1_0402_1%

1_0402_1%

+1.05VS_A_SM

+1.05VS_A_SM_CK

1 2

R103

R103 0_0603_5%

0_0603_5%

2.2U_0603_6.3V6K

NO_STUFF

1 2

R1188

R1188 0_0402_5%

0_0402_5%

@

0_0402_5%

+1.05VS_HPLL

+1.8V

12

1

C1494

+

2

GM@

1

2

GM@

C1499

C1499 1000P_0402_50V7K

1000P_0402_50V7K

C95

22U_0805_6.3V6M

1

C102

2

@

12

R1189

C1494

0.1U_0402_16V4Z

C1497

0.1U_0402_16V4Z

R1176

R1176 0_0402_5%

0_0402_5%

2

PM@

GM@

12

1

R1178

R1178 0_0402_5%

0_0402_5%

2

PM@

GM@

1

VCCA_LVDS: 13.2mA (1000PF*1)

2

GM@

VCCA_PEG_BG: 0.414mA (0.1UF*1)

+1.05VS_PEGPLL

VCCA_SM: (22UF*2, 4.7UF*1, 1UF*1)

1

2

C103

22U_0805_6.3V6M

C1518

0.1U_0402_16V4Z

VCCA_PEG_PLL: 50mA

1

C1504

(0.1UF*1)

0.1U_0402_16V4Z

2

1

C96

4.7U_0805_10V4Z

4.7U_0805_10V4Z 2

VCCA_SM_CK: 24mA (22UF*1, 2.2UF*1, 0.1UF*1)

1

C105

0.1U_0402_16V4Z

2

+3VS_TVDAC

VCCD_HDA: 50mA (0.1UF*1)

1

Close to A32

2

GM@

VCCD_HPLL: 157.2mA (0.1UF*1)

+1.05VS_PEGPLL

VCCD_PEG_PLL: 50mA (0.1UF*1)

1 2

R1191

R1191 0_0603_5%

0_0603_5%

GM@

C1522

10U_0805_6.3V6M

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VS_CRTDAC

+3VS_DACBG

+1.05VS_DPLLA

+1.05VS_DPLLB

+1.05VS_HPLL +1.05VS_MPLL

1

C97

2

1U_0402_6.3V6K

1

2

+1.5VS_HDA

+1.5VS_TVDAC

+1.5VS_QDAC

+1.8V_LVDS

1

2

GM@

VCCD_LVDS: 60.311111mA (1UF*1)

Issued Date

B27 A26

A25 B25

F47 L48 AD1 AE1

J48 J47

AD48

AA48

AR20 AP20 AN20 AR17 AP17 AN17 AT16 AR16 AP16

AP28 AN28 AP25 AN25 AN24 AM28 AM26 AM25

AL25

AM24

AL24

AM23

AL23

B24 A24

A32

M25 L28

AF1

AA47

M38 L37

1

C1523

1U_0402_6.3V6K

1U_0402_6.3V6K 2

3

U2H

852mA

73mA

VCCA_CRT_DAC_1 VCCA_CRT_DAC_2

2.69mA

VCCA_DAC_BG VSSA_DAC_BG

64.8mA

VCCA_DPLLA VCCA_DPLLB

24mA

VCCA_HPLL

139.2mA

VCCA_MPLL

13.2mA

VCCA_LVDS VSSA_LVDS

0.414mA

VCCA_PEG_BG

50mA

VCCA_PEG_PLL

480mA

VCCA_SM_1 VCCA_SM_2 VCCA_SM_3 VCCA_SM_4 VCCA_SM_5 VCCA_SM_6 VCCA_SM_7 VCCA_SM_8 VCCA_SM_9

24mA

VCCA_SM_CK_1 VCCA_SM_CK_2 VCCA_SM_CK_3 VCCA_SM_CK_4 VCCA_SM_CK_5 VCCA_SM_CK_NCTF_1 VCCA_SM_CK_NCTF_2 VCCA_SM_CK_NCTF_3 VCCA_SM_CK_NCTF_4 VCCA_SM_CK_NCTF_5 VCCA_SM_CK_NCTF_6 VCCA_SM_CK_NCTF_7 VCCA_SM_CK_NCTF_8

87.79mA

VCCA_TV_DAC_1 VCCA_TV_DAC_2

50mA

VCC_HDA

58.696mA

VCCD_TVDAC

48.363mA

VCCD_QDAC

157.2mA

VCCD_HPLL

50mA

VCCD_PEG_PLL

60.31mA

VCCD_LVDS_1 VCCD_LVDS_2

CANTIGA ES_FCBGA1329

GM@

12

R1192

R1192 0_0402_5%

0_0402_5%

PM@

2008/03/28 2008/09/20

CRTPLLA LVDSA PEG

VTT

POWER

A SM

AXF

VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4

SM CK

VCC_TX_LVDS

A CK

HV

TV

HDA

DMI PEG

VTTLF

LVDS D TV/CRT

Compal Secret Data

Deciphered Date

118.8mA

VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8

VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25

VCC_AXF_1 VCC_AXF_2 VCC_AXF_3

105.3mA

VCC_HV_1 VCC_HV_2 VCC_HV_3

1782mA

VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5

456mA

VCC_DMI_1 VCC_DMI_2 VCC_DMI_3 VCC_DMI_4

VTTLF1 VTTLF2 VTTLF3

U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1

B22 B21 A21

BF21 BH20 BG20 BF20

K47

VCC_HV: 105.3mA

C35 B35 A35

V48 U48 V47 U47 U46

AH48 AF48 AH47 AG47

VCC_DMI: 456mA (0.1UF*1)

VTTLF_CAP1

A8

VTTLF_CAP2

L1

VTTLF_CAP3

AB2

C110

0.47U_0603_16V4Z

2

VTT: 852mA

+1.05VS

(270UF*1, 4.7UF*2, 2.2UF*1, 0.47UF*1)

1

+

C71

C71 220U_D2_4VM_R15

220U_D2_4VM_R15

2

4.7U_0805_10V4Z

+1.05VS_AXF

1

C1505

10U_0805_6.3V6M

2

@

+1.8V_SM_CK

+1.8V_TX_LVDS: 118.8mA (22UF*1, 1000PF*1)

12

R1185

0_0402_5%

+3VS

1

C107

PM@

0.1U_0402_16V4Z

2

+1.05VS_PEG: 1782mA (220UF*1, 22UF*1, 4.7UF*1)

+1.05VS_DMI

1

C112

C111

0.47U_0603_16V4Z

0.47U_0603_16V4Z 2

2

0.47U_0603_16V4Z

D8

2 1

+1.05VS +3VS

CH751H-40PT_SOD323-2

1

2

VCC_AXF: 321.35mA (10UF*1, 1UF*1)

1

2

10U_0805_10V4Z

C80

C72

4.7U_0805_10V4Z

4.7U_0805_10V4Z 2

2.2U_0603_6.3V6K

1 2

R1180

R1180 0_0603_5%

0_0603_5%

1 C1506

C1506 1U_0402_6.3V6K

1U_0402_6.3V6K 2

VCC_SM_CK: 119.85mA (10UF*1, 0.1UF*1)

C1507

0.1U_0402_16V4Z

+1.8V_TX_LVDS

1

C1512

1000P_0402_50V7K

2

GM@

+1.05VS_PEG

1

+

C1514

2

1 2

R1190

R1190 0_0805_5%

0_0805_5%

1

C1519

0.1U_0402_16V4Z

2

R1194

1 2

10_0603_5%

Title

Size Document Number Rev

Custom

401597

Date: Sheet

1

C82

C81

0.47U_0603_16V4Z

2

1 2

R1182

R1182 1_0402_1%

1_0402_1%

1

C1513

2

10U_0805_10V4Z

C1515

C1515 220U_D2_4VM_R15

220U_D2_4VM_R15

Compal Electronics, Inc.

SCHEMATIC,A4491

0.47U_0603_16V4Z

2

Please check Power source if want support IAMT

+1.05VS

1uH 30%

1 2

L22

L22 MBK1608121YZF_0603

MBK1608121YZF_0603

0.1uH 20%

1 2

R1183

R1183 0_0603_5%

0_0603_5%

GM@

1 2

R1186

R1186 0_0805_5%

0_0805_5%

1 2

C1508

C1508 10U_0805_6.3V6M

10U_0805_6.3V6M

+1.05VS

+1.8V

Please check Power source if want support IAMT

+1.05VS

1

+1.8V

C

of

12 52Thursday, October 30, 2008

5

U2I

AU48

VSS_1

AR48

VSS_2

AL48

VSS_3

BB47

VSS_4

AW47

VSS_5

AN47

D D

C C

B B

A A

AJ47 AF47 AD47 AB47

BD46 BA46 AY46 AV46 AR46

AM46

BF44 AH44 AD44 AA44

BC43 AV43 AU43

AM43

BG42 AY42 AT42 AN42

AJ42 AE42

BD41 AU41

AM41

AH41 AD41 AA41

BG40 BB40 AV40 AN40

AT39

AM39

AJ39 AE39

BH38 BC38 BA38 AU38 AH38 AD38 AA38

BF37 BB37

AW37

AT37 AN37

AJ37

BG36 BD36 AK15 AU36

VSS_6 VSS_7 VSS_8 VSS_9 VSS_10

Y47

VSS_11

T47

VSS_12

N47

VSS_13

L47

VSS_14

G47

VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21

V46

VSS_22

R46

VSS_23

P46

VSS_24

H46

VSS_25

F46

VSS_26 VSS_27 VSS_28 VSS_29 VSS_30

Y44

VSS_31

U44

VSS_32

T44

VSS_33

M44

VSS_34

F44

VSS_35 VSS_36 VSS_37 VSS_38 VSS_39

J43

VSS_40

C43

VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47

N42

VSS_48

L42

VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55

Y41

VSS_56

U41

VSS_57

T41

VSS_58

M41

VSS_59

G41

VSS_60

B41

VSS_61 VSS_62 VSS_63 VSS_64 VSS_65

H40

VSS_66

E40

VSS_67 VSS_68 VSS_69 VSS_70 VSS_71

N39

VSS_72

L39

VSS_73

B39

VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81

Y38

VSS_82

U38

VSS_83

T38

VSS_84

J38

VSS_85

F38

VSS_86

C38

VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93

H37

VSS_94

C37

VSS_95 VSS_96 VSS_97 VSS_98 VSS_99

VSS

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329 GM@

GM@

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199

AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23 AJ6

4

U2J

BG21

VSS_199

L12

VSS_200

AW21

VSS_201

AU21

VSS_202

AP21

VSS_203

AN21

VSS_204

AH21

VSS_205

AF21

VSS_206

AB21

VSS_207

R21

VSS_208

M21

VSS_209

J21

VSS_210

G21

VSS_211

BC20

VSS_212

BA20

VSS_213

AW20

VSS_214

AT20

VSS_215

AJ20

VSS_216

AG20

VSS_217

Y20

VSS_218

N20

VSS_219

K20

VSS_220

F20

VSS_221

C20

VSS_222

A20

VSS_223

BG19

VSS_224

A18

VSS_225

BG17

VSS_226

BC17

VSS_227

AW17

VSS_228

AT17

VSS_229

R17

VSS_230

M17

VSS_231

H17

VSS_232

C17 BA16 AU16

AN16

BG15 AC15

W15

BG14 AA14

BG13 BC13 BA13

AN13

AJ13

AE13

BF12 AV12 AT12

AM12

AA12

BD11 BB11 AY11 AN11 AH11

BG10 AV10 AT10

AJ10 AE10 AA10

N16 G16

C14

N13 G13

N11 G11 C11

M10 BF9 BC9 AN9 AM9 AD9

BH8 BB8 AV8 AT8

VSS_233 VSS_235 VSS_237

VSS_238 VSS_239

K16

VSS_240 VSS_241

E16

VSS_242 VSS_243 VSS_244 VSS_245

A15

VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252

VSS_255 VSS_256 VSS_257 VSS_258

L13

VSS_259 VSS_260

E13

VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266

J12

VSS_267

A12

VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273

Y11

VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290

G9

VSS_291

B9

VSS_292 VSS_293 VSS_294 VSS_295 VSS_296

VSS

VSS NCTF

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329 GM@

GM@

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16

VSS_SCB_1 VSS_SCB_2 VSS_SCB_3 VSS_SCB_4 VSS_SCB_5

VSS SCB

NC

3

VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325

VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350

VSS_351 VSS_352 VSS_353 VSS_354

NC_26 NC_27 NC_28 NC_29 NC_30 NC_31 NC_32 NC_33 NC_34 NC_35 NC_36 NC_37 NC_38 NC_39 NC_40 NC_41 NC_42

AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4

BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1

U24 U28 U25 U29

AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17

BH48 BH1 A48 C1 A3

E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48

2

1

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/28 2008/09/20

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,A4491

401597

of

13 52Thursday, October 30, 2008

1

C

5

4

3

2

1

+1.8V +1.8V

JDIMM1

+DIMM_VREF

DDRA_SDQ0 DDRA_SDQ5 DDRA_SDQ1

DDRA_SDQS0#<9> DDRA_SDQS0<9>

D D

DDRA_SDQS1#<9> DDRA_SDQS1<9>

DDRA_SDQS2#<9> DDRA_SDQS2<9>

DDRA_CKE0<8>

C C

DDRA_SBS2#<9>

DDRA_SBS0#<9> DDRA_SWE#<9>

DDRA_SCAS#<9> DDRA_SCS1#<8>

DDRA_ODT1<8>

DDRA_SDQS4#<9> DDRA_SDQS4<9>

B B

DDRA_SDQS6#<9> DDRA_SDQS6<9>

D_CK_SDATA<15,16> D_CK_SCLK<15,16>

A A

+3VS

C171

2.2U_0603_6.3V6K

DDRA_SDQS0# DDRA_SDQS0

DDRA_SDQ2 DDRA_SDQ3

DDRA_SDQ8 DDRA_SDQ9

DDRA_SDQS1# DDRA_SDQS1

DDRA_SDQ10 DDRA_SDQ11

DDRA_SDQ16 DDRA_SDQ17

DDRA_SDQS2# DDRA_SDQS2

DDRA_SDQ18 DDRA_SDQ19

DDRA_SDQ24 DDRA_SDQ25 DDRA_SDQ29

DDRA_SDM3

DDRA_SDQ26 DDRA_SDQ27

DDRA_SBS2# DDRA_SMA12

DDRA_SMA9 DDRA_SMA8

DDRA_SMA5 DDRA_SMA3 DDRA_SMA1

DDRA_SMA10 DDRA_SBS0# DDRA_SWE#

DDRA_SCAS# DDRA_SCS1#

DDRA_ODT1 DDRA_SDQ32

DDRA_SDQ33 DDRA_SDQS4#

DDRA_SDQS4 DDRA_SDQ34

DDRA_SDQ35 DDRA_SDQ40

DDRA_SDQ41 DDRA_SDM5 DDRA_SDQ42

DDRA_SDQ43 DDRA_SDQ48

DDRA_SDQ49

DDRA_SDQS6# DDRA_SDQS6

DDRA_SDQ50 DDRA_SDQ51

DDRA_SDQ57 DDRA_SDM7 DDRA_SDQ58

DDRA_SDQ59 D_CK_SDATA

D_CK_SCLK

+3VS

DIMM0 REV H:10.1mm (BOT)

1

C172

0.1U_0402_16V4Z

0.1U_0402_16V4Z 2

2

5

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_ASOA426-M4R-TR

CONN@

DQ4 DQ5

DM0 DQ6

DQ7

DQ12 DQ13

DM1

CK0#

DQ14 DQ15

DQ20 DQ21

DM2

DQ22 DQ23

DQ28 DQ29

DQS3#

DQS3 DQ30

DQ31

NC/CKE1

VDD NC/A15 NC/A14

VDD

RAS#

VDD

ODT0

NC/A13

VDD

DQ36 DQ37

DM4

DQ38 DQ39

DQ44 DQ45

DQS5#

DQS5 DQ46

DQ47 DQ52

DQ53

CK1#

DM6

DQ54 DQ55

DQ60 DQ61

DQS7#

DQS7 DQ62

DQ63

SAO

VSS

VSS VSS

VSS

VSS VSS

CK0 VSS

VSS

BA1

VSS

VSS VSS

VSS

VSS CK1

VSS VSS

VSS

VSS SA1

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

42 44 46 48 50

NC

52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90

A11

92

A7

94

A6

96 98

A4

100

A2

102

A0

104 106 108 110

S0#

112 114 116 118 120

NC

122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200

DDRA_SDQ4

DDRA_SDM0 DDRA_SDQ6

DDRA_SDQ7 DDRA_SDQ12

DDRA_SDQ13 DDRA_SDM1

DDRA_SDQ14 DDRA_SDQ15

DDRA_SDQ20 DDRA_SDQ21

DDRA_SDM2 DDRA_SDQ22

DDRA_SDQ23 DDRA_SDQ28

DDRA_SDQS3# DDRA_SDQS3

DDRA_SDQ30 DDRA_SDQ31

DDRA_CKE1DDRA_CKE0

DDRA_SMA14 DDRA_SMA11

DDRA_SMA7 DDRA_SMA6

DDRA_SMA4 DDRA_SMA2 DDRA_SMA0

DDRA_SBS1# DDRA_SRAS# DDRA_SCS0#

DDRA_ODT0 DDRA_SMA13

DDRA_SDQ36 DDRA_SDQ37

DDRA_SDM4 DDRA_SDQ38

DDRA_SDQ39 DDRA_SDQ44

DDRA_SDQ45 DDRA_SDQS5#

DDRA_SDQS5 DDRA_SDQ46

DDRA_SDQ47 DDRA_SDQ52

DDRA_SDQ53

DDRA_SDM6 DDRA_SDQ54

DDRA_SDQ55 DDRA_SDQ60DDRA_SDQ56

DDRA_SDQ61 DDRA_SDQS7#

DDRA_SDQS7 DDRA_SDQ62

DDRA_SDQ63

R116 10K_0402_5%R116 10K_0402_5%

1 2

R115 10K_0402_5%R115 10K_0402_5%

1 2

4

DDRA_CLK0 <8> DDRA_CLK0# <8>

PM_EXTTS#0 <8>

DDRA_SDQS3# <9> DDRA_SDQS3 <9>

DDRA_CKE1 <8>

DDRA_SBS1# <9> DDRA_SRAS# <9> DDRA_SCS0# <8>

DDRA_ODT0 <8>

DDRA_SDQS5# <9> DDRA_SDQS5 <9>

DDRA_CLK1 <8> DDRA_CLK1# <8>

DDRA_SDQS7# <9> DDRA_SDQS7 <9>

+DIMM_VREF

20mils

1

C151

0.1U_0402_16V4Z

2

DDRA_SMA[0..14]<9> DDRA_SDQ[0..63]<9>

DDRA_SDM[0..7]<9>

DDRA_CKE0 DDRA_SBS2#

DDRA_SMA12 DDRA_SMA9

DDRA_SMA8 DDRA_SMA5

DDRA_SMA3 DDRA_SMA1

DDRA_SMA10 DDRA_SBS0#

DDRA_SWE# DDRA_SCAS#

DDRA_SCS1# DDRA_ODT1

DDRA_SMA14 DDRA_SMA11

DDRA_SMA7 DDRA_SMA6

DDRA_SMA4 DDRA_SMA2

DDRA_SMA0 DDRA_SBS1#

DDRA_SRAS# DDRA_SCS0#

DDRA_SMA13 DDRA_ODT0

DDRA_CKE1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DDRA_SMA[0..14] DDRA_SDQ[0..63] DDRA_SDM[0..7]

1 4 2 3

RP1 56_0404_4P2R_5%RP1 56_0404_4P2R_5%

1 4 2 3

RP2 56_0404_4P2R_5%RP2 56_0404_4P2R_5%

1 4 2 3

RP3 56_0404_4P2R_5%RP3 56_0404_4P2R_5%

1 4 2 3

RP4 56_0404_4P2R_5%RP4 56_0404_4P2R_5%

1 4 2 3

RP5 56_0404_4P2R_5%RP5 56_0404_4P2R_5%

1 4 2 3

RP6 56_0404_4P2R_5%RP6 56_0404_4P2R_5%

1 4 2 3

RP7 56_0404_4P2R_5%RP7 56_0404_4P2R_5%

1 4 2 3

RP8 56_0404_4P2R_5%RP8 56_0404_4P2R_5%

1 4 2 3

RP9 56_0404_4P2R_5%RP9 56_0404_4P2R_5%

1 4 2 3

RP10 56_0404_4P2R_5%RP10 56_0404_4P2R_5%

1 4 2 3

RP11 56_0404_4P2R_5%RP11 56_0404_4P2R_5%

1 4 2 3

RP12 56_0404_4P2R_5%RP12 56_0404_4P2R_5%

1 4 2 3

RP13 56_0404_4P2R_5%RP13 56_0404_4P2R_5%

1 2

R1198 56_0402_5%R1198 56_0402_5%

Compal Secret Data

2008/03/28 2008/09/20

Compal Secret Data

+1.8V

R1196

R1196 1K_0402_1%

1K_0402_1%

R1197

R1197 1K_0402_1%

1K_0402_1%

+0.9VS

Deciphered Date

12

C152

2.2U_0603_6.3V6K

C156

0.1U_0402_16V4Z

C158

0.1U_0402_16V4Z

C163

0.1U_0402_16V4Z

C168

0.1U_0402_16V4Z

20mils

+1.8V

1

2

+1.8V

1

2

+0.9VS

1

2

+0.9VS

1

2

+0.9VS

1

2

To SODIMM and GMCH

+DIMM_VREF

1

C153

C147

2.2U_0603_6.3V6K

2

2.2U_0603_6.3V6K

1

C149

C148

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

C159

C160

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

C164

C165

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

C169

C170

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

C154

2

2.2U_0603_6.3V6K

1

C157

2

0.1U_0402_16V4Z

1

C161

2

0.1U_0402_16V4Z

1

C166

2

0.1U_0402_16V4Z

1

2

Title

Size Document Number Rev

B

Date: Sheet

Date: Sheet of

1

C155

2.2U_0603_6.3V6K

2

1

2

1

C162

0.1U_0402_16V4Z

2

1

C167

0.1U_0402_16V4Z

2

401597

1

2

1

2

1

2

Compal Electronics, Inc.

SCHEMATIC,A4491

1

C

of

14 52Thursday, October 30, 2008

A

+1.8V +1.8V

JDIMM2

+DIMM_VREF

DDRB_SDQ0 DDRB_SDQ5

DDRB_SDQS0#<9>

1 1

DDRB_SDQS0<9>

DDRB_SDQS1#<9> DDRB_SDQS1<9>

DDRB_SDQS2#<9> DDRB_SDQS2<9>

2 2

DDRB_CKE0<8>

DDRB_SBS2#<9>

DDRB_SBS0#<9> DDRB_SWE#<9>

DDRB_SCAS#<9> DDRB_SCS1#<8>

DDRB_ODT1<8>

DDRB_SDQS4#<9> DDRB_SDQS4<9>

3 3

DDRB_SDQS6#<9> DDRB_SDQS6<9>

D_CK_SDATA<14,16> D_CK_SCLK<14,16>

4 4

DDRB_SDQS0# DDRB_SDQS0

DDRB_SDQ2 DDRB_SDQ3

DDRB_SDQ8 DDRB_SDQ9

DDRB_SDQS1# DDRB_SDQS1

DDRB_SDQ10 DDRB_SDQ11

DDRB_SDQ16

DDRB_SDQS2# DDRB_SDQS2

DDRB_SDQ18 DDRB_SDQ19

DDRB_SDQ24 DDRB_SDQ25

DDRB_SDM3

DDRB_SDQ26 DDRB_SDQ30 DDRB_SDQ27

DDRB_CKE0

DDRB_SBS2# DDRB_SMA12

DDRB_SMA9 DDRB_SMA8

DDRB_SMA5 DDRB_SMA3 DDRB_SMA1

DDRB_SMA10 DDRB_SBS0# DDRB_SWE#

DDRB_SCAS# DDRB_SCS1#

DDRB_ODT1 DDRB_SDQ32

DDRB_SDQ33 DDRB_SDQS4#

DDRB_SDQS4 DDRB_SDQ34

DDRB_SDQ35 DDRB_SDQ40

DDRB_SDQ41 DDRB_SDM5 DDRB_SDQ42

DDRB_SDQ43 DDRB_SDQ48

DDRB_SDQ49

DDRB_SDQS6# DDRB_SDQS6

DDRB_SDQ50 DDRB_SDQ51

DDRB_SDQ56

DDRB_SDM7 DDRB_SDQ58

DDRB_SDQ59 D_CK_SDATA

D_CK_SCLK

+3VS

DIMM1 REV H:5.6mm (BOT)

A

JDIMM2

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_AS0A426-N8RN-7F

CONN@

VSS DQ4 DQ5

VSS DM0

VSS DQ6 DQ7

VSS

DQ12 DQ13

VSS DM1

VSS

CK0

CK0#

VSS

DQ14 DQ15

VSS

DQ20 DQ21

VSS DM2

VSS

DQ22 DQ23

VSS

DQ28 DQ29

VSS

DQS3#

DQS3

VSS

DQ30 DQ31

VSS

NC/CKE1

VDD

NC/A15 NC/A14

VDD

BA1

RAS#

VDD

ODT0

NC/A13

VDD

VSS

DQ36 DQ37

VSS DM4

VSS

DQ38 DQ39

VSS

DQ44 DQ45

VSS

DQS5#

DQS5

VSS

DQ46 DQ47

VSS

DQ52 DQ53

VSS

CK1

CK1#

VSS DM6

VSS

DQ54 DQ55

VSS

DQ60 DQ61

VSS

DQS7#

DQS7

VSS

DQ62 DQ63

VSS

SA0

SA1

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

42 44 46 48 50

NC

52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90

A11

92

A7

94

A6

96 98

A4

100

A2

102

A0

104 106 108 110

S0#

112 114 116 118 120

NC

122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200

B

DDRB_SDQ4 DDRB_SDQ1

DDRB_SDM0 DDRB_SDQ6

DDRB_SDQ7 DDRB_SDQ12

DDRB_SDQ13 DDRB_SDM1

DDRB_SDQ14 DDRB_SDQ15

DDRB_SDQ20 DDRB_SDQ21DDRB_SDQ17

DDRB_SDM2 DDRB_SDQ22

DDRB_SDQ23 DDRB_SDQ28

DDRB_SDQ29 DDRB_SDQS3#

DDRB_SDQS3

DDRB_SDQ31 DDRB_CKE1

DDRB_SMA14 DDRB_SMA11

DDRB_SMA7 DDRB_SMA6

DDRB_SMA4 DDRB_SMA2 DDRB_SMA0

DDRB_SBS1# DDRB_SRAS# DDRB_SCS0#

DDRB_ODT0 DDRB_SMA13

DDRB_SDQ36 DDRB_SDQ37

DDRB_SDM4 DDRB_SDQ38

DDRB_SDQ39 DDRB_SDQ44

DDRB_SDQ45 DDRB_SDQS5#

DDRB_SDQS5 DDRB_SDQ46

DDRB_SDQ47 DDRB_SDQ52

DDRB_SDQ53

DDRB_SDM6 DDRB_SDQ54

DDRB_SDQ55 DDRB_SDQ60

DDRB_SDQ61DDRB_SDQ57 DDRB_SDQS7#

DDRB_SDQS7 DDRB_SDQ62

DDRB_SDQ63

R119 10K_0402_5%R119 10K_0402_5%

1 2

R118 10K_0402_5%R118 10K_0402_5%

1 2

B

DDRB_CLK0 <8> DDRB_CLK0# <8>

PM_EXTTS#1 <8>

DDRB_SDQS3# <9> DDRB_SDQS3 <9>

DDRB_CKE1 <8>

DDRB_SBS1# <9> DDRB_SRAS# <9> DDRB_SCS0# <8>

DDRB_ODT0 <8>

DDRB_SDQS5# <9> DDRB_SDQS5 <9>

DDRB_CLK1 <8> DDRB_CLK1# <8>

DDRB_SDQS7# <9> DDRB_SDQS7 <9>

+3VS

C

DDRB_SBS2# DDRB_CKE0

DDRB_SMA12 DDRB_SMA9

DDRB_SMA5 DDRB_SMA8

DDRB_SMA3 DDRB_SMA1

DDRB_SMA10 DDRB_SBS0#

DDRB_SWE# DDRB_SCAS#

DDRB_SCS1# DDRB_ODT1

DDRB_SMA11 DDRB_SMA14

DDRB_SMA6 DDRB_SMA7

DDRB_SMA2 DDRB_SMA4

DDRB_SBS1# DDRB_SMA0

DDRB_SCS0# DDRB_SRAS#

DDRB_SMA13 DDRB_ODT0

DDRB_CKE1

C

1

C182

2

0.1U_0402_16V4Z

DDRB_SMA[0..14] DDRB_SDQ[0..63] DDRB_SDM[0..7]

+0.9VS

1 4 2 3

RP14 56_0404_4P2R_5%RP14 56_0404_4P2R_5%

1 4 2 3

RP15 56_0404_4P2R_5%RP15 56_0404_4P2R_5%

1 4 2 3

RP16 56_0404_4P2R_5%RP16 56_0404_4P2R_5%

1 4 2 3

RP17 56_0404_4P2R_5%RP17 56_0404_4P2R_5%

1 4 2 3

RP18 56_0404_4P2R_5%RP18 56_0404_4P2R_5%

1 4 2 3

RP19 56_0404_4P2R_5%RP19 56_0404_4P2R_5%

1 4 2 3

RP20 56_0404_4P2R_5%RP20 56_0404_4P2R_5%

1 4 2 3

RP21 56_0404_4P2R_5%RP21 56_0404_4P2R_5%

1 4 2 3

RP22 56_0404_4P2R_5%RP22 56_0404_4P2R_5%

1 4 2 3

RP23 56_0404_4P2R_5%RP23 56_0404_4P2R_5%

1 4 2 3

RP24 56_0404_4P2R_5%RP24 56_0404_4P2R_5%

1 4 2 3

RP25 56_0404_4P2R_5%RP25 56_0404_4P2R_5%

1 4 2 3

RP26 56_0404_4P2R_5%RP26 56_0404_4P2R_5%

1 2

R1199 56_0402_5%R1199 56_0402_5%

Compal Secret Data

2008/03/28 2008/09/20

Compal Secret Data

Deciphered Date

1

C173

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K 2

DDRB_SMA[0..14]<9>

DDRB_SDQ[0..63]<9>

DDRB_SDM[0..7]<9>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

+1.8V+DIMM_VREF

1

+

C1526

2

330U_D2E_2.5VM_R15

+1.8V

1

C174

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K 2

2.2U_0603_6.3V6K

+1.8V

1

C178

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

+0.9VS

1

C184

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

+0.9VS

1

C189

0.1U_0402_16V4Z

0.1U_0402_16V4Z 2

+0.9VS

1

C194

0.1U_0402_16V4Z

0.1U_0402_16V4Z 2

0.1U_0402_16V4Z

D

1

+

C1527

2

330U_D2E_2.5VM_R15

@

1

C175

2

1

C179

2

1

C185

2

1

C190

2

0.1U_0402_16V4Z

1

C195

2

1

C176

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K 2

2.2U_0603_6.3V6K

1

C180

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

C186

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

C191

0.1U_0402_16V4Z

0.1U_0402_16V4Z 2

0.1U_0402_16V4Z

1

C196

0.1U_0402_16V4Z

0.1U_0402_16V4Z 2

E

1

C183

C181

C187

C192

Title

Size Document Number Rev

B

Date: Sheet

1

C177

2.2U_0603_6.3V6K

2

1

2

1

C188

2

0.1U_0402_16V4Z

1

C193

0.1U_0402_16V4Z

2

Compal Electronics, Inc.

SCHEMATIC,A4491

401597

of

15 52Thursday, October 30, 2008

E

C

A

FSLC FSLB FSLA CPU

CLKSEL2 CLKSEL1 CLKSEL0

0 0 0 266 100 33.3

10

1 1

01

CLK_REQ#

CR#_10(WLAN) PCIEX10 PCIEX0 CR#_6(MCH) CR#_4(NEW CARD) CR#_9(MINI CARDII)

SRC7(VGA_CLK): Discrete VGA[Enable] UMA[Disable]

+3VS

1 2

R1829 10K_0402_5%

1 2

PM@

R1584 10K_0402_5%R1584 10K_0402_5%

CLK_PCI2=1, Trusted Mode Enable(No overclocking allowed)

1 2

R1585 10K_0402_5%

@

1 2

2 2

3 3

4 4

R1586 10K_0402_5%R1586 10K_0402_5%

CLK_PCI5=0, Pin63,64 is SRC_CLK CLK_PCI5=1, Pin63,64 is ITP_CLK

1 2

R1587 10K_0402_5%

CLK_PCI4=0, Pin28, 29 is SRC_CLK

GM@

Pin24, 25 is DOT96_CLK

1 2

R1588 10K_0402_5%

@

C1898 10P_0402_50V8J

1 2

C1899 10P_0402_50V8J

1 2

@

@ @

@

+1.05VS

R1594

2.2K_0402_5%

CLKSEL0

CLKSEL1

CLKSEL2

1 2

R1597

R1597 1K_0402_5%

1K_0402_5%

1 2

R1604

R1604 0_0402_5%

0_0402_5%

@

R1610

R1610 10K_0402_5%

10K_0402_5%

1 2

R1612

R1612 0_0402_5%

0_0402_5%

@

A

@

+1.05VS

1 2

@

+1.05VS

1 2

@

MHz

200 100 33.3

0 1

Control

PCIEX6 PCIEX4 PCIEX9

CLK_PCI4

CLK_PCI2

CLK_PCI5

CLK_PCI4

CK_PWRGD

For EMI 10/9

R1593

56_0402_5%

56_0402_5% R1595

R1595 1K_0402_5%

1K_0402_5%

1 2

R1598

R1598 0_0402_5%

0_0402_5%

R1600

1K_0402_5%

1K_0402_5% R1601

R1601 1K_0402_5%

1K_0402_5%

1 2

R1605

R1605 0_0402_5%

0_0402_5%

R1609

1K_0402_5%

1K_0402_5% R1611

R1611 1K_0402_5%

1K_0402_5%

1 2

R1613

R1613 0_0402_5%

0_0402_5%

Table : ICS9LPRS387

mount to Enable ITP_CLK

SRC MHz

CLK_PCI_LPC CLK_PCI_ICH

MCH_CLKSEL0 <8>

MCH_CLKSEL1 <8>

CPU_BSEL1 <5>

MCH_CLKSEL2 <8>

CPU_BSEL2 <5>

B

PCI MHz

33.3100166

Free-Run

PCIEX1

+3VS

1 2 13

D

@

S

@

CPU_BSEL0 <5>

B

C

+CLK_VDDSRC

L56

+1.05VS

CLK_DREF_SSC_1

CLK_DREF_SSC#_1

L56

KC FBM-L11-201209-221LMAT_0805

1

C1882

C1882 10U_0805_10V4Z

10U_0805_10V4Z

2

GM@

PM@

GM@

PM@

R17550_0402_5%

12

R17560_0402_5%

12

R18270_0402_5%

12

R18280_0402_5%

12

C1883

C1883 10U_0805_10V4Z

10U_0805_10V4Z

CLK_DREF_SSC

CLK_DREF_SSC#

1

2

+CLK_VDDSRC

Must Close to CLKGEN PIN 28,29

R1583

R1583 10K_0402_5%

10K_0402_5%

CK505_PWRGD

2

G

Q106

Q106 2N7002_SOT23

2N7002_SOT23

CLK_PCI_LPC<35>

CLK_PCI_ICH<25>

CLK_ICH_48M<27>

CLK_ICH_14M<27>

ICH_SMBDATA<27,31,33,34>

ICH_SMBCLK<27,31,33,34>

CLK_ENABLE# <49>

CLK_PCI_LPC CLK_PCI3

CLK_PCI_ICH CLK_PCI5

CK_PWRGD<27>

VGATE<8,27,49>

C1900

1 2

27P_0402_50V8J

C1901

27P_0402_50V8J

1 2

CLK_ICH_48M

C

H_STP_CPU#<27>

H_STP_PCI#<27>

R1589 33_0402_5%R1589 33_0402_5%

R1590 33_0402_5%R1590 33_0402_5%

12

Y1

14.31818MHz_20P_FSX8L14.318181M20FDB

R1596 33_0402_5%R1596 33_0402_5%

R1599 33_0402_5%R1599 33_0402_5%

+3VS

R1602

4.7K_0402_5%

2

G

1 2

+3VS

2

S

Q107

Q107 2N7002_SOT23

2N7002_SOT23

R1608

4.7K_0402_5%

G

1 2

S

Q108

Q108 2N7002_SOT23

2N7002_SOT23

D_CK_SDATA

D_CK_SCLK

1 3

D

1 3

D

1

C1884

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

CLK_DREF_SSC <8>

27M_CLK <18>

CLK_DREF_SSC# <8>

27M_SSC <18>

H_STP_CPU# H_STP_PCI#

12

R15910_0402_5% R15910_0402_5%

12

R15920_0402_5%

12

@

CLK_XTALIN CLK_XTALOUT

12

+3VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

1

C1885

2

0.1U_0402_16V4Z

+CLK_VDD

CLK_PCI2

CLK_PCI4

CK505_PWRGD

CLKSEL0 CLKSEL1 CLKSEL2CLK_ICH_14M

1

C1886

C1887

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

U43

6

VDDREF

19

VDD48

72

VDDCPU

12

VDDPCI

27

VDDPLL3

55

VDDSRC

52

VDDSRC_IO

38

VDDSRC_IO

62

VDDSRC_IO

31

VDDPLL3_IO

66

VDDCPU_IO

23

VDD96_IO

53

CPU_STOP#

54

PCI_STOP#

13

PCI1

14

PCI2/TME

15

PCI3

16

PCI4/27_SELECT

17

PCI_F5/ITP_EN

1

CK_PWRGD/PD#

5

X1

4

X2

11

NC

20

USB_48MHz/FSLA

2

FSLB/TEST_MODE

7

FSLC/TEST_SEL/REF0

8

REF1

69

GNDCPU

3

GNDREF

18

GNDPCI

22

GND48

30

GND

26

GND

34

GNDSRC

59

GNDSRC

42

GNDSRC

73

GND_THERMAL_PAD

ICS9LPRS387BKLFT_MLF72_10x10

2008/03/28 2008/09/20

E

L57

1

C1888

0.1U_0402_16V4Z

2

ICS9LPRS387, PN:SA000020H10 SLG8SP556V, PN:SA000020K00

E

+3VS

1

C1889

2

Compal Secret Data

Deciphered Date

L57

KC FBM-L11-201209-221LMAT_0805

1

C1890

C1890 10U_0805_10V4Z

10U_0805_10V4Z

2

CPUT0_LPR_F

CPUC0_LPR_F

CPUT1_LPR_F

CPUC1_LPR_F

SRCT0_LPR/DOTT_96_LPR

SRCC0_LPR/DOTC_96_LPR

27MHz_NonSS/SRCT1_LPR/SE1

27MHz_SS/SRCC1_LPR/SE2

SRCT2_LPR/SATAT_LPR

SRCC2_LPR/SATAC_LPR

CPUT2_ITP_LPR/SRCT8_LPR

CPUC2_ITP_LPR/SRCC8_LPR

F

SDATA

SCLK

SRCT3_LPR SRCC3_LPR

SRCT4_LPR SRCC4_LPR

SRCT6_LPR SRCC6_LPR

SRCT7_LPR SRCC7_LPR

SRCT9_LPR SRCC9_LPR

SRCT10_LPR SRCC10_LPR

SRCT11_LPR SRCC11_LPR

CR#3 CR#4 CR#6 CR7#

CR#9 CR10# CR#11

CR#A

F

12

9 10

71 70

68 67

24 25

28 29

32 33

35 36

39 40

57 56

61 60

64 63

44 45

50 51

48 47

37 41 58 65 43 49 46 21

+CLK_VDD

1

C1891

0.1U_0402_16V4Z

2

10U_0805_10V4Z

D_CK_SDATA D_CK_SCLK

CLK_CPU_BCLK CLK_CPU_BCLK#

CLK_MCH_BCLK CLK_MCH_BCLK#

CLK_DREF_96M CLK_DREF_96M#

CLK_DREF_SSC_1 CLK_DREF_SSC#_1

CLK_PCIE_SATA CLK_PCIE_SATA#

CLK_PCIE_ICH CLK_PCIE_ICH#

CLK_PCIE_CARD CLK_PCIE_CARD#

CLK_MCH_3GPLL CLK_MCH_3GPLL#

CLK_PCIE_VGA CLK_PCIE_VGA#

CLK_PCIE_READER CLK_PCIE_READER#

CLK_PCIE_MINI2 CLK_PCIE_MINI2#

CLK_PCIE_MINI1 CLK_PCIE_MINI1#

CLK_PCIE_LAN CLK_PCIE_LAN#

(Pull High to +3VS at GMCH side)

(Pull High to +3VS at ICH side)

G

H

Clock Generator

1

C1893

0.1U_0402_16V4Z

2

D_CK_SDATA <14,15>

D_CK_SCLK <14,15>

CLK_CPU_BCLK <4> CLK_CPU_BCLK# <4>

CLK_MCH_BCLK <7> CLK_MCH_BCLK# <7>

CLK_DREF_96M <8> CLK_DREF_96M# <8>

1

C1894

2

0.1U_0402_16V4Z

C1892

2

0.1U_0402_16V4Z

VGA: disable this pair by BIOS

UMA: disable this pair by BIOS

1 2

R1603 10K_0402_5%R1603 10K_0402_5%

1 2

R1606 10K_0402_5%R1606 10K_0402_5%

1 2

R1607 10K_0402_5%R1607 10K_0402_5%

Title

Size Document Number Rev

Custom

Date: Sheet

CLK_PCIE_SATA <26> CLK_PCIE_SATA# <26>

CLK_PCIE_ICH <27> CLK_PCIE_ICH# <27>

CLK_PCIE_CARD <34> CLK_PCIE_CARD# <34>

CLK_MCH_3GPLL <8> CLK_MCH_3GPLL# <8>

CLK_PCIE_VGA <17> CLK_PCIE_VGA# <17>

CLK_PCIE_READER <30> CLK_PCIE_READER# <30>

CLK_PCIE_MINI2 <33> CLK_PCIE_MINI2# <33>

CLK_PCIE_MINI1 <33> CLK_PCIE_MINI1# <33>

CLK_PCIE_LAN <31> CLK_PCIE_LAN# <31>

+3VS

+3VS +3VS

Compal Electronics, Inc.

SCHEMATIC,A4491

401597

G

1

C1896

C1895

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

EXP_CLKREQ# <34> MCH_CLKREQ# <8>

MINI2_CLKREQ# <33> MINI1_CLKREQ# <33>

SATA_CLKREQ# <27>

1

2

C1897

16 52Thursday, October 30, 2008

H

of

C