ZMD ZMD31050 Datasheet

(4 to 20) mA configuration [(7 to 40) V],

Refer also chapter

2

for additional application circuits and details.

ZMD31050

Advanced Differential Sensor Signal Conditioner

Datasheet

Features

• Digital compensation of sensor offset, sensitivity,
temperature drift and non-linearity

• Accommodates nearly all bridge sensor types
(signal spans from 1 up to 275mV/V processable)

• Digital one-shot calibration: quick and precise

• Selectable compensation temperature T1 source:

bridge, thermistor, internal diode or external diode

• Output options: voltage (0V to 5V),
current (4mA to 20mA), PWM, I2C, SPI,
ZACwire

TM

(one-wire-interface), alarm

• Adjustable output resolution (up to 15 bits) versus
sampling rate (up to 3.9kHz)

• Selectable bridge excitation: ratiometric voltage,
constant voltage or constant current

• Input channel for separate temperature sensor

• Sensor connection and common mode check

(Sensor aging detection)

• Operation temperature -40 to +125°C (-40 to
+150°C derated, depending on product version)

• Supply voltage +2.7V to +5.5V

• Available in SSOP16 or as die

Benefits

• No external trimming components required

• PC-controlled configuration and calibration via

digital bus interface - simple, low cost

• High accuracy (±0.1% FSO @ -25°C to 85°C;
±0.25% FSO @ -40°C to 125°C)

Application Circuit (Examples)

Brief Description

ZMD31050 is a CMOS integrated circuit for highly­accurate amplification and sensor-specific correction
of bridge sensor signals. The device provides digital
compensation of sensor offset, sensitivity,
temperature drift and non-linearity by a 16-bit RISC
micro controller running a correction algorithm with
correction coefficients stored in non-volatile
EEPROM.

The ZMD31050 accommodates virtually any bridge
sensor (e.g. piezo-resistive, ceramic-thick film or steel
membrane based). In addition, the IC can interface a
separate temperature sensor.

The bi-directional digital interfaces (I2C, SPI,
ZACwireTM) can be used for a simple PC-controlled
one-shot calibration procedure, in order to program a
set of calibration coefficients into an on-chip
EEPROM. Thus a specific sensor and a ZMD31050
are mated digitally: fast, precise and without the cost
overhead associated with laser trimming, or
mechanical potentiometer methods.

 Application kit available (SSOP16 samples,

calibration PCB, calibration software, technical
documentation)

 Support for industrial mass calibration

available

 Quick circuit customization possible for large

production volumes

Fig.1: Ratiometric measurement with voltage output,

temperature compensation via external diode

Datasheet, Rev. 1.0, April 11, 2006 Page 1 of 19 © ZMD AG, 2006
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior

written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

Fig.2: Two-wire-

temperature compensation via internal diode

ZMD31050

Advanced Differential Sensor Signal Conditioner

Datasheet

Contents

1.

CIRCUIT DESCRIPTION ..............................................................................................................3

1.1 S

1.2 A

1.3 A

1.4 S

1.5 O

1.6 V

1.7 W

IGNAL FLOW
PPLICATION MODES
NALOG FRONT END

1.3.1. Programmable Gain Amplifier ............................................................................................. 5

1.3.2. Extended Zero Point Compensation (XZC).........................................................................5

1.3.3. Measurement Cycle realized by Multiplexer........................................................................6

1.3.4. Analog-to-Digital Converter ................................................................................................. 7

YSTEM CONTROL

UTPUT STAGE

1.5.1. Analog Output ...................................................................................................................10

1.5.2. Comparator Module (ALARM Output) ............................................................................... 10

1.5.3. Serial Digital Interface ....................................................................................................... 10

OLTAGE REGULATOR

ATCHDOG AND ERROR DETECTION

.............................................................................................................................. 3

...................................................................................................................4

(AFE) .........................................................................................................5

....................................................................................................................... 8

........................................................................................................................... 9

...............................................................................................................11

..........................................................................................11

2.

3.

4.

5.

5.1 A

5.2 O

5.3 B

5.4 E

5.5 I

6.

7.

8.

APPLICATION CIRCUIT EXAMPLES........................................................................................12

ESD/LATCH-UP-PROTECTION.................................................................................................13

PIN CONFIGURATION AND PACKAGE ...................................................................................13

IC CHARACTERISTICS ............................................................................................................. 14

BSOLUTE MAXIMUM RATINGS

PERATING CONDITIONS (VOLTAGES RELATED TO
UILD IN CHARACTERISTICS
LECTRICAL PARAMETERS (VOLTAGES RELATED TO

NTERFACE CHARACTERISTICS

RELIABILITY .............................................................................................................................. 19

CUSTOMIZATION ...................................................................................................................... 19

RELATED DOCUMENTS ...........................................................................................................19

...................................................................................................14

VSS) .......................................................14

.......................................................................................................15

VSS)...................................................... 17

...................................................................................................18

Datasheet, Rev. 1.0, April 11, 2006 Page 2 of 19 © ZMD AG, 2006
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior

written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

ZMD31050

Advanced Differential Sensor Signal Conditioner

Datasheet

1. Circuit Description

1.1 Signal Flow

Fig.3: ZMD31050 Block Diagram

PGA Programmable gain amplifier
MUX Multiplexer
ADC Analog-to-digital converter
CMC Calibration microcontroller
DAC Digital-to-analog converter
FIO1 Flexible I/O 1: analog out (voltage/current), PWM2,

ZACwire

FIO2 Flexible I/O 2: PWM1, SPI data out, SPI slave select, Alarm1, Alarm2
SIF Serial interface: I2C data I/O, SPI data in, clock

PCOMP Programmable comparator
EEPROM Non volatile memory for calibration parameters and configuration
TS On-chip temperature sensor (pn-junction)
ROM Memory for correction formula and –algorithm
PWM PWM module

TM

(one-wire-interface)

The ZMD31050’s signal path is partly analog (blue) and partly digital (red). The analog part is realized
differential – this means internal is the differential bridge sensor signal also handled via two signal
lines, which are rejected symmetrically around a common mode potential (analog ground = VDDA/2).
Consequently it is possible to amplify positive and negative input signals, which are located in the
common mode range of the signal input.
The differential signal from the bridge sensor is pre-amplified by the programmable gain amplifier
(PGA). The Multiplexer (MUX) transmits the signals from bridge sensor, external diode or separate

Datasheet, Rev. 1.0, April 11, 2006 Page 3 of 19 © ZMD AG, 2006
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior

written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

ZMD31050

Advanced Differential Sensor Signal Conditioner

Datasheet

temperature sensor to the ADC in a certain sequence (instead of the temperature diode the internal pn­junction (TS) can be used optionally). Afterwards the ADC converts these signals into digital values.
The digital signal correction takes place in the calibration micro-controller (CMC). It is based on a
special correction formula located in the ROM and on sensor-specific coefficients (stored into the
EEPROM during calibration). Dependent on the programmed output configuration the corrected sensor
signal is output as analog value, as PWM signal or in digital format (SPI, I2C,

ZACwire

signal is provided at 2 flexible I/O modules (FIO) and at the serial interface (SIF). The configuration
data and the correction parameters can be programmed into the EEPROM via the digital interfaces.
The modular circuit concept enables fast custom designs varying these blocks and, as a result,
functionality and die size.

1.2 Application Modes

For each application a configuration set has to be established (generally prior to calibration) by
programming the on-chip EEPROM regarding to the following modes:

 Sensor channel

− Sensor mode: ratiometric voltage or current supply mode.

− Input range: The gain of the analog front end has to be chosen with respect to the maximum

sensor signal span and to this has also adjusted the zero point of the ADC

− Additional offset compensation: The extended analog offset compensation has to be enabled if
required, e.g. if the sensor offset voltage is near to or larger than the sensor span.

− Resolution/response time: The A/D converter has to be configured for resolution and converting
scheme (first or second order). These settings influence the sampling rate, signal integration time
and this way the noise immunity. The Sample Order influences the response time too.

− Ability to invert the sensor bridge inputs

 Analog output

− Choice of output method (voltage value, current loop, PWM) for output register 1.

− Optional choice of additional output register 2: PWM via IO1 or alarm out module via IO1/2.

 Digital communication: The preferred protocol and its parameter have to be set.
 Temperature

−

The temperature measure source for the temperature correction has to be chosen.

−

The temperature measure source T1 sensor type
(only T1 is usable

for correction!!!)

for the temperature correction has to be chosen

− Optional: the temperature measure channel as the second output has to be chosen.

 Supply voltage : For non-ratiometric output the voltage regulation has to be configured.

Note: Not all possible combinations of settings are allowed (see section 1.5).

The calibration procedure must include

− Set of coefficients of calibration calculation

and, depending on configuration,

− Adjustment of the extended offset compensation,

− Zero compensation of temperature measurement,

− Adjustment of the bridge current

and, if necessary,

− Set of thresholds and delays for the alarms and the reference voltage.

TM

). The output

Datasheet, Rev. 1.0, April 11, 2006 Page 4 of 19 © ZMD AG, 2006
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior

written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

ZMD31050

Advanced Differential Sensor Signal Conditioner

Datasheet

1.3 Analog Front End (AFE)

The analog front end consists of the programmable gain amplifier (PGA), the multiplexer (MUX) and the
analog-to-digital converter (ADC).

1.3.1. Programmable Gain Amplifier

The following tables show the adjustable gains, the processable sensor signal spans and the allowed
common mode range.

No. PGA

Gain a

1 420 30 7 2 2 43 - 57
2 280 30 4,66 2 3 40 - 59
3 210 15 7 2 4 43 - 57
4 140 15 4,66 2 6 40 - 59
5 105 15 3,5 2 8 38 - 62
6 70 7,5 4,66 2 12 40 - 59
7 52,5 7,5 3,5 2 16 38 - 62
8 35 3,75 4,66 2 24 40 - 59

9 26,3 3,75 3,5 2 32 38 - 62
10 14 1 7 2 50 43 - 57
11 9,3 1 4,66 2 80 40 - 59
12 7 1 3,5 2 100 38 - 62
13 2,8 1 1,4 2 280 21 - 76

Table 1: Adjustable gains, resulting sensor signal spans and common mode ranges

IN

Gain

Amp1

Gain

Amp2

Gain

Amp3

Max. span

V

in mV/V

IN_SP

Input range

V

in % VDDA

IN_CM

∗∗∗∗

1.3.2. Extended Zero Point Compensation (XZC)

The ZMD31050 supports two methods of sensor offset cancellation (zero shift):

• Digital offset correction

• XZC – an analog cancellation for large offset values (up to approx 300% of span)

The digital sensor offset correction will be processed at the digital signal correction/conditioning by the
CMC. The analog sensor offset pre-compensation will be needed for compensation of large offset
values, which would be overdrive the analog signal path by uncompensated gaining. For analog sensor
offset pre-compensation a compensation voltage will be added in the analog pre-gaining signal path
(coarse offset removal). The analog offset compensation in the AFE can be adjusted by 6 EEPROM
bits. It allows an analog zero point shift up to 300% of the processable signal span.

The zero point shift of the temperature measurements can also be adjusted by 6 EEPROM bits
(Z

= -20…+20) and is calculated by:

XZC

V

/ VDDBR= k * Z

XZC

/ ( 20 * aIN)

XZC

∗

Bridge in voltage mode, refer “ZMD31050 Functional description” for usable input signal/common mode range at bridge in current mode

Datasheet, Rev. 1.0, April 11, 2006 Page 5 of 19 © ZMD AG, 2006
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior

written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

ZMD31050

Advanced Differential Sensor Signal Conditioner

Datasheet

PGA gain

aIN

420 2 3,0 15% +/- 7 330

280 3 1,833 9% +/- 6 200

210 4 3,0 15% +/- 14 330

140 6 1,833 9% +/- 12 200

105 8 1,25 6% +/- 12 140

70 12 1,833 9% +/- 24 200

52,5 16 1,25 6% +/- 22 140

35 24 1,833 9% +/-48 200

26,3 32 1,25 6% +/- 45 140

14 50 3,0 15% +/- 180 330

9,3 80 1,833 9% +/- 160 200

7 100 1,25 6% +/- 140 140

2,8 280 0,2 1% +/- 60 22

Note: Z

Max. span

V

IN_SP

in mV/V

Calculation

factor k

Offset shift per step

in % full span

Approx. maximum

offset shift in mV/V

Approx. maximum

shift in [% V

Table 2: Extended Zero Point Compensation Range

can be adjusted in range –31 to 31, parameters are guaranteed only in range –20 to 20.

XZC

IN_SP]

(@ ± 20 steps)

1.3.3. Measurement Cycle realized by Multiplexer

The Multiplexer selects, depending on EEPROM settings, the following inputs in a certain sequence.

 Internal offset of the input channel measured by input short circuiting
 Bridge temperature signal measured by external and internal diode (pn-junction)
 Bridge temperature signal measured by bridge resistors
 Separate temperature signal measured by external thermistor
 Pre-amplified bridge sensor signal

The complete measurement cycle is
controlled by the CMC. The cycle diagram
at the right shows its principle structure.

The EEPROM adjustable parameters are:

 Pressure measurement count,

n=<1,2,4,8,16,32,64,128>

 Enable temperature measurement 2,

e2=<0,1>

After Power ON the start routine is called. It
contains the pressure and auto zero
measurement. When enabled it measures the

→

→

→

→

→

→

→

→

→

→

→

Start routine

n Pressure measurement

1 Temp 1 auto zero

n Pressure measurement

1 Temp 1 measurement

n Pressure measurement

1 Pressure auto zero

n * e2 Pressure measurement

e2 Temp 2 auto zero

n * e2

Pressure measurement

*

e2 * Temp 2 measurement

temperature and its auto zeros.

Fig. 4: Measurement cycle ZMD31050

Datasheet, Rev. 1.0, April 11, 2006 Page 6 of 19 © ZMD AG, 2006
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written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

ZMD31050

Advanced Differential Sensor Signal Conditioner

Datasheet

1.3.4. Analog-to-Digital Converter

The ADC is a charge balancing converter in full differential switched capacitor technique. It can be
used as first or second order converter:

In the first order mode it is inherently monotone and insensitive against short and long term instability
of the clock frequency. The conversion cycle time depends on the desired resolution and can be
roughly calculated by:

The available ADC-resolutions are r

In the second order mode two conversions are stacked with the advantage of much shorter
conversion cycle time and the drawback of a lower noise immunity caused by the shorter signal
integration period. The conversion cycle time at this mode is roughly calculated by:

The available ADC-resolutions are r

The result of the AD conversion is a relative counter result corresponding to the following equation:

Z

= 2

Z

: Number of counts (result of the conversion)

ADC

V

ADC_DIFF

V

ADC_REF

RS

With the RS

: Differential input voltage of ADC (= aIN * V

: Reference voltage of ADC (= VBR or VDDA)

: Digital ADC Range Shift (RS

ADC

value a sensor input signal can be shifted in the optimal input range of the ADC.

ADC

ADC

r

ADC

= 2

= 2

(r

ADC

t

CYC_1

= <9,10,11,12,13,14>.

ADC

t

CYC_2

= <11,12,13,14,15>.

ADC

r

ADC

* [(V

ADC_DIFF /VADC_REF

= 15/16, 7/8, 3/4, 1/2, controlled by the EEPROM content)

ADC

µµµµs

+3)/2

IN_DIFF

µµµµs

) + (1 – RS

)

ADC

)]

The Pin <VBR>-potential is used in “VBR=VREF” mode as AD converters reference voltage V

ADC_REF

Sensor bridges with no ratiometric behaviour (f.i. temperature compensated bridges), which are
supplied by a constant current, requires VDDA potential as V

ADC_REF

and this can be adjusted by in
configuration. If these mode is enabled, XZC can’t by used (adjustment=0), but it has to be enabled
(refer calculation sheet “ZMD31050_Bridge_Current_Excitation_Rev*.xls” for details).

Note: The AD conversion time (sample rate) is only a part of a whole signal conditioning cycle.

ADC Maximum Output Resolution Sample Rate f

Order r

O

Bit Bit Bit Bit Hz Hz

ADC

1
1
1
1
1
1

1

Digital-OUT Analog-OUT r

ADC

9 9 9 9 1302 1465
10 10 10 10 781 879
11 11 11 11 434 488
12 12 11 12 230 259
13 13 11 12 115 129
14 14 11 12 59 67

PWM

f

=2MHz f

CLK

CLK

CON

=2.25MHz

1

ADC Resolution should be 1 to 2 Bits higher then applied Output Resolution

Datasheet, Rev. 1.0, April 11, 2006 Page 7 of 19 © ZMD AG, 2006
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written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

.

ZMD31050

Advanced Differential Sensor Signal Conditioner

Datasheet

ADC Maximum Output Resolution Sample Rate f

Order r

O

Bit Bit Bit Bit Hz Hz

ADC

2
2
2
2
2
2

1

Digital-OUT Analog-OUT r

ADC

10 10 10 10 3906 4395
11 11 11 11 3906 4395
12 12 11 12 3906 4395
13 13 11 12 1953 2197
14 14 11 12 1953 2197
15 15 11 12 977 1099

PWM

f

=2MHz f

CLK

CLK

Table 3: Output Resolution versus Sample Rate

1.4 System Control

The system control has the following features:
 Control of the I/O relations and of the measurement cycle regarding to the EEPROM-stored

configuration data

 16 bit correction calculation for each measurement signal using the EEPROM stored calibration

coefficients and ROM-based algorithms

 Started by internal POC, internal clock – generator or external clock
 For safety improvement the EEPROM data are proved with a signature within initialization

procedure, the registers of the CMC are steadily observed with a parity check. Once an error is
detected, the error flag of the CMC is set and the outputs are driven to a diagnostic value

Note: The conditioning includes up to third order sensor input correction. The available adjustment

ranges depend on the specific calibration parameters, a detailed description will be issued later.
To give a rough idea: Offset compensation and linear correction are only limited by the loose of
resolution it will cause, the second order correction is possible up to about 20% full scale
difference to straight line, third order up to about 10% (ADC resolution = 13bit). The
temperature calibration includes first and second order correction and should be fairly sufficient
in all relevant cases. ADC resolution influences also calibration possibilities – 1 bit more
resolution reduces calibration range by approximately 50%.

CON

=2.25MHz

1

ADC Resolution should be 1 to 2 Bits higher then applied Output Resolution

Datasheet, Rev. 1.0, April 11, 2006 Page 8 of 19 © ZMD AG, 2006
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written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

The ZMD31050 provides the following I/O

Via these pins the following signal formats

can be output: Analog (voltage/current),

The following values can be provided at the

O/I pins: bridge sensor signal, temperature

The Alarm signal only refers to the bridge

sensor signal, but never to a temperature

Due to the necessary pin sharing there are

restrictions to the possible combinations of

overview about

In the SPI mode the pin IO2 is used as

Slave select. Thus no Alarm 2 can be output

ZMD31050

Advanced Differential Sensor Signal Conditioner

Datasheet

1.5 Output Stage

Used SIF Used I/O pins

No. I2C SPI OUT IO1 IO2 SDA

1 X Data I/O

2 X ALARM1 Data I/O

3 X ALARM2 Data I/O

4 X ALARM1 ALARM2 Data I/O

5 X PWM1 Data I/O

6 X PWM1 ALARM2 Data I/O

7 X Analog Data I/O

8 X Analog ALARM1

9 X Analog ALARM2 Data I/O

10 X Analog ALARM1 ALARM2 Data I/O

11 X Analog PWM1 Data I/O

12 X Analog PWM1 ALARM2 Data I/O

13 X PWM2 Data I/O

14 X PWM2 ALARM1 Data I/O

15 X PWM2 ALARM2 Data I/O

16 X PWM2 ALARM1 ALARM2 Data I/O

17 X PWM2 PWM1 Data I/O

18 X PWM2 PWM1 ALARM2 Data I/O

19 X Data out

20 X

21 X

22 X Analog Data out

23 X Analog

24 X Analog

25 X PWM2 Data out

26

27

X PWM2

X

PWM2 Data out

Data out
ALARM1

Data out

PWM1

Data out

ALARM1

Data out

PWM1

Data out

ALARM1

PWM1

Data I/O

Slave
select
Slave
select

­Slave
select

­Slave
select
Slave
select

­Slave
select

­Slave
select
Slave
select

­Slave
select

-

Data in

Data in

Data in

Data in

Data in

Data in

Data in

Data in

Data in

-

-

-

-

-

-

pins: OUT, IO1, IO2 and SDA.

PWM, Data (SPI/I2C), Alarm.

signal 1, temperature signal 2, alarm.

Note:

signal.

outputs and interface connections.
The table beside gives an
possible combinations.

Note:

in this mode.

Table 4: Output configurations overview

Datasheet, Rev. 1.0, April 11, 2006 Page 9 of 19 © ZMD AG, 2006
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ZMD31050

Advanced Differential Sensor Signal Conditioner

Datasheet

1.5.1. Analog Output

For the analog output 3 registers of 15 bit depth are available, which can store the actual pressure and
the results of temperature measurement 1 and 2. Each register can be independently switched to one
of two output slots connected to the Pin OUT and IO1 respectively. In these output slots different output
modules are available according to the following table:

Output slot: OUT IO1

Voltage x

PWM x x

Table 5: Analog output configuration

The voltage module consists of an 11bit resistor string – DAC with buffered output and a subsequent
inverting amplifier with class AB rail-to-rail OpAmp. The two feedback nets are connected to the Pins
FBN and FBP. This structure offers wide flexibility for the output configuration, for example voltage
output and 4 mA to 20 mA current loop output. To short circuit the analog output against VSS or VDDA
does not damage the ZMD31050.

The PWM module provides pulse streams with signal dependent duty cycle. The PWM – frequency
depends on resolution and clock divider. The maximum resolution is 12 bit, the maximum PWM –
frequency is 4 kHz (9 bit). If both, second PWM and SPI protocol are activated, the output pin IO1 is
shared between the PWM output and the SPI_SDO output of the serial interface (interface
communication interrupts the PWM output).

1.5.2. Comparator Module (ALARM Output)

The comparator module consists of two comparator channels connectable to IO1 and IO2 respectively.
Each of them can be independently programmed referring to the parameters threshold, hysteresis,
switching direction and on/off – delay. Additional a window comparator mode is available.

1.5.3. Serial Digital Interface

The ZMD31050 includes a serial digital interface which is able to communicate in three different
communication protocols – I2CTM, SPITM and ZACwire

TM

(one wire communication).

In the SPI mode the pin IO2 operates as slave select input, the pin IO1 as data output.

Initializing Communication

After power-on the interface is for about 20ms (start window) in the state ZACwire. During the start
window it is possible to communicate via the one wire interface (pin OUT).
Detecting a proper request inside the start window the interface stays in the state ZACwire. This state
can be left by certain commands or a new power-on.
If during the start window no request happens then the serial interface switches to I2C or SPI mode
(depending on EEPROM settings). The OUT pin is used as analog output or as PWM output (also
depending on EEPROM settings). The start window can generally be disabled (or enabled) by a special
EEPROM setting.
For detailed description of the serial interfaces see “ZMD31050 Functional Description”.

Datasheet, Rev. 1.0, April 11, 2006 Page 10 of 19 © ZMD AG, 2006
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written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

ZMD31050

Advanced Differential Sensor Signal Conditioner

Datasheet

1.6 Voltage Regulator

For ratiometric applications 3V to 5V (±10%) the external supply voltage can be used for sensor
element biasing. If an absolute analog output is desired then the internal voltage regulator with external
power regulation element (JFET) can be used. The regulation is bandgap reference based and
designed for an external supply voltage V
sensor bridge voltage can be varied between 3V and 5.5V in 4 steps with the voltage regulator.

1.7 Watchdog and Error Detection

The ZMD31050 detects various possible errors. A detected error is signalized by changing in a
diagnostic mode. In this case the analog output is set to the high or low level (maximum or minimum
possible output value) and the output registers of the digital serial interface are set to a significant error
code.

A watchdog oversees the continuous working of the CMC and the running measurement loop.

A check of the sensor bridge for broken wires is done permanently by two comparators watching the
input voltage of each input [(VSSA + 0.5V) to (VDDA – 0.5V)]. Add on the common mode voltage of the
sensor is watched permanently (sensor aging).
Different functions and blocks in digital part are watched like RAM-, ROM,- EEPROM- and Register
content continuously, the document “ZMD31050 Functional Description” contains in chapter 1.3.4 a
detailed description of all watched blocks and methods of messaging of errors.

in the range of 7V to 40VDC. The internal supply and

SUPP

Datasheet, Rev. 1.0, April 11, 2006 Page 11 of 19 © ZMD AG, 2006
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written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

ZMD31050

Advanced Differential Sensor Signal Conditioner

Datasheet

2. Application Circuit Examples

Example 1

Typical ratiometric measurement with voltage
output, temperature compensation via external
diode, internal VDD regulator and active sensor
connection check (bridge must not be at VDDA)

Example 2

0V to 10V output configuration, supply regulator
(external JFET), temperature compensation via
internal diode and bridge in voltage mode

Example 3

Absolute voltage output, supply regulator
(external JFET), constant current excitation of
the sensor bridge, temperature compensation by
bridge voltage drop measurement, internal VDD
regulator without ext. capacitor

Example 4
Ratiometric bridge differential signal
measurement, 3–wire connection for end of line
calibration at pin OUT (ZACwire™), additional
temperature measurement with external
thermistor and PWM-output at pin IO1

Hints: It is possible to combine or split connectivity of different application examples. For
VDD generation ZMD recommends to use internal supply voltage regulator with external
capacitor. Notice additional application notes for usage of supply voltage regulation property
(non ratiometric mode) and current loop output mode.

Datasheet, Rev. 1.0, April 11, 2006 Page 12 of 19 © ZMD AG, 2006

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written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

Pin-Name

Pin-Nr

ZMD

U23456 abcd

xxxx YYWW

1

16

ZMD31050

Advanced Differential Sensor Signal Conditioner

Datasheet

3. ESD/Latch-Up-Protection

All pins have an ESD protection of >2000V (except the pins INN, INP and FBP with > 1200V) and a
latch-up protection of ±100mA or of +8V/ –4V (to VSS/VSSA) – refer chapter 4 for details and
restrictions. ESD protection referred to the human body model is tested with devices in SSOP16
packages during product qualification. The ESD test follows the human body model with

1.5kOhm/100pF based on MIL 883, method 3015.7.

4. Pin Configuration and Package

Pin Name Description Remarks Latch-Up related Application Circuit

Restrictions and/or Remarks

1 VDDA

2 IN3

3 VGATE

4 IO1

5 IO2

6 SCL

7 SDA

8 VDD

9 FBN

10 OUT

11 FBP

12

IR_TEMP Current source resistor i/o & temp. diode in Analog IO Circuitry secures potential inside of VSS-VDDA

13 VBR

14 VINP

15 VSS

16 VINN

Positive analog supply voltage Supply

Resistive temp sensor IN & external clock IN Analog IN Free accessible (latch-up related)

Gate voltage for external regulator FET Analog OUT Only connection to external FET

SPI data out & ALARM1 & PWM1 Output Digital IO Free accessibility

SPI chip select & ALARM2 Digital IO Free accessibility

I²C clock & SPI clock Digital IN, pull-up Free accessibility

Data IO for I²C & data IN for SPI Digital IO, pull-up Free accessibility

Positive digital supply voltage Supply Only short to VDDA or capacitor to VSS

Negative feedback connection output stage Analog IO Free accessibility

Analog output & PWM2 Output
& one wire interface i/o

Analog OUT &
dig. IO

Positive feedback connection output stage Analog IO Free accessibility

Bridge top sensing in bridge current out Analog IO Only short to VDDA or connection to sensor

Positive input sensor bridge Analog IN Free accessibility

Negative supply voltage Ground

Negative input sensor bridge Analog IN Free accessibility

Table 6: Pin Configuration

The standard package of the ZMD31050 is a SSOP16 (5.3mm body width) with lead-pitch 0.65mm:

Pin-Nr

10
11
12
13
14
15
16

Pin-Name

9

FBN

OUT

FBP

IR_TEMP

VBR

VINP

VSS

VINN

VDD
SDA
SCL
IO2
IO1
VGATE
IN3
VDDA

allowed, otherwise no application access

Free accessibility

range, otherwise no application access

bridge, otherwise no application access

8
7
6
5
4
3
2
1

Datasheet, Rev. 1.0, April 11, 2006 Page 13 of 19 © ZMD AG, 2006
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior

written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

ZMD31050

Advanced Differential Sensor Signal Conditioner

Datasheet

5. IC Characteristics

5.1 Absolute Maximum Ratings

No. Parameter Symbol min typ max Unit Conditions

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

Digital Supply Voltage VDD

Analog Supply Voltage VDDA

Voltage at all analog
and digital I/O – Pins

Voltage at Pin FBP V

V

V

FBP_AMR

Storage temperature T

5.2 Operating Conditions 1 (Voltages related to VSS)

No. Parameter Symbol min typ max Unit Conditions

-0.3 6.5 V DC To VSS

AMR

-0.3 6.5 V DC To VSS

AMR

,

A_I/O

D_I/O

-0.3 VDDA

-1.2 VDDA

+0.3

V DC Exception see 5.1.4

V DC 4 mA to 20mA –

+0.3

-45 150

STG

°C

Interface

5.2.1

5.2.2.1

5.2.2.2

5.2.3

5.2.4

5.2.5

5.2.6

5.2.7

5.2.8

5.2.9

Ambient temperature
advanced performance

Ambient temperature

T

ADV

T

AMB_TQA

-25 85

-40 125

°C TQI = -25 to 85°C

TQC = 0 to 70°C

°C

Automotive range

Ambient temperature
Extended automotive range

Ambient temperature

T

AMB_TQE

T

AMB_EEP

-40 150

-25 85

°C

°C

Operation life time < 1000h
@ 125 to 150°C

EEPROM programming

EEPROM programming

100

cycles

Data retention
(EEPROM)

15 a Averaged

temp < 85°C

Analog Supply Voltage VDDA 2.7 5.5 V DC Ratiometric mode

Analog Supply Voltage

VDDA

ADV

4.5 5.5 V DC Ratiometric mode

advanced performance

Digital Supply Voltage VDD -

2.7

External Supply
Voltage

V

SUPP

VDDA

+ 2V

1.05 - VDDA

External powered

V DC

2 V DC Voltage regulator

mode with ext. JFET

1

Default configuration: 2nd order AD-conversion, 13Bit Resolution, gain >=210, fclk<=2.25MHz

2

Maximum depending on breakdown voltage of external JFET, notice application hints in related application note.

Datasheet, Rev. 1.0, April 11, 2006 Page 14 of 19 © ZMD AG, 2006
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior

written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

ZMD31050

Advanced Differential Sensor Signal Conditioner

Datasheet

No. Parameter Symbol min typ max Unit Conditions

5.2.10

5.2.11

5.2.12

5.2.13

5.2.14

5.2.15

5.2.16

5.2.17

Common mode input
range

Input Voltage Pin FBP

Sensor Bridge
Resistance ∗

Reference Resistor for
Bridge Current Source *

Stabilization Capacitor *

VDD Stabilization
Capacitor *

Maximum allowed load
capacitance at OUT3

Minimum allowed load
resistance

V

0.21 0.76

IN_CM

V

-1 VDDA V DC

IN_FBP

R

BR

3.0 1

25.0

5.0

R

C

C

R

0.07 RBR

BR_REF

50 100 470 nF

VDDA

C

0 2 100 470 nF

VDD

50 nF

L_OUT

2

L_OUT

25.0

V

ADC_REF

kΩ
kΩ

kΩ

Depends on gain
adjustment -
refer chapter 1.3.1

Full temperature range
4mA to 20mA – Interface

Leads to
I

BR = VDDA /

Between VDDA
and VSS, external

Between VDD
and VSS, external

Output Voltage mode

Output Voltage mode

(16·R

BR_REF

)

5.2.18

Maximum allowed load
capacitance at VGATE

C

L_VGATE

10

nF

Summarized to all
potentials

5.3 Build In Characteristics

No. Parameter Symbol min typ max Unit Conditions

5.3.1

5.3.2

5.3.3

5.3.4

5.3.5

5.3.6

5.3.7

Selectable Input Span,
Pressure Measurement

Analog Offset Comp
Range (6 Bit setting)

A/D Resolution

D/A Resolution

PWM - Resolution

Bias current for external
temperature diodes

Sensitivity internal
temperature diode

V

2 280 mV/V

IN_SP

-20

20

-25

r

9 15 Bit

ADC

r

11 Bit

DAC

r

9 12 Bit

PWM

ITS 8 18 40

ST

2800

T_SI

3200

3600

count

25

ppm

f.s. /K

Refer chapter 1.3.1

ADJREF:BCUR=7

3 Bit setting 4

@ analogue output

µA

Raw values - without
conditioning

∗

No measurement in mass production, parameter is guarantied by design and/or quality observation

1

No limitations with an external connection between VDDA and VBR

2

Lower stabilization capacitors can increase noise level at the output

3

If used, consider special requirements of ZACwire™ single wire interface stated in “Functional Description” chapter 4.3

4

Resolution of 15bit is not applicable for 1st order ADC and not recommended for sensors with high nonlinearity behaviour

Datasheet, Rev. 1.0, April 11, 2006 Page 15 of 19 © ZMD AG, 2006
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior

written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

ZMD31050

Advanced Differential Sensor Signal Conditioner

Datasheet

5.3.8 Cycle Rate versus A/D-Resolution ∗

(linear related to master clock frequency1 - values calculated at exact 2 MHz )

ADC Order Resolution

O

r

ADC

ADC

Bit

1 9 1302

10 781
11 434
12 230
13 115
14 59

2 11 3906

12 3906
13 1953
14 1953
15 977

Conversion Cycle f

f

=2MHz f

CLK

CLK

Hz Hz

CYC

=2.25MHz

1465

879
488
259
129

67
4395
4395
2197
2197
1099

5.3.9 PWM Frequency *

PWM PWM Freq./Hz at 2 MHz Clock1

Resolution

r

[Bit] 1 0,5 0,25 0,125 1 0,5 0,25 0,125

PWM

Clock Divider Clock Divider

9 3906 1953 977 488
10 1953 977 488 244
11 977 488 244 122
12 488 244 122 61

PWM Freq./Hz at 2.25 MHz Clock2

4395 2197 1099 549
2197 1099 549 275
1099 549 275 137

549 275 137 69

∗

No measurement in mass production, parameter is guarantied by design and/or quality observation

1

Internal RC – Oscillator: coarse adjustment to1, 2 and 4 MHz, fine tuning +/- 25% , external clock is also possible

2

Internal RC – Oscillator: coarse adjustment to1.125, 2.25 and 4.5 MHz, fine tuning +/- 25% , external clock is also possible

Datasheet, Rev. 1.0, April 11, 2006 Page 16 of 19 © ZMD AG, 2006
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior

written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

ZMD31050

Advanced Differential Sensor Signal Conditioner

Datasheet

5.4 Electrical Parameters (Voltages related to VSS)

No. Parameter Symbol min typ max Unit Conditions

5.4.1 Supply / Regulation

5.4.1.1 Supply current I

5.4.1.2

Supply current for

SUPP

I

SUPP_CL

current loop

5.4.1.2

Temperature Coeff.

TC

Voltage Reference *

5.4.2.1

Parasitic differential

I

IN_OFF

input offset current *

5.4.3 DAC & Analog Output (Pin OUT)

5.4.3.1 Output signal range V

OUT_SR

5.4.3.2 Output DNL DNL

5.4.3.3 Output INL INL

5.4.3.4 Output slew rate * SR

5.4.3.5 Short circuit current * I

5.4.3.6

Addressable output
signal range *

OUT_max

V

OUT_ADR

2.5 4 mA

2.0 2.75

-200 ±50 200 ppm/K

REF

5.4.2 Analog Front End

-2 to -10

2 to 10

0.025 0.975

0.95

OUT

4

OUT

0.1

OUT

5 10 20 mA

0 1

nA

VDDA

LSB

LSB

V/µs

VDDA

Without bridge and load current,
f

≤2.4MHz, Bias-Adjust≤4

CLK

Without bridge current,
f

≤1.2MHz, Bias-Adjust≤1 1

CLK

Temp. range 5.2.2., T

Voltage Mode, assuming
minimum load of 2k
VDDA

VDDA

3

ADV

ADV

,T

,T

ADV

ADV

2

ADV

Voltage mode, CL<20nF,
using conditions of 5.4.3.1

2048 steps

5.4.4 PWM Output (Pin OUT, IO1)

5.4.4.1 PWM high voltage V

5.4.4.2 PWM low voltage V

5.4.4.3 PWM output slew rate

*

PWM_H

PWM_L

SR

0.9

0.1

15

PWM

VDDA

VDDA

V/µs

RL > 10 kΩ

RL > 10 kΩ

CL < 1nF

5.4.5 Temperature Sensors (Pin IR_TEMP)

5.4.5.1

Sensitivity external
diode / resistor meas.

ST

75 210

TS_E

µV/LSB

At r

= 13 Bit

ADC

5.4.6 Digital Outputs (IO1, IO2, OUT in digital mode)

5.4.6.1 Output-High-Level V

5.4.6.2 Output-Low-Level V

5.4.6.3

Output Current ∗

0.9

DOUT_H

0.1

DOUT_L

I

4 mA

DOUT

VDDA

VDDA

RL > 1 kΩ

RL > 1 kΩ

1

Recommended bias adjust <= 4, notice application hints and power consumption adjust constraints in related application note

2

Derated performance in lower part of supply voltage range (2.7 to 3.3V): 2.5 to 5%VDDA & 95 to 97.5%VDDA

3

Output linearity and accuracy can be enhanced by additional analog output stage calibration

∗

No measurement in mass production, parameter is guarantied by design and/or quality observation

Datasheet, Rev. 1.0, April 11, 2006 Page 17 of 19 © ZMD AG, 2006
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior

written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

ZMD31050

Advanced Differential Sensor Signal Conditioner

Datasheet

No. Parameter Symbol min typ max Unit Conditions

5.4.7 System Response

5.4.7.1 Startup time 1,* t

5.4.7.2 Response time * t

5.4.7.3

Overall accuracy (deviation
from ideal line including INL,
gain and offset errors) 2,*

5.4.7.4 Analog Output Noise

V

NOISE,PP

Peak-to-Peak *

5.4.7.5 Analog Output Noise

V

NOISE,RMS

RMS *

5.4.7.6 Ratiometricity Error RE
RE

STA

RESP

AC

OUT

2 5 ms

1.66 2.66 3.66 1/f

0.1

10 mV

3 mV

OUT_5V

OUT_3V

500

0.25

1000

ppm
ppm

PowerOn to first measure result at
output

66% jump, refer 1.3.4 for f

CON

%

T

, VDDA

%

T

T

ADV

AMB

ADV

&

,VDDA

ADV

@ ADJREF:BCUR<4

ADV

Shorted inputs, gain<=210
bandwidth ≤ 10kHz

Shorted inputs, gain<=210
bandwidth ≤ 10kHz

±5% respect. 1000ppm ±10% (5V)
±5% respect. 2000ppm ±10% (3V)

CON

5.5 Interface Characteristics

No. Parameter Symbol min typ max Unit Conditions

5.5.1 Multiport Serial Interfaces (I2C, SPI)

5.5.1.1 Input-High-Level V

5.5.1.2 Input-Low-Level V

5.5.1.3 Output-Low-Level V

I2C_OUT_L

5.5.1.4 Load capacitance @ SDA C

5.5.1.5 Clock frequency SCL 3 f

5.5.1.6 Pull-up Resistor R

0.7 1 VDDA

I2C_IN_H

0 0.3 VDDA

I2C_IN_L

0.1 VDDA

400 pF

SDA

400 kHz f

SCL

500

I2C_PU

Ω

CLK

≥ 2MHz

5.5.2 One Wire Serial Interface (ZACwire™)

5.5.2.1

5.5.2.2

5.5.2.3

OWI start window

Pull-up resistance master

OWI load capacitance

5.5.2.4 Voltage level Low V

5.5.2.5 Voltage level High V

R

OWI_PU

R

OWI_PU

C

OWI_LOAD

OWI_L

OWI_H

20 ms

330

0.08

Ω

t

OWI_BIT

R

OWI_PU

/

0.2 VDDA

0.75 VDDA

20µs < t
100µs

OWI_BIT <

∗

No measurement in mass production, parameter is guarantied by design and/or quality observation

1

OWI – start window disabled, according default configuration

(depends on resolution and configuration - start routine begins approximately 0.8ms after power on)

2

Accuracy better than 0.5% requires offset and gain calibration for the analog output stage

3

Internal clock frequency f

has to be in minimum 5 times higher than communication clock frequency

CLK

Datasheet, Rev. 1.0, April 11, 2006 Page 18 of 19 © ZMD AG, 2006
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior

written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

ZMD31050

Advanced Differential Sensor Signal Conditioner

Datasheet

6. Reliability

A reliability investigation according to the in-house non-automotive standard will be performed.

7. Customization

For high-volume applications, which require an up- or downgraded functionality compared to the
ZM31050, ZMD can customize the circuit design by adding or removing certain functional blocks.
For it ZMD has a considerable library of sensor-dedicated circuitry blocks.
Thus ZMD can provide a custom solution quickly. Please contact ZMD for further information.

8. Related Documents

• ZMD31050 Feature Sheet

• ZMD31050 Functional Description

• ZMD31050 Evaluation Kit Description

• ZMD31050 Development Status Report (including parts identification table)

• ZMD31050 Application Notes

For the most recent revisions of this document and of the related documents, please go to

www.zmd.biz

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. ZMD
assumes no obligation regarding future manufacture unless otherwise agreed in writing. The information furnished hereby is believed to be
correct and accurate. However, ZMD shall not be liable to any customer, licensee or any other third party for any damages in connection with
or arising out of the furnishing, performance or use of this technical data. No obligation or liability to any customer, licensee or any other third
party shall result from ZMD’s rendering of technical or other services.

For further
information:

ZMD AG
Grenzstrasse 28
01109 Dresden, Germany
Tel.: [phone]
Fax: [phone]

[e-mail]

ZMD America, Inc.
201 Old Country Road, Suite 204
Melville, NY 11747, USA
Phone [phone]
Fax [phone]

[e-mail]

ZMD Far East
Taipei World Center
Sinyi Road, Sec. 5, Suite 7A-03
Taipei 110, Taiwan
Phone [phone]
Fax [phone]

[e-mail]

Datasheet, Rev. 1.0, April 11, 2006 Page 19 of 19 © ZMD AG, 2006
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior

written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.