ZMD U634H256 User Manual
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Features Description
U634H256
PowerStore 32K x 8 nvSRAM
! High-performance CMOS non-
volatile static RAM 32768 x 8 bits
! 25, 35 and 45 ns Access Times
! 10, 15 and 20 ns Output Enable
Access Times
! I
= 15 mA typ. at 200 ns Cycle
CC
Time
! Automatic STORE to EEPROM
on Power Down using external
capacitor
! Hardware or Software initiated
STORE
(STORE Cycle Time < 10 ms)
! Automatic STORE Timing
5
! 10
! 10 years data retention in
STORE cycles to EEPROM
EEPROM
! Automatic RECALL on Power Up
! Software RECALL Initiation
(RECALL Cycle Time < 20 µs)
! Unlimited RECALL cycles from
EEPROM
! Single 5 V ± 10 % Operation
! Operating temperature ranges:
0to 70 °C
-40 to 85 °C
-40/-55 to 125 °C (only 35 ns)
! QS 9000 Quality Standard
! ESD protection > 2000 V
(MIL STD 883C M3015.7-HBM)
! Packages: SOP32 (300 mil),
PDIP32 (600 mil, only C/K-Type)
The U634H256 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disabled.
The U634H256 is a fast static RAM
(25, 35, 45 ns), with a nonvolatile
electrically erasable PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resides in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation) take place
automatically upon power down
using charge stored in an external
100 µF capacitor.
Transfers from the EEPROM to the
SRAM (the RECALL operation)
take place automatically on power
up.
The U634H256 combines the high
performance and ease of use of a
fast SRAM with nonvolatile data
integrity.
STORE cycles also may be initiated under user control via a software sequence or via a single pin
(HSB).
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
RECALL cycles may also be initiated by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvolatile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
Pin Configuration
A7
A6
A5
A4
A3
n.c.
A2
A1
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PDIP
SOP
Top View
VCAP
A14
A12
DQ0
DQ1
DQ2
VSS
April 21, 2004
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCCX
HSB
W
A13
A8
A9
A11
G
n.c.
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Pin Description
Signal Name Signal Description
A0 - A14 Address Inputs
DQ0 - DQ7 Data In/Out
E
G
W
Chip Enable
Output Enable
Write Enable
VCCX Power Supply Voltage
VSS Ground
VCAP Capacitor
HSB
Hardware Controlled Store/Busy
1
U634H256
Block Diagram
A5
A6
A7
A8
A9
A11
A12
A13
A14
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Truth Table for SRAM Operations
SRAM
512 Rows x
Row Decoder
Input Buffers
64 x 8 Columns
Column I/O
Column Decoder
A0 A1 A2 A3 A4 A10
EEPROM Array
512 x (64 x 8)
Array
STORE
RECALL
Power
Control
Store/
Recall
Control
Software
Detect
V
CCX
V
SS
V
CAP
V
CCX
V
CAP
HSB
A0 - A13
G
E
W
Operating Mode E HSB W G DQ0 - DQ7
Standby/not selected H H
**
Internal Read L H H H High-Z
Read L H H L Data Outputs Low-Z
Write L H L
*
Data Inputs High-Z
*H or L
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of V
input levels of V
with the exception of the t
Absolute Maximum Ratings
Power Supply Voltage V
Input Voltage V
Output Voltage V
Power Dissipation P
Operating Temperature C-Type
= 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,
IL
-times and ten-times, in which cases transition is measured ± 200 mV from steady-state voltage.
dis
a
K-Type
A-Type
M-Type
Symbol Min. Max. Unit
CC
I
O
D
T
a
-0.5 7 V
-0.3 VCC+0.5 V
-0.3 VCC+0.5 V
0
-40
-40
-55
,as well as
I
70
85
125
125
High-Z
1W
°C
°C
°C
°C
Storage Temperature T
a: Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
stg
2
-65 150 °C
April 21, 2004
U634H256
Recommended
Operating Conditions
Power Supply Voltage
b
Input Low Voltage V
Input High Voltage V
Symbol Conditions Min. Max. Unit
V
CC
-2 V at Pulse Width
IL
IH
10 ns permitted
DC Characteristics Symbol Conditions
Operating Supply Current
c
I
CC1
V
V
V
t
t
t
= 5.5 V
CC
= 0.8 V
IL
= 2.2 V
IH
= 25 ns
c
= 35 ns
c
= 45 ns
c
4.5 5.5 V
-0.3 0.8 V
2.2 VCC+0.3 V
C-Type K-Type A/M-Type
Min. Max. Min. Max. Min. Max.
95
75
65
100
80
70
-
80
-
Unit
mA
mA
mA
Average Supply Current during
STORE
c
Average Supply Current during
PowerStore Cycle
Standby Supply Current
d
(Cycling TTL Input Levels)
Operating Supply Current
at t
= 200 ns
cR
c
(Cycling CMOS Input Levels)
Standby Supply Curent
d
(Stable CMOS Input Levels)
I
CC2
V
E
W
V
V
I
CC4
V
V
V
I
CC(SB)1VCC
E
t
c
t
c
t
c
I
CC3
V
W
V
V
I
CC(SB)VCC
E
V
V
CC
IL
IH
CC
IL
IH
CC
IL
IH
IL
IH
= 5.5 V
≤ 0.2 V
≥ V
CC
≤ 0.2 V
≥ V
-0.2 V
CC
= 4.5 V
= 0.2 V
≥ V
-0.2 V
CC
= 5.5 V
= V
IH
= 25 ns
= 35 ns
= 45 ns
= 5.5 V
≥ V
-0.2 V
CC
≤ 0.2 V
≥ V
-0.2 V
CC
= 5.5 V
≥ V
-0.2 V
CC
≤ 0.2 V
≥ V
-0.2 V
CC
-0.2 V
677mA
444mA
40
36
33
42
38
35
38
-
mA
mA
-
mA
20 20 20 mA
334mA
b: VCC reference levels throughout this datasheet refer to V
nected to ground.
c: I
and I
CC1
The current I
I
is the average current required for the duration of the STORE cycle (STORE Cycle Time).
CC2
d: Bringing E
The current I
are depedent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
CC3
is measured for WRITE/READ - ratio of 1/2.
CC1
≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has t imed out. See MODE SELECTION able.
is measured for WR ITE/READ - ratio of 1/2.
CC(SB)1
April 21, 2004
if that is where the power supply connection is made, or V
CCX
3
CAP
if V
CCX
is con-
U634H256
DC Characteristics Symbol Conditions Min. Max. Unit
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Input Leakage Current
Output Leakage Current
High at Three-State- Output
Low at Three-State- Output
SRAM Memory Operations
Switching Characteristics
No.
Read Cycle
High
Low
V
V
I
I
I
I
I
OHZ
I
OLZ
OH
OL
OH
OL
IH
IL
V
I
I
V
V
V
V
V
V
V
V
V
CC
OH
OL
CC
OH
OL
CC
IH
IL
CC
OH
OL
= 4.5 V
=-4 mA
2.4
= 8 mA
= 4.5 V
= 2.4 V
= 0.4 V 8
= 5.5 V
= 5.5 V
= 0 V -1
= 5.5 V
= 5.5 V
= 0 V -1
Symbol 25 35 45
Alt. IEC Min. Max. Min. Max. Min. Max.
0.4
-4 mA
mA
1 µA
µA
1 µA
µA
Unit
V
V
1 Read Cycle Time
2 Address Access Time to Data Valid
f
g
3 Chip Enable Access Time to Data Valid t
4 Output Enable Access Time to Data Valid t
5E HIGH to Output in High-Z
HIGH to Output in High-Z
6G
LOW to Output in Low-Z t
7E
h
h
8G LOW to Output in Low-Z t
9 Output Hold Time after Address Change t
10 Chip Enable to Power Active
11 Chip Disable to Power Standby
e: Parameter guaranteed but not tested.
f: Device is continuously selected with E
g: Address valid prior to or coincident with E
h: Measured ± 200 mV from steady state output voltage.
e
d, e
and G both LOW.
transition LOW.
t
AVAV
t
AVQ V
ELQV
GLQV
t
EHQZ
t
GHQZ
ELQX
GLQX
AXQX
t
ELICCH
t
EHICCL
t
cR
t
a(A)
t
a(E)
t
a(G)
t
dis(E)
t
dis(G)
t
en(E)
t
en(G)
t
v(A)
t
PU
t
PD
25 35 45 ns
25 35 45 ns
25 35 45 ns
10 15 20 ns
10 13 15 ns
10 13 15 ns
555ns
000ns
333ns
000ns
25 35 45 ns
4
April 21, 2004
U634H256
Read Cycle 1: Ai-controlled (during Read cycle: E = G = VIL, W = VIH)
t
(1)
cR
Ai
DQi
Output
Previous Data Valid
t
v(A)
Read Cycle 2: G-, E-controlled (during Read cycle: W = VIH)
Ai
E
t
G
DQi
Output
I
CC
High Impedance
ACTIVE
STANDBY
en(E )
t
t
PU
en(G)
(10)
Address Valid
t
(2)
a(A)
(9)
t
(1)
cR
Address Valid
t
(2)
a(A)
t
a(E)
(3)
(7)
(8)
t
a(G)
g
(4)
Output Data Valid
f
Output Data Valid
t
(11)
PD
t
(5)
dis(E)
t
(6)
dis( G)
Switching Characteristics
No.
Write Cycle
12 Write Cycle Time t
13 Write Pulse Width t
Alt. #1 Alt. #2 IEC Min. Max. Min. Max. Min. Max.
AVAV
WLWH
14 Write Pulse Width Setup Time t
15 Address Setup Time t
16 Address Valid to End of Write t
17 Chip Enable Setup Time t
AVW L
AVW H
ELWH
18 Chip Enable to End of Write t
19 Data Setup Time to End of Write t
20 Data Hold Time after End of Write t
21 Address Hold after End of Write t
22 W
LOW to Output in High-Z
h, i
23 W HIGH to Output in Low-Z t
DVWH
WHDX
WHAX
t
WLQZ
WHQX
Symbol 25 35 45
t
AVAV
WLEH
t
AVEL
t
AVEH
ELEH
t
DVEH
t
EHDX
t
EHAX
t
cW
t
w(W)
t
su(W)
t
su(A)
t
su(A-WH)
t
su(E)
t
w(E)
t
su(D)
t
h(D)
t
h(A)
t
dis(W)
t
en(W)
25 35 45 ns
20 25 30 ns
20 25 30 ns
000ns
20 25 30 ns
20 25 30 ns
20 25 30 ns
10 12 15 ns
000ns
000ns
10 13 15 ns
555ns
Unit
April 21, 2004
5
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