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Features Description
U630H16
HardStore 2K x 8 nvSRAM
S High-performance CMOS nonvo-
latile static RAM 2048 x 8 bits
S 25, 35 and 45 ns Access Times
S 12, 20 and 25 ns Output Enable
Access Times
S Hardware STORE Initiation
(STORE Cycle Time < 10 ms)
S Automatic STORE Timing
6
S 10
S 100 years data retention in
STORE cycles to EEPROM
EEPROM
S Automatic RECALL on Power Up
S Hardware RECALL Initiation
(RECALL Cycle Time < 20 µs)
S Unlimited RECALL cycles from
EEPROM
S Unlimited Read and Write to
SRAM
S Single 5 V ± 10 % Operation
S Operating temperature ranges:
0to 70 °C
-40 to 85 °C
-40 to 125 °C (only 35 ns)
S QS 9000 Quality Standard
S ESD protection > 2000 V
(MIL STD 883C M3015.7-HBM)
S RoHS compliance and Pb- free
S Packages: SOP28 (300 mil),
PDIP28 (300/600 mil)
The U630H16 has two separate
modes of operation: SRAM mode
and nonvolatile mode, determined
by the state of the NE
pin.
In SRAM mode, the memory operates as an ordinary static RAM. In
nonvolatile operation, data is transferred in parallel from SRAM to
EEPROM or from EEPROM to
SRAM. In this mode SRAM
functions are disabled.
The U630H16 is a fast static RAM
(25, 35, 45 ns), with a nonvolatile
electrically erasable PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resides in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation), or from the
EEPROM to the SRAM (the
RECALL operation) are initiated
through the state of the NE
pin.
The U630H16 combines the high
performance and ease of use of a
fast SRAM with nonvolatile data
integrity.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvolatile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
Pin Configuration
1
NE
A7
A6
A5
A4
A3
A2
A1
A0
2
3
4
5
6
7
8
9
10
11
12
13
14
PDIP
n.c.
DQ0
DQ1
DQ2
VSS
Top View
April 7, 2005
SOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
W
n.c.
A8
A9
n.c.
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Pin Description
Signal Name Signal Description
A0 - A10 Address Inputs
DQ0 - DQ7 Data In/Out
E
G
W
NE
Chip Enable
Output Enable
Write Enable
Nonvolatile Enable
VCC Power Supply Voltage
VSS Ground
1
U630H16
Block Diagram
A5
A6
A7
A8
A9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Truth Table for SRAM Operations
SRAM
Array
Row Decoder
Input Buffers
32 Rows x
64 x 8 Columns
Column I/O
Column Decoder
A0 A1 A2 A3 A4A10
EEPROM Array
32 x (64 x 8)
STORE
RECALL
Store/
Recall
Control
G
NE
E
W
V
CC
V
SS
V
CC
Operating Mode E NE W G DQ0 - DQ7
Standby/not selected H
***
Internal Read L H H H High-Z
Read L H H L Data Outputs Low-Z
Write L H L
*
Data Inputs High-Z
* H or L
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of V
input levels of V
with the exception of the t
Absolute Maximum Ratings
Power Supply Voltage V
Input Voltage V
Output Voltage V
Power Dissipation P
= 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,
IL
-times and ten-times, in which cases transition is measured ± 200 mV from steady-state voltage.
dis
a
Symbol Min. Max. Unit
CC
I
O
D
-0.5 7 V
-0.3 VCC+0.5 V
-0.3 VCC+0.5 V
,as well as
I
High-Z
1W
Operating Temperature C-Type
K-Type
T
a
A-Type
Storage Temperature T
a: Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
stg
0
-40
-40
-65 150 °C
2
70
85
85
°C
°C
°C
April 7, 2005
U630H16
Recommended
Operating Conditions
Symbol Conditions Min. Max. Unit
Power Supply Voltage V
Input Low Voltage V
Input High Voltage V
DC Characteristics
Operating Supply Current
b
Symbol Conditions
I
CC1
V
V
V
t
t
t
CC
IL
IH
c
c
c
-2 V at Pulse Width
10 ns permitted
= 5.5 V
CC
= 0.8 V
IL
= 2.2 V
IH
= 25 ns
= 35 ns
= 45 ns
4.5 5.5 V
-0.3 0.8 V
2.2 VCC+0.3 V
C-Type K-Type A-Type
Min. Max. Min. Max. Min. Max.
90
80
75
95
85
80
-
85
-
Unit
mA
mA
mA
Average Supply Current during
STORE
Standby Supply Current
c
d
I
CC2
I
CC(SB)1VCC
(Cycling TTL Input Levels)
Average Supply Current
at t
= 200 ns
cR
b
I
CC3
(Cycling CMOS Input Levels)
Standby Supply Current
d
I
CC(SB)VCC
(Stable CMOS Input Levels)
b: I
and I
CC1
The current I
c: I
is the average current required for the duration of the STORE cycle (STORE Cycle Time).
CC2
d: Bringing E
table. The current I
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
CC3
is measured for WRITE/READ - ratio of 1/2.
CC1
≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION
is measured for WRITE/READ - ratio of 1/2.
CC(SB )1
V
E
W
V
V
E
t
t
t
V
W
V
V
E
V
V
= 5.5 V
CC
≥ V
-0.2 V
CC
≥ V
-0.2 V
CC
≤ 0.2 V
IL
≥ V
IH
CC
-0.2 V
= 5.5 V
≥ V
IH
= 25 ns
c
= 35 ns
c
= 45 ns
c
= 5.5 V
C
C
≥ V
-0.2 V
CC
≤ 0.2 V
IL
≥ V
IH
CC
-0.2 V
= 5.5 V
≥ V
-0.2 V
CC
≤ 0.2 V
IL
≥ V
IH
CC
-0.2 V
677mA
30
23
20
34
27
23
27
-
mA
mA
-
mA
15 15 15 mA
112mA
April 7, 2005
3
U630H16
DC Characteristics
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Input Leakage Current
Output Leakage Current
High at Three-State- Output
Low at Three-State- Output
SRAM Memory Operations
High
Low
Symbol Conditions Min. Max. Unit
V
V
I
OH
I
I
I
I
OHZ
I
OLZ
OH
OL
OL
IH
IL
V
CC
I
OH
I
OL
V
CC
V
OH
V
OL
V
CC
V
IH
V
IL
V
CC
V
OH
V
OL
= 4.5 V
=-4 mA
2.4
= 8 mA
= 4.5 V
= 2.4 V
= 0.4 V 8
= 5.5 V
= 5.5 V
= 0 V -1
= 5.5 V
= 5.5 V
= 0 V -1
0.4
-4 mA
mA
1 µA
µA
1 µA
µA
V
V
Switching Characteristics
No.
Read Cycle
1 Read Cycle Time
2 Address Access Time to Data Valid
f
g
3 Chip Enable Access Time to Data Valid t
4 Output Enable Access Time to Data Valid t
5E HIGH to Output in High-Z
HIGH to Output in High-Z
6G
LOW to Output in Low-Z t
7E
LOW to Output in Low-Z t
8G
9 Output Hold Time after Addr. Change
10 Chip Enable to Power Active
11 Chip Disable to Power Standby
e: Parameter guaranteed but not tested.
f: Device is continuously selected with E
g: Address valid prior to or coincident with E
h: Measured ± 200 mV from steady state output voltage.
h
h
g
e
d, e
and G both LOW.
transition LOW.
Symbol 25 35 45
Alt. IEC Min. Max. Min. Max. Min. Max.
t
AVAV
t
AVQ V
ELQV
GLQV
t
EHQZ
t
GHQZ
ELQX
GLQX
t
AXQX
t
ELICCH
t
EHICCL
t
cR
t
a(A)
t
a(E)
t
a(G)
t
dis(E)
t
dis(G)
t
en(E)
t
en(G)
t
v(A)
t
PU
t
PD
25 35 45 ns
25 35 45 ns
25 35 45 ns
12 20 25 ns
13 17 20 ns
13 17 20 ns
555 ns
000 ns
333 ns
000 ns
25 35 45 ns
Unit
4
April 7, 2005
U630H16
Read Cycle 1: Ai-controlled (during Read cycle: E = G = VIL, W = NE = VIH)
t
(1)
cR
Ai
DQi
Output
Previous Data Valid
t
v(A)
Read Cycle 2: G-, E-controlled (during Read cycle: W = NE = VIH)
Ai
E
t
t
(7)
G
DQi
Output
I
CC
High Impedance
ACTIVE
STANDBY
en(E)
t
en(G)
t
(10)
PU
Address Valid
t
(2)
a(A)
(9)
t
(1)
cR
Address Valid
(2)
a(A)
t
(3)
a(E)
t
a(G)
(8)
(4)
Output Data Valid
g
t
t
dis(G)
Output Data Valid
dis(E)
(5)
(6)
f
t
(11)
PD
Switching Characteristics
No.
Write Cycle
12 Write Cycle Time t
13 Write Pulse Width t
Alt. #1 Alt. #2 IEC Min. Max. Min. Max. Min. Max.
AVAVtAVAV
WLWH
14 Write Pulse Width Setup Time t
15 Address Setup Time t
16 Address Valid to End of Write t
17 Chip Enable Setup Time t
AVW LtAVELtsu(A)
AVW HtAVEH
ELWH
18 Chip Enable to End of Write t
19 Data Setup Time to End of Write t
20 Data Hold Time after End of Write t
21 Address Hold after End of Write t
LOW to Output in High-Z
22 W
HIGH to Output in Low-Z t
23 W
h, i
DVWHtDVEHtsu(D)
WHDXtEHDXth(D)
WHAXtEHAXth(A)
t
WLQZ
WHQX
Symbol 25 35 45
t
cW
t
w(W)
WLEHtsu(W)
25 35 45 ns
20 30 35 ns
20 30 35 ns
000ns
ELE
H
t
su(A-WH)
t
su(E)
t
w(E)
20 30 35 ns
20 30 35 ns
20 30 35 ns
12 18 20 ns
000ns
000ns
t
dis(W)
t
en(W)
10 13 15 ns
555ns
Unit
April 7, 2005
5
U630H16
Write Cycle #1: W-controlled
Ai
E
W
DQi
Input
DQi
Output
Write Cycle #2: E-controlled
j
t
su(A)
(15)
Previous Data
j
t
dis(W)
(22)
t
su(A-WH)
t
cW
(12)
Address Valid
t
(17)
su(E)
(16)
t
(13)
w(W)
t
su(D)
(19)
Input Data Valid
High Impedance
t
t
h(D)
t
en(W)
h(A)
(21)
(20)
(23)
Ai
E
W
DQi
Input
DQi
Output
t
en(E)
t
su(A)
(7)
(15)
L- to H-level undefined
t
dis(W)
t
cW
Address Valid
t
(18)
w(E)
t
(14)
su(W)
t
su(D)
(22)
(12)
Input Data Valid
High Impedance
t
h(A)
t
(21)
h(D)
(20)(19)
H- to L-level
i: If W is LOW and when E goes LOW, the outputs remain in the high impedance state.
j: E
or W and NE must be
>
V
during address transitions.
IH
6
April 7, 2005
Nonvolatile Memory Operations
U630H16
STORE Cycle Inhibit and
No.
Automatic Power Up RECALL
24 Power Up RECALL Duration
Low Voltage Trigger Level V
k: t
starts from the time VCC rises above V
REST ORE
k, e
SWITCH
.
Symbol
Alt. IEC
t
RESTORE
SWITCH
STORE Cycle Inhibit and Automatic Power Up RECALL
V
CC
5.0 V
V
SWITCH
Min. Max. Unit
650 µs
4.0 4.5 V
t
STORE inhibit
Power Up
RECALL
(24)
t
RESTORE
Mode Selection
E
W G NE Mode Power Notes
L H L L Nonvolatile RECALL
L L H L Nonvolatile STORE I
L
L
L
H
L
H
L
*
No operation Active
* H or L
Active l
CC2
l: An automatic RECALL also takes place at power up, starting when V
V
once it has been exceeded for the RECALL to function properly.
SWITCH
April 7, 2005
7
exceeds V
CC
SWITCH
and takes t
. VCC must not drop below
RESTORE
U630H16
STORE Cycles
No. STORE Cycle W
-controlled
Symbol
Min. Max. Unit
Alt. IEC
25 STORE Cycle Time
26 STORE Initiation Cycle Time
27 Output Disable Setup to NE
28 NE
Setup t
m
n
Fall t
29 Chip Enable Setup t
STORE Cycle: W-controlled
o
NE
G
t
su(G)S
(27)
W
t
su(E)S
E
DQi
Output
(29)
t
su(N)S
(28)
t
WLQX
t
WLNH
GHNL
NLWL
ELWL
t
d(W)S
t
w(W)S
t
su(G)S
t
su(N)S
t
su(E)S
t
(26)
w(W)S
High Impedance
t
d(W)S
10 ms
25 ns
5ns
5ns
5ns
(25)
No. STORE Cycle E-controlled
30 STORE Cycle Time t
31 STORE Initiation Cycle Time t
32 Output Disable Setup to E
33 NE
Setup t
Fall t
34 Write Enable Setup t
STORE Cycle: E-controlled
o
NE
G
t
su(G)S
t
su(W)S
W
E
DQi
Output
High Impedance
Symbol
Alt. IEC
ELQXS
ELNHS
GHEL
NLEL
WLEL
t
su(N)S
(33)
(32)
(34)
t
w(E)S
t
d(E)S
t
w(E)S
t
su(G)S
t
su(N)S
t
su(W)S
(31)
t
d(E)S
Min. Max. Unit
10 ms
25 ns
5ns
5ns
5ns
(30)
8
April 7, 2005
RECALL Cycles
No. RECALL Cycle NE
-controlled
U630H16
Symbol
Min. Max. Unit
Alt. IEC
35 RECALL Cycle Time
36 RECALL Initiation Cycle Time
p
q
37 Output Enable Setup t
38 Write Enable Setup t
39 Chip Enable Setup t
40 NE
RECALL Cycle: NE-controlled
Fall to Output Inactive t
o
NE
G
W
t
su(W)R
E
t
su(E)R
DQi
Output
t
su(G)R
(37)
(38)
t
NLQX
t
NLNH
GLNL
WHNL
ELNL
NLQZ
t
dis(N)R
t
d(N)R
t
w(N)R
t
su(G)R
t
su(W)R
t
su(E)R
t
dis(N)R
t
w(N)R (36)
(40)
High Impedance
t
d(N)R
20 µs
25 ns
5ns
5ns
5ns
25 ns
(35)(39)
No. RECALL Cycle E-controlled
41 RECALL Cycle Time t
42 RECALL Initiation Cycle Time t
43 NE
Setup t
44 Output Enable Setup t
45 Write Enable Setup t
RECALL Cycle: E-controlled
o
NE
t
su(G)R
G
t
W
su(W)R
(45)
E
DQi
Output
High Impedance
Symbol
Alt. IEC
ELQXR
ELNHR
NLEL
GLEL
WHEL
t
su(N)R
(43)
(44)
t
w(E)R
t
d(E)R
t
w(E)R
t
su(N)R
t
su(G)R
t
su(W)R
(42)
t
d(E)R
Min. Max. Unit
20 µs
25 ns
5ns
5ns
5ns
(41)
April 7, 2005
9
U630H16
No. RECALL Cycle G-controlled
Symbol
Min. Max. Unit
Alt. IEC
46 RECALL Cycle Time t
47 RECALL Initiation Cycle Time t
48 NE
Setup t
49 Write Enable Setup t
50 Chip Enable Setup t
RECALL Cycle: G-controlled
o, r
NE
G
W
t
su(W)R
t
su(E)R
E
DQi
Output
High Impedance
(50)
GLQXR
WHGL
t
su(N)R
(48)
(49)
GLNH
NLGL
ELGL
t
w(G)R
t
t
t
t
t
d(G)R
w(G)R
su(N)R
su(W)R
su(E)R
(47)
t
d(G)R
20 µs
25 ns
5ns
5ns
5ns
(46)
m: Measured with W and NE both returned HIGH, and G returned LOW. Note that STORE cycles are inhibited/aborted by V
(STORE inhibit).
n: Once t
terminate the STORE initiation cycle.
o: If E
For E
p: Measured with W
q: Once t
terminate the RECALL initiation cycle.
r: If W
has been satisfied by NE, G, W and E, the STORE cycle is completed automatically. Any of NE, G, W and E may be used to
w(W)S
is LOW for any period of time in which W is HIGH while G and NE are LOW, than a RECALL cycle may be initiated.
-controlled STORE during t
w(N)R
is LOW at any point in which both E and NE are LOW and G is HIGH, than a STORE cycle will be initiated instead of a RECALL.
and NE both HIGH, and G and E LOW.
has been satisfied by NE, G, W and E, the RECALL cycle is completed automatically. Any of NE, G or E may be used to
W, G, NE have to be static.
w(E)S
10
< V
CC
SWITCH
April 7, 2005
Test Configuration for Functional Check
U630H16
s: In measurement of t
t: Between V
Capacitance
and VSS must be connected a high frequency bypass capacitor 0.1 µF to avoid disturbances.
CC
e
Input Capacitance
Output Capacitance
A0
A1
A2
A3
V
IH
V
IL
Input level according to the
relevant test measurement
-times and ten-times the capacitance is 5 pF.
dis
A4
A5
A6
A7
A8
A9
A10
NE
E
W
G
Conditions Symbol Min. Max. Unit
V
V
T
f
CC
I
a
= 5.0 V
= V
SS
= 1 MHz
= 25 °C
t
V
CC
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
V
SS
C
I
C
O
5 V
480
V
O
Simultaneous measure-
ment of all 8 output pins
255
30 pF
s
8pF
7pF
All pins not under test must be connected with ground by capacitors.
Ordering Code
Example
G1S 25CU630H16
Type
Package
u
D
= PDIP28 (300 mil)
D1 = PDIP28 (600 mil)
S = SOP28 (300 mil)
Operating Temperature Range
C = 0 to 70 °C
K = -40 to 85 °C
A = -40 to 125 °C
u: on special request
(only 35 ns and SOP28 package)
Device Marking (example)
Product specification
ZMD
U630H16SC
25 Z 0425
G1
Leadfree Option
blank = Standard Package
G1 = Leadfree Green Package
Access Time
25 = 25 ns
35 = 35 ns
(C/K Type on special request)
45 = 45 ns
Date of manufacture
(The first 2 digits indicating
the year, and the last 2
digits the calendar week.)
Internal Code
April 7, 2005
Leadfree Green Package
11
U630H16
Device Operation
The U630H16 has two separate modes of operation:
SRAM mode and nonvolatile mode, determined by the
state of the NE
pin. In SRAM mode, the memory operates as a standard fast static RAM. In nonvolatile mode,
data is transferred from SRAM to EEPROM (the
STORE operation) or from EEPROM to SRAM (the
RECALL operation). In this mode SRAM functions are
disabled.
SRAM READ
The U630H16 performs a READ cycle whenever E
G
are LOW while W and NE are HIGH. The address
and
specified on pins A0 - A10 determines which of the
2048 data bytes will be accessed. When the READ is
initiated by an address transition, the outputs will be
valid after a delay of t
G
, the outputs will be valid at t
. If the READ is initiated by E or
cR
a(E)
or at t
, whichever
a(G)
is later. The data outputs will repeatedly respond to
address changes within the t
access time without the
cR
need for transition on any control input pins, and will
remain valid until another address change or until E
G
is brought HIGH or W or NE is brought LOW.
or
SRAM WRITE
A WRITE cycle is performed whenever E
LOW and NE
is HIGH. The address inputs must be sta-
and W are
ble prior to entering the WRITE cycle and must remain
stable until either E
or W goes HIGH at the end of the
cycle. The data on pins DQ0 - 7 will be written into the
memory if it is valid t
led WRITE or t
su(D)
before the end of a W control-
su(D
)
before the end of an E controlled
WRITE.
It is recommended that G
is kept HIGH during the entire WRITE cycle to avoid data bus contention on the
common I/O lines. If G
turn off the output buffers t
is left LOW, internal circuitry will
after W goes LOW.
dis(W)
Noise Consideration
STORE cycle, previous nonvolatile data is erased and
the SRAM contents are then programmed into nonvolatile elements. Once a STORE cycle is initiated, further
input and output is disabled and the DQ0 - 7 pins are
tristated until the cycle is completed.
If E
and G are LOW and W and NE are HIGH at the
end of the cycle, a READ will be performed and the outputs will go active, indicating the end of the STORE.
Hardware Nonvolatile RECALL
A RECALL cycle is performed when E
LOW while W
is HIGH. Like the STORE cycle, RECALL
, G and NE are
is initiated when the last of the three clock-signals goes
to the RECALL state. Once initiated, the RECALL cycle
will take „RECALL Cycle Time“ to complete, during
which all inputs are ignored. When the RECALL completes, any READ or WRITE state on the input pins will
take effect.
Internally, RECALL is a two step procedure. First, the
SRAM data is cleared and second, the nonvolatile
information is transferred into the SRAM cells. The
RECALL in no way alters the data in the nonvolatile
cells. The nonvolatile data can be recalled an unlimited
number of times.
Like the STORE cycle, a transition must occur on some
control pins to cause a RECALL, preventing inadvertend multi-triggering.
Automatic Power Up RECALL
On power up, once V
V
voltage on the V
, a RECALL cycle is automatically initiated. The
SWITCH
CC
exceeds the sense voltage of
CC
pin must not drop below V
SWITCH
once it has risen above it in order for the RECALL to
operate properly. Due to this automatic RECALL,
SRAM operation cannot commence until t
V
exceeds V
CC
. If the U630H16 is in a WRITE
SWITCH
RESTORE
after
state at the end of power up RECALL, the SRAM data
will be corrupted.
To help avoid this situation, a 10 KΩ resistor should be
connected between W
and system V
CC
.
The U630H16 is a high speed memory and therefore
must have a high frequency bypass capacitor of approximately 0.1 µF connected between V
and VSS using
CC
leads and traces that are as short as possible. As with
all high speed CMOS ICs, normal carefull routing of
power, ground and signals will help prevent noise problems.
Hardware Nonvolatile STORE
A STORE cycle is performed when NE
LOW while G
is HIGH. While any sequence to achieve
this state will initiate a STORE, only W
, E and W are
initiation and E
initiation are practical without risking an unintentional
SRAM WRITE that would disturb SRAM data. During a
Hardware Protection
The U630H16 offers two levels of protection to suppress inadvertent STORE cycles. If the control signals
(E
, G, W and NE) remain in the STORE condition at the
end of a STORE cycle, a second STORE cycle will not
be started. The STORE (or RECALL) will be initiated
only after a transition on any one of these signals to the
required state. In addition to multi-trigger protection, the
U630H16 offers hardware protection through V
Sense. When VCC < V
the externally initiated
SWITCH
STORE operation will be inhibited.
12
April 7, 2005
CC
Low Average Active Power
U630H16
The U630H16 has been designed to draw significantly
less power when E
access cycle time is longer than 55 ns.
When E
rent.
The overall average current drawn by the part depends
on the following items:
is HIGH the chip consumes only standby cur-
is LOW (chip enabled) but the
1. CMOS or TTL input levels
2. the time during which the chip is disabled (E
3. the cycle time for accesses (E
4. the ratio of READs to WRITEs
5. the operating temperature
6. the V
CC
level
LOW)
HIGH)
The information describes the type of component and shall not be considered as assured characteristics. Terms of
delivery and rights to change design reserved.
April 7, 2005
13
U630H16
LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the ZMD product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.
LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be reliable. However Zentrum
Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information
and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it.
The information in this document describes the type of component and shall not be considered as assured characteristics.
ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trademark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This
document does not in any way extent ZMD’s warranty on any product beyond that set forth in its standard terms and
conditions of sale.
ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,
presented in this publication at any time and without notice.
April 7, 2005
Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Email: memory@zmd.de • http://www.zmd.de
Zentrum Mikroelektronik Dresden AG
Grenzstraße 28 • D-01109 Dresden • P. O. B. 80 01 34 • D-01101 Dresden • Germany
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