ZMD U630H16 User Manual

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Features Description

U630H16

HardStore 2K x 8 nvSRAM

S High-performance CMOS nonvo-

latile static RAM 2048 x 8 bits

S 25, 35 and 45 ns Access Times S 12, 20 and 25 ns Output Enable

Access Times

S Hardware STORE Initiation

(STORE Cycle Time < 10 ms)

S Automatic STORE Timing

6

S 10 S 100 years data retention in

STORE cycles to EEPROM

EEPROM

S Automatic RECALL on Power Up S Hardware RECALL Initiation

(RECALL Cycle Time < 20 µs)

S Unlimited RECALL cycles from

EEPROM

S Unlimited Read and Write to

SRAM

S Single 5 V ± 10 % Operation S Operating temperature ranges:

0to 70 °C

-40 to 85 °C

-40 to 125 °C (only 35 ns)

S QS 9000 Quality Standard S ESD protection > 2000 V

(MIL STD 883C M3015.7-HBM)

S RoHS compliance and Pb- free S Packages: SOP28 (300 mil),

PDIP28 (300/600 mil)

The U630H16 has two separate modes of operation: SRAM mode and nonvolatile mode, determined by the state of the NE

pin. In SRAM mode, the memory operates as an ordinary static RAM. In nonvolatile operation, data is transferred in parallel from SRAM to EEPROM or from EEPROM to SRAM. In this mode SRAM functions are disabled. The U630H16 is a fast static RAM (25, 35, 45 ns), with a nonvolatile electrically erasable PROM (EEPROM) element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in EEPROM. Data transfers from the SRAM to the EEPROM (the STORE operation), or from the EEPROM to the SRAM (the RECALL operation) are initiated through the state of the NE

pin. The U630H16 combines the high performance and ease of use of a fast SRAM with nonvolatile data integrity. Once a STORE cycle is initiated,

further input or output are disabled until the cycle is completed. Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times.

Pin Configuration

1

NE

A7

A6

A5

A4

A3

A2

A1

A0

2

3

4

5

6

7

8

9

10

11

12

13

14

PDIP

n.c.

DQ0

DQ1

DQ2

VSS

Top View

April 7, 2005

SOP

28

27

26

25

24

23

22

21

20

19

18

17

16

15

VCC

W

n.c.

A8

A9

n.c.

G

A10

E

DQ7

DQ6

DQ5

DQ4

DQ3

Pin Description

Signal Name Signal Description

A0 - A10 Address Inputs

DQ0 - DQ7 Data In/Out

E

G

W

NE

Chip Enable

Output Enable

Write Enable

Nonvolatile Enable

VCC Power Supply Voltage

VSS Ground

1

U630H16

Block Diagram

A5 A6

A7

A8

A9

DQ0 DQ1

DQ2 DQ3

DQ4

DQ5 DQ6

DQ7

Truth Table for SRAM Operations

SRAM

Array

Row Decoder

Input Buffers

32 Rows x

64 x 8 Columns

Column I/O

Column Decoder

A0 A1 A2 A3 A4A10

EEPROM Array

32 x (64 x 8)

STORE

RECALL

Store/

Recall

Control

G

NE

E

W

V

CC

V

SS

V

CC

Operating Mode E NE W G DQ0 - DQ7

Standby/not selected H

***

Internal Read L H H H High-Z

Read L H H L Data Outputs Low-Z

Write L H L

*

Data Inputs High-Z

* H or L

Characteristics

All voltages are referenced to VSS = 0 V (ground). All characteristics are valid in the power supply voltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of V input levels of V with the exception of the t

Absolute Maximum Ratings

Power Supply Voltage V

Input Voltage V

Output Voltage V

Power Dissipation P

= 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,

IL

-times and ten-times, in which cases transition is measured ± 200 mV from steady-state voltage.

dis

a

Symbol Min. Max. Unit

CC

I

O

D

-0.5 7 V

-0.3 VCC+0.5 V

,as well as

I

High-Z

1W

Operating Temperature C-Type

K-Type

T

a

A-Type

Storage Temperature T

a: Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress

rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

stg

0

-40

-65 150 °C

2

70 85 85

°C °C

°C

April 7, 2005

U630H16

Recommended Operating Conditions

Symbol Conditions Min. Max. Unit

Power Supply Voltage V

Input Low Voltage V

Input High Voltage V

DC Characteristics

Operating Supply Current

b

Symbol Conditions

I

CC1

V V V

t t t

CC

IL

IH

c

-2 V at Pulse Width 10 ns permitted

= 5.5 V

CC

= 0.8 V

IL

= 2.2 V

IH

= 25 ns = 35 ns = 45 ns

4.5 5.5 V

-0.3 0.8 V

2.2 VCC+0.3 V

C-Type K-Type A-Type

Min. Max. Min. Max. Min. Max.

90 80 75

95 85 80

-

85

-

Unit

mA mA mA

Average Supply Current during STORE

Standby Supply Current

c

d

I

CC2

I

CC(SB)1VCC

(Cycling TTL Input Levels)

Average Supply Current at t

= 200 ns

cR

b

I

CC3

(Cycling CMOS Input Levels)

Standby Supply Current

d

I

CC(SB)VCC

(Stable CMOS Input Levels)

b: I

and I

CC1

The current I

c: I

is the average current required for the duration of the STORE cycle (STORE Cycle Time).

CC2

d: Bringing E

table. The current I

are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.

CC3

is measured for WRITE/READ - ratio of 1/2.

CC1

≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION

is measured for WRITE/READ - ratio of 1/2.

CC(SB )1

V E W V V

E

t t t

V W V V

E V V

= 5.5 V

CC

≥ V

-0.2 V

CC

≥ V

-0.2 V

CC

≤ 0.2 V

IL

≥ V

IH

CC

-0.2 V

= 5.5 V ≥ V

IH

= 25 ns

c

= 35 ns

c

= 45 ns

c

= 5.5 V

C

≥ V

-0.2 V

CC

≤ 0.2 V

IL

≥ V

IH

CC

-0.2 V

= 5.5 V ≥ V

-0.2 V

CC

≤ 0.2 V

IL

≥ V

IH

CC

-0.2 V

677mA

30 23 20

34 27 23

27

-

mA mA

-

mA

15 15 15 mA

112mA

April 7, 2005

3

U630H16

DC Characteristics

Output High Voltage Output Low Voltage

Output High Current Output Low Current

Input Leakage Current

Output Leakage Current

High at Three-State- Output Low at Three-State- Output

SRAM Memory Operations

High Low

Symbol Conditions Min. Max. Unit

V

I

OH

I

I I

I

OHZ

I

OLZ

OH

OL

IH

IL

V

CC

I

OH

I

OL

V

CC

V

OH

V

OL

V

CC

V

IH

V

IL

V

CC

V

OH

V

OL

= 4.5 V =-4 mA

2.4

= 8 mA

= 4.5 V = 2.4 V = 0.4 V 8

= 5.5 V

= 5.5 V = 0 V -1

= 5.5 V

= 5.5 V = 0 V -1

0.4

-4 mA mA

1 µA

µA

1 µA

µA

V V

Switching Characteristics

No.

Read Cycle

1 Read Cycle Time

2 Address Access Time to Data Valid

f

g

3 Chip Enable Access Time to Data Valid t

4 Output Enable Access Time to Data Valid t

5E HIGH to Output in High-Z

HIGH to Output in High-Z

6G

LOW to Output in Low-Z t

7E

LOW to Output in Low-Z t

8G

9 Output Hold Time after Addr. Change

10 Chip Enable to Power Active

11 Chip Disable to Power Standby

e: Parameter guaranteed but not tested. f: Device is continuously selected with E g: Address valid prior to or coincident with E h: Measured ± 200 mV from steady state output voltage.

h

g

e

d, e

and G both LOW.

transition LOW.

Symbol 25 35 45

Alt. IEC Min. Max. Min. Max. Min. Max.

t

AVAV

t

AVQ V

ELQV

GLQV

t

EHQZ

t

GHQZ

ELQX

GLQX

t

AXQX

t

ELICCH

t

EHICCL

t

cR

t

a(A)

t

a(E)

t

a(G)

t

dis(E)

t

dis(G)

t

en(E)

t

en(G)

t

v(A)

t

PU

t

PD

25 35 45 ns

12 20 25 ns

13 17 20 ns

555 ns

000 ns

333 ns

000 ns

25 35 45 ns

Unit

4

April 7, 2005

U630H16

Read Cycle 1: Ai-controlled (during Read cycle: E = G = VIL, W = NE = VIH)

t

(1)

cR

Ai

DQi

Output

Previous Data Valid

t

v(A)

Read Cycle 2: G-, E-controlled (during Read cycle: W = NE = VIH)

Ai

E

t

(7)

G

DQi

Output

I

CC

High Impedance

ACTIVE

STANDBY

en(E)

t

en(G)

t

(10)

PU

Address Valid

t

(2)

a(A)

(9)

t

(1)

cR

Address Valid

(2)

a(A)

t

(3)

a(E)

t

a(G)

(8)

(4)

Output Data Valid

g

t

dis(G)

Output Data Valid

dis(E)

(5)

(6)

f

t

(11)

PD

Switching Characteristics

No.

Write Cycle

12 Write Cycle Time t

13 Write Pulse Width t

Alt. #1 Alt. #2 IEC Min. Max. Min. Max. Min. Max.

AVAVtAVAV

WLWH

14 Write Pulse Width Setup Time t

15 Address Setup Time t

16 Address Valid to End of Write t

17 Chip Enable Setup Time t

AVW LtAVELtsu(A)

AVW HtAVEH

ELWH

18 Chip Enable to End of Write t

19 Data Setup Time to End of Write t

20 Data Hold Time after End of Write t

21 Address Hold after End of Write t

LOW to Output in High-Z

22 W

HIGH to Output in Low-Z t

23 W

h, i

DVWHtDVEHtsu(D)

WHDXtEHDXth(D)

WHAXtEHAXth(A)

t

WLQZ

WHQX

Symbol 25 35 45

t

cW

t

w(W)

WLEHtsu(W)

25 35 45 ns

20 30 35 ns

000ns

ELE

H

t

su(A-WH)

t

su(E)

t

w(E)

20 30 35 ns

12 18 20 ns

000ns

t

dis(W)

t

en(W)

10 13 15 ns

555ns

Unit

April 7, 2005

5

ZMD U630H16 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual