ZMD A²SI DATA SHEET

ASIP

ASIN

µ

µ F 5V

AMP

A²SI

Data Sheet Advanced AS-Interface IC

1 Features

• AS-i Complete Specification V2.11 compliant

• Integrated EEPROM

• Additional addressing channel using an opto-

electronic interface

• Extended address mode operation as programmable option (up to 62 slaves)

• High impedance AS-i line input, additional pins for further impedance optimizations

• DC voltage output, approximately 24 volts, not stabilized

• 5 volt DC voltage output, stabilized, CMOS logic can be supplied directly (e.g. µC)

• LED status indicator output (compliant with the standard indication recommendation)

• Integrated watchdog

3 Block Diagram

Figure 1: Block Diagram

U

2 Description

A²SI is a monolithic CMOS integrated circuit certified for AS-i (Actuator Sensor-interface) networks. AS-i networks are intended for industrial automation.

The main advantage of AS-i solutions is that actuators and sensors are connected using a two-wire unshielded cable that is easy to install. This cable transports both power and information/data.

AS-i network communication is based on the masterslave principle. The network can be extended (to cable lengths greater than 100m) by using the A²SI in the repeater mode configuration.

AS-i is a standard for the automation industry based on IEC 62026-2 and EN 50295.

The device is available in a 28-pin SSOP package.

2.2

24V

10

F

IN

U

OUT

U5R

U5RD

8 MHz

OSC1/2

2

CAP

C

R

CAP

ASI+

ASI –

All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

CAP

A

SI

POWERFAIL DETECTION

THERMAL

PROTECTION

ELECTRONIC

INDUCTOR

RECEIVE

TRANSMIT

GND2

0V

GND1

GND

POWER

SUPPLY

DIGITAL

LOGIC

IRD

OSCILLATOR

FID

LED

4

DOx

DIx

DSR

PST

Px

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A²SI

Data Sheet Advanced AS-Interface IC

4 Pin Description

Table 1: Pin Description

PIN # Name Type Description

1 ASIP INOUT To be connected to the AS-i-line ASI+ via reverse polarity protection diode 2 ASIN INOUT To be connected to the AS-i-line ASI3 0V SUPPLY Common 0V for all ports except ASIP/ASIN (to be connected to ASI- line) 4 IRD IN Addressing channel input 5 FID IN Input peripheral fault indication 6 OSC2 INOUT Crystal oscillator (8 MHz x-tal) 7 OSC1 IN Crystal oscillator / external clock input 8 DO3 OUT Output of data D3

9 DO2 OUT Output of data D2 10 DO1 OUT Output of data D1 11 DO0 OUT Output of data D0 12 GND SUPPLY Digital IO ground, must be connected to pin 0V 13 P3 I/O Input/output of parameter P3 14 P2 I/O Input/output of parameter P2 / receive strobe in ”Master Mode” 15 P1 I/O Input/output of parameter P1 / power fail in ”Master Mode” 16 P0 I/O Input/output of parameter P0 / data clock in ”Master Mode” 17 DI0 IN Input of data D0 18 DI1 IN Input of data D1 19 DI2 IN Input of data D2 20 DI3 IN Input of data D3 21 PST OUT Parameter strobe output 22 DSR I/O Data strobe output/reset input 23 U5RD SUPPLY Digital 5V supply input, should be connected to U5R 24 LED OUT Output LED "AS-i-Diagnosis" / addressing channel output 25 CAP IN/OUT For connection of external RC components 26 U5R OUT Internal 5V supply that might be used to supply external circuits as well 27 U 28 UIN SUPPLY Input of the power supply block (usually to be connected to the AS-i-line ASI+ via

OUT Supply of external circuitry (e.g. sensor, actuator, etc.), approx. V

OUT

reverse polarity protection diode)

minus 7 volt

UIN

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11

18

2

A²SI

Data Sheet Advanced AS-Interface IC

5 Pin Configuration

ASIP

ASIN

0V

IRD

FID OSC2 OSC1

DO3 DO2 DO1 DO0

GND

P3 P2

1 2 3 4 5 6 7 8 9 10

12 13 14

SI A

28 27 26 25 24 23 22 21 20 19

17 16 15

U

IN

U

OUT

U5R CAP LED U5RD DSR PST DI3

DI2 DI1 DI0

P0 P1

Figure 2: Pin Configuration, 28-Pin SSOP

6 Functional Block Description

6.1 Power Supply

An on-chip electronic inductor provides a de-coupled voltage at pin U internal 5V operating voltage. The de-coupling circuit (electronic coil) is connected between UIN and U and guarantees a high impedance seen at UIN. An external capacitor and resistor are required to allow a lowpass filter with a very high time constant. This high time-constant value is necessary to maximize the input impedance. The de-coupling circuit limits the current that can be drawn from U down the de-coupling circuit in case of an overload condition to prevent a total malfunction of the complete AS-i line. The regulated 5 volt supply voltage is connected to pin U5R. Two external capacitors are necessary to cope with fast internal and external load changes (spikes). Current drawn from pin U5R (up to 4 mA) has to be subtracted from the total load current. The power supply circuit dissipates the major amount of power.

and the power supply regulates the

OUT

. The power supply will shut

OUT

pins

The total power dissipation shall not exceed the specified values of Figure 6. The ground reference voltage for both UOUT and U5R is defined by the 0V pin. This pin must be connected to ASI- (ref. Figure 1: Block Diagram).

6.2 Receiver

The receiver detects signals on the AS-i line and delivers the appropriate pulses to the digital logic. The DC value of the input signal is removed and the AC signal is band-pass filtered. The digital output signals are extracted from the sin2-shaped input pulses by a set of comparators. The maximum voltage of the first negative pulse determines the threshold level for all following pulses. The maximum value is digitally filtered to guarantee stable conditions (burst spikes have no effect). This approach combines a fast adaptation to changing signal amplitudes with a high detection safety. The receiver delivers positive (P-PULSE) and negative (N-PULSE) pulses to the IC's logic. The logic resets the comparators after receiving the REC-RESET signal. When the receiver is turned on, the transmitter is turned off to reduce power consumption.

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A²SI

Data Sheet Advanced AS-Interface IC

6.3 Transmitter

The transmitter draws a modulated current between ASIP and ASIN pins to generate the communication signals. The shape of the current corresponds to the integral of a sin²-function. The transmitter uses a current DAC and a high current driver. In order to activate high current drive capability, a small current will be turned on automatically prior to each transmission (slave mode only). The current will be ramped up slowly to avoid false voltage pulses on the AS-I line. The amount of circuitry between ASI+ and ASI- pins is minimized to allow high impedance values. When the transmitter is turned on, the receiver is turned off to reduce power consumption.

6.4 Digital Logic

The digital logic block performs analysis of the received signal, controls reaction of the IC, transmits slave response, switches I/O-ports, and controls the internal EEPROM. Its principal function is described in detail in section 7.

6.5 Protection Circuitry

The device has several protection cells that prevent disruption and malfunction of the complete AS-i line. The thermal detection shuts down the power supply in case of over-heating condition (silicon temperature

> 140°C typically for more than 2 seconds) and when U

is shorted to GND for more than 2 seconds. The

OUT

device can only be reactivated by a power-on reset. An over-heating condition can occur by overloading any output pin. Therefore, the circuit monitors the operating conditions of the power supply (effectively monitors U

) and measures the temperature of the silicon.

OUT

6.6 Infrared Diode Input

The photo current input can be used as an alternative communication pin in slave mode. The IRD circuitry will be turned off when the communication has been switched to AS-i line. In Slave mode the logic sets IRD input to photo-detector mode and disables CMOS mode. In this photo-detector mode, signals of an external photo diode are amplified. In CMOS mode (master/repeater mode only), input signals have to be CMOS levels between 0V and V

U5R

.

6.7 Power-Fail Detection

The power-fail detector consists of a comparator that generates a logic signal in case the power supply drops below 22VDC (Power-Fail) for a time of more than t

(0.8 ± 0.1 ms). The power fail signal will be presented at

Loff

pin P1 in master mode only. Power-fail detection monitors the value of the ASIP voltage. It will activate a logic signal if power fails for more

than 1ms. The device is then buffered by the external capacitor at U

and the internal circuitry will be reset

OUT

when U5R supply voltage fails

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A²SI

Data Sheet Advanced AS-Interface IC

Figure 3 : Functional Block Diagram

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PORTS

UART

A²SI

Data Sheet Advanced AS-Interface IC

7 Description of Digital Logic

The digital logic is structured in four (4) parts:

1) the UART, which analyses the incoming signal from the AS-i line and ensures correct timing of output signals;

2) the STATE MACHINE, which controls the reaction of the IC;

3) the PORTS, which contain registers and digital I/O’s;

4) and finally the E²PROM, which contains the non-volatile data of the A2SI circuit.

Digital Logic

P-PULSE

N-PULSE

SEND-D

SEND-SBY

REC-RESET

POWER-FAIL

POWER-ON RESET

P-Pulse

REC-REG-0 REC-REG-1 REC-REG-2 REC-REG-3 REC-REG-4 REC-REG-5 REC-REG-6 REC-REG-7 REC-REG-8 REC-REG-9

REC-REG-10

REC-S

TRB

S

END-REG

S

END-REG

S

END-REG

S

END-REG

S

END-STRB

ADD-CLK

ADD-OUT

ADD-IN

-0

-1

-2

-3

E2PROM

DO-REG-0 DO-REG-1 DO-REG-2 DO-REG-3

DI-REG-0 DI-REG-1 DI-REG-2 DI-REG-3

PO-REG-0 PO-REG-1 PO-REG-2

STATE MACHINE

PO-REG-3

PI-0 PI-1

PI-2 PI-3

DATA-OUT-0 DATA-OUT-1 DATA-OUT-2 DATA-OUT-3 DATA-STRB RESET DATA-IN-0 DATA-IN-1 DATA-IN-2 DATA-IN-3 PARAM-OUT-0 PARAM-OUT-1 PARAM-OUT-2 PARAM-OUT-3 PARAM-STRB PARAM-IN-0 PARAM-IN-1 PARAM-IN-2 PARAM-IN-3 IRD-IN FAULT-IN LED-OUT OVER-HEAT U

S

HOUTDOWN

OUT

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Figure 4: Digital Logic

ACTIVITY

A²SI

Data Sheet Advanced AS-Interface IC

7.1 Operational Modes

7.1.1 Master/Repeater Mode

7.1.1.1 IRD Input (CMOS Input)

The IC sends signals retrieved from pin IRD to AS-i line as an AS-i telegram. The input signal is Manchestercoded and active low. A falling edge of the IRD signal, which is conducted to ADD-IN, starts the receiving process and triggers the Activity-Checker. Receive-Muxer selects pin IRD as input for the receive data

The IRD signal is connected with Send-Muxer to SEND-D via ADD-IN. The IRD signal is latched every 500 ns as long as there is activity on the input pin. If there is a high level on the IRD input longer then 7.0 µs, Activity- Checker will recognize this as no activity and Receive-Muxer is returning to idle state. The information on pin IRD is transported to pin SEND-D with a delay of 2.0 µs up to 2.5 µs. The sender is always in non-standby mode. The SEND-SBY signal is constant low and there is no generation of ADD-CLK.

P-PULSE N-PULSE

ADD-IN

S

END-REG

S

END-REG

S

END-REG

S

END-REG

PULSE

ENCODER

CHECKER

-0

-1

-2

-3

SEND

REGISTER

UART

RECEIVE

MUXER

MAN CODE

CHECKER

RECEIVE

REGISTER

REC-REG-0 REC-REG-1 REC-REG-2 REC-REG-3 REC-REG-4 REC-REG-5 REC-REG-6 REC-REG-7 REC-REG-8 REC-REG-9

REC-REG-10

SEND-D

SEND

STROBE

MUXER

ADD-OUT

UNIT

REC-STRB

SEND-STRB

CONTROL

UNIT

Figure 5: UART Block Diagram

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ADD-CLK

SEND-SBY

REC-RESET

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A²SI

Data Sheet Advanced AS-Interface IC

7.1.1.2 AS-i Input

A signal on the AS-i-line generates signals at the receiver output that are pulse coded with a minimal pulse width of 750 ns up to 875 ns. A pulse on the AS-i line starts the receiver and triggers the Activity-Checker through NPULSE or P-PULSE. The Receive-Muxer selects AS-i-line pins as input for the receive data. The N-PULSE and P-PULSE signals are latched every 250 ns as long as there is activity on the input pins. If there is a pulse distance on the AS-i-line inputs longer then 7.0 µs, the receiver will recognize this as no activity and the Receive- Muxer is going to the idle state.

The Pulse-Encoder is used to convert the active high pulse-coded signal to a active low Manchester-II-coded (MAN) signal. It will also check the pulse stream for timing and pulse errors (e.g. alternation error). In Master/Repeater mode the Pulse-Encoder additionally resynchronizes an error-free MAN telegram into a proper 3 µs time base. This is to eliminate the pulse jitter of the transformed AS-i telegram. The synchronized MAN signal is sent to ADD-OUT through the Send-Muxer. ADD-OUT is connected to LED-OUT on a higher hierarchy level. All in all, information on the AS-i-line pins is transported to pin LED-OUT with a delay of 2.5 µs up to

3.0 µs. In Master/Repeater mode the sender is never in standby mode, hence SEND-SBY signal is always low.

A generation of ADD-CLK is provided to simplify external processing of Manchester-coded data. The rising edge of the ADD-CLK signal is in the middle of the second half of the Manchester data assuring that correct binary data can be clocked into a shift register. The ADD-CLK starts with a rising edge 2.0 µs after the falling edge of the start bit at ADD-OUT with a period of 6.0 µs and a ratio of 1:1. The last rising edge of the ADD-CLK signal occurs 2.0 µs after the falling edge of the end bit at ADD-OUT.

If the received signal in the Master Mode is a valid slave answer with start bit, four (4) data bits, parity, and end bit and if a pause is following with a length greater than 6.0 µs, the UART generates the active high REC-STRB signal with a pulse width of 500 ns. The REC-STRB signal is connected to the P2 Parameter Output in this mode. It appears 10.0 to 10.5 µs after the rising edge of the end bit on AS-i-line.

7.1.1.3 Ports

Functional assignments of some IC ports depend on the operational mode of the IC. Thus, these ports perform multiple functions that are related to a particular mode of the IC.

In Master Mode, following signals and ports are connected:

PIN Slave Function Master Repeater

P0 Parameter output

port bit 0

P1 Parameter output

port bit 1

P2 Parameter output

port bit 2

LED LED

Fault indicator

output/addressing

channel output

IRD Addressing channel

input

REC-CLK REC-CLK

POWER-

FAIL

REC-STRB -

MAN-OUT MAN-OUT

MAN-IN MAN-IN

-

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A²SI

Data Sheet Advanced AS-Interface IC

7.1.2 Slave Mode

After IC-reset, Receive-Muxer is watching the two input channels (AS-i-line and IRD pin) depending on a multiplex select signal MPX. MPX has a frequency of about 1.0 kHz. If MPX is low, the Receive-Muxer selects the AS-i-line and vice versa if it is high, it selects the IRD pin as data input. The channel, from which a valid master call is received first, will be locked until the next IC-reset occurs.

7.1.2.1 IRD Input Mode (Photo Diode Input)

The photo diode current on the IRD input is Manchester-coded and low active (ref. 8.2.2 Addressing Channel Input IRD). A low level of the IRD signal starts the receiver and triggers the Activity-Checker. The Control-Unit is enabling the Receive-Register and the received information is clocked every 6 µs into the Receive-Register. If there is a high level on the IRD input longer then 7.0 µs, the Control-Unit will recognize this as no activity and the

Receive-Register will be disabled. If the received information is a correct master call with Start-Bit, eleven DataBits, Parity-Bit, End-Bit, and following pause of either greater than 6.0 µs (Synchronous Mode) or 18.0 µs

(Asynchronous Mode), the UART generates the internal active high REC-STRB signal with a pulse width of 500 ns.

If the received telegram contained an error, the Control-Unit will not generate the REC-STRB signal but go to its asynchronous state waiting for a pause at the IRD input. After a pause was detected, the UART is ready to receive the next telegram from the IRD input.

If a REC-STRB signal is generated, it occurs 9.5 µs up to 10.0 µs (Synchronous Mode) or 21.0 µs up to 21.5 µs (Asynchronous Mode), respectively, after the rising edge of the End-Bit on the IRD pin signal. If the slave was in asynchronous state, it now transforms to synchronous state. The Rec-Muxer is locked to the IRD input until the next IC-reset. After the generation of a REC-STRB signal the Control-Unit is waiting for about 6.0 µs for the SEND-STRB to be generated by the Main-State-Machine.

If the Control-Unit receives the active high SEND-STRB signal, it starts the transmission of the Send-Register data. Therefore, the Send-Register data will be converted to an active low Manchester II-coded (MAN) signal which is sent to the LED-OUT pin via ADD-OUT. The first falling edge of the MAN signal occurs 11.75 µs (Synchronous Mode) or 12.25 µs (Asynchronous Mode) after the rising edge of the REC-STRB signal. Hence, the delay from the rising edge of the End-Bit of the master call (IRD input) to the first falling edge of the slave response (LED output) is 21.25 to 21.75 µs (Synchronous Mode) or 33.25 to 33.75 µs (Asynchronous Mode). After the pause was detected, the UART is ready to receive the next telegram from the IRD input.

In case the Control-Unit will not receive a SEND-STRB signal within the given time frame (for instance, if this slave was not addressed), it will check for activity on the IRD input. Otherwise, it will just wait for the end of the response time (60 µs). In both cases the Control-Unit stays synchronous. Once a slave pause was detected, the UART is ready to receive the next telegram from the IRD input

7.1.2.2 AS-i Input Mode

A signal on the AS-i-line generates two pulse-coded signals (N-PULSE, P-PULSE) at the receiver output with a minimum pulse width of 750 to 875 ns. A pulse on the AS-i line starts the receiver and triggers the Activity- Checker through N-PULSE or P-PULSE.

The Pulse-Encoder is used to convert the active high pulse coded signal to an active low Manchester-II-coded (MAN) signal. It will also check the pulse stream for timing and pulse errors (e.g. alternation error). The Control- Unit enables the Receive-Register so that the received information can be clocked in every 6 µs. If there is a pulse distance on the AS-i-line input longer than 7.0 µs, the Control-Unit recognizes this as no activity and disables the Receive-Register.

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A²SI

Data Sheet Advanced AS-Interface IC

If the received information is a correct master call with Start-Bit, eleven (11) Data-Bits, Parity-Bit, End-Bit, and following pause of either greater than 6.0 µs (Synchronous Mode) or 18.0 µs (Asynchronous Mode), the UART generates the internal active high REC-STRB signal. If the received telegram contained an error, the ControlUnit will not generate the REC-STRB signal but go to its asynchronous state waiting for a pause at the AS-i line input. After a pause was detected the UART is ready to receive the next telegram from the AS-i line input.

If a REC-STRB signal is generated, it occurs 10.0 to 10.5 µs (Synchronous Mode) or 21.5 to 22 µs (Asynchronous Mode), respectively, after the rising edge (receiver comparator switching point) of the End-Bit on the AS-i line input. If the slave was in asynchronous state, it now transforms to synchronous state. The RecMuxer is locked to the AS-i line input until the next IC-reset. After the generation of a REC-STRB signal the Control-Unit is waiting for about 6.0 µs for the SEND-STRB to be generated by the Main-State-Machine.

If the Control-Unit receives the active high SEND-STRB signal (pulse width 500 ns), it starts the transmission of the Send-Register data. Therefore, the Send-Register data will be converted to an active low Manchester IIcoded (MAN) signal which is sent to the AS-i line transmitter via SEND-D. The first falling edge of the MAN signal occurs 11.75 µs (Synchronous Mode) or 12.25 µs (Asynchronous Mode) after the rising edge of the RECSTRB signal.

Hence, the delay from the rising edge of the End-Bit of the master call (AS-i input) to the first falling edge of the slave response (AS-i output) is 21.75 to 22.25 µs (Synchronous Mode) or 33.75 to 34.25 µs (Asynchronous Mode).

The SEND-SBY will always be set low 0.5 µs after the rising edge of REC-STRB. This is to turn on the transmitter and let it settle at its operation point. The small offset current, which is required to operate the transmitter, will be ramped up slowly to avoid any false voltage pulses on the AS-i line.

If all data is sent, the Control-Unit sets the sender in standby mode (SEND-SBY is high) and checks for a slave pause on the AS-i line input. After the pause was detected, the UART is ready to receive the next telegram from the AS-i line input.

In case the Control-Unit will not receive a SEND-STRB signal within the given time frame (for instance, if this slave was not addressed), it will check for activity on the AS-i line. If any activity is detected in a time frame of about 60 µs (another slave is transmitting data), the Control-Unit will wait for the next pause (slave pause). Otherwise, it will just wait for the end of the response time (60 µs). In both cases the Control-Unit stays synchronus. Once a slave pause was detected, the UART is ready to receive the next telegram from the AS-i line input.

7.1.2.3 Ports

Although the A²SI can still store the AS-i Slave IO-Configuration Code it does not decode the value to configure the direction of the Data-Port signals. The A²SI rather has distinctive Data-Out and Data-In ports which do always work in parallel.

If bi-directional Data I/O is desired on top of a single Data-Port only (for backwards compatibility), the Data-Out pins and the Data-In pins need to be shorted on the circuit board respectively and the non-volatile Multiplex flag has to be set TRUE.

In that case the output ports will switch to high impedance state for a certain time following the rising edge of the Data-Strobe and allow the input data to be put on the Data-Port.

The input data will be read inverted if the non-volatile Invert_Data_In flag is TRUE. This feature will simplify the circuitry for NPN-inputs.

Note: The Multiplex and the Invert_Data_In flags are Configuration flags which are stored in the Firmware region of the internal E²PROM. For a complete overview of the E²PROM content please see the A²SI Application Notes.

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A²SI

Data Sheet Advanced AS-Interface IC

The parameter port is always in bi-directional mode. The input data is the result of a wired-AND between the open drain output drivers and the application drivers.

7.1.2.4 Watchdog

Compliant to the AS-i Complete Specification, the IC contains an independent watchdog which is generally enabled by setting Watchdog_Active flag in the E²PROM to TRUE.

The watchdog will be activated for any slave address uneven to zero (0) after the reception of a Write_Parameter Request at the particular Slave Address. It will be deactivated by any circuit Reset and after the reception of a Delete_Address Request.

When activated, the Watchdog will be reset by every Write_Parameter and Data_Exchange Request received by the Slave. If no such request was received by the particular Slave within 40ms, a Hardware Reset will be performed and all Data and Parameter Outputs are switched inactive.

7.1.2.5 LED Output

An active FID (logic high) signal causes a flashing status LED (frequency approx. 2Hz) and Bit 1 of the AS-i Slave Status-Register (S1) is set as well. If FID is not active (logic low), S1 is cleared. In that case the status LED operation depends on the Data-Exchange-Disable flag.

The Data-Exchange-Disable is set to TRUE by each Reset of the A²SI. It becomes cleared (set to FALSE) after the first reception of a Write_Parameter Request.

If the Data-Exchange-Disable flag is set, no data exchange can be performed through the Data Ports which is indicated by a steady-on LED.

Note: An active FID has priority and will cause a flashing LED even if the Data-Exchange-Disable flag is set. If the UART has selected the IRD input channel, the LED output is again overwritten by the Addressing Channel

output. In this mode the LED pin does not operate as indicator LED output and periphery failures or status information can not be signaled.

7.1.2.6 Overtemp shutdown

The A²SI continuously observes its silicon die temperature. If the temperature rises above 140°C the IC will be put into shut-down and stay there until the next power-on reset occurs.

7.1.2.7 State Machine

The so-called Main-State-Machine performs the central control of the A2SI IC in terms of operation mode selection, EEPROM access control, processing of master requests and the control of the IC ports. The MainState-Machine interfaces with the UART through the Receive- and the Send-Register as well as certain strobe signals.

To avoid the situation in which a slave IC gets locked in a not allowed state (i.e by emission of strong electromagnetic radiation) and thereby would jeopardize the entire system, all prohibited states of the state machine will lead to a RESET which is comparable to the AS-i call ”Reset Slave (RES)”.

7.2 Summary of Master Calls

In the following diagram all Master Calls that will be decoded by the A2SI are listed. The "Enter Program Mode" call is intended for factory programming of the IC only. In order to achieve EEPROM firmware protection and to comply to the complete AS-i specification, the call "Enter Program Mode" has to be deactivated before shipment of the slave.

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Master Request

Slave Response

Instruction

MNESTCBA4A3A2A1A0I4I3I2I1I0PBEBSBI3I2I1I0PB

EB

~Sel

E0

~Sel

I0

Code-1

1

~Sel

Configuration

0

Sel

0

Sel

0

Sel

0

Sel

1

~Sel

A²SI

Data Sheet Advanced AS-Interface IC

Table 2: A²SI Master Calls and Related Save Responses

Data Exchange

Write Parameter

Address Assignment Write Extented ID

Delete Address

Reset Slave Read IO

Read ID Code

Read ID Code-1

Read ID Code-2

Read Status

Broadcast (Reset)

Enter Program Mode

DEXG 0 0 A4 A3 A2 A1 A0 0

WPAR 0 0 A4 A3 A2 A1 A0 1

ADRA 0 0 0 0 0 0 0 A4 A3 A2 A1 A0 PB 1 0 0 1 1 0 PB 1

WID1 0 1 0 0 0 0 0 0 ID3 ID2 ID1 ID0 PB 1 0 0 0 0 0 PB 1

DELA 0 1 A4 A3 A2 A1 A0 0 0 Sel 0 0 0 PB 1 0 0 0 0 0 PB 1

RES 0 1 A4 A3 A2 A1 A0 1

RDIO 0 1 A4 A3 A2 A1 A0 1

RDID 0 1 A4 A3 A2 A1 A0 1

RID1 0 1 A4 A3 A2 A1 A0 1

RID2 0 1 A4 A3 A2 A1 A0 1

RDST 0 1 A4 A3 A2 A1 A0 1

BR01 0 1 1 1 1 1 1 1 0 1 0 1 PB 1 --- no slave response ---

PRGM 0 1 0 0 0 0 0 1 1 1 0 1 PB 1 --- no slave response ---

D3

D2 D1 D0 PB 1 0

P3

P2 P1 P0 PB 1 0

1 0 0 PB 1 0 0 1 1 0 PB 1

0 0 0 PB 1 0 IO3 IO2 IO1 IO0 PB 1

0 0 1 PB 1 0 ID3 ID2 ID1 ID0 PB 1

0 1 0 PB 1 0 ID3 ID2 ID1 ID0 PB 1

0 1 1 PB 1 0 ID3 ID2 ID1 ID0 PB 1

1 1 0 PB 1 0 S3 S2 S1 S0 PB 1

D3 E3D2 E2D1 E1D0

P3 I3P2 I2P1 I1P0

Note: In extended address mode the "Select Bit" defines whether the A-Slave or B-Slave is being addressed. Dependent on the type of master call the I3 bit carries the select bit information (Sel) or the

PB 1

inverted select bit information (~Sel).

7.3 Program Mode

Provided that the non-volatile configuration flag, Program-Mode-Disable, has not been set, the device can be transferred in program mode by utilizing the “Enter Program Mode” call.

Please refer to the A²SI Application Notes [4] for details of the programming process.

AS-i Complete Specification compliance note:

In order to ensure full compliance with the AS-i Complete Specification, the Program-Mode-Disable flag must be set in the final manufacturing and configuration process before an AS-i slave device is being delivered to field application users.

All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

12/30

A²SI

Data Sheet Advanced AS-Interface IC

8 Electrical Specification

8.1 Absolute Maximum Ratings

Any stress above the listed Absolute Maximum Ratings may cause permanent damage to the device. The given conditions represent a stress rating only. Functional operation of the device at those conditions or at any other stress above the Operational Limits is not implied. Exposure to maximum rating conditions for extended times may effect device performance, functionality, and reliability.

Table 3: Absolute Maximum Ratings

SYMBOL PARAMETER MIN. MAX. UNITS NOTE

V

0V ,VGND

V

ASIP

V

ASIN

V

ASIP-ASIN

V

ASIPP

Voltage reference 0 0 V

Positive AS-i supply voltage -0.3 40 V

Negative AS-i supply voltage -0.3 20 V

Voltage difference from ASIP to ASIN (V

AS-i supply pulse voltage, voltage difference between pins

ASIP

- V

) -0.3 40 V

ASIN

50 V

ASIP and ASIN (from ASIP to ASIN)

V

Aux. power supply input voltage -0.3 40 V

UIN

V

Aux. power supply input voltage pulse 50 V

UINPV

V

Voltage at pins DI3 - DI0, DO3 - DO0, P3 - P0, DSR, PST,

inputs1

LED, FID, U

OUT

-0.3 V

UIN

0.3

+

V V

1

2

3

inputs1

≤ 40V

V

Voltage at pins OSC1, OSC2, IRD, CAP, U5R, U5RD -0.3 7 V

inputs2

Iin Input current into any pin except supply pins -25 25 mA H Humidity non-condensing V

Electrostatic discharge – human body model (HBM1) 4000 V

HBM1

V

Electrostatic discharge – human body model (HBM2) 2000 V

HBM2

V

Electrostatic discharge – equipment discharge model (EDM) 400 V

EDM

θ

STG

P

Total power dissipation 0.85 W

tot

1 ASIN-pin shall be shorted to 0V-pin on PCB. 2 Reverse polarity protection has to be performed externally. 3 Pulse with ≤ 50µs, repetition rate ≤ 0.5 Hz. 4 Level 4 according to JEDEC-020A is guaranteed 5 HBM1: C = 100pF charged to V 6 HBM2: C = 100pF charged to V 7 EDM: C = 200pF charged to V 8 At maximum operating temperature, the allowed total power dissipation depends on the additional thermal resistance from case to ambient and on the operation ambient temperature (see Figure 6).

CAUTION: ELECTROSTATIC SENSITIVE DEVICE Permanent damage resulting in a loss of functionality or performance

may occur if this device is subjected to high-energy electrostatic discharge.

Storage temperature -55 125 °C

with resistor R = 1.5kΩ in series, valid for ASIP-ASIN only.

HBM1

with resistor R = 1.5kΩ in series, valid for all pins except ASIP-ASIN.

HBM2

with no resistor in series, valid for ASIP-ASIN only.

EDM

4

5

6

7

8

All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

13/30

A²SI

Data Sheet Advanced AS-Interface IC

Ptot = f (Ta); 1L / 2L = 1 layer / 2 layer PCB

1

Figure 6: Maximum Power Dissipation,

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

-25 0 25 50 75 100

Table 4: Operating Conditions

Ptot (2L) Ptot (1L)

Ta

P

= f(Ambient Temperature)

TOT

SYMBOL PARAMETER MIN. MAX. UNITS NOTE

V

Positive supply voltage 16 33.1 V

UIN

V

Negative AS-i supply voltage 0 0 V

ASIN

V0V, V I

ASI

I

CL1

I

CL2

θ

amb

1 DC voltage 2 ASIN shall be shorted with 0V to ensure proper functionality of transmitter circuit. 3 fc = 8.000 MHz, no load at any pin without reaction of the circuit, ASIP is short-cut to UIN and ASIN to 0V respectively.

Negative supply voltage 0 0 V

GND

Supply current at V

= 30V 9 mA

ASI

Max. output sink current at pins DO3 - DO0, DSR 10 mA Max. output sink current at pins P0 - P3, PST 10 mA

Ambient temperature range, operating range -25 85 °C

1

2

3

8.2 DC and AC Characteristics

All parameters are valid for the recommended range of V tested within the recommended range of V

ASIP

- V

, VIN - V0V, θamb = +25°C (+ 85°C and - 25°C on sample

ASIN

base only) unless otherwise stated. Unused input pins shall be connected to a suitable potential within the application circuit because there are no internal pull-up/down resistors. It is recommended to connect these pins either to 0V or via resistor to U

or U5R respectively.

OUT

With an external LOW signal at the data strobe pin DSR (pull-down open drain driver) for more than 44µs, the IC will execute its reset procedure. During power on procedure all data and parameter ports will stay on highimpedance state.

ASIP

- V

ASIN

, V

- V0V, and θamb. The devices are

UIN

If the IC has been put in its initialization procedure by an external reset via DSR, the LED pin should not be toggled externally to avoid that the IC control logic transfers to test mode.

All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

14/30

A²SI

Data Sheet Advanced AS-Interface IC

8.2.1 Digital Input and Output Pins

Table 5: Input/Output Voltage and Current

SYMBOL PARAMETER MIN. MAX. UNITS NOTE Pins DI0 - DI3, P0 - P3, DSR, FID, PST

VIL Voltage range for input ”low” level, not P0 – P3 0 2.5 V VIL Voltage range for input ”low” level, only P0 – P3 0 2.4 V V

Voltage range for input ”high” level 3.5 V

ICH

V

Hysteresis for switching level 0.25 V

HYST

IIL Current range for input ”low” level -20 -5 µA I

Current range for input ”high” level -10 10 µA VO = 5V

ICH

I

Current range for high voltage input 2 mA VO = 30V

IHV

Pins DO0 - DO3, P0 - P3, DSR, PST

V

UOUT

1

V

Voltage range for output ”low” level 0 1 V I

OL1

V

Voltage range for output ”low” level 0 0.4 V I

OL2

= 10mA

OL1

= 2mA

OL2

IOH Output leakage current -10 10 µA VOH = 4.5V CDL Capacitance at pin DSR 10 pF

2

Pin LED

VOL Voltage range for output ”low” level 0 1 V I

= 10mA 3

OL1

IOH Output leakage current -10 30 µA VOH = 40V 4

1 Switching level approximately 3V, i.e. 3V ± V 2 For higher capacitive load an external pull-up resistor connected to UOUT is necessary to reach VIH ≥ 3.5V at DSR in less than 35 µs

after the beginning of a DSR = Low pulse, otherwise a reset will be executed. 3 The output driver sends a “low” (LED on). 4 The output driver sends a “high” (equivalent to tri-state, LED off).

HYST

.

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15/30

tCYCLE

with external signal source value

keep stable

A²SI

Data Sheet Advanced AS-Interface IC

Table 6: Timing Parameter Port

SYMBOL PARAMETER MIN. MAX. UNITS NOTE

t

Valid output data; P0 - P3 to PST-H/L 0.1 0.5 µs Figure 7

setup

t

PST pulse width 5 6 µs

PST

t

PST-H/L to parameter input latch 11 13.5 µs

PI-latch

t

Next cycle 150 µs

CYCLE

1 The parameter input data must be stable within the period that is defined by minimum and maximum t

tsetup tPST

PI-latch

.

1

PST

PO0-PO3

parameter input value (PIx) = parameter output value (POx) wired AND

Figure 7: Timing Diagram Parameter Port P0 - P3

Parameter port output data

tPI-latch

min

max

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16/30

DI0-DI3

A²SI

Data Sheet

Advanced AS-Interface IC

Table 7: Timing Data Port Outputs

SYMBOL PARAMETER MIN. MAX. UNITS NOTE

t

Valid output data; DO0 - DO3 to DSR-H/L 0.1 0.5 µs Figure 8

setup

t

Valid output data; DO0 - DO3 to DSR-L/H 0.1 0.5 µs

hold

t

DSR pulse width 5 6 µs

DSTR

t

DSR-H/L to data input latch 11 13.5 µs

DI-latch

t

Next cycle 150 µs

CYCLE

1 The data input must be stable within the period that is defined by minimum and maximum of t

DI-latch

.

tCYCLE

1

tsetup

tDSR

DSR

DO0-DO3

Figure 8: Timing Diagram Data Port DO0 - DO3

Data port output data

Data port input data

tDI-latch

data remains,

flag is not set

thold

if multiplex

min

if multiplex flag is set

hi-z,

keep stable

max

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17/30

DSR

DO0-DO3

PO0-PO3

A²SI

Data Sheet Advanced AS-Interface IC

Table 8: Timing Reset Signal

SYMBOL PARAMETER MIN. MAX. UNITS NOTE

t

Ext. DSR (no reset) 35 µs Figure 9

ALM1

t

Ext. DSR to DO0 - DO3 Hi-Z 44 µs

ALM2

t

Reset time after DSR = external L ->H transition 2 ms

RESET1

Data port output data

tRESET1

>0

hi-z

Parameter port output data

tALM1 tALM2

Figure 9: Timing Diagram External Reset via DSR

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18/30

A²SI

Data Sheet

Advanced AS-Interface IC

8.2.2 Addressing Channel Input IRD

The addressing channel input IRD is a dedicated photo-diode input. The photo-diode can be connected to the pins IRD and 0V directly. The IRD input is a AC current input. A valid signal at the current input has to have a certain amplitude (range) and should not exceed a certain offset value. A logic "low" at the IRD input will be detected, if the present signal value drops below I than I

IRDO

+ I

IRDA

.

IRD input current

, and a "high” will be detected, if its present value is greater

IRDO

MAX I

IRDA

MIN I

IRDA

MAX I

IRDO

time

Figure 10: Photo Current Waveform

Table 9: AC Current Amplitude of IR Diode Input in Slave Mode

SYMBOL PARAMETER MIN. MAX. UNITS NOTE

I

Input current offset 10 µA

IRDO

I

Input current amplitude 10 100 µA

IRDA

I

Input current amplitude 25 100 µA

IRDA

PP

IC Revision A&B

PP

IC Revision C

PP

Table 10: Digital Input IRD in Master/Repeater Mode

SYMBOL PARAMETER MIN. MAX. UNITS NOTE

VIL Voltage range for input ”low” level 0 2.5 V V

Voltage range for input ”high” level 3.5 V

ICH

Tr /Tf Rise/fall time 100 ns

V

U5R

1

1 In order to avoid jittery on the AS-i line, the rise/fall time of the IRD input signal should be as low as possible.

8.2.3 Fault Indication Input, FID

The fault indication input FID is a digital input dedicated for a periphery fault messaging signal. The S1 status bit is equivalent to the FID input signal. A FID transition will occur at S1 with a certain delay, because a synchronizer circuit is put in between.

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19/30

A²SI

Data Sheet Advanced AS-Interface IC

8.3 Voltage Outputs

Table 11: Properties of Voltage Output Pins U

and U5R

OUT

SYMBOL PARAMETER MIN. MAX. UNITS NOTE

V

U

UOUT

V

U

UOUTp

t

U

UOUTp

V

Voltage drop from pin UIN to pin U

DROP

V

5V supply voltage 4.5 5.5 V

U5R

I

U

UOUT

I5V U5R output supply current 0 4 mA I Io Total voltage output current I I

Short circuit output current 50 mA

UOUTS

C

Load capacitance at U

LUOUT

C

Load capacitance at U5R 1 µF

L5V

1 COUT = 10 µF, output current switches from 0 to 30 mA and vice versa. 2 11.0V < VOUT < 27.6V.

output supply voltage V

OUT

output voltage pulse deviation 1.5 V

OUT

output voltage pulse deviation width 2 ms

OUT

6.5 7.7 V V

OUT

output supply current 0 30 mA I

OUT

+ I5V 30 mA

UOUT

10 470 µF

OUT

UIN

V

DROPmax

-

V

UIN

V

DROPmin

-

V I

UOUT

UIN

U5R

UOUT

= 30mA

1

> 22V

= 0 mA

< 26 mA

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20/30

A²SI

Data Sheet

Advanced AS-Interface IC

8.3.1 AS-i Bus Load

The following parameters are determined with short-cut between the pins ASIP and UIN and the pins ASIN and 0V, respectively.

Table 12: AS-i Bus Interface Properties (Pins ASIP/ASIN and UIN)

SYMBOL PARAMETER MIN. MAX. UNITS NOTE

2, 3

1

2

V

Input AS-i voltage at UIN V

UIN

V

I

Input current limit at UIN 56 mA

LIN

V

Input signal voltage difference between ASIP and

SIG

+

UOUTmin

DROPmax

V

UOUTmax

+ V

DROPmin

3 8 VPP

ASIN

I

Modulated output peak current from ASIP to ASIN 55 68 mAP

SIG

C

Parasitic capacitance of the external over-voltage

Zener

20 pF

protection diode (zener diode)

R

Equivalent resistor of the device 16

IN1

L

Equivalent inductor of the device 18 mH

IN1

C

Equivalent capacitor of the device 30 pF

IN1

R

Equivalent resistor of the device 16

IN2

L

Equivalent inductor of the device 12 18 mH

IN2

C

Equivalent capacitor of the device 15 + (L-12mH)*

IN2

2.5pF/mH

V

kΩ

pF

1 DC Parameter 2 The equivalent circuit of a slave (which is calculated from the impedance of the device and the paralleled external over-voltage

protection diode (zener diode)) has to satisfy the Complete AS-i-Specification v.2.1 concerning the requirements for the extended

address range. 3 Subtracting the maximum parasitic capacitance of the external over voltage protection diode (20pF) either the triple RIN1, LIN1 and

CIN1 or the triple R

IN2

, L

IN2

and C

has to be committed by the device to fulfill the Complete AS-i-Specification v2.1.

IN2

8.3.2 Input Impedance Control

Table 13: CAP Pin

SYMBOL PARAMETER MIN. MAX. UNITS NOTE

R

External filter resistor 0 2.2

CAP

C

External filter capacitor 4.7 100 nF

CAP

1 Recommended values for optimal impedance are: R R See chapter 11, Package Marking, for details on how to distinguish different IC versions.

2 The de-coupling capacitor and serial resistor define internal low-pass filter time constant; lower values decrease the impedance but

improve the turn-on time. Higher values do not improve the impedance but do increase the turn-on time. The turn-on time also

depends on the load capacitor at UOUT. After connecting the slave to the power the capacitor is charged with the maximum current

IUOUT. The impedance will increase when the voltage allows the analog circuitry to fully operate.

= 1.2 kΩ and C

CAP

= 430 – 680 Ω and C

CAP

= 10 nF (IC Revision A)

CAP

= 4.7 nF (IC Revision B and C)

CAP

kΩ

1

1, 2

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21/30

A²SI

Data Sheet Advanced AS-Interface IC

8.3.3 Oscillator

Table 14: Oscillator Pins (OSC1 and OSC2)

SYMBOL PARAMETER MIN. MAX. UNITS NOTE

C

External parasitic capacitor at oscillator pins

OSC

OSC1, OSC2 VIL Input ”low” voltage 0 1.5 V V

Input ”high” voltage 3.5 V

ICH

1 For external clock applied to OSC1 only.

9 Development Information Data

Table 15: Information Data Conditions: Asynchronous mode, reset to default comparator level at „line pause“.

0 5 pF

V

U5R

1

Symbol V

LSIGon

PARAMETER MIN. MAX. UNITS NOTE

Receiver comparator threshold level

45 50 % Related to

(see Figure 11)

t

Reset time after Master Call „Reset AS-i-Slave“ or

reset1

2 ms

DSR = external L ->H transition t

Reset time after power on 30 ms

reset2

t

Reset time after power on with high capacitive load 1000 ms

reset3

V

ASIP-PF

V

voltage to detect power fail (master mode

ASIP

21.5 23.5 V

only) t

Power supply break down time (master mode only) 0.7 0.9 ms

Loff

V

POR1F

V

voltage to trigger internal reset procedure,

U5R

3.0 4.0 V

falling voltage V

POR1R

V

voltage to trigger INIT procedure, rising

U5R

2.5 3.5 V

voltage t

Power-on reset pulse width 4 6 µs

Low

T

Chip temperature for thermal shut down

Shut

125 160 °C

(overheating)

1 Guaranteed by design only. 2 ‘Power_on’ starts latest at VUIN = 18V, external capacitor at pin UOUT = 10µF. 3 CUOUT = 470µF, treset3 is guaranteed by design only. 4 CUOUT > 10µF, no power fail generated at VASIP < VASIP-PF for t < tLoff (in master mode only).

amplitude of 1st

pulse

1

2

3

4

1

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22/30

V

< ca. 15V

0V

≤

V

t

Low

V

ASIN

A²SI

Data Sheet Advanced AS-Interface IC

"DC level"

LSIGon = (0.45 - 0.50) * VSIG / 2

The IC determines the

LSIGon

amplitude of the first negative pulse of the AS-i telegram. This amplitude is asserted to be VSIG / 2.

First negative

pulse of the

AS-i telegram

Figure 11: Receiver Comparator Set Up

MASTER MODE only All Modes

ASIP

t

Loff

UIN

U5R POR1F

POR1R

SIG

/ 2

POR (active low)

No reset, but if the break down time exceeds t

, a power-fail

Loff

signal will be generated

Power-on Reset will be active, if the V drops below V

U5R

POR1F

Reset will be initalized

Figure 12: Power-Fail Generation (in Master Mode) and Reset Behavior (All Modes)

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23/30

ASI

Ω

A²SI

Data Sheet Advanced AS-Interface IC

10 Application Circuits

The following figures show typical application cases of the A2SI IC. Figure 14 shows an application circuit in which the A2SI is replacing an ASI3+ circuit. Finally, Figure 15 shows how the A2SI circuit can be used to perform the analog/digital interface between the AS-i-line and the master electronics. Furthermore this figure shows that the IC can be used in repeater applications as well.

10.1 EMC Precautions

Precaution must be taken to avoid radio frequency interference. It is recommended to keep input lines as short as possible and to connect unused inputs to U be de-coupled with ceramic capacitors (10 to 100 nF) in addition to the normal de-coupling capacitors. Also, it is recommended to connect a pull-up resistor from DSR (pin 22) to U reset under difficult EMC conditions.

10.2 Typical Slave Application

A2SI

28

U

IN

7

OSC1

8 MHz

6

OSC2

1

ASIP

2

ASIN

25

CAP

R

C

CAP

3

0V

GND

Figure 13: Typical Application, Slave Mode

through a pull-up resistor. Furthermore, the supply pins should

OUT

or U5R in order to avoid unintentional

OUT

17

DI0

18

DI1

19

DI2

20

DI3

11

DO0

10

DO1

9

DO2

8

DO3

16

P0

15

P1

14

P2

13

P3

22

DSR

21

PST

5

FID

23

12

U5RD

U5R

U

OUT

LED

IRD

26

27

RED GREEN

24

4

10µF

22 k

10n

2.2µF

DI_0 DI_1 DI_2 DI_3

DO_0 DO_1 DO_2 DO_3

P0 P1 P2 P3

DS&Reset PST

Fault Input39V/1W

+5V

+24V

0V

Note: Figure 13 and Figure 14 show all digital (data and parameter) ports without the application specific connections. For correct function, it is important to consider that all output drivers are open drain stages and hence each port must be connected with an appropriate pull-up resistor.

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24/30

ASI

C

R

Ω

A²SI

Data Sheet Advanced AS-Interface IC

10.3 Typical ASI3+ Compatible Application

7

OSC1

8 MHz

39V/1W

CAP

Figure 14: Typical ASI3+ Compatible Application

28

25

6

1

2

3

A2SI

OSC2

U

IN

ASIP

ASIN

CAP

0V

GND

12

DO0 DO1 DO2 DO3

DSR

PST

U5RD

U5R

U

OUT

LED

IRD

DI0 DI1 DI2 DI3

P0 P1 P2 P3

FID

26

23

27

24

17 18 19 20

11 10 9 8

16 15 14 13

22 21

5

4

10n

10µF

DIO-0 DIO-1 DIO-2 DIO-3

P0 P1 P2 P3

DS&Reset PS

22 k

+5V

+24V

2.2µF

10n

0V

Note: Depending on I/O-configuration, DO- and DI-ports are connected and Multiplex-Flag is set.

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25/30

(optional)

ISOLATION

/POWER-FAIL

A²SI

Data Sheet Advanced AS-Interface IC

10.4 Typical Master/Repeater Application

U

OUT

12

DI0 DI1 DI2 DI3

DO0 DO1 DO2 DO3

P0 P1 P2 P3

DSR

FID

LED

U5RD

U5R

IRD

PST

ASI+

ASI–

8 MHz

39V

R

CAP

A2SI

28

U

IN

7

OSC1

6

OSC2

1

ASIP

2

ASIN

25

CAP

C

CAP

3

0V

GND

27

16 15 14 13

22 5

24 23 26

4

21

2.2µF

10µF

10n

+U Vo

GND

+5V

+U

B

Vo

GND

+U

B

Vo

GND

+U

B

Vo

GND

B

REC-CLK

REC-STRB (optional)

RECEIVE DATA

SEND

0V

Figure 15: Master/Repeater Application

For further information see also A²SI Application Note.

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26/30

A²SI

Data Sheet Advanced AS-Interface IC

11 Package Outline

Figure 16: SSOP Package

Figure 17: Package Dimensions

Table 16: Package Dimensions (mm)

Symbol A A1 A2 B C D E e H L Nominal 1.86 0.13 1.73 0.30 0.15 10.20 5.30 7.80 0.75 4° Maximum 1.99 0.21 1.78 0.38 0.20 10.33 5.38 7.90 0.95 8° Minimum 1.73 0.05 1.68 0.25 0.13 10.07 5.20

0.65 BSC

7.65 0.55 0°

α

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27/30

PIN 1

TOP VIEW

BOTTOM

PIN 1

A

A²SI

Data Sheet Advanced AS-Interface IC

12 Package Marking

2

SI

R-XXXXYZZ

+

Figure 18: Package Marking

ZMD

LLLLLL

Top Marking: A²SI Product name ZMD Manufacturer R- Revision code XXXX Date code (year and week) Y Assembly location ZZ Traceability

Bottom Marking: LLLLLL ZMD Lot Number The yellow dot indicating pre-programmed Master function is printed at the pin 1 marking ⊕.

Note: IC Revision A did not have a revision code marking. ICs without a Revision Code are equivalent to

Revision A. Revision B shows “B-“, Revision C shows “C-“.

All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

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A²SI

Data Sheet Advanced AS-Interface IC

13 Evaluation boards for A²SI

Evaluation board equipped with A²SI can be ordered from Bihl+Wiedeman GmbH (www.bihl-wiedemann.de)

Figure 19: Evaluation board dimensions (L x W x H):(34 x 31 x 8) mm³

14 Ordering Information

Ordering

Code

A2SI-ST

A2SI-SR

A2SI-MT

A2SI-MR

Description Operating Temperature

Standard version of

A²SI

Standard version of

A²SI

Pre-programmed

master function

Pre-programmed

master function

Package Type Device

Range

-25°C to 85°C 28-pin SSOP (5.3 mm)

Shipping Form

Marking

A²SI Tubes

(47 parts/tube)

A²SI Tape-and-Reel

(1500 parts/reel)

A²SI

+ yellow dot

A²SI

+ yellow dot

Tubes

(47 parts/tube) Tape-and-Reel

(1500 parts/reel)

All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

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A²SI

Data Sheet Advanced AS-Interface IC

15 Application Support

15.1 AS-International Association

Documentation and promotional materials as well as detailed technical specifications regarding the AS-Interface Bus Standard are available from:

ASInternational Association:

Refer to the Association’s website here above for contact info on nine local AS-Interface associations which provide local support within Europe, in the US and in Japan.

15.2 ZMD

An Application Note an A²SI can be found under www.zmd.biz A²SI device related application support requests can be addressed to asi@zmd.de

15.3 ZMD

Since the A²SI-E is a high performance package option of the A²SI the application notes A²SI apply. The Application Note A²SI can be found under www.biz.com.

A²SI/A²SI-E device related application support requests can be addressed to asi@zmd.de.

15.4 ZMD Application Support Partners

ZMD Application Support Partners:

16 Sales Contacts

For further information:

Products sold by ZMD are covered exclusively by the warranty, patent indemnification and other provisions appearing in ZMD standard "Terms of Sale". ZMD makes no warranty (express, statutory, implied and/or by description), including without limitation any warranties of merchantability and/or fitness for a particular purpose, regarding the information set forth in the Materials pertaining to ZMD products, or regarding the freedom of any products described in the Materials from patent and/or other infringement. ZMD reserves the right to discontinue production and change specifications and prices of its products at any time and without notice. ZMD products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional mutually agreed upon processing by ZMD for such applications.

ZMD reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.

All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

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Contact - Rolf Becker Zum Taubengarten 52 D-63571 Gelnhausen PO Box 1103 Zip (63551) Tel: +49 6051 47 32 12 Fax: +49 6051 4732 82 Email: as-interface@t-online.de http://www.as-interface.net

Bihl+Wiedemann Flosswoerthstrasse 41 D-68199 Mannheim, Germany Tel.: +49 621 3 3996 0 Fax: +49 621 3 3922 39 Email: mail@bihl-wiedemann.de http://www.bihl-wiedemann.de

ZMD Stuttgart Office Nord-West-Ring 34 70974 Filderstadt - Bernhausen Tel.: +49 (0)711.674.517-0 Fax: +49 (0)711.674.517-99 sales@zmd.de

Fieldbus specialists 217 Colchester Road, Kilsyth 3137 Victoria, Australia Tel.: +61 3 9761 4653 Fax: +61 3 9761 5525 Email: fs_sales@fieldbus.com.au http://www.fieldbus.com.au

ZMD AG Grenzstrasse 28 01109 Dresden, Germany Tel.: +49 (0)351.8822.310 Fax: +49 (0)351.8822.337 sales@zmd.de

ZMD America Inc. 201 Old Country Road, Ste 204 Melville, NY 11747 Tel.: (631) 549-2666 Fax: (631) 549-2882 sensors@zmda.com

ZMD A²SI DATA SHEET

Specifications and Main Features

Frequently Asked Questions

User Manual