FEATURES
Z891350
Z89135
LOW-COST DUAL-PROCESSOR
DTAD CONTROLLERS
■ Part Z8 ROM Z8 RAM* Speed
Number (KBytes) (KBytes) (MHz)
Z89135 24 236 20
*General-Purpose
■ Part DSP ROM DSP RAM Speed
Number (Words) (Words) (MHz)
Z89135 6K 512 20
■ 68-Pin PLCC Package
■ 4.75- to 5.25-Volt Operating Range
■ Low-Power Consumption (200 mW Typical)
■ 0°C to +55°C Temperature Range
■ 25 Expanded Register Files
GENERAL DESCRIPTION
Zilog's Digital Voice Processor Controller family
combines a Z8® microcontroller and a DSP processor
on-chip for a cost-effective turnkey system in digital
telephone answering devices and other voice processing
applications.
The dual-processor architecture is loosely coupled by
mailbox registers and an interrupt system, enabling DSP or
Z8 programs to be directed by events in each other's
domain.
■ 47 Input/Output Lines
■ Six Vectored, Prioritized Z8 Interrupts with
Programmable Polarity
■ Three Vectored, Prioritized DSP Interrupts with
Programmable Polarity
■ Two Analog Comparators
■ Two Programmable Z8 8-Bit Counter/Timers,
Each with Two 6-Bit Programmable Prescaler
■ Watch-Dog Timer /Power-On Reset
■ On-Chip Oscillator that Accepts a Crystal,
Ceramic Resonator, LC, RC, or External Clock Drive
■ RAM and ROM Protect, Low-EMI Option
The Z89135 device offers a half-flash 8-bit A/D
converter with up to 128 kHz sample rate and a 10-bit
Pulse-Width modulator (PWM) D/A converter, eliminating
the need for an external CODEC.
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.:
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
The Z8 microcontroller uses an expanded register file to
allow access to register-mapped peripheral and I/O
circuits for programming versatility.
The 16-bit DSP processor features a 24-bit ALU and
accumulator with single-cycle instructions, providing the
algorithm processing power necessary for telephone voice
quality.
Connection Circuit Device
Power V
Ground GND V
CC
V
DD
SS
281
GENERAL DESCRIPTION (Continued)
Z89135
Address
or I/O
(Nibble
Address/Data
or I/O
(Byte
I/O
(Bit
P00
P01
P02
P04
P05
P06
P10
P11
P12
P13
P14
P15
P16
P20
P21
P22
P23
P24
P25
P26
RMLS
/AS
/DS
XTAL1
VDD
GND
Timer 0
Capture Reg.
Port 0
Register Bus
24 Kbytes
Program
ROM
(Z89135)
Expanded Register
Port 1 Port 4
Timer 1
Internal Address Bus
Internal Data Bus
File
(Z8)
Peripheral
Register
(DSP)
mailbox
Port 2 Port 5
6K Words
Program DSP Core
Ext.
Memory
Control
OSC
Power
Timer 2 Timer 3
Internal Address Bus
Internal Data Bus
INT 1
INT 2
Register File
256 x 8 Bit
Z8 Core
Expanded
Extended Bus of the DSP
256 Word
RAM 0
Extended Bus of the DSP
256 Word
RAM 1
Port 3
DSP Port
PWM
(10-Bit)
ADC
(8-Bit)
P31
P32
P34
P35
P36
P40
P41
P42
P43
P44
P45
P46
P50
P51
P52
P53
P54
P55
P56
DSP0
PWM
AN IN
AN VDD
AN GND
VREF+
Input
Output
I/O
(Bit
I/O
(Bit
282
Z89135 Functional Block Diagram
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