ZILOG Z87000, Z87L00 Datasheet

1

P

RELIMINARY

P

RODUCT

S

PECIFICATION

FEATURES

ROM

Device

Z87000 12 512 32 84-Pin PLCC

Z87L00 12 512 32 100-Pin QFP

Note: *General-Purpose

■

Transceiver/Controller Chip Optimized for Implement­ation of 900 MHz Spread Spectrum Cordless Phone

– Adaptive Frequency Hopping
– Transmit Power Control
– Error Control Signaling
– Handset Power Management
– Support of 32 kbps ADPCM Speech Coding for

■

DSP Core Acts as Phone Controller
– Zilog-Provided Embedded Transceiver Software to

– User-Modifiable Software Governs Phone

(KWords)

High V oice Quality

Control Transceiver Operation and Base Station­Handset Communications Protocol

Features

RAM*

(Words)

I/O

Lines

Package

Information

100-Pin QFP

Z87000/Z87L00

S

PREAD

■

Transceiver Circuitry Provides Primary Cordless Phone
Communications Functions

– Digital Downconversion with Automatic Frequency

– FSK Demodulator
– FSK Modulator
– Symbol Synchronizer
– Time Division Duplex (TDD) Transmit and Receive

■

On-Chip A/D and D/A to Support 10.7 MHz IF Interface

■

Bus Interface to Z87010 ADPCM Processor

■

Static CMOS for Low Power Consumption

■

3.0V to 3.6V, -20 ° C to +70 ° C, Z87L00

4.5V to 5.5V, -20 ° C to +70 ° C, Z87000

■

16.384 MHz Base Clock

S

PECTRUM

Control (AFC) Loop

Buffers

C

ONTROLLERS

1

GENERAL DESCRIPTION

The Z87000/Z87L00 FHSS Cordless Telephone Trans­ceiver/Controllers are expressly designed to implement a
900 MHz frequency hopping spread spectrum cordless
telephone compliant with United States FCC regulations
for unlicensed operation. The Z87000 and Z87L00 are dis­tinct 5V and 3.3V versions, respectively, of the device. For
the sake of brevity, all subsequent references to the
Z87000 in this document also apply to the Z87L00, unless
specifically noted.

DS96WRL0501

P R E L I M I N A R Y

The Z87000 supports a specific cordless phone system
design that uses frequency hopping and digital modulation
to provide extended range, high voice quality, and low sys­tem costs.The Z87000 uses a Zilog 16-bit fixed-point two’s
complement static CMOS Digital Signal Processor core as
the phone and RF section controller. The Z87000’s DSP
core processor further supports control of the RF section’s
frequency synthesizer for frequency hopping and the gen­eration of the control messages needed to coordinate in­corporation of the phone’s handset and base station.

1-1

Z87000/Z87L00
Spread Spectrum Controllers Zilog

GENERAL DESCRIPTION (Continued)

Additional on-chip transceiver circuitry supports Frequen­cy Shift Keying modulation/demodulation and multiplex­ing/demultiplexing of the 32 kbps voice data and 4 kbps
command data between handset and base station. The
Z87000 provides thirty-two I/O pins, including four wake­up inputs and two CPU interrupt inputs. These program­mable I/O pins allow a variety of user-determined phone
features and board layout configurations. Additionally, the
pins may be used so that phone features and interfaces

CODEC

Z87010
ADPCM
Processor

Telephone
Line
Interface

Z87000
Spread
Spectrum
Controller

RF Section

Base Station

Figure 1. System Block Diagram of a Z87000/Z87010 Based Phone

are supported by an optional microcontroller rather than by
the Z87000’s DSP core.

In combination with an RF section designed according to
the system specifications, Zilog’s Z87010/Z87L10 ADPCM
Processor, a standard 8-bit PCM telephone CODEC and
minimal additional phone circuity, the Z87000 and its em­bedded software provide a total system solution.

CODEC

RF Section

Z87000
Spread
Spectrum
Controller

Z87010
ADPCM
Processor

Handset

1-2

P R E L I M I N A R Y

DS96WRL0501

1

Z87000/Z87L00

Zilog Spread Spectrum Controllers

RX

VREF

TX

RXON

RFRX

RFTX

RFEON

SYLE

RSSI

PWLV

ANT0
ANT1

HBSW

RESETB

TEST

ADC

(1-bit)

DAC

(4-bit)

ADC

(8-bit)

DAC

(4-bit)

FSK Demodulator
(downconverter, limiter discriminator,
AFC, bit sync, frame sync, SNR
detector)

FSK Modulator

256 Word

RAM 0

Frame Counter(s),
Event Trigger ,
T/R Switch Ctrl,
Power On/Off Ctrl,

Antenna Select

Receive
Rate
Buffer

Transmit
Rate
Buffer

256 Word

RAM 1

DSP Core

12K Words
Program ROM

Z87010
Interface

Port 0

Port 1

Analog
Power

Digital
Power

VXDATA[7..0]
VXADD[2..0]
VXSTRB

VXRWB

VXRDYB

CLKOUT
CODCLK

P0[15..0]

P1[15..0]

AVDD

AGND

VDD
GND

Figure 2. Z87000 Functional Block Diagram

DS96WRL0501

P R E L I M I N A R Y

1-3

Z87000/Z87L00
Spread Spectrum Controllers Zilog

PIN DESCRIPTION

TX

AGND

RX
AVDD
VREF

RFEON

P115
GND
P114
P113
P112

VDD

P111

P110

P19

GND

P18
P17
P16

VDD

P15

RSSI

AVDD

33

PWLV

AGND

RFRX

SYLE

RFTX

RXON

VDD

GND

MCLK

/RESETB

112

Z87000

VXADD0

VXADD1

CODCLK

VXADD2

VDD

VXRWB

GND

VXRDYB

VXSTRB

75

54

VXDATA0
VXDATA1
VXDATA2
VDD
VXDATA3
VXDATA4
VXDATA5
VXDATA6
VXDATA7
CLKOUT
HBSW
GND
TEST
VDD
ANT0
ANT1
P00
P01
GND
P02
P03

P11

GND

P10

P015

VDD

P014

P012

P013

P011

P12

P13

P14

Figure 3. 84-Pin PLCC ROM Pin Configuration (Z87000 only)

GND

P010

P09

P07

P08

P06

P05

VDD

P04

1-4

P R E L I M I N A R Y

DS96WRL0501

1

DD

Z87000/Z87L00

–

Zilog Spread Spectrum Controllers

Table 1. 84-Pin PLCC Pin Description Summary

Pin Number Symbol Function Direction

1,19,27,36,46,
56,63,75

2 MCLK Master clock (16.384 MHz) Input
3,23,31,41,51,

61,71,79
4 RFTX RF transmit switch control Output
5 SYLE RF synthesizer load enable Output
6 RXON Demodulator “on” indication Output
7 RFRX RF receive switch control Output
8,13 AGND Analog ground –
9 PWLV RF transmit power level Output
10 RSSI RF receive signals strength indicator Input
11,15 AV

12 TX Analog transmit IF signal Output
14 RX Analog receive IF signal Input
16 V

17 RFEON RF module on/off control Output
18,20,21,22,24,

25,26,28,29,30,
32,33,34,35,37,38

59,60 ANT1 RF diversity antenna control Input/Output
62 TEST Main test mode control Input
64 HBSW Handset/Base Control –
65 CLKOUT Clock output to ADPCM Processor Output
76 VXRDYB ADPCM processor ready signal Output
77 VXSTRB ADPCM processor data strobe Input
78 VXRWB ADPCM read/write control Input
80,81,82 VXADD2 ADPCM processor address bus Input
83 CODCLK Clock output to codec Output
84 /RESETB Reset signal Input

GND Ground –

V

DD

DD

REF

P115 General-purpose Input

Digital –

Analog V

Analog reference voltage for RX signal Output

DS96WRL0501

P R E L I M I N A R Y

1-5

Z87000/Z87L00
Spread Spectrum Controllers Zilog

PIN DESCRIPTION (Continued)

AVDD

N/C
N/C
N/C

TX

AGND

RX

AVDD
VREF

RFEON

P115

GND
P114
P113

N/C

P112

VDD
P111
P110

P19

GND

P18
P17
P16

VDD

P15

N/C

N/C
N/C

P14

RSSI

PWLV

1

31

AGND

RFRX

VDD

SYLE

RFTX

RXON

GND

MCLK

Z87000/Z87L00

N/C

RESETB

CODCLK

VXADD0

VDD

VXADD1

VXADD2

VXRWB

VXSTRB

81

51

VXRDYB

GND
N/C

N/C

N/C
VXDATA0
VXDATA1
VXDATA2
VDD
VXDATA3
VXDATA4
VXDATA5
VXDATA6
VXDATA7
CLKOUT
N/C

HBSW

GND

TEST

VDD

ANT0

ANT1

P00

P01

GND

P02

P03
N/C

N/C

N/C

P04

1-6

P12

P13

P10

P11

GND

Figure 4. 100-Pin QFP Pin Configuration

P014

P015

P R E L I M I N A R Y

VDD

P013

N/C

P012

P011

GND

P010

P08

P09

P06

P07

P05

VDD

DS96WRL0501

1

Zilog Spread Spectrum Controllers

Table 2. 100-Pin QFP Pin Configuration

No Symbol Function Direction

1,8 AV
2,3,4,15,27,28,

29,40,52,53,54,
66,77,78,79,90

5 TX Analog transmit IF signal Output
6,98 AGND Analog ground –
7 RX Analog receive IF signal Input
9 VREF Analog reference voltage for RX signal –
10 RFEON RF module on/off control Output
11,13,14,16,18,

19,20,22,23,23,
26,30,31,32,34,35

17,25,38,49,62,
73,84,93

36,37,39,41,42,
43,45,46,47,48,
50,51,55,56,58,59

60,61 ANT[1..0] RF diversity antenna control Input/Output
63 TEST Main test mode control Input
65 HBSW Handset/bast control Input
67 CLKOUT Clock output to ADPCM processor Output
68,69,70,71,72,

74,75,76
81 VXRDYB ADPCM processor ready signal Output
82 VXSTRB ADPCM processor data strobe Input
83 VXRWB ADPCM processor read/write control Input
85,86,87 VXADD[2..0] ADPCM processor address bus Input
88 CODCLK Clock output to codec Output
89 /RESETB Reset signal Input
92 MCLK Master clock input (16.384 MHz) Input
94 RFTX RF transmit switch control Output
95 SYLE RF synthesizer load enable Output
96 RXON Demodulator “on” indication Output
97 RFRX RF receive switch control Output
99 PWLV RF transmit power level Input
100 RSSI RF receive signal strength indicator Input

DD

N/C No connection –

P1[15..0] General-purpose I/O port 0 Input

V

DD

P0[15..0] General-purpose I/O port 0 Input

VXDATA[7..] ADPCM processor data bus Input

Analog V

Digital –

DD

Z87000/Z87L00

–

DS96WRL0501

P R E L I M I N A R Y

1-7

°

°

Z87000/Z87L00
Spread Spectrum Controllers Zilog

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Min Max Units

V

DD

, AV

DC Supply

DD

-0.5 7.0 V

Voltage(1)

V
V
T

IN
OUT

A

Input V oltage(2) -0.5 V
Output V oltage(3) -0.5 V
Operating

-20 +70

+ 0.5 V

DD

+ 0.5 V

DD

C

Temperature

T

STG

Storage

-65 +150

C

Temperature

Notes:

1. Voltage on all pins with respect to GND.

2. Voltage on all inputs WRT VDD

3. Voltage on all outputs WRT VDD

STANDARD TEST CONDITIONS

The electrical characteristics listed below apply for the fol­lowing standard test conditions, unless otherwise noted.
All voltages are referenced to GND. Positive current flows
into the referenced pins. Standard test conditions are as
follows:

■

■

3.0V < V

4.5V < V

< 3.6V (Z87L00)

DD

< 5.5V (Z87000)

DD

Stresses greater than those listed under Absolute Maxi­mum Ratings may cause permanent damage to the de­vice. This is a stress rating only; operation of the device at
any condition above those indicated in the operational sec­tions of these specifications is not implied. Exposure to ab­solute maximum rating conditions for extended period may
affect device reliability.

IoL

Threshold
Voltage

Output
Under
Test

GND = 0V

■

T

= -20 to +70 ° C

■

A

50pF

IoH

Figure 5. Test Load Diagram

1-8

P R E L I M I N A R Y

DS96WRL0501

1

Z87000/Z87L00

Zilog Spread Spectrum Controllers

RECOMMENDED OPERATING CONDITIONS

Table 3. 5V ± 0.5V Operation (Z87000)

Symbol Parameter Min Max Units

V

, AV

DD

DD

V

IH

V

IL

I

OH

I

OL1

I

OL2

T

A

Notes:

1. Maximum 3 pins total from P0[15..0] and P1[15..0]

Supply V oltage 4.5 5.5 V
Input High Voltage 2.0 V

+ 0.3 V

DD

Input Low Voltage GND -0.3 0.8 V
Output High Current -2.0 mA
Output Low Current 4.0 mA
Output Low Current, Ports (limited usage, 1) 12.0 mA
Operating Temperature -20 +70

Table 4. 3.3V ± 0.3V Operation (Z87L00)

Symbol Parameter Min Max Units

V

DD

V

IH

V

IL

I

OH

I

OL1

I

OL2

T

A

Notes:

1. Maximum 3 pins total from P0[15..0] and P1[15..0]

Supply V oltage 3.0 3.6 V
Input High Voltage 0.7 V

DD

Input Low Voltage GND -0.3 0.1 V

VDD+0.3 V

DD

Output High Current -1.0 mA
Output Low Current 2.0 mA
Output Low Current, Ports (limited usage, 2) 6.0 mA
Operating Temperature -20 +70 °C

°C

V

DS96WRL0501

P R E L I M I N A R Y

1-9

Z87000/Z87L00
Spread Spectrum Controllers Zilog

DC ELECTRICAL CHARACTERISTICS

Conditions for DC characteristics are corresponding oper­ating conditions, and standard test conditions, unless oth­erwise specified.

Table 5. 5V ± 0.5V Operation (Z87000)

Symbol Parameter Test Condition Min Max Units

V

OH

V

OL1

V

OL2

I

L

I

CC

I

CC2

Notes:

1. Maximum 3 pins total from P0[15..0] and P1[15..0]

2. 2.3 mA typical at 25°C, 5 volts.

Output High Voltage VDD min, IOH max 2.4 V
Output Low Voltage VDD min, I
Output Low Voltage, Ports (1) VDD min, I
Input Leakage VIN = 0V, V

max 0.6 V

OL1

max 1.2 V

OL2

DD

-2 2 µA
Supply Current 80 mA
Standby Mode Current (2) 4 mA

Table 6. 3.3V ± 0.3V Operation (Z87L00)

Symbol Parameter Test Condition Min Max Units

V

OH

V

OL1

V

OL2

I

L

I

CC

I

CC2

Notes:

1. Maximum 3 pins total from P0[15..0] and P1[15..0]

2. 1.6 mA typical at 25°C, 3.3 volts.

Output High Voltage VDD min, IOH max 1.6 V
Output Low Voltage VDD min, I
Output Low Voltage, Ports(1) VDD min, I
Input Leakage VIN = 0V, V

max 0.4 V

OL1

max 1.2 V

OL2

DD

-2 2 µA
Supply Current 55 mA
Standby Mode Current(2) 1.4 mA

1-10 P R E L I M I N A R Y DS96WRL0501

Z87000/Z87L00

1

Zilog Spread Spectrum Controllers

ANALOG CHARACTERISTICS

Table 7. 1-Bit ADC (Temperature: -20/+70°C)

Parameter Minimum Typical Maximum Units

Resolution - 1 - bit
Power dissipation 0.54

(70°c)

Power dissipation, Stop mode 0.06

(70°c)

1.0

(40°c)

0.2

(40°c)

2.75

(-20°c)

1.1

(-20°c)

mW

mW

Sample frequency - 8.192 - MHz
Sample window(1) 29 31 33 ns
Bandwidth - 60 - MHz
Supply Range(=AVDD)
Z87L00

Z87000

3.0

4.5

3.6

5.5

V
V

Acquisition time 2 3 8 ns
Settling time 8 10 18 ns
Conversion time 4 6 18 ns
Aperture delay 2 3 8.5 ns
Aperture uncertainty(2) - - 0.5 ns
Input voltage range (p-p) 800 1000 1200 mV
Reference voltage

Z87L00
Z87000

1.7 (AV

2.7 (AV

DD

DD

= 3V)

=4.5V)

1.9 (AV

3.0 (AV

= 3.3V)

DD

DD

= 5V)

2.1 (AV

3.3 (AV

= 3.6V)

DD

= 5.5V)

DD

V
V

Input resistance 10 18 25 KOhm
Input capacitance - 10 - pF

Notes:

Window of time while input signal is applied to sampling capacitor; see next figure.
Uncertainty in sampling time due to random variations such as thermal noise.

DS96WRL0501 P R E L I M I N A R Y 1-11

Z87000/Z87L00
Spread Spectrum Controllers Zilog

ANALOG CHARACTERISTICS (Continued)

CLK (16.384MHz)

Aperture
Delay

SAMPLING
WINDOW

INPUT
SIGNAL

Acquisition
Time

Sampling

Latched
Output

Settling
Time

Conversion

+

Time (for
digital output)

Figure 6. 1-Bit ADC Definition of Terms

Table 8. 8-bit ADC (Temperature -20/+70°C)

Parameter Minimum Typical Maximum Units

Resolution - 6 - bit
Integral non-linearity - 0.5 1 LSB
Differential non-linearity - - 0.5 LSB
Power Dissipation (peak) 35 70 mW
Sample window 5 - 120 ns
Bandwidth - - 2 Msps
Supply Range (=AVDD)
Z87L00

Z87000

3.0

4.5

Input voltage range 0-AV

3.3

5.0

DD

3.6

5.5

V
V

V

Conversion time 0.5 - - µs
Aperture delay 2 3 8.5 ns
Aperture uncertainty - - 1 ns
Input resistance - 25 - Kohm
Input capacitance - 10 - pF

Notes:

1. 8-bit ADC only tested for 6-bit resolution.

1-12 P R E L I M I N A R Y DS96WRL0501

Z87000/Z87L00

1

Zilog Spread Spectrum Controllers

Table 9. 4-bit DAC (Temperature: -20/+70°C)

Parameter Minimum Typical Maximum Units

Resolution - 4 - bit
Integral non-linearity - 0.25 0.5 LSB
Differential non-linearity - 0.25 1 LSB
Settling time (1/2 LSB) - - 22.5 ns
Zero error at 25°C-12mV
Conversion time (input change to output change) 14 19 76 ns
Power dissipation, 25 pF load 1.2

(70°c)

Power dissipation, 25 pF load, Stop mode 0.18

(70°c)
Conversion time (input change to output change) 14.5 19.1 75.8 ns
Rise time (full swing) 11 15 71 ns
Output slew rate 8 67 96 V/µs
Output voltage range - 0.2 AV

Supply Range (=AV
Z87L00

Z87000
Output load resistance 330 Ohm
Output load capacitance - 25 - pF

DD

)

3.0

4.5

20

(40°c)

1.0

(40°c)

to 0.6A V

DD

3.3

5.0

DD

24.1

(-20°c)

1.1

(-20°c)

-V

3.6

5.5

mW

mW

V
V

DS96WRL0501 P R E L I M I N A R Y 1-13

Z87000/Z87L00
Spread Spectrum Controllers Zilog

INPUT/OUTPUT PIN CHARACTERISTICS

All digital pins (all pins except VDD, AVDD, GND, AGND,
V

, RX, TX, RSSI and PWLV) have an internal capaci-

REF

tance of 5 pF.

The RX analog input pin has an input capacitance of 10
pF.

The RSSI analog input pin has an input capacitance of 10
pF.

AC ELECTRICAL CHARACTERISTICS
Clocks, Reset and RF Interface

Table 10. Clocks, Reset and RF Interface

No. Symbol Parameter Min Max Units

1 TpC MCLK input clock period (1) 61 61 ns
2 TwC MCLK input clock pulse width 20 40 ns
3 TrC, TfC MCLK input clock rise/fall time 15 ns
4 TrCC, TfCC CLKOUT output clock rise/fall time 2 6 ns
5 TrCO, TfCO CODCLK output clock rise/fall time 2 6 ns
6 TwR RESETB input low width 18 TpC
7 TrRF, TfRF RF output controls rise/fall time (2) 2 6 ns

Notes:

1. MCLK is 16.384 MHz ± 25 ppm

2. RF Controls are RFTX, RFRX, RXON, RFEON, SYLE.

1-14 P R E L I M I N A R Y DS96WRL0501

Z87000/Z87L00

1

Zilog Spread Spectrum Controllers

ADPCM Processor Interface

The Z87000 is a peripheral device for the ADPCM Proces­sor. The interface from the Z87000 perspective is com­posed of an input address bus, a bidirectional data bus,
strobe and read/write input control signals and a
ready/wait output control signal.

Table 11. Read Cycles

Signal Name Function Direction

VXADD[2..0] Address Bus ADPCM Proc. to Z87000

VXDATA[7..0] Data Bus Bidirectional

VXSTRB Strobe Control Signal ADPCM Proc. to Z87000

VXRWB Read/Write Control Signal ADPCM Proc. to Z87000

VXRDYB Ready Control Signal Z87000 to ADPCM Proc.

Table 12. Write Cycles

No. Symbol Parameter Min Max Units

8 TsAS Address, Read/Write setup time before Strobe falls 10 ns

9 ThSA Address, Read/Write hold time after Strobe rises 3 ns
10 TaDrS Data read access time after Strobe falls 30 (1) ns
11 ThDrS Data read hold time after Strobe rises 8.5 40 (2) ns
12 TwS Strobe pulse width 20
13 TsDwS Data write setup time before Strobe rises 10 ns
14 ThDwS Data write hold time after Strobe rises 3 ns
15 TaDrRY Data read valid before Ready falls 22 ns
16 TdSRY Strobe high after Ready falls 0 ns

Notes:

1. Requires wait state on ADPCM Processor read cycles

2. Requires no write cycle directly following read cycle on ADPCM Processor

READ CYCLES refer to data transfers from the Z87000 to
the ADPCM Processor.

WRITE CYCLES refer to data transfers from the ADPCM
Processor to the Z87000.

DS96WRL0501 P R E L I M I N A R Y 1-15