ZILOG Z86C27, Z86C97 Datasheet

C

USTOMER PRODUCT SPECIFICATION

Z86C27-ROM

Z86C27/C97

CPS DC-2974-04

GENERAL DESCRIPTION

The Z86C27 and Z86C97 Digital Television Controller
(DTC) introduce a new level of sophistication to single-chip
architecture. The Z86C27/C97 are members of the Z8
single-chip microcontroller family with 8 Kbytes of ROM
(Z86C27), ROMless (Z86C97) and 236 bytes of RAM. Both
devices are housed in a 64-pin DIP package, and are
CMOS compatible. Having the ROM/ROMless selectivity,
the DTC offers both external memory and pre-programmed
ROM which enables the Z8 microcontroller to be used in a
high volume production application device embedded
with a custom program (customer supplied program). The
Z86C97 ROMless offers the use of external memory rather
than a preprogrammed ROM. This enables the Z8
microcontroller to be used in prototyping, low volume
applications or where code flexibility is required. Zilog’s
DTC offers fast execution, efficient use of memory, sophis­ticated interrupts, input/output bit manipulation capabili­ties, and easy hardware/software system expansion along
with low cost and low power consumption. The device
provides an ideal performance and reliability solution for
consumer and industrial television applications.

The Z86C27/C97 architecture is characterized by utilizing
Zilog’s advanced Superintegration™ design methodol­ogy. The devices have an 8-bit internal data path con­trolled by a Z8 microcontroller, and On Screen Display
(OSD) logic circuits/Pulse Width Modulators (PWM). On­chip peripherals include two register mapped I/O ports
(Ports 2 and Port 3), Interrupt control logic (1 software, 2
external and 3 internal interrupts) and a standby mode
recovery input port (Port 3, pin P30).

The OSD control circuits support 8 rows by 20 columns for
128 kinds of characters. The character color is specified

Z86C97-ROM

CMOS Z8

®

8-BIT

LESS

MICROCONTROLLER

by row. One of the 8 rows is assigned to show two kinds of
colors for bar type displays such as volume control. The
OSD is capable of displaying either low resolution (5x7 dot
pattern) or high resolution (11x15 dot pattern) characters.
The Z86C97 currently supports high resolution char­acters only.

A 14-bit PWM port provides enough voltage resolution for
a voltage synthesizer tuning system. Seven 6-bit PWM
ports are used for controlling audio signal level. Five 8-bit
PWM ports are used to vary picture levels.

The DTC applications demand powerful I/O capabilities.
The Z86C27/C97 fulfills this with 35 I/O pins dedicated to
input and output. These lines are grouped into five ports,
and are configurable under software control to provide
timing, status signals, parallel I/O and an address/data
bus for interfacing to external memory.

There are three basic address spaces available to support
this wide range of configurations: Program Memory, Reg­ister File and Data Memory. The Register File is composed
of 236 bytes of general purpose register, two I/O Port
registers and 15 control and status registers.

To unburden the program from coping with the real-time
problems such as counting/timing and data communica­tion, the DTC’s offer two on-chip counter/timers with a large
number of user selectable modes (see block diagram).

Note: All Signals with a preceding front slash, "/", are active
Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is
active Low, only).

DC-2974-04 (6-10-93)

1

GENERAL DESCRIPTION (Continued)

Z86C27/C97

CPS DC-2974-04

/RESET

P40( P10 )
P41( P11 )
P42( P12 )
P43( P13 )
P44( P14 )
P45( P15 )
P46( P16 )
P47( P17 )
P50( P00 )
P51( P01 )
P52( P02 )
P53( P03 )
P54( P04 )
P55( P05 )
P56( P06 )
P57( P07 )
P60( /AS )
P61( /DS )

P62( R//W )

P63( SCLK )

P64( P66 )*
P65( P67 )*

AFCIN

XTAL1
XTAL2

P30
P31
P34
P35
P36

RESET

Oscillator

WDT

Counter

Timer

Counter

Timer

Port 3/

Interrupt

Port4

(Port 1)

Port 5

(Port 0)

Port 6

(Control)

8K Byte

Program ROM

Z8 CPU

256 Byte

Register File

Port 0

A8:15

160 Byte

Character RAM

4 KByte

Character ROM

Core

Port 1

AD0:7

Port 2

PWM 1

14 -bit

PWM 2

to

PWM 8

6-bit

PWM 9

to

PWM 13

8-bit

On Screen

Display

P27
P26
P25
P24
P23
P22
P21
P20

PWM 1

PWM 2
PWM 3
PWM 4
PWM 5
PWM 6
PWM 7
PWM 8
PWM 9
PWM 10
PWM 11
PWM 12
PWM 13

OSCIN
OSCOUT
HSYNC
VSYNC
VRED
VGREEN
VBLUE
VBLANK

* ( ) Denotes Z86C97 signal differences.

Functional Block Diagram

2

T

T

PIN CONFIGURATION

Z86C27/C97

CPS DC-2974-04

PWM5
PWM4
PWM3
PWM2
PWM1

P35
P36
P34
P31

P30
XTAL1
XTAL2

/RESE

P60

GND

P61

P62

VCC

P63

P64

P65

AFCIN

P50

P51

P52

P53

P54

P55

P56

P57

OSCIN

OSCOUT

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

Z86C27

64
63
62
61
60
59
58

57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

PWM6
PWM7
PWM8
PWM9
PWM10
PWM11
PWM12
PWM13
P27
P26
P25
P24
P23

GND
P22
P21

VCC
P20
P47
P46
P45
P44
P43
P42
P41
P40
VBLANK
VBLUE
VGREEN
VRED
VSYNC
HSYNC

PWM5
PWM4
PWM3
PWM2
PWM1

P35
P36
P34
P31

P30
XTAL1
XTAL2

/RESE

/AS

GND

/DS

R//W

VCC

SCLK

P66

P67

AFCIN

P00

P01

P02

P03

P04

P05

P06

P07

OSCIN

OSCOUT

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

Z86C97

64
63
62
61
60
59
58

57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

PWM6
PWM7
PWM8
PWM9
PWM10
PWM11
PWM12
PWM13
P27
P26
P25
P24
P23

GND

P22
P21

VCC

P20
P17
P16
P15
P14
P13
P12
P11
P10
VBLANK
VBLUE
VGREEN
VRED
VSYNC
HSYNC

Z86C27 Mask-ROM Plastic DIP Z86C97 ROMless Plastic DIP

3

ABSOLUTE MAXIMUM RATINGS

Z86C27/C97

CPS DC-2974-04

Stress greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This
is a stress rating only; operation of the device at any

tions of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods
may affect device reliability.

condition above those indicated in the operational sec-

Symbol Parameters Min Max Units Notes

V

CC

V

I

V

I

V

O

I

OH

I

OH

I

OL

I

OL

I

OL

T

A

T

STG

Notes:

[1] Port 2 open-drain
[2] PWM open-drain outputs
[3] Port 5

Power Supply Voltage † –0.3 +7 V
Input Voltage –0.3 V
Input Voltage –0.3 V
Output Voltage –0.3 V

+0.3 V

CC

+0.3 V [1]

CC

+8.0 V [2]

CC

Output Current High –10 mA 1 pin

Output Current High –100 mA all total
Output Current Low 20 mA 1 pin
Output Current Low 40 mA [3] (1 pin)
Output Current Low,all total 200 mA
Operating Temperature ††
Storage Temperature –65 +150 C

† Voltage on all pins with respect to GND.
†† See Ordering Information

STANDARD TEST CONDITIONS

The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to GND.
Positive current flows into the referenced pin (see Test
Load Diagram).

CAPACITANCE

T

=25°C, V

A

Parameter Max Units

Input capacitance 10 pF
Output capacitance 20 pF
I/O capacitance 25 pF
AFCIN input capacitance 10 pF

=GND=0 V, Freq=1.0 MHz, unmeasured pins to GND.

CC

From Output
Under Test

150 pF

Test Load Diagram

VDD

RLL

RLH

4

DC CHARACTERISTICS

T

=0°C to +70°C; V

A

Symbol Parameter Min Max @ 25°C Units Conditions

=+4.5 V to +5.5 V; F

CC

TA=0°C to +70°C Typical

=4 MHz

OSC

Z86C27/C97

CPS DC-2974-04

V

IL

V

ILC

V

IH

V

IHC

V

HY

V

PU

V

OL

V

00-01

V

01-11

V

OH

I

IR

I

IL

I

OL

I

CC

I

CC1

I

CC2

Notes:

[1] Port 5
[2] PWM Open-Drain

Input Voltage Low 0 0.2 V
Input XTAL/Osc In Low 0.07 V
Input Voltage 0.7 V
Input XTAL/Osc in High 0.8 V

Schmitt Hysteresis 0.1 V
Maximum Pull-up Voltage 12 V [2]
Output Voltage Low 0.4 0.16 V IOL=1.00 mA

AFC Level 01 In 0.45 V
AFC Level 11 In 0.5 V

Output Voltage High VCC–0.4 4.75 V IOH= –0.75 mA
Reset Input Current –80 –46 µAVRL=0 V
Input Leakage –3.0 3.0 0.01 µA 0 V,V
Tri-State Leakage –3.0 3.0 0.02 µA 0 V,V

Supply Current 20 13.2 mA All inputs at rail

CC

CC

CC

CC

1.48 V

CC

0.98 V External Clock Generator Driven

CC

V

CC

V

CC

3.0 V

3.2 V External Clock Generator Driven

0.8 V

0.4 0.19 V IOL=3.2 mA, [1]

0.4 0.19 V IOL=0.75 mA [2]

1.5 1.00 V IOL=10 mA [1]

1.9 V

CC

0.75 V

CC

3.12 V

CC

CC

6 3.2 mA All inputs at rail

10 0 µA All inputs at rail

AC CHARACTERISTICS

Timing Diagrams

1

XTAL1

External Clock

3

7 5

Tin

3

2

2

4

6

Counter Timer

5

Vcc

Z86C27/C97

CPS DC-2974-04

IRQn

8 9

Interrupt Request

Internal /RESET

External /RESET

HSYNC

OSC2

10

Power On Reset

11

12

1413

On Screen Display

6

Z86C27/C97

CPS DC-2974-04

AC CHARACTERISTICS

T

=0° C to +70° C; V

A

No Symbol Parameter Min Max Unit

1 TpC Input clock period 250 1000 ns
2 TrC,TfC Clock input raise and fall 15 ns
3 TwC Input clock width 125 ns
4 TwTinL Timer input low width 70 ns

5 TwTinH Timer input high width 3 TpC
6 TpTin Timer input period 8 TpC
7 TrTin,TfTin Timer input raise and fall 100 ns
8A TwIL Int req input low 70 ns

8B TwIL 3 TpC
9 TwIH Int request input high 3 TpC
10 TdPOR Power On Reset delay 25 100 ms
11 TdLVIRES Low voltage detect to In- 200 ns

12 TwRES Reset minimum width 5 TpC
13 TdHsOI Hsync start to Vosc stop 2 TpV 3 TpV
14 TdHsOh Hsync end to Vosc start 1 TpV
15 TdWDT WDT Refresh Time 12 ms

=+4.5 V to +5.5 V; F

CC

Internal RESET condition

=4 MHz,

OSC

Notes:

[1] Refer to DC Characteristics for details on switching levels.

* Units in nanoseconds

7

AC CHARACTERISTICS

Unique to Z86C97 External Memory Read/Write Timing Diagram

R//W

Z86C27/C97

CPS DC-2974-04

Port 0, /DM

Port 1

/AS

/DS

(Read)

Port1

12

16

19

3

13

A7 - A0 D7 - D0 IN

21

8 18 11

4

5

17

6

9

10

D7 - D0 OUTA7 - A0

/DS

(Write)

14

7

Z86C97 External Memory Read/Write Timing

15

8

Z86C27/C97

CPS DC-2974-04

AC CHARACTERISTICS

Unique to Z86C97, T

No Symbol Parameter Min Max Unit Notes

1 TdA(AS) Address Valid to /AS High Delay 35 ns [2]
2 TdAS(AS) /AS High to Address Float Delay 45 ns [2]
3 TdAS(DR) /AS High to Read Data Required Valid 250 ns [1,2]
4 TwAS /AS Low Width 55 ns [2]

5 TdAZ(DS) Address Float to /DS Low 0 ns [2]
6 TwDSR /DS (Read) Low Width 185 ns [1,2]
7 TwDSW DS (Write) Low Width 110 ns [1,2]
8 TdDSR(DR) /DS Low to Read Data Required Valid 130 ns [1,2]

9 ThDR(DS) Read Data to /DS High Hold 5 ns
10 TdDS(A) /DS High to Address Active Delay 55 ns [2]
11 TdDS(AS) /DS High to /AS Low Delay 55 ns [2]
12 TdR/W(AS) R//W Valid to /AS High Delay 35 ns [2]

13 TdDS(R/W) /DS High to R//W Not Valid 55 ns [2]
14 TdDW(DSW) Write Data Valid to /DS Low Delay 35 ns [2]
15 TdDS(DW) /DS High to Write Data Not Valid 55 ns [2]

=0°C to +70°C; V

A

=+4.5 V to +5.5 V; F

CC

= 4 MHz

OSC

16 TdA(DR) Address Valid to Read Data Required Valid 330 ns [1,2]
17 TdAS(DS) /AS High to /DS Low Delay 65 ns [2]
18 TdDI(DS) Data Input Setup to /DS High 75 ns [1]

Notes:

[1] When using extended memory timing, for parameters 3, 6, 7, 8, and 16, add 2 TpC (250 ns @ 4.0 MHz).
[2] Min and Max times are in nanoseconds unless otherwise noted.

© 1993 by Zilog, Inc. All rights reserved. No part of this document
may be copied or reproduced in any form or by any means
without the prior written consent of Zilog, Inc. The information in
this document is subject to change without notice. Devices sold
by Zilog, Inc. are covered by warranty and patent indemnification
provisions appearing in Zilog, Inc. Terms and Conditions of Sale
only. Zilog, Inc. makes no warranty, express, statutory, implied or
by description, regarding the information set forth herein or
regarding the freedom of the described devices from intellectual
property infringement. Zilog, Inc. makes no warranty of mer­chantability or fitness for any purpose. Zilog, Inc. shall not be
responsible for any errors that may appear in this document.
Zilog, Inc. makes no commitment to update or keep current the
information contained in this document.

Zilog's products are not authorized for use as critical compo­nents in life support devices or systems unless a specific written
agreement pertaining to such intended use is executed between
the customer and Zilog prior to use. Life support devices or
systems are those which are intended for surgical implantation
into the body, or which sustains life whose failure to perform,
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result in
significant injury to the user.

Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone [phone]
Telex 910-338-7621
FAX [phone]

9