ZILOG Z86228 Datasheet

GENERAL DESCRIPTION

PRELIMINARY

P

RELIMINARY

C

USTOMER PROCUREMENT SPECIFICATION

Z86228

LINE 21 CLOSED CAPTION
CONTROLLER (L21C)

CPS DC-4243-00

Z86228

The Z86228 (Line 21 Closed-Caption Controller) is a single
I.C. designed to provide the functional performance of a
L21C Decoder module. This Superintegration™ VLSI device
is completely self contained requiring only composite
video, a horizontal timing signal as input and an external
keyer (i.e., video switch between TV video and Closed­Caption video) to produce captioned video. The Z86228
uses a wired logic approach to perform the functions
selected through its input control signals. It is fabricated
using standard CMOS technology and designed to achieve
the lowest possible cost.

The Z86228 is intended for use in a set-top decoder or in
any television receiver conforming to the NTSC standard.
It is capable of processing and displaying all standard
L21C format transmissions including the codes specified

by the FCC "Report and Order" on GEN Docket No. 91-1,
dated April 12, 1991. In addition, the device conforms to
the Electronic Industry Association's Recomended Practice
608, which provides supplemental guidelines for the
transmission of captions, text, and Extended Data Services
(EDS) on NTSC Field 2. Extended Data Services (EDS)
packets encoded on Field 2 , may be displayed in either of
two screen formats. If and when PAL and SECAM TV
standards define a protocol using the Line 21 format, this
design will be readily convertible to that standard.

The Line 21 Closed Captioning System

The L21C system provides for the transmission of CAPTION
information and other TEXT material as an encoded
composite data signal. This is during the unblanked portion
of Line 21, field 1, of the standard NTSC video signal. The
video signal conforms to the Standard Synchronizing
Waveform for Color Transmission given in Sub-part E, Part
73 of the FCC Rules and Regulations.

DC-4243-00 (2-18-94)

1

PIN DESCRIPTION

PRELIMINARY

CPS DC-4243-00

Z86228

DONF/SEN

NRESET

VSS (Digital)

Pin No. Signal Description

11 Composite Video Input (CVI)

Composite NTSC video, nominally 1.0V p-p,.
band limited to 600 kHz. Circuit operates with
signal variations between 0.7-1.4V p-p. It is
recommended that this signal pin be driven by
an emitter follower through a 0.1 µF capacitor.

12 Sync Slice Level (SSL)

Capacitor (0.1µF) to store sync slice level
voltage.

8 H Flyback Input (HFI)

Horizontal sync input at CMOS levels, polarity
independent. Typically derived from the H
Flyback pulse or any other horizontal timing
signal.

13 H Loop Filter (HLF)

Value to be specified

18
17
16
15
14
13
12
11
10

LNG/SCK
CT/SDA
NSIN

VDD (Digital)
VDD (Analog)
HLF
SSL
CVI
VSS (Analog)

BOX
LUM

HFI

1
2
3
4

R

5

G

6

B

7
8
9

18-Pin DIP Package Diagram

Pin No. Signal Description

2 NRESET

Master reset for the I.C. and must be used in the
Parallel Control Mode. It may be tied High in the
Serial Mode if reset is to be performed through
the serial data stream.

18 LAG/SCK Input (control)

In Parallel Mode this input selects the Data
Channel to be processed (along with CT). CMOS
input High=LANGUAGE I, Low=LANGUAGE II.
In Serial Mode this input is Serial Clock In.

3 Box Output (Box)

Active High, CMOS level “black box” keying
signal for Caption/Text display area.

4 Luminance Output (LUM)

Active High, CMOS level signal.
Character video luminance signal.

9V

(Digital) Digital Ground

SS

Connect to system ground

1 DONF/SEN Input (control)

In Parallel Mode this input controls the Decoder
On/Off function CMOS input with High = On,
Low = Off. In Serial Mode this input is the Enable
for serial data input.

17 CT/SDA Input (control)

In Parallel Mode this input selects the Data
Channel to be processed (along with LNG).
CMOS input with High=CAPTIONS, Low =TEXT.
In Serial mode this input is serial data input.

2

5, 6, 7 Color signals, RGB Outputs

Active High, CMOS level color character video
for color receiver use.

15 V
14 V
10 V

Digital Power pin. Connect to +5V source.

DD

Analog

DD

Analog. Analog Ground. Connect to

SS

system ground.

16 (NSIN) Input (Control)

Selects the mode to be used in interpreting the
signals on the three Control pins. High = Parallel
Mode, Low = Serial Mode.

Horizontal Timing

PRELIMINARY

CPS DC-4243-00

Z86228

The timing of the output signals; Box, Luminance, and RGB
is set so that the start of the leading box preceding the first
displayable character cell will occur at 13.6*µs. (*Value
may be altered by a Mask change - consult factory.) This
is after the midpoint of the leading edge of the horizontal
sync pulse of the composite video signal measured at pin
11 of the Z86228. It is assumed that the delay through the
low pass filter will be 220 ns (refererence Figure).

There are two ways to execute a FULL RESET of the
Z86228:

1. Hold NRESET Low for 100 ns. This stops all internal

circuits. The part is static and the 100 ns is the worst
case time for the NRESET signal to propagate through
the various gates.

ABSOLUTE MAXIMUM RATINGS

Sym Description Min Max Units

V

cc

T

STG

T

A

Notes:

* Voltages on all pins with respect to GND.

Supply Voltage* –0.3 +7.0 V
Storage Temp –65°C +150° C
Oper Ambient Temp 0° 70° C

2. Send NRESET command through the serial interface.

The result is the same as in number 1.

FULL RESET is useful during power-up. A FULL RESET of
the part during normal operation is not necessary.

A partial reset may also be executed through the serial
interface only. This is the COMMAND PROCESSOR RESET.
Basically, all internal timing circuits continue to operate,
but the caption display is removed from the screen and the
Z86228 waits for new line 21 data. This is useful for
situations such as channel change.

Stress greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This
is a stress rating only; operation of the device at any
condition above those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for an extended period may
affect device reliability.

STANDARD TEST CONDITIONS

The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to GND.
Positive current flows into the referenced pin in Standard
Test Load.

From Output

Under Test

+5V

2.1 kΩ

150 pF

▼ 250 µA

Standard Test Load

3