ZILOG Z8613112PSC, Z8613112SSC, Z8612912PSC, Z8612912SSC, Z8613012PSC Datasheet

1

P

RELIMINARY

P

RODUCT

S

PECIFICATION

Z86129/130/131

NTSC L

INE

21 D

ECODER

1

FEATURES

Speed Pin Count/ Standard On-Screen Display Automatic Data Extraction

Devices (MHz) Package Types Temp. Range & Closed Captioning V-Chip Time of Day

Z86129 12 18-Pin DIP, SOIC 0 ° to +70 ° C Yes Yes Yes
Z86130 12 18-Pin DIP, SOIC 0 ° to +70 ° C No Yes Yes
Z86131 12 18-Pin DIP, SOIC 0 ° to +70 ° CNo NoYes

■

Complete Stand-Alone Line 21 Decoder for Closed­Captions and Extended Data Services (XDS).

■

Preprogrammed to Provide Full Compliance with EIA­608 Specifications for Extended Data Services.

■

Automatic Extraction and Serial Output of Special
XDS Packets such as Time of Day, Local Time Zone,
and Program Rating ( V-Chip ).

■

Cost-Effective Solution for NTSC Violence Blocking
inside Picture-in-Picture (PiP) Windows.

■

Minimal Communications and Control Overhead
Provides Simple Implementation of Violence Block,
Closed Caption, and Auto Clock Set Features.

■

Programmable, Full Screen On-Screen Display (OSD)
for Creating OSD or Captions inside a Picture-in­Picture (PiP) Window (Z86129 only).

2

■

I

C Serial Data and Control Communication

■

User-Programmable Horizontal Display Position for
easy OSD Centering and Adjustment (Z86129 only).

GENERAL DESCRIPTION

The Z86129/130/131 is a stand-alone integrated circuit,
capable of processing Vertical Blanking Interval (VBI) data
from both fields of the video frame in data conforming to
the transmission format defined in the Television Decoder
Circuits Act of 1990 and in accordance with the Electronics
Industry Association specification 608 (EIA-608).

The Line 21 data stream can consist of data from several
data channels multiplexed together. Field 1 has four data
channels, two Captions and two Text. Field 2 has five
additional data channels, two Captions, two Text and
Extended Data Services (XDS). XDS data structure is
defined in EIA-608. The Z86129 can recover and display
data transmitted on any of these nine data channels. The
Z86130 and Z86131 are derivatives of the Z86129 which
can recover XDS data and output the recovered data via
the serial port. The Z86130 and Z86131 do not have OSD

DS96TEL0200 1

capability, but are ideally suited for Line 21 data slicer
applications.

The Z86129/130/131 can recover and output to a host
processor via the I
defined in EIA-608. On-chip XDS filters are fully
programmable, enabling recovery of only those XDS data
packets selected by the user, making the Z86129/130 an
ideal choice for implementing NTSC Violence Block. The
Z86131 is designed especially for extracting XDS time
information for Automatic Clock-Set features in TVs,
VCRs, and Set-Top boxes.

In addition, the Z86129/130 is ideally suited to monitor Line
21 of video displayed in a PiP window for violence blocking
purposes. A block diagram of the Z86129/130/131 is
shown in Figure 1.

2

C serial bus any XDS data packet

Z86129/130/131
NTSC Line 21 Decoder P R E L I M I N A R Y

GENERAL DESCRIPTION (Continued)

+5V

6 4 15 14 1613

VDD

12

SDO
SDA

SCK

Serial

SEN

SMS

Intro

VIN/

Data Line

Data CLK

Data

Sliced

Data

Buffer

Addr Bus

Row

Status Reg

Control Port

VW

Data Bus

FEW

Recovery

AW

Slicer

SIG

Lock

Command

Test Reg

II Lock

Digital

PG

Processor

4

Row

Slicer

SYNC

Address

10

Latch

MUX

6

DOT CLK

RAM

Display

DIV

DOT CLK

V Lock

COMP SYNC

DEC

ADDR

Character

13

8

Latch

Display

FLD

CIR

CHAR

CW

CHAR CLK

OSCO/S

ADDR

Decoder

Generator

4

SS CTR

MSGR

Logic

Output

Line &

LS

FLD

Control

I Drive

& MUX

Field

Control

SLS

SFLD

CKT

POR

V/I

Ref

Line & Fld

RED
GREEN
BLUE
BOX

10

Decodes

11

1

9

17 3 2 18

Z86129 only

RREF

Vss(A)

Vss

Loop

LPF

Filter

FR

HIN

5

7

Video

Dual

Clamp

Slice Level

8

CSYNC

CG Lines

CG

Logic

MSYNC

PH1

PH2

Figure 1. Z86129 Block Diagram

2 DS96TEL0200

1

PIN DESCRIPTION

V

GREEN*

BLUE*

SEN

SMS

VIDEO

CSYNC

SS

HIN

LPF

*Z86129 Only

1
2
3
4
5
6
7
8
9

Figure 2. Z86129/130/131, 18-Pin DIP/SOIC

Pin Configuration

18
17

16
15
14
13
12
11
10

RED*
BOX*
SDO
SCK
SDA
VIN/INTRO

V

DD

VSS(A)
RREF

°

°

Z86129/130/131

P R E L I M I N A R Y NTSC Line 21 Decoder

Table 1. 18-Pin DIP and SOIC Pin Identification

No. Symbol Function Direction

1V

SS

Power Supply GND

2* GREEN Video Output Output
3* BLUE Video Output Output

4 SEN Serial Enable Input
5 HIN Horizontal In Input
6 SMS Serial Mode Select Input
7 VIDEO Composite Video Input
8 CSYNC Composite Sync Output

9 LPF Loop Filter Output
10 RREF Resistor Reference Input
11 V

12 V

(A) Pwr. Supply (Analog) GND

SS
DD

Power Supply

13 VIN/INTRO Vertical In/Interrupt Out In/Output
14 SDA Serial Data In/Output
15 SCK Serial Clock Input
16 SDO Serial Data Out Output

17* BOX OSD Timing Signal Output
18* RED Video Output Output

Note: DIP and SOIC pin configuration are identical. *However,

the Z86130/Z86131 do not have signals on pins 2, 3, 18 and 19.

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

DD

V

IN

V

OUT

I

IN

I

OUT

I

DD

P

D

T

STG

T

L

Notes:

Voltages referenced to V
Maximum ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the limits specified in the DC and AC Characteristics tables or Pin Description section.

DC Supply Voltage –0.5 to 6.0 V
DC Input Voltage –0.5 to V
DC Output Voltage –0.5 to V

+0.5 V

DD

+0.5 V

DD

CAUTION: DC Input Current per Pin +10 mA

DC Output Current per Pin +20 mA
DC Supply Current +30 mA
Power Dissipation per Device 300 mW
Storage Temperature –65 to +150
Lead Temperature, 1 mm from Case for 10 seconds 260

(A) and V

SS

SS

.

C
C

DS96TEL0200 3

Z86129/130/131
NTSC Line 21 Decoder P R E L I M I N A R Y

STANDARD TEST CONDITIONS

µ

The characteristics listed below apply for standard test

+5V

conditions as noted. All voltages are referenced to
Ground. Positive current flows into the referenced pin
(Figure 3).

From Output
Under Test

150 pF

250 µA

2.1 kΩ

Figure 3. Standard Test Load

DC ELECTRICAL CHARACTERISTICS

Note: T

Symbol Parameter Conditions Min. Max. Unit

Note: *Not guaranteed

= 0 ° C to +70 ° C; V

A

V

IL

V

IH

V

OL

V

OH

I

IL

I

DD

K φ
I

LP

= +4.75V to +5.25V

DD

Input V oltage Low 0 0.2 V
Input V oltage High 0.7 V
Output V oltage Low I
Output V oltage High I
Input Leakage 0V, V

= 1.00 mA – 0.4 V

OL

= 0.75 mA V

OH

DD

–0.4V – V

DD

–3.0 3.0

DD

V

DD

DD

V
V

Supply Current Estimated* 30 mA

VCO Gain – TBD MHz/V

Loop Filter Current – TBD mA

A

AC AND TIMING CHARACTERISTICS
Composite Video Input

Parameter Conditions

Amplitude 1.0V p-p ± 3 dB
Polarity Sync tips negative
Bandwidth 600 kHz
Signal Type Interlaced
Max Input R 470 ohms
DC Offset Signal to be AC coupled with a minimum series capacitance of 0.1 µ F

4 DS96TEL0200

P R E L I M I N A R Y NTSC Line 21 Decoder

1

ELECTRICAL CHARACTERISTICS
Non Standard Video Signals must have the following characteristics:

Z86129/130/131

Parameter Conditions

Sync Amplitude 200 mV minimum
Vertical Pulse Width 3H ± 0.5H
Vertical Pulse Tilt 20 mV maximum
H Timing Phase Step (Head Switch) ± 10 µ s maximum

Fh Deviation (long term) ± 0.5% maximum
Fh p-p Deviation (short term) ± 0.3% maximum

Vertical Sync Signal The internal sync circuits will lock to all 525 or 625 line signals having a vertical

sync pulse that meets the following conditions:

1. It is at least 2H wide.

2. It starts at the proper 2H boundary for its field.

3. If equalizing pulse serrations are present, they must be less than 0.125H in
width.

Minimum Signal-to-Noise The Z86129/130/131 will function down to a 25 dB signal-to-noise ratio (CCIR

weighted) with one error per row or better at that level.

Ratio to Composite Video Input

Horizontal Signal Input (preferably H Flyback)

Parameter Conditions

Amplitude CMOS level signal where Low <= 0.2 V
Video Lock Mode: Polarity

Frequency

HIN Lock Mode: Polarity

Frequency

Any
15,734.263 Hz ± 3%

Any
Same as Display Horizontal Flyback Pulse (HFB) pulse

CC

Line 21 Input Parameters (at 1.0V p-p)

Note: Line 21 must be in its proper position to the leading edge of the Vertical Sync signal.

Parameter Conditions

Cod Amplitude 50 IRE
Code Zero Level 5 IRE, +15 IRE relative to Back Porch
Start of Code 10.5 ±0.5 µs, (Measured from the midpoint of the falling edge of the last cloc k run-in cycle

to the midpoint of the rising edge of the start bit.)

Start of Data 3.972 µs, –0.00 µsec, +0.30 µs (Measured from the midpoint of the falling edge of the last

clock run-in cycle to the midpoint of the rising edge of the start bit.

Timing Signals

Parameter Conditions

Dot 768 x FH = 12.0839 MHz
Dot Period 82.75 ns
Character Cell Width 1.324 µs (tH/48)
Width of Row (Box) 45.018 µs (34 chars = 17/24 x tH
Width of Row (Char) 42.370 µs (32 chars = 2/3 x tH
Horizontal Display Timing The timing of the output signals Box and RGB have been set to make a centered display.

The positioning of these outputs can be adjusted in 330 ns increments by writing a new
value to the Z86129 H Position Register (Address = 02h).

DS96TEL0200 5

Z86129/130/131
NTSC Line 21 Decoder P R E L I M I N A R Y

PIN DESCRIPTIONS
Inputs

VIDEO (Pin 7). Composite NTSC video input, 1.0V p-p

(nom), band limited to 600 kHz. Circuit will operate with
signal variation between 0.7-1.4V p-p. The polarity is sync
tips negative. This signal pin should be AC coupled
through a 0.1 µF capacitor and driven by a source
impedance of 470 ohms or less.

HIN (Pin 5). Horizontal sync input at CMOS levels. When
the device is used in the VIDEO LOCK mode, this signal
pulls the on-chip VCO within the proper range. The circuit
uses the frequency of this signal which must be within ±3%
Fh but can be of either polarity. When used in the H LOCK
mode, the VCO phase locks to the rising edge of this
signal. The HPOL bit of the H Position register can be set
to operate with either polarity of input signal. This is usually
the H Flyback signal. The timing difference between HIN
rising edge and the leading edge of composite sync (of
VIDEO input) is one of the factors which will affect the
horizontal position of the display. Any shift resulting from
the timing of this signal can be compensated for with the
horizontal timing value in H Position Register.

SMS (Pin 6). Mode select pin for the Serial Control Port.
When this input is at a CMOS High state (1) the Serial
Control Port will operate in the SPI mode. When the input
is Low (0), the Serial Control Port will operate in the I
slave mode. In SPI mode, the SEN pin must be tied High.
(See Reset Operation section.)

2

Input/Output

VIN/INTRO (Pin 13). In external (EXT) vertical lock mode

of operation, the internal vertical sync circuits will lock to
the VIN input signal applied at this pin. The part will lock to
the rising or falling edge of the signal in accordance with
the setting of the V Polarity command. The default is rising
edge. The VIN pulse must be at least 2 lines wide.

In INTRO Mode, when configured for internal vertical
synchronization, this pin will be an output pin providing an
interrupt signal to the master control device in accordance
with the settings in the Interrupt Mask Register.

SDA (Pin 14). When the Serial Control Port has been set

2

C mode operation, this pin serves as the bidirectional

to I
data line for sending and receiving serial data. In SPI mode
operation it operates as serial data input. SPI mode output
data is available on the SDO pin.

Outputs

SDO (Pin 16). Provides the serial data output when SPI

mode communications have been selected. This pin is not
used in I2C mode operation.

Box (Pin 17*). Black box keying output is an active High,
CMOS level signal used to key in the black box in the

C

captions/text displays. This output will be in the high­impedance state when the background attribute has been
set to semi-transparent (*Z86129 only).

SEN (Pin 4). Enable signal for the SPI mode operation of
the Serial Control Port. When this pin is Low (0), the SPI
port is disabled and the SDO pin is in the high-impedance
state. Transitions on the SCK and SDA pins are ignored.
SPI mode operation is enabled when SMS is High (1).

SCK (Pin 15). Input pin for serial clock signal from the
master control device. In I2C mode operation the clock rate
is expected to be within I2C limits. In SPI mode, the
maximum clock frequency is 10 MHz.

Reset Operation. When the SMS and SEN pins are both
in the Low (0) state, the part will be in the Reset state.
Therefore, in the I2C mode the SEN pin can be used as an
NReset input. When SPI mode is used, if three wire
operation is desired, both SMS and SEN can be tied
together and used as the NReset input. In either mode,
NReset must be held Low (0) for at least 100 ns.

RED, GREEN, BLUE (Pins 2*, 3*, 18*). Positive acting
CMOS levels signals (*Z86129 only).

Color Mode: Red, Green and Blue character video outputs
for use in a color receiver.

■ Mono Mode: All three outputs carry the character

luminance information.

Notes: The selection of Color/Mono Mode is user
controlled in bit D1 of the Configuration Register
(Address=00h). (See Internal Registers section.).

6 DS96TEL0200

Z86129/130/131

1

P R E L I M I N A R Y NTSC Line 21 Decoder

Pins With External Components

CSync (Pin 8). Sync slice level. A 0.1 µF capacitor must

be tied between this pin and analog ground VSS(A). This
capacitor stores the sync slice level voltage.

LPF (Pin 9). Loop Filter. A series RC low-pass filter must
be tied between this pin and analog ground VSS(A). There
must also be second capacitor from the pin to VSS(A).
Values for the three parts to be specified at a later date.

RREF (Pin 10). Reference setting resistor. Resistor must
be 10 kohms, ±2%.

Z86129/130/131 BLOCK DIAGRAM DESCRIPTION

The Z86129 is designed to process both fields of Line 21
of the television VBI and provide the functional
performance of a Line 21 Closed-Caption decoder and
Extended Data Service decoder. It requires two input
signals, Composite Video and a horizontal timing signal
(HIN), and several passive components for proper
operation. A vertical input signal is also required if OSD
display mode is desired when no video signal is present.
The Decoder performs several functions, namely
extraction of the data from Line 21, separation of the
normal Line 21 data from the XDS data, on-screen display
(Z86129 only) of the selected data channel and outputting
of the XDS data through the serial communications
channel.

Input Signals

The Composite Video input should be a signal which is
nominally 1.0 Volt p-p with sync tips negative and band
limited to 600 kHz. The Z86129 will operate with an input
level variation of ±3 dB.

The HIN input signal is required to bring the VCO close to
the desired operating frequency. It must be a CMOS level
signal. The HIN signal can have positive or negative
polarity and is only required to be within 3% of the standard
H frequency. When configured for EXT HLK operation, this
signal should correspond to the H Flyback signal.

The timing difference between HIN rising edge and the
leading edge of composite sync (of VIDEO input) is one of
the factors that will affect the horizontal position of the
display. Any shift resulting from the timing of this signal can
be compensated for with the horizontal timing value in the
H Position register.

Video Input Signal Processing

The Comp Video input is AC coupled to the device where
the sync tip is internally clamped to a fixed reference
voltage by means of a dual clamp. Initially, the unlocked
signal is clamped using a simple clamp. Improved impulse
noise performance is then achieved after the internal sync

Power Supply

VDD (Pin 12). The voltage on this pin is nominally 5.0 Volts

and may range between 4.75 to 5.25 Volts with respect to
the VSS pins.

VSS (Pins 1, 11). These pins are the lowest potential
power pins for the analog and digital circuits. They are
normally tied to system ground. Note: The recommended
printed circuit pattern for implementing the power
connection and critical components will be supplied at a
later date.

circuits lock to the incoming signal. Noise rejection is
obtained by making the clamp operative only during the
sync tip. The clamped composite video signal is fed to both
the Data Slicer and Sync Slicer blocks.

The Data Slicer generates a clean CMOS level data signal
by slicing the signal at its midpoint. The slice level is
established on an adaptive basis during Line 21. The
resultant value is stored until the next occurrence of that
Line 21. A high level of noise immunity is achieved by
using this process.

The Sync Slicer processes the clamped Comp Video
signal to extract Comp Sync. This signal is used to lock the
internally generated sync to the incoming video when the
video lock mode of operation has been enabled. Sync
slicing is performed in two steps. In the non-locked mode,
the sync is sliced at a fixed offset level from the sync tip.
When proper lock operation has been achieved, the slice
level voltage switches from a fixed reference level to an
adaptive level. The slice level is stored on the sync slice
capacitor, CSYNC.

The Data Clock Recovery circuit operates in conjunction
with the Digital H Lock circuit. They produce a 32H clock
signal (DCLK) that is locked in phase to the clock run-in
burst portion of the sliced data obtained from the Data
Slicer. When Line 21 code appears, DCLK phase lock is
achieved during the clock run-in burst and used to reclock
the sliced data. Once phase lock is established it is
maintained until a change in video signal occurs.

The Digital H Lock circuit produces the video timing gates,
PG, STG, and so on, which are locked in phase with
HSYNC, the video timing signal, no matter which H lock
mode is used in the display generation circuits. This
independent phase lock loop is able to respond quickly to
changes in video timing, without concern for display
stability requirements.

DS96TEL0200 7

Z86129/130/131
NTSC Line 21 Decoder P R E L I M I N A R Y

Z86129/130/131 BLOCK DIAGRAM DESCRIPTION (Continued)
VCO and One Shot

All internal timing and synchronizing signals are derived
from the on-board 12 MHz VCO. Its output is the Dot Clk
signal used to drive the Horizontal and Vertical counter
chains and for display timing. The One Shot circuit
produces a horizontal timing signal derived from the
incoming video and qualified by the Copy Guard logic
circuits.

The VCO can be locked in phase to two different sources.
For television operation, where a good horizontal display
timing signal is available, the VCO is locked to the HIN
input through the action of the Phase Detector (PH2).
When a proper HIN signal is not available, such as in a
VCR, the VCO can be locked to the incoming video
through the Phase Detector (PH1). In this case the
frequency detector (FR) circuit is activated as required to
bring the VCO within the pull-in range of PH1.

Timing and Counting Circuits

The Dot Clk is first divided down to produce the character
timing clock CHAR CLK. This signal is then further divided
to generate the horizontal timing signals, H, 2H and
HSQR. These timing signals are used in the data output
(display) circuits.

The H signal is further divided in the LINE and FLD CNTR
to produce the various decodes used to establish vertical
lock and to time the display and control functions required
for proper operation. The H signal is also used to generate
the Smooth Scroll timing signal for display.

Command Processor

The Command Processor circuit controls the manipulation
of the data for storage and display. It processes the
Control Port input commands to determine the display
status desired and the data channel selected. During the
display time (lines 43-237), this information is used to
control the loading, addressing and clearing of the Display
RAM and the operations of the Character ROM and Output
Logic circuits.

During data recovery time (TV lines 21-42), the Command
Processor, in conjunction with the data recovery circuits,
recovers the XDS data and the data for the selected data
channel. Data is sent to the RAM for storage and display
and/or to the serial port, as appropriate. Where necessary,
the Command Processor converts the input data to the
appropriate form.

Output Logic (Z86129 only)

The output logic circuits operate together to generate the
output color signals RED, GREEN and BLUE and the Box
signal. When MONOchrome mode is selected all three
color outputs will carry the Luminance information. These
outputs are positive output logic signals.

The character ROM contains the dot pattern for all the
characters. The output logic provides the hardware
underline, graphics characters and the Italics slant
generator circuits. The smooth scroll display is achieved
by the smooth scroll counter logic controlling the
addressing of the Character ROM.

The V Lock circuits produce a noise free vertical pulse
derived from the horizontal timing signal. When the user
selects Video as the vertical lock source, the internal
synchronizing signals are phased up with the incoming
video by comparing the internally generated vertical pulse
to an input vertical pulse derived from the Comp Sync
signal provided by the Sync Slicer. In the vertical lock set
to VIN mode the VIN signal is used in place of the signal
derived from Comp Sync. In either case, when proper
phasing has been established, this circuit outputs the
LOCK signal which is used to provide additional noise
immunity to the slicing circuits.

The LOCKed state is established only after several
successive fields have occurred in which these two vertical
pulses remain in sync. Once LOCKed, the internal timing
will flywheel until such time as the two vertical pulses lose
coincidence for a number of consecutive fields. Until
LOCK is established, the decoder operates on a pulse for
pulse basis.

Decoder Control Circuit

The Decoder Control circuit block is the users
communications port. It converts the information provided
to the control port into the internal control signals required
to establish the operating mode of the decoder. This port
can be operated in one of two serial modes. The SMS pin
is used to establish the serial control mode to be used.

In the two wire (I2C) control mode, the Z86129/130/131 will
respond to its slave address for both the read and write
conditions. If the read bit is Low (indicating a WRITE
sequence) then the Z86129/130/131 will respond with an
acknowledge. The master should then send an address
byte followed by a data byte. If the read bit is High
(indicating a READ sequence) then the Z86129/130/131
will respond with an acknowledge followed by a status byte
then a data byte. Read data will only be available through
indirect addressing. Write addressing will have both
indirect and direct modes. The busy bit in the status byte
will indicate if the write operation has been completed or if
read data is available.

8 DS96TEL0200

Z86129/130/131

1

P R E L I M I N A R Y NTSC Line 21 Decoder

The SPI mode is a three wire bus with the Z86129/130/131
performing as the slave device. Communication is
synchronized by the SCK signal generated by the master.
Typically, the serial data output is transmitted on the falling
edge of SCK and the received data is captured on the
rising edge of SCK. All data is exchanged as 8-bit bytes.

Z86129/130/131 FUNCTIONAL DESCRIPTION

The Z86129 provides full function NTSC, Line 21
performance. Input commands are included to enable the
decoder to process and display any of the eight
Caption/Text data channels (CC1, CC2, CC3, CC4, T1,
T2, T3 or T4) contained in Line 21 of either field of the
incoming video. XDS data can also be selected for display.
The DECODER ON/OFF commands control whether or
not the Line 21 data in the selected channel is actually
displayed. When switched to the DECODER OFF (TV)
state, incoming data in the selected channel will still be
processed but not displayed.

The Z86129/130/131 can also be configured to operate
with PAL or SECAM video signals. It will decode
information encoded into its VBI in Line 22. The encoded
data must conform to the waveform and command
structure defined for NTSC Line 21 operation.

VCO Lock

The design includes a VCO with stable gain characteristics
and good power supply rejection. The internal horizontal
and vertical synchronizing circuits provide a high degree of
noise immunity. There are options for both horizontal and
vertical lock. The VCO can be phase locked either to the
horizontal signal derived from the video input signal
(VIDEO) or to the externally supplied HIN signal, typically
horizontal flyback.

HIN lock is used to provide a display having a minimum of
observable jitter. This requires an HIN signal derived from
the TV display and of the proper polarity. Such a signal is
readily available in a television receiver. VIDEO lock mode
enables the VCO to lock in phase to the incoming video
signal, thus providing good operation in an application
where no display related HIN signal is available, such as in
a VCR.

Video Timing

Timing signals are derived from the VCO for use in the line
counting and display circuits. Line counting requires
proper identification of the input signal's vertical pulse.
Default operation uses the vertical sync signal derived
from the video input signal as the source for vertical lock.
This method results in locking characteristics having good
performance and good noise immunity.

Voltage/Current Reference

The Voltage/Current reference circuit uses an externally
connected resistor to establish the reference levels that
are used throughout the Z86129/130/131. The use of an
external resistor provides improved internal precision at
minimal additional cost.

In the event that OSD operation is required under
conditions when no input video is present, it would be
necessary to set the Z86129 for VIN lock. In this mode, the
vertical timing will be determined from the vertical pulse
signal supplied to the VIN pin.

The horizontal position of the caption display is determined
by the internal timing circuits. A default condition has been
established that should result in a well centered display in
a typical application. However, since signal delays through
video processing circuits can vary between designs, the
Z86129 provides the user with the ability to change the
default timing. No matter which of the horizontal lock
modes are selected, the display horizontal position on the
screen can be adjusted in quarter character (330 ns) steps
by serial port commands.

Displayable Character Set (Z86129 only)

Normal Mode. Characters are displayed as white or

colored dot matrix characters on an opaque background.
The Box is normally black but the Z86129 can be set to a
blue background Box with a serial command. The
characters are described by a 12 by 18 dot pattern within
a character cell which is 16 dots wide by 26 dots high per
frame. The location of the character luminance within the
character cell varies from character to character to allow
for the display of lower case letters with descenders. All
characters have at least a 1-dot border of black around
each character. Underline is also provided. Figure 4 shows
the Z86129 standard character map and font.

The character ROM consists of a 12 by 18 dot matrix
pattern per character. Figure 5 shows the character font.
Alternate rows and columns are read out in each field to
produce an interleaved and rounded character. A display
row contains a maximum of 32 characters plus a leading
and trailing black box, each a character cell in width,
making the overall width of a display row 34 x 8 = 272 dots.
Successive display rows are butted together so that the
total display occupies 195 dots high.

The black box 34 character cells wide by 195 dots high
results in a box size of 45.018 µs in width by 195 scan lines
in height. The Box starts in scan line 43 and extends to
scan line 237. Theoretically, the display will be horizontally
centered in the video display when the Box starts 13.2 µs
after the leading edge of H.

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Z86129/130/131 FUNCTIONAL DESCRIPTION (Continued)

The default setting of the Z86129 places the center of the
Box at about 13.5 µs to allow for some delay in the normal
video path. However, the Box horizontal position can be
adjusted by the user in 330 ns increments. The display will
be approximately within the safe title area for NTSC
receivers. Character width is 42.37 µs also centered on the
screen, resulting in a leading and trailing 1.32 µs black
border.

An optional Caption display mode, Drop Shadow, can be
selected by the user through the serial port. This display
mode eliminates the black box around the characters and
places a 2-dot black shadow to the right and below the
character luminance dots when in the 15 scan line per row
mode. This display mode is usable in Captions, Text and
OSD displays. Figure 5 shows the characters with
shadowing added.

Extended Features

EIA-608 defined new extended features such as optional
Background and Foreground display attributes and
optional Extended Characters. The Z86129 will always
respond to the Extended Characters but the Extended
Background/Foreground response can be controlled by
the user. The Background and Foreground attributes add
codes for background colors, black foreground as well as
transparent, opaque and semi-transparent background.
The BOX signal output pin will be set to a tri-state condition
whenever one of the semi-transparent attribute codes is
active. The external keying circuits can then use this
condition to implement the intended video display.

The font for the Extended Characters are shown in Figure

6. The accented capital letters have been implemented by
placing the accent marks above the character cell. When
selected, this mode will result in the accent marks being
written into the character cell space of the row above. In
some operating modes the Z86129 will expand the size of
the overall box height by adding two additional scan lines
at the top and one additional line at the bottom. This will
make room for the accent marks in the topmost row and
add a black line below the descenders of any lowercase
characters in the last row.

This approach is desirable because shrinking the capitals
to make room for the accent mark within the character cell
makes poor quality characters and in some cases there
would be no differentiation between the capital and lower
case letter. It also has the advantage of minimizing the
ROM size and providing a good readable font that closely
matches what is normally seen in print.

In the unlikely case of a conflict between an accented
capital letter in one row and a lower case descender in the
same character position in the row above, the descender
is given priority. The improved readability of this approach
over shrunk capital letters far outweighs this potential
conflict and results in a cost-effective compromise for
providing a full, extended features implementation.

The Extended Characters share their address space with
the OSD Graphics Characters. When a BOX display is
used the Extended Character set is in force. However, if a
Drop Shadow display is used the Graphics Characters are
in force. For Caption and Text display modes, if Drop
Shadow is set, the user must also command the Z86129
to switch back to Extended Characters.

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P R E L I M I N A R Y NTSC Line 21 Decoder

Figure 4. Z86129 Standard Character Map and Font

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Z86129/130/131 FUNCTIONAL DESCRIPTION (Continued)

Figure 5. Caption Display Mode, Drop Shadow

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Figure 6. Extended Characters Font

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Z86129/130/131 FUNCTIONAL DESCRIPTION (Continued)
Text Mode Display (Z86129 only)

When TEXT mode is selected, a black box will be
displayed as long as valid Line 21 code in the field selected
is being detected. The Z86129 provides the option to make
the box blue instead of black. This option holds for
Captions as well as Text.

The default TEXT display mode uses a 15 row by 34
character black box. TEXT characters will be displayed as
they are received starting in the top row. Successive
carriage returns will move the display down successive
rows until all 15 rows have been displayed. Thereafter, the
text will scroll up as new characters are added to the
bottom row.

If the data for the selected channel is interrupted by a
command for another channel, data processing will stop
but the display will remain. When a Resume Text
command is received, data processing will resume and the
new characters will be added starting at the position that
the display row/column pointer was in at the interruption of
data processing. If a Start Text command is received, the
display will be cleared and new characters will be
displayed starting in row 1, column 1 (left side).

The number of display rows and the location (base row) of
the TEXT box, can be altered by the user. In this way, the
user can decide how much of the screen can be covered
when displaying non-program related information.

When scrolling, the display will shift one scan line per
frame until a complete row has been scrolled. If a carriage
return is received before scrolling is complete, the display
will immediately complete the “scroll” by jumping up the
remaining scan lines and start displaying the new text.

Caption Mode Display (Z86129 only)

According to the FCC specifications Caption data can
appear in any of the 15 display rows but a single caption
may consist of no more than 4 rows. The form of the
caption display depends on the caption mode indicated by
the transmitted caption command, Pop-on, Paint-on or
Roll-up. The Z86129 can display a single caption having
as many as eight rows. When any of the CAPTION display
modes have been selected, the screen will be transparent.
(Display box is only present when a caption is being
displayed.)

Pop-on captions work with two caption memories. One of
them is normally displayed while the other is being used to
accumulate new caption data. A new caption is popped-on
by swapping the two memories with the End Of Caption
(EOC) command. When the on-screen memory is erased,
the screen is blank (transparent) and the memory will
default to the row/column pointer at row 1, column 1 and
monochrome non-underlined.

When caption mode is selected, the decoder will process
any data following the Resume Caption Loading (RCL)
command (or the EOC). Normally, this command will be
followed by a Preamble Address Code (PAC) to indicate
the row, column and character attributes to be used with
the following data. If no PAC is received the data will be
added to the location last indicated by the row/column
pointer prior to the receipt of the RCL command.

Paint-on caption mode is essentially equivalent to the Pop­on mode except that the data received after the Resume
Direct Captioning (RDC) command is written to the on­screen memory rather than the off-screen memory. All the
rules for PACs, Midcodes, and so on, are otherwise the
same.

Roll-up caption mode presents a “text” like display that is
limited to 2, 3 or 4 rows, depending on the Resume Roll­up (RUn) command used. The PAC following the RUn
command is used as the BASE ROW for the ROLL-UP
display. The BASE ROW will be the “bottom” row of the
ROLL-UP display. In this case, the black box does not
appear until characters are being displayed and the box is
only wide enough to provide a leading and trailing box in
each line. The new data appears in the bottom row and as
each carriage return is received, the row scrolls up and the
new data added to the bottom. When the number of rows
indicated by the Resume command has been reached, the
data in the top row scrolls off as new data is added to the
bottom.

The TAB (INDENT) PAC permits placing Captions starting
at 4 character boundaries in any caption row. The TAB
OFFSET command provides the means for adjusting the
starting position for a Caption at any column position in the
current row.

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XDS Display Modes (Z86129 only)

Two preprogrammed XDS display modes are provided.
One provides information about the current program that
would be of interest for “channel grazing”. The second
display shows the grazing packets plus additional XDS
packets which will inform the viewer about the program
content. Information will be displayed as it is received. The
displays use drop shadow mode with 15 scan lines per
row.

The XDSG mode is the GRAZE (channel grazing) display
(Figure 7). The display will contain three rows of
information at the top of the screen, formatted for easy
reading. They will contain the following XDS packet
information:

OSD Row 1 Network Name, Call Letters (Green)
OSD Row 2 Program Name (Italics, Underline, White)
OSD Row 3 Program Length, Time In Show (Cyan)

OSD Row 1

Network Name

Program Name

Program Length

OSD Row 2

Call Letters

Time in Show

Since 15 scan lines per row mode is being used, rows 10­13 will appear at the bottom of the screen.

OSD Row 1 Network Name, Call Letters (Green)
OSD Row 2 Program Name (Italics, Underline,

White)

OSD Row 3 Program Length, Program Type, Time In

Show (Cyan)

OSD Row 10 Program Description Row 1 (Yellow)
OSD Row 11 Program Description Row 2 (Yellow)
OSD Row 12 Program Description Row 3 (Yellow)
OSD Row 13 Program Description Row 4 (Yellow)

OSD Row 1

Network Name

Program Name

Program Length

OSD Row 3

Program Description information goes
here on OSD rows 10, 11

OSD Row 2

Call Letters

Time in Show

12 and,

13

OSD Row 3

Figure 7. XDSG (Graze) Mode Sample Display

The XDSF mode is the FULL (information) display (Figure

8). This display shows the same information as the
GRAZE display and adds the program type as well the first
four program description rows (if transmitted). Although
XDS defines eight program description rows, the first four
are identified as containing the most important information.
The display of Program Description is limited to the first
four rows because eight rows would obscure much of the
screen and because more than four rows is not likely to be
sent due to the time required for transmission.

Figure 8. XDSF Mode Sample Display

When an XDS display mode has been selected, the
information will be displayed as the appropriate packets
are received. The display will remain on screen as long as
valid XDS data continues to be received. If the 16 Second
Erase Timer is enabled (the default condition), the XDS
display will be erased when no valid XDS data has been
received for 16 Seconds. If subsequent XDS data is
received with displayable packets, that information will
reappear on the screen. XDS data recovery can be active
in the XDS display mode.

The XDS display mode is turned off by selecting a different
display mode.

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