ZILOG Z86116 Datasheet

PRELIMINARY
FEATURES
ROM RAM* SPEED
Part (Kbytes) (Kbytes) (MHz)
Z86116 1 124 12
* General-Purpose
18-Pin DIP and SOIC Packages
3.0- to 5.5-Volt Operating Range
Low-Power Consumption
Z86116
CP95WRL0501
P
RELIMINARY
C
USTOMER PROCUREMENT SPECIFICATION
Z86116
CMOS Z8® PN MODULATOR WIRELESS CONTROLLER
On-Chip PN Modulator for Spread Spectrum
Communications
12 Input/Output Lines (One with Comparator Input)
Vectored, Prioritized Interrupts With Programmable
Polarity
Analog Comparator
Two Programmable 8-Bit Counter/Timers Each with
Two 6-Bit Programmable Prescalers
0° to +70°C Temperature Range
Expanded Register File (ERF)
GENERAL DESCRIPTION
The Z86116 Wireless Controller is a member of the Z8 single-chip microcontroller family based on Zilog’s 8-bit microcontroller core. The Z86116 is designed with specific features for wireless spread spectrum applications using direct sequence pseudo-noise (PN) modulation.
Three address spaces, the Program Memory, Register File, and Expanded Register File (ERF), support a wide range of memory configurations. Through the ERF, the designer has access to three additional control registers that provide extra peripheral devices, I/O ports, and register addresses.
Watch-Dog Timer (WDT)/Power-On Reset (POR)
On-Chip Oscillator that Accepts a RC, or External
Clock Drive
Low-Voltage Protection / Low-EMI Option
®
For applications demanding powerful I/O capabilities, the Z86116's dedicated input and output lines are grouped into two ports, and are configurable under software control to provide timing, status signals, or parallel I/O.
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g., B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection Circuit Device
Power V
Ground GND V
CC
V
DD SS
CP95WRL0501 (8/95)
1

FUNCTIONAL DESCRIPTION

PRELIMINARY
Z86116
CP95WRL0501
TM BASE
InputOutput
Port 3
Counter/
Timers (2)
Interrupt
Control
T wo Analog
Comparators
PN
Modulator
VCC GND
ALU
FLAG
Register
Pointer
Register File
144 x 8-Bit
RC
Machine T iming &
Instruction Control
Time Base
Generator
WDT, POR
Prg. Memory
1024 x 8-Bit
Program
Counter
Port 2
I/O
(Bit Programmable)
Functional Block Diagram
2
PRELIMINARY
FUNCTIONAL DESCRIPTION (Continued)
P24 P25 P26 P27
1 2 3 4
18 17 16 15
P23 P22 P21 P20
Z86116
CP95WRL0501
18-Pin DIP/SOIC Pin Identification
No Symbol Function Direction
1-4 P24-27 Port 2, Pins 4, 5, 6, 7 In/Output 5VCCPower Supply Input 6 RC2 RC Oscillator Clock Output 7 RC1 RC Oscillator Clock Input
Z86116
VCC
RC2
RC1
P31 P33
18-Pin DIP/SOIC Pin Configuration
5 6 7 8 9
14 13 12 11 10
GND P36 P35 GND TM BASE
8-9 P31, P33 Port 3, Pins 1, 3 Fixed Input 10 TM BASE Time Base Clock Input 11 GND Ground 12-13 P35-36 Port 3, Pins 5, 6 Fixed Output 14 GND Ground 15-18 P20-23 Port 2, Pins 0, 1, 2, 3 In/Output
3
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