Zilog EZ80F916 User Manual
eZ80® CPU
User Manual
UM007715-0415
Copyright © 2015 by Zilog®, Inc. All rights reserved.
www.zilog.com
eZ80® CPU
Warning:
User Manual
DO NOT USE IN LIFE SUPPORT
LIFE SUPPORT POLICY
ZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF
THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.
As used herein
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)
support or sustain life and whose failure to perform when properly used in accordance with instructions for
use provided in the labeling can be reasonably expected to result in a significant injury to the user. A
critical component is any component in a life support device or system whose failure to perform can be
reasonably expected to cause the failure of the life support device or system or to affect its safety or
effectiveness.
ii
Document Disclaimer
©2015 by Zilog, Inc. All rights reserved. Information in this publication concerning the devices,
applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG,
INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY
OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT.
ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY
INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR
TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this
document has been verified according to the general principles of electrical and mechanical engineering.
Z8, Z8 Encore!, eZ80, Z8 Encore! XP, Z8 Encore! MC, Crimzon, and ZNEO are tradema rks or registered
trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. .
UM007715-0415
Revision History
Each instance in Revision History reflects a change to this document from its previous
revision. For more details, refer to the corresponding pages and appropriate links in the
table below.
Revision
Date
April 2015 15 Corrected the typo on Page 25 from '59h'
September
2008
Level Description Page Number
14 Change to new User Manual format All
eZ80® CPU
User Manual
iii
25
to '49h'.
UM007715-0415 Revision History
Table of Contents
Manual Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .vi
About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi
Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi
Manual Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .vi
Manual Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
Safeguards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ix
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Processor Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pipeline Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
eZ80® CPU
User Manual
iv
Memory Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Z80 MEMORY Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ADL MEMORY Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Registers and Bit Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
®
eZ80
CPU Working Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
®
CPU Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
eZ80
®
eZ80
CPU Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
®
eZ80
CPU Registers in Z80 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
®
CPU Registers in ADL Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
eZ80
®
eZ80
CPU Status Indicators (Flag Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Memory Mode Switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ADL Mode and Z80 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Memory Mode Compiler Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Opcode Suffixes for Memory Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Single-Instruction Memory Mode Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Suffix Completion by the Assembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Assembly of the Opcode Suffixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Persistent Memory Mode Changes in ADL and Z80 Modes . . . . . . . . . . . . . . . . . . . . 25
Mixed-Memory Mode Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
MIXED MEMORY Mode Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Interrupt Enable Flags (IEF1 and IEF2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Interrupts in Mixed Memory Mode Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
®
eZ80
CPU Response to a Nonmaskable Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
®
eZ80
CPU Response to a Maskable Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Vectored Interrupts for On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
UM007715-0415 Table of Contents
eZ80® CPU
User Manual
Illegal Instruction Traps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
I/O Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Addressing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
v
CPU Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
®
eZ80
CPU Assembly Language Programming Introduction . . . . . . . . . . . . . . . . . . . 52
®
CPU Instruction Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
eZ80
®
eZ80
CPU Instruction Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
®
CPU Instruction Set Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
eZ80
Opcode Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
UM007715-0415 Table of Contents
Manual Objectives
This user manual describes the architecture and instruction set of the eZ80® CPU User
Manual.
About This Manual
Zilog recommends you to read all the chapters and instructions provided in this manual
before using the software.
Intended Audience
eZ80® CPU
User Manual
vi
This document is written for Zilog customers who are experienced at working with microcontrollers or in writing assembly code or compilers.
Manual Organization
The eZ80 CPU User Manual is divided into twelve sections; each section details a specific
topic about the product.
Introduction
This chapter provides an introduction to eZ80 CPU, Zilog’s next-generation processor
core.
Architectural Overview
This chapter provides an overview of eZ80 CPU’s features and benefits, and a description
of the eZ80 processor.
Memory Modes
This chapter describes eZ80’s two memory modes: ADL and Z80.
Registers and Bit Flags
This chapter provides register and bit descriptions for ADL and Z80 modes.
Memory Mode Switching
This chapter provides description of switching capability between ADL and Z80 modes.
UM007715-0415 Manual Objectives
eZ80® CPU
User Manual
Interrupts
This chapter describes interrupt operation in maskable and nonmaskable mixed memory
modes.
Illegal Instruction Traps
This chapter describes the consequences of undefined operations.
I/O Space
This chapter describes input/output memory for on- and off-chip peripherals.
Addressing Modes
This chapter describes methods of accessing different addressing modes.
Mixed-Memory Mode Applications
vii
This chapter describes the MADL control bit and mixed memory mode guidelines.
CPU Instruction Set
This chapter lists assembly language instructions, including mnemonic definitions and a
summary of the eZ80
®
CPU instruction set.
Opcode Maps
This chapter provides a detailed diagram of each opcode segment.
Related Documents
eZ80190 eZ80190 Product Specification PS0066
eZ80190 Module Product Specification PS0191
eZ80L92 eZ80L92 Product Specification PS0130
eZ80L92 Module Product Specification PS0170
eZ80F92 eZ80F92 Product Specification PS0153
eZ80F92 Ethernet Module Product Specification PS0186
eZ80F92 Flash Module Product Specification PS0189
eZ80F91 eZ80F91 Product Specification PS0192
eZ80F91 Module Product Specification PS0193
Manual Conventions
The following conventions are used to provide clarity in the document.
UM007715-0415 Manual Objectives
eZ80® CPU
User Manual
Courier Typeface
Commands, code lines and fragments, bits, equations, hexadecimal addresses, and various
executable items are distinguished from general text by the use of the
Where the use of the font is not indicated, as in the Index, the name of the entity is presented in upper case.
•
Example: FLAGS[1] is smrf.
Hexadecimal Values
Courier typeface.
viii
Hexadecimal values are designated by a lowercase h and appear in the
•
Example: STAT is set to F8h.
Brackets
The square brackets, [ ], indicate a register or bus.
•
Example: for the register REG1[7:0], REG1 is an 8-bit register, REG1[7] is the msb,
and REG1[0] is the lsb.
Braces
The curly braces, { }, indicate a single register or bus created by concatenating some combination of smaller registers, or buses.
•
Example: the 24-bit register {00h, REG1[7:0], REG2[7:0]} is composed of an 8-bit
hexadecimal value (
the 24-bit register, and REG2 is the LSB of the 24-bit register.
Parentheses
The parentheses, ( ), indicate an indirect register address lookup.
•
Example: (BC) is the memory location referenced by the address contained in the BC
register.
00h) and two 8-bit registers, REG1 and REG2. 00h is the MSB of
Courier typeface.
Parentheses/Bracket Combinations
The parentheses, ( ), indicate an indirect register address lookup and the square brackets, [
], indicate a register or bus.
•
Example: assume BC[15:0] contains the value 1234h. ({37h, BC[15:0]}) then refers
to the contents of the memory location at address
Use of the Words Set and Clear
The words set and clear imply that a register bit or a condition contains a logical 1 and a
logical 0, respectively. When either of these terms is followed by a number, the word logi-
cal may not be included; however, it is implied.
UM007715-0415 Manual Objectives
371234h.
eZ80® CPU
User Manual
Use of the Terms LSB and MSB
In this document, the terms LSB and MSB, when appearing in upper case, mean least significant byte and most significant byte, respectively. The lowercase forms, msb and lsb,
mean least significant bit and most significant bit, respectively.
Use of Initial Uppercase Letters
Initial uppercase letters designate settings, modes, and conditions in general text.
•
Example 1: The Slave receiver leaves the data line High.
•
Example 2: The receiver forces the SCL line to Low.
•
Example 3: The Master can generate a Stop condition to abort the transfer.
Use of All Uppercase Letters
The use of all uppercase letters designates the names of states, modes, and commands.
ix
•
Example 1: The bus is considered BUSY after the Start condition.
•
Example 2: In TRANSMIT mode, the byte is sent most significant bit first.
•
Example 3: A START command triggers the processing of the initialization sequence.
Register Access Abbreviations
Register access is designated by the following abbreviations:
Designation Description
R Read Only
R/W Read/Write
W Write Only
— Unspecified or indeterminate
Bit Numbering
Bits are numbered from 0 to n–1.
Safeguards
It is important that you understand the following safety terms, which are defined here.
Caution:
UM007715-0415 Manual Objectives
Means a procedur e or file may become corrupted if you do not follow
directions.
Introduction
Zilog’s eZ80® CPU is a high-speed, 8-bit microcontroller capable of executing code four
times faster than a standard Z80 operating at the same clock speed. The increased
processing efficiency of the eZ80 CPU improves available bandwidth and decrease power
consumption. The eZ80 CPU’s 8-bit processing power rivals the performance of
competitors’ 16-bit microcontrollers.
The eZ80 CPU is also the first 8-bit microcontroller to support 16 MB linear addressing.
Each software module, or each task, under a real-time executive or operating system can
operate in Z80-compatible (64 KB) mode or full 24-bit (16 MB) address mode.
The eZ80 CPU’s instruction set is a superset of the instruction sets for the Z80 and Z180
CPUs. The Z80 and Z180 programs are executed on an eZ80 CPU with little or no modification.
eZ80® CPU
User Manual
1
The eZ80 CPU is combined with peripherals, I/O devices, volatile and nonvolatile
memory, etc., for various eZ80 CPU products within the eZ80 and eZ80Acclaim!
product lines. Refer to the eZ80 and eZ80Acclaim!
information on these products.
1
®
product specifications for more
®
1. The term eZ80® CPU is referred to as CPU in this document.
UM007715-0415 Introduction
Architectural Overview
The eZ80® CPU is Zilog's next-generation Z80 processor core. It is the basis of a new
family of integrated microcontrollers and includes the following features:
•
Upward code-compatible from Z80 and Z180 products.
•
Several address-generation modes, including 24-bit linear addressing.
•
24-bit registers and ALU.
•
8-bit data path.
•
Single-cycle fetch.
•
Pipelined fetch, decode, and execute.
eZ80® CPU
User Manual
2
Processor Description
The eZ80® CPU is an 8-bit microcontroller that performs certain 16- or 24-bit operations.
A simplified block diagram of the CPU is displayed in Figure 1. Understanding the sepa-
ration between the control block and the data block is helpful toward understanding the
two eZ80
mode.
Control Block Data Block
DATA
®
memory modes—Z80 mode and ADDRESS AND DATA LONG (ADL)
Instruction
Fetch
Mode
Control
Figure 1. eZ80
I/O Control
Op Code
Decoder
CPU
Registers
ALU
®
CPU Block Diagram
Address
Generator
Data
Selector
ADDR
DATA
Instruction Fetch
The instruction fetch block contains a state machine which controls the READs from
memory. It fetches opcodes and operands and keeps track of the start and end of each
instruction. An instruction fetch block stores opcodes during external memory READs
UM007715-0415 Architectural Overview
eZ80® CPU
User Manual
and WRITEs. It also discards prefetched instructions when jumps, interrupts, and other
control transfer events occur.
Mode Control
3
The Mode Control block of the CPU controls which mode the processor is currently operating in: HALT mode, SLEEP mode, Interrupt mode, debug mode, and ADL mode
1
.
Opcode Decoder
The opcodes are decoded within the CPU control block. After each instruction is fetched,
it is passed to the decoder. The opcode decoder is organized similarly to a large microcoded ROM.
CPU Registers
The CPU registers are contained within the CPU’s data block. Some are special purpose
registers, such as the Program Counter, the Stack Pointer, and the Flags register. There are
also a number of CPU control registers.
ALU
The arithmetic logic unit (ALU) is contained within the CPU’s data block. The ALU performs the arithmetic and logic functions on the addresses and the data passed over from
the control block or from the CPU
registers.
Address Generator
The address generator creates the addresses for all CPU memory READ and WRITE operations. The address generator also contains the Z80 Memory Mode Base Address register
(MBASE) for address translation in Z80 mode operation.
Data Selector
The data selector places the appropriate data onto the data bus. The data selector controls
the data path based on the instruction currently being executed.
Pipeline Description
The CPU pipeline reduces the overall cycle time for each instruction. In principle, each
instruction must be fetched, decoded, and executed. This process normally spans at least
three cycles. The CPU pipeline, however, can reduce the overall time of some instructions
to as little as one cycle by allowing the next instruction to be prefetched and decoded
1. The debug interface is discussed in greater detail in the eZ80
product specification.
UM007715-0415 Architectural Overview
®
product specification and eZ80Acclaim!®
eZ80® CPU
User Manual
while it executes the current instruction as displayed in Figure 2. The CPU operates on
multiple instructions simultaneously to improve operating efficiency.
System Clock
4
Instruction 1
Instruction 2
Instruction 3
Fetch Decode Execute
Fetch Decode Execute
Fetch Decode Execute
Figure 2. Pipeline Overview
In Figure 3, the pipelining process is demonstrated using a series of instructions. The first
LD
instruction prefetches its opcode and first operand during the decode and execute
phases of the preceding
INC
instruction. However, the second LD instruction in the
sequence only prefetches its opcode. The bus WRITE during the execute phase of the first
LD
instruction prevents the pipeline from prefetching the first operand of the next instruction. Thus, the number of bytes prefetched is a function of the command currently executing in the CPU.
When a control transfer takes place, the Program Counter (PC) does not progress sequentially. Therefore, the pipeline must be flushed. All prefetched values are ignored. Control
transfer can occur because of an interrupt or during execution of a Jump
RET
Return (
), Restart (
RST
), or similar instruction. After the control transfer instruction
(JP
),
CALL
,
is executed, the pipeline must start over to fetch the next operand.
UM007715-0415 Architectural Overview
Clock
Address
PC
PC+1 PC+2 PC+3 PC+4 PC+5 PC+6 PC+7 5678h1234h
eZ80® CPU
User Manual
5
Data In
Command
Execution
State
LD (1234h), A
LD (5678h), A
Data Out
INST_READ
MEM_READ
MEM_WRITE
INC A LD (nn), A nL nH LD (nn), A Write nL nH INC A Write
INC A Fetch Decode
INC A
Note: F & D = Fetch & Decode
Prefetch
Next command
Execute
F & D F & D Decode
1 clock delay for execution
Execute
Prefetch
F & D F & D Decode
Figure 3. Pipeline Example
78h(1234h)32h12h (5678h)3Ch56h34h32h3Ch
1 clock delay for execution
Next command
Execute
Prefetch
ValidInvalidValidInvalid
UM007715-0415 Architectural Overview
Memory Modes
The eZ80® CPU is capable of operating in two memory modes: Z80 mode and ADL
mode. For backward compatibility with legacy Z80 programs, the CPU operates in Z80
MEMORY mode with 16-bit addresses and 16-bit CPU registers. For 24-bit linear
addressing and 24-bit CPU registers, the CPU operates in ADDRESS AND DATA LONG
(ADL) mode. Selection of the memory mode is controlled by the ADL mode bit.
The multiple memory modes of the processor allow CPU products to easily mix existing
Z80 code or Z180 code with new ADL mode code. Collectively, the Z80 and ADL
memory modes may be referred to as ADL modes, because they are controlled by the
ADL bit.
Z80 MEMORY Mode
eZ80® CPU
User Manual
6
When the ADL bit is cleared to 0, the CPU operates using Z80-compatible addressing and
Z80-style, 16-bit CPU registers. This Z80 MEMORY mode is also occasionally referred to
as non-ADL mode. Z80 MEMORY mode is the default operating mode on reset.
In Z80 MEMORY mode (or its alternate term, Z80 mode), all of the multibyte internal
CPU registers are 16 bits. Also, the 16-bit Stack Pointer Short (SPS) register is used to
store the stack pointer value.
In addition, the CPU employs an 8-bit MBASE address register that is always prepended
to the 16-bit Z80 mode address. The complete 24-bit address is returned by {MBASE,
ADDR[15:0]}. The MBASE address register allows Z80 code to be placed anywhere
within the available 16 MB addressing space. This placement allows for 256 unique Z80
code blocks within the 16 MB address space, as displayed in Figure 4 on page 7.
UM007715-0415 Memory Modes
eZ80® CPU
User Manual
7
MBASE
00h
01h
02h
8Fh
FEh
FFh
Z80 Mode˜Page 0
64 KB
Z80 Mode˜Page 1
64 KB
Z80 Mode˜Page 2
64 KB
Z80 Mode˜Page 127
64 KB
Z80 Mode˜Page 254
64 KB
Z80 Mode˜Page 255
64 KB
Memory
Location
000000h
00FFFFh
010000h
01FFFFh
020000h
02FFFFh
8F0000h
8FFFFFh
FE0000h
FEFFFFh
FF0000h
FFFFFFh
Figure 4. Z80 MEMORY Mode Map
When MBASE is set to 00h, the CPU operates like a classic Z80 with
16-bit addressing from
bit Z80-style addresses are offset to a new page, as defined by MBASE.
By altering MBASE, multiple Z80 tasks can possess their own individual Z80 partitions.
The MBASE register can only be changed while in ADL mode, thereby preventing accidental page switching when operating in Z80 MEMORY mode. The MBASE address register does not affect the length of the CPU register. In Z80 mode, the CPU registers remain
16 bits, independent of the value of MBASE. For more information on the CPU registers
in Z80 mode, see the eZ80
ADL MEMORY Mode
Setting the ADL bit to 1 selects ADL mode. This memory mode is referred to as ADL
MEMORY mode or ADL mode. In ADL mode, the user application can take advantage of
the CPU’s 16 MB linear addressing space, 24-bit CPU registers, and enhanced instruction
0000h to 00FFh. When MBASE is set to a nonzero value, the 16-
®
CPU Registers in Z80 Mode on page 11.
UM007715-0415 Memory Modes
eZ80® CPU
User Manual
set. When ADL mode is selected, MBASE does not affect memory addressing. Figure 5
displays the ADL mode memory map.
8
Note:
There are no pages in ADL mode.
24-Bit
Address
000000h
FFFFFFh
Figure 5. ADL Addressing Mode Memory Map
Memory
Location
000000h
ADL Mode
16 MB Linear
Memory Space
FFFFFFh
In ADL mode, the CPU’s multibyte registers are expanded from 16 to 24 bits. A 24-bit
Stack Pointer Long (SPL) register replaces the 16-bit Stack Pointer Short (SPS) register.
®
For more information on the CPU registers in ADL mode, see eZ80
CPU Registers in
ADL Mode on page 12.
In ADL mode, all addresses and data are 24 bits. All data READ and WRITE operations
pass 3 bytes of data to and from the CPU when operating in ADL mode (as opposed to
only 2 bytes of data while in Z80 mode operation). Thus, instructions operating in ADL
mode may require more clock cycles to complete than in Z80 mode. Although MBASE
does not affect operation during ADL mode, the MBASE register can only be written to
when operating in ADL mode.
UM007715-0415 Memory Modes
Registers and Bit Flags
eZ80® CPU Working Registers
The CPU contains two banks of working registers—the main register set and the alternate
register set. The main register set contains the 8-bit accumulator register (A) and six 8-bit
working registers (B, C, D, E, H, and L). The six 8-bit working registers can be combined
to function as the multibyte register pairs BC, DE, and HL. The 8-bit Flag register F completes the main register set.
Similarly, the alternate register set also contains an 8-bit accumulator register (A’) and six
8-bit working registers (B’, C’, D’, E’, H’, and L’). These six 8-bit alternate working registers can also be combined to function as the multibyte register pairs BC’, DE’, and HL’.
The 8-bit Flag register F’ completes the alternate register set.
eZ80® CPU
User Manual
9
High-speed exchange between these two register banks is performed. See the EX and
EXX instructions on pages 143 through 147 for directions on exchanging register bank
contents. High-speed exchange between these banks can be used by a single section of
application code. Alternatively, the main program could use one register bank while the
other register banks are allocated to interrupt service routines.
eZ80® CPU Control Register Definitions
In addition to the two working register sets described in the previous section, the CPU
contains several registers that control CPU operation.
•
Interrupt Page Address Register (I)—the 16-bit I register stores the upper 16 bits of
the interrupt vector table address for Mode 2 vectored interrupts.
Note:
The 16-bit I register is not supported on eZ80190, eZ80L92, or eZ80F92/F93 devices.
•
Index Registers (IX and IY)—the multibyte registers IX and IY allow standard
addressing and relative displacement addressing in memory. Many instructions
employ the IX and IY registers for relative addressing in which an 8-bit two’s-comple-
d
ment displacement (
address. Additionally, certain 8-bit opcodes address the High and Low bytes of these
registers directly. For Index Register IX, the High byte is indicated by IXH, while the
Low byte is indicated by IXL. Similarly, for Index Register IY, the High byte is indicated by IYH, while the Low byte is indicated by IYL.
) is added to the contents of the IX or IY register to generate an
•
Z80 Memory Mode Base Address (MBASE) register—the 8-bit MBASE register
determines the page of memory currently employed when operating in Z80 mode. The
MBASE register is only used during Z80 mode. However, the MBASE register can
only be altered from ADL mode.
UM007715-0415 Registers and Bit Flags
eZ80® CPU
User Manual
•
Program Counter (PC) register—the multibyte Program Counter register stores the
address of the current instruction being fetched from memory. The Program Counter is
automatically incremented during program execution. When a program jump occurs,
the new value is placed in the Program Counter, overriding the incremented value. In
Z80 mode, the Program Counter is only 16 bits; however, a full 24-bit address
{MBASE,PC[15:0]}, is used. In ADL mode, the Program Counter is returned by
{PC[23:0]}.
•
Refresh Counter (R) register—the Refresh Counter register contains a count of executed instruction fetch cycles. The 7 least significant bits (lsb) of the R register are
automatically incremented after each instruction fetch. The most significant bit (msb)
can only be changed by writing to the R register. The R register can be read from and
written to using dedicated instructions
•
Stack Pointer Long (SPL) register—in ADL mode, the 24-bit Stack Pointer Long
stores the address for the current top of the external stack. In ADL mode, the stack can
be located anywhere in memory. The external stack is organized as a last-in first-out
(LIFO) file. Data can be pushed onto the stack or popped off of the stack using the
PUSH and POP instructions. Interrupts, traps, calls, and returns also employ the
stack.
LD
A,R and LD R,A, respectively.
10
•
Stack Pointer Short register (SPS)—in Z80 mode, the 16-bit Stack Pointer Short stores
the address for the current top of the stack. In Z80 mode, the stack can be located anywhere within the current Z80 memory page. The current Z80 memory page is selected
by the MBASE register. The 24-bit Stack Pointer address in Z80 mode is {MBASE,
SPS}. The stack is organized as a last-in first-out (LIFO) file. Data can be pushed onto
the stack or popped off of the stack using the PUSH and POP instructions. Interrupts,
traps, calls, and returns also employ the stack.
eZ80® CPU Control Bits
•
Address and Data Long Mode Bit (ADL)—the ADL mode bit indicates the current
memory mode of the CPU. An ADL mode bit reset to 0 indicates that the CPU is operating in Z80 MEMORY mode with 16-bit Z80-style addresses offset by the 8-bit
MBASE register. An ADL mode bit set to 1 indicates that the CPU is operating in
ADL mode with 24-bit linear addressing. The default for the ADL mode bit is reset
(cleared to 0). The ADL mode bit can only be changed by those instructions that allow
persistent memory mode changes, interrupts, and traps. The ADL mode bit cannot be
directly written to.
•
Mixed-ADL Bit (MADL)—the MADL control bit is used to configure the CPU to
execute programs containing code that uses both ADL and Z80 MEMORY modes.
The MADL control bit is explained in more detail in Interrupts in Mixed Memory
Mode Applications on page 36. An additional explanation is available in the MixedMemory Mode Applications on page 34.
UM007715-0415 Registers and Bit Flags
•
Interrupt Enable Flags (IEF1 and IEF2)—in the CPU, there are two interrupt enable
flags that are set or reset using the Enable Interrupt (EI) and Disable Interrupt (DI)
instructions. When IEF1 is reset to 0, a maskable interrupt cannot be accepted by the
CPU. The Interrupt Enable flags are described in more detail in Interrupts on page 36.
eZ80® CPU Registers in Z80 Mode
In Z80 mode, the BC, DE, and HL register pairs and the IX and IY
registers function as 16-bit registers for multibyte operations and indirect addressing. The
active Stack Pointer is the 16-bit Stack Pointer Short
register (SPS). The Program Counter register (PC) is also 16 bits long. The address is 24
bits long and is composed as {MBASE, ADDR[15:0]}. While the MBASE register is only
used during Z80 mode operations, it cannot be written while operating in this mode.
Tables 1 and 2 lists the CPU registers and bit flags during Z80 mode operation.
eZ80® CPU
User Manual
11
Caution:
Note:
In Z80 mode, the upper byte of the I register, bits [15:8], is not used.
In Z80 mode, the upper byte (bits 23:16) of each multibyte register is
undefined. When performing 16-bit operations with these registers, the
application program cannot assume values or behavior for the upper byte. The upper
byte is only valid in ADL mode.
Table 1. CPU Working Registers in Z80 Mode
Main Register Set Alternate Register Set
8-Bit
Registers
AA’
FF’
Individual
8-Bit
Registers
B C BC B’ C’ BC’
D E DE D’ E’ DE’
Or
16-Bit
Registers
8-Bit
Registers
Individual
8-Bit
Registers
16-Bit
Registers
Or
H L HL H’ L’ HL’
UM007715-0415 Registers and Bit Flags
Table 2. CPU Control Registers and Bit Flags in Z80 Mode
eZ80® CPU
User Manual
12
8-Bit
Registers
I SPS ADL
MBASE PC MADL
RIEF1
Individual 8-Bit Registers
IXH IXL IX
IYH IYL IY
Or
eZ80® CPU Registers in ADL Mode
In ADL mode, the BC, DE, HL, IX and IY registers are 24 bits long for multibyte operations and indirect addressing. The most significant bytes (MSBs) of these 3 multibyte reg-
isters are designated with a U to indicate the upper byte. For example, the upper byte of
multibyte register BC is designated BCU. Thus, the 24-bit BC register in ADL mode is
composed of the three 8-bit registers {BCU, B, C}. Likewise, the upper byte of the IX register is designated IXU. The 24-bit IX register in ADL mode is composed of the three 8-bit
registers {IXU, IXH, IXL}.
16-Bit
Registers Single-Bit Flags
IEF2
16-Bit
Registers
Note:
None of the upper bytes (BCU, DEU, IXU, etc.) are individually accessible as standalone
8-bit registers.
MBASE is not used for address generation in ADL mode; however, it can only be written
in ADL mode. The Program Counter is 24 bits long, as is SPL. IEF1, IEF2, ADL, and
MADL are single bit flags.
The CPU registers and bit flags during Z80 mode operation are indicated in Tables 3 and
4. Reset states are detailed in Table 5.
UM007715-0415 Registers and Bit Flags
Table 3. CPU Working Registers in ADL Mode
Main Register Set Alternate Register Set
eZ80® CPU
User Manual
13
8-Bit
Registers
AA’
FF’
24-Bit
Individual
8-Bit Registers
BCU B C BC BCU’ B’ C’ BC’
DEU D E DE DEU’ D’ E’ DE’
HLU H L HL HLU’ H’ L’ HL’
Register
s
Or
8-Bit
Registers
Individual
8-Bit Registers
24-Bit
Register
s
Or
Table 4. CPU Control Registers and Bit Flags in ADL Mode
Control Registers and Bit Flags
Single-Bit
8-Bit Registers 24-Bit Registers
I SPL ADL
MBASE PC MADL
RIEF1
Flags
IEF2
Individual
8-Bit Registers
IXU IXH IXL IX
IYU IYH IYL IY
UM007715-0415 Registers and Bit Flags
24-Bit Registers
Or
Table 5. CPU Register and Bit Flag Reset States
CPU Register
or Bit Flag Reset State
8-Bit Working Registers A, A’ Undefined
B, B’ Undefined
C, C’ Undefined
D, D’ Undefined
E, E’ Undefined
F, F’ Undefined
H, H’ Undefined
L, L’ Undefined
Upper Bytes of 24-Bit Multibyte
Working Registers
8-Bit Control Registers I 00h
Upper Bytes of 24-Bit Multibyte
Control Registers
16- and 24-Bit Control Registers PC 000000h
Single-Bit Flags ADL 0
BCU Undefined
DEU Undefined
HLU Undefined
IXH 00h
IXL 00h
IYH 00h
IYL 00h
MBASE 00h
R 00h
IXU 00h
IYU 00h
SPS 0000h
SPL 000000h
IEF1 0
IEF2 0
MADL 0
eZ80® CPU
User Manual
14
eZ80® CPU Status Indicators (Flag Register)
The Flag register (F and F’) contains status information for the CPU. The bit position for
each flag is indicated in Table 6 .
Table 6. Flag Register Bit Positions
Bit 76543210
Flag S Z XHXP/VNC
UM007715-0415 Registers and Bit Flags
eZ80® CPU
User Manual
where:
C = Carry Flag
N = Add/Subtract Flag
P/V = Parity/Overflow Flag
H = Half-Carry Flag
Z = 0 Flag
S = Sign Flag
X = Not used
Each of the two CPU flag registers contain six bits of status information that are set or
reset by CPU operations. Bits 3 and 5 are not used. Four of these bits are testable (C, P/V,
Z and S) for use with conditional
jump, call
or
return
instructions. Two flags are not test-
able (H, N) and are used for BCD arithmetic.
Carry Flag (C)
15
The Carry Flag bit is set or reset, depending on the operation that is performed. For
instructions that generate a carry and
SUBTRACT
Carry flag is set to 1. The Carry flag is reset by an
instructions that generate a borrow, the
ADD
that does not generate a carry, and
ADD
a subtract that does not generate a borrow. This saved carry facilitates software routines
for extended precision arithmetic. Also, the
DAA
instruction sets the Carry flag to 1 if the
conditions for making the decimal adjustment are met.
For the
RLA, RRA, RLC
and
RRC
instructions, the Carry flag is used as a link between
the least significant bit (lsb) and most significant bit (msb) for any register or memory
location. During the
RLCA, RLC m
value shifted out of bit 7 of any register or memory location. During the
SRA m
and
SRL m
instructions, the carry contains the last value shifted out of bit 0 of
any register or memory location. For the logical instructions
A s
, the carry is reset. The Carry flag can also be set (
and
SLA m
instructions, the carry contains the last
RRCA, RRC m
AND A s, OR A s
SCF
) and complemented (
, and
CCF
XOR
).
Add/Subtract Flag (N)
The Add/Subtract (N) flag is used by the decimal adjust accumulator instructions (
ADD
and
to distinguish between
is set to 0. For all
SUBTRACT
SUBTRACT
instructions, N is set to 1.
instructions. For all
ADD
instructions, N
DAA
)
Parity/Overflow Flag (P/V)
The Parity/Overflow (P/V) flag is set or reset, depending on the operation that is performed. For arithmetic operations, this flag indicates an overflow condition when the
result in the accumulator is greater than the maximum possible number (+127) or is less
than the minimum possible number (–128). This overflow condition can be determined by
examining the sign bits of the operands.
,
UM007715-0415 Registers and Bit Flags
eZ80® CPU
User Manual
For addition, operands with different signs never causes overflow. When adding operands
with like signs where the result yields a different sign, the overflow flag is set to 1, as indicated in Table 7 .
Table 7. Overflow Flag Addition Settings
+120 = 0111 10 00 ADDEND
+105 = 0110 10 01 AUGEND
+225 1110 0001 (–95) SUM
The two numbers added together result in a number that exceeds +127 and the two positive operands result in a negative number (–95), which is incorrect. Thus, the Overflow
flag is set to 1.
For subtraction, overflow can occur for operands of unlike signs. Operands of like signs
never causes overflow, as indicated in Table 8.
Table 8. Overflow Flag Subtraction Settings
16
+127 0111 1111 MINUEND
(–) –64 1100 0000 SUBTRAHEND
+191 1011 1111 DIFFERENCE
The minuend sign is changed from positive to negative, returning an incorrect difference.
Thus, overflow is set to 1. Another method for
predicting an overflow is to observe the carry into and out of the sign bit. If there is a carry
in and no carry out, then overflow occurs.
This flag is also used with logical operation and rotate instructions to
indicate the parity of the result. The number of 1 bits in a byte are counted. If the total is
odd, then odd parity (P = 0) is flagged. If the total is even, then even parity (P = 1) is
flagged.
During search instructions (
(
LDI, LDIR, LDD, LDDR
CPI, CPIR, CPD, CPDR
) and block transfer instructions
), the P/V flag monitors the state of the byte count register
(BC). When decrementing, the byte counter results in a 0 value and the flag is reset to 0;
otherwise the flag is logical 1.
During
LD A, I
and
LD A, R
instructions, the P/V flag is set to 1 with the contents of the
interrupt enable flip-flop (IEF2) for storage or testing. When inputting a byte from an I/O
device,
IN r,(C)
, the flag is adjusted to indicate the parity of the data.
The P/V flag is set to 1 to indicate even parity, and cleared to 0 to indicate odd parity.
UM007715-0415 Registers and Bit Flags
eZ80® CPU
User Manual
Half-Carry Flag (H)
The Half-Carry flag (H) is set or reset, depending on the carry and borrow status between
bits 3 and 4 of an 8-bit arithmetic operation. This flag is used by the decimal adjust accumulator instruction (
DAA
) to correct the result of a packed BCD addition or subtraction.
The H flag is set to 1 or reset to 0, as indicated in Table 9.
Table 9. H Flag Settings
H ADD SUBTRACT
1 There is a carry from bit 3 to bit 4 There is a borrow from bit 4.
0 There is no carry from bit 3 to bit 4There is no borrow from bit 4.
Zero Flag (Z)
The Zero flag (Z) is set to 1 if the result generated by the execution of
certain instructions is 0. For 8-bit arithmetic and logical operations, the Z flag is set to 1 if
the resulting byte in the accumulator is 0. If the byte is not 0, the Z flag is reset to 0.
17
For compare instructions, the Z flag is set to 1 if the value in the
accumulator is the same as the data it is being compared against. When testing a bit in a
register or memory location, the Z flag contains the
complemented state of the indicated bit (see the
BIT b, r
instruction.
When inputting or outputting a byte between a memory location and an I/O device (for
example,
INI, IND, OUTI
and
OUTD
), the B register is decremented. If the result of this
decrement is 0 (that is, B–1 = 0), then the Z flag is set to 1. Otherwise, the Z flag is reset
(cleared to 0). Also, for byte inputs from I/O devices using
IN r,(C)
, the Z flag is set to 1 to
indicate a zero-byte input.
Sign Flag (S)
The Sign flag stores the state of the most significant bit of the
accumulator (bit 7). When the CPU performs arithmetic operations on signed numbers,
binary two’s-complement notation is used to represent and process numerical information.
A positive number is identified by a 0 in bit 7. A negative number is identified by a 1.
The binary equivalent of the magnitude of a positive number is stored in bits 0–6 for a
total range of 0–127. A negative number is represented by the two’s-complement of the
equivalent positive number. The total range for negative numbers is –1 to –128.
When inputting a byte from an I/O device to a register,
IN r,(C)
, the S flag indicates either
positive (S = 0) or negative (S = 1) data.
UM007715-0415 Registers and Bit Flags
Memory Mode Switching
ADL Mode and Z80 Mode
The CPU is capable of easily switching between the two available memory modes (ADL
mode and Z80 mode). There are two types of mode changes available to the CPU: persistent and single-instruction. For example, persistent mode switches allow the CPU to operate indefinitely in ADL mode, then switch to Z80 mode to run a section of Z80 code, and
then return to ADL mode. Conversely, single-instruction mode changes allow certain
instructions to operate using either addressing mode without making a persistent change to
the mode.
Memory Mode Compiler Directives
eZ80® CPU
User Manual
18
In the Zilog ZMASM/ZDS assembler, the application code is assembled for a given state
of the ADL mode bit by placing one of the two following compiler directives at the top of
the code:
.ASSUME ADL = 1
.ASSUME ADL = 0
These compiler directives indicate that either ADL MEMORY mode (ADL = 1) or Z80
MEMORY mode (ADL = 0) is the default memory mode for the code being currently compiled. The code developer is responsible for ensuring that this source file setting matches
the state of the hardware ADL mode bit when the code is executed.
Opcode Suffixes for Memory Mode Control
When developing application code for CPU applications, care must be taken when manipulating the ADL and Z80 memory modes. Special opcode suffixes are added to the
instruction set to assist with memory mode switching operations. There are four individual
suffixes available for use:
many instructions to indicate that a memory mode change or an exception to standard
memory mode operation is being requested.
Even with the compiler directives described in the section Memory Mode Compiler
Directives on page 18, the code developer must still employ these opcode suffixes to allow
exceptions to the default memory mode. For example, the opcode suffixes can be used to
allow persistent memory mode switching between ADL and Z80 modes. In addition, there
may be times when ADL mode code may fetch a 16-bit address generated from a section
of Z80 mode code. Alternatively, a section of Z80 mode code may retrieve immediate data
created by a section of ADL mode code. The memory mode control suffixes facilitate
these requirements.
.SIS, .SIL, .LIS
, and
.LIL
. These suffixes are appended to
UM007715-0415 Memory Mode Switching
eZ80® CPU
User Manual
19
Each of the four suffixes
.SIS, .SIL, .LIS
, and
.LIL
is composed of 2 parts that define the
operation in the control block and the data block within the CPU (see Figure 1 on page 2
and Tab l e 1 0 ). The first part of the suffix, either Short (
.S
within the data block of the CPU.
and .L control whether the overall operation of the
.S
) or Long (.L), directs operations
instruction and the internal registers should use 16 or 24 bits. The .S and .L portions of the
suffix also indicate if MBASE is used to define the 24-bit address. The last part of the suf-
.IS
or
.IL
fix, either
Short and Instruction Stream Long suffixes,
, directs the control block within the CPU. The Instruction Stream
.IS
and
.IL
, control whether a multibyte
immediate data or address value fetched during instruction execution is 2 or 3 bytes long
(for example, a
must know whether to fetch 3 bytes (
LD HL, Mmn
instruction versus a
Mmn
) or 2 bytes (mn) of data. The
LD HL, mn
instruction). The CPU
.IS
and
.IL
portions of the suffix tell the CPU the length of the instruction. If the length of the instruction
is unambiguous, the
.IS
and
.IL
suffixes yield no effect.
Table 10. Opcode Suffix Description
Suffix
Full Suffix
.SIS .S The CPU data block operates in Z80 mode using 16-bit
.SIL .S The CPU data block operates in Z80 mode using 16-bit
.LIS .L The CPU data block operates in ADL mode using 24-bit
.LIL .L The CPU data block operates in ADL mode using 24-bit
Components Description
registers. All addresses use MBASE.
.IS The CPU control block operates in Z80 mode. For
instructions with an ambiguous number of bytes, the .IS
suffix indicates that only 2 bytes of immediate data or
address must be fetched.
registers. All addresses use MBASE.
.IL The CPU control block operates in ADL mode. For
instructions with an ambiguous number of bytes, the .IL
suffix indicates that 3 bytes of immediate data or address
must be fetched.
registers. Addresses do not use MBASE.
.IS The CPU control block operates in Z80 mode. For
instructions with an ambiguous number of bytes, the .IS
suffix indicates that only 2 bytes of immediate data or
address must be fetched.
registers. Addresses do not use MBASE.
.IL The CPU control block operates in ADL mode. For
instructions with an ambiguous number of bytes, the .IL
suffix indicates that 3 bytes of immediate data or address
must be fetched.
UM007715-0415 Memory Mode Switching
Single-Instruction Memory Mode Changes
Often, the CPU must perform a single operation using the memory mode opposite from
that currently set by the ADL mode bit. The CPU is capable of changing between ADL
mode and Z80 mode for a single instruction. Certain CPU instructions can be appended
with the memory mode opcode suffixes
ticular memory mode is appropriate for this instruction only. The following three examples serve to make the suffix operation for single-instruction memory mode changes more
clear.
.SIS, .LIL, .LIS
, and
eZ80® CPU
User Manual
.SIL
to indicate that a par-
20
Suffix Example 1: LD HL, Mmn in
In
Z80 mode (ADL mode bit = 0), only two bytes of immediate data are normally fetched
Z80 Mode
and the upper byte of all CPU multibyte registers is undefined. Compare the operation of
the following lines of code to observe the effect of the opcode suffixes.
.ASSUME ADL = 0 ;Z80 mode operation is default.
LD HL, 3456h ;HL[23:0] ¨ {00h, 3456h}.
LD HL, 123456h ;Invalid–Z80 mode cannot load 24-;bit value.
LD.SIS HL, 3456h ;Same as LD HL, 3456, because
;ADL = 0. HL[23:0] ¨ {00h, 3456h}.
;.IS directs eZ80 to fetch only
;16 bits of data.
;.S forces upper byte of HL
;register to an undefined state.
LD.LIL HL, 123456h ;HL[23:0] ¨ 123456h.
;.IL directs eZ80 to fetch 24;bits of data.
;.L uses all 3 bytes of HL
;register.
LD.LIS HL, 3456h ;HL[23:0] ¨ {00h, 3456h}. .IS
;directs eZ80 to fetch only 16;bits of data. .L uses all 3 bytes
;of HL register.
LD.SIL HL, 123456h ;HL[23:0] ¨ {00h, 3456h}.
;.IL directs eZ80 to fetch 24 bits
;of data. .S forces upper byte of
;HL register to an undefined
;state because registers are
;defined to be only 16-bits.
In all cases of Suffix Example 1, the memory mode is unchanged after the operation, as it
remains in Z80 mode (ADL mode bit = 0) following completion of each instruction. How-
ever, during operation of the LD.LIS, LD.LIL, and LD.SIL instructions, all or parts of
.IL
the CPU function temporarily in ADL mode. The
.L
trol block, to operate in ADL mode. The
segment of the suffix forces the data block to
segment of the suffix forces the con-
operate in ADL mode.
UM007715-0415 Memory Mode Switching
eZ80® CPU
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Suffix Example 2: LD HL, Mmn in ADL Mode
Suffix Example 2 considers the same examples as in Suffix Example 1. However, for this
example, it is assumed that the part begins in ADL mode.
.ASSUME ADL = 1 ;ADL mode operation is default.
LD HL, 3456h ;HL[23:0] 003456h.
;3456h is valid 24-bit value.;Leading 0s are
assumed.
LD HL, 123456h ;HL[23:0] 123456h.
LD.SIS HL, 3456h ;HL[23:0] {00h, 3456h}.
;.IS directs the eZ80 to fetch
;only 16 bits of data.
;.S forces upper byte of the HL
;register to an undefined state.
LD.LIL HL, 123456h ;Same as LD HL, 123456h, because
;ADL = 1. HL[23:0] 123456h.
;.IL directs eZ80 to fetch 24
;bits of data.
;.L uses all 3 bytes of HL
;register.
LD.LIS HL, 3456h ;HL[23:0] {00h, 3456h}.
;.IS directs eZ80 to fetch only
;16 bits of data.
;.L uses all 3 bytes of HL
;register.
LD.SIL HL, 123456h ;HL[23:0] {00h, 3456h}.
;.IL directs eZ80 to fetch 24 bits
;of data.
.S forces upper byte of HL
;register to an undefined state.
21
From these two suffix examples, it can be seen that with the extensions applied, operation
is consistent regardless of the persistent memory mode in operation at the time. To
explain, a
rently operating in
LD.SIL
LD.LIS
, and
instruction operates in the same manner whether or not the CPU is cur-
Z80 mode or ADL mode. The same is also true for the
LD.LIL
instructions.
LD.SIS
,
Suffix Example 3: Risks with Using the .SIL Suffix
As Suffix Examples 1 and 2 demonstrate, special care must be taken when using the
.SIL
suffix. Wherever possible, the
the suffix (
.S
and
.IL
) are relevant. The
suffix should be avoided whenever both segments of
.IL
segment of the suffix indicates a long direct
.SIL
memory address or immediate data in the instruction stream and the CPU reads the 24-bit
.S
value. Because the
upper bits (23–16) that were read from the instruction are discarded (replaced with
is active, the internal registers are treated as 16-bit registers and the
00h).
Additionally, all memory WRITEs use Z80 mode employing MBASE. Therefore, the
upper byte of a 24-bit memory WRITE address is replaced by MBASE.
UM007715-0415 Memory Mode Switching
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