Zilog EZ80190 User Manual

An Company

eZ80190 Development Kit

User Manual

UM014108-0810

www.zilog.com

eZ80190 Development Kit

Caution:

User Manual

Safeguards

The following precautions must be observed when working with the devices described in this document.

Always use a grounding strap to prevent damage resulting from electrostatic discharge (ESD).

UM014108-0810

Introduction

The eZ80190 Development Kit provides a general-purpose platform for evaluating the capabilities and operation of ZiLOG’s eZ80190 microprocessor. The eZ8 0F9 1 Develo pmen t Kit features two primary boards: the eZ80Acclaim! arrangement provides a full development platform when using both boards. It can also provide a smaller-sized reference platform with the eZ80190 Module as a stand-alone development tool.

Kit Features

The key features of the eZ80190 Development Kit are:

eZ80190 Development Kit

User Manual

®

Development Platform and the eZ80190 Module. This

1

•

eZ80Acclaim!® Development Platform: – Up to 2 MB fast SRAM (12 ns access time) – Embedded Modem Socket with a U.S. Telephone Line Interface

2

C EEPROM

–I

2

–I

C Configuration Register – GPIO Port and Memory Headers – LEDs, including a 7 x 5 LED matrix – Jumpers – Two RS232 connectors—Console, Modem – 9 VDC Power Connector – RS485 connector – JTA G Debug Interface – ZiLOG Debug Interface (ZDI) – ZiLOG Developer Studio II and the eZ80

1. The eZ80Acclaim!® Development Platform’s RS485 and JTAG functions are not supported on the eZ80190 device.

UM014108-0810 Kit Features

1

®

C-Compiler

eZ80190 Development Kit User Manual

2

•

eZ80190 Module: – eZ80190 device operating at 50 MHz –1 MB Flash Memory – 512 KB SRAM – 10 BaseT Ethernet Interface – Real-Time Clock with Battery Back-Up

•

ZPAK II Debug Interface Tool

•

4-port 10 BaseT Ethernet hub

•

eZ80® Software and Documentation CD-ROM

Hardware Specifications

Table 1 lists the specifications of the eZ80Acclaim!® Development Platform.

Table 1. eZ80Acclaim!® Development Platform

Hardware Specifications

Operating Temperature: 20ºC ±5ºC

Operating Voltage: 9 VDC

eZ80190 Development Board Revision History

99C0858-001 Rev C or later:

10/20/03 - Updated layout and added reset fix. 05/30/06 - The following components are not populated on the board:

– U11: Triac, SCR Phone Line D0-214 – U26 and U27: IC RS485, XCVR, Low PWR, 8-SOIC – C3 and C4: CAP 1000pF Ceramic Disc 1KV – D1 and D3: Diode LED Amber 0805 SMT

Introduction UM014108-0810

eZ80190 Development Kit

User Manual

– T1: Inductor Ferrite Bead, 2x15 Turns – J1: Conn HDR/Pin 1x32 2mm socket – J5: Conn HDR/Pin 1x2 2mm socket – J9: Conn HDR/Pin 1x9 2mm socket – P4: Conn RJ14 Jack 6-Pos 4-CKT – P5: Conn 9-CKT Cir rt-angl PC Mount

eZ80Acclaim! Development Platform Overview

3

The purpose of the eZ80190 Development Kit is to provide the developer with a set of tools for evaluating the features of the eZ80

®

family of

devices, and to be able to develop a new application before building

®

application hardware. The eZ80Acclaim! designed to accept a number of application-specific modules and eZ80

Development Platform is

®

based add-on modules, including the eZ80190 Module, which features an Ethernet MAC, a Real-Time Clock, and the eZ80190 microprocessor with a fast Multiply-Accumulate unit.

When attached to the eZ80

®

Development Platform, the eZ80190 Module can operate in stand-alone mode with Flash memory, or interface via the ZPAK II debug interface tool to a host PC running ZiLOG Developer Studio II Integrated Development Environment (ZDS IDE) software. If the user’s eZ80

®

application demands Internet connectivity and/or a network connection, the eZ80190 microprocessor can serve web pages over a TCP/IP network, allowing easy system monitoring and control, and effortless processor code updates.

The address bus, data bus, and all eZ80190 Module control signals are

®

buffered on the eZ80Acclaim!

Development Platform to provide suffi-

cient drive capability.

®

A block diagram of the eZ80Acclaim!

Development Platform and the

eZ80190 Module is shown in Figure 1.

-

UM014108-0810 eZ80Acclaim! Development Platform Overview

eZ80190 Development Kit

GPIO

RS232-0

(Console)

RS485

LED

(7x5 matrix)

Push-

buttons

I C

EEPROM

I C

Register

Data Bus

SRAM

(512 KB

up to 2 MB)

Application Module Headers

2

Address Bus

GPIO

and Address Decoder

RS232-1 (Modem)

Embedded

Modem

Peripheral Device Signals

eZ80

Ethermet

Module

Interface

¤

eZ80190

Address Bus

Flash

(1 MB)

EMAC

SRAM

(512 KB)

RTC with

Battery

Data Bus

eZ80190

Module

User Manual

4

Figure 1. eZ80Acclaim!® Development Platform Block Diagram

with eZ80190 Module

Introduction UM014108-0810

eZ80190 Development Kit

User Manual

Figure 2 is a photographic representation of the eZ80Acclaim!® Development Platform segmented into its key blocks, as shown in the legend for the figure.

C

5

Key to blocks A–E:

A. Power and serial communications. B. eZ80190 Module interface. C. Debug interface.

Figure 2. The eZ80Acclaim!® Development Platform

A

B

D

E

D. Application module interfaces. E. General-Purpose Port and LED with address

decoder.

UM014108-0810 eZ80Acclaim! Development Platform Overview

eZ80190 Development Kit

A

C

B

D

User Manual

6

Figure 3 is a photographic representation of the eZ80190 Module segmented into its key blocks, as shown in the legend for the figure.

Note: Key to blocks A–D.

A. eZ80190 Module interfaces. B. eZ80190 CPU. C. 10/100 BaseT Ethernet Interface D. IrDA transceiver.

Figure 3. The eZ80190 Module

®

Development Platform and the

starting on

The structures of the eZ80Acclaim! eZ80190 Module are illustrated in the Schematic Diagrams page 61.

Introduction UM014108-0810

eZ80190 Development Kit

User Manual

eZ80Acclaim! Development Platform

This section describes the eZ80Acclaim!® Development Platform hardware, its key components and its interfaces, including detailed programmer interface information such as memory maps, register definitions, and interrupt usage.

Functional Description

The eZ80Acclaim!® Development Platform consists of seven major hardware blocks. These blocks, listed below, are diagrammed in Figure 4.

•

eZ80190 Module interface (2 male headers)

•

Power supply for the eZ80Acclaim!® Development Platform, the eZ80190 Module, and application modules

7

•

Application Module interface (2 female headers)

•

General-Purpose Port and LED matrix

•

RS232 serial communications ports

•

Embedded modem interface

•

I2C devices

UM014108-0810 Functional Description

eZ80190 Development Kit User Manual

8

Peripheral Device Signals

eZ80

Address Bus

Module

Interface

Data Bus

SRAM

(512 KB

RS232-0

(Console)

up to 2 MB)

RS232-1 (Modem)

Embedded

Modem

LED

(7x5 matrix)

Push-

GPIO

and Address Decoder

buttons

2

I C

EEPROM

2

I C

Register

Application Module Headers

Figure 4. Basic eZ80Acclaim!® Development Platform Block Diagram

eZ80Acclaim! Development Platform UM014108-0810

Physical Dimensions

The dimensions of the eZ80Acclaim!® Development Platform PCB is

177.8 mm x 182.9 mm. The overall height is 38.1 mm. See Figure 5.

43.2 mm

96.5 mm 55.9 mm

eZ80190 Development Kit

User Manual

9

175.3 mm

114.3 mm

157.5 mm

167.6 mm

5.1 mm

165.1 mm

5.1 mm

Figure 5. Physical Dimensions of the eZ80Acclaim!® Development Platform

UM014108-0810 Functional Description

eZ80190 Development Kit User Manual

10

Operational Description

The eZ80Acclaim!® Development Platform can accept any eZ80®-corebased modules, provided that the module interfaces correctly to the eZ80Acclaim! eZ80Acclaim! developer with a tool to evaluate the features of the eZ80190 device and to develop an application without building additional hardware.

eZ80190 Module Interface

®

Development Platform. The purpose of the

®

Development Platform is to provide the application

The eZ80190 Module interface provides easy an connection for the eZ80190 Module. This interface is designed to fit future eZ80

®

and user-developed modules using current eZ80

devices.

®

modules

The eZ80190 Module interface consists of two 50-pin receptacles, JP1 and JP2, which are described in the next pages.

Peripheral Bus Connector (JP1)

Figure 6 illustrates the pin layout of the Peripheral Bus Connector in the 50-pin header, located at position JP1 on the eZ80Acclaim!

®

Develop-

ment Platform. Table 2 describes the pins and their functions.

eZ80Acclaim! Development Platform UM014108-0810

eZ80190 Development Kit

A0

A2

A4

A6

A8

A10

CS2

D3

A17

A5

V3.3_EXT

GND_EXT

A7

A22

A1

A18 A1 6

GND_EXT

RD

D5

GND_EXT

A9

A23

CS1

A13

A11

D0

A19

D6

BUSACK

V3.3_EXT

CS0

INSTRD

A15

D1

A14

A3

D4

D7

IOREQ

A21

GND_EXT

MREQ

A12 A20

DIS_FLASH

BUSREQ

WR

D2

DIS_ETH

JP1

HEADER 25X2 IDC50

12 34 56 78 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

User Manual

11

UM014108-0810 Operational Description

Figure 6. eZ80Acclaim!® Development Platform

Peripheral Bus Connector Pin Configuration—JP1

eZ80190 Development Kit User Manual

12

Table 2. eZ80Acclaim!® Development Platform

Peripheral Bus Connector Identification—JP1

1

eZ801900100ZCO

Pin # Symbol Signal Direction Active Level

Signal

1 A6 Bidirectional Yes

2 A0 Bidirectional Yes

3 A10 Bidirectional Yes

4 A3 Bidirectional Yes

5GND

6V

DD

7 A8 Bidirectional Yes

8 A7 Bidirectional Yes

9 A13 Bidirectional Yes

10 A9 Bidirectional Yes

11 A15 Bidirectional Yes

12 A14 Bidirectional Yes

13 A18 Bidirectional Yes

2

14 A16 Bidirectional Yes

15 A19 Bidirectional Yes

Notes:

1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from this table. The entire interface is represented in the eZ80190 Module Schematic Diagrams pages 66 through 73.

2. The Power and Ground nets are connected directly to the eZ801900100ZCO device.

Additional note: external capacitive loads on RD be below 10 pF to satisfy the timing requirements for the eZ80 pulled to either V to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80F91’s Peripheral Power-Down Register.

or GND, depending on their inactive levels to reduce power consumption and

DD

, WR, IORQ, MREQ, D0–D7 and A0–A23 should

®

CPU. All unused inputs should be

on

eZ80Acclaim! Development Platform UM014108-0810

eZ80190 Development Kit

User Manual

13

Table 2. eZ80Acclaim!

Peripheral Bus Connector Identification—JP1

®

Development Platform

1

(Continued)

eZ801900100ZCO

Pin # Symbol Signal Direction Active Level

Signal

16 GND

17 A2 Bidirectional Yes

18 A1 Bidirectional Yes

19 A11 Bidirectional Yes

20 A12 Bidirectional Yes

21 A4 Bidirectional Yes

22 A20 Bidirectional Yes

23 A5 Bidirectional Yes

24 A17 Bidirectional Yes

25 DIS_ETH

26 EN_FLASH

Output Low No

27 A21 Bidirectional Yes

28 V

DD

29 A22 Bidirectional Yes

2

30 A23 Bidirectional Yes

Notes:

1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from this table. The entire interface is represented in the eZ80190 Module Schematic Diagrams pages 66 through 73.

2. The Power and Ground nets are connected directly to the eZ801900100ZCO device.

Additional note: external capacitive loads on RD be below 10 pF to satisfy the timing requirements for the eZ80 pulled to either V to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80F91’s Peripheral Power-Down Register.

or GND, depending on their inactive levels to reduce power consumption and

DD

, WR, IORQ, MREQ, D0–D7 and A0–A23 should

®

CPU. All unused inputs should be

on

UM014108-0810 Operational Description

eZ80190 Development Kit User Manual

14

Table 2. eZ80Acclaim!

Peripheral Bus Connector Identification—JP1

®

Development Platform

1

(Continued)

eZ801900100ZCO

Pin # Symbol Signal Direction Active Level

Signal

31 CS0 Input Low Yes

32 CS1

33 CS2

Input Low Yes

34 D0 Bidirectional Yes

35 D1 Bidirectional Yes

36 D2 Bidirectional No

37 D3 Bidirectional Yes

38 D4 Bidirectional Yes

39 D5 Bidirectional Yes

40 GND

41 D7 Bidirectional Yes

42 D6 Bidirectional Yes

43 MREQ

Bidirectional Low Yes

2

44 IORQ

Bidirectional Low Yes

45 GND

Notes:

1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from this table. The entire interface is represented in the eZ80190 Module Schematic Diagrams pages 66 through 73.

2. The Power and Ground nets are connected directly to the eZ801900100ZCO device.

Additional note: external capacitive loads on RD be below 10 pF to satisfy the timing requirements for the eZ80 pulled to either V to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80F91’s Peripheral Power-Down Register.

or GND, depending on their inactive levels to reduce power consumption and

DD

, WR, IORQ, MREQ, D0–D7 and A0–A23 should

®

CPU. All unused inputs should be

on

eZ80Acclaim! Development Platform UM014108-0810

eZ80190 Development Kit

®

Table 2. eZ80Acclaim!

Peripheral Bus Connector Identification—JP1

Development Platform

User Manual

1

(Continued)

15

Pin # Symbol Signal Direction Active Level

eZ801900100ZCO

Signal

2

46 RD Bidirectional Low Yes

47 WR

48 INSTRD

49 BUSACK

50 BUSREQ

Notes:

1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from this table. The entire interface is represented in the eZ80190 Module Schematic Diagrams pages 66 through 73.

2. The Power and Ground nets are connected directly to the eZ801900100ZCO device.

Additional note: external capacitive loads on RD be below 10 pF to satisfy the timing requirements for the eZ80 pulled to either VDD or GND, depending on their inactive levels to reduce power consumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80F91’s Peripheral Power-Down Register.

Bidirectional Low Yes

Input Low Yes

Input Pull-Up 10 K¾; Low Yes

Output Pull-Up 10 K¾; Low Yes

, WR, IORQ, MREQ, D0–D7 and A0–A23 should

®

CPU. All unused inputs should be

on

I/O Connector (JP2)

Figure 7 illustrates the pin layout of the eZ80Acclaim!® Development Platform’s I/O Con nector in the 50-pin header. The I/O Connector is located at

®

position JP2 on the eZ80Acclaim!

Development Platform. Table 3

describes the pins and their functions.

UM014108-0810 Operational Description

eZ80190 Development Kit

PB1

PB3

PB5

PB7

PC1

PC3

PC5

PC7

GND_EXT

PD1

PD3

PD5

PD7

DIS_IRDA

CS3

EZ80CLK

V3.3_EXT

FLASHWE

NMI

WAIT GND_EXT

PB0

PB2

PB4

PB6

GND_EXT

PC2

PC4

RTC_VDD

PD0

PD2

PD4

PD6

GND_EXT

IICSCL IICSDA

TDITDO TRIGOUT

TCK TMS

RESET

GND_EXT

HALT_SLP

V3.3_EXT

PC6

PC0

JP2

HEADER 25X2 IDC50

12 34 56 78 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

User Manual

16

eZ80Acclaim! Development Platform UM014108-0810

Figure 7. eZ80Acclaim!® Development Platform

I/O Connector Pin Configuration—JP2

eZ80190 Development Kit

User Manual

17

Table 3. eZ80Acclaim!® Development Platform

I/O Connector Identification—JP2

1

Pin # Symbol Signal Direction Active Level eZ80F91 Signal

1 PB7 Bidirectional Yes

2 PB6 Bidirectional Yes

3 PB5 Bidirectional Yes

4 PB4 Bidirectional Yes

5 PB3 Bidirectional Yes

6 PB2 Bidirectional Yes

7 PB1 Bidirectional Yes

8 PB0 Bidirectional Yes

9GND

10 PC7 Bidirectional Yes

11 PC6 Bidirectional Yes

12 PC5 Bidirectional Yes

13 PC4 Bidirectional Yes

14 PC3 Bidirectional Yes

2

15 PC2 Bidirectional Yes

16 PC1 Bidirectional Yes

17 PC0 Bidirectional Yes

18 PD7 Bidirectional Yes

Notes:

1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from this table. The entire interface is represented in the eZ80190 Module Schematic Diagrams pages 66 through 73.

2. The Power and Ground nets are connected directly to the eZ80F91 device.

on

UM014108-0810 Operational Description

eZ80190 Development Kit User Manual

18

Table 3. eZ80Acclaim!

I/O Connector Identification—JP2

®

Development Platform

1

(Continued)

Pin # Symbol Signal Direction Active Level eZ80F91 Signal

19 PD6 Bidirectional

20 GND

21 PD5 Bidirectional Yes

22 PD4 Bidirectional Yes

23 PD3 Bidirectional Yes

24 PD2 Bidirectional Yes

25 PD1 Bidirectional Yes

26 PD0 Bidirectional Yes

27 TDO Input Yes

28 TDI/ZDA Output Yes

29 GND

30 TRIGOUT Input High

31 TCK/ZCL Output Yes

2

32 TMS Output High Yes

33 RTC_V

DD

34 EZ80CLK Input Yes

35 SCL Bidirectional Yes

36 GND

Notes:

1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from this table. The entire interface is represented in the eZ80190 Module Schematic Diagrams pages 66 through 73.

2. The Power and Ground nets are connected directly to the eZ80F91 device.

on

eZ80Acclaim! Development Platform UM014108-0810

eZ80190 Development Kit

User Manual

19

Table 3. eZ80Acclaim!

I/O Connector Identification—JP2

®

Development Platform

1

(Continued)

Pin # Symbol Signal Direction Active Level eZ80F91 Signal

37 SDA Bidirectional Yes

38 GND

39 FlashWE

Output Low No

40 GND

41 CS3

42 DIS_IrDA

43 RESET

44 WAIT

45 V

DD

Input Low Yes

Output Low No

Bidirectional Low Yes

Output Pull-Up 10 K¾; Low Yes

46 GND

47 HALT_SLP

48 NMI

49 V

DD

Input Low Yes

Output Low Yes

50 Reserved

2

Notes:

1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from this table. The entire interface is represented in the eZ80190 Module Schematic Diagrams pages 66 through 73.

2. The Power and Ground nets are connected directly to the eZ80F91 device.

on

Almost all of the connectors’ signals are received directly from the CPU. Four input signals, in particular, offer options to the application developer by disabling certain functions of the eZ80190 Module.

These four inputs are:

UM014108-0810 Operational Description

eZ80190 Development Kit User Manual

20

•

These four signals are described below.

Disable Ethernet

Disable Ethernet (DIS_ETH) Enable Flash (EN_FLASH) Flash Write Enable (FlashWE) Disable IrDA (DIS_IrDA—not used)

When active Low, the DIS_ETH responding to CPU requests. As a result, additional input/output or memory devices can be used in the CS3 the Ethernet signal is listed in Appendix A

Disable Flash

When active Low , the EN_FLASH the eZ80190 Module.

Flash Write Enable

When active Low, the FlashWE the Flash boot block of the eZ80190 Module.

Disable IrDA

This signal does not perform a function on the eZ80190 Module. UART0 is always used with the RS232 interface on the eZ80Acclaim! ment Platform.

Application Module Interface

An Application Module Interface is provided to allow the user to add an application-specific module to the ZiLOG’s Thermostat Application Module (not provided in the kit) is an example application-specific module that demonstrates an HVAC control system.

output signal disables the EMAC from

address space. The logic that disables

on page 74.

input signal disables the Flash chip on

input signal enables Write operations on

®

Develop-

eZ80Acclaim!® Development Platform.

eZ80Acclaim! Development Platform UM014108-0810

eZ80190 Development Kit

To design an application module, the user should be familiar with the architecture and features of the eZ80190 Module currently installed. Implementing an application module via the Application Module Interface requires that the eZ80190 Module also be mounted on the Development Platform, because it (the eZ80190 Module) contains the eZ80190 microprocessor. To mount an application module, use the two male connectors J6 and J8.

Connector J6 carries the GPIO signals, and connector J8 carries memory and control signals. T ables 4 and 5 list the signals and functions related to each of these jumpers by pin. Power and ground signals are omitted for the sake of simplicity.

Table 4. GPIO Port Connector J6*

Signal Pin # Function Direction Notes

SCL 5 I

SDA 7 I

2

C Clock Bidirectional

2

C Data Bidirectional

User Manual

21

eZ80Acclaim!®

MOD_DIS

MWAIT

EM_D0 15 GPIO, Bit 0 Bidirectional

CS3

EM_D[7:1] 21,23,25,

Note: *All of the signals are driven directly by the CPU.

UM014108-0810 Operational Description

9 Modem Disable Input If a shunt is installed between

pins 6 and 9, the modem function on the eZ80Acclaim! Development Platform is disabled.

13 WAIT signal for

the CPU

17 Chip Select 3 of

the CPU

Port A, Bit [7:1] Bidirectional 27,29,31, 33

Input This signal does not perform a

function on the eZ80190 Module.

Output This signal is also present on

the J8.

®

eZ80190 Development Kit User Manual

22

Table 4. GPIO Port Connector J6* (Continued)

Signal Pin # Function Direction Notes

Reserved 35

PC[7:0] 39,41,43,

Port C, Bit [7:0] Bidirectional 45,47,49, 51,53

®

ID_[2:0] 6,8,10 eZ80Acclaim!

Output Development Platform ID

CON_DIS 12 Console Disable Input If a shunt is installed between

pins 12 and 14, the Console function on the eZ80Acclaim! Development Platform is disabled.

Reserved 16,18

PD[7:0] 22,24,26,

Port D, Bit[7:0] Bidirectional

28,30,32, 34,36

PB[7:0] 40,42,44,

Port B, Bit[7:0] Bidirectional

46,48,50, 52,54

Note: *All of the signals are driven directly by the CPU.

®

eZ80Acclaim! Development Platform UM014108-0810

eZ80190 Development Kit

User Manual

Table 5. CPU Bus Connector J8*

Signal Pin # Function Direction

A[0:7] 3–10 Address Bus, Low Byte Output

A[8:15] 13–20 Address Bus, High Byte Output

A[16:23] 23–30 Address Bus, Upper Byte Output

23

RD

RESET

BUSACK

NMI

D[0:7] 43–50 Data Bus Bidirectional

CS[0:3] 53–56 Chip Selects Output

MREQ

WR

INSTRD

BUSREQ

PHY 40 Clock output of the CPU Output

Note: *All of the signals except BUSACK and INSTRD are driven by lowvoltage CMOS technology (LVC) drivers.

33 Read Signal Output

35 Push Button Reset Output

37 CPU Bus Acknowledge Signal Output

39 Nonmaskable Interrupt Input

57 Memory Request Output

34 Write Signal Output

36 Instruction Fetch Output

38 CPU Bus Request signal Input

I/O Functionality

The

eZ80Acclaim!® Development Platform provides additional functional-

ity, featuring general-purpose port, an LED matrix, a modem reset, and two user triggers. These functions are memory-mapped with an address decoder based on the Generic Array Logic GAL22lV10D (U15) device manu factured by Lattice Semiconductor, and a bidirectional latch (U16). Additionally, U15 is used to decode addresses for access to the 7 x 5 LED matrix.

UM014108-0810 Operational Description

Zilog EZ80190 User Manual

Safeguards

Table of Contents

Introduction

Kit Features

Hardware Specifications

eZ80190 Development Board Revision History

eZ80Acclaim! Development Platform Overview

eZ80Acclaim! Development Platform

Functional Description

Physical Dimensions

Operational Description

eZ80190 Module Interface

Application Module Interface

I/O Functionality