Zilog EZ80190 User Manual

An Company

eZ80190 Development Kit

User Manual

UM014108-0810

Copyright ©2010 by Zilog, Inc. All rights reserved.

www.zilog.com

eZ80190 Development Kit

Caution:

User Manual

Safeguards

The following precautions must be observed when working with the
devices described in this document.

Always use a grounding strap to prevent damage resulting from
electrostatic discharge (ESD).

UM014108-0810

Table of Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Kit Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Hardware Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

eZ80190 Development Board Revision History . . . . . . . . . . . . . . . .2

eZ80Acclaim! Development Platform Overview . . . . . . . . . . . . . . . . . . .3

eZ80Acclaim! Development Platform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

eZ80190 Module Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Application Module Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

I/O Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Embedded Modem Socket Interface . . . . . . . . . . . . . . . . . . . . . . . .28

eZ80Acclaim!

LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Push Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

I2C Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

eZ80190 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Ethernet Media Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . .49

eZ80190 Module Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

®

Development Platform Memory . . . . . . . . . . . . . .31

eZ80190 Development Kit

User Manual

iii

UM014108-0810 Table of Contents

eZ80190 Development Kit
User Manual

iv

Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

I2C Bus Software Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Flash Loader Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Mounting the Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Changing the Power Supply Plug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

ZPAK II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

ZDI Target Interface Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Application Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

ZDS II. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Cannot Download Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

No Output on Console Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

IrDA Port Not Working . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Difference Between EMAC and IP Address . . . . . . . . . . . . . . . . . . . . . 58

Schematic Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Appendix A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

General Array Logic Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Reset Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Media Access Control (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

IP Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

®

eZ80

Development Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

eZ80190 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

U10 Address Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

U15 Address Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table of Contents UM014108-0810

Introduction

The eZ80190 Development Kit provides a general-purpose platform for
evaluating the capabilities and operation of ZiLOG’s eZ80190 micropro­cessor. The eZ8 0F9 1 Develo pmen t Kit features two primary boards: the
eZ80Acclaim!
arrangement provides a full development platform when using both
boards. It can also provide a smaller-sized reference platform with the
eZ80190 Module as a stand-alone development tool.

Kit Features

The key features of the eZ80190 Development Kit are:

eZ80190 Development Kit

User Manual

®

Development Platform and the eZ80190 Module. This

1

•

eZ80Acclaim!® Development Platform:
– Up to 2 MB fast SRAM (12 ns access time)
– Embedded Modem Socket with a U.S. Telephone Line Interface

2

C EEPROM

–I

2

–I

C Configuration Register
– GPIO Port and Memory Headers
– LEDs, including a 7 x 5 LED matrix
– Jumpers
– Two RS232 connectors—Console, Modem
– 9 VDC Power Connector
– RS485 connector
– JTA G Debug Interface
– ZiLOG Debug Interface (ZDI)
– ZiLOG Developer Studio II and the eZ80

1. The eZ80Acclaim!® Development Platform’s RS485 and JTAG functions are not supported on
the eZ80190 device.

UM014108-0810 Kit Features

1

1

®

C-Compiler

eZ80190 Development Kit
User Manual

2

•

eZ80190 Module:
– eZ80190 device operating at 50 MHz
–1 MB Flash Memory
– 512 KB SRAM
– 10 BaseT Ethernet Interface
– Real-Time Clock with Battery Back-Up

•

ZPAK II Debug Interface Tool

•

4-port 10 BaseT Ethernet hub

•

eZ80® Software and Documentation CD-ROM

Hardware Specifications

Table 1 lists the specifications of the eZ80Acclaim!® Development Plat­form.

Table 1. eZ80Acclaim!® Development Platform

Hardware Specifications

Operating Temperature: 20ºC ±5ºC

Operating Voltage: 9 VDC

eZ80190 Development Board Revision History

99C0858-001 Rev C or later:

10/20/03 - Updated layout and added reset fix.
05/30/06 - The following components are not populated on the board:

– U11: Triac, SCR Phone Line D0-214
– U26 and U27: IC RS485, XCVR, Low PWR, 8-SOIC
– C3 and C4: CAP 1000pF Ceramic Disc 1KV
– D1 and D3: Diode LED Amber 0805 SMT

Introduction UM014108-0810

eZ80190 Development Kit

User Manual

– T1: Inductor Ferrite Bead, 2x15 Turns
– J1: Conn HDR/Pin 1x32 2mm socket
– J5: Conn HDR/Pin 1x2 2mm socket
– J9: Conn HDR/Pin 1x9 2mm socket
– P4: Conn RJ14 Jack 6-Pos 4-CKT
– P5: Conn 9-CKT Cir rt-angl PC Mount

eZ80Acclaim! Development Platform Overview

3

The purpose of the eZ80190 Development Kit is to provide the developer
with a set of tools for evaluating the features of the eZ80

®

family of

devices, and to be able to develop a new application before building

®

application hardware. The eZ80Acclaim!
designed to accept a number of application-specific modules and eZ80

Development Platform is

®

based add-on modules, including the eZ80190 Module, which features an
Ethernet MAC, a Real-Time Clock, and the eZ80190 microprocessor with
a fast Multiply-Accumulate unit.

When attached to the eZ80

®

Development Platform, the eZ80190 Module
can operate in stand-alone mode with Flash memory, or interface via the
ZPAK II debug interface tool to a host PC running ZiLOG Developer Stu­dio II Integrated Development Environment (ZDS IDE) software. If the
user’s eZ80

®

application demands Internet connectivity and/or a network
connection, the eZ80190 microprocessor can serve web pages over a
TCP/IP network, allowing easy system monitoring and control, and
effortless processor code updates.

The address bus, data bus, and all eZ80190 Module control signals are

®

buffered on the eZ80Acclaim!

Development Platform to provide suffi-

cient drive capability.

®

A block diagram of the eZ80Acclaim!

Development Platform and the

eZ80190 Module is shown in Figure 1.

-

UM014108-0810 eZ80Acclaim! Development Platform Overview

eZ80190 Development Kit

GPIO

RS232-0

(Console)

RS485

LED

(7x5 matrix)

Push-

buttons

I C

EEPROM

I C

Register

Data Bus

SRAM

(512 KB

up to 2 MB)

Application Module Headers

2

2

Address Bus

GPIO

and
Address
Decoder

RS232-1
(Modem)

Embedded

Modem

Peripheral Device Signals

eZ80

Ethermet

Module

Interface

¤

eZ80190

Address Bus

Flash

(1 MB)

EMAC

SRAM

(512 KB)

RTC with

Battery

Data Bus

eZ80190

Module

User Manual

4

Figure 1. eZ80Acclaim!® Development Platform Block Diagram

with eZ80190 Module

Introduction UM014108-0810

eZ80190 Development Kit

User Manual

Figure 2 is a photographic representation of the eZ80Acclaim!® Develop­ment Platform segmented into its key blocks, as shown in the legend for
the figure.

C

5

Key to blocks A–E:

A. Power and serial communications.
B. eZ80190 Module interface.
C. Debug interface.

Figure 2. The eZ80Acclaim!® Development Platform

A

B

D

E

D. Application module interfaces.
E. General-Purpose Port and LED with address

decoder.

UM014108-0810 eZ80Acclaim! Development Platform Overview

eZ80190 Development Kit

A

A

C

B

D

User Manual

6

Figure 3 is a photographic representation of the eZ80190 Module seg­mented into its key blocks, as shown in the legend for the figure.

Note: Key to blocks A–D.

A. eZ80190 Module interfaces.
B. eZ80190 CPU.
C. 10/100 BaseT Ethernet Interface
D. IrDA transceiver.

Figure 3. The eZ80190 Module

®

Development Platform and the

starting on

The structures of the eZ80Acclaim!
eZ80190 Module are illustrated in the Schematic Diagrams
page 61.

Introduction UM014108-0810

eZ80190 Development Kit

User Manual

eZ80Acclaim! Development Platform

This section describes the eZ80Acclaim!® Development Platform hard­ware, its key components and its interfaces, including detailed program­mer interface information such as memory maps, register definitions, and
interrupt usage.

Functional Description

The eZ80Acclaim!® Development Platform consists of seven major hard­ware blocks. These blocks, listed below, are diagrammed in Figure 4.

•

eZ80190 Module interface (2 male headers)

•

Power supply for the eZ80Acclaim!® Development Platform, the
eZ80190 Module, and application modules

7

•

Application Module interface (2 female headers)

•

General-Purpose Port and LED matrix

•

RS232 serial communications ports

•

Embedded modem interface

•

I2C devices

UM014108-0810 Functional Description

eZ80190 Development Kit
User Manual

8

Peripheral Device Signals

eZ80

Address Bus

Module

Interface

Data Bus

SRAM

(512 KB

RS232-0

(Console)

up to 2 MB)

RS232-1
(Modem)

Embedded

Modem

LED

(7x5 matrix)

Push-

GPIO

and
Address
Decoder

buttons

2

I C

EEPROM

2

I C

Register

Application Module Headers

Figure 4. Basic eZ80Acclaim!® Development Platform Block Diagram

eZ80Acclaim! Development Platform UM014108-0810

Physical Dimensions

The dimensions of the eZ80Acclaim!® Development Platform PCB is

177.8 mm x 182.9 mm. The overall height is 38.1 mm. See Figure 5.

43.2 mm

96.5 mm 55.9 mm

eZ80190 Development Kit

User Manual

9

175.3 mm

114.3 mm

157.5 mm

167.6 mm

5.1 mm

165.1 mm

5.1 mm

Figure 5. Physical Dimensions of the eZ80Acclaim!® Development Platform

UM014108-0810 Functional Description

eZ80190 Development Kit
User Manual

10

Operational Description

The eZ80Acclaim!® Development Platform can accept any eZ80®-core­based modules, provided that the module interfaces correctly to the
eZ80Acclaim!
eZ80Acclaim!
developer with a tool to evaluate the features of the eZ80190 device and
to develop an application without building additional hardware.

eZ80190 Module Interface

®

Development Platform. The purpose of the

®

Development Platform is to provide the application

The eZ80190 Module interface provides easy an connection for the
eZ80190 Module. This interface is designed to fit future eZ80

®

and user-developed modules using current eZ80

devices.

®

modules

The eZ80190 Module interface consists of two 50-pin receptacles, JP1
and JP2, which are described in the next pages.

Peripheral Bus Connector (JP1)

Figure 6 illustrates the pin layout of the Peripheral Bus Connector in the
50-pin header, located at position JP1 on the eZ80Acclaim!

®

Develop-

ment Platform. Table 2 describes the pins and their functions.

eZ80Acclaim! Development Platform UM014108-0810

eZ80190 Development Kit

A0

A2

A4

A6

A8

A10

CS2

D3

A17

A5

V3.3_EXT

GND_EXT

A7

A22

A1

A18 A1 6

GND_EXT

RD

D5

GND_EXT

A9

A23

CS1

A13

A11

D0

A19

D6

BUSACK

V3.3_EXT

CS0

INSTRD

A15

D1

A14

A3

D4

D7

IOREQ

A21

GND_EXT

MREQ

A12
A20

DIS_FLASH

BUSREQ

WR

D2

DIS_ETH

JP1

HEADER 25X2
IDC50

12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50

User Manual

11

UM014108-0810 Operational Description

Figure 6. eZ80Acclaim!® Development Platform

Peripheral Bus Connector Pin Configuration—JP1

eZ80190 Development Kit
User Manual

12

Table 2. eZ80Acclaim!® Development Platform

Peripheral Bus Connector Identification—JP1

1

eZ801900100ZCO

Pin # Symbol Signal Direction Active Level

Signal

1 A6 Bidirectional Yes

2 A0 Bidirectional Yes

3 A10 Bidirectional Yes

4 A3 Bidirectional Yes

5GND

6V

DD

7 A8 Bidirectional Yes

8 A7 Bidirectional Yes

9 A13 Bidirectional Yes

10 A9 Bidirectional Yes

11 A15 Bidirectional Yes

12 A14 Bidirectional Yes

13 A18 Bidirectional Yes

2

14 A16 Bidirectional Yes

15 A19 Bidirectional Yes

Notes:

1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from
this table. The entire interface is represented in the eZ80190 Module Schematic Diagrams
pages 66 through 73.

2. The Power and Ground nets are connected directly to the eZ801900100ZCO device.

Additional note: external capacitive loads on RD
be below 10 pF to satisfy the timing requirements for the eZ80
pulled to either V
to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in
the eZ80F91’s Peripheral Power-Down Register.

or GND, depending on their inactive levels to reduce power consumption and

DD

, WR, IORQ, MREQ, D0–D7 and A0–A23 should

®

CPU. All unused inputs should be

on

eZ80Acclaim! Development Platform UM014108-0810

eZ80190 Development Kit

User Manual

13

Table 2. eZ80Acclaim!

Peripheral Bus Connector Identification—JP1

®

Development Platform

1

(Continued)

eZ801900100ZCO

Pin # Symbol Signal Direction Active Level

Signal

16 GND

17 A2 Bidirectional Yes

18 A1 Bidirectional Yes

19 A11 Bidirectional Yes

20 A12 Bidirectional Yes

21 A4 Bidirectional Yes

22 A20 Bidirectional Yes

23 A5 Bidirectional Yes

24 A17 Bidirectional Yes

25 DIS_ETH

26 EN_FLASH

Output Low No

Output Low No

27 A21 Bidirectional Yes

28 V

DD

29 A22 Bidirectional Yes

2

30 A23 Bidirectional Yes

Notes:

1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from
this table. The entire interface is represented in the eZ80190 Module Schematic Diagrams
pages 66 through 73.

2. The Power and Ground nets are connected directly to the eZ801900100ZCO device.

Additional note: external capacitive loads on RD
be below 10 pF to satisfy the timing requirements for the eZ80
pulled to either V
to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in
the eZ80F91’s Peripheral Power-Down Register.

or GND, depending on their inactive levels to reduce power consumption and

DD

, WR, IORQ, MREQ, D0–D7 and A0–A23 should

®

CPU. All unused inputs should be

on

UM014108-0810 Operational Description

eZ80190 Development Kit
User Manual

14

Table 2. eZ80Acclaim!

Peripheral Bus Connector Identification—JP1

®

Development Platform

1

(Continued)

eZ801900100ZCO

Pin # Symbol Signal Direction Active Level

Signal

31 CS0 Input Low Yes

32 CS1

33 CS2

Input Low Yes

Input Low Yes

34 D0 Bidirectional Yes

35 D1 Bidirectional Yes

36 D2 Bidirectional No

37 D3 Bidirectional Yes

38 D4 Bidirectional Yes

39 D5 Bidirectional Yes

40 GND

41 D7 Bidirectional Yes

42 D6 Bidirectional Yes

43 MREQ

Bidirectional Low Yes

2

44 IORQ

Bidirectional Low Yes

45 GND

Notes:

1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from
this table. The entire interface is represented in the eZ80190 Module Schematic Diagrams
pages 66 through 73.

2. The Power and Ground nets are connected directly to the eZ801900100ZCO device.

Additional note: external capacitive loads on RD
be below 10 pF to satisfy the timing requirements for the eZ80
pulled to either V
to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in
the eZ80F91’s Peripheral Power-Down Register.

or GND, depending on their inactive levels to reduce power consumption and

DD

, WR, IORQ, MREQ, D0–D7 and A0–A23 should

®

CPU. All unused inputs should be

on

eZ80Acclaim! Development Platform UM014108-0810

eZ80190 Development Kit

®

Table 2. eZ80Acclaim!

Peripheral Bus Connector Identification—JP1

Development Platform

User Manual

1

(Continued)

15

Pin # Symbol Signal Direction Active Level

eZ801900100ZCO

Signal

2

46 RD Bidirectional Low Yes

47 WR

48 INSTRD

49 BUSACK

50 BUSREQ

Notes:

1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from
this table. The entire interface is represented in the eZ80190 Module Schematic Diagrams
pages 66 through 73.

2. The Power and Ground nets are connected directly to the eZ801900100ZCO device.

Additional note: external capacitive loads on RD
be below 10 pF to satisfy the timing requirements for the eZ80
pulled to either VDD or GND, depending on their inactive levels to reduce power consumption and
to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in
the eZ80F91’s Peripheral Power-Down Register.

Bidirectional Low Yes

Input Low Yes

Input Pull-Up 10 K¾; Low Yes

Output Pull-Up 10 K¾; Low Yes

, WR, IORQ, MREQ, D0–D7 and A0–A23 should

®

CPU. All unused inputs should be

on

I/O Connector (JP2)

Figure 7 illustrates the pin layout of the eZ80Acclaim!® Development Plat­form’s I/O Con nector in the 50-pin header. The I/O Connector is located at

®

position JP2 on the eZ80Acclaim!

Development Platform. Table 3

describes the pins and their functions.

UM014108-0810 Operational Description

eZ80190 Development Kit

PB1

PB3

PB5

PB7

PC1

PC3

PC5

PC7

GND_EXT

PD1

PD3

PD5

PD7

DIS_IRDA

CS3

EZ80CLK

V3.3_EXT

FLASHWE

NMI

WAIT
GND_EXT

PB0

PB2

PB4

PB6

GND_EXT

PC2

PC4

RTC_VDD

PD0

PD2

PD4

PD6

GND_EXT

IICSCL
IICSDA

TDITDO
TRIGOUT

TCK TMS

RESET

GND_EXT

HALT_SLP

V3.3_EXT

PC6

PC0

JP2

HEADER 25X2
IDC50

12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50

User Manual

16

eZ80Acclaim! Development Platform UM014108-0810

Figure 7. eZ80Acclaim!® Development Platform

I/O Connector Pin Configuration—JP2

eZ80190 Development Kit

User Manual

17

Table 3. eZ80Acclaim!® Development Platform

I/O Connector Identification—JP2

1

Pin # Symbol Signal Direction Active Level eZ80F91 Signal

1 PB7 Bidirectional Yes

2 PB6 Bidirectional Yes

3 PB5 Bidirectional Yes

4 PB4 Bidirectional Yes

5 PB3 Bidirectional Yes

6 PB2 Bidirectional Yes

7 PB1 Bidirectional Yes

8 PB0 Bidirectional Yes

9GND

10 PC7 Bidirectional Yes

11 PC6 Bidirectional Yes

12 PC5 Bidirectional Yes

13 PC4 Bidirectional Yes

14 PC3 Bidirectional Yes

2

15 PC2 Bidirectional Yes

16 PC1 Bidirectional Yes

17 PC0 Bidirectional Yes

18 PD7 Bidirectional Yes

Notes:

1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from
this table. The entire interface is represented in the eZ80190 Module Schematic Diagrams
pages 66 through 73.

2. The Power and Ground nets are connected directly to the eZ80F91 device.

on

UM014108-0810 Operational Description

eZ80190 Development Kit
User Manual

18

Table 3. eZ80Acclaim!

I/O Connector Identification—JP2

®

Development Platform

1

(Continued)

Pin # Symbol Signal Direction Active Level eZ80F91 Signal

19 PD6 Bidirectional

20 GND

21 PD5 Bidirectional Yes

22 PD4 Bidirectional Yes

23 PD3 Bidirectional Yes

24 PD2 Bidirectional Yes

25 PD1 Bidirectional Yes

26 PD0 Bidirectional Yes

27 TDO Input Yes

28 TDI/ZDA Output Yes

29 GND

30 TRIGOUT Input High

31 TCK/ZCL Output Yes

2

32 TMS Output High Yes

33 RTC_V

DD

34 EZ80CLK Input Yes

35 SCL Bidirectional Yes

36 GND

Notes:

1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from
this table. The entire interface is represented in the eZ80190 Module Schematic Diagrams
pages 66 through 73.

2. The Power and Ground nets are connected directly to the eZ80F91 device.

on

eZ80Acclaim! Development Platform UM014108-0810

eZ80190 Development Kit

User Manual

19

Table 3. eZ80Acclaim!

I/O Connector Identification—JP2

®

Development Platform

1

(Continued)

Pin # Symbol Signal Direction Active Level eZ80F91 Signal

37 SDA Bidirectional Yes

38 GND

39 FlashWE

Output Low No

40 GND

41 CS3

42 DIS_IrDA

43 RESET

44 WAIT

45 V

DD

Input Low Yes

Output Low No

Bidirectional Low Yes

Output Pull-Up 10 K¾; Low Yes

46 GND

47 HALT_SLP

48 NMI

49 V

DD

Input Low Yes

Output Low Yes

50 Reserved

2

Notes:

1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from
this table. The entire interface is represented in the eZ80190 Module Schematic Diagrams
pages 66 through 73.

2. The Power and Ground nets are connected directly to the eZ80F91 device.

on

Almost all of the connectors’ signals are received directly from the CPU.
Four input signals, in particular, offer options to the application developer
by disabling certain functions of the eZ80190 Module.

These four inputs are:

UM014108-0810 Operational Description

eZ80190 Development Kit
User Manual

20

•

•

•

•

These four signals are described below.

Disable Ethernet

Disable Ethernet (DIS_ETH)
Enable Flash (EN_FLASH)
Flash Write Enable (FlashWE)
Disable IrDA (DIS_IrDA—not used)

When active Low, the DIS_ETH
responding to CPU requests. As a result, additional input/output or mem­ory devices can be used in the CS3
the Ethernet signal is listed in Appendix A

Disable Flash

When active Low , the EN_FLASH
the eZ80190 Module.

Flash Write Enable

When active Low, the FlashWE
the Flash boot block of the eZ80190 Module.

Disable IrDA

This signal does not perform a function on the eZ80190 Module. UART0
is always used with the RS232 interface on the eZ80Acclaim!
ment Platform.

Application Module Interface

An Application Module Interface is provided to allow the user to add an
application-specific module to the
ZiLOG’s Thermostat Application Module (not provided in the kit) is an
example application-specific module that demonstrates an HVAC control
system.

output signal disables the EMAC from

address space. The logic that disables

on page 74.

input signal disables the Flash chip on

input signal enables Write operations on

®

Develop-

eZ80Acclaim!® Development Platform.

eZ80Acclaim! Development Platform UM014108-0810

eZ80190 Development Kit

To design an application module, the user should be familiar with the
architecture and features of the eZ80190 Module currently installed.
Implementing an application module via the Application Module Interface
requires that the eZ80190 Module also be mounted on the
Development Platform, because it (the eZ80190 Module) contains the
eZ80190 microprocessor. To mount an application module, use the two
male connectors J6 and J8.

Connector J6 carries the GPIO signals, and connector J8 carries memory
and control signals. T ables 4 and 5 list the signals and functions related to
each of these jumpers by pin. Power and ground signals are omitted for
the sake of simplicity.

Table 4. GPIO Port Connector J6*

Signal Pin # Function Direction Notes

SCL 5 I

SDA 7 I

2

C Clock Bidirectional

2

C Data Bidirectional

User Manual

21

eZ80Acclaim!®

MOD_DIS

MWAIT

EM_D0 15 GPIO, Bit 0 Bidirectional

CS3

EM_D[7:1] 21,23,25,

Note: *All of the signals are driven directly by the CPU.

UM014108-0810 Operational Description

9 Modem Disable Input If a shunt is installed between

pins 6 and 9, the modem
function on the eZ80Acclaim!
Development Platform is
disabled.

13 WAIT signal for

the CPU

17 Chip Select 3 of

the CPU

Port A, Bit [7:1] Bidirectional
27,29,31,
33

Input This signal does not perform a

function on the eZ80190
Module.

Output This signal is also present on

the J8.

®

eZ80190 Development Kit
User Manual

22

Table 4. GPIO Port Connector J6* (Continued)

Signal Pin # Function Direction Notes

Reserved 35

PC[7:0] 39,41,43,

Port C, Bit [7:0] Bidirectional
45,47,49,
51,53

®

ID_[2:0] 6,8,10 eZ80Acclaim!

Output
Development
Platform ID

CON_DIS 12 Console Disable Input If a shunt is installed between

pins 12 and 14, the Console
function on the eZ80Acclaim!
Development Platform is
disabled.

Reserved 16,18

PD[7:0] 22,24,26,

Port D, Bit[7:0] Bidirectional

28,30,32,
34,36

PB[7:0] 40,42,44,

Port B, Bit[7:0] Bidirectional

46,48,50,
52,54

Note: *All of the signals are driven directly by the CPU.

®

eZ80Acclaim! Development Platform UM014108-0810

eZ80190 Development Kit

User Manual

Table 5. CPU Bus Connector J8*

Signal Pin # Function Direction

A[0:7] 3–10 Address Bus, Low Byte Output

A[8:15] 13–20 Address Bus, High Byte Output

A[16:23] 23–30 Address Bus, Upper Byte Output

23

RD

RESET

BUSACK

NMI

D[0:7] 43–50 Data Bus Bidirectional

CS[0:3] 53–56 Chip Selects Output

MREQ

WR

INSTRD

BUSREQ

PHY 40 Clock output of the CPU Output

Note: *All of the signals except BUSACK and INSTRD are driven by low­voltage CMOS technology (LVC) drivers.

33 Read Signal Output

35 Push Button Reset Output

37 CPU Bus Acknowledge Signal Output

39 Nonmaskable Interrupt Input

57 Memory Request Output

34 Write Signal Output

36 Instruction Fetch Output

38 CPU Bus Request signal Input

I/O Functionality

The

eZ80Acclaim!® Development Platform provides additional functional-

ity, featuring general-purpose port, an LED matrix, a modem reset, and two
user triggers. These functions are memory-mapped with an address decoder
based on the Generic Array Logic GAL22lV10D (U15) device manu fac­tured by Lattice Semiconductor, and a bidirectional latch (U16). Addition­ally, U15 is used to decode addresses for access to the 7 x 5 LED matrix.

UM014108-0810 Operational Description

eZ80190 Development Kit
User Manual

24

T able 6 lists the memory map addresses to registers that allow access to the
above functions. The register at address
pose port output control and LED anode register functions. The register at
address
modem reset, and user triggers. Address
pose port data.

Address Register Function Access

800000h

800001h

Table 6. LED and Port Emulation Addresses

controls the register functions for the LED cathode,

800002h

controls general-pur-

controls general-pur-

800000h LED Anode/General-Purpose Port

Output Control

800001h LED Cathode/Modem/Trig WR

800002h General-Purpose Port Data RD/WR

WR

General-Purpose Port

The general-purpose port is emulated with the use of the GPIO Output
Control Register and the GPIO Data Register. If bit 7 in the GPIO Output
Control Register is 1, all of the lines on the general-purpose port are con­figured as inputs. If this bit is 0, all of the lines on the general-purpose
port are configured as outputs. Table 7 lists the multiple functions of the
register.

Table 7. LED Anode/General-Purpose Port Output Control Register

Bit #

Function

Anode Col 1 X

Anode Col 2 X

Anode Col 3 X

Anode Col 4 X

76543210

eZ80Acclaim! Development Platform UM014108-0810

eZ80190 Development Kit

Caution:

User Manual

Table 7. LED Anode/General-Purpose Port Output Control Register (C ontinued)

Bit #

25

Function

Anode Col 5 X

Anode Col 6 X

Anode Col 6 X

GPIO Output X

76543210

The GPIO Data Register receives inputs or provides outputs for each of
the seven general-purpose port lines, depending on the configuration o f
the port. See Table 8.

Table 8. General-Purpose Port Data Register

Bit #

Function

GPIO D0 X

GPIO D1 X

GPIO D2 X

GPIO D3 X

GPIO D4 X

GPIO D5 X

GPIO D6 X

GPIO D7 X

76543210

Reading from the general-purpose port can damage the drivers
used for the general-purpose port and memory. The port can,
however, be used for writing data.

UM014108-0810 Operational Description

eZ80190 Development Kit
User Manual

26

LED Matrix

The one 7 x 5 LED matrix device on the eZ80Acclaim!
Platform is a memory-mapped device that can be used to display informa­tion, such as programmed alphanumeric characters. For example, the
LED display sample program that is shipped with this kit displays the
alphanumeric message:

To illuminate any LED in the matrix, its respective anode bit must be set
to 1 and its corresponding cathode bit must be set to 0.

Bits 0–6 in Table 7 are LED anode bits. They must be set High (1) and
their corresponding cathode bits, bits 0–4 in Table 9, must be set Low (0)
to illuminate each of the LED’s, respectively.

Bit 7 in Table 7 does not carry any significance within the LED matrix. It
is used for the general-purpose port as a control bit.

eZ80

®

Development

Table 9 indicates the multiple register functions of the LED cathode,
modem, and triggers. This table shows the bit configuration for each cath­ode bit. Bits 5, 6, and 7 do not carry any significance within the LED
matrix. These three bits are control bits for the modem reset, Trig1, and
Trig2 functions, respectively.

Table 9. Bit Access to the LED Cathode, Modem, and Triggers

Bit #

Function

Cathode Row 5 X

Cathode Row 4 X

Cathode Row 3 X

Cathode Row 2 X

eZ80Acclaim! Development Platform UM014108-0810

76543210

eZ80190 Development Kit

User Manual

Table 9. Bit Access to the LED Cathode, Modem, and Triggers (Continued)

Bit #

Function

Cathode Row 1 X

MRESET X

Trig 1 X

Trig 2 X

76543210

An LED display sample program is shipped with the eZ80190 Develop­ment Kit. Please refer to the eZ80190 Development Kit Quick S tart Guide
(QS0004) or to the Tutorial section in the ZiLOG Developer Studio II—
eZ80Acclaim! User Manual (UM0144).

27

Modem Reset

The Modem Reset signal, MRESET, is used to reset an optional socket
modem. This signal is controlled by bit 5 in the register shown in

Table 9.
The MRESET signal is available at the embedded modem socket inter­face (J9, Pin 1).

Setting this bit Low p laces the optional socket modem into
a reset state. The user must pull this bit High again to enable the socket
modem. Reference the appropriate documentation for the socket modem to
reset timing requirements. More information about this signal is provided
in the next section.

User Triggers

Two general-purpose trigger output pins are provided on the
eZ80Acclaim!

®

Development Platform. Labeled J21 (Trig2) and J22
(Trig1), these pins allow the user a way to trigger external equipment to
aid in the debug of the system. See Figure 8 for trigger pin details.

UM014108-0810 Operational Description

eZ80190 Development Kit

J21

Trig2

J22

Trig1

Ground

Trigger output

User Manual

28

Bits 6 and 7 in T able 9 are the control bits for the user triggers. If either bit
is a 1, the corresponding Trig1 and T rig2 signals are driven High. If either
bit is 0, the corresponding Trig1 and Trig2 signals are driven Low.

Embedded Modem Socket Interface

Figure 8. Trigger Pins J21 and J22

The eZ80Acclaim!® Development Platform
optional 56K modem (a modem is not included in the kit).
modem for this

eZ80190 Development Kit

features a socket for an

The tested

is a Conexant socket modem,
part number SF56D/SP. Information about this modem and its interface is
available in the SmartSCM SocketModem data sheet (Doc. No. 101522D)
from

www .conexant.com

.

Connectors J1, J5, and J9 provide connection capability. The modem
socket interface provided by these three connectors is shown in Figure 9.
Tables 10 through 12 identify the pins for each connector. The embedded
modem utilizes UART1, which is available via the Port C pins.

eZ80Acclaim! Development Platform UM014108-0810

eZ80190 Development Kit

J5

J9

J1

12

4

24

25

26

27

28

29

30

31

32

2

1

3

6

7

8

9

User Manual

29

Pin Symbol Description

1 M-TIP Telephone Line Interface—TIP.

2 M-RING Telephone Line Interface—RING.

Pin Symbol Description

1 MRESET Reset, active Low, 50–100 ms. Closure to GND for reset.

3 GND Ground.

UM014108-0810 Operational Description

Figure 9. Embedded Modem Socket Interface—J1, J5, and J9

Table 10. Connector J5

Table 11. Connector J 9

eZ80190 Development Kit
User Manual

30

Table 11. Connector J9

6 D1 DCD indicator; can drive an LED anode without additional circuitry.

7 D2 RxD indicator; can drive an LED anode without additional circuitry.

8 D3 DTR indicator; can drive an LED anode without additional circuitry.

9 D4 TxD indicator; can drive an LED anode without additional circuitry.

Table 12. Connector J1

Pin Symbol Description

2 MOD_DIS Modem disable, active Low.

4V

24 GND Ground.

25 PC4_DTR1 DTR interface; TTL levels.

26 PC6_DCD1 DCD interface; TTL levels.

27 PC3_CTS1 CTS interface; TTL levels.

28 PC5_DSR1 DSR interface; TTL levels.

29 PC7_RI1 Ring Indicator interface; TTL levels.

30 PC0_TXD1 TxD interface; TTL levels.

31 PC1_RXD1 RxD interface; TTL levels.

32 PC2_RTS1 RTS interface; TTL levels.

CC

+5 VDC or +3.3 VDC input.

Components P4, T1, C3, C4, and U11 provide the phone line interface to
the modem. On the eZ80Acclaim!

®

Development Platform, LEDs D1,

D2, D3, and D4 function as status indicators for this optional modem.
The phone line connection for the modem is for the United States only.

Connecting the modem outside of the U.S. requires modification.

eZ80Acclaim! Development Platform UM014108-0810

eZ80190 Development Kit

eZ80Acclaim!® Development Platform Memory

Memory space on the eZ80Acclaim!® Development Platform consists of
onboard SRAM and additional footprints.

Onboard SRAM

The eZ80Acclaim!
U20. This SRAM provides the basic memory requirement for small appli­cations development. This SRAM is in the address range

BFFFFFh.

Additional SRAM

The amount of eZ80Acclaim!
extended if required by adding SRAM devices. U19, U18, and U17 pro­vide this capability. However, the user should be aware that additional
SRAM must be installed in the following order:

®

Development Platform features 512 KB SRAM at

®

Development Platform memory can be

User Manual

31

B80000h–

1. U19, address range

B00000h–B7FFFFh

2. U18, address range A80000h–AFFFFFh

3. U17, address range A00000h–A7FFFFh
If SRAM memory is installed in a different order than the above

sequence, SRAM will not be contiguous unless the user is able to change
the address decoder, U10. Memory access decoding is performed by this
address decoder, implemented in the Generic Array Logic device,
GAL22LV10D (U10).

Memory Map

A memory map of the eZ80® CPU is illustrated in Figure 10. Flash mem­ory and SRAM on the eZ80190 Module are addressed when
are active Low. SRAM on the
addressed when

UM014108-0810 Operational Description

CS2

is active Low.

eZ80Acclaim!® Development Platform is

CS0

and

CS1

eZ80190 Development Kit

Note:

User Manual

32

The eZ80190 MCU features 8 KB of internal SRAM in the address range

E000h–FFFFh
DFFFh

space in 64 KB steps (
included in the eZ80190 Development Kit assumes internal RAM in the
range
address range assigned to Flash memory (

The Ethernet controller, located on the eZ80190 Modu le, is mapped as an
I/O device at address

and 1 KB of MACC RAM in the address range

DC00h

. Internal RAM can be mapped anywhere in the 16 MB address

E000h–FFFFh

DC00h–FFFFh

for the interrupt vector table. This range overlaps the

300h. It uses CS3.

to

DC00h–FFFFFFh

CS0

) on the eZ80190 Module.

). The software

–

eZ80Acclaim! Development Platform UM014108-0810

eZ80190 Development Kit

FFFFFFh

DFFFFFh

C7FFFFh

C00000h

CS1

CS2

CS0 (8 MB)

Main Board
SRAM (512 KB)

1 MB on
Ethernet Module

Ethernet Module
SRAM

BFFFFFh

B80000h

80FFFFh

800000h

7FFFFFh

400000h

3FFFFFh

Flash Memory

Expansion Module

Flash Memory up to 4 MB

Expansion SRAM Memory

up to 1.5 MB

SRAM Memory

up to 2 MB

000000h

0FFFFFh

Up to 4 MB

Up to 4 MB

User Manual

33

UM014108-0810 Operational Description

Figure 10. Memory Map of the eZ80Acclaim!® Development Platform

and eZ80190 Module

The LED matrix and the general-purpose port circuitry are mapped in the
address range

800000h–80ffffh. The CS2 chip select should be driven

Low to select the LED matrix or general-purpose port.

eZ80190 Development Kit
User Manual

34

LEDs

As stated earlier, LEDs D1, D2, D3, and D4 function as status indicators
for an optional modem. This section describes each LED and the LED
matrix device.

Data Carrier Detect

The Data Carrier Detect (DCD) signal at D1 indicates that a good carrier
signal is being received from the remote modem.

RX

The RX signal at D2 indicates that data is received from the modem.

Data Terminal Ready

The Data T erminal Ready (DTR) signal at D3 informs the modem that the
PC is ready.

TX

The TX signal at D4 indicates that data is transmitted to the modem.

Push Buttons

The eZ80Acclaim!® Development Platform provides user controls in the
form of push buttons. These push buttons serve as input devices to the

®

Ethernet Device device. The programmer can use them as neces-

eZ80
sary for application development. All push buttons are connected to the
general-purpose port pins.

PB0

The PB0 push button switch, SW1, is connected to bit 0 of the general­purpose port. This switch can be used as the port input if required by the
user.

eZ80Acclaim! Development Platform UM014108-0810

eZ80190 Development Kit

User Manual

PB1

The PB1 push button switch, SW2, is connected to bit 1 of the general­purpose port. This switch can be used as the port input if required by the
user.

PB2

The PB2 push button switch, SW3, is connected to bit 2 of the general­purpose port. This switch can be used as the port input if required by the
user.

RESET

The Reset push button switch, SW4, resets the eZ80

®

eZ80Acclaim!

Development Platform.

®

CPU and the

35

Jumpers

The eZ80Acclaim!® Development Platform provides a number of jump­ers that are used to enable or disable functionality on the platform, enable
or disable optional features, or to provide protection from inadvertent use.

Jumper J2

The J2 jumper enables/disables IrDA transceiver functionality. When the
shunt is placed, IrDA communication is disabled. This jumper does not
perform any functions when the eZ80190 Module is installed.

UM014108-0810 Operational Description

eZ80190 Development Kit
User Manual

36

Jumper J3

The J3 jumper connection controls the mode of the general-purpose port
and communication with the 7 x 5 LED. When the shunt is placed, the
general-purpose port is disabled. See Table 13.

Table 13. J3—DIS_EM

Shunt
Status Function Affected Device

In Application Module

Hardware Disabled

Out Application Module

Hardware Enabled

Communication with 7 x 5 LED and Port emulation
circuit is disabled.

Communication with 7 x 5 LED and the general­purpose port circuit is enabled.

Jumper J7

The J7 jumper connection controls Flash boot loader programming. When
the shunt is placed, overwriting of the Flash boot loader program is
enabled. See Table 14.

Table 14. J7—FlashWE

Shunt
Status Function Affected Device

Out The Flash boot sector of the eZ80190

Module is write-protected.

In The Flash boot sector of the eZ80190

Module is enabled for writing or
overwriting.

Flash boot sector of the eZ80190
Module.

Flash boot sector of the eZ80190
Module.

eZ80Acclaim! Development Platform UM014108-0810

eZ80190 Development Kit

Note:

User Manual

Jumper J11

The J11 jumper connection controls access to the off-chip Flash memory
device. When the shunt is placed, access to this Flash device is enabled.
See Table 15.

The silk-screened label on the eZ80Acclaim!

®

Development Platform for
jumper J11 is incorrect. Currently , it reads DIS_FLASH. The correct label
is EN_FLASH.

Table 15. J11—EN_FLASH (Off-Chip)*

Shunt
Status Function Affected Device

IN All access to external Flash memory on the

eZ80190 Module is enabled.

OUT All access to external Flash memory on the

eZ80190 Module is disabled.

Note: As shipped from the factory, external Flash memory is not installed.

External Flash memory on the
eZ80190 Module.

External Flash memory on the
eZ80190 Module.

37

Jumper J12

The J12 jumper connection controls the selection of a 5 V or 3 VDC power
supply to the embedded modem, if an embedded modem is used. See
Tabl e 16.

Table 16. J12—5VDC/3.3VDC for an Embedded Modem

Shunt
Status Function Affected Device

1–2 5 VDC is provided to power the embedded modem. Embedded modem.

2–3 3.3 VDC is provided to power the embedded modem. Embedded modem.

UM014108-0810 Operational Description

eZ80190 Development Kit
User Manual

38

Jumper J14

The J14 jumper connection controls the polarity of the Ring Indicator . See
Tabl e 17.

Table 17. J14—RI

Shunt
Status Function Affected Device

1–2 The Ring Indicator for UART1 is inverted. UART1.

2–3 The Ring Indicator for UART1 is not inverted. UART1.

For jumpers J15–J18, RS485 functionality is not available on the
eZ80190 Module. However, this func tionality is available in other eZ80
devices.

Jumper J15

The J15 jumper connection controls the selection RS485 circuit along
with UART0. When the shunt is placed, the RS485 circuit is enabled. See
Table 18. RS485 functionality will be available in future eZ80

Table 18. J15—RS485_1_EN*

Shunt
Status Function Affected Device

In The RS485 circuit is enabled on UART0. 

The UART0 CONSOLE interface and IrDA are
disabled.

Out The RS485 circuit is disabled on UART0. IrDA, UART0 CONSOLE

Note: *To enable the RS485 circuit, the corresponding IrDA/RS232 circuit must be disabled.

IrDA, UART0 CONSOLE
interface, RS485 interface.

interface, RS485 interface.

®

devices.

®

eZ80Acclaim! Development Platform UM014108-0810

eZ80190 Development Kit

User Manual

Jumper J16

The J16 jumper connection controls the selection of the RS485 circuit.
However, UART1 MODEM interface and the socket modem interface are
disabled if the RS485 circuit is enabled. When the shunt is placed, the
RS485 circuit is enabled. See Table 19.

Table 19. J16—RS485_2_EN

Shunt
Status Function Affected Device

39

In The RS485 circuit is enabled on UART1. The

UART1 MODEM interface and the Socket
Modem interface are disabled.

Out The RS485 circuit is disabled on UART1. UART1 MODEM interface,

UART1 MODEM interface,
Socket Modem Interface, and
RS485 interface.

Socket Modem Interface, and
RS485 interface.

Jumper J17

The J17 jumper connection controls the selection of the RS485 termina­tion resistor circuit. When the shunt is placed, the RS485 termination
resistor circuit is enabled. See Table 20.

Table 20. J17—RT_1*

Shunt
Status Function Affected Device

In The Termination Resistor for RS485_1 is IN. RS485 interface.

Out The Termination Resistor for RS485_1 is OUT. RS485 interface.

Note: *Before enabling the termination resistor, ensure that the device is located at the end of the
interface line.

UM014108-0810 Operational Description

eZ80190 Development Kit
User Manual

40

Jumper J18

The J18 jumper connection controls the selection of the RS485 termina­tion resistor circuit. When the shunt is placed, the RS485 termination
resistor circuit is enabled. See Table 21.

Table 21. J18—RT_2*

Shunt
Status Function Affected Device

In The Termination Resistor for RS485_2 is IN. RS485 interface.

Out The Termination Resistor for RS485_2 is OUT. RS485 interface.

Note: *Before enabling the termination resistor, ensure that the device is located at the end of the
interface line.

Jumper J19

The J19 jumper connection selects the range of memory addresses for the
external chip select signal, CS_EX

, to the application module. See

Tabl e 22.

Table 22. J19—EX_SEL

Shunt
Status Function Affected Device

1–2 CS_EX

located in the address range 400000h–7FFFFFh.

3–4 CS_EX

located in the address range A00000h–A7FFFFh.

5–6 CS_EX

located in the address range A80000h–AFFFFFh.

7–8 CS_EX

located in the address range B00000h–B7FFFFh.

eZ80Acclaim! Development Platform UM014108-0810

is decoded in the CS0 memory space and is

is decoded in the CS2 memory space and is

is decoded in the CS2 memory space and is

is decoded in the CS2 memory space and is

Application module
addressing.

Application module
addressing.

Application module
addressing.

Application module
addressing.

eZ80190 Development Kit

User Manual

Jumper J20

The J20 jumper connection controls the selection of the external chip
select in the external application module. When the shunt is placed, the
external chip select signal, CS_EX

Table 23. J20—EX_FL_DIS

Shunt
Status Function Affected Device

IN The jumper for EX_FL_DIS is IN. The chip select on the application module

, is disabled. See Table 23.

is disabled.

41

OUT

The jumper for EX_FL_DIS is OUT.

Connectors

A number of connectors are available for connecting external devices
such as the ZPAK II emulator, PC serial ports, external modems, the con­sole, and LAN/telephone lines.

J6 and J8 are the headers, or connectors, that provide pin-outs to connect
any external application module, such as ZiLOG’s Thermostat Applica­tion Module.

Connector J6

The J6 connector provides pin-outs to make use of GPIO functionality.

Connector J8

The J8 connector provides pin-outs to access memory and other control
signals.

The chip select on the application module
is enabled.

UM014108-0810 Operational Description

eZ80190 Development Kit
User Manual

42

Console

Connector P2 is the RS232 terminal, which can be used for observing the
console output. P2 can be connected to a PC running a HyperTerminal
program if required.

Modem

Connector P3 provides a terminal for connecting an external modem, if
used with the eZ80190 Development Kit.

I2C Devices

The two I2C devices on the eZ80Acclaim!® Development Platform are
the U2 EEPROM and the U13 Configuration register. The EEPROM pro­vides 16 KB of memory. The Configuration register provides access to
control the configuration of an application-specific function at the Appli­cation Module Interface. Neither device is utilized by the eZ80190 Devel­opment Kit software. The user is free to develop proprietary software for
these two devices. The addresses for accessing these devices are listed in
Tabl e 24.

Table 24. I2C Addresses

Device/Bit # 76543210

EEPROM (U10)* 10100A1A0R/W

Configuration Register (U13)1001110R/W

Note: *EEPROM address bits A0 and A1 are configured for 0s.

DC Characteristics

Understanding proper DC current requirements for the eZ80Acclaim!®
Development Platform when application modules are plugged into it is

eZ80Acclaim! Development Platform UM014108-0810

very important for developing applications. This section provides an esti­mate of the average current requirement when different combinations of
these application modules are plugged in to the eZ80Acclaim!
ment Platform.

The measurements of current that are shown in T able 25 are for the user’s
reference. These values can vary depending on the type of application that
is developed to run with the platform.

T able 25. DC Current Characteristics of the

eZ80Acclaim!

Platform/Modules Configurations

eZ80Acclaim!

®

Development Platform

and eZ80190 Module

eZ80Acclaim!

®

Development Platform,

eZ80190 Module, and Modem Module

eZ80Acclaim!

®

Development Platform,
eZ80190 Module, and Thermostat
Application Module

eZ80Acclaim!

®

Development Platform,
eZ80190 Module, Modem Module, and
Thermostat Application Module

eZ80Acclaim!

®

Development Platform
and eZ80190 Module

eZ80Acclaim!

®

Development Platform,
eZ80190 Module, and Modem Module

®

Development Platform with Different Module Loads

eZ80190 Development Kit

User Manual

®

Develop-

Current 
Requirement (mA) Status

173 When connected only to a

power supply, and when
no program is running.

174 When connected only to a

power supply, and when
no program is running.

195 When connected only to a

power supply, and when
no program is running.

203 When connected only to a

power supply, and when
no program is running.

325 When the LED demo is

running.

325 When the LED demo is

running.

43

UM014108-0810 DC Characteristics

eZ80190 Development Kit
User Manual

44

T able 25. DC Current Characteristics of the

eZ80Acclaim!

Platform/Modules Configurations

®

Development Platform with Different Module Loads (Continued)

Current 
Requirement (mA) Status

eZ80Acclaim!® Development Platform,
eZ80190 Module, and Thermostat
Application Module

®

eZ80Acclaim!

Development Platform,
eZ80190 Module, Modem Module, and
Thermostat Application Module

350 When the LED demo is

running.

360 When the LED demo is

running.

eZ80Acclaim! Development Platform UM014108-0810

eZ80190 Module

This section describes the eZ80190 Module hardware, its interfaces and
key components, including the CPU, Ethernet Media Access Controller
(EMAC), and memory.

Functional Description

The eZ80190 Module is a compact, high-performance Ethernet module
specially designed for the rapid development and deployment of embed­ded systems requiring control and Internet/Intranet connectivity via
Ethernet and/or fast Multiply-Accumulate operations. Additional devices
such as serial ports, LED matrices, GPIO ports, and I
ported when connected to the eZ80Acclaim!
block diagram representing both of these boards is shown in Figure 1
page 4.

The eZ80190 Module is developed to be a plug-in module to the eZ80
Development Platform. The small-footprint eZ80190 Module provides a
CPU, SRAM, Flash memory, a real-time clock, and an EMAC. This low­cost, expandable module is powered by the eZ80190 microprocessor, a
member of ZILOG’s new eZ80
tains a battery and an oscillator in support of the onboard Real-Time
Clock (RTC). The eZ80190 Module can also be used as a stand-alone
development tool when provided with an external power source.

eZ80190 Development Kit

User Manual

2

®

Development Platform. A

®

product family. The module also con-

C devices are sup-

on

®

45

Physical Dimensions

The footprint of the eZ80190 Module PCB is 6 3.5 mm x 78.7 mm. With an
RJ-45 Ethernet connector, the overall height is 25 mm. See Figure 11.

UM014108-0810 Functional Description

eZ80190 Development Kit

63.5 mm

63.5 mm

78.7 mm

User Manual

46

Figure 11. Physical Dimensions of the eZ80190 Module

eZ80190 Module UM014108-0810

eZ80190 Development Kit

User Manual

Figure 12 illustrates the top layer silkscreen of the eZ80190 Module.

47

Figure 12. eZ80190 Module—Top Layer

UM014108-0810 Functional Description

eZ80190 Development Kit
User Manual

48

Figure 13 illustrates the bottom layer silkscreen of the eZ80190 Module.

Figure 13. eZ80190 Module—Bottom Layer

Operational Description

The purpose of the eZ80190 Module as a feature of the eZ80190 Devel­opment Kit is to provide the application developer with a plug-in tool to
evaluate memory and the other features of the eZ80190 device.

eZ80190 Module UM014108-0810

Ethernet Media Access Controller

The eZ80190 Module contains a CS8900A Ethernet Media Access Con­troller (EMAC—combines MAC and PHY functions) which is attached
to the data/address bus (A0–A3, D0–D7, RD
This chip is connected to the processor’s CS3
pins for interrupt purposes. Connection of pins PD6 and PD7 for
LANACT (wake-up from sleep) and SLEEP is optional and resistor­selectable onboard (see below). Details about the internal registers of the
CS8900A EMAC can be found on the Cirrus Logic website at 

w

ww.cirrus.com.

Ethernet LEDs

There are two green LEDs, a Link LED and a LAN LED, that are located
adjacent to each other on the eZ80190 Module. A steady LAN LED (top)
indicates received link pulses from the Ethernet. A flashing Link LED
(bottom) indicates Traffic (RX or TX) on the LAN.

eZ80190 Development Kit

User Manual

49

, and WR) of the processor.

Chip Select, and to the PD4

Ethernet Connector

The eZ80190 Module is equipped with an RJ-45 connector that features
integrated magnetics (transformer, common mode chokes). The remain­ing pins on the onboard RJ-45 connector are not connected.

An RJ-45 loopback connector can be used to verify the correct operation
of the Receiver and the Transmitter. Pin assignments for the RJ-45 Ether­net connector are shown in Table 26.

Table 26. Ethernet Connector Pin Assignments

Pin Function

1 TX+

2 TX–

3 RX+

6 RX–

UM014108-0810 Operational Description

eZ80190 Development Kit
User Manual

50

To connect the eZ80190 Module directly to another host (e.g., to a per­sonal computer), a crossover cable must be used.

The EMAC can be additionally protected by placing an ESD protection
array on the module at U8. This array can be either of the LCDA15C-6
(Semtech) or ESDA25B1 (ST Microelectronics) devices.

GPIO Pins for Enabling LAN Activity, Sleep, Interrupt

GPIO input bit PD4 serves as an active High interrupt input for the
EMAC’s INTRQ0 output.

GPIO output bit PD7 can be used to place the EMAC into SLEEP mode.
When pulling SLEEP (PD7) Low after enabling HWStandbyE and
HWSleepE modes, the chip draws lower current, because only the
receiver is operating. A zero-Ohm resistor at position R14 on the
eZ80190 Development Kit is required for this function.

If LAN activity is detected, the LANACT signal is pulled Low. The
LANACT is connected to GPIO input PD6 and can be used in interrupt
edge-detection mode to wake up and reinitialize the Ethernet chip. A
zero-Ohm resistor at position R15 on the module is required for this func­tion. In this case, the PD6 pin is not available for GPIO on the I/O connec­tor.

EMAC Access

CS3

is used for selecting the Ethernet MAC. For 50 MHz operation, set

the CS3_CTL register (I/O address

B3h) to F8h (7 wait states for I/O).

The EMAC requires –IOR to be active for 135 ns and –IOW to be active
for 110 ns.

To satisfy proper setup times at 50 MHz, –IOR is delayed by one clock
cycle and –IOW is delayed by two clock cycles when CS3

goes active. To
satisfy proper hold times at 50 MHz, the EMAC address and data are
latched when CS3

eZ80190 Module UM014108-0810

goes inactive.

eZ80190 Module Memory

The eZ80190 Module contains 512 KB SRAM and 1 MB Flash memory.
This addressing structure provides 1.5 MB of contiguous RAM for imme­diate use.

SRAM Memory

The eZ80190 Module features 512 KB of fast SRAM. Access speed is
typically 12 ns or faster, allowing zero-wait-state operation at 50 MHz.
With the CPU at 50 MHz, onboard SRAM can be accessed with zero wait
states. CS1_CTL (chip select CS1

Flash Memory

The Flash Boot Loader, application code, and user configuration data are
held permanently in Flash memory.

eZ80190 Development Kit

User Manual

51

) is set to 08h (no wait states).

Internal RAM

The eZ80190 MCU features 8 KB of zero-wait-state internal SRAM. This
internal RAM can be mapped anywhere in the 16 MB address space in the
address range

E000h–FFFFh.

Reset Generator

The onboard Reset Generator Chip is connected to the eZ80190 Reset
input pin. It performs reliable Power-On Reset functions, generating a
reset pulse with a duration of 200 ms if the power supply drops below

2.93 V. This reset pulse ensures that the board always starts in a defined
condition. The RESET pin on the I/O connector reflects the status of the
RESET line. It is a bidirectional pin for resetting external peripheral com­ponents or for resetting the eZ80190 Development Kit with a low-imped­ance output (e.g. a 100-Ohm push button).

UM014108-0810 Operational Description

eZ80190 Development Kit
User Manual

52

Real Time Clock

The onboard real-time clock can function when the system power supply
is down. An onboard capacitor (GoldCap) or external accumulator/battery
serves as a standby power supply. The M41T11 Real-Time-Clock
included on the eZ80190 Module cont ains Binary Cod ed Decimal (BCD)
counting registers for Seconds, Minutes, Hours, Day, Month, Year; it also
contains a Century bit and 56 bytes of backed-up RAM. The fully­charged 0.1 F GoldCap bridges power outages with a max imum of 4
hours. The GoldCap, in contrast to a battery or an accumulator, offers an
advantage in that service/replacement is not necessary.

The I
Details about the internal registers of the M41T11 Real-Time clock can be

found on the ST Microelectronics website (www.st.com

2

C address of the RTC is D0h for Writes and D1h for Reads.

).

I2C Bus Software Emulation

The eZ80190 device contains two powerful master/slave mode I2C bus
controllers. The I
PC1/PC0 GPIO are multiplexed with the UAR T and SPI functions. To use

2

C bus operation in parallel with console and modem I/O, the module

I
IICSCL/IICSDA pins on connector JP2 can be linked to PA7 (IICSDA)
and PA6 (IICSC L) of the eZ80190 device. In this case, an I
mode software emulation is necessary to access I

Using PA7/PA6 or PC1/PC0 for IICSDA/IICSCL is resistor -selectable on
the eZ80190 Module.

2

C data (SDA) and clock (SCL) pins on PD1/PD0 and

2

2

C devices.

C master-

DC Characteristics

As different combinations of application modules are loaded onto the
eZ80Acclaim!
Please see Table 25
for these different modules.

eZ80190 Module UM014108-0810

®

Development Platform, current requirements change.

on page 43 to reference current consumption values

Flash Loader Utility

The Flash Loader utility resides in the boot sector of Flash memory,
located on the eZ80190 Module. The Flash Loader utility allows the user
to program application code into Flash memory.

Please refer to the External Flash Loader Product User Guide
(PUG0012) for more details.

Mounting the Module

When mounting the eZ80190 Module onto the eZ80Acclaim!® Develop­ment Platform, check its orientation to the platform to ensure a correct fit.
Pin 11 of JP1 on the eZ80190 Modul e must align with pin 1 of JP1 on th e
eZ80Acclaim!
Module must align with pin 1 of JP2 on the eZ80Acclaim!
Platform, etc.

®

Development Platform; Pin 11 of JP2 on the eZ80190

eZ80190 Development Kit

User Manual

®

Development

53

Changing the Power Supply Plug

The universal 9VDC power supply offers three different plug configura­tions and a tool that aids in removing one plug configuration to insert
another, as shown in Figure 14.

Figure 14. 9VDC Universal Power Supply Components

UM014108-0810 Flash Loader Utility

eZ80190 Development Kit
User Manual

54

To exchange one plug configuration for another, perform the following
steps:

1. Place the tip of the removal tool into the round hole at the top of the

2. Press down to disengage the keeper tab and push the plug configura-

3. Select the plug configuration appropriate for your location, and insert

4. Push the new plug configuration down until it snaps into place, as

current plug configuration.

tion out of its slot.

it into the slot formerly occupied by the previous plug configuration.

indicated in Figure 15.

Figure 15. Inserting a New Plug Configuration

eZ80190 Module UM014108-0810

ZPAK II

ZPAK II is a debug tool used to develop and debug hardware and soft­ware. It is a networked device featuring an Ethernet interface and an
RS232 console port. ZPAK II is shipped with a preconfigured IP address
that can be changed to suit the user on a local network. For more informa­tion about using and configuring ZPAK II, please refer to the ZP AK II

Debug Interface Tool Product User Guide (PUG0015) and the eZ80190
Development Kit Quick Start Guide (QS0004).

ZDI Target Interface Module

eZ80190 Development Kit

User Manual

55

The ZDI Target Interface Module provides a physical interface between
ZPAK II and the eZ80Acclaim!
ule supports ZDI functions. For more information on using the TIM mod­ule or ZDI please refer to the eZ80190 Development Kit Quick Start
Guide (QS0004) and the eZ80190 Module Product Specification
(PS0191).

JTAG

Connector P1 is the JT AG connector on the eZ80Acclaim!® Development
Platform. JTAG will be supported in the next offering of eZ80

Application Modules

ZiLOG offers the Thermostat Application module, which can be used for
evaluating and developing process control and simple I/O applications.
The Thermostat Application module is equipped with an LCD display
that can be used to display process control and other physical parameters.
For additional reading about the Thermostat application, please see the
Java Thermostat Demo Application Note (AN0104) on zilog.com.

®

Development Platform. The TIM mod-

®

products.

UM014108-0810 ZDI Target Interface Module

eZ80190 Development Kit
User Manual

56

ZDS II

ZiLOG Developer Studio II (ZDS II) Integrated Development Environ­ment is a complete stand-alone system that provides a state-of-the-art
development environment. Based on the Windows
SP4/WinXP Professional user interfaces, ZDS II integrates a language­sensitive editor, project manager , C-Compiler , assembler, linker , librarian,
and source-level symbolic debugger that supports the eZ80
more information about using and configuring ZDS II, please refer to the
ZiLOG Developer Studio II—eZ80Acclaim! User Manual (UM0144).

®

Win 98SE/Win2000-

®

CPU. For

ZDS II UM014108-0810

Troubleshooting

Overview

Before contacting ZiLOG Customer Support to submit a problem report,
please follow these simple steps. If a hardware failure is suspected, con­tact a local ZiLOG representative for assistance.

Cannot Download Code

eZ80190 Development Kit

User Manual

57

If you are unable to download code to RAM using ZDS, make sure to
press and release the Reset button on the eZ80Acclaim!
Platform prior to selecting
ZDS.

No Output on Console Port

The eZ80190 Development Kit is shipped with a Flash Loader utility that
is loaded in the protected boot sector of Flash memory (U3). Upon power­up of the eZ80Acclaim!
server-i E-NET Module, the eZ80190 device on the module starts running
code from this Flash memory area. This code enables the Console port
with settings of 57.6 kbps, 8, N, 1.

The Console checks the Receive buffer. If a space character is received on
the Console port, the Flash Loader utility is enabled and a boot message
should be displayed on your connected device. If no message is displayed,
check the following:

•

Jumper J2 must be ON (IrDA is disabled)

•

On Connector J6, the jumper must be removed from pins 6 and 9 (pin
names con_dis and GND).

®

Development Platform and the eZ80 Web-

Debug



Reset

and then

®

Development

Debug  Go

in

UM014108-0810 Overview

eZ80190 Development Kit
User Manual

58

IrDA Port Not Working

If you plan on using the IrDA transceiver on the eZ80 Webserver-i E-NET
Module, make sure the hardware is set up as follows:

•

Jumper J2 must be OFF (to enable the control gate that drives the
IrDA device)

•

Set port pin PD2 Low. When this port pin and Jumper J2 are turned
OFF, the IrDA device is enabled.

•

Install a jumper on connector J6 across pin names con_dis and GND
to disable the console serial port driver

Difference Between EMAC and IP Address

Media Access Control (MAC)

Each and every Ethernet device interface to the network media (e.g., net­work adapter, port on a hub) contains a unique MAC address, which is
hard-coded into the hardware when it is manufactured. An Ethernet
device addresses a host using a unique 48-bit address called its Ethernet
address or Media Access Control (MAC) address.

MAC addresses are usually represented as six colon-separated pairs of
hex digits, e.g., 6:0:20:11:ac: 85. The first three bytes (e.g., 6-0-20) are
the manufacturer’s code, which can be used to identify the manufacturer.
The last three bytes are the unique station ID or serial number for the
interface. This station ID is unique and is associated with a particular
Ethernet device. The Data Link layer's protocol-specific header specifies
the MAC address of the packet's source and destination. When a packet is
sent to all hosts (broadcast), a special MAC address (ff:ff:ff:ff:ff:ff) is
used.

MAC addresses uniquely identify each node in a network at the Media
Access Control layer, the lowest network layer that directly interfaces
with the physical media (e.g., twisted-pair wires).

Troubleshooting UM014108-0810

On a Local Area Network or other network, the MAC address is the com­puter's unique hardware number. (On an Ethernet LAN, the MAC address
is the same as an Ethernet address.) When it is connected to the Internet, a
computer (or host as the Internet protocol considers it), a correspondence
table relates the Internet Protocol (IP) address to the computer's physical
(MAC) address on the LAN.

IP Address

An IP address is a 32-bit number that identifies each sender or receiver of
information that is sent in packets across the Internet.

An IP address contains two parts: the identifier of a particular network on
the Internet, and an identifier of the particular device (which can be a
server or a workstation) within that network. On the Internet itself—that
is, between the router that moves packets from one point to another along
the route—only the network part of the address is examined.

eZ80190 Development Kit

User Manual

59

Relationship of the IP Address to the Physical Address

The machine or physical address used within an organization's local area
networks can be different than the IP address coming from the Internet.
The most typical example is the 48-bit Ethernet address. TCP/IP includes
the Address Resolution Protocol (ARP) that lets the administrator create a
table that maps IP addresses to physical addresses.

The Ethernet MAC address of the ZPAK II

When connecting the ZPAK II serial port to a PC running HyperT erminal,
hold the space bar and reset the ZPAK II.

When HyperTerminal prompts with

eZ80>

enter e to display the MAC address.

UM014108-0810 Difference Between EMAC and IP Address

eZ80190 Development Kit
User Manual

60

Resolving IP Address/Subnet Mask Conflicts

For running demos properly. the ZPAK II IP address and subnet mask
must be properly configured. Please follow the instructions provided in
the eZ80190 Development Kit Quick Start Guide (QS0004) to set up and
run the demos on ZDS II.

Troubleshooting UM014108-0810

e

Z80190 D

Kit

5 4 3 2 1

D D

C C

B B

A A

DO NOT USE J6_17 A

ND J6_35

MODEM CONNECTORS

MODEM's
AGND

ZDI
INTERFAC

E

DCD

RX

DTR

TX

Connectors

96C

0858-001

C

Schematic,

eZ80L92 Evaluation Board

ZiLOG

910 E. Hamilton Avenue

B

Title

SizeDocument Number

Rev

TCK
TDI

TD

O

TDI

TRIGOUT

TCK

TMS

PRSTn

VDD

PB2_SS

D3

VDD

PB6_MISO

D2
D4

VDD

A20

GND

A6

A14

D5

GND

D6

A9

GND

PB1_T1_I

GND

GND

GND

D0

A0

A23

A11

GND

GND

A5

GND

PB7_MOSI

PB0_T0_I

A4

A19

A2

A16

A21

A12

-RESE

T

VDD

D1

GND

A1

A17

A7

GND

GND

GND

A8

D7

PHI

VDD

GND

A22

A13

A3

A18

PB3_SCK

GND

GND

A10

A15

VDD

VDD

VDD

MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7

A0
A1
A2
A3
A4
A5
A6
A7

A11

MA15

MA11

A14

MA12

A13

A15

A9

MA8
MA9

A12

MA13

A10

MA14

MA10

A8

A16

A22

A19

MA21

MA19

MA17

MA20

A23

A21

MA23

MA18

A18

MA16

A17

MA22

A20

MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7

D1
D2

D0

D4

D3

D5
D6
D7

-M_RD

D[7:0]

A[23:0]

SCL

SDA

VDD

ID_0

ID_1

ID_2

9V_DC

GND

PC6_DCD1

PC2_RTS1

-MR

ESET

PC1_RXD1

PC3_CTS1
PC5_DSR1

PC

0_TXD1

PC7_RI1

GND

PC4_DTR1

MA6
MA10

GND
MA8
MA13
MA15
MA18
MA19
MA2
MA11
MA4
MA5

-DIS_ETH
MA21
MA22

-M_CS0

-M_CS2
MD1
MD3
MD5
MD7

-M_MEMRQ

GND

-M_WR

-BUSACK

MD6

MA16

VDD

MD2

MA

9

-M_RD

GND

VDD

MA

0

MA12

MA17

MA

1

INSTRD

MA23

MD0

MD4

MA

7

-DIS_FL

-M_IORQ

MA

3

GND

MA20

-M_CS

1

MA14

-M_CS3

PC4_DTR1

PB3_SCK

VDD

SCL

GND

VDD

-FLASHWE

TDO

PB7_MOSI

PD6_DCD0

PD3_CTS0

PC

0_TXD1

HALT_SL

P

GND

RTC_VDD

SDA

PB1_T1_I

PD1_RXD0

-RST

PB5

_T5_O

PC2_RTS1

PD5_DSR0

TCK

-DIS_IRDA

PC3_CTS1

PB2_SS

GND

PC7_RI1

GND

TDI

PB6_MISO

GND

PD2_RTS0

PD7_RI0

-NMI

TRIGOUT

M_PHI

PB0_T0_I

PD

0_TXD0

PB4

_T4_O

PC1_RXD1

PD4_DTR0

TM

S

PC5_DSR1

GND

VDD

-M_CS0

-M_CS1

-M_CS2

M_

TIP

M_RING

GND

GND

GND

VCC

GND

GND

MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7

PC6_DCD1

VDD

VDD

-BUSREQ

VDD

GND

VDD

VCC

GND

VDD

-M

WAIT

PB

4_T4_O

PB

5_T5_O

-CS3

-FLASHWE

GND

GND

GND

VDD
GND

GND

GND

GND

VDD

GND

VDD

VDD

VCC

VCC

VDD

TVCC_RESETn

VDD

GND

-M_IORQ

-M_MEMRQ

-M_WR

-M_RD

-M_CS3
M_PHI

PRSTn

-RST

PC3_CTS1

-MOD_DIS

PD

0_TXD0

-NMI

PC4_DTR1

PD1_RXD0

-CS0

INSTRD

PD2_RTS0

PHI

PD7_RI0

-CS2

-RD

PD4_DTR0

-BUSREQ

PC1_RXD1

PD5_DSR0

PD3_CTS0

PC2_RTS1

-CS1

PC5_DSR1

-IORQ

PC7_RI1

PC6_DCD1

PC

0_TXD1

-CON_DIS

-WR

PD6_DCD0

-ME

MRQ

-BUSACK

-RESE

T

EM_D1

EM_D2

EM_D3

EM_D4

EM_D5

EM_D6

EM_D7

D[7:0]

A[23:0]

EM_D0

-MW

AIT

-MRE

SET

-MOD_DIS

-CS0

-CS1

-CS2

-C

S_EX

SCL
SDA

MD[7:0]

VDD
GND

VCC

9VDC

PB2_SS
PB1_T1_I
PB0_T0_I

-DIS_FL

ID_0

ID_1

ID_2

M_T

IP

M_RING

-L_RD

-DIS_ETH

-DIS_IRDA

-IORQ

-ME

MRQ

PHI

-WR

-RD

-CS3

J1

HEADER 32

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

R1
10K

JP2

Header 25x2

12
34
56
78
9

10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50

D1

21

C34

0.1uF

R9

0

J2

HEADER 2

1
2

D2

21

C31

0.1uF

D4

21

P1

con 7x2

12
34
56
78
9

10
11 12
13 14

R8

0

R2
10K

U1

74LV244A

2
4
6
8

1

18
16
14
12

20
10

11
13
15
17

9
7
5
3

19

A1
A2
A3
A4

1OE

Y1
Y2
Y3
Y4

VCC

GND

A5
A6
A7
A8

Y5
Y6
Y7
Y8

2OE

C1

0.1uF

J4

Header 3x2

12
34
56

J5

HEADER 2

1
2

J8

Header 30x2

12
34
56
78
9

10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60

R3
10K

R19

10K

R5

1K

C33

0.1uF

U8A

TC7

4LVT125

23

14

1

7

U21

74LVC827/SO

12

24

23
22
21
20
19
18
17
16

2
3
4
5
6
7
8
9

13

1

10
11

15
14

GND

VCC

Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8

A1
A2
A3
A4
A5
A6
A7
A8

OE2

OE1

A9
A10Y9Y10

J12

Header 3

1
2
3

R24
10K

U5

74LV244A

2
4
6
8

1

18
16
14
12

20
10

11
13
15
17

9
7
5
3

19

A1
A2
A3
A4

1OE

Y1
Y2
Y3
Y4

VCC

GND

A5
A6
A7
A8

Y5
Y6
Y7
Y8

2OE

R4
10K

R20

0

J7

HEADER 2

1
2

U2

AT24C1

28

1
2

4

5

6

7

8

3

A0
A1

GND

SDA

SCL

WP

VCC

NC

U3

74LV244A

2
4
6
8

1

18
16
14
12

20
10

11
13
15
17

9
7
5
3

19

A1
A2
A3
A4

1OE

Y1
Y2
Y3
Y4

VCC

GND

A5
A6
A7
A8

Y5
Y6
Y7
Y8

2OE

D3

21

U9A

TC74LVC08

1

2

3

147

J9

HEADER 9

1
2
3
4
5
6
7
8
9

R21

0

U7

74LVC245/SO

2
3
4
5
6
7
8
9

19

1

18
17
16
15
14
13
12
11

20
10

A0
A1
A2
A3
A4
A5
A6
A7

OE

DIR

B0
B1
B2
B3
B4
B5
B6
B7

VCC
GND

JP1

Header 25x2

12
34
56
78
9

10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50

J6

Header 30x2

12
34
56
78
9

10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60

C30

0.1uF

evelopment

User Manual

Schematic Diagrams

eZ80® Development Platform

Figures 16 through 20 present the schematics of the eZ80® Development Platform.

UM014108-0810

Figure 16. eZ80® Development Platform Schematic Diagram, #1 of 5

61

e

Z80190 D

Kit

evelopment

User Manual

62

-DIS_EM

A[23:0]

D[7:0]

MD[7:0]

-CS0

-CS1

-CS2

-CS3

-MEMRQ

-IORQ

PHI

-RD

-WR

SDA
SCL

VDD
GND

R6

VDD

J11

VDD

VDD

GND

GND

TRIG1
TRIG2

10K

-CS2

2
1

2
1

CT4
CT3
CT2
CT1
CT0

MD[7:0]

-MRESETD5

C6

0.1uF

-FL_DIS

-CS0
A23
A22
A21
A20
A19
A18
A17
A16

-EX_FL_DIS

R710K

-MRESET

AN0

AN1

AN2

AN3

AN4

AN5

U16

3

A1

4

A2

5

A3

6

A4

7

A5

8

A6

9

A7

10

A8

14

LEAB

1

LEBA

13

OEAB

2

OEBA

11

CEAB

23

CEBA

74LCX543/SO

12

11

C5

0.1uF

AN6

MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0 EM_D0

-EM_WR

-EM_RD

-EM_WR_OE

U10

3

I1

4

I2

5

I3

6

I4

7

I5

9

I6

10

I7

11

I8

12

I9

13

I10

16

I11

2 14

CLK/I0 GND

22V10A/LCC

1 3 10 7 8

2

9

4

5

6

22

B1

21

B2

20

B3

19

B4

18

B5

17

B6

16

B7

15

B8

24

VCC

12

GND

VDD

I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9

VCC

EM_D7
EM_D6
EM_D5
EM_D4
EM_D3
EM_D2
EM_D1

GND

M_TIP

M_RING

SCL
SDA

GND

VDD

1
2
3
4
5
6
7
8 9

-CON_DIS

-DIS_0

-DIS_IRDA

R10

R11

10K

10K

12

SIDACTOR P3100SB
U11

C3

0.001uF

GND

U13

SCL
SDA
OVERR
M_IN_A
M_IN_B
M_IN_C
M_IN_D
GND M_OUT_D

PCA8550

R12
10K

N_MUX_O

MUX_SEL
M_OUT_A
M_OUT_B

M_OUT_C

GND

-CS_EX_IN

-MEM_CEN1

-MEM_CEN2

-MEM_CEN3

PB0_T0_I

PB1_T1_I

PB2_SS

VDD

-EM_EN

VDD

GND

GND

-CS_EX_IN

-MEM_CEN1

-MEM_CEN2

-MEM_CEN3

-MEM_CEN4

-L_RD

-DIS_FL

C2

0.1uF

TRIG1

TRIG2

-MEM_CEN1

-MEM_CEN2

-MEM_CEN3

-MEM_CEN4

JP4

1

Pin2

JP5

1

Pin2

14

10

9 8

U8C

7

TC74LVT125

14

4

5 6

U8B

7

TC74LVT125

SW1

SW PUSHBUTTON

SW2

SW PUSHBUTTON

SW3

SW PUSHBUTTON

17
18
19
20
21
23
24
25
26
27

28

D5

LTP -757

EM_D7
EM_D6
EM_D5
EM_D4
EM_D3
EM_D2
EM_D1
EM_D0

C8

0.1uF

VCC

GND

VCC

GND

-EM_RD

-EM_WR

-CT_WR

-AN_WR

-CS3
A6

-FL_DIS

-EX_FL_DIS

2

Q0

5

Q1

6

Q2

9

Q3

12

Q4

15

Q5

16

Q6

19

Q7

20

10

2

Q0

5

Q1

6

Q2

9

Q3

12

Q4

15

Q5

16

Q6

19

Q7

20

10

-DIS_ETH

C7

0.1uF

VDD

J20

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19

D[7:0]

A20
A21
A22
A23

D0
D1
D2
D3
D4
D5
D6
D7

MD[7:0]

-CS0

-CS1

PHI

-RD

-WR

SDA
SCL

-CS2

-CS3

GND

2
1

J3

-IORQ

VDD
GND

D[7:0]

VDD

R13
10K

-EM_EN
A0
A1

-RD

-WR
A2
A3
A4
A5 A7

D0
D1
D2
D3
D4

D6
D7

-CT_WR

D0
D1
D2
D3
D4
D5
D6
D7 -EM_WR_OE

-AN_WR

U15

3

I/O0

I1

4

I/O1

I2

5

I/O2

I3

6

I/O3

I4

7

I/O4

I5

9

I/O5

I6

10
11
12
13
16

I/O6

I7

I/O7

I8

I/O8

I9

I/O9

I10
I11

VCC

2 14

CLK/I0 GND

22V10A/LCC_0

U12

3

D0

4

D1

7

D2

8

D3

13

D4

14

D5

17

D6

18

D7

11

CLK

1

OE

74HCT374

U14

3

D0

4

D1

7

D2

8

D3

13

D4

14

D5

17

D6

18

D7

11

CLK

1

OE

74HCT374

17
18
19
20
21
23
24
25
26
27

VDD

28

GND

WP

Ferrite Core

C4

0.001uF

VDD

16

GND

15
14

GND

13
12
11
10

14

13

12 11

U8D

7

TC74LVT125

J19

2
4
6
8

EX_SEL

T1

ID_2
ID_1
ID_0

1
3
5
7

1
2
3
4

RJ14

-DIS_1

-MOD_DIS

P4

1
2
3
4

-CS_EX

UM014108-0810

Figure 17. eZ80® Development Platform Schematic Diagram, #2 of 5

Z80190 D

Kit

A[23:0]

D[7:0]

A[23:0]

D[7:0]

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18

D0
D1
D2
D3
D4
D5
D6
D7

A[23:0]

-MEM_CEN1

-WR

-RD

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18

1
2
3
4

5
14
15
16
17
18
20
21
22
23
24
32
33
34
35
19
36

6
13
31

U17

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
NC
NC

CE
WE
OE

AS7C34096

VDD0
VDD1

VSS0
VSS1

e

evelopment

User Manual

63

D[7:0]

A[23:0]

D0
D1
D2
D3
D4
D5
D6
D7

D1

8

D2

11

D3

12

D4

25

D5

26

D6

29

D7

30

9
27

10
28

C9

0.1uF

D0

7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18

-MEM_CEN2

-WR

-RD

1
2
3
4

5
14
15
16
17
18
20
21
22
23
24
32
33
34
35
19
36

6
13
31

U18

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
NC
NC

CE
WE
OE

AS7C34096

VDD0
VDD1

VSS0
VSS1

7

D0

8

D1

11

D2

12

D3

25

D4

26

D5

29

D6

30

D7

9
27

10
28

D[7:0]

A[23:0]
D0
D1
D2
D3
D4
D5
D6
D7

C10

0.1uF

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18

-MEM_CEN3

-WR -WR

-RD

1
2
3
4

5
14
15
16
17
18
20
21
22
23
24
32
33
34
35
19
36

6
13
31

U19

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
NC
NC

CE
WE
OE

AS7C34096

VDD0
VDD1

VSS0
VSS1

7

D0

8

D1

11

D2

12

D3

25

D4

26

D5

29

D6

30

D7

9
27

10
28

D[7:0]

A[23:0]
D0
D1
D2
D3
D4
D5
D6
D7

VDDVDD

C11

0.1uF

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18

-MEM_CEN4

-RDGND GND GND GND

1
2
3
4

5
14
15
16
17
18
20
21
22
23
24
32
33
34
35
19
36

6
13
31

U20

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
NC
NC

CE
WE
OE

AS7C34096

VDD0
VDD1

VSS0
VSS1

7

D0

8

D1

11

D2

12

D3

25

D4

26

D5

29

D6

30

D7

9
27

10
28

D[7:0]

D0
D1
D2
D3
D4
D5
D6
D7

VDDVDD

C12

0.1uF

-MEM_CEN1

-MEM_CEN2

-MEM_CEN3

-MEM_CEN4

-RD

-WR

VDD
GND

-MEM_CEN1

-MEM_CEN2

-MEM_CEN3

-MEM_CEN4

-RD

-WR

VDD
GND

GND

147

9

10

147

4

5

147

12

13

Figure 18. eZ80® Development Platform Schematic Diagram, #3 of 5

U9C

TC74LVC08

8

U9B

TC74LVC08

6

U9D

TC74LVC08

11

UM014108-0810

e

Z80190 D

Kit

evelopment

User Manual

64

PC7_RI1

PD0_TXD0

PD2_RTS0

VDD

RI1_NB

C15

0.1

RI1_B

-DIS_CON

R14

PD3_CTS0

PD1_RXD0

10K

C14

0.1

GND

VDD

J14

1
2
3

Header 3

28

24

1

2

14

13

12

22

23

20

19

18

17

16

15

-MOD_DIS

R16

VDD

U22

C1+

C1-

C2+

C2-

T1IN

T2IN

T3IN

FORCEOFF

FORCEON

R2OUTB

R1OUT

R2OUT

R3OUT

R4OUT

R5OUT

C25

0.1

PC0_TXD1

PC4_DTR1

PC2_RTS1

10K

PC5_DSR1

PC3_CTS1

PC1_RXD1

PC6_DCD1

C24

0.1

RI1_B

RI1_NB

26

VCC

T1OUT

T2OUT

T3OUT

INVALID

GND

MAX3245CAI

25

R1IN

R2IN

R3IN

R4IN

R5IN

V+

V-

28

24

1

2

14

13

12

22

23

20

19

18

17

16

15

27

3

9

10

11

21

4

5

6

7

8

VDD

U24

C1+

C1-

C2+

C2-

T1IN

T2IN

T3IN

FORCEOFF

FORCEON

R2OUTB

R1OUT

R2OUT

R3OUT

R4OUT

R5OUT

TXD0

RTS0

CTS0

RXD0

C13

0.1F

26

VCC

GND

25

C21

0.1

V+

V-

T1OUT

T2OUT

T3OUT

INVALID

R1IN

R2IN

R3IN

R4IN

R5IN

MAX3245CAI

C17

C16

0.1uF

0.1F

GND

27

3

TXD1

9

DTR1

10

RTS1

11

21

DSR1

4

5

CTS1 RTS1

6

RXD1

7

DCD1

8

J10

HEADER 5

C27

0.1

12345

RESET

C26

0.1

SW4

TXD0

CTS0
RXD0
RTS0

DCD1
DSR1RI1
RXD1

TXD1

CTS1
DTR1

RI1

GND

9VDC

9VDC

F1

RXE160

J15

1
2

RS485_1_EN

1

2

3

4 5

1

2

3

4 5

J16

RS485_2_EN

D6

S26

U26

RO

RE

DE

DI GND

DS1487

U27

RO

RE

DE

DI GND

DS1487

1
2

VCC

VCC

C22

0.1

8

7

B

6

A

8

7

B

6

A

J13

2
3
1

PWR JACK

-RESET

P2
1
6
2
7
3
8
4
9

CONSOLE

5

DB9 Female

PD1_RXD0

PD2_RTS0

PD0_TXD0

PC1_RXD1

PC2_RTS1

PC0_TXD1

P3
1
6
2
7
3
8
4
9
5

MODEM

DB9 Male

U23
LM7805C/TO220/0.5A

1 3

IN OUT

2

+

C23
22uF

R17
10K

VCC

GND

R18
10K

GND

C32

0.1uF

C18

0.1uF

C20

0.1

U25

3 2

VIN VOUT

1

GND

LT1086-3.3/TO220

-DIS_0

J17

RT_1

J18

RT_2

VCC

5V

1
2

1
2

+

22/10

C19

R23

R22

VCC

3.3V

C29

0.1

120

120

+

22/6.3

C28

21

GND

VDD

VDD

R15

680

D7

GREEN

3.3 OK

GND

P4
1
2
3
4
5
6
7
8

con8

-DIS_1

UM014108-0810

VCC

Figure 19. eZ80® Development Platform Schematic Diagram, #4 of 5

Z80190 D

Kit

MATES WITH AMP = 749268-1

P1

1
2
3
4
5
6
7
8

LENGTH = 5’
WIRES 28 AWG

Figure 20. eZ80® Development Platform Schematic Diagram, #5 of 5—RS-485 Cable

e

evelopment

User Manual

65

UM014108-0810

Z80190 D

Kit

eZ80190 Module

-CS0 --> FLASH

-CS1 --> RAM

-CS2 --> ext. IO

-CS3 --> ETH

=

don’t
stuff

place caps close
to pins 97, 8, 38, 48

don’t
stuff

PA[0..7]

D[0..7]

PC[0..7]

PB[0..7]

A[0..23]

D[0..7]

A[0..23]

PB[0..7]

D0D1D2D3D4D5D6

D7

A0
A1
A2
A3
A4
A5
A6
A7

A8
A9
A10
A11
A12
A13

A14

A15

A16

A17

A18

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PD0

PD1

PD2

PD3

PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0

PB5
PB4
PB3
PB2
PB1
PB0

-CS0

-CS1

-CS2

-CS3

ZDA
ZCL

-BUSREQ

-RESET

PD6

PD7

PD4

PB7
PB6

-WR

-RD

-WR

-RD

ZDA

ZCL

-RESET

-SLEEP

-ACTIVE

CLK_OUT

CLK_OUT

A19

A20

A21

A22

A23

-CS[0..3]

-NMI

-IOREQ

-INSTRD

-HALT

-IOREQ

-INSTRD

-HALT

-MREQ

-BUSACK

PD5

XIN

PD[0..7]

PC[0..7]

PD[0..7]

-NMI

IICSD

A

IICSCL

-BUSREQ

-BUSACK

-MREQ

PD7

PD6

PD4ETHIRQ

PA7

PA6

PC1

PC0

PA[0..7]

D[0..7]

A[0..23]

-WR

-RD

ZDA

ZCL

-CS[0..3]

-RESET

-IOREQ

-INSTRD

-HALT

PB[0..7]

PC[0..7]

PD[0..7]

-NMI

ETHIRQ

-ACTIVE

-SLEEP

-BUSACK

-BUSREQ

-MREQ

CLK_OUT

IICSDA

IICSCL

PA[0..7]

C18
1nF
0603

C19
1nF
0603

C20
1nF
0603

U1

eZ80190

TQFP100

83748240817380

26

84

85

86

87

88

96799572947893

75

97

98

99

100

9277914907689

715
70

41

27

69

42

68

6

67

1

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

30

43744

312324533

3

283429

46

358364737

9

10

381139

12
13
14

48

491550

16
17
18
19
20
21
22
23
24
25

PD7/RI0

PC7/RI1

PD6/DCD0

D0

PD5/DSR0

PC6/DCD1

PD4/DTR0

A14

VDD

VSS

XTAL

EXTAL

BUSACK

PA7

PD3/SS0/CTS0

PA6

PC5/DSR1

PA5

PD2/SCK0/RTS0

PA4

TEST

VDD

VSS

BUSREQ

PHI

PA3

PD1/SDA0/MOSI0/RxD0

PA2

CS0

PA1

PD0/SCL0/MISO0/TxD0

PA0

PC4/DTR1CS1

PC3/SS1/CTS1

D1

A15

PC2/SCK1/RTS1

D2

PC1/SDA1/MOSI1/RxD1

CS2

PC0/SCL1/MISO1/TxD1

MREQ

HALT

INSTRD

IORQ

RESET

ZCL

ZDA

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

VDD

VSS

A16

D3

CS3

D4

A17WRA18D5A19

RD

VDD

A20

VSS

D6

A21

VDD

A22D7A23

VSS
A0

VDDA1VSS

A2
A3
A4

VDD

VSSA5NMI

A6
A7
VDD
VSS
A8
A9
A10
A11
A12
A13

R4

1k
0603

R32

0R
0603

R33

0R
0603

R31

0R
0603

R30

0R
0603

R14

0R
0603

X1

50.000MHz, 3.3V
SG-710

13

OEOUT

R13

4k7
0603

R15

0R
0603

Figures 21 through 28 present the schematics of the eZ80190 Module.

e

evelopment

User Manual

66

UM014108-0810 Schematic Diagrams

Figure 21. eZ80190 Module Schematic Diagram, #1 of 8—CPU

e

Z80190 D

Kit

A21/ A22/ A23
not used her e

=

A[0..23]

D[0..7] A0

A1
A2
A3

-CSRAM
D0
D1

D2
D3

-WR
A12
A9
A6
A4

A16
A15
A14
A13

-RD
D7
D6

D5
D4
A11
A8
A10
A7
A5

A18

A17

-CSRAM-CS1

-RD

-WR

D7
D6
D5
D4
D3
D2
D1
D0

A20

A19

VSS

VDD

D[0..7]

A[0..23]

-CS1

-RD

-WR

V3.3

GND

C1
100nF
0603

RN1

9 x 4k7
SIP10

12

3

4

5

6

7

8

9

10

U2

512kx8 fast SRAM
SOJ36.400
AS7C34096-10JC

31

35

6

34

5

33

7

32

4

3

24

2

25

23

26

36

29

30

1

22

28

13

27

21

8

11
12

18

17

10

19

20

16

15

14

9

OE

A18

CE

A17

A4

A16

I/O0

A15

A3

A2

A14

A1

I/O4

A13

I/O5

N.C.

I/O6

I/O7

A0

A12

VSS

WE

VDD

A11

I/O1

I/O2
I/O3

A9

A8

VSS

N.C.

A10

A7

A6

A5

VDD

evelopment

User Manual

67

Figure 22. eZ80190 Module Schematic Diagram, #2 of 8—36-Pin SRAM Device

UM014108-0810 Schematic Diagrams

Z80190 D

Kit

D[0..7]

e

evelopment

User Manual

68

D[0..7]

A[0..23]

-RD

-WR

-CS0

-DIS_FLASH

-RESET

-FLASHWE

A[0..23]

C2
100nF
0603

D[0..7]

A[0..23]

-RD

-WR

-CS0

-DIS_FLASH

-FLASHWE

Intel-Type

30

U3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19

8

A8

7

A9

36

A10

6

A11

5

A12

4

A13

3

A14

2

A15

1

A16

40

A17

13

A18

37 38

A19 N.C.

Pi n37=N. C.
f or 4Mbi t ­Fl ashes

A22/ A23
not used her e

R6

10k
0603

-RESFLASH-RESET

=

31

DQ0A0

VDD

VDD

DQ1A1
DQ2A2
DQ3A3
DQ4A4
DQ5A5
DQ6A6
DQ7A7

WE

WP

VPP

N.C.

VSS

VSS

Flash 1Mx8 3.3V

23

39

TSOP40.20MM
MT28F008B3VG

2521
2620
2719
2818
3217
3316
3415
3514

22

CE

24

OE

9
10

RP

12

11

29

-FLASHWE

DFLASH0
DFLASH1
DFLASH2
DFLASH3
DFLASH4
DFLASH5
DFLASH6
DFLASH7

-CSFLASH

-RD

-WR

-RESFLASH

-WP

VPP

A21
A20

R5

0R 0603

A20/ A21 used f or
16/ 32Mbi t - Fl as h

U6A

1 2

74LCX04
TSSOP14

R7
10k

0603

U6B

3 4

-CS0

-FLASH_EN-DIS_FLASH

-WP

U4

5

1B2

6

1B3

9

1B4

10

1B5

15

2B1

16

2B2

19

2B3

20

2B4

23

2B5

74CBTLV3384
SO24.300

1

2

1A11B1
1A2
1A3
1A4
1A5
2A1
2A2
2A3
2A4
2A5

1OE
2OE

U5A

74LCX32
TSSOP14

32
4
7
8
11
14
17
18
21
22

1
13

3

D0
D1
D2
D3
D4
D5
D6
D7

-CSFLASH

-CSFLASH

V3.3

VDD

VSS

GND

Note: Must be pulled Low
externally for programming.

74LCX04
TSSOP14

Figure 23. eZ80190 Module Schematic Diagram, #3 of 8—NOR Flash Device

UM014108-0810 Schematic Diagrams

Z80190 D

Kit

R11
4k7
0603

ETHIRQ

SA0
SA1
SA2
SA3

SA[0..3]

-DIS_ETH

device addresses:
00300h bis 0030Fh

-ETHRD

-ETHWR

-DIS_ETH

SD[0..7]

SA[0..3]

ETHIRQ

-SLEEP

-ACTIVE

19

20

21

22

23

24

25

SD11

SD9
SD8
MEMW
MEMR
INTRQ2
INTRQ1
INTRQ0
IOCS16
MEMCS16
INTRQ3
SHBE
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
REFRESH
SA12

515253

-LANLED-ACTIVE

SD10

SA13

26
27
28
29
30
31
32
33
34
35
36
37

-ETHRD

-ETHWR -ETHWR

-DIS_ETH

SD[0..7]

SA[0..3]

ETHIRQ

-SLEEP

=

DVSS

SA14

SA15

DVDD

SA16

54

555657

-ETHRD

SD13

SD12

DVSS

DVDD

SD[0..7]

15

16

17

18

SD15

SD14

CSOUT

DMACK0

DMARQ0

DMACK2

DMACK1

DMARQ1

DVSS

DMARQ2

U7

CS8900A-CQ3

TQFP100

SD0

IOW

AEN (TCK)

IOCHRDY

64

SD1

656667

SD0

SD1

SA17

DVSS

585960

SA18

SA19

IOR

616263

DVDD

SD2

68

SD2

SD3

DVSS

CHIPSEL

SD3

DVDD

69

70

VDD

EESK

EECS

EEDATAIN

LINKLED/HC0

EEDATAOUT (TDO)

BSTATU S/HC1

SD4

SD5

SD6

DVSS

717273

74

SD4

SD5

SD6

SD7

V3.3

GND

R8

10k
0603

138239340441542643744845946104711481249135014

AVSS

ELCS

LANLED

XTAL2
XTAL1

AVSS

AVDD

AVSS

RXD-

RXD+

AVDD

AVSS

TXD­TXD+
AVSS

AVDD

DO+

SLEEP

TEST

SD7

RESET

75

RES

DO-

CI-

CI+

DI-

DI+

through-hole
solder pad
place near
FAST JACK

L1

ferrite
1210

do not stuff

100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76

C4
100nF
0603

-LANLED

-LINKLED

R12

RXD-

4k99/1%

RXD+

0603

TXD­TXD+

-SLEEP

int. Pull-Up

TXD-

R1

TXD+

R2

RXD- RD-

RXD+

JP4

HEADER 1
SIP1

1

CASEVSS

Y1

20.000 MHz
HC49

8R2
0603

8R2
0603

do not

stuff

R3
100
0603

TD-

C3
560pF
0603

TD+

RD+

-LANLED

-LINKLED

C5
100nF
0603

e

Dual-LED assembly,
right angle, grn/grn

LD1

green

upper LED

green

lower LED

5682F5;5
LED5682F

ESD protection array

RD+

RD-

U8

1

2

3

4 5

GND GND

CASE

1
2

CRD

3
4
5
6

8

CTD

shi el d

C6

100nF
0603

plane or
big trace

CASE

R9
100
0603

LCDA15C-6
SO8.150

910

J1

HFJ11-1041(E)
HALOFA STJACK

TX+ <- > 1
TX- <- > 2
RX+ < - > 3
RX- <- > 6

evelopment

User Manual

R10
100
0603

TD+

8

TD-

7

6

69

Figure 24. eZ80190 Module Schematic Diagram, #4 of 8—Ethernet Module

UM014108-0810 Schematic Diagrams

e

Z80190 D

Kit

don’t
stu

ff

=

SD[0..7]D[0..7]

SD[0..7]

SA[0..3]A[0..23]

A[0..23] SA[0..3]

CLK_OUT

-RD

-WR

-CSETH-CS3

-ETHRD

-ETHWR

VSS

VDD

D0
D1
D2
D3
D4
D5
D6
D7

SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7

-ETHWR

-WR

-CSETH

-RD

-CSETH

CLK_OUT CLK_OUT

-CSETH

CSETH_P

-WR

-RD

-ETHRD

-ETHWR

D[0..7]

A0
A1
A2
A3

CSETH_P

-CSETH1D

-CSETH1D -CSETH2D

SA0
SA1
SA2
SA3

-RD

-WR

-CS3

CLK_OUT

-ETHRD

-ETHWR

SD[0..7]D[0..7]

A[0..23] SA[0..3]

V3.3

GND

V3.3 V3.3

U11A

74LCX74
TSSOP14

2

3

5

6

41

D

CLK

Q

Q

PRCL

U11B

74LCX74
TSSOP14

12

11

9

8

1013

D

CLK

Q

Q

PRCL

R17
0R

0603

U5C

74LCX32
TSSOP14

9

10

8

U5B

74LCX32
TSSOP14

4

5

6

U6C

74LCX04
TSSOP14

5 6

U10

74LCX573
TSSOP20

2
3
4
5
6
7
8
9

11

1

19
18
17
16
15
14
13
12

D1
D2
D3
D4
D5
D6
D7
D8

LE
OE

Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8

R16
0R
0603

U9

74LCX543
TSSOP24

3
4
5
6
7
8
9

10

22
21
20
19
18
17
16
15

13
14
11

2
1

23

A0
A1
A2
A3
A4
A5
A6
A7

B0
B1
B2
B3
B4
B5
B6
B7

OEAB
LEAB
CEAB

OEBA
LEBA
CEBA

evelopment

User Manual

70

Figure 25. eZ80190 Module Schematic Diagram, #5 of 8—Ethernet Module Logic

UM014108-0810 Schematic Diagrams

Z80190 D

Kit

open-drain

{D0} /{D1}

HH

-RESET -RESET

VSS

VD D

IICSDA
IICS CL

IICSDA

IICS

CL

VBAT

RTC _VDD

RTC _VDD

IIC

SDA

IICS CL

RTC _VDD

-RESET

V3.3

V3.3

GND

V3.3

R20

0R
0603

R18
2k2
0603

C7
100nF
0603

C8
10nF
0603

R23

4k7
0603

U12

M A X6328U R 29
SOT-23-L3

2

1 3

RESET

GND VDD

C10
100nF
0603

U13

M 41T11M 6
SO 8.150

1
2

4

8

7

6

5

3

OSCI
OS CO

GND

V+

FT/OUT

SCL

SD A

VBAT

C11
unplace
0603

Y2

32.768kHz
XTA

L3

R22
4k7

0603

R21
4k7

0603

D1
TMM BAT 41

MINIM E LF_AK

R19

100
0603

power supervisor

real-time clock

alternative:
Maxim MAX6802UR29D3

Gold Cap
C9
0,1F
GOLDCAP_SD_V

I2C bus address:

e

evelopment

User Manual

71

UM014108-0810 Schematic Diagrams

Figure 26. eZ80190 Module Schematic Diagram, #6 of 8—Ethernet Module Peripherals

e

Z80190 D

Kit

NC

(* WAI T * )

PB6
PB4
PB2
PB0
PC7
PC5
PC3
PC1
PD7
GND_EXT
PD4
PD2
PD0
ZDA

EZ80CLK

GND_EXT

NOTUSED1
GND_EXT

-NMI

A6
A10
GND_EXT
A8
A13
A15
A18
A19
A2
A11
A4
A5

-DIS_ETH
A21
A22

-CS0

-CS2
D1
D3
D5
D7

-MREQ
GND_EXT

-WR

-BUSACK

A0
A3
V3.3_EXT
A7
A9
A14
A16
GND_EXT
A1
A12
A20
A17

-DIS_FLASH
V3.3_EXT
A23

-CS1
D0
D2
D4
GND_EXT
D6

-IOREQ

-RD

-INSTRD

-BUSREQ

PB7
PB5
PB3
PB1
GND_EXT
PC6
PC4
PC2
PC0
PD6
PD5
PD3
PD1

GND_EXT
ZCL
RTC_VDD
IICSCL
IICSDA

-FLASHWE

-CS3

-RESET
V3.3_EXT

-HALT

GND_EXT
GND_EXT

V3.3_EXT

A[0..23]

D[0..7]

-CS[0..3]

PB[0..7]

PC[0..7]

PD[0..7]

CLK_OUT

RTC_VDD

EZ80CLK

-FLASHWE

IICSDA
IICSCL

-RD

-WR

-IOREQ

-INSTRD

NOTUSED1

-HALT

-BUSREQ

-BUSACK

-NMI

V3.3_EXT

ZDA
ZCL

GND_EXT

-MREQ

-DIS_FLASH

-RESET

-DIS_ETH

GND_EXT V3.3_EXT V3.3_EXT GND_EXT

PA1

PA3

PA5

PA7 PA6

PA4
PA2
PA0

PA[0..7]

D[0..7]

A[0..23]

-CS[0..3]

PB[0..7]

PC[0..7]

PD[0..7]

-RESET

RTC_VDD

IICSDA

ZDA
ZCL

IICSCL

CLK_OUT

-RD

-WR

-IOREQ

-MREQ

-INSTRD

-BUSACK

-NMI

-DIS_ETH

-FLASHWE

-DIS_FLASH

-BUSREQ

-HALT

PA[0..7]

V3.3

GND

R24

33 0603

R28
10k

0603

R27
10k

0603

R29
10k

0603

R26

2k2
0603

R25
10k

0603

JP1

Header 30x2

12
34
56
78
910
11 1 2
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60

JP2

Header 30x2

12
34
56
78
910
11 1 2
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60

peripheral bus
connector

I/O connector

Pin 50 open,
to be keyed

place near eZ80
output (PHI)

connector 1 connector 2

evelopment

User Manual

72

Figure 27. eZ80190 Module Schematic Diagram, #7 of 8—Headers

UM014108-0810 Schematic Diagrams

Z80190 D

Kit

unused gates

GND

V3.3 VDD

VSS

U5D

74LCX32
TSSO P14

12

13

11

C12
22uF
SMT7343

C13
22uF
SMT7343

C14
1nF
0603

C15
100nF
0603

C16
1nF
0603

C17
100nF
0603

PCB1

eZ80190 ethernet module board
98Cxxxx-xxx

U6D

74LCX04
TSSOP14

9 8

U6E

74LCX04
TSSOP14

11 10

U6F

74LCX04
TSSOP14

13 12

no power supply on board

Input: VDD ( = V3.3) = 3.3V –5%
Power: Pmax = tbd
Ptyp = tbd
Current: lmax = tbd
ltyp = tbd

common power plane

common ground plane

e

evelopment

User Manual

73

Figure 28. eZ80190 Module Schematic Diagram, #8 of 8—Power Supply

UM014108-0810 Schematic Diagrams

Appendix A

General Array Logic Equations

This appendix shows the equations for disabling the Ethernet signals pro­vided by the U10 and U15 General Array Logic (GAL) devices.

U10 Address Decoder

//`define idle 2'b00
//`define state1 2'b01
//`define state2 2'b11
//`define state3 2'b10
// FOR eZ80
// This PAL generates 4 memory chip selects

module l92_decod(

nCS_EX, // Enables Extension Module's Memory

nFL_DIS, // when Low Module Flash is

nCS0,
A7, //A23
A6, //A22
A5, //A21
A4, //A20
A3, //A19
A2, //A18

®

Development Platform Rev B

// when Low

// disabled (nDIS_FL=0),
// when High nDIS_FL depends upon
// state of nmemenX

eZ80190 Development Kit

User Manual

74

UM014108-0810 General Array Logic Equations

eZ80190 Development Kit
User Manual

75

A1, //A17
A0, //A16
nCS2,
nEX_FL_DIS, // disables Flash on the expansion

// module, when Low

nEM_EN, // enables Development Platform LED

// and the general-purpose port.
nDIS_FL, // disables Module Flash when Low
nL_RD, // enables local data bus to be read

// by CPU
nmemen1,
nmemen2,
nmemen3,
nmemen4
);

input

nFL_DIS /* synthesis loc="P4"*/,
nCS0 /* synthesis loc="P5"*/,
nCS2 /* synthesis loc="P3"*/, //was 23
A7 /* synthesis loc="P6"*/,
A6 /* synthesis loc="P7"*/,
A5 /* synthesis loc="P9"*/,
A4 /* synthesis loc="P10"*/,
A3 /* synthesis loc="P11"*/,
A2 /* synthesis loc="P12"*/,
A1 /* synthesis loc="P13"*/,
A0 /* synthesis loc="P16"*/,
nEX_FL_DIS /* synthesis loc="P2"*/;

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//input[7:0] A;upper part of Address Bus of 190

//A23=A7,A22=A6,A21=A5,A20=A4,A19=A3
//A18=A2,A17=A1,A16=A0

output

nCS_EX /* synthesis loc="P17"*/,//enables
memory on the

// Expansion Module

nmemen1 /* synthesis loc="P18"*/,//enables
memory on

// the Development Platform
nmemen2 /* synthesis loc="P19"*/,
nmemen3 /* synthesis loc="P20"*/,
nmemen4 /* synthesis loc="P21"*/,
nEM_EN /* synthesis loc="P24"*/,//enables

LED and the

// general-purpose port.
nDIS_FL /* synthesis loc="P25"*/,
nL_RD /* synthesis loc="P23"*/
;

76

wire nCS_EX,

nmemen1,
nmemen2,
nmemen3,
nmemen4;

//wire MOD_DIS =

((nmemen1==0)|(nmemen2==0)|(nmemen3==0)|(nmemen4==0)
);//if any

//of the signals is Low,

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wire nEXP_EN = ~((nCS0==0)&(A7==0)&(A6==1));//

//wire nDIS_FL = (nFL_DIS) ? ~nEXP_EN : ~(nFL_DIS);

wire nDIS_FL = nFL_DIS & nEXP_EN; //if either of them

assign nCS_EX = (nEX_FL_DIS) ? nEXP_EN :

assign nL_RD =

assign nmemen4 =

assign nmemen3 =

assign nmemen2 =

assign nmemen1 =

assign nEM_EN =

endmodule

//Flash on the Module will be
//disabled if nDIS_FL is High

expansion module

//Flash enabled if this is 0

is 0 Flash is

//disabled

~(nEX_FL_DIS);

~((nmemen1==0)|(nmemen2==0)|(nmemen3==0)|(nmemen4==0
)|(nEM_EN==0)|(nCS_EX==0));

~((nCS2==0)&({A7,A6,A5,A4,A3}==5'h17));

~((nCS2==0)&({A7,A6,A5,A4,A3}==5'h16));

~((nCS2==0)&({A7,A6,A5,A4,A3}==5'h15));

~((nCS2==0)&({A7,A6,A5,A4,A3}==5'h14));

~((nCS2==0)&({A7,A6,A5,A4,A3,A2,A1,A0}==8'h80));

U15 Address Decoder

`define anode 8'h00

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`define cathode 8'h01
`define latch 8'h02
// FOR eZ80
// This PAL generates signals that control Expansion

Module

// access, LED and the general-purpose port.
// This device is a GAL22LV10-5JC (5ns tpd) or

equivalent with

// Package = 28 pin PLCC
//
//

module l92_em_pal(

nDIS_EM,
nEM_EN,
A0,
A1,
A2,
A3,
A4,
A5,
A6,
A7,
nRD,
nCS,
nWR,
nMEMRQ,
nIORQ,
nEM_RD,
nEM_WR,

®

Development Platform Rev B

78

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input nDIS_EM /* synthesis loc="P3"*/,

nAN_WR,
nCT_WR,
nDIS_ETH
);

nEM_EN /* synthesis loc="P4"*/,
A0 /* synthesis loc="P5"*/,
A1 /* synthesis loc="P6"*/,
A2 /* synthesis loc="P10"*/,
A3 /* synthesis loc="P11"*/,
A4 /* synthesis loc="P12"*/,
A5 /* synthesis loc="P13"*/,
A6 /* synthesis loc="P27"*/,
A7 /* synthesis loc="P26"*/,
nIORQ /* synthesis loc="P2"*/,
nRD /* synthesis loc="P7"*/,
nCS /* synthesis loc="P25"*/, //CS3 for CS9800
nWR /* synthesis loc="P9"*/,
nMEMRQ /* synthesis loc="P16"*/;

output

nEM_RD /* synthesis loc="P17"*/,
nEM_WR /* synthesis loc="P18"*/,
nCT_WR /* synthesis loc="P19"*/,
nAN_WR /* synthesis loc="P20"*/,
nDIS_ETH /* synthesis loc="P21"*/;

parameter anode=8'h00;
parameter cathode=8'h01;

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parameter latch=8'h02;

wire [7:0] address={A7,A6,A5,A4,A3,A2,A1,A0};

assign nEM_WR =

~((nDIS_EM==1)&(nWR==0)&(nEM_EN==0)&(address==latch)
);

assign nEM_RD =

~((nDIS_EM==1)&(nRD==0)&(nEM_EN==0)&(address==latch)
);

assign nAN_WR =

~((nDIS_EM==1)&(nWR==0)&(nEM_EN==0)&(address==anode)
);

assign nCT_WR =

~((nDIS_EM==1)&(nWR==0)&(nEM_EN==0)&(address==cathod
e));

80

assign nDIS_ETH = ~(nCS);
endmodul

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General Array Logic Equations UM014108-0810

Customer Support

For answers to technical questions about the product, documentation, 
or any other issues with ZiLOG’s offerings, please visit ZiLOG’s Knowl­edge Base at http://www.zilog.com/kb

For any comments, detail technical questions, or reporting problems,
please visit ZiLOG’s Technical Support at http://support.zilog.com

eZ80190 Development Kit

User Manual

82

.

.

UM014108-0810

DO NOT USE IN LIFE SUPPORT

Warning:

LIFE SUPPORT POLICY

ZiLOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE
EXPRESS PRIOR WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF ZiLOG CORPORATION.

As used herein

Life support devices or systems are devices which (a) are intended for surgical implant
into the body, or (b) support or sustain life and whose failure to perform when properly
used in accordance with instructions for use provided in the labeling can be reasonably
expected to result in a significant injury to the user. A critical component is any
component in a life support device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or system or to affect its safety or
effectiveness.

Document Disclaimer

©2010 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the
devices, applications, or technology described is intended to suggest possible uses and
may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR
PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION,
DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO
DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY
INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION,
DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The
information contained within this document has been verified according to the general
principles of electrical and mechanical engineering.

Z8, Z8 Encore!, eZ80, and eZ80Acclaim!, and Z8 Encore! XP are register ed tra d em arks of ZiLOG, Inc. All
other product or service names are the property of their respective owners.