Zebra Technologies 211486030A User Manual

148603 Project Document

Motorola Solutions Inc.

Title:

148603 Specification and Integration Guide

Description/Abstract/Synopsis:

The purpose of this document is to provide an integration guide targeted for module integrators who have an NDA with Motorola Solutions.

Document Status:

In Progress

A

[ ] – Released Version

MPA Document Number:

[ ] – Next Release In Process

NA

Division:

Sub-team:

[ ] – Document Obsolete

Working Revision: 20110610-i

MCD

RF-SYS

Obsolete Document Replaced By:

Last Updated: 01/18/2012

Document Type:

SPEC / IG

N/A

Confidentiality Statement:

Classification: N/A

[] - Contains Motorola Solutions partner NDA related material (Disclosure requires a three-way NDA.)

Partner Name

Agreement Number

USI

Under NDA and Motorola Corporate Supply Agreement between Motorola Solutions and USI

[] - For Motorola Solutions Internal Use Only

[ x] - Disclosure allowed under Motorola Solutions NDA Only

[x] - Does or may contain Motorola Solutions patentable property

*** Direct this document‟s disclosure inquires to (Job Title):

TNT Archive Location/Path: Agile

Current Owner:

Authors / Contributors:

Revision History

148603 Project Document

Rev #

Author

Date

Notes

Supporting or Reference Documentation

MPA or Motorola Solutions Document Number

Title

Release Signatures Required Divisional Role

Motorola Solutions Associate

Copyright Information

No part of this document may be reproduced, stored in or introduced into a retrieval system, or transmitted in any form or by any means (electronic, mechanical, photocopying, recording, or otherwise) for any purposes, without the express written permission of Motorola Solutions, Inc.

Motorola Solutions, Inc. may have patents, patent applications, trademarks, copyrights, or other intellectual property rights covering subject matter in this document. Except as expressly provided in any written license agreement from Motorola Solutions, Inc., the furnishing of this document does not give you any express or implied rights to these patents, trademarks, copyrights, or other intellectual property. © 2011 Motorola Solutions, Incorporated. All rights reserved.

MPA Project Document

Table of Contents

1. INTRODUCTION 6

1.1. BACKGROUND 6

1.2. GENERAL NOTE 6

1.3. PURPOSE 6

1.4. PART NUMBERS 6

2. ARCHITECTURE 7

2.1. WLAN 7

2.1.1. HOST COMMUNICATIONS 7

2.2. BLUETOOTH 7

2.3. GPS 9

2.4. POWER SUB-SYSTEM 9

3. SIGNAL DESCRIPTIONS 10

3.1. SIGNAL DESCRIPTIONS 10

3.1. PIN LAYOUT 13

4. DESIGN GUIDELINES AND RECOMMENDATIONS 14

4.1. TYPICAL APPLICATION SCHEMATIC 14

4.2. HOST PCB LAYOUT RECOMMENDATIONS 17

5. HOST REQUIREMENTS 18

5.1. ELECTRICAL POWER 18

5.2. ENVIRONMENTAL 18

5.2.1. ABSOLUTE MAXIMUM RATINGS 18

5.2.2. NORMAL OPERATING CONDITIONS 19

5.4. TIMING REQUIREMENTS 21

5.4.1. POWER UP TIMING 21

5.4.1.1. WLAN 21

5.4.1.2. BT/GPS/FM 21

5.4.2. SDIO TIMING REQUIREMENTS 22

5.4.2.1. SDIO DATA SWITCHING CHARACTERISTICS 22

5.4.2.2. SDIO DATA SWITCHING CHARACTERISTICS 22

5.4.2.3. SDIO SWITCHING CHARACTERISTICS 23

5.5. ANTENNA REQUIREMENTS 24

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5.5.1. WLAN 24

5.5.2. BT 24

5.5.3. GPS 25

6. MODULE SPECIFICATIONS 26

6.1. POWER CONSUMPTION 26

6.1.1. WLAN POWER CONSUMPTION 27

6.1.2. BT POWER CONSUMPTION 28

6.1.3. GPS POWER CONSUMPTION 28

7. APPENDIX 29

7.1. RECOMMENDED HOST PCB PASTEMASK 29

7.2. MECHANICAL INTERFACE DRAWING 30

7.3. REGULATORY 30

7.3.1. CE REGULATIONS 30

7.3.2. FCC REGULATIONS 31

7.3.3. IC REGULATIONS 33

Table of Figures

Figure 1 - Pin Map 13 Figure 2 – TOP VIEW Recommended Option 3) Solid ground beneath the specific module areas 17 Figure 3 - Recommended host PCB PasteMask 29

Table of Tables

Table 1 - Module Part Numbers and Description ............................................................ 6

Table 2 – Signal Descriptions ........................................................................................ 10

Table 3 - Typical Application Schematic BOM .............................................................. 15

Table 4 - Absolute Maximum Ratings ............................................................................ 18

Table 5 - Normal Operating Conditions ......................................................................... 19

Table 6 - Slow Clock Requirements .............................................................................. 20

Table 7 - SDIO Single Block Read ................................................................................ 22

Table 8 - SDIO Interface Read ...................................................................................... 22

Table 9 - SDIO Single Block Write ................................................................................ 22

Table 10 -SDIO Interface Write ..................................................................................... 22

Table 11 – SDIO Timing ................................................................................................ 23

Table 12 - SDIO Timing ................................................................................................. 23

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Table 13 - WLAN Antenna Requirements ..................................................................... 24

Table 14 - Bluetooth Antenna Requirements ................................................................ 24

Table 15 - GPS Antenna Requirements ........................................................................ 25

Table 16 - Hardware Low Power Mode - Module Shutdown (SDWN) Current Draw ..... 26

Table 17 - BT Power Consumption ............................................................................... 28

Table 18 - GPS Power Consumption ............................................................................ 28

148603 Project Document

Part Number

SKU

21-148603-01

Diversity version with WLAN and BT

on SHARED RF paths

21-148603-02

Diversity version with WLAN and BT

on SEPARETE RF paths

21-148603-03

NON-Diversity version with WLAN and

BT on a SHARED RF path

21-148603-04

NON-Diversity version with WLAN and

BT on SEPARETE RF paths

1. Introduction

1.1. Background

148603 is a radio module that will provide Wireless Local Area Network (WLAN) Bluetooth, GPS and FM features to Motorola Solutions‟ EMS products.

NOTE: FM is DISABLED in all revisions, and WLAN RF0 Path is not populated in the -01 and -02 versions.

1.2. General Note

This is a living document. Some descriptions are based on the current phase of the

148603 module design program. Changes to this document will occur without direct

notification to its users. Users who wish to have the latest information should coordinate with the module team leader. The terms “preferred” and “recommend” are used throughout this document. Preferred can be thought of as a “nice-to-have” or “in-

good practice”. The term “recommendation” should be taken as a stronger

implementation guideline where if not implemented performance degradation may occur.

1.3. Purpose

The purpose of this document is to provide a guide targeted for module integrators who have an NDA with Motorola Solutions.

1.4. Part Numbers

Table 1 - Module Part Numbers and Description

148603 Project Document

2. Architecture

2.1. WLAN

2.1.1. Host Communications

The WLAN core requires a total of eight (8) dedicated signals in order to communicate to the host processor. The WLAN core is enabled via the WL_EN signal (1) and communicates to the host processor via SDIO (6) with an additional interrupt signal WL_IRQ(1).

2.1.1.1. Hardware Interface

The interface between the host and the 148603 Module is a standard SDIO interface (see SDIO spec version 2.0), supporting maximum clock rate of 52MHz.

The WL1281/3 SDIO also supports the following features:

• Both 1 and 4 bit data bus

• Abort command

• Multi-Block data transfer

• The SDIO interface is used for WLAN IP only.

• The SDIO interface supports High Speed protocol.

2.2. Bluetooth

2.2.1. Host Communications

The Bluetooth subsystem requires nine (9) connections to the host in order for full operation, including PCM (4), High-Speed UART (4) and BT_GPS_FM_EN (1) , which shall be connected to the host to enable the Bluetooth IP. It should also be noted that an additional line from the WL1283 can be used for debug purposes, namely BT_UART_DBG.

2.2.1.1. Hardware Interface

2.2.1.1.1. HCI UART Transport layers The HCI UART Supports 4-wire UART interface to host. Supports most baud rates for all fast clock frequencies, up to a maximum of 4Mbps. Default baud rate after power up is 115.kkbps with a deviation of +1.5%, -2.5%, until baud is changed via a vendor specific command.

148603 Project Document

o BT_GPS_FM_TX o BT_GPS_FM_RX o BT_GPS_FM_RTS o BT_GPS_FM_CTS

2.2.1.1.2. PCM Audio

PCM audio interface to the host uses the following signals: In Slave mode, input frequencies up to 16MHz supported. In master mode, the TI1283 can generate any clock frequency between 64KHz and 4.096MHz.

o BT_PCM_OUT o BT_PCM_IN o BT_PCM_SYNC o BT_PCM_CLK

The BT Audio Codec has a fully dedicated programmable serial port

o Two voice channels o Supports Master/slave modes o u-law, a-law, linear and transparent coding schemes o Long and short frames o Different data sizes, order and positions o UDI profile o High rate PCM

2.2.2. Power Class

148603 supports up to Power Class 1.5 Operation.

2.2.3. 148603 BT RF Paths

The 148603 design will be the first internal module to integrate a PTA and selection diversity antenna structure over the same RF paths. Due to the development cycle and

schedule, at the time of the release of the module‟s engineering design, this timing was

not fully understood. Consequently, the 148603 team designed in a provision that would allow the BT RF to be available through a separate RF port. Should this population option need to be used, external matching and filtering would be required and support from the 148603 module team should be sought when implementing this option.

 IMPORTANT NOTE: A tradeoff performance evaluation is currently being

conducted to demonstrate the ability to break-out the BT RF from the WL1283 to the 148603 Module pins, bypassing the FEM and disabling PTA.

148603 Project Document

2.3. GPS

The GPS hardware interface shares the BT UART hardware interface as described in Section Error! Reference source not found.. On power up, the core is disabled by default and will remain in this state until host enables it by setting BT_GPS_FM_EN and writing Vendor Specific commands to turn on GPS via the shared transport.

2.4. Power Sub-System

The 148603 requires two external voltage sources a VBAT=3.3V nominal and a VIO=1.8V nominal. The VBAT is used to supply voltage to the SoC, FEM, and antenna selection control logic. The VIO is used to supply voltage to the SoC and provide level detection to the antenna switch control logic. The SoC incorporates an internal 1.8V that is used to supply the internal Soc 1.8V rail as well as power to the 26MHz TCXO.

2.5. Internal Clock Frequencies

The 148603 has on-module TCXO operating at 26MHz

2.5.1. WLAN WLAN has an Zero-IF architecture and thus the LO operates at ~10GHz that is divided by 2 for 5G Band operation and divided by 4 for 2.4GHz Band operation.

2.5.2. BT The TCXO is used to produce the relevant BT channel, between 2.402G to 2.480GHz. The ADPLL produces the frequencies between 4.804GHz to 4.96GHz, which divided by 2 to provide the BT frequencies.

2.5.3. GPS The LO frequency for GPS is 1579.5MHz.

2.5.4. FM The FM IP generates the FM station frequency from the divided FREF clock or by the 32K clock. It is generated by the Synthesizer and ADPLL. The FM channel frequency band is between 76-108MHz (Europe and Japan).

NOTE: FM is DISABLED.

148603 Project Document

PIN DEFINE REV

0.02

Module

Pin Name

Pin # I/O

Type

Function

Connects

to

SD State

Default State (after POR)

Buffer

[mA]

Description

VBAT1

68

PWR

GEN

PWR

VBAT 3.3V Input

VBAT2

69

PWR

GEN

PWR

VBAT 3.3V Input

VBAT3

70

PWR

GEN

PWR

VBAT 3.3V Input

VBAT4

71

PWR

GEN

PWR

VBAT 3.3V Input

VIO1

16

PWR

GEN

PWR

VIO 1.8V Digital Voltage

VIO2

17

PWR

GEN

PWR

VIO 1.8V Digital Voltage

GND1

6

GND

GEN

GND

Ground Pin

GND3

8

GND

GEN

GND

Ground Pin

GND4

10

GND

GEN

GND

Ground Pin

GND5

11

GND

GEN

GND

Ground Pin

GND6

13

GND

GEN

GND

Ground Pin

GND7

14

GND

GEN

GND

Ground Pin

GND8

15

GND

GEN

GND

Ground Pin

GND9

18

GND

GEN

GND

Ground Pin

GND10

23

GND

GEN

GND

Ground Pin

GND11

30

GND

GEN

GND

Ground Pin

GND12

33

GND

GEN

GND

Ground Pin

GND13

36

GND

GEN

GND

Ground Pin

GND14

38

GND

GEN

GND

Ground Pin

GND15

41

GND

GEN

GND

Ground Pin

GND16

43

GND

GEN

GND

Ground Pin

GND17

46

GND

GEN

GND

Ground Pin

GND18

48

GND

GEN

GND

Ground Pin

GND19

50

GND

GEN

GND

Ground Pin

GND20

54

GND

GEN

GND

Ground Pin

GND21

60

GND

GEN

GND

Ground Pin

GND22

67

GND

GEN

GND

Ground Pin

3. Signal Descriptions

3.1. Signal Descriptions

Listed below are the pin numbers and signals on the 148603 module. GEN = General (No specific function), PWR= Power Supply, ANA= Analog

NOTE: FM is DISABLED in all revisions, and WLAN RF0 Path is not populated in the -01 and -02 versions.

Table 2 – Signal Descriptions

148603 Specification and Integration Guide

148603 Project Document

GND23

72

GND

GEN

GND

Ground Pin

GND_H

73

GND

GEN

GND

Ground Pin Heat Sink Pad

WL_EN

32

IN

WLAN

HOST

PD

N/A

WLAN IP enable (0=not active, 1=host enable WLAN IP)

SDIO_CLK

25

IN

WLAN

HOST

HiZ

4

WLAN SDIO clock. Place signal conditioning resistor on SDIO_CLK close to host processor

SDIO_CMD

24

I/O

WLAN

HOST

HiZ

HiZ 8/6/4/2

SDIO command in. SDIO lines must be pulled up by the host.

SDIO_D0

26

I/O

WLAN

HOST

HiZ

HiZ 8/6/4/2

SDIO data bit 0. SDIO lines must be pulled up by the host.

SDIO_D3

28

I/O

WLAN

HOST

PD

HiZ 8/6/4/2

SDIO data bit 3. SDIO lines must be pulled up by the host.

SDIO_D1

29

I/O

WLAN

HOST

HiZ

HiZ 8/6/4/2

WLAN SDIO data bit 1. SDIO lines must be pulled up by the host.

SDIO_D2

27

I/O

WLAN

HOST

HiZ

HiZ 8/6/4/2

WLAN SDIO data bit 2 . SDIO lines must be pulled up by the host.

WLAN_IRQ

58

OUT

WLAN

HOST

PD

Drive 0

4

WLAN Interrupt out. Active low.

WL_RS232_TX

66

OUT

WLAN

DEBUG

PU

Drive 1

4

RTT tool UART output

WL_RS232_RX

65

IN

WLAN

DEBUG

PU

PU 4 RTT tool UART input

WL_UART_DBG

57

OUT

WLAN

DEBUG

PU

Drive 1

4

WLAN Logger output UART output

JTAG_TMS

62

IN

WLAN

DEBUG

PU

PU 4 JTAG Test Mode State Input

JTAG_TDO

61

OUT

WLAN

DEBUG

PU

Drive 1

4

JTAG Test Data Out Output

JTAG_TDI

64

IN

WLAN

DEBUG

PU

PU 4 JTAG Test Data In Input

JTAG_TCK

63

IN

WLAN

DEBUG

PD

PD 4 JTAG Test Clock Input

RF2

9

RF

WLAN/BT

ANT

RF

Default WLAN RF Port (Shared with BT using -01 Module Configuration) 50Ω Termination if not used.

RF1

12

RF

WLAN/BT

ANT

RF

Auxiliary WLAN RF Port (Shared with BT using -01 Module Configuration) 50Ω Termination if not used.

RF0

7

RF

GEN

GND

RF

Diversity Bypass Path. WLAN RF Port (Shared with BT using -03 Module Configuration) This path is mutually exclusive with RF1 and RF2. RF0 Path

is not populated in the -01 and -02 versions. 50Ω Termination if not used.

BT_GPS_FM_EN

53

IN

BT/GPS/FM

HOST

PD*

N/A

Bluetooth IP enable (0=not active, 1= host enable Bluetooth IP (GPS and FM active through VS commands)

BT_GPS_FM_TX

19

OUT

BT/GPS/FM

HOST

PU

Drive 1

4

HCI UART transmit output

BT_GPS_FM_RX

20

IN

BT/GPS/FM

HOST

PU

PU 4 HCI UART receive input

BT_GPS_FM_CTS

21

IN

BT/GPS/FM

HOST

PU

4

HCI UART clear to send input (active low)

BT_GPS_FM_RTS

22

OUT

BT/GPS/FM

HOST

PU

Drive 1

4

HCI UART request to send (active low). Signal IRQ asserted until cleared by host.

148603 Specification and Integration Guide