ZARLINK ZL10310, ZL10311 DATA SHEET

查询ZL10311供应商

ZL10310/ZL10311

Digital Television DVB-T-On-a-Chip

Processor

Data Sheet

Features

• DTV-SoC for Digital Terrestrial Television (DTT)

• On-chip DVB-T COFDM demodulator with FEC.

• 6 Video DACs on-chip, for Composite or Component (RGB or Y U/V) Analog Video

• Twin PAL/NTSC DENCs

• Low Power (<1.4W Typical)

• Low Component Count

• Unified SDRAM controller

S Digital Audio Input

•I

S and S/PDIF Digital Audio outputs

• MPEG-2 Audio & Video decoders

• PowerPC 405 Memory manager and Virtual memory system

• Complete Linux-based Software Development Kit (SDK)

•IDE interface

• Inputs for external MPEG-2 Transport Streams, allowing support for external demodulators (e.g. Cable TV, Satellite TV)

• Conditional Access (CA) DVB-descrambler

CPU Core with 16k/16k cache,

Issue 1.0 November 2002

Ordering Information

ZL10310/GAC 388 ball EPBGA

ZL10311/GAC 388 ball EPBGA

C to +700C

• Smart Card Interface

• Infrared & UART interface

• DVB-compatible Common Interface (CI) control and bitstream interfaces

• Multi-stream multiplexing to support internal and external demodulators

• External Modem support interface

• Supports Macrovision

Copy Protection -

(ZL10311 only; available to Macrovision license

holders only)

•Dolby



Digital* Decoding - (ZL10311 only;

available to Dolby



Digital* license holders only -

*awaiting certification)

Bitstream

O/P

/Second

Smart Card

Bitstream

I/P

De-mod

/JTAG

ADC IN

/De-mod

AGC B

Flash

IDE

CI Control

Smart Card

CODEC/modem

I C

UART/IRDA

BIT I/O

Stereo Audio

ZL10310 / ZL10311 DTV-SOC

EXTIN

JTAG

ADCIN

AUX Bus

PowerPC 405

Sub System

Peripherals

Power Management

Cached

COFDM

DeModulator

& FEC

8k Boot

ROM

Multiplexing &

SDRAM

Controller

SDRAM 1

BUS

Bitstream

Control

De-

scrambler

SDRAM

Controller

SDRAM 0

BUS

(optional)

Audio

Decoder

System

DeMultiplex

Video

Decoder

Video Scaler

/ Blender

Comp Video

Video DENCs /DACs

Y+U/V

RGB

I S

DAC

S/PDIF

Analog Video

Figure 1 - Block Diagram of ZL10310 and ZL10311

ZL10310/ZL10311 Data Sheet

Applications

• Low power, small footprint TV adaptors

• Integrated Digital Televisions (iDTV)

• Digital terrestrial set-top boxes

• DTT / DVD Combo

• DVB-T radio receivers

• Terrestrial / Satellite Combo

• Terrestrial / Cable Combo

• Terrestrial / IP (Internet Protocol) Combo

Description

Zarlink Semiconductor has responded to market demand by integrating its key DVB-T compliant COFDM demodulation technology with Set Top Box functionality (MPEG-2 A/V decoder and system interfaces) together with a high performance CPU to offer a “DVB-T On-a-Chip” solution.

The ZL10310 DVB-T On-a-Chip, can address a wide range of DVB-T consumer electronic products. At the entry level it can be used to build ultra-compact Free-To-View Digital TV adaptors (such as for FreeView in the UK), yet consumes less than 4W of power in full operational mode.

This level of compactness also considerably eases the integration of DVB-T receiver technology inside integrated Digital TV sets (iDTV’s) where space considerations and thermal management are key design issues.

The ZL10310 is based upon an industry standard PowerPC 405 Management sub-systems. This permits the device to be effectively deployed in compelling applications such as interactive Digital TV which are able to exploit the superior processing performance offered by the PowerPC processor core.



The PowerPC

provides an ideal platform for running robust open standard operating systems such as Linux which

can benefit system developers in a number of key areas:

RISC processor, which has Virtual and Memory



• Unified software development environment, from entry level basic channel zapper systems through to fully interactive high performance Digital Set Top Boxes.

• Re-use of software code from multiple projects

• Exploit software code developed in the Linux community.

• Low cost-per-seat software development environment.

• Familiar software development environment.

• Royalty free.

Also available is the ZL10311 DVB-T On-a-Chip, which additionally offers Dolby decoding, and Macrovision

Copy Protection for applications requiring Dolby Audio and Pay TV services.



Digital1 multi-channel audio

1. The ZL10311 device is awaiting Dolby Certification

2 Zarlink Semiconductor Inc.

Data Sheet ZL10310/ZL10311

Table of Contents

1.0 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.0 Device Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3.0 Typical Digital Television (DTV) Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4.0 Functional Blocks Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4.1 Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4.2 Clock Generation Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4.3 Coded Orthogonal Frequency Division Multiplex (COFDM) Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . 7

4.4 MPEG Audio Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4.5 MPEG-2 Video Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.6 PowerPC 405TM Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.7 Transport Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.8 Video Display System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5.0 Physical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

6.0 ZL10310/ZL10311 388-pin Package Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

6.1 Pin Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

6.2 Front End Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

6.3 Video DAC Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.4 SDRAM Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.5 Bit Stream Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.6 Auxiliary External Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.7 Peripheral Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.8 Modem/Codec Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.9 Smart Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.10 General Purpose Input Output Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.11 Simplified General Purpose Input Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.12 Inter Integrated Circuit (I2C) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.13 Inter IC Sound (I2S) Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.14 Clock and Reset Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.15 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.16 Reserved Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.0 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.1 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

IBM

, the IBM Logo, PowerPC® and PowerPC405TM are trademarks of International Business Machines

Corporation.



Dolby

is a trademark of Dolby Laboratories. Supply of this implementation of Dolby Technology does not convey a license or imply a right under any patent, or any other Industrial or Intellectual Property Right of Dolby Laboratories, to use this implementation in any finished end-user or ready-to-use final product. It is hereby notified that a license for such use is required from Dolby Laboratories

This device is protected by US patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. Use of the Macrovision anticopy process in the device is licensed by Macrovision for non-commercial, home and limited exhibition use only. Reverse engineering or disassembly is prohibited. A valid Macrovision license must be in effect between the purchaser of the ZL10311 IC and Macrovision Corporation. Additional per-chip royalties may be required and are payable by the purchaser to Macrovision.

1. The ZL10311 device is awaiting Dolby Certification

3Zarlink Semiconductor Inc.

ZL10310/ZL10311 Data Sheet

1.0 Device Overview

Zarlink Semiconductor has designed the ZL10310 and ZL10311 System On a Chip (SoC) devices specifically for DVB-T applications. Integrating a high performance PowerPC 405 MPEG-2 audio and video decoding, OSD and a COFDM demodulator, the ZL10310 and ZL10311 deliver the performance and functionality required for advanced Digital TV entertainment products. It enables the rapid design and manufacture of cost-effective iDTV and Digital Audio Visual Home Entertainment Centers.

The enhanced ZL10311 also supports DVD playback with up to six Dolby integrating the COFDM demodulator, the ZL10310 and ZL10311 enable the implementation of very small footprint TV Adaptor modules.

2.0 Device Interfaces

The following peripheral interfaces are available to the user. Apart from possible level translation and connector buffering, no external devices are required to support any of the interfaces.

• 10-bit input that may be configured for an ADC input to the internal COFDM demodulator

• Additional input bus for additional MPEG-2 Transport Sources

• AGC (PWM) outputs for a terrestrial tuner

• Serial control port for a digital tuners

• Common interface control and bitstream interfaces for an external descrambler

• Normal PC (PCMCIA) memory module interface for local software updates

• Unified 64 Mbit SDRAM interface for all decoders and PowerPC 405

• Additional SDRAM interface for high end systems requiring increased memory bandwidth

• Static memory interface for Flash and external peripherals

• IDE/ATAPI interface for hard disk and DVD drives

• External DMA channel and interrupts

• Six analog video outputs give full flexibility on RGB, S-VHS, and composite signals (with and without OSD)

S input port from external Digital Stereo source

•I

•Three I

•Dolby

• Sony/Philips Digital InterFace (S/PDIF)

S ports to external audio DACs for main, surround, and centre channels



surround sound control signals

processor with robust industry proven



Digital1 audio channels. In addition, by

If not required in a particular system, any of the peripheral interfaces can be replaced by individual I/O bits from internal general purpose registers. These can then be used for additional purpose, such as interfacing to switches and displays.

• Full RS232 interface to an external modem or a 4 wire interface to a Codec

• IRDA interface or an additional asynchronous serial interface

• Synchronous serial interface for EEPROM, etc.

• Two Smart card Interfaces (one instead of a Common Interface)

• General purpose I

C interface

• General purpose timer for Infrared (IR) decoding

• General purpose individual bit I/Os

1. The ZL10311 device is awaiting Dolby Certification

4 Zarlink Semiconductor Inc.

Data Sheet ZL10310/ZL10311

InfraRed Sens or

Analog Video

Terrestrial

Tuner

Tuner Control

A D C

20.48MHz

ADCIN

AGC B

ADCCLK

COFDM

Clock

20.48MHz Crystal

Oscillator

ZL10310

DTV-SOC

CLK 27IN

Error

Aux Bus

27MHz

VCXO

Aux Bus

FLASH

Digital Audio

8MB

(I S)

Common Interface

SDRAM1

Bus

Figure 2 - Block diagram of a typical ZL10310-based Free to Air TV Adaptor

Comp Video

RGB or Y U/V

D A

Analog Audio

Serial

EEPROM

Bitstream o/ps

Bitstream i/ps

SDRAM

External Peripherals

3.0 Typical Digital Television (DTV) Receiver

Figure 2 shows a typical Free to Air TV receiver block diagram employing a ZL10310 DTV-SoC device. In its minimal configuration, the ZL10310 DTV-SoC device only requires a single 64 Mbit SDRAM, an audio DAC, and a Flash ROM, which are in addition to a DVB-T tuner front end and a 10-bit analog to digital converter.

The Terrestrial Tuner section performs an independent down conversion of the received DVB-T signal from the Antenna, to an IF frequency in the range of 30MHz to 57MHz, dependent on television system (typically 36.17MHz Center Frequency, with ±4MHz span). The analogue IF is then converted to the digital domain, with a 10-bit ADC, clocked at 20.48MHz and the resulting Digital output is centered on 15.69MHz. This Digital signal is applied to the ZL10310 via the ADC_IN[9:0] input pins, in the form of a 10-bit parallel signal.

The ZL10310 converts the digitized IF from a Terrestrial TV Tuner into an MPEG-2 Transport Stream, which can be optionally de-scrambled (if CA scrambling is used by the broadcaster), and de-multiplexed into separate Packetised Elementary Streams (PES), which are routed to the MPEG Audio and Video decoders, and SI data to the PowerPC

subsystem.

405

Decoded Video can then be mixed and optionally scaled with On-Screen Display (OSD) Graphics generated by the DTV application software. The resultant combination of video and graphics are then routed to the PAL/NTSC Digital ENCoders (DENCs) for display on the TV via the on-chip 10-bit video DACs.

Decoded Audio is output directly from the audio decoder sub-system to the I InterFace) outputs.

S and S/PDIF (Sony/Philips Digital

5Zarlink Semiconductor Inc.

ZL10310/ZL10311 Data Sheet

4.0 Functional Blocks Overview

4.1 Boot ROM

Program execution on the Power PC normally starts from address 0xFFFFFFFC after the internal reset has gone inactive. This would normally be an address in the external Flash ROM (enabled by BI_CS0), but, by forcing the SGPIO2_3 pin low during reset, it is possible to boot from the Internal 8k Boot ROM. The ZL10310 and ZL10311 devices contain an 8k Boot ROM containing code, which is executed under the noted conditions above following a complete system reset (i.e. when main power has been removed from the ZL10310 or ZL10311).

The code installed on the Boot ROM, allows the ZL10310/ZL10311 to undertake any of the following 4 functions after a complete reset:

1. Enter ISP (in-system programmable) mode, in which the software in the internal Boot ROM will try booting from

an SPI or I

2. Try booting from an Atmel Serial Flash device (AT45xxxxx) first, if that fails then enter ISP mode.

3. Try booting from an asynchronous parallel flash device connected to the EBIU bus (CS0) first. If that fails, then

try booting from SPI or I

4. Enter debug/monitor mode in which a command prompt is available for debugging registers, downloading code, etc.

4.2 Clock Generation Block

C EEPROM.

C EEPROM or Serial Flash.

The ZL10310/ZL10311 devices use two separate external clock sources to provide all the clocks required; a 27MHz external Voltage Controlled crystal Oscillator (VCXO), and a 20.48MHz external Crystal Oscillator.

A standard 27MHz input to the systems PLL is supplied from an external VCXO. Outputs from this PLL are used to clock the various internal MPEG decoders, the PowerPC



micro controller system, and the external SDRAM. The frequency can be adjusted in the ppm range, using a voltage produced by the pulse width modulated frequency error signal, available from GPIO port GP29.

The 27MHz input also drives a separate audio PLL that is dedicated to providing 256/512 times the audio sampling rate for the audio decoder and external audio DAC.

The COFDM de-modulators have their own PLL driven from an internal 20.48MHz oscillator. An external crystal is required for this oscillator.

6 Zarlink Semiconductor Inc.

Data Sheet ZL10310/ZL10311

4.3 Coded Orthogonal Frequency Division Multiplex (COFDM) Demodulator

The COFDM demodulator is used to demodulate a digitized COFDM modulated IF signal from the TV Tuner, and ultimately convert the resulting MPEG-2 Transport Stream to the MPEG-2 demultiplexer.

The Digitized IF is converted to a complex Baseband signal centered on zero frequency. It also removes adjacent channel interference prior to a Time-to-Frequency Fast Fourier Transform (FFT). The resulting signals are then sent to a digital re-timing block, symbol sync, carrier recovery, and timing recovery. An AGC signal, with a variable mark space ratio, is provided to control the signal levels in the tuner sections of the receiver. Forward Error Correction (FEC) is performed by Viterbi decoding of the convolutional coded data, followed by de-interleaving, Reed-Solomon decoding, and energy dispersal de-randomising. The output is MPEG-2 Transport Stream packets, in byte format.

The COFDM demodulator is fully compliant with the ETSI 300 744 and Digital Television Group (DTG) specifications. Key features are:

• FFT processor operates in 2k and 8k carrier mode.

• All hierarchical and non-hierarchical constellations.

• Automatic digital carrier recovery over a wide range of offsets without the need for AFC

• Automatic digital carrier recovery without the need for a VCXO

• Common phase error correction

• Channel correction using time and frequency filtering

• Automatic co - channel protection, frame sync, and fast channel re- acquisition

• Internal controller handles all tracking and acquisition

• Viterbi decoding with code rates of 1/2, 2/3, 3/4, 5/6, 6/7, and 7/8

• Automatic synchronization and code rate detection

• Constraint length K = 7

• Trace back depth of 128

• De-interleaver followed by DVB Reed Solomon error correction

• De-randomizer and common interface formatting

4.4 MPEG Audio Decoder

The MPEG Audio Decoder produces dual channel outputs from MPEG -1 or MPEG -2 Transport Streams with a maximum rate of 640 kbit/sec. It supports sampling rates of 32, 44.1, and 48 KHz, plus the half rate options. All sampling rates, plus 512/256 Fs, are produced from an internal PLL. A version of the device is available which produces six channels of audio output for holders of the Dolby

• Decodes MPEG-1 and dual channel MPEG-2 audio

• Performs MPEG-1 audio parsing and MPEG-2 Packetised Elementary Stream (PES) audio parsing, or accepts audio elementary streams

• Supports 32kHz, 44.1 kHz, and 48 kHz sampling rates plus the half rate options

• All sampling rates, plus 512/256 Fs, derived from an internal PLL

• 64 step audio attenuation with smooth step transitions

• SPDIF output meeting IEC1937 specifications

• Re-locatable ancillary data region

• Audio Clip Mode

• Dolby

1. For details on 8k carrier performance and use, please consult Zarlink Field Applications

2. The ZL10311 device is awaiting Dolby Certification



AC3 option



Digital2 License.

7Zarlink Semiconductor Inc.

ZL10310/ZL10311 Data Sheet

4.5 MPEG-2 Video Decoder

The MPEG-2 Video Decoder provides complete decoding and synchronized playback of MPEG-2 MP@ML (Main Profile at Main Level) video streams. It supports the decoding of still pictures as well as moving video, with error concealment when necessary. A command driven local controller minimizes the amount of application software needed to control the decoding / channel change process.

The decoder accepts PES from the Transport De-multiplexer, with average rates of up to 15 Mbps. PES header parsing supports the extraction of Presentation Time Stamp (PTS) values, which are then used by the audio/ video synchronization hardware. PES or ES streams can be directly decoded from SDRAM in the Video Clip mode of operation.

Feature summary:

• Packetised MPEG-2 MP @ ML video streams from the transport demultiplexer or from SDRAM

• MPEG-1 video (ES) streams from SDRAM

• Sustained bit rates from 1.5 Mbps to 15 Mbps.

• Local processor driven by commands from the application processor

• Sophisticated error concealment based on the use of stored motion vectors from the previous row

• Supports the decoding of still images

• Automatic or manual image re-sizing

• Conversion of MPEG-1, 24 Hz progressive scan, pictures to 60 Hz interlaced (3:2 pull-down)

4.6 PowerPC 405TM Processor

An integrated PowerPC 405TM processor core is provided for applications and control software, and this provides approx. 150 Drhystone MIPS with a clock of 108 MHz.

It has instruction and data caches with lock down facilities such that defined areas can be used as general purpose ram. The processor has its own internal bus to which is attached the caches, all the peripherals, and a DMA controller. Code can thus be executed, using internal resources, whilst the MPEG decoders are using the SDRAM.

This processor bus is also connected to an auxiliary external bus, which is used for Flash code transfer during the power on routine, and for Flash write operations. PCMCIA, and IDE data transfers also use this bus to provide data and address signals, but their respective control signals have dedicated pins. A bridge to the internal multi-master bus provides software access to the external SDRAM.

All internal and external memory is in a unified address space, and a DMA controller supports high speed data transfers. Controllers are provided for two smart cards, an RS232 modem, a serial Codec, an I synchronous serial port, and an IRDA interface. Individual bit I/O is also supported.

Key Features:

• PowerPC 405

Processor Core running at 108 MHz

• Integrated instruction and data caches (16k/16k) with lock down

• Integrated set top box peripheral controllers

• Four channel DMA controller for peripheral and data transfers

• Dedicated internal processor bus with its own SDRAM controller and auxiliary bus

• Bridge to the decoder multi-master bus and shared SDRAM

•Real Time Counters

• Watch dog timer

• Interrupt Controller

C master, a

8 Zarlink Semiconductor Inc.

Data Sheet ZL10310/ZL10311

4.7 Transport Engine

The ZL10310/ZL10311 devices contain a dedicated hardware implementation of an MPEG/DVB transport stream de-multiplexer, with the configuration of this hardware controlled by application software. Included in the hardware are synchronization, Packet Identifier (PID) filtering, clock recovery, de-scrambling, and table section filtering. PID filtered packets are stored in a local buffer, which can hold up to 10 packets before they are moved to the decoders or to memory queues in SDRAM. The queues are used for the tables containing system information. Packets for three destinations can be moved concurrently out of the buffer.

The hardware acts in conjunction with a Transport Assist Processor, and the resultant hardware/software combination gives increased adaptability and extended processing capability. Further parsing and filtering is possible, and interrupts can be generated to notify the processor when a given condition has been met. The transport assist processor can then read and manipulate packets whilst they are still in the transport packet buffer. It can then allow data to pass through to SDRAM or the decoders, or can record status information and optionally interrupt the application.

Key Features:

• 32 PID values can be used to filter the transport stream

• Flexible, hardware based, section filtering

• 64, 4 byte, filter blocks.

• Filter blocks can be cascaded to provide deep filtering when necessary

• Hardware Cyclical Redundancy Check (CRC) checking

• Captured data is transferred to one of thirty two queues in SDRAM

• Options to transfer complete transport packets with or without headers, or sections

• Adaptation fields can be delivered to a separate queue

• Hardware to extract PCR values with option for software filtering to remove long term jitter

• Comprehensive error detection hardware

• Integrated DVB descrambler

4.8 Video Display System

The Video Display System provides multi-layered video. This features the On-Screen Display (OSD) for menuing and MHEG-5, the Decoded Video Presentation system, and a Video Blending capability to merge the OSD and Video.

The On-Screen Display system is designed to meet or exceed the specifications of major European broadcasters. The final image on the screen is constructed from five separate planes using a fixed display hierarchy. The screen hierarchy consists of:

1. Cursor plane (Top)

2. Region-based graphics plane (typically used for EPG and System menus)

3. Video plane

4. Still image plane (typically used for MHEG-5)

5. Background plane

All planes, apart from the background plane, can be separately enabled. The graphics and image planes are region based, and driven by means of bitmaps controlled by a link-list processor. They can operate independently, but have nearly identical operational controls. The size of a bitmap region can vary between 4 pixels wide by 2 pixels deep, and 1K pixels wide and 1K pixels deep. The color resolution of a pixel within a region can be defined by 2, 4, 8, or 16 bits. The 16-bit option is for direct colors; the other options use color look up tables.

The Video Presentation system is used to scale and process a decoded Video signal. Decoded Video is stored in Field Stores contained in external SDRAM memory. Prior to display it can be automatically scaled from the original resolution and aspect ratio up to PAL or NTSC full screen size. If the encoded image has a 16:9 aspect ratio, but the display has a 4:3 aspect ratio, then any horizontal scaling factor necessary to fill the screen must be adjusted by

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ZL10310/ZL10311 Data Sheet

Pin A1

a further factor of 4/3. Alternatively, a factor of 3/4 can be applied vertically (letter box mode). Video is displayed at the standard PAL or NTSC field rates. Synchronization signals for video presentation can be provided by either the video decoder itself (master mode), or the decoder can slave to incoming signals.

The Video Blending System is used to blend the outputs from separate Digital Encoded Video (DENC) blocks for the Video and OSD systems on-chip:

1. RGB – Red Green Blue

2. Y U/V

3. CVBS – Chroma Video Blanking and Sync

5.0 Physical Specification

The device is contained in a 388-ball Enhanced Plastic Ball-Grid Array (388 EPBGA) package:

• Body Size: 27mm x 27mm

• Ball Count: 388 (includes 36 Thermal Balls)

• Ball Pitch: 1.0mm

• Ball Matrix: 26 x 26 (partially populated with a 6 x 6 GND matrix in the centre)

• Ball Diameter 0.60mm

• Total Package Thickness 2.65mm

Package is viewed from the top side (i.e. through top of the package). Note ball A1 is non-chamfered corner.

Pin A1 ident

ident

123456789

Figure 3 - Package View and Ball Positions

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Data Sheet ZL10310/ZL10311

6.0 ZL10310/ZL10311 388-pin Package Pin Descriptions

This section explains the ZL10310 and ZL10311 device pin functions. The following tables are segmented by signal functions. Many of the pins listed below have multiple functions, and in these cases there is information on how the multiplexed function connects to the pin.

Many references are made to register settings throughout the Pin Descriptions. The details of the ZL10310 and ZL10311 registers can be found in the Hardware Design Manual for the ZL103xx family of Integrated Digital Television Processors (Publication DM5797), available to customers on request, subject to NDA.

6.1 Pin Types

I An Input Type with no designator indicates that the signal must be produced by a device using 3.3V

outputs, and ESD protection is provided. There is no internal pull up, so unused inputs should be tied high or low.

IO Pin Type indicates that the pin can be programmed with control bits to be used as an input or an

output.

B Pin Type indicates that the pin function can alternate between an input and output depending on the

use at that instant i.e. it is Bi-directional. Out characteristics are the same as an Out pin.

OD is an open drain Output.

5V is a 5V tolerant Input or Output. An Input Type with a 5V designator indicates that the input tolerates

is a standard 3.3 V, 65 ohm, output, unless otherwise specified. DC drive is 8.2mA/5.4mA @ VH/VL respectively. Maximum slew rate is 75mA/ns, unless otherwise specified.

5V signals. There is no internal pull up.

6.2 Front End Interfaces

Pin Name

ADCCLK R02 ADCCLK O Sampling Clock Output to External Tuner IF

AGC[0] L02 Tuner AGC control O 5V Master AGC Control Output to External TV Tuner 1

AGC[1] M03 Tuner AGC control

GPP[0] L01 Tuner_SCL O 5V External TV Tuner Control Bus - Clock Output 1, 6

GPP[1] N04 Tuner_SDA B 5V External TV Tuner Control Bus - Data

EXT_IN[0] K01 ED1_MDO[7]

Pin No.

Function

offset

(MSB)

Type

Analog to Digital Converter. Clock = 20.48MHz.

O 5V Secondary AGC Control Output to External TV

Tuner. Used to provide a differential AGC feed to external TV Tuner, if required.

Input/Output.

I External Demodulator 1 Digital Input -

Data Bit 7 (MSB)

Description Notes

1, 6

5, 7

DV2_IN_DATA[7] (MSB)

RW_TDO O Debug Interface - JTAG TDO (Data Out) 3

I Reserved 7

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ZL10310/ZL10311 Data Sheet

Pin Name

EXT_IN[1] K02 ED1_MDO[6] I 5V External Demodulator 1 Digital Input - Data Bit 6 1, 5, 7

EXT_IN[2] J01 ED1_MDO[5] I External Demodulator 1 Digital Input - Data Bit 5 5, 7

EXT_IN[3] L03 ED1_MDO[4] I External Demodulator 1 Digital Input - Data Bit 4 5, 7

EXT_IN[4] J02 ED1_MDO[3] I External Demodulator 1 Digital Input - Data Bit 3 5, 7

Pin No.

Function

RW_TDI I 5V Debug Interface - JTAG TDI (Data In) 1, 3

DA_SER_DATAI I 5V Digital Audio Serial Data Input. Main left and right

DV2_IN_DATA[6] I Reserved 7

RW_HALT I Debug Interface - JTAG Halt 3

DV2_IN_DATA[5] I Reserved 7

RW_TMS I Debug Interface - JTAG TMS 3

DV2_IN_DATA[4] I Reserved 7

RW_TCK I Debug Interface - JTAG TCK 3

Typ e

Description Notes

1, 4 serial audio data at a rate of 64fs. Signal routed through to GP12 (not bonded out)

EXT_IN[5] L04 ED1_MDO[2] I External Demodulator 1 Digital Input - Data Bit 2 5, 7

DV2_IN_DATA[3] I Reserved 7

Tes t[ 0] I Tes t M od e A - Tes t P in 0

EXT_IN[6] K03 ED1_MDO[1] I External Demodulator 1 Digital Input - Data Bit 1 5, 7

DV2_IN_DATA[2] I Reserved 7

Tes t[ 1] I Tes t M od e A - Tes t P in 1

EXT_IN[7] H02 ED1_MDO[0]

(LSB)

DV2_IN_DATA[1] I Reserved 7

Tes t[ 2] I Tes t M od e A - Tes t P in 2

EXT_IN[8] G01 ED1_MVAL I External Demodulator 1 Digital Input - Data Valid

DV2_IN_DATA[0] (LSB)

Tes t[ 3] I Tes t M od e A - Tes t P in 3

EXT_IN[9] J03 ED1_MCLK I External Demodulator 1 Digital Input - Clock Input 5

I External Demodulator 1 Digital Input - Data Bit 0

(LSB)

Input

I Reserved 7

5, 7

DV2_Pixel_Clk I Reserved

Tes t[ 4] I Tes t M od e A - Tes t P in 4

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+ 28 hidden pages

ZARLINK ZL10310, ZL10311 DATA SHEET

Specifications and Main Features

Frequently Asked Questions

User Manual