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Le51HE0060V2
User Manual
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Zarlink Le51HE0060V2 User Manual

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Le51HE0060V2
Le58QL063 QLSLAC™ /
Le5711/12 DSLIC™
Evaluation Board User’s Guide
Rev. A, Ver. 2
October 2, 2007
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
Information relating to products and services f urnished herein by Z arlink Semiconductor Inc. or i ts subsidiaries (collectively “Zarlink”) is b elieved to be rel iable. However, Zarlink a ssumes n o liability f or errors t hat may a ppear in t his pu blication, or f or lia bility o therwise a rising from t he ap plication or use of a ny such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the s upply of s uch information or pu rchase of product or se rvice con veys any license, either express o r implied, under p atents or other intellectual property rights owned by Z arlink o r licensed from third parties by Z arlink, whatsoever. Purchasers of products are also hereby notified that th e use of product i n certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information ap pearing in this publication are subject t o cha nge by Za rlink without no tice. No wa rranty or gu arantee express or implied i s ma de re garding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a sp ecific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
Purchase of Zarlink’s I conforms to the I
Zarlink, ZL , th e Zarlink Se miconductor lo go an d th e L egerity l ogo an d co mbinations the reof, VoiceEdge, VoicePort, SLAC , ISLI C, ISLAC an d V oicePath are trademarks of Zarlink Semiconductor Inc.
2C components conveys a lic ense under the Philips I2C Patent rights to use these components in an I2C System, provided that the system
2C Standard Specification as defined by Philips.
TECHNICAL DOCUMENTATION - NOT FOR RESALE
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Zarlink Semiconductor Inc.
Document ID# 081167 Date: Oct 2, 2007 Rev: A Version: 2 Distribution: Public Document
TABLE OF CONTENTS
CHAPTER 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 DSLIC™ eTQFP (Exposed Pad) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
CHAPTER 2 BOARD SETUP AND CONNECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Board Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Board Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.1 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.2 Telephone Line Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3 Interconnection of the Le51HE0060V2 Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4 PCM/MPI Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
CHAPTER 3 BOARD OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Jumper Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Jumper And Switch Settings For The Le51HE0060V2 Evaluation Board . . . . . . . . . . . . . . 8
CHAPTER 4 SOFTWARE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CHAPTER 5 SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 Evaluation Board Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 Le51HE00602V Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
CHAPTER 6 GLOSSARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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CHAPTER
1
Zarlink Semiconductor Inc.
1
INTRODUCTION
1.1 OVERVIEW
The Zarlink Le51HE0060V2 evaluation board provides a platform to evaluate the capabilities of the Le58QL063 QLSLAC™ and Le5711/12 DSLIC™ devices. All digital control signals, voice band and MPI signals have test points for easy probing. Power is brought to the board via a set of banana jack connectors. The QLSLAC device and the two DSLIC devices are mounted in ZIF sockets.
Detailed device explanations, operational circuit descriptions and required formulas can be found within the individual QLSLAC and DSLIC device data sheets. Figure 1–1
shows the physical layout
of the Le51HE0060V evaluation board. Figure 1–2
shows a block diagram.
Figure 1–1 Le51HE0060V2 Evaluation Board
1.2 DSLIC™ eTQFP (Exposed Pad)
The Le5711/12 DSLIC device has an exposed thermal pad (heat slug) on the underside of the device. This pad should be connected to VBAT for thermal relief (see the Thermal Design for Le5711 and Le5712 application note for details of the connection). However, due to the type of sockets used the connection to VBAT could not be made. Because of the socket, thermal performance may be compromised. Do not connect to any other voltage.
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Figure 1–2 Le51HE0060V2 Evaluation Board Block Diagram
QSLAC
DSLIC
DSLIC
Channel
1
Interface
(EMR)
Channel
2
Interface
(EMR)
Channel
3
Interface
(LCAS)
Channel
4
Interface
(LCAS)
Ringing Voltage
Distribution
Circuits
Power Distribution and Filtering
PCM/MPI Interface
Tip/Ring 1
Tip/Ring 2
Tip/Ring 3
Tip/Ring 4
To all circuits
VBAT1, VBAT2,
BGND, +5 V, AGND
+3.3 V, DGND
Ringing Voltage
Ringing Rtn
Manual DSLIC
Controls
CHAPTER
3
Zarlink Semiconductor Inc.
2
BOARD SETUP AND CON­NECTION
2.1 BOARD FEATURES
The Le51HE0060V2 evaluation board design features the following:
• MPI/PCM Connector
• TIP/RING banana jacks and RJ-11 connectors
• Test Points for all major signals
• Banana jacks for all power connections
• QSLAC or manual control of DSLIC devices
• Two channels of solid state ringing switches and two channels of EMR ringing switches
• Battery or earth backed ringing
• Socketed components for easier evaluation
• On-board protection for tip/ring
• Meter rejection filtering
• DC parameters programmable via easy to change socketed components
• AC parameters programmable through the QLSLAC device
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2.2 BOARD CONNECTIONS
The Le51HE0060V2 can be plugged directly into either a Voice Path Demo (VP Demo) Board or an Advanced Computer Interface Board (ACIF2-A) via the 50-pin IFB01 connector of the
Le51HE0060V2 evaluation board. All power is supplied via the nine banana jacks across the top of the board. est points are included for all major signals. Eight banana jacks, labeled TIP
X
and
RING
X
, are located on the right-hand edge of the evaluation board for connection to test equipment or for connecting to a standard telephone station set. These jacks are also connected in parallel with an industry standard RJ-11 connector.
2.2.1 Power
The required power for the board is supplied through nine banana jacks, as detailed in Table 2–1.
Table 2-1 Power Connections
Before connecting a ringing supply, the user should assure that the jumpers used for earth/battery backed ringing selection are appropriately set. Details are contained in Chapter 3
Power sequencing is recommended, though not required. The suggested power sequencing scheme is: VBAT1 powered-up first, followed by VBAT2, +3.3 V, and finally the +5-V supply. DGND and AGND are tied together on the board with zero ohm resistors R9 and R10. BGND is not tied to either AGND or DGND and care is required to assure that the maximum potential difference between these points, as defined in the DSLIC data sheet, is not exceeded
2.2.2 Telephone Line Interface
To interface the Le51HE0060V2 evaluation board to a telephone station set, plug the telephone station set into the TIP and RING banana jack pair (BJ1 and BJ2, BJ3 and BJ4, BJ12 and BJ13 or BJ14 and BJ15). Alternately, the RJ-11 jacks (J11, J12, J13, J14) can be used.
A tip/ring surge protection circuit is included on the board. The LCAS protection circuits use a fixed voltage protection scheme while the EMR protection circuits use a battery referenced protection scheme.
Jack # Signal Description Board Name (PW1)
BJ5 VBAT1 Battery Supply, higher absolute voltage VBAT1
BJ6 VBAT2 Battery Supply, lower absolute voltage VBAT2
BJ7 +5 V Five volt analog supply Vcc
BJ8 +3.3 V 3.3-V digital supply 3.3 V
BJ9 DGND Digital ground, return for the +3.3-V supply DGND
BJ10 AGND Analog ground, return for the +5-V supply. AGND
BJ11 BGND Battery ground BGND
BJ16 Ring In Ringing voltage source Ring in
BJ17 Ring Return Ringing voltage return Ring return
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2.3 INTERCONNECTION OF THE Le51HE0060V2 EVALUATION BOARD
A representative connection of a complete Zarlink evaluation platform setup is shown in
Figure 2–1
and Figure 2–2 below.
Figure 2–1
shows the evaluation board connected to the 50-pin connector (SPA) of the VP Demo board. The host PC runs the VP-Script Software. Commands are passed through the VP Demo board, via a serial COM port, to the evaluation board.
Figure 2–1 Le51HE0060V2 Evaluation Board to VP Demo Board Connection Diagram
Analog access to test equipment is connected to the TIP/RING connectors of the Le51HE0060V2 evaluation board. Digital PCM access to test equipment is provided through the VP Demo Board.
Figure 2–2
shows the evaluation board connected to the 50-pin connector LNB#0 of the ACIF2-A Board. The host PC runs the WinACIF Software. Commands are passed through the ACIF2-A board, via a serial COM port, to the evaluation board.
Figure 2–2 Le51HE0060V2 Evaluation Board to ACIF2-A Connection Diagram
Analog access to test equipment is connected to the TIP/RING connectors of the L371HE0060V2 evaluation board. Digital PCM access to test equipment is provided through the ACIF2-A Board.
VP Demo
Board
QLSLAC
Le5711/12
PCM-4
Analog
Telephone Telephone
T1/E1
Telephone
Telephone
ACIF2-A Board
QLSLAC
Le5711/12
PCM-4
Digital
Analog
Telephone Telephone
Telephone Telephone
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2.4 PCM/MPI CONNECTIONS
All PCM/MPI interface signals are passed through the ACIF connector. Pinout for the VP Demo Board SPA connector is shown below.
The QLSLAC device multiplexes Data In and Data Out on the same pin, DIO. To assure the VP­Script Software will look for Data In and Data Out on the same pin, after starting the VP-Script program, the user will need to open the PCM sub-menu and set chip select to CS11 and DIO to combined.
Table 2–1 PCM/MPI Connections
Pin # Signal Pin # Signal
1 RST 26 Digital Ground
2 MCLK 27 Digital Ground
3 DCLK 28 Digital Ground
4 DRB 29 Digital Ground
5 DIO 30 Digital Ground
6 INT 31 Digital Ground
7 DXA 32 Digital Ground
8 CS 33 Digital Ground
9 DRA 34 Digital Ground
10 DXB 35 Digital Ground
11 FS 36 Digital Ground
12 PCLK 37 Digital Ground
13-25 N/C 38-50 Digital Ground
CHAPTER
7
Zarlink Semiconductor Inc.
3
BOARD OPERATION
3.1 JUMPER LOCATIONS
Figure 3–1 Jumper Locations
DSLIC JumpersRinging JumpersDSLIC Manual
Controls
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3.2 JUMPER AND SWITCH SETTINGS FOR THE Le51HE0060V2 EVALUATION BOARD
This evaluation board contains a plethora of jumper and switch settings to allow testing of all the
operational modes of the QLSLAC/DSLIC combination. Figure 3–1
shows the mechanical position of the jumpers and switches. All these settings may be categorized into several groups by logical function, as follows:
1. QLSLAC controls
2. DSLIC controls (these are in the form of DIP switches instead of jumpers)
3. Line side options for DSLIC
4. Ringing options.
Table 3–1 QLSLAC Control Jumpers
Jumper Designation
1 to 2
jumpered
2 to 3
jumpered No jumper
JMCKE1
Select MCLK1 on IFB0 connector for QLSLAC MCLK(E1) input
Tie QLSLAC MCLK(E1) to DSLIC pin 18 with a pullup resistor. Use this setting only if the QSLAC is a mode that uses this pin as an output.
QLSLAC MCLK input floats, not recommended.
J3, LCAS control
TSD input to LCAS for channel 3 is open.
TSD input for channel 3 is connected to DSLAC control lead C73, DSLAC controls LCAS for channel 3.
TSD input to LCAS for channel 3 is open.
J4, LCAS control
TSD input to LCAS for channel 4 is open.
TSD input for channel 3 is connected to DSLIC control lead C74, DSLIC controls LCAS for channel 4.
TSD input to LCAS for channel 4 is open.
Table 3–2 DSLIC Switch Controls for Channel 1
Switch Designation
+ (logic one) setting
(position 2)
O (open) setting (position
1)
- (logic zero) setting Position 0
S1-1
DSLIC channel 1 lead C11 tied to VCC (manual control of DSLIC)
DSLIC channel 1 lead C11 tied to QSLAC lead C31 (QSLAC controls DSLIC)
DSLIC channel 1 lead C11 tied to AGND (manual control of DSLIC)
S1-2
DSLIC channel 1 lead C21 tied to VCC (manual control of DSLIC)
DSLIC channel 1 lead C21 tied to QSLAC lead C41 (QSLAC controls DSLIC)
DSLIC channel 1 lead C21 tied to AGND (manual control of DSLIC)
S1-3
DSLIC channel 1 lead C31 tied to VCC (manual control of DSLIC)
DSLIC channel 1 lead C31 tied to QSLAC lead C51 (QSLAC controls DSLIC)
DSLIC channel 1 lead C31 tied to AGND (manual control of DSLIC)
S1-4 Not Used Not Used Not Used
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Note:
The "open" position of the switch allows the QLSLAC device to control the three DSLIC channel controls. The other two positions provide manual control. When using manual controls, refer to the DSLIC data sheet for state information.
Table 3–3 DSLIC Switch Controls for Channel 2
Switch Designation
+ (logic one) setting
(position 2)
O (open) setting (position
1)
- (logic zero) setting Position 0
S2-1
DSLIC channel 2 lead C12 tied to VCC (manual control of DSLIC)
DSLIC channel 2 lead C11 tied to QSLAC lead C32 (QSLAC controls DSLIC)
DSLIC channel 2 lead C12 tied to AGND (manual control of DSLIC)
s2-2
DSLIC channel 2 lead C22 tied to VCC (manual control of DSLIC)
DSLIC channel 2 lead C21 tied to QSLAC lead C42 (QSLAC controls DSLIC)
DSLIC channel 2 lead C22 tied to AGND (manual control of DSLIC)
S2-3
DSLIC channel 2 lead C32 tied to VCC (manual control of DSLIC)
DSLIC channel 2 lead C31 tied to QSLAC lead C52 (QSLAC controls DSLIC)
DSLIC channel 2 lead C32 tied to AGND (manual control of DSLIC)
S2-4 Not Used Not Used Not Used
Table 3–4 DSLIC Switch Controls for Channel 3
Switch Designation
+ (logic one) setting
(position 2)
O (open) setting (position
1)
- (logic zero) setting Position 0
S3-1
DSLIC channel 3 lead C11 tied to VCC (manual control of DSLIC)
DSLIC channel 3 lead C11 tied to QSLAC lead C33 (QSLAC controls DSLIC)
DSLIC channel 3 lead C11 tied to AGND (manual control of DSLIC)
S3-2
DSLIC channel 3 lead C21 tied to VCC (manual control of DSLIC)
DSLIC channel 3 lead C21 tied to QSLAC lead C43 (QSLAC controls DSLIC)
DSLIC channel 3 lead C21 tied to AGND (manual control of DSLIC)
S3-3
DSLIC channel 3 lead C31 tied to VCC (manual control of DSLIC)
DSLIC channel 3 lead C31 tied to QSLAC lead C53 (QSLAC controls DSLIC)
DSLIC channel 3 lead C31 tied to AGND (manual control of DSLIC)
S3-4 Not Used Not Used Not Used
Table 3–5 DSLIC Switch Controls for Channel 4
Switch Designation
+ (logic one) setting
(position 2)
O (open) setting (position
1)
- (logic zero) setting Position 0
S4-1
DSLIC channel 4 lead C12 tied to VCC (manual control of DSLIC)
DSLIC channel 2 lead C11 tied to QSLAC lead C34 (QSLAC controls DSLIC)
DSLIC channel 4 lead C12 tied to AGND (manual control of DSLIC)
S4-2
DSLIC channel 4 lead C22 tied to VCC (manual control of DSLIC)
DSLIC channel 2 lead C21 tied to QSLAC lead C44 (QSLAC controls DSLIC)
DSLIC channel 4 lead C22 tied to AGND (manual control of DSLIC)
S4-3
DSLIC channel 4 lead C32 tied to VCC (manual control of DSLIC)
DSLIC channel 2 lead C31 tied to QSLAC lead C54 (QSLAC controls DSLIC)
DSLIC channel 4 lead C32 tied to AGND (manual control of DSLIC)
S4-4 Not Used Not Used Not Used
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Table 3–6 Line Side DSLIC Controls
Jumper Designation
1 to 2
jumpered
2 to 3
jumpered No jumper
J5, intended for troubleshooting and insertion of ammeter in line.
RING3 - LCAS and output jacks connected to DSLIC
N/A
RING3 LCAS and output jacks not connected to DSLIC
J6, intended for troubleshooting and insertion of ammeter in line.
TIP3 - LCAS and output jacks connected to DSLIC
N/A
TIP3 LCAS and output jacks not connected to DSLIC
J7, intended for troubleshooting and insertion of ammeter in line.
TIP4 - LCAS and output jacks connected to DSLIC
N/A
TIP4 LCAS and output jacks not connected to DSLIC
J8, intended for troubleshooting and insertion of ammeter in line.
RING4 - LCAS and output jacks connected to DSLIC
N/A
RING4 LCAS and output jacks not connected to DSLIC
J10, intended for insertion of an ammeter
Connect VBAT (and VBATREF) input of DSLIC for channels 1 and 2 to VBAT1 source.
N/A
Do not connect DSLIC VBAT input to VBAT1 source. No source is selected.
J15, intended for troubleshooting and insertion of ammeter in line.
TIP1 - ringing relay and output jacks connected to DSLIC
N/A
TIP1 ringing relay and output jacks not connected to DSLIC
J16, intended for troubleshooting and insertion of ammeter in line.
RING1 - ringing relay and output jacks connected to DSLIC
N/A
RING1 ringing relay and output jacks not connected to DSLIC
J17, intended for troubleshooting and insertion of ammeter in line.
TIP2 - ringing relay and output jacks connected to DSLIC
N/A
TIP2 ringing relay and output jacks not connected to DSLIC
J18, intended for troubleshooting and insertion of ammeter in line.
RING2 - ringing relay and output jacks connected to DSLIC
N/A
RING2 ringing relay and output jacks not connected to DSLIC
J19, intended for insertion of an ammeter
Connect VBAT (and VBATREF) input of DSLIC for channels 3 and 4 to VBAT1 source.
N/A
Do not connect DSLIC VBAT input to VBAT1 source. No source is selected.
J101, VBAT2 connections
Connect VBAT2 source to pin TMG1(VBAT2) of DSLIC for channel 1.
Connect VBAT1 source to pin TMG1(VBAT2) of DSLIC for channel 1.
TMG1(VBAT2) input to DSLIC is open.
J102,VBAT2 connections
Connect VBAT2 source to pin TMG12(VBAT2) of DSLIC for channel 2.
Connect VBAT1 source to pin TMG2(VBAT2) of DSLIC for channel 2.
TMG2(VBAT2) input to DSLIC is open.
J103, reserved for future use, do not jumper.
Do not jumper. Do not jumper. Do not jumper.
J201, VBAT2 connections
Connect VBAT2 source to pin TMG1(VBAT2) of DSLIC for channel 3.
Connect VBAT1 source to pin TMG1(VBAT2) of DSLIC for channel 3.
TMG1(VBAT2) input to DSLIC is open.
J202,VBAT2 connections
Connect VBAT2 source to pin TMG12(VBAT2) of DSLIC for channel 4.
Connect VBAT1 source to pin TMG2(VBAT2) of DSLIC for channel 4.
TMG2(VBAT2) input to DSLIC is open.
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Note:
All of the jumpers in the table below MUST be set consistently for proper operation. All jumpers must connect positions 1 and 2 for battery-backed ringing OR connect 2 and 3 for earth-backed ringing. The setting of these jumpers must be checked before applying the ringing voltage source to the board.
Table 3–7 Ringing Controls
Jumper Designation 1 to 2
jumpered
2 to 3 jumpered
No jumper
JSR1, RING IN selector. Select battery backed
ringing for all 4 channels.
Select earth backed ring­ing for all 4 channels.
Disconnect all 4 circuits from the RING IN source.
JSR2, RING RETURN selector.
Select battery backed ringing for all 4 channels.
Select earth backed ring­ing for all 4 channels.
Disconnect all 4 circuits from RING RETURN.
JSR3, DSLIC DAC (posi­tive input for ring trip comparator) control for channels 1 and 2.
Select battery backed ringing.
Select earth backed ring­ing.
Disconnect signal.
JSR4, DSLIC DAC (posi­tive input for ring trip comparator) control for channels 1 and 2.
Select battery backed ringing.
Select earth backed ring­ing.
Disconnect signal.
JSR5, DSLIC DAC (posi­tive input for ring trip comparator) control for channels 1 and 2.
Select battery backed ringing.
Select earth backed ring­ing.
Disconnect signal.
JSR6, DSLIC DB1 (nega­tive input for ring trip comparator) control for channel 1.
Select battery backed ringing.
Select earth backed ring­ing.
Disconnect signal.
JSR7, DSLIC DB2 (nega­tive input for ring trip comparator) control for channel 2.
Select battery backed ringing.
Select earth backed ring­ing.
Disconnect signal.
JSR8, DSLIC DAC (posi­tive input for ring trip comparator) control for channels 3 and 4.
Select battery backed ringing.
Select earth backed ring­ing.
Disconnect signal.
JSR9, DSLIC DAC (posi­tive input for ring trip comparator) control for channels 3 and 4.
Select battery backed ringing.
Select earth backed ring­ing.
Disconnect signal.
JSR10, DSLIC DAC (pos­itive input for ring trip comparator) control for channels 3 and 4.
Select battery backed ringing.
Select earth backed ring­ing.
Disconnect signal.
JSR11, DSLIC DB1 (neg­ative input for ring trip comparator) control for channel 3.
Select battery backed ringing.
Select earth backed ring­ing.
Disconnect signal.
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JSR12, DSLIC DB2 (neg­ative input for ring trip comparator) control for channel 4.
Select battery backed ringing.
Select earth backed ring­ing.
Disconnect signal.
JSR13, Ringing indicator control.
Illuminate battery backed ringing indicator.
Illuminate earth backed ringing indicator.
Both indicators are off.
JRSR1, Select ring side ringing source for chan­nel 1.
Select battery backed ringing.
Select earth backed ring­ing.
Disconnect signal.
JRSR2, Select ring side ringing source for chan­nel 2.
Select battery backed ringing.
Select earth backed ring­ing.
Disconnect signal.
JRSR3, Select ring side ringing source for chan­nel 3.
Select battery backed ringing.
Select earth backed ring­ing.
Disconnect signal.
JRSR4, Select ring side ringing source for chan­nel 4.
Select battery backed ringing.
Select earth backed ring­ing.
Disconnect signal.
JRST1, Select tip side ringing source for chan­nel 1.
Select battery backed ringing (ringing return via RRTN1 resistor to BGND).
Select earth backed ring­ing.
Disconnect signal.
JRST2, Select tip side ringing source for chan­nel 2.
Select battery-backed ringing (ringing return via RRTN2 resistor to BGND).
Select earth backed ring­ing.
Disconnect signal.
JRST3, Select tip side ringing source for chan­nel 3.
Select battery-backed ringing (ringing return via RRTN3 resistor to BGND).
Select earth backed ring­ing.
Disconnect signal.
JRST4, Select tip side ringing source for chan­nel 4.
Select battery-backed ringing (ringing return via RRTN4 resistor to BGND).
Select earth backed ring­ing.
Disconnect signal.
Table 3–7 Ringing Controls
Jumper Designation 1 to 2
jumpered
2 to 3 jumpered
No jumper
CHAPTER
13
Zarlink Semiconductor Inc.
4
SOFTWARE OPERATION
4.1 OVERVIEW
Three software platforms enable the user full control of the Le51HE0060V2 evaluation board. The first two are control platforms to communicate with the evaluation board. The first platform is the VP Demo Board and the VP-Script program or the Voice Path Mini-PBX software. The second platform is the ACIF2-A hardware board along with its accompanying WinACIF2™ software program. The third software program, WinSLAC2™, is used to calculate the required coefficients for the QLSLAC and UVoSLIC devices.
The WinSLAC2 software models both the QLSLAC and Le9502 devices. The program is designed to calculate programmable coefficients for optimizing two-wire impedance, hybrid balance and transmit and receive responses. WinSLAC2 calculates and predicts transmission performance for:
• Two-Wire Return Loss
• Four-Wire Return Loss
• Transmit and receive attenuation distortion
• Transmit and receive path equalization
• Two-wire stability
For a more detailed description refer to the WinSLAC2 Software User's Guide, document ID #080779.
The VoicePath Demo Board is one of the control platforms that can be used for communicating with the evaluation board. The VP-Script program uses a command menu to send information to and receive information from the evaluation board (supports PCM mode only). Refer to the VP-Script Software User's Guide, publication #080757, for more detailed information.
Note:
The VP-Script program will need to be set up to send data to or receive data from the QLSLAC device on a single pin. To do this, once the VP-Script program has been started, open the PCM sub­menu and set chip select to CS11 and DIO to combined.
The ACIF2-A hardware board and the WinACIF software is an alternate platform that can be used to communicate with the Le71He0062V board. Once the software has been initialized with the correct configuration, a command menu is used to send information to and receive information from the chip set (supports PCM and GCI modes). Refer to the WinACIF User's Guide, document ID #080269, for more detailed information.
Note:
When the WinACIF program is initialized, the software is automatically set to transmit and receive data on a single pin.
Le51HE0060V2 Eval Board User Guide
14
Zarlink Semiconductor Inc.
CHAPTER
15
Zarlink Semiconductor Inc.
5
SCHEMATICS
5.1 EVALUATION BOARD SCHEMATICS
Schematics and a bill of materials for the Le51HE0060V2 evaluation board are included on the following pages.
Le51HE0060V2 Eval Board User Guide
16
Zarlink Semiconductor Inc.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Page 1 Cover Sheet
Page 2 Block Schematic
Page 3 DSLIC 1 Schematic
Page 4 DSLIC 2 Schematic
Page 5 Power and Decoulping Schematic
Page 6 QSLAC Schematic
Page 7 Ring Signal Schematic
58QL063VC and 5712 Dual SLIC Evaluation Board
Revision 2.0
LE51HE0060V2 2.0ZaR
Zarlink QLSLAC DSLIC 5712 Evaluation Board
B
17Friday, June 20, 2003
WPE
PPC - VNA
2136 North 13th st
Reading, Pa 19604
Title
Size Document Number Rev
Date: Sheet
of
Designer
Le51HE0060V2 Eval Board User Guide
17
Zarlink Semiconductor Inc.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Page 7
Page 2
Page 3
Page 4
Page 6
Page 5
Hierarchical Flow
Le51HE0060V2 2.0Z
Zarlink QLSLAC DSLIC 5712 Evaluation Board
C
27Friday, June 20, 2003
WPE
PPC - VNA
2136 North 13th st
Reading, Pa 19604
Title
Size Document Number Rev
Date: Sheet
of
Designer
Power & Decoupling
VCC
3.3V
BGND
AGND
DGND
VBAT1
VBAT2
QLSLAC 063
QLSLAC
VOUT1
VIN1
CD11
CD21
C31
C41
C51
C61
VOUT2
VIN2
CD12
CD22
C32
C42
C52
C62
VOUT3
VIN3
CD13
CD23
C33
C43
C53
C63
VOUT4
VIN4
CD14
CD24
C34
C44
C54
C64
E1
TSD3
TSD4
VREF
VCC
AGND
DGND
3.3V
DSLIC1
DSLIC 1
VOUT1
VIN1
CD11
CD21
C31
C41
C51
C61
VOUT2
VIN2
CD12
CD22
C32
C42
C52
C62 DAC12_SELECT
DB1_SELECT
DB2_SELECT
RS1
RS2
E1
RPRC1
RPRC2
TS1R
TS2R
VREF
BGND
AGND
VBAT1
VBAT2
VCC
DSLIC2
DSLIC 2
VOUT3
VIN3
CD13
CD23
C33
C43
C53
C63
VOUT4
VIN4
CD14
CD24
C34
C44
C54
C64
DAC34_SELECT
DB3_SELECT
DB4_SELECT
RS3
RS4
E1
RPRC3
RPRC4
TS3R
TS4R
TSD3
TSD4
VREF
VBAT1
VBAT2 VCC
AGND
BGND
RING Signal
RING Signal
RS1
RS2
RS3
RS4
RPRC1
RPRC2
RPRC3
RPRC4
TS1R
TS2R
TS3R
TS4R
DAC12_SELECT
DB1_SELECT
DB2_SELECT
DAC34_SELECT
DB3_SELECT
DB4_SELECT
VCC
BGND
VBAT1
AGND
DGND BGND
AGND
VCC
VBAT1
VBAT2
3.3V
VCCVBAT2
VBAT1
BGNDAGND
VCC
VBAT1
BGNDAGND
VBAT2
VCC
DGND
AGND
BGND
VCC
VBAT1
AGND
3.3V
Le51HE0060V2 Eval Board User Guide
18
Zarlink Semiconductor Inc.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
RING2
RED
TIP2
BLACK
TIP1
BLACK
RING1
RED
DSLIC Channels 1 & 2 with EMR
See note 1.
See note 1.
Notes:
1. Board may be assembled with either PTC's or resistors
TX2-5V
TX2-5V
2. Due to socket design the thermal PAD (pin 45) could not be tied to the proper potential.
3. Populate either U42 & U43 or U40 but not both.
See Note 2
Socketed
Le51HE0060V2 2.0Z
Zarlink QLSLAC DSLIC 5712 Evaluation Board
C
37Wednesday, June 04, 2003
WPE
PPC - VNA
2136 North 13th st
Reading, Pa 19604
Title
Size Document Number Rev
Date: Sheet
of
Designer
VBat1
BGND
AGND
BGND
AGND
BGND
BGND
VBAT1
BGND
VBAT1
BGND
AUX_VCC
AGND
AGND
VCC
VCC
VCC
AGND
VCC
AGND
AGND
AGND
AGND
VBat2
VBAT2
BGND
BGND
AGNDAGND
AGND
AGND
AGND
AGND
AGND
AGND
BGND
AGND AGND
VCC
VCC
AGND
VCC
AGND
BGND
AUX_VCC
AGND
BGND
BGND
CB2
NF
TIP1
1
RRX1
75K
RLED2
5372T5
BGND1
1
JRST2
123
C31
1
VREF1
1
CPRT1
100nF
CRSN1
390pF
12
U2
LE5712
31
35
32
34
27
22
25
21
24
16
14
40
42
2
1
9
104411
8
7
30
26
37
19
33
23
43
12
5
4
29
45
3
6
13
15
39
18
36
28
20
38
17
41
AD1
HP1
BD1
[VBAT2] TMG1
VBAT
[VBAT2] TMG2
AD2
HP2
BD2
VTX2
RSN2
VTX1
RSN1
C11
C21
C12
C22
DET1
DET2
IREF
CAS
DB1
DB2
FLT1
FLT2
BGND1
BGND2
CDC1
CDC2
VCC
A/DGND
DAC
e-PAD
C31
NC [RD]
C32
NC [C42]
[R1] NC
NC [E1]
[RYE1] NC
[BSWTH] NC
[RYE2] NC
[VBREF] NC
[R2] NC
NC [C41]
TIP2
1
J18
1
2
RTA1
49.9K
CRSN2
390pF
12
REF1
15K
U40-1
TISP6NTP2A_SOIC
1
2
8
7
K1
G3,4
K4
A
CHP2
100nF
CFLT_2
1
DET2
1
R6
1.0K
CP1
390pF
RRLY1
10K
LDET2
5372T5
CDC2
330nF
VTX2
1
BD2
1
MTRSG2
1
J17
1
2
BGND4
1
CFLT2
100nF
PTCB2
C62
1
RRSN1
0 Ohm
1 2
K1
4
3
5
9
10
8
1
12
CA11
22nF
CA2
NF
U40-2
TISP6NTP2A_SOIC
4
3
5
6
K1
G3,4
K4
A
RRTN2
50
QRL3
MMBT5088
1
3
2
HP2
1
U43
B1101UC
123
5
CA21
22nF
DVBL1
MURS120
LDET1
5372T5
BD1
1
R1
1.0K
QRL2
MMBT5088
1
3
2
QRL4
MMBT5088
1
3
2
R2
1.0K
C52
1
RTB1
49.9K
RFB1
50
J102
123
C6
100nF
CVBL22
100nF
RTMG2
1.6K
CB1
NF
VRX2
1
BGND3
1
CT1
1.5nF
12
HP1
1
CXB1
1.5nF
BGND5
1
RRTN1
50
RFB2
50
RD1
80.6
CP2
390pF
RRLY4
10K
CVTX1
100nF
RRLY2
10K
CAS1
1
J12
246
135
CB11
22nF
VTX22
1
K2
4
3
5
9
10
8
1
12
J101
123
R7
1.0K
JRSR1
123
CDET2
22nF
RMTR1
6.34K
DVBL2
MURS120
AD1
1
RHP2
15K
C41
1
JRSR2
123
RP2
11K
MTRSG1
1
U42
B1101UC
123
5
RFA1
50
RING2
1
PTCA1
CVRX2
100nF
CVB1
100nF
RP1
11K
Q1
MMBT5087
VTX11
1
CA1
NF
K1TP1
1
J103
123
CT2
1.5nF
12
J11
246
135
RRX2
75K
RDET1
100K
RDET2
100K
CFLT_1
1
J10
1
2
C51
1
RTA2
49.9K
RFA2
50
Q2
MMBT5087
CDC1
330nF
D5
MURS120
QRL1
MMBT5088
1
3
2
AD2
1
RRSN2
0 Ohm
1 2
K2TP1
1
PTCB1
J15
1
2
C61
1
S1
TDS-04
123
45
8
C32
1
RTMG1
1.6K
CHP1
100nF
VTX1
1
CVBL11
100nF
DVBH12
MURS120
RHP1
15K
R3
1.0K
R5
1.0K
BGND2
1
DET1
1
CFLT1
100nF
CCAS1
330nF
VRX1
1
CDET1
22nF
JRST1
123
CXB2
1.5nF
RING1
1
RTB2
49.9K
CVTX2
100nF
RLED1
5372T5
RXA2
4.99K
C42
1
CPRT2
100nF
RMTR2
6.34K
RRLY3
10K
S2
TDS-04
123
45
8
CB21
22nF
D2
MURS120
J16
1
2
PTCA2
CVRX1
100nF
RXA1
4.99K
VOUT1
CD11
CD21
C31
C41
C51
C61
VOUT2
CD12
CD22
C32
C42
C52
C62
VIN1
DB1_SELECT
DAC12_SELECT
RS1
RS2
E1
DB2_SELECT
TS1R
TS2R
RPRC2
RPRC1
VIN2
BGND
AGND
VCC
VCC
VBat2
VBat1
VREF
Le51HE0060V2 Eval Board User Guide
19
Zarlink Semiconductor Inc.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
RING3
RED
TIP3
BLACK
DSLIC Channels 3 & 4 with LCAS
See note 1.
See note 1.
(Place 0 Ohm jumper within
outline of RS-2B resistor.)
(Place 0 Ohm jumper within
outline of RS-2B resistor.)
See Note 3
See Note 3
See Note 2
Socketed
1. Board may be assembled with either PTc's or resistors
Notes:
2. Due to socket design the thermal PAD (pin 45) could not be tied to the proper potential.
TIP4
BLACK
RING4
RED
Le51HE0060V2 2.0Z
Zarlink QLSLAC DSLIC 5712 Evaluation Board
C
47Wednesday, June 04, 2003
WPE
PPC - VNA
2136 North 13th st
Reading, Pa 19604
Title
Size Document Number Rev
Date: Sheet
of
Designer
VCC
AGND
AGND
BGND
BGND
BGND
VBAT1
VCC
VBAT1
VCC
VBAT1
BGND
BGND
BGND
BGND
VCC
AGND
VCC
AGND
AGND
AGND
BGND
BGND
BGND
AGND
AGND
AGND
AGND
AGND
AGND AGND
AGND
AGND
AGND
DSLIC_VCC
DSLIC_VCC
AGND
BGND
VBAT2
AGND
AGND
AGND
BGND
BGND
AGND
AGND
BGND
CP3
390pF
RRX3
75K
TIP3
1
BGND7
1
VREF2
1
C33
1
BD4
1
U3
LE5712
31
35
32
34
27
22
25
21
24
16
14
40
42
2
1
9
104411
8
7
30
26
37
19
33
23
43
12
5
4
29
45
3
6
13
15
39
18
36
28
20
38
17
41
AD1
HP1
BD1
[VBAT2] TMG1
VBAT
[VBAT2] TMG2
AD2
HP2
BD2
VTX2
RSN2
VTX1
RSN1
C11
C21
C12
C22
DET1
DET2
IREF
CAS
DB1
DB2
FLT1
FLT2
BGND1
BGND2
CDC1
CDC2
VCC
A/DGND
DAC
e-PAD
C31
NC [RD]
C32
NC [C42]
[R1] NC
NC [E1]
[RYE1] NC
[BSWTH] NC
[RYE2] NC
[VBREF] NC
[R2] NC
NC [C41]
CHP4
100nF
TIP4
1
DVBH34
MURS120
RFA4
50
CDET3
22nF
CFLT_3
1
JRSR4
123
R17
1.0K
CVTX4
100nF
U7
ATTL7581AAE
32
6
15 14
716
9 1
121110
8
4513
TLINETBAT
TRING
RBAT RLINE
VDDVBAT
DGND FGND
RRING
LATCH
INPUT
TSD
N/C
N/C
N/C
DET4
1
RP3
11K
MTRSG3
1
R15
1.0K
RMTR4
6.34K
CA4
NF
VTX4
1
J202
123
BGND6
1
CFLT4
100nF
PTCB4
RRSN3
0 Ohm
1 2
CA31
22nF
CAS2
1
CCAS2
330nF
RTA4
49.9K
CFLT3
100nF
RTMG4
1.6K
R12
1.0K
R11
1.0K
BD3
1
RFA3
50
RTB3
49.9K
C54
1
C7
100nF
VRX4
1
CB3
NF
HP3
1
CT3
1.5nF
12
BGND8
1
RD2
80.6
RDET4
100K
CVTX3
100nF
Q4
MMBT5087
J13
246
135
CVRX3
100nF
CVBH2
100nF
LDET4
5372T5
RXA4
4.99K
RHP4
15K
JRSR3
123
Q3
MMBT5087
RMTR3
6.34K
AD3
1
RRX4
75K
RHP3
15K
C43
1
RTB4
49.9K
C10
100nF
RING4
1
MTRSG4
1
RTA3
49.9K
BGND10
1
C11
100nF
CVB13
100nF
PTCA3
CT4
1.5nF
12
J19
1
2
VTX44
1
CDC3
330nF
CA3
NF
CDET4
22nF
J8
1
2
CXB3
1.5nF
Tip
Ring
Gnd
U9A
LMP1220U
1
2
3
AD4
1
CFLT_4
1
J5
1
2
RP4
11K
RDET3
100K
CVRX4
100nF
R16
1.0K
DVBL3
MURS120
LDET3
5372T5
CB41
22nF
C53
1
REF2
15K
CB31
22nF
RRTN3
0
C64
1
CP4
390pF
RRSN4
0 Ohm
1 2
CRSN4
390pF
12
JRST4
123
Tip
Ring
Gnd
U41
TISPL7585LF3D
4
5
1
2
3
678
CB4
NF
PTCB3
J7
1
2
C34
1
S3
TDS-04
123
45
8
RTMG3
1.6K
VTX3
1
CHP3
100nF
CRSN3
390pF
12
RFB3
50
C13
100nF
RFB4
50
R13
1.0K
HP4
1
VTX23
1
BGND9
1
DET3
1
C12
100nF
DVBL4
MURS120
VRX3
1
U6
ATTL7581AAE
32
6
15 14
716
9 1
121110
8
4513
TLINETBAT
TRING
RBAT RLINE
VDDVBAT
DGND FGND
RRING
LATCH
INPUT
TSD
N/C
N/C
N/C
JRST3
123
CA41
22nF
RRTN4
0
CXB4
1.5nF
RING3
1
CVB24
100nF
J201
123
C44
1
J6
1
2
C63
1
J14
246
135
CDC4
330nF
S4
TDS-04
123
45
8
RXA3
4.99K
PTCA4
VOUT3
CD13
CD23
C33
C43
C53
C63
VOUT4
CD14
CD24
C34
C44
C54
C64
VIN3
VIN4
DB3_SELECT
DAC34_SELECT
DB4_SELECT
E1
TS3R
RS3
RPRC3
RPRC4
RS4
TS4R
TSD3
TSD4
AGND
BGND
VBAT2
VCC
VBAT1
VREF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Power & Decoupling
BGND
AGND
DGND
+5V
+3.3V
VBAT2
VBAT1
Do Not Populate Socketed
Le51HE0060V2 2.0Z
Zarlink QLSLAC DSLIC 5712 Evaluation Board
B
5 7Wednesday, May 28, 2003
WPE
PPC - VNA
2136 North 13th st
Reading, Pa 19604
Title
Size Document Number Rev
Date: Sheet of
Designer
DGND
BGND
AGND
BGND
3.3V
VCC
VBAT2
VBAT1
AGND
DGND
AGND
DGND
BGND
BGND
Black
CC3 100nF
+
TC3
10uF
XU1 Le58QL063_TQFP_Blank
R9
0 Ohms
1 2
CC1 100nF
Black
Green
CC5 100nF
CC4 100nF
Green
Red
XU3 Le5712_TQFP_Blank
XU2 Le5712_TQFP_Blank
Red
Green
R10
0 Ohms
1 2
+
EC5 10uF
+
EC4 10uF
+
TC1
10uF
Tip
Ring
Gnd
U9B LMP1220U
4
5
6
VBAT2
VBAT1
VCC
DGND
AGND
BGND
3.3V
Le51HE0060V2 Eval Board User Guide
21
Zarlink Semiconductor Inc.
Le51HE0060V2 Eval Board User Guide
22
Zarlink Semiconductor Inc.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
To DSLIC1
To DSLIC2
QLSLAC & PCM/MPI Connections
Page 3
Page 4
To DSLIC 1 & 2 Diagrams
Pin 1 - 2 = MCLK input to QLSLAC
Pin 2 - 3 = E1 output to DSLIC
To Metering Diagram
Socketed
Le51HE0060V2 2.0Z
Zarlink QLSLAC DSLIC 5712 Evaluation Board
B
78Wednesday, May 28, 2003
WPE
PPC - VNA
2136 North 13th st
Reading, Pa 19604
Title
Size Document Number Rev
Date: Sheet
of
Designer
AGND
VCC
DGND
DGND
DGND
VCC
DGND
AGND
3.3V
VCC
AGND
AGND
AGND
DGND
3.3V
3.3V
3.3V
DGND1
1
AGND1
1
FS1
1
DGND5
1
DGND2
1
U1
Le58QL063
7
8
38
39
101142
43
34494731463337483236354150
45
44
1257565554535251
4564636261605958
131217181920212223
161524252627282930
9
6
3
14
40
VCCA1
VCCA2
VCCD1
VCCD2
AGND1
AGND2
DGND1
DGND2
RST
MCLK [E1]
DCLK [S0]
DRB
DIO [S1]
INT
DXA [DU]
CS [PG]
DRA [DD]
DXB
FS [FSC]
PCLK [DCL]
CHCLK
TSCA
TSCB
VOUT1
VIN1
CD11
CD21
C31
C41
C51
C61
C71
VOUT2
VIN2
CD12
CD22
C32
C42
C52
C62
C72
VOUT3
VIN3
CD13
CD23
C33
C43
C53
C63
C73
VOUT4
VIN4
CD14
CD24
C34
C44
C54
C64
C74
VREF
N/C
N/C
N/C
N/C
RE1
10K
J4
123
RDXA
10K
DGND7
1
VREF
1
DRA1
1
RTSCA
243
DRB1
1
C4
100nF
AGND2
1
CHCLK
1
DXB1
1
RDXB
10K
C1
100nF
IFB0
AMP-50
12345678910111213141516171819202122232425
26272829303132333435363738394041424344454647484950
DGND4
1
AGND3
1
/INT1
1
AGND4
1
PCLK1
1
CVREF
100nF
DCLK1
1
DIO1
1
DXA1
1
AGND5
1
MCLK1
1
C2
100nF
/RST1
1
JMCKE1
123
AGND6
1
/CS1
1
DGND6
1
J3
123
DGND3
1
C3
100nF
RTSCB
243
C34
C54
CD22
C51
C64
C41
CD14
C44
C31
CD21
VOUT3
CD11
CD23
VIN3
C61
C33
VIN1
C53
C63
VOUT1
CD12
CD13
VIN2
C43
E1
C42
VOUT4
C62
VOUT2
TSD3
CD24
C52
VIN4
C32
TSD4
AGND
DGND
VREF
3.3V
VCC
Le51HE0060V2 Eval Board User Guide
23
Zarlink Semiconductor Inc.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
RING IN
Channel 1 & 2
Channel 3 & 4
Battery Backed Ringing
Channel 3 & 4
Channel 1 & 2
(Off Board
Ringing
Signal)
RING
RETURN
Earth Backed Ringing
Notes:
1). Jumpers JS3 through JS9 are a single fixed block of shunts. Placing the shunt block between pins 1 & 2 will select the Battery Backed
Ringing circuit. Placing the shunt block across pins 2 & 3 will select the Earth Backed Ringing circuit. The last jumper in the block (JS9)
makes the ground connection to illuminate the appropriate LED as a visual indicator for which ringing circuit has been selected.
See note 1.
2). JS1 and JS2 must be positioned identical to the block shunt for JS3 to JS9. Placing the shunts between pins 1 & 2 will select the Battery
Backed Ringing. Placing the shunts between pins 2 & 3 will select Earth Backed Ringing.
RING FEED
SIGNAL.
RING FEED
SIGNAL.
RING FEED
SIGNAL.
RING FEED
SIGNAL.
RING FEED
SIGNAL.
(Jumper block JRS set to pins 2-3) (Jumper block JRS set to pins 1-2)
Channel 2 Channel 1 Channel 1Channel 2
Channel 3
Channel 3
Channel 4
Channel 4
Le51HE0060V2 2.0Z
Zarlink QLSLAC DSLIC 5712 Evaluation Board
C
77Friday, June 20, 2003
WPE
PPC - VNA
2136 North 13th st
Reading, Pa 19604
Title
Size Document Number Rev
Date: Sheet
of
Designer
BGND BGND
BGND
BGND
BGND
BGND BGND BGND
BGND
BGND
BGND
BGND
AGND
VCC
VCC
BGND
VBAT1
BGND
VBAT1
BGND
VBAT1
BGND
VBAT1
BGND
RTH1
1.8M
RBR1
200
RBB14
10M
JRS2
123
D11
5372T5
RRTH2
953K
JRS8
1
2
3
JRS4
1
2
3
RSR3
1M
TP6
1
Q13
MMBTA42
RBR2
200
RSR1
1M
TP15
1
CRBB2
22nF
TP12
1
JRS7
123
CRT1
100nF
RTH3
1.8M
CTH2
22nF
TP17
1
RSR2
1M
RBB10
10M
RBB13
10M
D12
5372T5
RPR2
200
RTH4
3.65M
RSR4
1M
RBB4
3.65M
Q11
MMBTA42
RSR11
1M
RR3
400
RTH2
3.65M
JRS3
1
2
3
RBB1
4.02M
RBR3
200
CTH3
22nF
CRT3
100nF
CTH1
22nF
RTH11
2M
TP14
1
JRS10
123
RSR33
1M
RPR3
200
RRTH3
1M
RBB7
10M
TP16
1
RSR44
1M
RBB11
10M
CRTH2
22nF
RR4
400
TP8
1
CRBB4
22nF
TP18
1
TP11
1
JRS13
123
Q12
MMBTA42
RBB3
4.02M
RR1
400
JRS5
123
Yellow
JRS11
123
RBR4
200
RRTH4
953K
RR2
400
RRTH1
1M
JRS1
123
CTH4
22nF
CRT2
100nF
RSR22
1M
TP7
1
RPR1
200
RTH33
2M
RBB2
3.65M
RPR4
200
Q14
MMBTA42
RTH22
4.02M
RBB8
10M
JRS9
1
2
3
RTH44
4.02M
TP9
1
JRS6
123
Black
RBB12
10M
RBB15
10M
JRS12
123
CRT4
100nF
TP10
1
CRTH4
22nF
RS3
RS4
RS2
RS1
TS2R
TS1R
TS4R
TS3R
DAC12_SELECT
DB2_SELECT
DB1_SELECT
RPRC2
RPRC1
RPRC3
RPRC4
DAC34_SELECT
DB4_SELECT
DB3_SELECT
AGND
BGND
VCC
VBat1
Le51HE0060V2 Eval Board User Guide
24
Zarlink Semiconductor Inc.
4.2 Le51HE0060V2 BILL OF MATERIALS
Item Quantity Reference Part Foot Print Manufacturer Part Number Distributor Distributor Part Number Tolerance Voltage Notes
1 115 VTX1,VRX1,VREF1,TIP1, TP SIP-1P KeyStone 5013 Digikey 5013K-ND
RING1,PCLK1,MTRSG1,MCLK1,
HP1,FS1,DXB1,DXA1,DRB1,
DRA1,DIO1,DGND1,DET1,
DCLK1,CFLT_1,CAS1,BGND1,
BD1,AGND1,AD1,/RST1,
/INT1,/CS1,VTX2,VRX2,
VREF2,TIP2,RING2,MTRSG2,
HP2,DGND2,DET2,CFLT_2,
CAS2,BGND2,BD2,AGND2,AD2,
VTX3,VRX3,TIP3,RING3,
MTRSG3,HP3,DGND3,DET3,
CFLT_3,BGND3,BD3,AGND3,
AD3,VTX4,VRX4,TIP4,RING4,
MTRSG4,HP4,DGND4,DET4,
CFLT_4,BGND4,BD4,AGND4,
AD4,DGND5,BGND5,AGND5,
TP6,DGND6,BGND6,AGND6,
TP7,DGND7,BGND7,TP8,
BGND8,TP9,BGND9,TP10,
BGND10,VTX11,TP11,K1TP1,
TP12,TP14,TP15,TP16,TP17,
TP18,K2TP1,VTX22,VTX23,
C31,C32,C33,C34,C41,C42,
C43,VTX44,C44,C51,C52,
C53,C54,C61,C62,C63,C64,
VREF,CHCLK
2 7 BJ1,BJ3,BJ5,BJ6,BJ12, B_Jack Pin3 SPC Technologies 845-GR Newark 39N869
BJ14,BJ16
3 6 BJ2,BJ4,BJ7,BJ8,BJ13, B_Jack Pin3 SPC Technologies 845-GR Newark 39N868
BJ15
4 3 BJ9,BJ10,BJ11 B_Jack Pin3 SPC Technologies 845-GR Newark 39N870
5 1 BJ17 B_Jack Pin3 SPC Technologies 845-GR Newark 39N871
6 8 CB1,CA1,CB2,CA2,CB3,CA3, NF 805
CB4,CA4
7 8 CB11,CA11,CB21,CA21,CB31, 22nF 1206 Vishay VJ1206Y223KXBMT Mouser 77-VJ12Y100V223K 10% 100V
CA31,CB41,CA41
8 2 CCAS1,CCAS2 330nF CK06 Kemet C062K334K1X5CA Mouser 80-CK06BX334K 10% 100V
9 13 CVTX1,CVRX1,CC1,CVTX2, 100nF 805 Kemet C0805C104K3RACTU Digikey 399-1168-1-ND 10% 25V
CVRX2,CVTX3,CVRX3,CC3,
CVTX4,CVRX4,C11,C13,
CVREF
10 4 CC4,CC5,C10,C12 100nF 1206 Kemet C1206C104K1RACTU Digikey 399-1805-1-ND 10% 100V
11 4 CDC1,CDC2,CDC3,CDC4 330nF 1206 Kemet C1206334K5RACTU Digikey 399-1285-1-ND 10% 25V
12 11 CTH1,CDET1,CTH2,CRTH2, 22nF XCK06 Kemet C062K223K1X5CA Mouser 80-CK06BX223K 10% 100V
CRBB2,CDET2,CTH3,CDET3,
CTH4,CRBB4,CDET4
13 8 CRT1,CFLT1,CRT2,CFLT2, 100nF XCK06 Kemet C062K104K1X5CA Mouser 80-CK06BX104K 10% 100V
CRT3,CFLT3,CRT4,CFLT4
14 12 CVB1,CPRT1,CHP1,CVBH2, 100nF 1210 Kemet C1210C1041RACTU Digikey 399-1268-1-ND 10% 100V
CPRT2,CHP2,CHP3,CHP4,
CVBL11,CVB13,CVBL22,
CVB24
15 4 CP1,CP2,CP3,CP4 390pF XCK05 Kemet C052K331K2X5CA Mouser 80-CK05BX331K 10% 200V
16 4 CRSN1,CRSN2,CRSN3,CRSN4 390pF XPin4 Kemet C052K391K25X5CA Mouser 80-CK05BX391K 10% 200V Open
17 1 CRTH4 22nF 1206 Panasonic ECJ-3YB2A223K Digikey PCC2010CT-ND 10% 100V
18 4 CT1,CT2,CT3,CT4 1.5nF XPin4 Kemet C052K152K1X5CA Mouser 80-CK05BX152K 10% 200V
19 4 CXB1,CXB2,CXB3,CXB4 1.5nF XCK06 Kemet C062K154K1X5CA Mouser 80-CK06BX154K 10% 100V
20 6 C1,C2,C3,C4,C6,C7 100nF 603 Kemet C0603C104K3RACTU Digikey 399-1281-1-ND 10%
21 8 DVBL1,DVBL2,D2,DVBL3, MURS120 SMB Diodes Inc MUR120 Digikey MURS120DICT-ND 200V
DVBL4,D5,DVBH12,DVBH34
Le51HE0060V2 Eval Board User Guide
25
Zarlink Semiconductor Inc.
Le51HE0060V2 Bill of Materials (Cont.)
22 8 RLED1,LDET1,RLED2,LDET2, 5372T5 2pin Chicago Miniture Lamp 5372T5-5VLC Digikey L20295-ND 5V
LDET3,LDET4,D11,D12
23 4 TC1,TC3,EC4,EC5 10uF F_Case_Code Panasonic ECE-V2AA100P Digikey PCE3206CT-ND 10% 100V
24 1 IFB0 AMP-50 Pin50 AMP-Tyco 552726-1 Digikey A1555-ND WACIF Connector
25 29 JRST1,JRSR1,JRS1,JMCKE1, JMPR 3 SIP-3P Sullens PTC36SAAN Digikey S1012-03-ND
JRST2,JRSR2,JRS2,JRST3,
JRSR3,JRS3,J3,JRST4,
JRSR4,JRS4,J4,JRS5,JRS6,
JRS7,JRS8,JRS9,JRS10,
JRS11,JRS12,JRS13,J101,
J102,J103,J201,J202
26 10 J5,J6,J7,J8,J10,J15,J16, 100 mil Header 2 pos Pin4 Sullens PTC36SAAN Digikey S1012-02-ND
J17,J18,J19
27 4 J11,J12,J13,J14 555163-1 Pin6 AMP 555163-1 Mouser 571-555-1631
28 2 K1,K2 RELAY_TX2-5V SMD12Pin Aromat TX2-5V Digikey 255-1034-5-ND 5V 2 Form C Contacts
29 8 PTCB1,PTCA1,PTCB2,PTCA2, PTC XPTC-FUSE Thermometrics 527-4510-120V50 Mouser RL4510-120-120-PTO 120V
PTCB3,PTCA3,PTCB4,PTCA4
30 130 P1-1,P1-2,P1-3,P1-4,P1-5, PinSocket_1 Pin063 MilMax 0295-0-15-01-0627100 Digikey ED5008-ND
P1-6,P1-7,P1-8,P1-9,
P1-10,P1-11,P1-12,P1-13,
P1-14,P1-15,P1-16,P1-17,
P1-18,P1-19,P1-20,P1-21,
P1-22,P1-23,P1-24,P1-25,
P1-26,P1-27,P1-28,P1-29,
P1-30,P1-31,P1-32,P1-33,
P1-34,P1-35,P1-36,P1-37,
P1-38,P1-39,P1-40,P1-41,
P1-42,P1-43,P1-44,P1-45,
P1-46,P1-47,P1-48,P1-49,
P1-50,P1-51,P1-52,P1-53,
P1-54,P1-55,P1-56,P1-57,
P1-58,P1-59,P1-60,P1-61,
P1-62,P1-63,P1-64,P1-65,
P1-66,P1-69,P1-70,P1-71,
P1-72,P1-73,P1-74,P1-75,
P1-76,P1-88,P1-89,P1-90,
P1-92,P1-93,P1-94,P1-95,
P1-96,P1-97,P1-98,P1-99,
P1-101,P1-103,P1-104,
P1-105,P1-106,P1-107,
P1-108,P1-110,P1-111,
P1-112,P1-114,P1-115,
P1-116,P1-117,P1-118,
P1-119,P1-121,P1-122,
P1-123,P1-125,P1-126,
P1-127,P1-128,P1-129,
P1-130,P1-67-3W,P1-68-3W,
P1-77-3W,P1-78-3W,
P1-79-1W,P1-80-1W,
P1-81-1W,P1-82-1W,
P1-83-2W,P1-84-2W,
P1-85-2W,P1-86-2W,
P1-87-2W,P1-91-2W,
P1-100-2W,P1-102-2W,
P1-109-2W,P1-113-2W,
P1-120-2W,P1-124-2W
31 130 P2-1,P2-2,P2-3,P2-4,P2-5, PinSocket_2 Pin063 MilMax 0295-0-15-01-0627100 Digikey ED5008-ND
P2-6,P2-7,P2-8,P2-9,
P2-10,P2-11,P2-12,P2-13,
P2-14,P2-15,P2-16,P2-17,
P2-18,P2-19,P2-20,P2-21,
P2-22,P2-23,P2-24,P2-25,
Le51HE0060V2 Eval Board User Guide
26
Zarlink Semiconductor Inc.
Le51HE0060V2 Bill of Materials (Cont.)
P2-26,P2-27,P2-28,P2-29,
P2-30,P2-31,P2-32,P2-33,
P2-34,P2-35,P2-36,P2-37,
P2-38,P2-39,P2-40,P2-41,
P2-42,P2-43,P2-44,P2-45,
P2-46,P2-47,P2-48,P2-49,
P2-50,P2-51,P2-52,P2-53,
P2-54,P2-55,P2-56,P2-57,
P2-58,P2-59,P2-60,P2-61,
P2-62,P2-63,P2-64,P2-65,
P2-66,P2-69,P2-70,P2-71,
P2-72,P2-73,P2-74,P2-75,
P2-76,P2-88,P2-89,P2-90,
P2-92,P2-93,P2-94,P2-95,
P2-96,P2-97,P2-98,P2-99,
P2-101,P2-103,P2-104,
P2-105,P2-106,P2-107,
P2-108,P2-110,P2-111,
P2-112,P2-114,P2-115,
P2-116,P2-117,P2-118,
P2-119,P2-121,P2-122,
P2-123,P2-125,P2-126,
P2-127,P2-128,P2-129,
P2-130,P2-67-3W,P2-68-3W,
P2-77-3W,P2-78-3W,
P2-79-1W,P2-80-1W,
P2-81-1W,P2-82-1W,
P2-83-2W,P2-84-2W,
P2-85-2W,P2-86-2W,
P2-87-2W,P2-91-2W,
P2-100-2W,P2-102-2W,
P2-109-2W,P2-113-2W,
P2-120-2W,P2-124-2W
32 4 QRL1,QRL2,QRL3,QRL4 MMBT5088 SOT23 Fairchild MMBT5088 Digikey MMBT5088CT-ND 30Vce
33 4 Q1,Q2,Q3,Q4 MMBT5087 SOT23 Fairchild MMBT5087 Digikey MMBT5087CT-ND 50Vce
34 4 Q11,Q12,Q13,Q14 MMBTA42 SOT23 Fairchild MMBT5088 Digikey 512-MMBTA42 300Vce
35 4 RBB1,RBB3,RTH22,RTH44 4.02M X1/4W Vishay CMF-60-4024F Mouser 71RN60D-F-4024 1%
36 4 RTH2,RBB2,RTH4,RBB4 3.65M X1/4W Vishay CMF-60-3654F Mouser 71RN60D-F-3654 1%
37 8 RBB7,RBB9,RBB10,RBB11, 10M 805 Panasonic ERJ-6ENF1005V Digikey P1005CTR-ND 1%
RBB12,RBB13,RBB14,RBB15
38 8 RPR1,RBR1,RPR2,RBR2,RPR3, 200 X2W Vishay CPF2-200-F Mouser 71-CPF2-F-200 1%
RBR3,RPR4,RBR4
39 1 RDET1 100K 805 Panasonic ERJ-6EN1003V Digikey P1003CTR-ND 1%
40 3 RDET2,RDET3,RDET4 100K 805 Panasonic ERJ-6ENF1003V Digikey P1003CTR-ND 1%
41 7 RRLY1,RE1,RRLY2,RRLY3, 10K 805 Panasonic ERJ-6ENF1002V Digikey P1002CTR-ND 1%
RRLY4,RDXB,RDXA
42 2 RD1,RD2 80.6 X1/4W Vishay CMF-60-80R6F Mouser 71RN60D-F-80R6 1%
43 2 REF1,REF2 15K X1/4W Vishay CMF-60-1502F Mouser 71RN60D-F-1502 1%
44 8 RFB1,RFA1,RFB2,RFA2,RFB3, 50 XRNC90Y Vishay RNC90Y-50R00BM 0.01%
RFA3,RFB4,RFA4
45 4 RHP1,RHP2,RHP3,RHP4 15K 805 Panasonic ERJ-6ENF1502V Digikey P1502CTR-ND 1%
46 4 RMTR1,RMTR2,RMTR3,RMTR4 6.34K 805 Panasonic ERJ-6ENF6341V Digikey P6341CTR-ND 1%
47 4 RP1,RP2,RP3,RP4 11K X1/4W Vishay CMF-1102F Mouser 71RN60D-F-1102 1%
48 3 RRSN1,RRSN2,RRSN3 0 Ohm XRES-1/4W
49 1 RRSN4 0 Ohm RES-1/4W
50 10 RSR1,RRTH1,RSR2,RSR3, 1M X1/4W Vishay CMF-1004F Mouser 71RN60D-F-1004 1%
RRTH3,RSR4,RSR11,RSR22,
RSR33,RSR44
51 2 RRTH2,RRTH4 953K X1/4W Vishay CMF-60-9533F Mouser 71RN60D-F-9533 1%
52 2 RRTN2,RRTN1 50 X3W Vishay CPF3-50F Mouser 71-CPF3-F-50 1%
53 2 RRTN3,RRTN4 0 X3W Vishay CPF3-50F Mouser 71-CPF3-F-50 1%
54 4 RRX1,RRX2,RRX3,RRX4 75K X1/4W Vishay CMF-7502F Mouser 71RN60D-F-7502 1%
Le51HE0060V2 Eval Board User Guide
27
Zarlink Semiconductor Inc.
Le71HE00602V Bill of Materials (Cont.)
55 4 RR1,RR2,RR3,RR4 400 X2W Vishay CPF2-400-F Mouser 71-CPF2-F-400 1%
56 8 RTB1,RTA1,RTB2,RTA2,RTB3, 49.9K X1/4W Vishay CMF-4992F Mouser 71RN60D-F-4992 1%
RTA3,RTB4,RTA4
57 2 RTH1,RTH3 1.8M X1/4W Vishay CMF-60-1804F Mouser 71RN60D-F-1804 1%
58 2 RTH11,RTH33 2M X1/4W Vishay CMF-60-2004F Mouser 71RN60D-F-2004 1%
59 4 RTMG1,RTMG2,RTMG3,RTMG4 1.6K RS-2B
60 2 RTSCA,RTSCB 243 805 Panasonic ERJ-6EN2430V Digikey P2430CTR-ND 1%
61 4 RXA1,RXA2,RXA3,RXA4 4.99K X1/4W Vishay CMF-4991F Mouser 71RN60D-F-4991 1%
62 12 R1,R2,R3,R5,R6,R7,R11, 1.0K 805 Panasonic ERJ-6EN1001V Digikey P1001CTR-ND 1%
R12,R13,R15,R16,R17
63 2 R9,R10 0 Ohms X1/4W
64 4 S1,S2,S3,S4 TDS-04 DIP8pin APEM TSD04 Go Electronics TDS04
65 1 U1 Le58QL063 TQFP64_Socket Nepenthe QP1-064050-108 Socket for LE58QL063V
66 2 U2,U3 LE5712 TQFP44_Socket Wells CTI 7010-044-X-08 Socket for the LE5712
67 2 U7,U6 ATTL7581AAE AGERE-L7581
68 1 U9 LMP1220U SOIC6pin Teccor LMP1220U 130TipV/220RingV
69 1 U40 TISP6NTP2A_SOIC SOIC8pin Bourns -90
70 1 U41 TISPL7585LF3D SOIC8pin Power Innovations TISP758LF3D 130TipV/220RingV
71 2 U42,U43 B1161UC MS-013 Teccor B1161UC NF
72 1 XU1 Le58QL063_TQFP_Blank XTQFP64 Nepenthe Le58QL063VC Socket for LE58QL063V
73 2 XU3,XU2 Le5712_TQFP_Blank XTQFP44 Wells CTI 7010-044-X-08 Socket for the LE5712
APPENDIX
Glossary 27
A
GLOSSARY
The following is a list of terms and their definitions, as used in this manual.
ACIF2-A Advanced Computer Interface Board second design, revision A. This board works
with the WinACIF Software program and is used as an interface between the host PC and evaluation board via a serial interface.
GCI General Circuit Interface. Allows for a common data highway that conveys the PCM
encoded voice data, device programming commands and data, and loop control and status information.
Mini-PBX Software
Embedded software application that runs on the VP Demo Board and provides real­time operation of the evaluation boards and line modules to allow performance and evaluation in a real-time operational environment.
MPI Microprocessor Interface. Communicates with an external microprocessor over a
serial interface. It passes user control information to internal blocks of the VoSLAC device and passes status information from the internal blocks to the user.
PCM Pulse Code Modulation. The modulation scheme involving sampling digitization,
filtering and encoding of an audio waveform.
SLIC Subscriber Line Interface Circuit. Provides telephone interface functions to the two-
wire telephone line. Supports BORSCHT functions.
VP Demo Board
Voice Path Demo Board. The board is used with the VP-Script software.
VP-Script Software
Voice Path Script software. Windows based interactive program. Provides interactive control of the VoSLAC device registers, filters and operating commands. Supports PCM mode only.
WinACIF Windows
®
based Advanced Computer Interface software program that provides interactive control of the VoSLAC device registers, filters and operating commands. Supports PCM and GCI modes.
WinSLAC2 Windows based software tool that aids in the calculation of coefficients for the
programmable filters of a SLAC device along with predicted performance of system parameters.
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