Le51HE0060V2
Le58QL063 QLSLAC™ /
Le5711/12 DSLIC™
Evaluation Board User’s Guide
Rev. A, Ver. 2
October 2, 2007
Document Number: 081167
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capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a sp ecific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
Purchase of Zarlink’s I
conforms to the I
Zarlink, ZL , th e Zarlink Se miconductor lo go an d th e L egerity l ogo an d co mbinations the reof, VoiceEdge, VoicePort, SLAC , ISLI C, ISLAC an d V oicePath are
trademarks of Zarlink Semiconductor Inc.
2C components conveys a lic ense under the Philips I2C Patent rights to use these components in an I2C System, provided that the system
2C Standard Specification as defined by Philips.
TECHNICAL DOCUMENTATION - NOT FOR RESALE
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Zarlink Semiconductor Inc.
Document ID# 081167 Date: Oct 2, 2007
Rev: A Version: 2
Distribution: Public Document
TABLE OF CONTENTS
CHAPTER 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 DSLIC™ eTQFP (Exposed Pad) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
CHAPTER 2 BOARD SETUP AND CONNECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Board Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Board Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.1 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.2 Telephone Line Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3 Interconnection of the Le51HE0060V2 Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4 PCM/MPI Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
CHAPTER 3 BOARD OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Jumper Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Jumper And Switch Settings For The Le51HE0060V2 Evaluation Board . . . . . . . . . . . . . . 8
CHAPTER 4 SOFTWARE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CHAPTER 5 SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 Evaluation Board Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 Le51HE00602V Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
CHAPTER 6 GLOSSARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Le51HE0060V2 Eval Board User Guide
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CHAPTER
1
Zarlink Semiconductor Inc.
1
INTRODUCTION
1.1 OVERVIEW
The Zarlink Le51HE0060V2 evaluation board provides a platform to evaluate the capabilities of
the Le58QL063 QLSLAC™ and Le5711/12 DSLIC™ devices. All digital control signals, voice band
and MPI signals have test points for easy probing. Power is brought to the board via a set of banana
jack connectors. The QLSLAC device and the two DSLIC devices are mounted in ZIF sockets.
Detailed device explanations, operational circuit descriptions and required formulas can be found
within the individual QLSLAC and DSLIC device data sheets. Figure 1–1
shows the physical layout
of the Le51HE0060V evaluation board. Figure 1–2
shows a block diagram.
Figure 1–1 Le51HE0060V2 Evaluation Board
1.2 DSLIC™ eTQFP (Exposed Pad)
The Le5711/12 DSLIC device has an exposed thermal pad (heat slug) on the underside of the
device. This pad should be connected to VBAT for thermal relief (see the Thermal Design for
Le5711 and Le5712 application note for details of the connection). However, due to the type of
sockets used the connection to VBAT could not be made. Because of the socket, thermal
performance may be compromised. Do not connect to any other voltage.
Le51HE0060V2 Eval Board User Guide
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Figure 1–2 Le51HE0060V2 Evaluation Board Block Diagram
QSLAC
DSLIC
DSLIC
Channel
1
Interface
(EMR)
Channel
2
Interface
(EMR)
Channel
3
Interface
(LCAS)
Channel
4
Interface
(LCAS)
Ringing Voltage
Distribution
Circuits
Power Distribution and Filtering
PCM/MPI Interface
Tip/Ring 1
Tip/Ring 2
Tip/Ring 3
Tip/Ring 4
To all circuits
VBAT1,
VBAT2,
BGND, +5 V, AGND
+3.3 V, DGND
Ringing Voltage
Ringing Rtn
Manual DSLIC
Controls
CHAPTER
3
Zarlink Semiconductor Inc.
2
BOARD SETUP AND CONNECTION
2.1 BOARD FEATURES
The Le51HE0060V2 evaluation board design features the following:
• MPI/PCM Connector
• TIP/RING banana jacks and RJ-11 connectors
• Test Points for all major signals
• Banana jacks for all power connections
• QSLAC or manual control of DSLIC devices
• Two channels of solid state ringing switches and two channels of EMR ringing switches
• Battery or earth backed ringing
• Socketed components for easier evaluation
• On-board protection for tip/ring
• Meter rejection filtering
• DC parameters programmable via easy to change socketed components
• AC parameters programmable through the QLSLAC device
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2.2 BOARD CONNECTIONS
The Le51HE0060V2 can be plugged directly into either a Voice Path Demo (VP Demo) Board or an
Advanced Computer Interface Board (ACIF2-A) via the 50-pin IFB01 connector of the
Le51HE0060V2 evaluation board. All power is supplied via the nine banana jacks across the top of
the board. est points are included for all major signals. Eight banana jacks, labeled TIP
X
and
RING
X
, are located on the right-hand edge of the evaluation board for connection to test equipment
or for connecting to a standard telephone station set. These jacks are also connected in parallel
with an industry standard RJ-11 connector.
2.2.1 Power
The required power for the board is supplied through nine banana jacks, as detailed in Table 2–1.
Table 2-1 Power Connections
Before connecting a ringing supply, the user should assure that the jumpers used for earth/battery
backed ringing selection are appropriately set. Details are contained in Chapter 3
Power sequencing is recommended, though not required. The suggested power sequencing
scheme is: VBAT1 powered-up first, followed by VBAT2, +3.3 V, and finally the +5-V supply. DGND
and AGND are tied together on the board with zero ohm resistors R9 and R10. BGND is not tied to
either AGND or DGND and care is required to assure that the maximum potential difference
between these points, as defined in the DSLIC data sheet, is not exceeded
2.2.2 Telephone Line Interface
To interface the Le51HE0060V2 evaluation board to a telephone station set, plug the telephone
station set into the TIP and RING banana jack pair (BJ1 and BJ2, BJ3 and BJ4, BJ12 and BJ13 or
BJ14 and BJ15). Alternately, the RJ-11 jacks (J11, J12, J13, J14) can be used.
A tip/ring surge protection circuit is included on the board. The LCAS protection circuits use a fixed
voltage protection scheme while the EMR protection circuits use a battery referenced protection
scheme.
Jack # Signal Description Board Name (PW1)
BJ5 VBAT1 Battery Supply, higher absolute voltage VBAT1
BJ6 VBAT2 Battery Supply, lower absolute voltage VBAT2
BJ7 +5 V Five volt analog supply Vcc
BJ8 +3.3 V 3.3-V digital supply 3.3 V
BJ9 DGND Digital ground, return for the +3.3-V supply DGND
BJ10 AGND Analog ground, return for the +5-V supply. AGND
BJ11 BGND Battery ground BGND
BJ16 Ring In Ringing voltage source Ring in
BJ17 Ring Return Ringing voltage return Ring return
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2.3 INTERCONNECTION OF THE Le51HE0060V2 EVALUATION BOARD
A representative connection of a complete Zarlink evaluation platform setup is shown in
Figure 2–1
and Figure 2–2 below.
Figure 2–1
shows the evaluation board connected to the 50-pin connector (SPA) of the VP Demo
board. The host PC runs the VP-Script Software. Commands are passed through the VP Demo
board, via a serial COM port, to the evaluation board.
Figure 2–1 Le51HE0060V2 Evaluation Board to VP Demo Board Connection Diagram
Analog access to test equipment is connected to the TIP/RING connectors of the Le51HE0060V2
evaluation board. Digital PCM access to test equipment is provided through the VP Demo Board.
Figure 2–2
shows the evaluation board connected to the 50-pin connector LNB#0 of the ACIF2-A
Board. The host PC runs the WinACIF Software. Commands are passed through the ACIF2-A
board, via a serial COM port, to the evaluation board.
Figure 2–2 Le51HE0060V2 Evaluation Board to ACIF2-A Connection Diagram
Analog access to test equipment is connected to the TIP/RING connectors of the L371HE0060V2
evaluation board. Digital PCM access to test equipment is provided through the ACIF2-A Board.
VP Demo
Board
QLSLAC
Le5711/12
PCM-4
Analog
Telephone Telephone
T1/E1
Telephone
Telephone
ACIF2-A
Board
QLSLAC
Le5711/12
PCM-4
Digital
Analog
Telephone Telephone
Telephone Telephone
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2.4 PCM/MPI CONNECTIONS
All PCM/MPI interface signals are passed through the ACIF connector. Pinout for the VP Demo
Board SPA connector is shown below.
The QLSLAC device multiplexes Data In and Data Out on the same pin, DIO. To assure the VPScript Software will look for Data In and Data Out on the same pin, after starting the VP-Script
program, the user will need to open the PCM sub-menu and set chip select to CS11 and DIO to
combined.
Table 2–1 PCM/MPI Connections
Pin # Signal Pin # Signal
1 RST 26 Digital Ground
2 MCLK 27 Digital Ground
3 DCLK 28 Digital Ground
4 DRB 29 Digital Ground
5 DIO 30 Digital Ground
6 INT 31 Digital Ground
7 DXA 32 Digital Ground
8 CS 33 Digital Ground
9 DRA 34 Digital Ground
10 DXB 35 Digital Ground
11 FS 36 Digital Ground
12 PCLK 37 Digital Ground
13-25 N/C 38-50 Digital Ground
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