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Zynq-7000
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Xilinx Zynq-7000 User Manual

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Zynq-7000 AP SoC and 7 Series Devices Memory Interface Solutions v4.1
User Guide
UG586 November 30, 2016
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Date Version Revision
• Renamed QuestaSim to Questa Advanced Simulator.
QDR II+
• Updated qdr_k_n/p directions in Physical Interface Signals table.
11/30/2016 4.1
10/05/2016 4.1
06/08/2016 4.0
04/06/2016 3.0
• Updated in qdr_k_n/p directions I/O Standards table.
RLDRAM II/RLDRAM 3
• Updated rld_dk_p/n directions in Physical Interface Signals table.
• Updated rld_dk_p/n directions in RLDRAM II I/O Standards and RLDRAM 3 Standards tables.
• Updated to core version 4.1.
• Updated file name path to _ex/imports in all sections.
DDR3 and DDR2
• Updated Controller Options Page figure.
• Added Number of Bank Machines bullet in the Controller Options section.
DDR3 and DDR2
• Updated Memory Part description in Controller Option section.
• Added app_ecc_single_err[7:0] in Table 1-17: User Interface table.
• Added app_ecc_single_err[7:0] and note in Table 1-56: User Interface for ECC Operation.
• Updated description in dbg_pi_phase_locked_phy4lanes and dbg_pi_dqs_found_lanes_phy4lanes in Table 1-74: DDR2/DDR3 Debug Signals.
• Updated to core version 3.0.
• Updated Termination for all sections.
• Updated 1.0 µF capacitor in General Memory Routing Guideline chapter.
DDR3 and DDR2
• Added note in FPGA Options section.
• Added note in Interfacing to the Core section.
• Updated sys_rst descriptions in DDR3 and DD2 Configuration sections.
• Added note in Debug Signals section.
• Updated reset description in General Checks section.
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Date Version Revision
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• Added asynchronous to sys_rst in all sections.
• Added note to RELAXED mode in DDR3/DDR2 and LDDR2 sections.
• Updated code in all Configuration sections
• Added Important jitter note in Pinout Requirements in all sections.
DDR3 and DDR2
• Added Synplify Pro Black Box Testing section.
11/18/2015 2.4
09/30/2015 2.4
06/24/2015 2.3
QDR II+
• Updated DEBUG_PORT Signal Descriptions, Write Init Debug Signal Map, and Read Stage 1 Debug Signal Map tables.
• Updated Calibration of Read Clock and Data description.
• Updated Write Calibration description.
RLDRAM II/ RLDRAM 3
• Updated Read Stage 1 Debug Signal Map table.
• Updated Calibration of Read Clock and Data description.
• Added CLOCK_DEDICATED_ROUTE Constraints in all sections.
DDR3 and DDR2
• Updated Trace Lengths section.
QDR II+
• Added Termination section.
RLDRAM II/ RLDRAM 3
• Added Termination section.
• Updated Margin Check section.
• Updated Automatic Margin Check section.
• Updated Table 3-33: Debug Port Signals.
LPDDR2
• Updated Trace Lengths section.
Appendix
• Added General Memory Routing Guidelines.
• Added Simulation Flow Using VCS and IES to all sections.
• Added Clocking sections to QDR II+, RLDRAM II/RLDRAM 3, and LPDDR2 chapters.
RLDRAM II/ RLDRAM 3
• Added address/control signal and SSI descriptions in Pinout Requirements section.
• Updated Input Clock Guidelines section.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 3
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• Updated description in all Configuration sections.
• Updated SIM_BYPASS_INIT_CAL.
Chapter 1
• Added description in Setting DDR3 Memory Parameter Option section.
• Added Note to Answer Record: 54025 in Controller Options section.
• Added description to app_rd_data_end in Table 1-17: User Interface.
• Updated Table 1-19: AXI4 Slave Interface Parameters.
• Updated description in AXI4 Slave Interface Signals section.
• Updated Time Division Multiplexing (TDM), Round-Robin, and Read Priority (RD_PRI_REG) sections.
• Updated GES description in Calibration Times section.
• Updated Fig. 1-50: Clocking Architecture.
• Updated Table 1-87: Memory Controller to Calibration Logic Interface Signals.
• Updated AXI Addressing section.
• Updated Write Path section.
• Updated Fig. 1-84: Command Processing.
04/01/2015 2.3
Continued
• Updated Physical Layer Interface (Non-Memory Controller Design) section.
• Updated CK signal description in Trace Length section.
• Updated Fig. 1-93: Calibration Stages.
• Updated description in Determine the Failing Calibration Stage section.
• Updated Table 1-100: DDR2/DDR3 Debug Signals.
• Updated Table 1-102: Debug Signals of Interest for Write Leveling Calibration.
• Updated Table 1-103: Debug Signals of Interest for MPR Read Leveling Calibration.
• Updated calibration overview in Debugging OCLKDELAYED Calibration Failures section.
• Updated Debug bullets in Debugging OCLKDELAYED Calibration Failures section.
• Updated Table 1-104: Debug Signals of Interest for OCLKDELAYED Calibration to Table 1-106: Debug Signals of Interest for Read Leveling Stage 1 Calibration.
• Updated Table 1-108: Calibration Time in Hardware.
• Updated Checking and Varying Read Timing to Manual Window Check sections.
• Updated Calibration Times section.
Chapter 2
• Updated Fig. 2-43: High-Level PHY Block Diagram for a 36-Bit QDR II+ Interface.
• Updated Margin Check and Automated Margin Check sections.
Chapter 3
• Updated description in Interfacing with the Core through the Client Interface section.
Chapter 4
• Corrected app_wdf_data[APP_DATA_WIDTH – 1:0] and app_wdf_mask[APP_MASK_WIDTH – 1:0] sections.
• Updated Fig. 4-43: Clocking Architecture.
• Updated Read Path section.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 4
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Chapter 1
• Updated description in Round-Robin section.
• Updated RTT_WR in Table 1-92: 7 Series FPGA Memory Solution Configuration Parameters.
11/19/2014 2.3
10/01/2014 2.2
Continued
• Updated description in Debugging OCLKDELAYED Calibration Failures section.
• Updated Table 1-106: Debug Signals of Interest for OCLKDELAYED Calibration.
•Updated GES time in Calibration Times section.
• Updated bits in left_loss_pb and right_gain_pb in Table 1-109: Debug Signals of Interest for PRBS Read Leveling Calibration.
• Global update to example design link in Files in example_design/sim Directory tables, updated links in Simulation Flow Using IES and VCS Script Files section, updated Simulation Flow Using Vivado Simulator section, and updated Simulation Flow Using QuestaSim section.
Chapter 1
• Updated Reference Clock description in FPGA Option section.
• Updated C_S_AXI_DATA_WIDTH description in Table 1-19: AXI4 Slave Interface Parameters.
• Updated Fig. 1-50: Clocking Architecture.
• Updated OCLKDELAYED Calibration section.
• Updated Write Path section.
• Added REF_CLK_MMCM_IODELAY_CTRL in Table 1-92: 7 Series FPGA Memory Solution Configuration Parameters.
• Added note for nBANK_MACHS in Table 1-93: Embedded 7 Series FPGAs Memory Solution Configuration Parameters.
• Added row and updated Table 1-94: DDR2/DDR3 SDRAM Memory Interface Solution Pinout Parameters
• Updated CK/CK# bullet in Trace Length section.
• Updated Table 1-102: DDR2/DDR3 Debug Signals.
• Updated debug signals in Table 1-112: Debug Signals Used for Checking and Varying Read/Write Timing.
Chapter 2
• Added Bank Sharing Among Controllers section in Design Guideline section.
Chapter 3
• Added Bank Sharing Among Controllers section in Design Guideline section.
Chapter 4
• Updated Figs. 4-57 to 4-59 and Figs. 4-62 to 4-63.
• Updated 2:1 description in Write Path section.
• Updated rules in Termination section.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 5
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Chapter 1
• Added reference to data sheet in Features section.
• Added Important note about Data Mask in Controller Options section.
• Added note in Precharge Policy section.
• Added PRBS_SADDR_ MASK)POS to Table 1-11: Traffic Generator Parameters Set in the example_top Module.
• Updated IDELAYCTRL frequency in IDELAYCTRL section.
• Updated IDELAY Reference Clock section.
• Updated PRBS Read Leveling section.
• Updated CL description for DDR3 in Table 1-93: Embedded 7 Series FPGAs Memory Solution Configuration Parameters.
• Updated package length descriptions in Trace Length section.
• Added simulation description in Note in Debugging DDR3/DDR2 Designs.
• Updated description in Debugging PRBS Read Leveling Failures section.
06/04/2014 2.1
Continued
• Updated Table 109: Debug Signals of Interest for PRBS Read Leveling Calibration.
Chapter 2
• Added reference to data sheet in Introduction section.
• Updated package length descriptions in Trace Length Requirements section.
• Added CPT_CLK_SEL_* row in Table 2-11: QDR II+ SRAM Memory Interface Solution Pinout Parameters.
• Added simulation description in Note in Debugging QDR II+ Designs.
Chapter 3
• Added reference to data sheet in Features section.
• Added note in Memory Controller section.
• Added PRBS_SADDR_ MASK)POS to Table 3-8: Traffic Generator Parameters Set in the example_top Module.
• Updated rules and package length descriptions in Trace Length Requirements section.
• Added simulation description in Note in Debugging RLDRAM II and 3 Designs.
Chapter 4
• Added note in Precharge Policy section.
• Added PRBS_SADDR_ MASK)POS to Table 4-11: Traffic Generator Parameters Set in the example_top Module.
• Updated package length descriptions in Trace Length Requirements section.
• Added simulation description in Note in Read Path section.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 6
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Chapter 1
• Updated book to DQS.
• Updated Table 1-4: Files in example_design/sim Directory.
• Updated file description in Simulation Flow Using IES and VCS Script Files section.
• Added No Buffer description in the System Clock bullet in FPGA Options section.
• Updated mc_data_offset description in Memory Controller to Calibration Logic Interface Signals table.
• Added MPR read leveling process in Multi-Purpose Register Read Leveling section.
• Updated Temperature Monitor section.
• Added tempmon information in Physical Layer Interface (Non-Memory Controller Design) section.
• Added description in address and control signals in Termination section for DDR3.
• Added description in address and control signals and updated CKE signal bullet in Termination section for DDR2.
• Added CK description in Trace Lengths section.
• Added new code constraints for DDR3/DDR2 Configuration sections.
04/02/2014 2.0
• Added Clocking section.
• Updated ocal signals in Table 1-102: DDR2/DDR3 Debug Signals.
Chapter 2
• Added new code constraints in Configuration section.
• Updated Table 2-3: Files in example_design/sim Directory.
• Updated file description in Simulation Flow Using IES and VCS Script Files section.
Chapter 3
• Added new code constraints in Configuration section.
• Updated Table 3-3: Files in example_design/sim Directory.
• Added important note on write and read commands in Interfacing with the Core through the Client Interface section.
• Updated option for MRS_RD_LATENCY in RLDRAM II Memory Interface Solution Configurable Parameters table.
• Updated file description in Simulation Flow Using IES and VCS Script Files section.
Chapter 4
• Added new code constraints in Configuration section.
• Updated Table 4-4: Files in example_design/sim Directory.
• Updated file description in Simulation Flow Using IES and VCS Script Files section.
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Date Version Revision
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• Vivado Design Suite release only for MIG v2.0.
Chapter 1
• Added Out of Context content.
• Updated Table 1-4: Modules in example_design/sim Directory.
• Updated <component name>/user_design section.
• Updated Fig. 1-39: Synthesizable Example Design Block Diagram.
• Added simulator flows.
• Added Bits[39:32] to Table 1-15: Debug Status for the Write Transaction.
• Added Bits[39:32] to Table 1-16: Debug Status for the Read Transaction.
• Added OOC description in Customizing the Core section.
• Added ILA trigger settings in Vivado Lab Tools section.
• Added note on read latency in Debug section.
• Updated Chipscope triggers to R in Debug section.
Chapter 2
• Added Out of Context content.
• Updated Table 2-3: Modules in example_design/sim Directory.
• Updated <component name>/user_design section.
• Added OOC description in Customizing the Core section.
• Added simulator flows.
12/18/2013 2.0
• Added ILA trigger settings in Vivado Lab Tools section.
Chapter 3
• Added Out of Context content.
• Updated Table 3-3: Modules in example_design/sim Directory.
• Updated <component name>/user_design section.
• Updated Fig. 3-35: Synthesizable Example Design Block Diagram.
• Added OOC description in Customizing the Core section.
• Added simulator flows.
• Added ILA trigger settings in Vivado Lab Tools section.
• Updated Fig. 3-48 Write Path Block Diagram of the RLDRAM II Interface Solution.
• Added note on read latency in Debug section.
Chapter 4
• Added Out of Context content.
• Updated Table 4-4: Modules in example_design/sim Directory.
• Updated <component name>/user_design section.
• Updated Fig. 4-37: Synthesizable Example Design Block Diagram.
• Added OOC description in Customizing the Core section.
• Added simulator flows.
• Added note on read latency in Debug section.
Chapter 5
• Added Out of Context content.
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• Vivado Design Suite release only for MIG v2.0.
• Removed ISE content throughout book and updated screenshots to v2.0.
Chapter 1
• Updated Memory Part bullet description.
• Updated Table 1-4 sim.do description and simulation directory.
• Updated Fig. 1-44 7 Series FPGAs MIS.
• Added aresetn in Table 1-20 AXI4 Slave Interface Signals.
• Added Caution note in Single Error and Double Error Reporting section.
• Updated Table 1-77 Memory Interface Commands.
• Updated and added stage 3 tap in OCLKDELAYED Calibration section.
• Added #4 table note to Table 1-91 7 Series FPGA Memory Solution Configuration Parameters.
• Updated description in app_wdf_mask[APP_MASK_WIDTH - 1:0] section.
• Added Memory Address Mapping description in User Interface section.
• Updated Table 1-106 Debug Signals of Interest for OCLKDELAYED Calibration
Chapter 2
10/02/2013 2.0
• Updated Table 2-3 sim.do description and simulation directory.
• Updated DIFF_HSTL_I in I/O Standards table.
• Updated reference clock descriptions in Clocking Architecture section.
• Added #1 table note to Table 2-11 7 Series FPGAs QDR II+ SRAM Memory Interface Solution Configurable Parameters. And updated SIM_BYPASS_INIT_CAL.
Chapter 3
• Updated Table 3-3 sim.do description and simulation directory.
• Updated reference clock descriptions in Clocking Architecture section.
• Added #1 table note to Table 3-13 RLDRAM II Memory Interface Solution Configurable Parameters. And updated SIM_BYPASS_INIT_CAL.
Chapter 4
• Updated Table 4-4 sim.do description and simulation directory.
• Updated Fig. 4-37 7 Series FPGAs MIS.
• Updated Table 4-14 User Interface.
• Added #4 note to Table 4-25 7 Series FPGA Memory Solution Configuration Parameters.
• Updated description in app_wdf_mask[APP_MASK_WIDTH - 1:0] section.
• Added Memory Address Mapping description in User Interface section.
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• Vivado Design Suite release only for MIG v2.0. Revision number advanced to 2.0 to align with core version number.
Chapter 1
• Updated ChipScope to Vivado logic analyzer, VIO, and ILA.
• Updated ui_clk and ui_clk_sync_rst descriptions in Table 1-17 User Interface.
• Updated ui_clk and ui_clk_sync_rst descriptions.
• Added Ordering Modes in Reordering section and added modes in Table 1-91.
• Updated ECC enable in AXI4 Slave Interface Block section.
• Updated Read Priority (RD_PRI) section.
• Updated Table 1-19 AXI4 Slave Interface Parameters, C_S_AXI_ADDR_WIDTH value and descriptions.
• Added Write Priority description.
• Updated PHASER_IN DQSFOUND Calibration section.
•Removed Downsizing Option.
• Added DM in DQ descriptions.
• Added Dynamic Calibration and Periodic Read Behavior section.
• Added Vivado Lab Tools section.
• Added AR 54025 for Vivado.
• Updated Debugging PHASER_IN DQSFOUND Calibration Failures
06/19/2013 2.0
(dbg_pi_dqsfound_err = 1) section.
Chapter 2
• Updated ChipScope to Vivado logic analyzer, VIO, and ILA.
• Added Fixed Latency Mode description in Controller Options section.
• Removed qdr_qvld in Table 2-12 Physical Interface Signals.
• Updated Figure 2-26 Four-Word Burst Length Memory Device Protocol.
• Updated Output Architecture section in Write Path.
• Added Write Calibration section.
•Removed QVLD.
• Updated Table 2-20 Write Init Debug Signal Map.
• Updated Tables 2-21 and 2-22 Read Stage 1 and Stage 2 Debug Signal Map tables.
Chapter 3
• Updated ChipScope to Vivado logic analyzer, VIO, and ILA.
• Removed rld_qvld in Table 3-13 Physical Interface Signals.
• Removed QVLD and QVLD_MAP in Table 3-16 RLDRAM II Memory Interface Solution Pinout Parameters.
•Removed QVLD.
• Updated descriptions in Manual Pinout Changes section.
• Added new calibration description in Calibration section.
• Updated Table 3-26 Physical Layer Simple Status Bus Description Defined in the rld_phy_top Module.
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• Updated Table 3-27 DEBUG_PORT Signal with dbg_rd_stage1_rtr_error[N_DATA_LANES - 1:0] and dbg_rd_stage1_error[N_DATA_LANES - 1:0].
• Updated Tables 3-31 and 3-32 Read Stage 1 and Stage 2 Debug Signal Map tables.
• Added Fig. 3-36 Calibration Flow Diagram and Fig. 3-37 Read Level Stage 1.
• Added description to Data Alignment and Valid Generation section.
• Updated description and added Figs. 3-38 to 3-43 in Write Calibration section.
• Added Write Calibration Debug Map section.
Continued
03/20/2013 1.9
Chapter 4
• Updated ChipScope to Vivado logic analyzer, VIO, and ILA.
• Updated ui_clk and ui_clk_sync_rst descriptions in Table 4-14 User Interface.
• Updated ui_clk and ui_clk_sync_rst descriptions.
• Added Ordering Modes in Reordering section and added modes in Table 4-25.
• Added DM in DQ descriptions.
• Added Termination description in LPDDR2 Pinout Examples section.
Chapter 6
• Added Upgrading the ISE/CORE Generator MIG Core in Vivado section.
• ISE 14.5 and Vivado Design Suite 2013.1 releases for MIG v1.9 and v1.9a.
Chapter 1
• Added Memory Part frequency in Controller Options section.
• Added No Buffer option description in FPGA Options section.
• Added pinout description in Verify Pin Changes and Update Design section.
• Updated Fig. 1-15 Setting Memory Mode Options.
• Updated Fig. 1-16 FPGA Options.
• Updated Fig. 1-30 7 Series FPGAs Memory Interface Solution to User’s FPGA Logic
• Added ECC description in AXI4 Slave Interface Block section.
• Updated Table 1-91 7 Series FPGA Memory Solution Configuration Parameters.
• Updated Table 1-92 Embedded 7 Series FPGAs Memory Solution Configuration Parameters.
• Updated Table 1-93 DDR2/DDR3 SDRAM Memory Interface Solution Pinout Parameters.
• Added description in Verifying the Simulation Using the Example Design section.
• Reworked Design Guidelines DDR3 SDRAM section.
• Added new debug section.
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Chapter 2
• Added No Buffer option description in FPGA Options section.
• Added pinout description in Verify Pin Changes and Update Design section.
• Updated Fig. 2-15 FPGA Options.
• Updated REFCLK_FREQ and RST_ACT_LOW in Table 2-13 7 Series FPGAs QDR II+ SRAM Memory Interface Solution Configurable Parameters
• Updated Table 2-14 QDR II+ SRAM Memory Interface Solution Pinout Parameters.
• Added description in Verifying the Simulation Using the Example Design section.
Chapter 3
• Added No Buffer option description in FPGA Options section.
Continued
• Updated Fig. 3-14 FPGA Options.
• Added Verify Pin Changes and Update Design section.
• Updated nCK_PER_CLK in Table 3-10 Traffic Generator Parameters Set in the example_top Module
• Updated Table 3-15 RLDRAM II Memory Interface Solution Configurable Parameters.
• Updated Table 3-16 RLDRAM II Memory Interface Solution Pinout Parameters.
• Added description in Verifying the Simulation Using the Example Design section.
Chapter 4
• Added new LPDDR2 SDRAM section.
Chapter 6
• Updated to new GUIs.
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• ISE 14.4 and Vivado 2012.4 Design Suite releases for MIG v1.8.
Chapter 1
• Updated Table 1-2 to 1-9 with new table note and.v name.
• Updated Fig. 1-16 FPGA Options GUI.
• Added XADC Instantiation bullet.
• Added description to sim.do in Table 1-4.
• Updated Table 1-11 DATA_PATTERN to 0xA.
• Updated Table 1-13 vio_data_mode_value[3:0] to 0xA.
• Updated description in Setting Up for Simulation.
• Added description to EDK Clocking.
• Updated ui_clk and ui_clk_sync_rst in Table 1-17.
• Added description in Internal (FPGA) Logic Clock.
• Added TEMP_MON_CONTROL to Table 1-91.
• Added DATA_IO_IDLE_PWRDWN and CA_MIRROR to Table 1-92.
• Added HP bank description in Bank and Pin Selection Guides for DDR3 Designs.
• Added DDR3 SDRAM interface description to Configuration.
• Added HP bank description in Bank and Pin Selection Guides for DDR2 Designs.
• Added DDR2 SDRAM interface description to Configuration.
12/18/2012 1.8
Chapter 2
• Updated Table 2-2 and 2-7 to 2-8 with new table note and.v name.
• Added description to sim.do in Table 2-3.
• Updated descriptions and added Fig 2-26 to Clocking Architecture.
• Updated description in Write Path Output Architecture.
• Updated descriptions in Trace Length Requirements.
• Added QDRII description in Configuration.
• Added description to Verifying the Simulation Using the Example Design.
• Added Margin Check and Automated Margin Check sections.
Chapter 3
• Updated Table 3-2 and 3-6 to 3-8 with new table note and.v name.
• Added description to sim.do in Table 3-3.
• Updated Table 3-10 DATA_PATTERN to 0xA.
• Updated descriptions and added Fig 3-30 to Clocking Architecture.
• Updated descriptions in Trace Length Requirements.
• Added descriptions in RLDRAM II.
• Added RLDRAM II description in Configuration.
• Added description to Verifying the Simulation Using the Example Design.
• Added Debug section.
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• MIG 1.7 release. Updated ISE Design Suite version to 14.3.
• Chapter 1: Added AXI4-Lite Slave Control/Status Register Interface Block section. Updated figures (1-32 and 1-37) and added PRBS and Temperature Monitor sections. Added CLKIN_PERIOD to USE_DM_PORT parameters in Table 1-37. Updated Table 1-38 PHY0_BITLANES description.
• Chapter 2: Added CLKIN_PERIOD to DIVCLK_DIVIDE parameters in Table 2-13.
10/16/2012 1.7
07/25/2012 1.6
06/13/2012 1.5
• Chapter 3: Added RLDRAM 3 content throughout. Updated/added figures (3-10, 3-13, 3-23 to 3-32, 3-36 to 3-37, 3-40 to 3-41, 3-45 to 3-47, and 3-50). Added mem_ck_lock_complete parameter in Table 3-11. Added CLKOUT0_PHASE parameter in Table 3-15. Updated descriptions in Table 3-16 and added Table 3-28. Updated Table 3-29 user_cmd signal. Updated Table 3-31 and 3-34 descriptions. Added Debugging Write Calibration section.
• Chapter 4: Added System Clock Sharing section
• Chapter 5: Updated figures (5-15, 5-17 to 5-20), updated steps in Getting Started with Vivado – MIG IP Generation
• MIG 1.6 release. Updated ISE Design Suite version to 14.2. Updated GUI screen captures throughout document.
• Chapter 1: Added No Buffer, Use System Clock, and Sample Data Depth in FPGA Options, page 36. Changed the parameters nCK_PER_CLK, tZQI, SYSCLK_TYPE, REFCLK_TYPE, and APP_DATA_WIDTH. Added bulleted item about multiple CK outputs to Bank and Pin Selection Guides for DDR3 Designs, page 186. Updated Trace Lengths, page 191 and Termination, page 200.
• Chapter 2: Added No Buffer, Use System Clock, and Sample Data Depth in FPGA Options, page 282. Changed the parameters SYSCLK_TYPE and REFCLK_TYPE.
• Chapter 3: Added No Buffer, Use System Clock, and Sample Data Depth in FPGA Options, page 282. Changed the parameters SYSCLK_TYPE and REFCLK_TYPE.
• Chapter 6: Added new chapter on migrating to Vivado Design Suite.
Revised the recommended total electrical delay on CK/CK# relative to DQS/DQS# on page 191.
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• MIG 1.5 release. Updated ISE Design Suite version to 14.1. Updated GUI screen captures throughout document. Replaced IODELAYCTRL with IDELAYCTRL throughout.
• Chapter 1: Added I/O Power Reduction option to FPGA Options. Revised I/O standards for sys_rst option in Bank Selection. Added Creating ISE Project Navigator Flow for MIG Example Design, Power-Saving Features, Multi-Purpose Register Read Leveling, OCLKDELAYED Calibration, Upsizing, and External Vref sections. Changed bits [16:15] to from Rank Count to Reserved in the PHY Control word. Revised maximum setting of NUM_DQ_PINS in Table 1-11. Revised Figure 1-55 flowchart. Removed RankSel[1:0] from Figure 1-56 and Figure 1-58. Added mc_odt and mc_cke to Table 1-87. Replaced AXI Addressing. Updated REFCLK_FREQ, RANK_WIDTH, and WRLVL in Table 1-92. Added DATA_IO_PRIM_TYPE to Table 1-93. Added bullet about
04/24/2012 1.4
01/18/2012 1.3
DQS pins to Bank and Pin Selection Guides for DDR3 Designs. Changed DIFF_SSTL_15 to DIFF_SSTL18_II and SSTL15 to SSTL18_II.
• Chapter 2: Changed DIFF_SSTL_15 to DIFF_HSTL_I and SSTL15 to HSTL_I. Revised I/O standards for sys_rst option in System Pins Selection. Revised the PHY_BITLANE parameters in Table 2-11. Added System Clock, PLL Location, and Constraints and Configuration sections.
• Chapter 3: Changed DIFF_SSTL_15 to DIFF_HSTL_I and SSTL15 to HSTL_I. to Revised I/O standards for sys_rst option in System Pins Selection. Added the Write Calibration, System Clock, PLL Location, and Constraints, and Configuration sections. Revised the PHY_BITLANE parameters in Table 3-15. In Table 3-28, added dbg_wrcal_sel_stg[1:0], dbg_wrcal[63:0], dbg_wrcal_done[2:0], dbg_wrcal_po_first_edge[5:0], dbg_wrcal_po_second_edge[5:0], and dbg_wrcal_po_final[5:0].
• MIG 1.4 release. Updated ISE Design Suite version to 13.4. Updated GUI screen captures throughout document.
• Chapter 1: Added support for DDR2 SDRAM. Added option 3 to MIG Output Options. Added EDK Clocking. Added Replaced Figure 1-41 and Figure 1-69.
• Chapter 2: Removed Input Clock Period option from Controller Options. Added Memory Options. Added Reference Clock option to FPGA Options. Updated Debug Signals.
• Chapter 3: Removed Input Clock Period option from Controller Options. Added Input Clock Period option to Memory Options. Added Reference Clock option to FPGA Options. Added Debugging RLDRAM II and RLDRAM 3 Designs.
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• MIG 1.3 release. Updated ISE Design Suite version to 13.3.
• Chapter 1: Added step 2 to MIG Output Options, page 26. Added note about optional use of the memory controller to Controller Options, page 30. Added arbitration scheme to AXI Parameter Options, page 33. Added description of DCI Cascade under Figure 1-23. Updated text about devices with SSI technology and SLRs on page 41 and page 187. Changed error to tg_compare_error on page 42. Replaced Table 1-8. Added qdr_wr_cmd_o, vio_fixed_instr_value, vio_fixed_bl_value, vio_pause_traffic, and vio_data_mask_gen signals to Table 1-13. Added signals to the User Interface in Figure 1-49 and Figure 1-51. Added app_sr_req, app_sr_active, app_ref_req, app_ref_ack, app_zq_req, and app_zq_ack signals to Table 1-17. Added app_wdf_rdy, app_ref_req, app_ref_ack, app_zq_req, app_zq_ack, Read Priority with Starve Limit (RD_PRI_REG_STARVE_LIMIT), Native Interface Maintenance Command Signals, User Refresh, and User ZQ sections. Added C_RD_WR_ARB_ALGORITHM to Table 1-19. Updated fields in Table 1-84, changed Hi Index (Rank) to Rank Count, and added CAS slot field. Updated AXI Addressing and Physical Layer Interface (Non-Memory Controller Design). Added Figure 1-75 through Figure 1-77 in Write Path. In Table 1-92, removed DISABLED option from RTT_NOM for DDR3_SDRAM, changed RTT_NOM to RTT_WR in RTT_WR, updated SIM_BYPASS_INIT_CAL, and updated table note 2. In Table 1-93, updated tZQI and added USER_REFRESH. Added Table 1-94. In Configuration, updated constraints example and removed paragraph
10/19/2011 1.2
about SCL and SDA.
• Chapter 2: Added step 2 to MIG Output Options, page 275. Added Input Clock Period description in Controller Options, page 279. Added Debug Signals Control and Internal Vref Selection options to FPGA Options, page 282. Added I/O Planning Options, page 285. In System Pins Selection, page 288, changed cal_done signal to init_calib_complete and error signal to tg_compare_error. Replaced Table 2-2. Changed file names in Table 2-5. Updated signal names in Figure 2-38, Figure 2-39, and Figure 2-40. Updated signal names in Table 2-7. Added CPT_CLK_CQ_ONLY and updated value for SIM_BYPASS_INIT_CAL in Table 2-10. Added Table 2-11. Updated pinout rules in Pinout Requirements, page 337. Added paragraph about DCI and IN_TERM after Table 2-12. Added Debugging QDR II+ SRAM Designs, page 340.
• Chapter 3: Added step 2 to MIG Output Options, page 375. Added Input Clock Period description in Controller Options. Added Debug Signals Control and Internal Vref Selection options to FPGA Options, page 382. In System Pins Selection, changed cal_done signal to init_calib_complete and error signal to tg_compare_error. Changed file names in Table 3-6. Removed Table 3-12, which contained Reserved signals not used. Added rst_phaser_ref to Table 3-11. Removed PHY-Only Interface section. In Table 3-14, added RLD_ADDR_WIDTH, MEM_TYPE, CLKIN_PERIOD, and SIMULATION, and renamed CLKFBOUT_MULT, CLKOUT0_DIVIDE, CLKOUT1_DIVIDE, CLKOUT2_DIVIDE, and CLKOUT3_DIVIDE. Updated Table 3-15. Added paragraph about DCI and IN_TERM after Table 3-24.
• Added Chapter 5, Multicontroller Design.
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Date Version Revision
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• MIG 1.2 release. Updated ISE Design Suite version to 13.2. Updated GUI screen captures throughout document.
• Chapter 1: Added Verify Pin Changes and Update Design, Simulating the Example Design (for Designs with the AXI4 Interface), Error Correcting Code, and DDR3 Pinout Examples sections. Added paragraph about SLRs to Pin Compatible FPGAs, page 27. Added Input Clock Period and PHY to Controller bullets in Controller Options, page 30. To Setting DDR3 Memory Parameter Option, page 35, indicated that DDR3 SDRAM supports burst lengths of 8. Added Internal Termination for High Range Banks option under Figure 1-23. Added bulleted item about Pin/Bank selection mode on page 39. Added notes about chip select and data mask options on page 74. Added app_correct_en_i to Table 1-17. Added three command types to Command Path,
06/22/2011 1.1
03/01/2011 1.0 Initial Xilinx release.
page 134. Added phy_mc_ctl_full, phy_mc_cmd_full, and phy_mc_data_full signals to Table 1-87. Added paragraph about FIFOs at the end of Physical Layer Interface (Non-Memory Controller Design), page 168. Updated the description and options for DATA_BUF_ADDR_WIDTH in Table 1-93. Added bullet about SLRs to Bank and Pin Selection Guides for DDR3 Designs, page 186. Added LVCMOS15 and DIFF_SSTL15 I/O standards to Configuration, page 194. Changed resistor values in Figure 1-88, Figure 1-89, and Figure 1-90. Changed resistor values in FPGA DCI or IN_TERM column in Table 1-95.
• Chapter 2: Added the Verify Pin Changes and Update Design and Output Path sections. Revised latency mode description on page 280. Added bulleted item about Pin/Bank selection mode on page 285. Added Internal Termination for High Range Banks option under Figure 2-22. Updated Implementation Details, page 324.
• Chapter 3: Added new chapter on RLDRAM II.
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Table of Contents

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Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Using MIG in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Synplify Pro Black Box Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Core Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Designing with the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Interfacing to the Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Customizing the Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Design Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Debugging DDR3/DDR2 Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Chapter 2: QDR II+ Memory Interface Solution
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Using MIG in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Core Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Customizing the Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Design Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Debugging QDR II+ SRAM Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
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Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
Using MIG in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
Core Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
Customizing the Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
Design Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
Debugging RLDRAM II and RLDRAM 3 Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
Using MIG in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
Core Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
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Designing with the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
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Interfacing to the Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
Customizing the Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
Design Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
Chapter 5: Multicontroller Design
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644
Using MIG in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
Chapter 6: Upgrading the ISE/CORE Generator MIG Core in Vivado
Appendix A: General Memory Routing Guidelines
Appendix B: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678
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DDR3 and DDR2 SDRAM Memory
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Interface Solution

Introduction

The Xilinx® 7 series FPGAs Memory Interface Solutions (MIS) core is a combined pre-engineered controller and physical layer (PHY) for interfacing 7 series FPGA user designs and AMBA DDR2 SDRAM devices. This user guide provides information about using, customizing, and simulating a LogiCORE™ IP DDR3 or DDR2 SDRAM interface core for 7 series FPGAs. The user guide describes the core architecture and provides details on customizing and interfacing to the core.
®
Advanced eXtensible Interface (AXI4) slave interfaces to DDR3 and
Chapter 1
IMPORTANT: Memory Interface Solutions v4.1 only supports the Vivado
Design Suite is not supported in this version.
®
Design Suite. The ISE®

Features

Enhancements to the Xilinx 7 series FPGA memory interface solutions from earlier memory interface solution device families include:
• Higher performance.
• New hardware blocks used in the physical layer: PHASER_IN and PHASER_OUT, PHY control block, and I/O FIFOs (see Core Architecture, page 90).
• Pinout rules changed due to the hardware blocks (see Design Guidelines, page 192).
• Controller and user interface operate at 1/4 the memory clock frequency.
For a full list of supported features, see the Zynq-7000 AP SoC and 7 Series FPGAs Memory Interface Solutions Data Sheet (DS176) [Ref 1].
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X-Ref Target - Figure 1-1
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Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution

Using MIG in the Vivado Design Suite

This section provides the steps to generate the Memory Interface Generator (MIG) IP core using the Vivado Design Suite and run implementation.
1. Start the Vivado Design Suite (see Figure 1-1).
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Figure 1-1: Vivado Design Suite
2. To create a new project, click the Create New Project option shown in Figure 1-1 to open the page as shown in Figure 1-2.
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X-Ref Target - Figure 1-2
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Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Figure 1-2: Create a New Vivado Tool Project
3. Click Next to proceed to the Project Name page (Figure 1-3). Enter the Project Name and Project Location. Based on the details provided, the project is saved in the directory.
X-Ref Target - Figure 1-3
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Figure 1-3: Project Name
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Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
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4. Click Next to proceed to the Project Type page (Figure 1-4). Select the Project Type as RTL Project because MIG deliverables are RTL files.
X-Ref Target - Figure 1-4
Figure 1-4: Project Type
5. Click Next to proceed to the Add Sources page (Figure 1-5). RTL files can be added to the project in this page. If the project was not created earlier, proceed to the next page.
X-Ref Target - Figure 1-5
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Figure 1-5: Add Sources
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Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
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6. Click Next to open the Add Existing IP (Optional) page (Figure 1-6). If the IP is already created, the XCI file generated by the IP can be added to the project and the previous created IP files are automatically added to the project. If the IP was not created earlier, proceed to the next page.
X-Ref Target - Figure 1-6
Figure 1-6: Add Existing IP (Optional)
7. Click Next to open the Add Constraints (Optional) page (Figure 1-7). If the constraints file exists in the repository, it can be added to the project. Proceed to the next page if the constraints file does not exist.
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X-Ref Target - Figure 1-7
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Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Figure 1-7: Add Constraints (Optional)
8. Click Next to proceed to the Default Part page (Figure 1-8) where the device that needs to be targeted can be selected. The Default Part page appears as shown in
Figure 1-8.
X-Ref Target - Figure 1-8
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Figure 1-8: Default Part (Default Window)
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Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
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Select the target Family, Package, and Speed Grade. The valid devices are displayed in the same page, and the device can be selected based on the targeted device (Figure 1-9).
X-Ref Target - Figure 1-9
Figure 1-9: Default Part (Customized Window)
Apart from selecting the parts by using Parts option, parts can be selected by choosing the Boards option, which brings up the evaluation boards supported by Xilinx (Figure 1-10). With this option, design can be targeted for the various evaluation boards. If the XCI file of an existing IP was selected in an earlier step, the same part should be selected here.
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X-Ref Target - Figure 1-10
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Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Figure 1-10: Default Part Boards Option
9. Click Next to open the New Project Summary page (Figure 1-11). This includes the summary of selected project details.
X-Ref Target - Figure 1-11
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Figure 1-11: New Project Summary
10. Click Finish to complete the project creation.
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X-Ref Target - Figure 1-12
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Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
11. Click IP Catalog on the Project Manager window to open the IP catalog window. The Vivado IP catalog window appears on the right side panel (see Figure 1-12, highlighted in a red circle).
12. The MIG tool exists in the Memories & Storage Elements > Memory Interface Generators section of the IP catalog window (Figure 1-12) or you can search from the Search tool bar for the string “MIG.”
Figure 1-12: IP Catalog Window – Memory Interface Generator
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Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
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13. Select MIG 7 Series to open the MIG tool (Figure 1-13).
X-Ref Target - Figure 1-13
Figure 1-13: 7 Series FPGAs Memory Interface Generator FPGA Front Page
14. Click Next to display the Output Options page.

Customizing and Generating the Core

CAUTION! The Windows operating system has a 260-character limit for path lengths, which can affect
the Vivado tools. To avoid this issue, use the shortest possible names and directory locations when creating projects, defining IP or managed IP projects, and creating block designs.
MIG Output Options
1. Select the Create Design to create a new Memory Controller design. Enter a component name in the Component Name field (Figure 1-14).
2. Choose the number of controllers to be generated. This option determines the replication of further pages.
3. DDR2 and DDR3 SDRAM designs support the memory-mapped AXI4 interface. The AXI4 interface is implemented in Verilog only. If an AXI4 interface is required, select the language as “Verilog” in the Vivado Design Suite before invoking the MIG tool. If the AXI4 interface is not selected, the user interface (UI) is the primary interface.
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X-Ref Target - Figure 1-14
UG586_c1_09_120311
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Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Figure 1-14: MIG Output Options
MIG outputs are generated with the folder name <component name>.
IMPORTANT: Only alphanumeric characters can be used for <component name>. Special characters
cannot be used. This name should always start with an alphabetical character and can end with an alphanumeric character.
When invoked from Xilinx Platform Studio (XPS), the component name is corrected to be the IP instance name from XPS.
4. Click Next to display the Pin Compatible FPGAs page.
Pin Compatible FPGAs
The Pin Compatible FPGAs page lists FPGAs in the selected family having the same package. If the generated pinout from the MIG tool needs to be compatible with any of these other FPGAs, this option should be used to select the FPGAs with which the pinout has to be compatible (Figure 1-15).
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