Xilinx ZCU111 User Manual
ZCU111 Evaluation Board
User Guide
UG1271 (v1.1) August 6, 2018
Revision History
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The following table shows the revision history for this document.
Section Revision Summary
8/06/2018 Version 1.1
RF Data Converter Clocking Removed RF Clocking Overview figure.
Figure 3-18 Added capacitor option.
Table 3-18 and Tab le 3- 19 Added optional RFMC and SYSREF capacitor options.
SFP28 Module Connectors
Added note and reference to SNIA Technology
Affiliates website.
06/28/2018 Version 1.0
Initial Xilinx release.
ZCU111 Board User Guide 2
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Table of Contents
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Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 1: Introduction
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Board Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Board Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Environmental . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Operating Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Chapter 2: Board Setup and Configuration
Board Component Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Default Jumper and Switch Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
RFSoC Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Quad SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
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Chapter 3: Board Component Descriptions
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Component Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Zynq UltraScale+ XCZU28DR RFSoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Encryption Key Battery Backup Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
PS-Side: DDR4 SODIMM Socket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
PL-Side: DDR4 Component Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
PSMIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Quad SPI Flash Memory (MIO 0–12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
GPIO (MIO 13, 38) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
I2C0 (MIO 14-15), I2C1 (MIO 16-17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
I2C0 (MIO 14-15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
I2C1 (MIO 16-17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
UART0 (MIO 18-19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
UART1 (MIO 20-21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
GPIO (MIO 22-23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
CAN1 (MIO 24-25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
PMU GPI (MIO 26) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
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DPAUX (MIO 27-30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
PMU GPO (MIO 32-37) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
SD Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
USB 3.0 Transceiver and USB 2.0 ULPI PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
GEM3 Ethernet (MIO 64-77) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
10/100/1000 MHz Tri-Speed Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Programmable Logic JTAG Programming Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
RF Data Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
RF Data Converter Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
RF RFMC Plug-in Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
SFP28 Module Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
User PMOD GPIO Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
User I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Power and Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
GTY Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PS-Side: GTR Transceivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
PS M.2 SATA Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
FPGA Mezzanine Card Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Cooling Fan Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
VADJ_FMC Power Rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
ZCU111 System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Board Power System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Monitoring Voltage and Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
. . . . . . . . . . . . . . . . . . .71
Appendix A: VITA 57.4 FMCP Connector Pinouts
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Appendix B: Xilinx Design Constraints
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Appendix C: Regulatory and Compliance Information
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
CE Directives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
CE Standards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Appendix D: HW-FMC-XM500
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
AMS RFMC Plug-in Card Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
XM500 Card Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
ADC/DAC Bank Data and Clock Channel Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
XM500 ADC/DAC Data and Clock SMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
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Appendix E: Additional Resources and Legal Notices
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Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
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Introduction
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Overview
The ZCU111 evaluation board features the Zynq® UltraScale+™ RFSoC ZCU28DR device.
This board enables the evaluation of the integrated RF-DAC and RF-ADC functionality, soft
decision forward error correction (SDFEC), and FPGA fabric and RFSoC features, such as the
quad core Arm® Cortex™-A53 processing system (PS) and the dual-core Arm Cortex-R5
real-time processors. The ZCU111 evaluation board is equipped with many of the common
board-level features needed for design development, such as DDR4 memory, networking
interfaces, FMC+ expansion port, and access to the new RF-FMC interface.
The Z C U111 eva luation b oard kit i ncludes a n out-of - the-box FMC XM500 balun transformer
add-on card to support signal analysis and loopback evaluation. This card includes
on-board high-frequency and low frequency baluns and SMAs for custom baluns and
filtering. For more information on this card, see Appendix D, HW-FMC-XM500.
Chapter 1
Additional Resources
See Appendix E, Additional Resources and Legal Notices for references to documents, files,
and resources relevant to the ZCU111 evaluation board.
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X-Ref Target - Figure 1-1
RFMC_ADC[06:07]
RFMC_ADC[00:01]
RFMC_ADC[04:05]
RFMC_ADC[02:03]
X21110-062118
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Chapter 1: Introduction
Block Diagram
The ZCU111 board block diagram is shown in Figure 1-1.
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Figure 1-1: ZCU111 Evaluation Board Block Diagram
Board Features
The ZCU111 evaluation board features are listed here. Detailed information for each feature
is provided in Board Component Descriptions in Chapter 3.
• XCZU28DR-2E, FFVG1517 package
• Form factor: rectangular 11.811 in. x 7.874 in. x 0.1 in.
• Configuration from:
Dual Quad SPI
°
Micro SD card
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°
USB-to-JTAG bridge
°
•Clocks
GTR_REF_CLK_DP 27 MHz
°
GTR_REF_CLK_USB3 26 MHz
°
GTR_REF_CLK_SATA 125 MHz
°
CLK_100 100 MHz
°
CLK_125 125 MHz
°
PS_REF_CLK 33.33 MHz
°
USER_MGT_SI570 (default 156.25 MHz)
°
USER_SI570 (default 300 MHz)
°
• PS DDR4 4 GB 64-bit SODIMM
• PL DDR4 4 GB 64-bit component (4x16-bit)
Chapter 1: Introduction
• PS GTR (bank 505) assignment
DisplayPort 1.2 transmit only (two GTR)
°
USB3 (one GTR)
°
SATA with M2 connector (one GTR)
°
• PL GTY assignment (16 total)
SFP28 (four, bank GTY128)
°
FMCP HSCP DP (four, bank GTY129)
°
FMCP HSCP DP (four, bank GTY130)
°
FMCP HSCP DP (four, bank GTY131)
°
• PL FMCP HSCP (FMC+) connectivity - full LA[00:33] bus
• PS MIO connectivity
PS MIO[0:5, 7:12]: dual Quad SPI flash memory
°
PS MIO[13]: PS_GPIO2
°
PS MIO[14:17]: two channels of I2C
°
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PS MIO[18:19]: UART (one of three FT4232 UART channels)
°
PS MIO[22:23]: PS_PB, PS_LED I/F
°
PS MIO[26]: platform management unit (PMU)
°
PS MIO[27:30]: DisplayPort control
°
PS MIO[32:37]: PMU_GPIO[0:5]
Send Feedback
°
PS MIO[38]: PS_GPIO1
°
PS MIO[44:51]: SD I/F
°
PS MIO[52:63]: USB3.0
°
PS MIO[64:77]: GEM3 Ethernet
°
• PL I/O connections:
PL-side user DIP switch (8-position)
°
PL-side CPU reset pushbutton
°
PL-side user LEDs (eight)
°
PL-side user pushbuttons (five, geographic N, S, E, W, C)
°
PL-side PMOD0/1 (two R.A. 2x6 receptacles)
°
• Security - PSBATT button battery backup
•SYSMON header
Chapter 1: Introduction
• Operational switches (power on/off, PROG_B, boot mode DIP switch)
• Operational status LEDs (INIT, DONE, PS STATUS, PGOOD)
• Power management
• System controller (MSP430)
The ZCU111 provides a rapid prototyping platform using the XCZU28DR-2EFFVG1517
device. See the Zynq UltraScale+ RFSoC Data Sheet: Overview (DS889) [Ref 1] for a feature
set overview, description, and ordering information.
Board Specifications
Dimensions
Height: 11.811 inches (30.0 cm)
Width: 7.874 inches (20.0 cm)
Thickness: 100.8 mil (0.2743 cm)
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Note:
A 3D model of this board is not available.
See ZCU111 board documentation for the XDC listing and board schematics.
Environmental
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Temperature
Operating: 0°C to +45°C
Storage: -25°C to +60°C
Humidity
10% to 90% non-condensing
Operating Voltage
Chapter 1: Introduction
+12 V
DC
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Board Setup and Configuration
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Board Component Location
Figure 2-1 shows the ZCU111 board component locations. Each numbered component
shown in the figure is keyed to Tab l e 2- 1. Ta ble 2 -1 identifies the components, references
the respective schematic (0381811) page numbers, and links to a detailed functional
description of the components and board features in Chapter 3.
IMPORTANT: Figure 2-1 is for visual reference only and might not reflect the current revision of the
board.
IMPORTANT: There could be multiple revisions of this board. The specific details concerning the
differences between revisions are not captured in this document. This document is not intended to be
a reference design guide and the information herein should not be used as such. Always refer to the
schematic, layout, and XDC files of the specific ZCU111 version of interest for such details.
Chapter 2
CAUTION! The ZCU111 board can be damaged by electrostatic discharge (ESD). Follow standard ESD
prevention measures when handling the board.
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X-Ref Target - Figure 2-1
1
00
Round callout references a component
on the front side of the board
Square callout references a component
on the back side of the board
00
26
41
28
15
43
20
19
27
18
52
42
60
40
62
61
1
57
26
41
28
13
15
43
20
19
27
32
18
52
42
60
40
63
30
12
62
61
16
22
7
6
24
25
17
17
35
29 5
37
55
53
36
54
56
23
2
4
8
51
49
14
45
50
34
3
14
31
58
33
38
39
21
9
10
59
28
11
44
X20477-06211
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Chapter 2: Board Setup and Configuration
ZCU111 Board User Guide 12
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Figure 2-1: ZCU111 Evaluation Board Components
Table 2-1: Board Component Locations
Send Feedback
Chapter 2: Board Setup and Configuration
Callout Ref. Des. Feature [B] = Bottom Notes
1U1
2J50
3 U80, U94-U96 PL-Side: DDR4 Component Memory Micron MT40A512M16JY-075E 72-75
4 U17, U18 Quad SPI Flash Memory (MIO 0–12) Micron MT25QU02CBB8E-0SIT 25
5 U12, J96
6 J100 SD Card Interface MOLEX 5025700893 28
7 U34, J83 UART0 (MIO 18-19)
8U46
9U47Programmable User SI570 Clock Silicon Labs SI570BAB001614DG 45
10 U49
Zy nq U ltra Sca le+ XCZU 28DR RFS oC
fansink
PS-Side: DDR4 SODIMM Socket,
w/64-bit DDR4 SODIMM
USB 3.0 Transceiver and USB 2.0
ULPI PHY [B]
SI5341B 10 Independent Output
Any-Frequency Clock Generator
Programmable User MGT SI570
Clock, user MGT clock,
156.250 MHz, 3.3V LVDS
XCZU28DR-2FFVG1517
COFAN 30-4988-10
LOTES ADDR0067-P001A
with MICRON
MTA4ATF51264HZ-2G6E1
SMSC USB3320-EZK,
WURTH 692122030100
FTDI FT4232Hx-REEL,
Hirose ZX62D-AB-5P8
Silicon Labs SI5341B-D07833-GM 40
Silicon Labs SI570BAB000544DG 45
Schematic
Page
43
24
29
11 U48 SI5382A SFP28 Clock Recovery [B] Silicon Labs SI5382B-C-GMR 39
12 U37, P12
13 U22, U23 I2C0 (MIO 14-15), expander
14 U26, U27 I2C1 (MIO 16-17) [B] Two each TI TCA9548APWR 27
15
16 U42 ZCU111 System Controller TI MSP430F5342 32
17 J48, J49
18 DS11-DS18
19 SW9-SW13
20 SW14
21 SW20
22 SW8 System controller 5-pole C&K SDA05H1SBD 32
J27, J32, J37,
J42
10/100/1000 MHz Tri-Speed
Ethernet PHY, RJ45 with mag
SFP28 Module Connectors Molex 170382-0001 38
User PMOD GPIO Connectors,
PMOD0/1 RA receptacles
User I/O, eight user LEDs, active
High
User I/O, user pushbutton switches,
active High
User I/O, user 8-pole DIP switch,
active High
User I/O, CPU_RESET pushbutton,
active High
TI DP83867IRPAP,
Wurth 7499111221A
TI TCA6416APWR,
TI PCA9544ARGYR
SULLINS PPPC062LJBN-RC 42
GPIO LEDs, GREEN 0603 41
E-Switch TL3301EP100QG
(N,S,W,E,C pattern)
C&K SDA08H1SBD 41
E-switch TL3301EP100QG 41
30
26
41
23 SW3, SW4
ZCU111 Board User Guide 13
UG1271 (v1.1) August 6, 2018 www.xilinx.com
Switches, PS_SRST_B, PS_POR_B
pushbuttons
E-switch TL3301EP100QG 12
Table 2-1: Board Component Locations (Cont’d)
Send Feedback
Chapter 2: Board Setup and Configuration
Callout Ref. Des. Feature [B] = Bottom Notes
24 SW16
25 J52
26 SW2
27 J26
28 - Board Power System, (top, [B]) Infineon regulators 47-61
29 P11 DPAUX (MIO 27-30), DisplayPort MOLEX 0472720001 22-23
30 J19
31 J92
32 SW6
33 J5
Power On/Off Slide Switch, power
ON/OFF slide switch
Power On/Off Slide Switch, power
connector
Program_B Pushbutton, PS_PROG
pushbutton
FPGA Mezzanine Card Interface,
FMCP HSPC connector
Monitoring Voltage and Current,
PMBUS connector
System controller, MSP430 SC
emulation cable connector
RFSoC Device Configuration, FPGA
MODE 4-pole DIP switch
SYSMON 2X6 vertical male pin
header
C&K 1201M2S3AQE2 46
MOLEX 39-30-1060 46
E-switch TL3301EP100QG 12
Samtec ASP_184329_01 33-37
SULLINS PBC36SAAN 26
TYCO 5103308-2 32
4-pole C&K SDA04H1SBD 12
SULLINS PBC36DAAN 3
Schematic
Page
34 J47
35 J94
36 U40 PS M.2 SATA Connector Amphenol MDT420M02001 31
37 M2CAGE1
38 U52
39 J60
40 J14
41 J15
42 J95
43 J108
44 J109
RF Data Converters, low profile
array (LPAF) socket
RF Data Converters, low profile
array (LPAF) socket
PS M.2 SATA Connector, M.2 conn.
EMI cage
Cooling Fan Connector, fan
controller
Cooling Fan Connector, fan
controller
User SMA MGT Clock, SMA
USER_SMA_MGT_CLOCK_P
User SMA MGT Clock, SMA
USER_SMA_MGT_CLOCK_N
User SMA MGT Clock, SMA
RF_FPGA_REF_CLK
RF clocking, U90 LMK04208 RF
REFCLK SMA
RF clocking, U90 LMK04208 RF
external REFCLK SMA
Samtec
Samtec
Leader Tech
20S-CBSFNSV-1.0x2.25x0.40
Maxim MAX6643LBBAEE++ 46
Molex 22-11-2032 46
Rosenberger 32K10K-400L5 8
Rosenberger 32K10K-400L5 8
Rosenberger 32K10K-400L5 4
Rosenberger 32K10K-400L5 67
Rosenberger 32K10K-400L5 67
LPAF-40-03.0-S-08-2-K-TR 63
LPAF-40-03.0-S-08-2-K-TR 64
31
45 U90 RF clocking, LMK04208 RF REFCLK T I L M K 04208 67
ZCU111 Board User Guide 14
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Table 2-1: Board Component Locations (Cont’d)
Send Feedback
Chapter 2: Board Setup and Configuration
Callout Ref. Des. Feature [B] = Bottom Notes
49 U102 RF clocking, ADC RFPLL TI LMX2594RHAT 68
50 U103 RF clocking, DAC RFPLL TI LMX2594RHAT 69
51 U104 RF clocking, ADC RFPLL TI LMX2594RHAT 70
52 U6
53 U13
54 J20
55 J8
56 J9
57 U53
58 U55
59 U57
System Reset Pushbuttons,
power-on reset
USB 3.0 Transceiver and USB 2.0
ULPI PHY, USB3 power switch,
System Reset Pushbuttons,
2-pin HDR PS_POR_B
System Reset Pushbuttons,
2-pin HDR PS_SRST_B
System Reset Pushbuttons, 2-pin
HDR MR_B (U6 MAX16025 POR)
Board Power System,
INFINEON PMIC1
Board Power System,
INFINEON PMIC2
Board Power System,
INFINEON PMIC3
Maxim MAX16025TE+ 12
Micrel MIC2544A-1YM 24
SULLINS PBC36SAAN 12
SULLINS PBC36SAAN 12
SULLINS PBC36SAAN 12
Infineon IRPS5401MXI04TRP 47
Infineon IRPS5401MXI04TRP 49
Infineon IRPS5401MXI04TRP 51
Schematic
Page
60 U83 Power and Status LEDs, LED driver TI SN74AVC8T245PWR 62
61 U84 Power and Status LEDs, LED driver TI SN74AVC8T245PWR 62
62 U85 Power and Status LEDs, LED driver TI SN74AVC8T245PWR 62
63 SW7
PB U42 MSP430 reset,
PB reset (U42 MSP430).
E-switch TL3301EP100QG 32
ZCU111 Board User Guide 15
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X-Ref Target - Figure 2-2
1
2
4
3
8
9
10
11
12
15
14
13
16
18
17
19
20
27 23
25
26
29
32
28
24
21
22
31
7
6
5
30
X20479-062118
Send Feedback
Chapter 2: Board Setup and Configuration
Default Jumper and Switch Settings
Figure 2-2 shows the ZCU111 board jumper header and switch locations. Each numbered
component shown in the figure is keyed to Tab l e 2- 2 (for default jumper settings) or
Tab l e 2- 3 (for default switch settings). Both tables reference the respective schematic page
numbers.
Figure 2-2: Board Jumper Header and Switch Locations
ZCU111 Board User Guide 16
UG1271 (v1.1) August 6, 2018 www.xilinx.com
Jumpers
Send Feedback
Table 2-2: Default Jumper Settings
Chapter 2: Board Setup and Configuration
Callout
Number
1 J85 POR_OVERRIDE 2-3 3
1-2: Enable
2-3: Disable
2 J2 SYSMON I2C address On 3
Off: SYSMON_VP_R floating
On: SYSMON_VP_P pulled down
3 J3 SYSMON I2C Address On 3
Off: SYSMON_VN_R floating
On: SYSMON_VP_N pulled down
4J4SYSMON VREFP 1-2 3
1-2: 1.25V VREFP connected to fpga
2-3: VREFP connected to GND
5 J20 Reset sequencer PS_POR_B On 12
Off: sequencer does not control PS_POR_B
On: sequencer can control PS_POR_B
Ref Des Function Default
Schematic
Page
6 J8 Reset sequencer PS_SRST_B On 12
Off: sequencer does not control PS_SRST_B
On: sequencer can control PS_SRST_B
7 J9 Reset sequencer inhibit Off 12
Off: sequencer normal operation
On: sequencer inhibit (resets will stay asserted)
8 J17 USB 3.0 connector J96 shield connection options 2-3 24
1-2: J96 shield capacitor C171 to GND
2-3: J96 shield directly to GND
9 J18 ULPI USB3320 U12 ULPIO_VBUS_SEL option jumper Off 24
On: Selects U13 MIC2544A switch 5V for VBUS
Off: normal operation, VBUS from J96 USB3.0 conn.
10 J1 SD3.0 U107 IP4856CX25 level-trans. ref. voltage select 1-2 28
1-2: track SD3.0 J100 socket UTIL_3V3 3.3V
2-3: GND = revert to internal voltage reference
11 J23 U93 SC18IS602IPW I2C-to-SPI bridge enable Off 66
On: U93 bridge RESET_B to GND, U93 inhibited
ZCU111 Board User Guide 17
UG1271 (v1.1) August 6, 2018 www.xilinx.com
Table 2-2: Default Jumper Settings (Cont’d)
Send Feedback
Chapter 2: Board Setup and Configuration
Callout
Number
Off: U93 bridge enabled
12 J164 U111 MPS430 RST_B and test pin options 32
1-2: MSP430_RST_B connected to PMOD1_0 Open
2-3: MSP430_TEST connected to PMOD1_1 Open
13 J29 SFP0 J29 enable jumper On 38
On: SFP0 TX_DISABLE = GND = enabled
Off: SFP0 TX_DISABLE = high = disabled
14 J35 SFP1 J35 enable jumper On 38
On: SFP1 TX_DISABLE = GND = enabled
Off: SFP1 TX_DISABLE = high = disabled
15 J40 SFP2 J40 enable jumper On 38
On: SFP2 TX_DISABLE = GND = enabled
Off: SFP2 TX_DISABLE = high = disabled
16 J44 SFP3 J44 enable jumper On 38
On: SFP3 TX_DISABLE = GND = enabled
Ref Des Function Default
Schematic
Page
Off: SFP3 TX_DISABLE = high = disabled
17 J87 USB2ANY cable select jumper Off 66
On: USBANY_SDO connected to I2CSPI_SDO
Off: USBANY_SDO not connected to I2CSPI_SDO
18 J89 ZU28DR RFSoC U1 ADC bank 224 ADC_REXT select Off 9
On: bank 224 ADC_REXT pin AB8 = GND
Off: bank 224 ADC_REXT pin AB8 = 2.49K to GND
19 J90 ZU28DR RFSoC U1 DAC bank 228 DAC_REXT select Off 10
On: bank 228 DAC_REXT pin W8 = GND
Off: bank 228 DAC_REXT pin W8 = 2.49K to GND
20 J101 SPI CS select header 66
1-2:
3-4:
5-6:
7-8:
21 J111 SPI SDO select header 66
1-2:
ZCU111 Board User Guide 18
UG1271 (v1.1) August 6, 2018 www.xilinx.com
3-4:
5-6:
Table 2-2: Default Jumper Settings (Cont’d)
Send Feedback
Chapter 2: Board Setup and Configuration
Callout
Number
7-8:
22 J110 U92 12.8MHz TXCO power On 67
On: U92 is on
Off: U92 is off
Ref Des Function Default
Switches
Table 2-3: Default Switch Settings
Callout
Number
23 SW6 RFSoC U1 Mode 4-Pole DIP Switch 0010 12
Switch OFF = 1 = High; ON = 0 = Low
Mode = SW6[4:1] = Mode[3:0]
JTAG = ON,ON,ON,ON = 0000
QSPI32 = ON,ON,OFF,ON = 0010
SD = OFF,OFF,OFF,ON = 1110
24 SW2 PS_PROG_B pushbutton
25 SW3 PS_POR_B pushbutton
Ref Des Function Default
(1)
(1)
SW4 PS_SRST_B pushbutton
(1)
Schematic
Page
Schematic
Page
12
12
12
26 SW8
27 SW8
28 SW9 GPIO pushbutton (geographic) GPIO_SW_N
SW10 GPIO pushbutton (geographic) GPIO_SW_W
SW11 GPIO pushbutton (geographic) GPIO_SW_C
SW12 GPIO pushbutton (geographic) GPIO_SW_E
SW13 GPIO pushbutton (geographic) GPIO_SW_S
29 SW14
30 SW15 CPU_RESET pushbutton
31 SW16 Main power slide switch off 46
32 SW19 PS MIO22_BUTTON pushbutton
Notes:
1. Pushbutton switch default = open (not pressed).
MSP430 U42 5-Pole GPIO DIP switch
Switch Off = 1 = High; On = 0 = Low
RST_B pushbutton for MSP430 U42/MSP430
EMUL. cable J92
GPIO 8 -Pole D IP sw it ch
Switch Off = 0 = Low; On = 1 = High
11111 32
(1)
(1)
(1)
(1)
(1)
(1)
00000000 41
(1)
(1)
32
41
41
41
41
41
41
11
ZCU111 Board User Guide 19
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Chapter 2: Board Setup and Configuration
Send Feedback
RFSoC Device Configuration
Zynq UltraScale+ XC ZU28 DR-2 E RFS oC de vices use a multi-stage boot process as described
in the “Boot and Configuration” chapter of the Zynq UltraScale+ Device Technical Reference
Manual (UG1085) [Ref 3]. Switch SW6 configuration option settings are listed in Tabl e 2- 4 .
Table 2-4: Switch SW6 Configuration Option Settings
Boot Mode Mode Pins [3:0] Mode SW6 [4:1]
JTAG 0000 ON,ON,ON,ON
QSPI32 0010
SD 1110 OFF,OFF,OFF,ON
Notes:
1. Default switch setting.
JTAG
(1)
ON,ON,OFF,ON
Vivado®, Xilinx SDK, or third-party tools can establish a JTAG connection to the Zynq
UltraScale+ RFSoC device through the FTDI FT4232 USB-to-JTAG/USB UART device (U34)
connected to micro-USB connector (J83).
Quad SPI
To boot from the dual Quad SPI nonvolatile configuration memory:
1. Store a valid Zynq UltraScale+ RFSoC boot image in the Quad SPI flash devices
connected to the MIO Quad SPI interface. See the ZCU111 Restoring Flash Tutorial
XTP515 [Ref 13] for information on programming the QSPI.
2. Set the boot mode pins SW6 [3:0] PS_MODE[3:0] as indicated in Ta b le 2 - 4 for Quad
SPI32.
3. Either power-cycle or press the power-on reset (POR) pushbutton. SW6 is callout 46 in
Figure 2-1.
SD
To boot from an SD card:
ZCU111 Board User Guide 20
UG1271 (v1.1) August 6, 2018 www.xilinx.com
1. Store a valid Zynq UltraScale+ RFSoC boot image file on to an SD card (and then plug
the SD card into ZCU111 board socket J100).
2. Set the boot mode pins SW6 [3:0] PS_MODE[3:0] as indicated in Ta b le 2 - 4 for SD.
3. Either power-cycle or press the power-on reset (POR) pushbutton. SW6 is callout 46 in
Figure 2-1.
Chapter 2: Board Setup and Configuration
Send Feedback
See the Zynq UltraScale+ Device Technical Reference Manual (UG1085) [Ref 3] for more
information about Zynq UltraScale+ RFSoC configuration options.
ZCU111 Board User Guide 21
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Board Component Descriptions
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Overview
This chapter provides a detailed functional description of the board’s components and
features. Tab le 2-1 , pa ge 13 identifies the components, references the respective schematic
page numbers, and links to the corresponding detailed functional description in this
chapter. Component locations are shown in Figure 2-1, page 12.
Component Descriptions
Chapter 3
Zynq UltraScale+ XCZU28DR RFSoC
[Figure 2-1, callout 1]
The ZCU111 board is populated with the Zynq UltraScale+ XCZU28DR-2FFVG1517 RFSoC,
which combines a powerful processing system (PS) and programmable logic (PL) in the
same device. The PS in a Zynq UltraScale+ RFSoC features the Arm
64-bit quad-core processor and Cortex-R5 dual-core real-time processor.
For additional information on the Zynq UltraScale+ XCZU28DR-2FFVG1517 RFSoC, see the
Zynq UltraScale+ RFSoC Data Sheet (DS926) [Ref 2]. See the Zynq UltraScale+ Device
Technical Reference Manual (UG1085) [Ref 3] for more information about Zynq UltraScale+
RFSoC configuration options.
®
flagship Cortex®-A53
ZCU111 Board User Guide 22
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Chapter 3: Board Component Descriptions
X20480-062118
Send Feedback
Encryption Key Battery Backup Circuit
The XCZU28DR RFSoC U1 implements bitstream encryption key technology. The ZCU111
board provides the encryption key backup battery circuit shown in Figure 3-1.
X-Ref Target - Figure 3-1
ZCU111 Board User Guide 23
UG1271 (v1.1) August 6, 2018 www.xilinx.com
Figure 3-1: Encryption Key Backup Circuit
The Seiko TS518FE rechargeable 1.5V lithium button-type battery B1 is soldered to the
board with the positive output connected to the XCZU28DR-2E RFSoC U1 V
Y23. The battery supply current I
specification is 150 nA maximum when board power is
BATT
CC_PSBATT
pin
off. B1 is charged from the UTIL_1V8 1.8V rail through a series diode with a typical forward
voltage drop of 0.38V and 4.7 ΩK current limit resistor. The nominal charging voltage is
1.42V.
Chapter 3: Board Component Descriptions
Send Feedback
I/O Voltage Rails
The XCZU28DR RFSoC PL I/O bank voltages on the ZCU111 board are listed in Tabl e 3-1 .
Table 3-1: I/O Voltage Rails
XCZU28DR
PL bank 64 VCC1V8 1.8V GPIO
PL bank 65 VADJ_FMC
PL bank 66 VADJ_FMC
PL bank 67 VCC1V2 1.2V PL_DDR4_DQ[32:63]
PL bank 68 VCCIV2 1.2V PL_DDR4_DQ[0:31], SFPx_TX_DISABLE, SYSMON_SDA/SCL
PL bank 69 VCC1V2 1.2V PL_DDR4 ADDR/CTRL, PMOD0&1[0:7],MSP430_GPIO[0:3]
PL bank 84 VCC1V8 1.8V ADCIO[0:19], GPIO_SW[N,E,C,W]
PL bank 87 VCC1V8 1.8V DACIO[0:19], GPIO_SW[S], SFP_SI5382_CLK_IN_SEL
PS bank 500 VCC1V8 1.8V QSPI LWR/UPR, PS_GPIO2, I2Cx_SDA/SCL, UART0_RXD/TXD
PS bank 501 VCC1V8 1.8V DP CTRL, PMU_GPO[0:5], SDIO I/F, PS_GPIO1
PS bank 502 VCC1V8 1.8V USB I/F, ENET I/F
PS bank 503 VCC1V8 1.8V PS CONFIG I/F
PS bank 504 VCC1V2 1.2V PS_DDR4 64-BIT SODIMM I/F
Notes:
1. The ZCU111 board is shipped with VADJ_FMC set to 1.8V by the MSP430 system controller.
Power Net
Name
(1)
(1)
Voltage Connected To
1.8V FMCP_HSPC LA BUS [0:16]
1.8V FMCP_HSPC LA BUS [17:32]
PS-Side: DDR4 SODIMM Socket
[Figure 2-1, callout 2]
The PS-side memory is wired to the Zynq UltraScale+ DDRC bank 504 hard memory
controller. A 64-bit single rank DDR4 SODIMM is inserted into socket J50. The ZCU111
board is shipped with a DDR4 SODIMM installed:
• Manufacturer: Micron
• Part Number: MTA4ATF51264HZ-2G6E1
•Description:
4 GByte 260-pin DDR4 SODIMM
°
Single rank x16
°
512 Mbit x 64-bit
°
Supports 1333 MT/s – 2666 MT/s
°
ZCU111 Board User Guide 24
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Chapter 3: Board Component Descriptions
Send Feedback
The ZCU111 XCZU28DR RFSoC PS DDR interface maximum 2133 MT/s performance is
documented in the Zynq UltraScale+ RFSoC Data Sheet (DS926)[Ref 2].
The ZCU111 DDR4 SODIMM interface adheres to the constraints guidelines documented in
the PCB guidelines for DDR4 section of the UltraScale Architecture PCB Design User Guide
(UG583) [Ref 4]. The DDR4 SODIMM interface is a 40Ω impedance implementation. Other
memory interface details are also available in the UltraScale Architecture-Based FPGAs
Memory IP LogiCORE IP Product Guide (PG150) [Ref 5]. For more details, see the Micron
MTA4ATF51264HZ-2G6E1 data sheet at the Micron website [Ref 15].
The connections between the DDR4 SODIMM socket J50 and XCZU28DR PS bank 504 are
referenced in Appendix B, Xilinx Design Constraints.
PL-Side: DDR4 Component Memory
[Figure 2-1, callout 3]
The 4 GB, 64-bit wide DDR4 memory system is comprised of four 512 Mb x 16 SDRAM, U80
and U94-U96.
• Manufacturer: Micron
• Part Number: MT40A512M16JY-075E
• Description:
8 Gb (512 Mb x 16)
°
1.2V 96-ball TFBGA
°
DDR4-2666
°
This memory system is connected to PL-side XCZU28DR banks 67, 68, and 69. The DDR4
0.6V VTT termination voltage is supplied from sink-source regulator U81.
The ZCU111 board DDR4 64-bit component memory interface adheres to the constraints
guidelines documented in the PCB guidelines for DDR4 section of UltraScale Architecture
PCB Design User Guide (UG583) [Ref 4]. The ZCU111 DDR4 component interface is a 40Ω
impedance implementation. Other memory interface details are also available in the
UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150) [Ref 5].
For more details, see the Micron MTA4ATF51264HZ-2G6E1 data sheet at the Micron website
[Ref 15]
The connections between the DDR4 component memories and the XCZU28DR banks are
referenced in Appendix B, Xilinx Design Constraints.
ZCU111 Board User Guide 25
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Chapter 3: Board Component Descriptions
Send Feedback
PSMIO
Tab l e 3- 2 provides PS MIO peripheral mapping implemented on the ZCU111 board. See the
Zynq UltraScale+ Device Technical Reference Manual (UG1085) [Ref 3] for more information
on PS MIO peripheral mapping.
Table 3-2: MIO Peripheral Mapping
MIO[0:25] Bank 500 MIO[26:51] Bank 501 MIO[52:77] Bank 502
0 QSPI 26 PMU IN 52 USB0
1QSPI27DPAUX53USB0
2 QSPI 28 DPAUX 54 USB0
3QSPI29DPAUX55USB0
4 QSPI 30 DPAUX 56 USB0
5 QSPI 31 Not assigned/no connect 57 USB0
6 Not assigned/no connect 32 PMU OUT 58 USB0
7 QSPI 33 PMU OUT 59 USB0
8 QSPI 34 PMU OUT 60 USB0
9 QSPI 35 PMU OUT 61 USB0
10 QSPI 36 PMU OUT 62 USB0
11 QSPI 37 PMU OUT 63 USB0
12 QSPI 38 GPIO 64 GEM3
13 GPIO 39 SD1 65 GEM3
14 I2C0 40 SD1 66 GEM3
15 I2C0 41 SD1 67 GEM3
16 I2C1 42 SD1 68 GEM3
17 I2C1 43 Not assigned/no connect 69 GEM3
18 UART0 44 Not assigned/no connect 70 GEM3
19 UART0 45 SD1 71 GEM3
20 Not assigned/no connect 46 SD1 72 GEM3
21 Not assigned/no connect 46 SD1 73 GEM3
22 GPIO 48 SD1 74 GEM3
23 GPIO 49 SD1 75 GEM3
24 Not assigned/no connect 50 SD1 76 MDI03
ZCU111 Board User Guide 26
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25 Not assigned/no connect 51 SD1 77 MDI03
Chapter 3: Board Component Descriptions
Send Feedback
Quad SPI Flash Memory (MIO 0–12)
[Figure 2-1, callout 4]
The Micron dual MT25QU02GCBB8E12-0sit serial NOR flash Quad SPI flash memory can
hold the boot image for the RFSoC system. This interface is used to support QSPI32 boot
mode as defined in the Zynq UltraScale+ Device Technical Reference Manual (UG1085)
[Ref 3].
The dual Quad SPI flash memory located at U17/U18 provides 4 Gb of non-volatile storage
that can be used for configuration and data storage.
• Part number: MT25QU02GCBB8E12-0SIT (Micron)
• Supply voltage: 1.8V
• Datapath width: 8 bits
• Data rate: various depending on single, dual, or quad mode
The configuration and Quad SPI flash memory section of the Zynq UltraScale+ Device
Technical Reference Manual (UG1085) [Ref 3] provides details on using the memory. For
more Quad SPI details, see the Micron MT25QU02GCBB8E12-0SIT data sheet at the Micron
website [Ref 15].
The connections between the Quad SPI flash memory and XCZU28DR PS bank 500 are
referenced in Appendix B, Xilinx Design Constraints.
GPIO (MIO 13, 38)
These two GPIO bits are connected to the U42 MSP430 system controller for general
purpose signaling or communications between the Zynq UltraScale+ RFSoC device and the
MSP430 system controller. These signals are level-shifted by TSX0108E U41. The
connections between the U42 system controller and the XCZU28DR RFSoC are listed in
Tab l e 3- 3.
Table 3-3: System Controller U42 GPIO Connections to XCZU28DR U1
XCZU28DR (U1)
Pin
E27 MIO38_PS_GPIO1 P1_6 19
R28 MIO13_PS_GPIO2 P1_7 20
Net Name
Pin Name Pin #
MSP430 U42
ZCU111 Board User Guide 27
UG1271 (v1.1) August 6, 2018 www.xilinx.com
X-Ref Target - Figure 3-2
Zynq UltraScale+
RFSoc PS-Side
RFSoC PL-Side
I2C0
PS_I2C0
PS_I2C1
PL_I2C0
PL_I2C1
0x74
0
1
2
3
4
5
6
7
EEPROM
SI5341
USER_SI570
USER_MGT_S1570
SI5328
I2CSP1
RFMC
N.C.
12C
Mux
#1
0x75
0
1
2
3
4
5
6
7
FMC+ HSPC
N.C.
SYSMON (DNP resistors)
PS_DDR4_SODIMM
SFP283
SFP282
SFP281
SFP280
12C
Mux
#2
0x75
0
1
2
3
INA226 PMBus
N.C.
IRPS5401 PS + PL Voltage Controller PMBus
SYSMON
12C
Mux
#3
PMBus Cable
0x20
GPIO
Expander
U22 TCA6416A
System Controller
P3
P4
U42 MSP430
U23 PCA9544A
I2C0
J19
I2C1
U27 TCA9548A
U26 TCA9548A
I2C1
U1 XCZU28DR
L/S
U19
L/S
U20
L/S
U25
L/S
U24
X20530-062118
Send Feedback
Chapter 3: Board Component Descriptions
I2C0 (MIO 14-15), I2C1 (MIO 16-17)
Figure 3-2 shows a high-level view of the I2C0 and I2C1 bus connectivity.
Figure 3-2: I2C0 and I2C1 Bus Connectivity Overview
ZCU111 Board User Guide 28
UG1271 (v1.1) August 6, 2018 www.xilinx.com
X-Ref Target - Figure 3-3
TCA6416A
P00
P01
P02
P04
P05
P06
MAX6643_OT_B
MAX6643_FANFAIL_B
MI026_PMU_INPUT_LS
SFP28_SI5328_INT_ALM
IIC_MUX_RESET_B
GEM3_EXP_RESET_B
SDA/
SCL
BANK 500
PS I2C0
MIO15/
MIO14
U1
BANK 64
PL I2C0
AW16/AT16
U1
MPS430
U42
22 P3_0
23 P3_1
L/S
U19
0x20
P10
P11
P12
P16
P17
FMC_HSPC_PRSNT_M2C_B
CLK_SPI_MUX_SEL0
CLK_SPI_MUX_SEL1
IRPS5401_ALERT_B
INA226_PMBUS_ALERT
U20
TCA6416A
SDA/
SCL
0x75
INA226_PMBUS_SCA/SCL
Not Connected
IRPS5401_PMBUS_SDA/SCL
SYSMON_SCA/SCL
U23
SD0/SC0
SD1/SC1
SD2/SC2
SD3/SC3
U22
I2C0_SDA/SCL
L/S
X20531-062118
Send Feedback
Chapter 3: Board Component Descriptions
I2C0 (MIO 14-15)
[Figure 2-1, callout 13]
The I2C bus I2C0 connects the RFSoC U1 PS bank 500, PL bank 64, and the system controller
U42 to a GPIO 16-bit port expander (TCA6416A U22) and I2C switch (PCA9544A U23). The
port expander enables controlling resets and power system enable pins, and accepting
various alarm inputs without requiring the PL-side to be configured. The I2C0 bus also
provides access to the PMBus power controllers and the INA226 power monitors via the
U23 PCA9544A switch. TCA6416A U22 is pin-strapped to respond to I2C address 0x20. The
PCA9544A U23 switch is set to 0x75.
The devices on each port of the I2C0 U22 TCA6416A port expander are listed in Tab l e 3- 4 ,
and the devices on each bus of the I2C0 U23 PCA9544A switch are listed in Ta bl e 3 - 5.
Figure 3-3 shows a high-level view of the I2C0 bus connectivity represented in Ta bl e 3 -4
and Tab le 3-5 .
ZCU111 Board User Guide 29
UG1271 (v1.1) August 6, 2018 www.xilinx.com
Figure 3-3: I2C0 Bus Topology
Chapter 3: Board Component Descriptions
Send Feedback
Table 3-4: I2C0 Port Expander TCA6416A U22 Addr. 0x20 Connections
TCA6416A
Connected To
U22
Schematic Net Name
Pin
Name
SDA 23 I2C0_SDA
SCL 22 I2C0_SCL
P00 4 MAX6643_OT_B 9 OT_B U52 MAX6643
P01 5 MAX6643_FANFAIL_B 4 FANFAIL_B U52 MAX6643
P02 6 MIO26_PMU_INPUT_LS G25 PS_MIO26 U1 XCZU28DR
P04 8 SFP_SI5382_INT_ALM 12 INTRB U48 SI5382A
P05 9 IIC_MUX_RESET_B 3 RESET_B U26,U27 TCA9548A
P06 10 GEN3_EXP_RESET_B 2 B U14 SN74LVC1G08
P10 13 FMCP_HSPC_PRSNT_M2C_B
P11 14 CLK_SPI_MUX_SEL0 14 S0 U97 IDTQS3VH253QG8
Pin
No.
Pin
No.
4 OE U45 NC7SZ66P5X
H2 PRSNT_M2C_L J26(H) ASP_184329_01
Z1 PRSNT_M2C_L J26(Z) ASP_184329_01
Pin Name
Refer to connections shown in Figure 3-3.
TCA6416A U22 Addr. 0x20
Reference
Designator
Device
P12 15 CLK_SPI_MUX_SEL1 2 S1 U97 IDTQS3VH253QG8
11 INT2_B U23 PCA9544A
P16 19 IRPS5401_ALERT_B
P17 20 INA226_PMBUS_ALERT
17 ALERT_B U53,U55,U57 IRPS5401
17 SALERT_B U68,U70,U74,U75 IR38060
4 INT0_B U23 PCA9544A
3ALERT
3ALERT
U3,U59-U61
U63-U66
INA226
U67,U69,U71,U73,
U77,U79
ZCU111 Board User Guide 30
UG1271 (v1.1) August 6, 2018 www.xilinx.com
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