Xilinx ZCU102 User Manual

ZCU102 Evaluation
Board

User Guide

UG1182 (v1.2) March 20, 2017

Revision History

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The following table shows the revision history for this document.

Date Version Revision

03/20/2017 1.2

11/16/2016 1.1

05/11/2016 1.0

Added notes to Dimensions in Chapter 1. Updated SW6 default switch setting in

Table 2-2 and SD configuration setting in Table 2-4. Clarified SW6[4:1] boot mode pin

settings under Quad-SPI and SD in Chapter 2. Changed “DDR SODIMM Memory J1”
heading to “DDR Component Memory” in Table 3-4. Changed PS_REF_CLK frequency
from 33 MHz to 33.33 MHz in Table 3-12. Changed “UART2_RTS_O_B” to
“UART2_CTS_O_B” in Table 3-16. Replaced Figure 3-16. Changed “QSPI119 (LWR),
U120 (UPR)” heading to “MSP430 U41” in Table 3-17. Clarified references to

Figure 3-17 in Table 3-19 and Table 3-20. Added addresses to titles in Table 3-21 and
Table 3-22 and headings in Table 3-23 and Table 3-24. Changed “22” to “L22” in
Table 3-28. Updated GTH connectivity for Quad 128, Quad 228, Quad 229, and

Quad 23 under GTH Transceivers in Chapter 3. Updated bank assignments in

Figure 3-35. Added callout 44 to Switches in Chapter 3. Updated Xilinx websites in
Appendix D, Additional Resources and Legal Notices.

Updated device part number from XCZU9EG-2FFVB1156 to XCZU9EG-2FFVB1156I
throughout document. Updated board photos (Figure 2-1 and Figure 2-1) to rev 1.0.
Updated Table 2-1 and Table 2-3. Updated Chapter 3, Component Descriptions.
Updated Appendix B, Master Constraints File Listing.

Initial Xilinx release - limited distribution.

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UG1182 (v1.2) March 20, 2017

Table of Contents

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Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Chapter 1: Introduction

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Board Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Board Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Environmental . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Operating Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Chapter 2: Board Setup and Configuration

Board Component Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Default Switch and Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

MPSoC Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Chapter 3: Board Component Descriptions

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Component Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Zynq UltraScale XCZU9EG MPSoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

PS-Side: DDR4 SODIMM Socket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

DDR4 Component Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

PSMIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Quad-SPI Flash Memory (MIO 0–12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

USB 3.0 Transceiver and USB 2.0 ULPI PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

SD Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Programmable Logic JTAG Programming Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

EMIO ARM Trace Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

GEM3 Ethernet (MIO 64-77) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

10/100/1000 MHz Tri-Speed Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

CP2108 USB UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

GPIO (MIO 13, 38) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

I2C0 (MIO 14-15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

I2C1 (MIO 16-17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

UART0 (MIO 18-19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

UART1 (MIO 20-21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

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GPIO (MIO 22-23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

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CAN1 (MIO 24-25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

PMU GPI (MIO 26) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

DPAUX (MIO 27-30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

PCIe Reset (MIO 31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

PMU GPO (MIO 32-37) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

HDMI Video Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

HDMI Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

SFP/SFP+ Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

SFP/SFP+ Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

User PMOD GPIO Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Prototype Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

User I2C0 Receptacle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

User I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Power and Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

GTH Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

PS-Side: GTR Transceivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

PCIe (MIO 31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

PCI Express Root Port Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

FPGA Mezzanine Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

FMC HPC0 Connector J5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

FMC HPC1 Connector J4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

Cooling Fan Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

VADJ_FMC Power Rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

TI MSP430 System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

ZCU102 Board Power System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

Monitoring Voltage and Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

Appendix A: VITA 57.1 FMC Connector Pinouts

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Appendix B: Master Constraints File Listing

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

ZCU102 Board Constraints File Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Appendix C: Regulatory and Compliance Information

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Declaration of Conformity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Appendix D: Additional Resources and Legal Notices

Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

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References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

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Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

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UG1182 (v1.2) March 20, 2017

Introduction

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Overview

The ZCU102 is a general purpose evaluation board for rapid-prototyping based on the
Zynq® UltraScale+
speed DDR4 SODIMM and component memory interfaces, FMC expansion ports,
multi-gigabit per second serial transceivers, a variety of peripheral interfaces, and FPGA
logic for user customized designs provides a flexible prototyping platform.

™

XCZU9EG-2FFVB1156I MPSoC (multiprocessor system-on-chip). High

Chapter 1

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UG1182 (v1.2) March 20, 2017

X-Ref Target - Figure 1-1

Prototype Header
Display Port Aux
MSP430 GPIO IIC0
Connection
Pages 44, 56, 38

SYSMON IIC
SFP Disables

MSP430/CP2108 UART

HDMI control
Pages 6, 34

PMOD
125MHz CLK
Trace
IIC1 Connection
Pages 54-55, 58

Ethernet
USB

Pages 51-52

SDIO
PMU, GPIO
PS Display Port Aux

Pages 47, 44-45

FMC HPC1
GT Interface

Pages 30-33

HDMI
SMA

Pages 35-37, 40

SFP 2x2 Cage

Page 34

FMC HPC0
GT Interface

Pages 26-29

FMC HPC0
LA Bus

Pages 26-29

FMC HPC0
LA Bus

Pages 41-43

FMC HPC1
LA Bus

Pages 30-33

HDMI TX Clock

Pages 35-37

DDR4 Comp.
Memory
16-bit: 1 x 16-bit

MT40A256M16GE-075E

Pages 26-29

SFP Recovered
Clock

Page 34

HDMI Recovered
Clock

Pages 35-37

MUX connections:
PCIe / DisplayPort
USB3.0 / SATA

Pages 43-45, 48, 51

INIT, DONE LEDs
PROG. PB
PS POR, SRST PBs

Page 12

SI570
Programmable
Oscillator

Page 40

BPIO

74.25MHz clk

Page 39

PS UART
PS I2C
PS QSPI

Pages 42, 46, 57-58

DDR4 72-bit
S0DIMM

Page 23

DDR4 DIMM
DECOUPLING

Page 24

JTAG CONN.

Page 22

GTR Muxes

Page 45

PS/PL/System
Clock devices

Pages 39-41

MECHANICALS

Page 87

GTH230

GTH229

GTH228

66

HP

65

HP

64

HP

49

50

48 47

PS

502

PS

501

PS

503

(PS-Side

CONFIG)

GTH130

GTH129

GTH128

PS

GTR505

67

HP

U1

0

44

PS

500

PS

504

PS DDR

PS PWR

XCZU9EGFFVB1156

;

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Chapter 1: Introduction

Block Diagram

The ZCU102 board block diagram is shown in Figure 1-1. Page numbers in the block
diagram reference the corresponding page number(s) of schematic 0381701.

Figure 1-1: ZCU102 Evaluation Board Block Diagram

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Chapter 1: Introduction

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Board Features

The ZCU102 evaluation board features are listed here. Detailed information for each feature
is provided in Chapter 3, Board Component Descriptions.

• XCZU9EG-2FFVB1156I MPSoC

•PL V

for range in datasheet

CCINT

• Form factor for PCIe Gen2x4 Host, Micro-ATX chassis footprint

• Configuration from QSPI

• Configuration from SD card

• Configuration over JTAG with PC4 header

• Configuration over JTAG with ARM 20-pin header

• Configuration over USB-to-JTAG Bridge

• Clocks (PL-system, PS_CLK, Programmable Clock, SMA, SMA_GT_REF, Ethernet, USB)

• PS DDR4 64-bit SODIMM w/ ECC

• PL DDR4 Component (16-bit)

• PS GTR assignment

SATA

°

DisplayPort

°

USB3

°

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PCIe Gen2x4 Root Port

°

• PL GTH assignment

FMC #1 (8 GTH) and FMC #2 (8 GTH) PL GT assignment

°

HDMI (3 GTH) PL GT assignment

°

SFP+ (4 GTH) PL GT assignment

°

SMA (1 GTH) PL GT assignment

°

• PL FMC HPC #1 Connectivity - Full LA Bus

• PL FMC HPC #2 Connectivity - Partial LA Bus

•PS MIO: QSPI

• PS MIO: Ethernet

• PS MIO: USB2 (same connector as USB3)

• PS MIO: SD

•PS MIO: CAN

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• PS MIO: UART (using USB-to-UART bridge)

• PS MIO: Second UART

• PS MIO: I2C shared across PS and PL

•PS/PL EMIO: Trace

•PL-side UART

• PL-side LEDs (8)

• PL-side DIP switch (8-position)

• PL-side Pushbuttons (5)

• PS-side Pushbutton (1)

• PS-side LED (1)

• System User Switches (PROG, CPU Reset)

•PJTAG

Chapter 1: Introduction

• Security - PSBATT button battery backup

•SYSMON

• Operational Switches (Power on/off, PROG, Boot mode)

• Operational Status LEDs (power supply status, INIT, DONE, PG, JTAG status, DDR power
good)

• Power Management

The ZCU102 evaluation board provides designers a rapid prototyping platform utilizing the
XCZU9EG-2FFVB1156I device. The ZU9EG contains many useful processor system (PS) hard
block peripherals exposed through the Multi-use I/O (MIO) interface and a variety of FPGA
programmable logic (PL), high-density (HD) and high-performance (HP) banks. Table 1-1
lists a brief summary of the resources available within the ZU9EG. A feature set overview,
description, and ordering information is provided in the UltraScale Architecture and Product
Overview (DS890) [Ref 1].

Table 1-1: Zynq UltraScale+ MPSoC ZCU9EG Features and Resources

Feature Resource Count

HD banks 5 banks, total of 120 pins

HP banks 4 banks, total of 208 pins

ZCU102 Evaluation Board User Guide www.xilinx.com 9

UG1182 (v1.2) March 20, 2017

MIO banks 3 banks, total of 78 pins

PS-side GTR 6 Gb/s transceivers 4 PS-GTRs

PL-side GTH 16.3 Gb/s transceivers 24 GTHs

Effective LEs 575K

Chapter 1: Introduction

Send Feedback

Table 1-1: Zynq UltraScale+ MPSoC ZCU9EG Features and Resources (Cont’d)

Feature Resource Count

Logic cells 480K

CLB flip-flops 548K

Max. distributed RAM 8.8 Mb

Total block RAM 32.1 Mb

DSP slices 2,520

Board Specifications

Dimensions

Width: 9.350 in. (23.749 cm)

Length: 9.600 in. (24.384 cm)

Thickness: 0.104 in. (0.2642 cm)

Notes:

• A 3D model of this board is not available.

• ZCU102 board documentation (xdc listing, schematics, layout files and board outline/fab
drawings, etc.) is available on the web at: www.xilinx.com/zcu102

.

Environmental

Temp erature

Operating: 0°C to +45°C

Storage: -25°C to +60°C

Humidity

10% to 90% non-condensing

Operating Voltage

ZCU102 Evaluation Board User Guide www.xilinx.com 10

UG1182 (v1.2) March 20, 2017

+12 V

DC

Board Setup and Configuration

Send Feedback

Board Component Location

Figure 2-1 shows the ZCU102 board component locations. Each numbered component

shown in Figure 2-1 is keyed to Table 2-1. Table 2-1 identifies the components, references
the respective schematic page numbers, and links to a detailed functional description of the
components and board features in Chapter 3.

IMPORTANT: Figure 2-1 is for visual reference only and might not reflect the latest revision of the

board. (This user guide documents ZCU102 Rev. 1.0 and later.)

IMPORTANT: There could be multiple revisions of this board. The specific details concerning the

differences between revisions is not captured in this document. This document is not intended to be a
reference design guide and the information herein should not be used as such. Always refer to the
schematic and xdc of the specific ZCU102 version of interest for such details.

Chapter 2

CAUTION! Electrostatic discharge (ESD) can cause board damage. Follow standard ESD prevention

measures when handling the board.

ZCU102 Evaluation Board User Guide www.xilinx.com 11

UG1182 (v1.2) March 20, 2017

X-Ref Target - Figure 2-1

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Send Feedback

Chapter 2: Board Setup and Configuration

Figure 2-1: ZCU102 Evaluation Board Components

ZCU102 Evaluation Board User Guide www.xilinx.com 12

UG1182 (v1.2) March 20, 2017

Table 2-1: ZCU102 Board Components

Send Feedback

Chapter 2: Board Setup and Configuration

Callout Ref. Des. Feature/Component Notes

Page Number

1

2

3

4

5

6J100SD Card Interface (connector) Hirose DMIAA-SF-PET(21) 47

7

8

9

10

11 U20 SFP/SFP+ Clock Recovery (jitter attenuated clock) Silicon Labs SI5328B-C-GMR 41

12

13

14

15

16 U34, U135 I2C1 (MIO 16-17) bus switches TI TCA9548APWR, 2ea. 58

17

18 U41 TI MSP430 System Controller TI MSP430F5342 38

19

20

21 DS37-DS44 User I/O (8 LEDs) GPIO LEDs, GREEN 0603 53

22 SW13

23

U1 Zynq UltraScale XCZU9EG MPSoC

with fan sink on soldered FPGA

J1 PS-Side: DDR4 SODIMM Socket

with SODIMM

U2 DDR4 Component Memory, (4 Gb) Micron

U119, U120 Quad-SPI Flash Memory (MIO 0–12) (1 Gb total) Micron

U116, J96 USB 3.0 Transceiver and USB 2.0 ULPI PHY (USB

micro-AB connector)

U21/J2 Programmable Logic JTAG Programming Options

(module with separate USB Micro-B conn.)

U42 Programmable User Clock

(300 MHz default, 3.3V LVDS)

U56 Programmable User MGT Clock

(156.250 MHz default, 3.3V LVDS)

U69 SI5341B 10 Independent Output Any-Frequency

Clock Generator (PS Reference Clock) (I2C

programmable any frequency clock generator)

U98/P12 Ethernet PHY LED Interface Ethernet PHY U98 with

P12 RJ45 with magnetics

U40/J83 CP2108 USB UART Interface (bridge IC/USB Micro-B

connector)

U94/P7 HDMI Video Output (controller/connector) TI SN65DP159RGZ,

U60, U61,

U97

J54 SFP/SFP+ Connector (quad) Allbest

J55/J87 User PMOD GPIO Headers

J160 For more information about PMOD connector

SW14-SW18 User I/O (pushbutton switches, active High) E-Switch TL3301EP100QG

I2C0 (MIO 14-15) bus switch and expanders) TI PCA9544ARGYR, 2 ea.

(PMOD0-RA receptacle/PMOD1-vert. male pin hdr.)

compatible PMOD modules, see [Ref 23]. (PMOD I2C

RA receptacle)

User I/O (8-pole DIP switch) C&K SDA08H1SBD 53

XCZU9EG-2FFVB1156I
Radian FA35+K52B+T710

LOTES ADDR0067-P001A
Micron

MT40A256M16GE-075E:B

MT25QU512ABB8ESF-OSIT

SMCS USB3320-EZK, KYON
KMMX-AB10-SMT1SB30TR

Digilent JTAG_2_NC,
Hirose ZX62D-AB-5P8

Silicon Labs
SI570BAB001614DG

Silicon Labs SI
SI570BAB001544DG

Silicon Labs
SI5341B-B05071-GM 39

TI DP83867IRPAP,
Wurth 7499111221A

Silicon Labs CP2108-B02-GM,
Hirose ZX62D-AB-5P8

TEC Connectivity 1888811-1

TI TCA6416APWR

R-OP-008080-6-F-N-26-F63

SULLINS PPPO062LJBN-RC,
SULLINS PBC36DAAN

SULLINS PPPO062LJBN-RC

placed in N, S, W, E, C pattern

Schematic

0381449

23

25

46

51

22

40

40

52

42

35

57

34

55

49

53

ZCU102 Evaluation Board User Guide www.xilinx.com 13

UG1182 (v1.2) March 20, 2017

Table 2-1: ZCU102 Board Components (Cont’d)

Send Feedback

Chapter 2: Board Setup and Configuration

Callout Ref. Des. Feature/Component Notes

0381449

Page Number

24 SW20 User I/O (CPU_RESET pushbutton switch, active High) E-Switch TL3301EP100QG 53

Schematic

25

26

27

28

29 J52 Power connector (Power On/Off Slide Switch) MOLEX 39-30-1060 59

30 SW5 Program_B Pushbutton (FPGA program) E-Switch TL3301EP100QG 12

31 J5 FMC HPC0 Connector J5 Samtec ASP_134486_01 26-29

32 J4 FMC HPC1 Connector J4 Samtec ASP_134486_01 30-33

33 J10 Switched output power connector TEC Connectivity 794285-1 59

34 - Power management system (top and bottom) Maxim Regulators 59-86

35 P1 PCI Express Root Port Slot (PCIe 4-lane connector) FCI 10061913-101CLF 43

36 P11 DPAUX (MIO 27-30) (DisplayPort) MOLEX 0472720001 44

37 J84 PMBus connector (Monitoring Voltage and Current) ASSMANN

38 J92 JTAG connector (TI MSP430 System Controller) TYCO 5103308-2 38

39 J6 ARM JTAG connector (Programmable Logic JTAG

40 U108 HDMI Clock Recovery (HDMI jitter attenuated clock) Silicon Labs SI 5324C-C-GMR 37

41 J3 For more information about PMOD connector

42 J70-J72

43 P6 EMIO ARM Trace Port (ARM Trace receptacle) MICTOR 2-5767004-2 54

44 SW6 Switches (mode 4-pole DIP switch) 4-pole C&K SDA04H1SBD 12

45 (Misc. DSnn) Power and Status LEDs (Misc. LEDs) Miscellaneous LEDs 86

SW8 DIP Switch, 5-pole, GPIO (TI MSP430 System

Controller)

SW3, SW4 Switches (SRST_RESET, POR_B pushbutton switches,

active Low)

U122, J98 CAN1 (MIO 24-25) (bus transceiver/2x4 male header) TI SN65HVD232,

SW1 Power On/Off Slide Switch (Power On/Off slide

switch)

Programming Options)

compatible PMOD modules, see [Ref 23]. MPSoC U1

Bank 50 GPIO 2x12 male pin proto header

SMA (MGTH interface SMA connectors) ROSENBERGER

J79-J80

5 pole C&K SDA05H1SBD 38

E-Switch TL3301EP100QG 12

SULLINS PBC36DAAN

C&K 1201M2S3AQE2 59

AWHW16G-0202-T-R

ASSMANN
AWHW20G-0202-T-R

SULLINS PBC36DAAN

32K10K-400L5

50

57

22

56

40

ZCU102 Evaluation Board User Guide www.xilinx.com 14

UG1182 (v1.2) March 20, 2017

X-Ref Target - Figure 2-2

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;

Send Feedback

Chapter 2: Board Setup and Configuration

Default Switch and Jumper Settings

Figure 2-2 shows the board jumper header and DIP switch locations. Each numbered

component shown in the figure is keyed to Table 2-2 (for default switch settings) or

Table 2-3 (for default jumper settings). Both tables reference the respective schematic page

numbers.

ZCU102 Evaluation Board User Guide www.xilinx.com 15

UG1182 (v1.2) March 20, 2017

Figure 2-2: DIP Switch and Board Header Jumper Locations

Switches

Send Feedback

Table 2-2: Default Switch Settings

Chapter 2: Board Setup and Configuration

DIP

Switch

SW1 Main Power Switch OFF 29 59

Switch PS_MODE select

• ON = pull down =

• OFF = pull up = 1

SW6

SW8

SW13

• MODE[3:0] = 0010 (selects QSPI32)

MSP430 GPIO 5-POLE

•ON = GND

• OFF = Open

GPIO 8-POLE

• OFF = pull down

• ON = pull up

Function Default

0

4: PS_MODE3
3: PS_MODE2
2: PS_MODE1
1: PS_MODE0

1: SW0
2: SW1
3: SW2
4: SW3
5: SW4

ON
ON

OFF

ON

OFF
OFF
OFF
OFF
OFF

All OFF 28 53

Figure 2-2

Callout

26 12

27 38

Schematic

Page

Jumpers

Table 2-3: Default Jumper Settings

Jumper Function Default

POR_OVERRIDE

J85

J12

J13

J90

• 1-2: Enable

•2-3: Disable

SYSMON I2C Address

• Open: SYSMON_VP_R floating

• 1-2: SYSMON_VP_P pulled down

SYSMON I2C Address

• Open: SYSMON_VN_R floating

• 1-2: SYSMON_VP_N pulled down

SYSMON VREFP

• 1-2: 1.25V VREFP connected to FPGA

• 2-3: VREFP connected to GND

2-3 1 3

1-2 2 3

1-2 3 3

1-2 4 3

Figure 2-2

Callout

Schematic

Page

ZCU102 Evaluation Board User Guide www.xilinx.com 16

UG1182 (v1.2) March 20, 2017

Table 2-3: Default Jumper Settings (Cont’d)

Send Feedback

Chapter 2: Board Setup and Configuration

Jumper Function Default

Reset Sequencer PS_POR_B

J20

J21

J22

J14

J15

J56

• OFF: No sequencer control of PS_POR_B

• 1-2: Sequencer can control PS_POR_B

Reset Sequencer PS_SRST_B

• OFF: No sequence control of PS_SRST_B

• 1-2: Sequencer can control PS_SRST_B

Reset Sequencer inhibit

• OFF: Sequencer normal operation

• 1-2: Sequencer inhibit (resets will stay
asserted)

ARM Debug VTREF

•Open: VTREF floating

• 1-2: VTREF = VCCOPS3 (1.8V)

ARM Debug VSUPPLY

• OFF: VSUPPLY floating

• 1-2: VSUPPLY = VCCOPS3 (1.8V)

VCCO_PSDDR_504 select

• 1-2: Switched DDR4 VDDQ

• 3-4: Direct DDR4 VDDQ

1-2 5 12

1-2 6 12

OFF 7 12

1-2 8 22

OFF 9 22

1-2 10 24

Figure 2-2

Callout

Schematic

Page

DDR4 Reset Suspend Enable

J159

J16 SFP0 TX: 1-2:Disable; OFF: Enable OFF 12 34

J17 SFP1 TX: 1-2:Disable; OFF: Enable OFF 12 34

J42 SFP2 TX: 1-2:Disable; OFF: Enable OFF 14 34

J54 SFP3 TX: 1-2:Disable; OFF: Enable OFF 15 34

J162

J110

J109

J112

• 1-2: Suspend disabled (Gate bypass)

• 2-3: Suspend enabled

PCIe PRSNT select

•1-2: x1

•3-4: x4

•5-6: GND (not used)

USB ULPI CVBUS Select

•1-2: DEVICE or OTG Mode

• 2-3: Host Mode

USB ULPI ID select

• 1-2: Connector ID

• 2-3: VDD33 ID

USB ULPI Shield GND select

•1-2: Capacitor

•2-3: GND

1-2 11 24

5-6 16 43

1-2 17 51

2-3 18 51

1-2 19 51

ZCU102 Evaluation Board User Guide www.xilinx.com 17

UG1182 (v1.2) March 20, 2017

Table 2-3: Default Jumper Settings (Cont’d)

Send Feedback

Chapter 2: Board Setup and Configuration

Jumper Function Default

USB ULPI Device or Host select

J7

J113

J88

J38

J153

J9

• 1-2: HOST/OTG

•Open: Device

USB ULPI Device/Host or OTG select

• 1-2: Device or Host

•2-3: OTG

ARM Trace VTREF

• 1-2: 3.3V

•Open: 0V

ARM Trace power

• 1-2: 3.3V

•Open: 0V

Power inhibit

• OFF: rails power on normally

• 1-2: all rails (except UTIL) OFF

PS_DDR4_VPP_2V5 power inhibit (U39)

• OFF: rail powers on normally

• 1-2: PS_DDR4_VPP_2V5 OFF

OPEN 20 51

1-2 21 51

1-2 22 54

1-2 23 54

OFF 24 59

OFF 25 77

Figure 2-2

Callout

Schematic

Page

J164 MSP430 firmware upgrade header OFF 26 38

ZCU102 Evaluation Board User Guide www.xilinx.com 18

UG1182 (v1.2) March 20, 2017

Chapter 2: Board Setup and Configuration

Send Feedback

MPSoC Device Configuration

Zynq UltraScale+ XCZU9EG MPSoC devices use a multi-stage boot process documented in
the Boot and Configuration chapter of the Zynq UltraScale+ MPSoC Technical Reference
Manual (UG1085) [Ref 2].

Switch SW6 configuration option settings are identified in Table 2-4.

Table 2-4: Switch SW6 Configuration Option Settings

Boot Mode Mode Pins [3:0] Mode SW6 [4:1]

JTAG

QSPI32

SD

Notes:

1. Default switch setting.

0000

0010

1110

(1)

on, on, on, on

on, on, off, on

off, off, off, on

JTAG

Vivado, SDK, or third-party tools can establish a JTAG connection to the Zynq UltraScale+
MPSoC device through one of the three provided JTAG interfaces:

1. Xilinx platform USB or cable PC4 connector (J8)

2. ARM 20-pin JTAG connector (J6)

3. Digilent SMT2.5 USB-to-JTAG module with off-module micro-USB connector (J2)

Quad-SPI

Booting from the dual Quad-SPI nonvolatile configuration memory is accomplished by
storing a valid Zynq UltraScale+ MPSoC boot image into the Quad-SPI flash devices
connected to the MIO Quad-SPI interface, setting the boot mode pins SW6 [4:1] = QSPI32
(see Table 2-4), then either power-cycling or pressing the power-on reset (POR) pushbutton.
SW6 is callout 23 in Figure 2-1.

ZCU102 Evaluation Board User Guide www.xilinx.com 19

UG1182 (v1.2) March 20, 2017

SD

Booting from an SD card is accomplished by storing a valid Zynq UltraScale+ MPSoC boot
image file onto an SD card (plugged into SD socket J100) connected to the MIO SD
interface, setting the boot mode pins SW6 [4:1] = SD (see Table 2-4), then either
power-cycling or pressing the power-on reset (POR) pushbutton.

See the Zynq UltraScale+ MPSoC Technical Reference Manual (UG1085) [Ref 2] for more
information about Zynq UltraScale+ MPSoC configuration options.

Board Component Descriptions

Send Feedback

Overview

This chapter provides a detailed functional description of the board’s components and
features. Table 2-1, page 13 identifies the components, references the respective schematic
page numbers, and links to the corresponding detailed functional description in this
chapter. Component locations are shown in Figure 2-1, page 12.

Component Descriptions

Chapter 3

Zynq UltraScale XCZU9EG MPSoC

[Figure 2-1, callout 1]

The ZCU102 board is populated with the Zynq UltraScale+ XCZU9EG-2FFVB1156I MPSoC
which combines a powerful processing system (PS) and user-programmable logic (PL) into
the same device. The processing system in a Zynq UltraScale+ MPSoC features the ARM®
flagship Cortex®-A53 64-bit quad-core processor and Cortex-R5 dual-core real-time
processor.

Production ZCU102 Evaluation boards will ship with -2LE speed grade devices. Support of
multiple speed grades requires voltage adjustments.

The PL-side V
in Table 3-1 to support multiple Zynq UltraScale+ MPSoC speed grades.

Table 3-1: Recommended Operating Conditions

Symbol Description Min. Typ. Max Units

Programmable Logic (PL)

V

CCINT

supply will be user adjustable via PMBUS with the voltage ranges shown

CCINT

Internal supply voltage.

For -1LI and -2LE devices: internal supply voltage.

For -3E devices: internal supply voltage.

0.825 0.850 0.875 V

0.698 0.720 0.742 V

0.873 0.900 0.927 V

ZCU102 Evaluation Board User Guide www.xilinx.com 20

UG1182 (v1.2) March 20, 2017

X-Ref Target - Figure 3-1

RPU

256 KB

OCM

LPD-DMA

CSU

PMU

Processing System

Cortex-R5
32 KB I/D

128 KB TCM

Cortex-R5

32 KB I/D

128 KB TCM

4 x 1GE

APU

Cortex-A53

32 KB I/D

Cortex-A53

32 KB I/D

Cortex-A53

32 KB I/D

Cortex-A53

32 KB I/D

GIC

SCU

ACP 1 MB L2

GPU

Mali-400 MP2

64 KB L2

2 x USB 3.0

NAND x8
ONFI 3.1

2 x SD3.0/

eMMC4.51

Quad-SPI

x 8

2 x SPI

2 x CAN

2 x I2C

2 x UART

GPIOs

SYSMON

MIO

Central
Switch

FPD-DMA

PCIe

Gen4

DisplayPort

v1.2 x1, x2

2 x SATA

v3.1

PCIe Gen2

x1, x2, or x4

SHA3
AES-GCM
RSA

Processor

System

BPU

DDRC (DDR4/3/3L, LPDDR3/4)

Programmable

Logic

128 KB RAM

PL_LPD

HP

GIC

RGMII

ULPI

PS-GTR

SMMU/CCI

GFC

USB 3.0

SGMII

Low Power Switch

To ACP

Low Power Full Power

Battery

Power

32-bit/64-bit

64-bit

MS

128-bit

MS

LPD_PL HPCHPM

GTY

Quad

GTH

Quad

Interlaken

100G

Ethernet

ACE

DisplayPort

Video and

Audio Interface

Low-latency

Peripheral Port

Low-latency

Peripheral Port

;

Send Feedback

Chapter 3: Board Component Descriptions

The top-level block diagram is shown in Figure 3-1.

ZCU102 Evaluation Board User Guide www.xilinx.com 21

UG1182 (v1.2) March 20, 2017

Figure 3-1: Zynq UltraScale+ MPSoC Top-Level Block Diagram

Chapter 3: Board Component Descriptions

Send Feedback

The Zynq UltraScale+ MPSoC PS block has three major processing units:

Cortex-A53 application processing unit (APU)-ARM v8 architecture-based 64-bit

°

quad-core multiprocessing CPU.

Cortex-R5 real-time processing unit (RPU)-ARM v7 architecture-based 32-bit dual

°

real-time processing unit with dedicated tightly coupled memory (TCM).

Mali-400 graphics processing unit (GPU)-graphics processing unit with pixel and

°

geometry processor and 64 KB L2 cache.

The Zynq UltraScale+ MPSoC PS has four high-speed serial I/O (HSSIO) interfaces
supporting the following protocols:

Integrated block for PCI Express® interface-PCIe™ base specification version 2.1

°

compliant.

SATA 3.1 specification compliant interface.

°

DisplayPort interface-implements a DisplayPort source-only interface with video

°

resolution up to 4K x 2K-30 (300 MHz pixel rate).

USB 3.0 interface-compliant to USB 3.0 specification implementing a 5 Gb/s line

°

rate.

Serial GMII interface-supports a 1 Gb/s SGMII interface.

°

The PS and PL can be coupled with multiple interfaces and other signals to effectively
integrate user-created hardware accelerators and other functions in the PL logic that are
accessible to the processors. They can also access memory resources in the processing
system. The PS I/O peripherals, including the static/flash memory interfaces share a
multiplexed I/O (MIO) of up to 78 MIO pins. Zynq UltraScale+ MPSoCs can also use the I/O
in the PL domain for many of the PS I/O peripherals. This is done through an extended
multiplexed I/O interface (EMIO).and boots at power-up or reset.

For additional information on Zynq UltraScale+ MPSoC devices, see the UltraScale

Architecture and Product Overview (DS890) [Ref 1], and the Zynq UltraScale+ MPSoC
Technical Reference Manual (UG1085) [Ref 2] for more information about Zynq UltraScale+

MPSoC configuration options.

ZCU102 Evaluation Board User Guide www.xilinx.com 22

UG1182 (v1.2) March 20, 2017

Chapter 3: Board Component Descriptions

;

Send Feedback

Encryption Key Backup Circuit

The XCZU9EG MPSoC U1 implements bitstream encryption key technology. The ZCU102
board provides the encryption key backup battery circuit shown in Figure 3-2

X-Ref Target - Figure 3-2

ZCU102 Evaluation Board User Guide www.xilinx.com 23

UG1182 (v1.2) March 20, 2017

Figure 3-2: Encryption Key Backup Circuit

The Seiko TS518FE rechargeable 1.5V lithium button-type battery B1 is soldered to the
board with the positive output connected to the XCZU9EG MPSoC U1 V
The battery supply current I

specification is 150 nA maximum when board power is off.

BATT

CC_PSBATT

pin AA22.

B1 is charged from the UTIL_1V8 1.8V rail through a series diode with a typical forward
voltage drop of 0.38V and 4.7 ΩK current limit resistor. The nominal charging voltage is

1.42V.

Chapter 3: Board Component Descriptions

Send Feedback

I/O Voltage Rails

There are nine PL I/O banks available on the XCZU9EG MPSoC. The voltages applied to the
XCZU9EG MPSoC I/O banks used by the ZCU102 board are listed in Table 3-2.

Table 3-2: I/O Voltage Rails

XCZU9EG Power Net Name Voltage Connected To

PL Bank 0

PL Bank 44

PL Bank 47

PL Bank 48

PL Bank 49

PL Bank 50

PL Bank 64

PL Bank 65

PL Bank 66

PL Bank 67

PS Bank 500

PS Bank 501

PS Bank 502

PS Bank 503

PS DDR Bank 504

NA NA

V

CC3V3

V

CC3V3

V

CC3V3

V

CC3V3

V

CC3V3

V

CC1V2

V

CCOPS

V

CCOPS

V

CCOPS

CCOPS3

(1)

(1)

(1)

V

ADJ_FMC

V

ADJ_FMC

V

ADJ_FMC

V

V

CCO_PSDDR_504

3.3V

3.3V

3.3V

3.3V

3.3V

1.2V

1.8V

1.8V

1.8V

1.8V

1.8V

1.8V

1.81V

1.2V

MPSoC Configuration Bank 0

GPIO DIP SW, PB SW, LEDs, 74.25 MHz CLK

GPIO PMOD0 (RT-ANG. FEMALE), PMOD1 (STR.
MALE), PL I2C1, TRACEDATA, 125 MHz CLK

TRACEDATA

HDMI Codec, SYSMON I2C, SFP CTRL, UART2, MSP430
UCA1

HDMI Codec, MSP430 GPIO, PL I2C0, PROTO. HDR. IO

DDR4 DQ[0:15], DDR4 ADDR/CTRL, USER_SI570 CLK

FMC_HPC1 LA BUS, HDMI TX

FMC_HPC0 LA BUS, HDMI REC CLK

FMC_HPC0 LA BUS, SFP REC CLK

QSPI LWR, QSPI UPR, UART1, MIO_I2C0, MIO_I2C1,
MIO_RXD/TXD, CAN IF

MIO_SD IF, MIO_PMU IF, MIO_DP IF

MIO_ENET, MIO_USB

PS CONFIGURATION IF

DDR4 SODIMM IF

ZCU102 Evaluation Board User Guide www.xilinx.com 24

UG1182 (v1.2) March 20, 2017

Notes:

1. The ZCU102 board is shipped with V

ADJ_FMC

set to 1.8V by the MSP430 system controller.

PS-Side: DDR4 SODIMM Socket

[Figure 2-1, callout 2]

The PS-side memory is wired to the Zynq UltraScale+ DDRC hard memory controller. A
64-bit single rank DDR4 SODIMM with ECC (72-bit) is inserted into socket J1. The ZCU102
is shipped with a DDR4 SODIMM installed:

• Manufacturer: Kingston

• Part Number: KVR21SE15S8/4

•Description:
4GByte DDR4 SODIMM

°

Single Rank x8

°

512Mbit x 72-Bit

°

PC4-2133 260-Pin

°

Chapter 3: Board Component Descriptions

Send Feedback

The ZCU102 supports full power-off suspend mode where only the system controller and
the PS-side DDR4 SODIMM memory are powered. The DDR4 memory is kept in a
self-refresh state and has its reset input controlled by the system controller such that the
memory is not reset when waking-up from suspend mode. DDR4 SODIMM standard right
angle Socket J1 connections are identified in Table 3-3.

Table 3-3: DDR4 SODIMM Socket J1 Connections to FPGA PS DDR Bank 504

XCZU9EG

(U1) Pin

AP29

AP30

AP26

AP27

AP25

AN24

AM29

AM28

AM26

AM25

AL28

AK27

AJ25

AL25

AH26

Net Name

DDR4 SODIMM Memory J1

Pin Number Pin Name

DDR4_SODIMM_A0 144 A0

DDR4_SODIMM_A1 133 A1

DDR4_SODIMM_A2 132 A2

DDR4_SODIMM_A3 131 A3

DDR4_SODIMM_A4 128 A4

DDR4_SODIMM_A5 126 A5

DDR4_SODIMM_A6 127 A6

DDR4_SODIMM_A7 122 A7

DDR4_SODIMM_A8 125 A8

DDR4_SODIMM_A9 121 A9

DDR4_SODIMM_A10 146 A10/AP

DDR4_SODIMM_A11 120 A11

DDR4_SODIMM_A12 119 A12

DDR4_SODIMM_A13 158 A13

DDR4_SODIMM_BA0 150 BA0

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UG1182 (v1.2) March 20, 2017

AG26

AK28

AH27

AP20

AP18

AP19

AP17

AM20

AM19

AM18

AL18

AP22

AP21

AP24

DDR4_SODIMM_BA1 145 BA1

DDR4_SODIMM_BG0 115 BG0

DDR4_SODIMM_BG1 113 BG1

DDR4_SODIMM_DQ0 8 DQ0

DDR4_SODIMM_DQ1 7 DQ1

DDR4_SODIMM_DQ2 20 DQ2

DDR4_SODIMM_DQ3 21 DQ3

DDR4_SODIMM_DQ4 4 DQ4

DDR4_SODIMM_DQ5 3 DQ5

DDR4_SODIMM_DQ6 16 DQ6

DDR4_SODIMM_DQ7 17 DQ7

DDR4_SODIMM_DQ8 28 DQ8

DDR4_SODIMM_DQ9 29 DQ9

DDR4_SODIMM_DQ10 41 DQ10

Chapter 3: Board Component Descriptions

Send Feedback

Table 3-3: DDR4 SODIMM Socket J1 Connections to FPGA PS DDR Bank 504 (Cont’d)

XCZU9EG

(U1) Pin

AN23

AL21

AL22

AM23

AL23

AL20

AK20

AJ20

AK18

AG20

AH18

AG19

AG18

AG21

AH21

Net Name

DDR4 SODIMM Memory J1

Pin Number Pin Name

DDR4_SODIMM_DQ11 42 DQ11

DDR4_SODIMM_DQ12 24 DQ12

DDR4_SODIMM_DQ13 25 DQ13

DDR4_SODIMM_DQ14 38 DQ14

DDR4_SODIMM_DQ15 37 DQ15

DDR4_SODIMM_DQ16 50 DQ16

DDR4_SODIMM_DQ17 49 DQ17

DDR4_SODIMM_DQ18 62 DQ18

DDR4_SODIMM_DQ19 63 DQ19

DDR4_SODIMM_DQ20 46 DQ20

DDR4_SODIMM_DQ21 45 DQ21

DDR4_SODIMM_DQ22 58 DQ22

DDR4_SODIMM_DQ23 59 DQ23

DDR4_SODIMM_DQ24 70 DQ24

DDR4_SODIMM_DQ25 71 DQ25

AG24

AG23

AK22

AJ21

AJ22

AK23

AG31

AG30

AG29

AG28

AJ30

AK29

AK30

AJ29

AE27

AF28

AF30

DDR4_SODIMM_DQ26 83 DQ26

DDR4_SODIMM_DQ27 84 DQ27

DDR4_SODIMM_DQ28 66 DQ28

DDR4_SODIMM_DQ29 67 DQ29

DDR4_SODIMM_DQ30 79 DQ30

DDR4_SODIMM_DQ31 80 DQ31

DDR4_SODIMM_DQ32 174 DQ32

DDR4_SODIMM_DQ33 173 DQ33

DDR4_SODIMM_DQ34 187 DQ34

DDR4_SODIMM_DQ35 186 DQ35

DDR4_SODIMM_DQ36 170 DQ36

DDR4_SODIMM_DQ37 169 DQ37

DDR4_SODIMM_DQ38 183 DQ38

DDR4_SODIMM_DQ39 182 DQ39

DDR4_SODIMM_DQ40 195 DQ40

DDR4_SODIMM_DQ41 194 DQ41

DDR4_SODIMM_DQ42 207 DQ42

ZCU102 Evaluation Board User Guide www.xilinx.com 26

UG1182 (v1.2) March 20, 2017

AF31

AD28

DDR4_SODIMM_DQ43 208 DQ43

DDR4_SODIMM_DQ44 191 DQ44

Chapter 3: Board Component Descriptions

Send Feedback

Table 3-3: DDR4 SODIMM Socket J1 Connections to FPGA PS DDR Bank 504 (Cont’d)

XCZU9EG

(U1) Pin

AD27

AD29

AD30

AH33

AJ34

AH34

AH32

AK34

AK33

AL32

AL31

AG33

AG34

AF32

AF33

Net Name

DDR4 SODIMM Memory J1

Pin Number Pin Name

DDR4_SODIMM_DQ45 190 DQ45

DDR4_SODIMM_DQ46 203 DQ46

DDR4_SODIMM_DQ47 204 DQ47

DDR4_SODIMM_DQ48 216 DQ48

DDR4_SODIMM_DQ49 215 DQ49

DDR4_SODIMM_DQ50 228 DQ50

DDR4_SODIMM_DQ51 229 DQ51

DDR4_SODIMM_DQ52 211 DQ52

DDR4_SODIMM_DQ53 212 DQ53

DDR4_SODIMM_DQ54 224 DQ54

DDR4_SODIMM_DQ55 225 DQ55

DDR4_SODIMM_DQ56 237 DQ56

DDR4_SODIMM_DQ57 236 DQ57

DDR4_SODIMM_DQ58 249 DQ58

DDR4_SODIMM_DQ59 250 DQ59

AD31

AD32

AD34

AD33

AN31

AP31

AP32

AP33

AM31

AM33

AM34

AL33

AN17

AM21

AK19

AH24

AH31

DDR4_SODIMM_DQ60 232 DQ60

DDR4_SODIMM_DQ61 233 DQ61

DDR4_SODIMM_DQ62 245 DQ62

DDR4_SODIMM_DQ63 246 DQ63

DDR4_SODIMM_CB0 92 CB0/NC

DDR4_SODIMM_CB1 91 CB1/NC

DDR4_SODIMM_CB2 101 CB2/NC

DDR4_SODIMM_CB3 105 CB3/NC

DDR4_SODIMM_CB4 88 CB4/NC

DDR4_SODIMM_CB5 87 CB5/NC

DDR4_SODIMM_CB6 100 CB6/NC

DDR4_SODIMM_CB7 104 CB7/NC

DDR4_SODIMM_DM0_B 12 DM0_N/DBI0_N

DDR4_SODIMM_DM1_B 33 DM1_N/DBI1_N

DDR4_SODIMM_DM2_B 54 DM2_N/DBI2_N

DDR4_SODIMM_DM3_B 75 DM3_N/DBI3_N

DDR4_SODIMM_DM4_B 178 DM4_N/DBI4_N

ZCU102 Evaluation Board User Guide www.xilinx.com 27

UG1182 (v1.2) March 20, 2017

AE30

AJ31

DDR4_SODIMM_DM5_B 199 DM5_N/DBI5_N

DDR4_SODIMM_DM6_B 220 DM6_N/DBI6_N

Chapter 3: Board Component Descriptions

Send Feedback

Table 3-3: DDR4 SODIMM Socket J1 Connections to FPGA PS DDR Bank 504 (Cont’d)

XCZU9EG

(U1) Pin

AE34

AN34

AN18

AN19

AN21

AN22

AH19

AJ19

AH22

AH23

AH28

AH29

AE28

AE29

AJ32

Net Name

DDR4 SODIMM Memory J1

Pin Number Pin Name

DDR4_SODIMM_DM7_B 241 DM7_N/DBI7_N

DDR4_SODIMM_DM8_B 96 DM8_N/DBI8_N/NC

DDR4_SODIMM_DQS0_T 13 DQS0_T

DDR4_SODIMM_DQS0_C 11 DQS0_C

DDR4_SODIMM_DQS1_T 34 DQS1_T

DDR4_SODIMM_DQS1_C 32 DQS1_C

DDR4_SODIMM_DQS2_T 55 DQS2_T

DDR4_SODIMM_DQS2_C 53 DQS2_C

DDR4_SODIMM_DQS3_T 76 DQS3_T

DDR4_SODIMM_DQS3_C 74 DQS3_C

DDR4_SODIMM_DQS4_T 179 DQS4_T

DDR4_SODIMM_DQS4_C 177 DQS4_C

DDR4_SODIMM_DQS5_T 200 DQS5_T

DDR4_SODIMM_DQS5_C 198 DQS5_C

DDR4_SODIMM_DQS6_T 221 DQS6_T

AK32

AE32

AE33

AN32

AN33

AN27

AN26

AL27

AL26

AN29

AJ27

AM30

AJ26

AM24

AK24

AK25

AG25

DDR4_SODIMM_DQS6_C 219 DQS6_C

DDR4_SODIMM_DQS7_T 242 DQS7_T

DDR4_SODIMM_DQS7_C 240 DQS7_C

DDR4_SODIMM_DQS8_T 97 DQS8_T

DDR4_SODIMM_DQS8_C 95 DQS8_C

DDR4_SODIMM_CK0_C 139 CK0_C

DDR4_SODIMM_CK0_T 137 CK0_T

DDR4_SODIMM_CK1_C 140 CK1_C/NF

DDR4_SODIMM_CK1_T 138 CK1_T/NF

DDR4_SODIMM_CKE0 109 CKE0

DDR4_SODIMM_CKE1 110 CKE1

DDR4_SODIMM_ODT0 155 ODT0

DDR4_SODIMM_ODT1 161 ODT1

DDR4_SODIMM_RAS_B 152 RAS_N/A16

DDR4_SODIMM_CAS_B 156 CAS_N/A15

DDR4_SODIMM_WE_B 151 WE_N/A14

DDR4_SODIMM_ACT_B 114 ACT_N

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UG1182 (v1.2) March 20, 2017

AF22

AF20

DDR4_SODIMM_ALERT_B 116 ALERT_N

DDR4_SODIMM_PARITY 143 PARITY

Chapter 3: Board Component Descriptions

Send Feedback

Table 3-3: DDR4 SODIMM Socket J1 Connections to FPGA PS DDR Bank 504 (Cont’d)

XCZU9EG

(U1) Pin

AN28

AL30

Net Name

DDR4_SODIMM_CS0_B 149 CS0_N

DDR4_SODIMM_CS1_B 157 CS1_N

DDR4 SODIMM Memory J1

Pin Number Pin Name

The ZCU102 DDR4 SODIMM interface adheres to the constraints guidelines documented in
the PCB Guidelines for DDR4 section of UltraScale Architecture PCB Design Guide (UG583)

[Ref 3] The ZCU102 DDR4 SODIMM interface is a 40Ω impedance implementation. Other

memory interface details are also available in the UltraScale Architecture FPGAs Memory
Interface Solutions Guide (PG150) [Ref 4].

DDR4 Component Memory

[Figure 2-1, callout 3]

The 4 Gb, 16-bit wide DDR4 memory system is comprised of one 256 Mb x 16 SDRAM
(Micron MT40A256M16GE-075E) at U2. This memory system is connected to the PL-side
XCZU9EG bank 64. The DDR4 0.6V VTT termination voltage is supplied from sink-source
regulator U35. The connections between the DDR4 memory and XCZU9EG bank 64 are
listed in Table 3-4.

Table 3-4: DDR4 Component Memory Connection to the XCZU9EG MPSoC

XCZU9EG

(U1) Pin

AM8

AM9

AP8

AN8

AK10

AJ10

AP9

AN9

AP10

AP11

AM10

AL10

AM11

AL11

Net Name I/O Standard

DDR4_A0 SSTL12_DCI P3 A0

DDR4_A1 SSTL12_DCI P7 A1

DDR4_A2 SSTL12_DCI R3 A2

DDR4_A3 SSTL12_DCI N7 A3

DDR4_A4 SSTL12_DCI N3 A4

DDR4_A5 SSTL12_DCI P8 A5

DDR4_A6 SSTL12_DCI P2 A6

DDR4_A7 SSTL12_DCI R8 A7

DDR4_A8 SSTL12_DCI R2 A8

DDR4_A9 SSTL12_DCI R7 A9

DDR4_A10 SSTL12_DCI M3 A10/AP

DDR4_A11 SSTL12_DCI T2 A11

DDR4_A12 SSTL12_DCI M7 A12/BC_B

DDR4_A13 SSTL12_DCI T8 A13

DDR4 Component Memory

Pin Number Pin Name

ZCU102 Evaluation Board User Guide www.xilinx.com 29

UG1182 (v1.2) March 20, 2017

AK12

DDR4_BA0 SSTL12_DCI N2 BA0

Chapter 3: Board Component Descriptions

Send Feedback

Table 3-4: DDR4 Component Memory Connection to the XCZU9EG MPSoC (Cont’d)

XCZU9EG

(U1) Pin

AJ12

AK7

AJ7

AJ9

AL5

AN7

AP7

AM3

AK8

AP1

AH9

AK9

AP2

AK4

AK5

Net Name I/O Standard

DDR4 Component Memory

Pin Number Pin Name

DDR4_BA1 SSTL12_DCI N8 BA1

DDR4_BG0 SSTL12_DCI M2 BG0

DDR4_A14_WE_B SSTL12_DCI L2 WE_B/A14

DDR4_A16_RAS_B SSTL12_DCI L8 RAS_B/A16

DDR4_A15_CAS_B SSTL12_DCI M8 CAS_B/A15

DDR4_CK_T DIFF_SSTL12 K7 CK_T

DDR4_CK_C DIFF_SSTL12 K8 CK_C

DDR4_CKE SSTL12_DCI K2 CKE

DDR4_ACT_B SSTL12_DCI L3 ACT_B

DDR4_PAR SSTL12_DCI T3 PAR

DDR4_RESET_B_LS LVCMOS18 P1 RESET_B

DDR4_ODT SSTL12_DCI K3 ODT

DDR4_CS_B SSTL12_DCI L7 CS_B

DDR4_DQ0 POD12_DCI G2 DQL0

DDR4_DQ1 POD12_DCI F7 DQL1

AN4

AM4

AP4

AP5

AM5

AM6

AK2

AK3

AL1

AK1

AN1

AM1

AP3

AN3

AN6

AP6

AL3

DDR4_DQ2 POD12_DCI H3 DQL2

DDR4_DQ3 POD12_DCI H7 DQL3

DDR4_DQ4 POD12_DCI H2 DQL4

DDR4_DQ5 POD12_DCI H8 DQL5

DDR4_DQ6 POD12_DCI J3 DQL6

DDR4_DQ7 POD12_DCI J7 DQL7

DDR4_DQ8 POD12_DCI A3 DQU0

DDR4_DQ9 POD12_DCI B8 DQU1

DDR4_DQ10 POD12_DCI C3 DQU2

DDR4_DQ11 POD12_DCI C7 DQU3

DDR4_DQ12 POD12_DCI C2 DQU4

DDR4_DQ13 POD12_DCI C8 DQU5

DDR4_DQ14 POD12_DCI D3 DQU6

DDR4_DQ15 POD12_DCI D7 DQU7

DDR4_DQS0_T DIFF_POD12 G3 DQSL_T

DDR4_DQS0_C DIFF_POD12 F3 DQSL_C

DDR4_DQS1_T DIFF_POD12 B7 DQSU_T

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UG1182 (v1.2) March 20, 2017

AL2

DDR4_DQS1_C DIFF_POD12 A7 DQSU_C