ZC706 Evaluation Board
for the Zynq-7000
XC7Z045
All Programmable SoC
User Guide
UG954 (v1.5) September 10, 2015
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included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective
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; IP cores may be
.
Revision History
The following table shows the revision history for this document.
Date Version Revision
10/08/2012 1.0
11/21/2012 1.1
Initial Xilinx release.
Added additional user LED in ZC706 Evaluation Board Features section, Ta bl e 1- 1,
User I/O section, Figure 1-25, and Tab le 1- 28 . In Tab le 1- 1, added fan sink
information and updated notes for 10/100/1000 Ethernet PHY, user pushbuttons,
user DIP switch, and FPGA PROG pushbutton. Added Encryption Key Backup Circuit
section. Updated second paragraph in DDR3 SODIMM Memory (PL) section.
Updated second paragraph in SD Card Interface section. Updated Tab le 1- 11 .
Added U53 information to first paragraph in HDMI Video Output section. Added
fourth bullet to Real T ime Clock (RTC) section. Updated Figure 1-23. Added pin A17
to Tab le 1- 28 . Updated Figure 1-32. Replaced UCF in Appendix C. Added additional
reference to References in Appendix F.
ZC706 Evaluation Board User Guide www.xilinx.com 2
UG954 (v1.5) September 10, 2015
Date Version Revision
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04/24/2013 1.2
07/31/2013 1.3
04/28/2015 1.4
Chapter 1, ZC706 Evaluation Board Features: Tab le 1-1 feature descriptions are now
linked to their respective sections in the book. Figure 1-2, Figure 1-33, and
Figure 1-34 were replaced. Table 1-2 was removed because it was a duplicate of
Tab le 1-1 1. Tab le 1- 2: Switch SW11 Configuration Option Settings was added. FMC
Connector JTAG Bypass, page 33 was updated. Default lane size information below
Figure 1-17 was changed. Figure 1-18 PCI Express Lane Size Select Jumper J19 was
added. The names of pins 18 and 19 changed in Tabl e 1-1 7. The address of I
PMBUS_DATA/CLOCK changed in Tab le 1- 25 . Reference designator DS35 was added
to Ta bl e 1 -2 7. Callout numbers in the User I/O, page 57 section are now linked to
Tab le 1-1 . SW13 information was added to the section User Pushbuttons, page 59.
In Tab le 1-3 3, J5 pin H22 changed to XC7Z045 (U1) pin AH26 and H23 changed to
AH27. The section ZC706 Board Power System, page 72 was added. Voltage levels
were changed in VADJ Voltage Control, page 79. Tab le 1-3 7 was modified and
Tab le 1-3 8 was added.
Appendix A, Default Switch and Jumper Settings: The SW11 selection in Ta bl e A- 1
changed.
Appendix G, Regulatory and Compliance Information: A link to the master answer
record was added.
Updated Tabl e 1- 22 . Replaced the master User Constraints File (UCF) list in
Appendix C, Master Constraints File Listing with the master Xilinx Design
Constraints (XDC) list. Updated references throughout the document.
Updated “LMZ22000 Family Regulator Description” to LMZ31500 and LMZ31700
Family Regulator Description. Updated Ta bl e 1 -4, Tab le 1-7 , Tab le 1-1 3, Tab le 1- 23 ,
Tab le 1-2 8 through Ta bl e 1 -3 0, Ta bl e 1- 32 through Tab le 1-3 4, Tab le 1-3 6, and
Tab le A-2 . Added Figure A-1. Updated Appendix C, Master Constraints File Listing.
2
C bus
09/10/2015 1.5
Updated J48 header jumper setting (third row in Tab le 1 -7 ).
ZC706 Evaluation Board User Guide www.xilinx.com 3
UG954 (v1.5) September 10, 2015
Table of Contents
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Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 1: ZC706 Evaluation Board Features
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ZC706 Evaluation Board Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Feature Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Zynq-7000 XC7Z045 AP SoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Encryption Key Backup Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
I/O Voltage Rails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
DDR3 SODIMM Memory (PL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
DDR3 Component Memory (PS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Quad-SPI Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
USB 2.0 ULPI Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
SD Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Programmable Logic JTAG Programming Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Programmable Logic JTAG Select Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
FMC Connector JTAG Bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Programmable User Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
User SMA Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Processing System Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
GTX SMA Clock (SMA_MGT_REFCLK_P and SMA_MGT_REFCLK_N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Jitter Attenuated Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
GTX Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
PCI Express Endpoint Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
SFP/SFP+ Module Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
10/100/1000 Mb/s Tri-Speed Ethernet PHY (PL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Ethernet PHY Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
USB-to-UART Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
HDMI Video Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Real Time Clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Status and User LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Ethernet PHY User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
User I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
User Pushbuttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
GPIO DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
User PMOD GPIO Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
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Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
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Power On/Off Slide Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Program_B Pushbutton . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
PS Power-On and System Reset Pushbuttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
FPGA Mezzanine (FMC) Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
HPC Connector J37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
LPC Connector J5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
ZC706 Board Power System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
UCD90120A Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
LMZ31500 and LMZ31700 Family Regulator Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
XADC Power System Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
VADJ Voltage Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
AP SoC Programmable Logic (PL) Voltage Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Monitoring Voltage and Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Cooling Fan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
XADC Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Appendix A: Default Switch and Jumper Settings
Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Appendix B: VITA 57.1 FMC Connector Pinouts
Appendix C: Master Constraints File Listing
ZC706 Evaluation Board XDC Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Appendix D: Board Setup
Installing the ZC706 Board in a PC Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Appendix E: Board Specifications
Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Environmental . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Humidity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Operating Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Appendix F: Additional Resources
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Appendix G: Regulatory and Compliance Information
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Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Declaration of Conformity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
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Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
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ZC706 Evaluation Board Features
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Overview
The ZC706 evaluation board for the XC7Z045 All Programmable SoC (AP SoC) provides a
hardware environment for developing and evaluating designs targeting the Zynq®-7000
XC7Z045-2FFG900C AP SoC. The ZC706 evaluation board provides features common to
many embedded processing systems, including DDR3 SODIMM and component memory, a
four-lane PCI Express® interface, an Ethernet PHY, general purpose I/O, and two UART
interfaces. Other features can be supported using VITA-57 FPGA mezzanine cards (FMC)
attached to the low pin count (LPC) FMC and high pin count (HPC) FMC connectors.
ZC706 Evaluation Board Features
Chapter 1
The ZC706 evaluation board features are listed in here. Detailed information for each
feature is provided in Feature Descriptions starting on page 14.
• Zynq-7000 XC7Z045-2FFG900C AP SoC
• 1 GB DDR3 memory SODIMM on the programmable logic (PL) side
• 1 GB DDR3 component memory (four [256 Mb x 8] devices) on the processing system
(PS) side
• Two 128 Mb Quad-SPI (QSPI) flash memory (Dual Quad-SPI)
• USB 2.0 ULPI (UTMI+ low pin interface) transceiver with micro-B USB connector
• Secure Digital (SD) connector
• USB JTAG interface via Digilent module with micro-B USB connector
• Clock sources:
Fixed 200 MHz LVDS oscillator (differential)
°
I2C programmable LVDS oscillator (differential)
°
Fixed 33.33 MHz LVCMOS oscillator (single-ended)
°
Subminiature version A (SMA) connectors (differential)
°
ZC706 Evaluation Board User Guide www.xilinx.com 7
UG954 (v1.5) September 10, 2015
SMA connectors for GTX transceiver clocking (differential)
°
•GTX transceivers
Send Feedback
FMC HPC connector (eight GTX transceivers)
°
FMC LPC connector (one GTX transceiver)
°
SMA connectors (one pair each for TX, RX and REFCLK)
°
PCI Express (four lanes)
°
Small form-factor pluggable plus (SFP+) connector
°
Ethernet PHY RGMII interface
°
• PCI Express endpoint connectivity
Gen1 4-lane (x4)
°
Gen2 4-lane (x4)
°
• SFP+ Connector
• Ethernet PHY RGMII interface with RJ-45 connector
Overview
• USB-to-UART bridge with mini-B USB connector
• HDMI codec with HDMI connector
I2C bus
•
I2C bus multiplexed to:
•
Si570 user clock
°
ADV7511 HDMI codec
°
M24C08 EEPROM (1 kB)
°
1-to-16 TCA6416APWR port expander
°
DDR3 SODIMM
°
RTC-8564JE real time clock
°
FMC HPC connector
°
FMC LPC connector
°
PMBUS data/clock
°
•Status LEDs:
ZC706 Evaluation Board User Guide www.xilinx.com 8
UG954 (v1.5) September 10, 2015
Ethernet status
°
TI Power Good
°
Linear Power Good
°
PS DDR3 Component Vtt Good
°
PL DDR3 SODIMM Vtt Good
°
FMC Power Good
Send Feedback
°
12V Input Power On
°
FPGA INIT
°
FPGA DONE
°
•User I/O:
Four (PL) user LEDs
°
Three (PL) user pushbuttons
°
One (PL) user DIP switch (4-pole)
°
Two Dual row Pmod GPIO headers
°
• AP SoC PS Reset Pushbuttons:
SRST_B PS reset button
°
POR_B PS reset button
°
Overview
• VITA 57.1 FMC HPC connector
• VITA 57.1 FMC LPC connector
• Power on/off slide switch
•Program_B pushbutton
• Power management with PMBus voltage and current monitoring through TI power
controller
• Dual 12-bit 1 MSPS XADC analog-to-digital front end
• Configuration options:
Dual Quad-SPI flash memory
°
USB JTAG configuration port (Digilent module)
°
Platform cable header JTAG configuration port
°
20-pin PL PJTAG header
°
ZC706 Evaluation Board User Guide www.xilinx.com 9
UG954 (v1.5) September 10, 2015
X-Ref Target - Figure 1-1
U1
Zync-7000 AP SoC
XC7Z045-2FFG900C
Processing
System
Programmable Logic
UG954_c1_01_1002012
JTAG Module
and
JTAG Header
Page 16
Dual Quad-SPI
Flash Memory
Page 21
PCIe
x 4-Lane
Page 42
SD Card
Connector
Page 22
FMC HPC
Connector
Pages 24-27
10/100/1,000
Ethernet PHY
(RGMII only)
Page 29, 30
USB 2.0 ULPI
Transceiver
and Connector
Page 31
Clock and
Reset/POR
Pushbuttons
Pages 15, 34
USB UART
and
Connector
Page 40
ARM PJTAG
Header
Page 39
Switches
LEDs and
Pushbuttons
Page 38
Mechanicals
Page 58
I2C
Real Time
Clock
Page 37
DDR3
SODIMM
Page 23
DDR3 Memory
4 x 256 Mb x 8
SDRAM
Pages 17-20
HDMI Codec
and
Connector
Pages 32, 33
I2C Multiplexer
and
I2C EEPROM
Page 36
XADC
Header
Page 35
Configurable
Clocks
Page 34
FMC LPC
Connector
Page 28
Note: Page numbers reference the page number of schematic 0381513.
Send Feedback
Overview
Block Diagram
The ZC706 evaluation board block diagram is shown in Figure 1-1.
Figure 1-1: ZC706 Evaluation Board Block Diagram
Board Layout
Figure 1-2 shows the ZC706 evaluation board. Each numbered feature that is referenced in
Figure 1-2 is described in Tab le 1- 1 with a link to detailed information provided under
Feature Descriptions starting on page 14.
Note: The image in Figure 1-2 is for reference only and might not reflect the current revision of the
board.
CAUTION! The ZC706 evaluation board can be damaged by electrostatic discharge (ESD). Follow ESD
prevention measures when handling the board.
ZC706 Evaluation Board User Guide www.xilinx.com 10
UG954 (v1.5) September 10, 2015
X-Ref Target - Figure 1-2
17
6
30
31
21
18
15
2
11
13
12
1
4
7
3
9
10
16
25
24
26
22
33
27
19
32
23
28
14
35
29
5
8
20
34
36
37
38
00
Square callout references a component
on the back side of the board
Round callout references a component
on the front side of the board
00
UG954_c1_02_042114
Send Feedback
Overview
Figure 1-2: ZC706 Evaluation Board Component Locations
Table 1-1: ZC706 Evaluation Board Component Descriptions
Callout Feature Notes
1
2
3
4
5
6
7
Zynq-7000 XC7Z045 AP SoC, page 14
Zynq-7000 All Programmable SoC with fan sink
DDR3 SODIMM Memory (PL), page 18
DDR3 SODIMM Memory Socket (J1)
DDR3 Component Memory (PS), page 22
DDR3 Memory 1GB (4x256M U2-U5)
Quad-SPI Flash Memory, page 25
Dual Quad-SPI Flash (128Mb) (U58-U59)
SD Card Interface, page 29
SD Card Interface Connector (J30)
USB 2.0 ULPI Transceiver, page 27
USB JTAG Interface w/Micro-B Connector (U30)
System Clock, page 34
System Clock, 2.5V LVDS (U64)
XC7Z045T-2FFG900C with Radian
INC3001-7_1.5BU_LI98 fan sink
Micron MT8JTF12864HZ-1G6G1
Micron MT41J256M8HX-15E
Spansion S25FL128SAGMFIR01
Molex 67840-8001
Digilent USB JTAG Module
SiTime SIT9102-243N25E200.0000
Schematic
0381513
Page Number
23
17-20
21
22
16
34
ZC706 Evaluation Board User Guide www.xilinx.com 11
UG954 (v1.5) September 10, 2015
Table 1-1: ZC706 Evaluation Board Component Descriptions (Cont’d)
Send Feedback
Callout Feature Notes
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Programmable User Clock, page 35
2
I
C Prog. User Clock 3.3V LVDS (U37, bottom of
board)
User SMA Clock Source, page 36
User Differential SMA Clock P/N (J67/J68)
GTX SMA Clock (SMA_MGT_REFCLK_P and
SMA_MGT_REFCLK_N), page 37
GTX Differential SMA Clock P/N (J36/J31)
Jitter Attenuated Clock, page 38
Jitter Attenuated Clock (U60, bottom of board)
GTX Transceivers, page 39
GTX Transceivers
PCI Express Endpoint Connectivity, page 44
PCI Express Connector (P4)
SFP/SFP+ Module Connector, page 46
SFP/SFP+ Module Connector (P2)
10/100/1000 Mb/s Tri-Speed Ethernet PHY (PL),
page 47
RGMII only 10/100/1000 Mb/s Ethernet PHY
w/RJ45 (U51, P3)
GTX Differential SMA TX and RX P/N
(J35/J34and J32/J33)
USB-to-UART Bridge, page 49
USB-to-UART Bridge with Mini-B Connector
(U52, J21)
HDMI Video Output, page 50
HDMI Controller (U53), HDMI Video Connector
(P1)
USB 2.0 ULPI Transceiver, page 27
USB 2.0 ULPI Controller w/ Micro-B Connector
(U12, J2)
I2C Bus, page 53
2
C Bus MUX (U65, bottom of board)
I
Ethernet PHY User LEDs, page 57
Ethernet PHY Status LEDs (DS28-DS30)
User LEDs, page 58
User LEDs (DS8-DS10, DS35)
User Pushbuttons, page 59
User pushbuttons, active-High (SW7, 9, 8)
Silicon Labs SI570BAB0000544DG,
default 156.250 MHz
Rosenberger 32K10K-400L5
Rosenberger 32K10K-400L5
Silicon Labs SI5324C-C-GM
Embedded within AP SoC U1
4-lane card edge connector
Molex 74441-0010
Marvell 88E1116RA0-NNC1C000
Rosenberger 32K10K-400L5
Silicon Labs CP2103GM bridge
Analog Devices ADV7511KSTZ-P,
Molex 500254-1927,
SMSC USB3320C-EZK
TI PCA9548ARGER
EPHY status LED, GREEN single-stack
GPIO LEDs, GREEN 0603
E-Switch TL3301EF100QG in Left,
Center, Right pattern
Overview
Schematic
0381513
Page Number
34
44
44
43
8
42
41
29
44
40
32, 33
31
36
29
38
38
ZC706 Evaluation Board User Guide www.xilinx.com 12
UG954 (v1.5) September 10, 2015
Table 1-1: ZC706 Evaluation Board Component Descriptions (Cont’d)
Send Feedback
Callout Feature Notes
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
GPIO DIP Switch, page 60
4-pole C&K SDA04H1SBD
GPIO DIP Switch (SW12)
ARM® core PJTAG Header (J64) 2x10 0.1inch male header, Samtec
TST-110-01-G-D
User PMOD GPIO Headers, page 60
2x6 0.1 inch male header
PMOD Headers (J57, J58)
Power On/Off Slide Switch, page 62
C&K 1201M2S3AQE2
Power On/Off Switch (SW1)
Program_B Pushbutton, page 63
E-Switch TL3301EF100QG
FPGA PROG pushbutton (SW10)
AP SoC MIO Config. DIP Switch (SW11) 5-pole DPDT CTS 206-125 15
HPC Connector J37, page 65
Samtec ASP_134486_01
FMC HPC connector (J37)
LPC Connector J5, page 69
Samtec ASP_134603_01
FMC LPC connector (J5)
Power Management, page 77
Power Management System (top and bottom of
TI UCD90120ARGC in conjunction
w/various regulators
board)
XADC Analog-to-Digital Converter, page 83
XADC Connector (J63)
Programmable Logic JTAG Select Switch,
2x10 0.1inch male header, Samtec
TST-110-01-G-D
2-pole C&K SDA02H1SBD
page 31
JTAG Configuration DIP Switch (SW4)
JTAG Flying Lead Header (J62) 2x10 0.1inch male header, Samtec
TST-110-01-G-D
2x5 shrouded PMBus connector J4 ASSMAN HW10G-0202 48
2x7 2mm shrouded JTAG cable connector J3 MOLEX 87832-1420 16
12V power input 2x6 connector J22 MOLEX-39-30-1060 48
Overview
Schematic
0381513
Page Number
38
39
37, 39
48
38
24-27
28
48-57
35
16
16
Notes:
1. Jumper header locations are identified in Appendix A, Default Switch and Jumper Settings.
ZC706 Evaluation Board User Guide www.xilinx.com 13
UG954 (v1.5) September 10, 2015
Feature Descriptions
Application
Processor Unit (APU)
Common
Peripherals
Custom
Peripherals
Common Accelerators
Custom Accelerators
Memory
Interfaces
Processing
System
(PS)
Programmable
Logic
(PL)
Input Output
Peripherals
(IOP)
High-Bandwidth
AMBA
®
AXI Interfaces
UG954_c1_03_100112
Interconnect
Send Feedback
Feature Descriptions
Detailed information for each feature shown in Figure 1-2 and listed in Table 1 -1 is
provided in this section.
Zynq-7000 XC7Z045 AP SoC
[Figure 1-2, callout 1]
The ZC706 evaluation board is populated with the Zynq-7000 XC7Z045-2FFG900C AP SoC.
The XC7Z045 AP SoC consists of an integrated processing system (PS) and programmable
logic (PL), on a single die. The high-level block diagram is shown in Figure 1-3.
X-Ref Target - Figure 1-3
ZC706 Evaluation Board User Guide www.xilinx.com 14
UG954 (v1.5) September 10, 2015
Figure 1-3: High-Level Block Diagram
The PS integrates two ARM® Cortex™-A9 MPCore™ application processors, AMBA®
interconnect, internal memories, external memory interfaces, and peripherals including
USB, Ethernet, SPI, SD/SDIO,
and boots at power-up or reset.
A system level block diagram is shown in Figure 1-4.
I2C, CAN, UART, and GPIO. The PS runs independently of the PL
X-Ref Target - Figure 1-4
2x USB
2x GigE
2x SD
Zynq-7000 AP SoC
I/O
Peripherals
IRQ
IRQ
EMIO
SelectIO
Resources
DMA 8
Channel
CoreSight
Components
Programmable Logic
DAP
DevC
SWDT
DMA
Sync
Notes:
1) Arrow direction shows control (master to slave)
2) Data flows in both directions: AXI 32-Bit/64-Bit, AXI 64-Bit, AXI 32-Bit, AHB 32-Bit, APB 32-Bit, Custom
ACP
256K
SRAM
Application Processor Unit
TTC
System-
Level
Control
Regs
GigE
CAN
SD
SDIO
UART
GPIO
UART
CAN
I2C
SRAM/
NOR
ONFI 1.0
NAND
Processing System
Memory
Interfaces
Q-SPI
CTRL
USB
GigE
I2C
USB
SD
SDIO
SPI
SPI
Programmable Logic to
Memory Interconnect
MMU
FPU and NEON Engine
Snoop Controller, AWDT, Timer
GIC
32 KB
I-Cache
ARM Cortex-A9
CPU
ARM Cortex-A9
CPU
MMU
FPU and NEON Engine
Config
AES/
SHA
XADC
12-Bit ADC
Memory
Interfaces
512 KB L2 Cache & Controller
OCM
Interconnect
DDR2/3,
LPDDR2
Controller
UG954_c1_04_100112
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
MIO
Clock
Generation
Reset
Central
Interconnect
General-Purpose
Por ts
High-Performance Ports
Send Feedback
Feature Descriptions
For additional information on Zynq-7000 SoC devices, see Zynq-7000 All Programmable
SoC Overview (DS190
(UG585
).
Figure 1-4: Zynq-7000 Block Diagram
) and Zynq-7000 All Programmable SoC Technical Reference Manual
Device Configuration
the Zynq-7000 XC7Z045 AP SoC uses a multi-stage boot process that supports both a
non-secure and a secure boot. The PS is the master of the boot and configuration process.
For a secure boot, the PL must be powered on to enable the use of the security block
located within the PL, which provides 256-bit AES and SHA decryption/authentication.
The ZC706 evaluation board supports these configuration options:
• PS Configuration: Quad-SPI flash memory
ZC706 Evaluation Board User Guide www.xilinx.com 15
UG954 (v1.5) September 10, 2015
• PS Configuration: Processor System Boot from SD Card (J30)
Feature Descriptions
Send Feedback
• PL Configuration: USB JTAG configuration port (Digilent module U30)
• PL Configuration: Platform cable header J3 and flying lead header J62 JTAG
configuration ports
TIP: Designs using serial configuration based on Quad-SPI flash memory can take advantage of
low-cost commodity SPI flash memory.
The JTAG configuration option is selected by setting SW11 (PS) as shown in Tab le 1 -2 and
SW4 (PL) as described in Programmable Logic JTAG Programming Options, page 31. SW11
is callout 29 in Figure 1-2.
Table 1-2: Switch SW11 Configuration Option Settings
Boot Mode SW11.1 SW11.2 SW11.3 SW11.4 SW11.5
JTAG mode
(1)
00000
Independent JTAG mode
QSPI mode
SD mode
MIO configuration pin
Notes:
1. Default switch setting
10000
00010
00110
MIO2 MIO3 MIO4 MIO5 MIO6
For more information about Zynq-7000 AP SoC configuration settings, see Zynq-7000 All
Programmable SoC Technical Reference Manual (UG585
).
Encryption Key Backup Circuit
The XC7Z045 AP SoC U1 implements bitstream encryption key technology. The ZC706
board provides the encryption key backup battery circuit shown in Figure 1-5. The Seiko
TS518FE rechargeable 1.5V lithium button-type battery B2 is soldered to the board with the
positive output connected to the XC7Z045 AP SoC U1 VCCBATT pin P9. The battery supply
current IBATT specification is 150 nA max when board power is off. B2 is charged from the
VCCAUX 1.8V rail through a series diode with a typical forward voltage drop of 0.38V and
4.7 K
Ω current limit resistor. The nominal charging voltage is 1.42V.
ZC706 Evaluation Board User Guide www.xilinx.com 16
UG954 (v1.5) September 10, 2015
X-Ref Target - Figure 1-5
Send Feedback
To XC7Z045 AP SoC
U1 Pin P9
(VCCBATT)
D7
40V
200 mW
FPGA_VBATT
B2
Feature Descriptions
NC
1
VCCAUX
3
BAS40-04
2
R9
4.70K 1%
1/16W
1
+
Lithium Battery
Seiko
TS518SE_FL35E
1.5V
2
GND
UG954_c1_05_041113
Figure 1-5: Encryption Key Backup Circuit
I/O Voltage Rails
There are eleven I/O banks available on the XC7Z045 AP SoC. The voltages applied to the
XC7Z045 AP SoC I/O banks used by the ZC706 evaluation board are listed in Tab le 1 -3.
Table 1-3: I/O Voltage Rails
XC7Z045 (U1)
Bank
PL Bank 0 VCC3V3_FPGA 3.3V AP SoC Configuration Bank 0
PL Bank 9
PL Bank 10 FMC_LPC, PL_JTAG,GPIO
PL Bank 11 FMC_HPC, GPIO_LED, HDMI
PL Bank 12 FMC_LPC, HDMI
PL Bank 13 FMC_HPC, HDMI
Net Name Voltage Connected To
PMOD, USER_SMA_CLOCK, SM_FAN, REC_CLOCK,
SFP_TX_DISABLE
VADJ_FPGA 2.5V
ZC706 Evaluation Board User Guide www.xilinx.com 17
UG954 (v1.5) September 10, 2015
PL Bank 33
PL Bank 34 PL_DDR3_A, SYSCLK
VCC1V5_PL 1.5V
PL_DDR3_D[31:0]
PL Bank 35 PL_DDR3_D[63:32], XADC
Table 1-3: I/O Voltage Rails (Cont’d)
Send Feedback
Feature Descriptions
XC7Z045 (U1)
Bank
PS Bank 500
PS Bank 501 PHY_IF,SDIO_IF,USB_IF
PS Bank 502 PS_DDR3_IF
Notes:
1. The ZC706 evaluation board is shipped with V
Net Name Voltage Connected To
QSPI0,QSPI1
VCCP1V8 1.8V
set to 2.5V.
ADJ
DDR3 SODIMM Memory (PL)
[Figure 1-2, callout 2]
The memory module at J1 is a 1 GB DDR3 small outline dual-inline memory module
(SODIMM). It provides volatile synchronous dynamic random access memory (SDRAM) for
storing user code and data.
• Part number: MT8JTF12864HZ-1G6G1 (Micron Technology)
• Supply voltage: 1.5V
• Datapath width: 64 bits
• Data rate: Up to 1,600 MT/s
The DDR3 interface is implemented across the PL-side I/O banks. Bank 33 and bank 35 have
a dedicated DCI VRP/N resistor connection. An external 0.75V reference VTTREF_SODIMM is
provided for data interface banks. Any interface connected to these banks that requires the
VTTREF voltage must use this FPGA voltage reference. The connections between the DDR3
memory and the AP SoC are listed in Tab le 1- 4.
Table 1-4: DDR3 SODIMM Socket J1 Connections to the XC7Z045 AP SoC
XC7Z045 (U1)
Pin
E10 PL_DDR3_A0 SSTL15 98 A0
B9 PL_DDR3_A1 SSTL15 97 A1
E11 PL_DDR3_A2 SSTL15 96 A2
A9 PL_DDR3_A3 SSTL15 95 A3
D11 PL_DDR3_A4 SSTL15 92 A4
B6 PL_DDR3_A5 SSTL15 91 A5
F9 PL_DDR3_A6 SSTL15 90 A6
E8 PL_DDR3_A7 SSTL15 86 A7
B10 PL_DDR3_A8 SSTL15 89 A8
Net Name I/O Standard
DDR3 SODIMM Memory J1
Pin Number Pin Name
ZC706 Evaluation Board User Guide www.xilinx.com 18
UG954 (v1.5) September 10, 2015
J8 PL_DDR3_A9 SSTL15 85 A9
Feature Descriptions
Send Feedback
Table 1-4: DDR3 SODIMM Socket J1 Connections to the XC7Z045 AP SoC (Cont’d)
XC7Z045 (U1)
Pin
D6 PL_DDR3_A10 SSTL15 107 A10/AP
B7 PL_DDR3_A11 SSTL15 84 A11
H12 PL_DDR3_A12 SSTL15 83 A12_BC_N
A10 PL_DDR3_A13 SSTL15 119 A13
G11 PL_DDR3_A14 SSTL15 80 A14
C6 PL_DDR3_A15 SSTL15 78 A15
F8 PL_DDR3_BA0 SSTL15 109 BA0
H7 PL_DDR3_BA1 SSTL15 108 BA1
A7 PL_DDR3_BA2 SSTL15 79 BA2
L1 PL_DDR3_D0 SSTL15 5 DQ0
L2 PL_DDR3_D1 SSTL15 7 DQ1
K5 PL_DDR3_D2 SSTL15 15 DQ2
J4 PL_DDR3_D3 SSTL15 17 DQ3
K1 PL_DDR3_D4 SSTL15 4 DQ4
L3 PL_DDR3_D5 SSTL15 6 DQ5
J5 PL_DDR3_D6 SSTL15 16 DQ6
K6 PL_DDR3_D7 SSTL15 18 DQ7
Net Name I/O Standard
DDR3 SODIMM Memory J1
Pin Number Pin Name
G6 PL_DDR3_D8 SSTL15 21 DQ8
H4 PL_DDR3_D9 SSTL15 23 DQ9
H6 PL_DDR3_D10 SSTL15 33 DQ10
H3 PL_DDR3_D11 SSTL15 35 DQ11
G1 PL_DDR3_D12 SSTL15 22 DQ12
H2 PL_DDR3_D13 SSTL15 24 DQ13
G5 PL_DDR3_D14 SSTL15 34 DQ14
G4 PL_DDR3_D15 SSTL15 36 DQ15
E2 PL_DDR3_D16 SSTL15 39 DQ16
E3 PL_DDR3_D17 SSTL15 41 DQ17
D4 PL_DDR3_D18 SSTL15 51 DQ18
E5 PL_DDR3_D19 SSTL15 53 DQ19
F4 PL_DDR3_D20 SSTL15 40 DQ20
F3 PL_DDR3_D21 SSTL15 42 DQ21
D1 PL_DDR3_D22 SSTL15 50 DQ22
D3 PL_DDR3_D23 SSTL15 52 DQ23
A2 PL_DDR3_D24 SSTL15 57 DQ24
B2 PL_DDR3_D25 SSTL15 59 DQ25
ZC706 Evaluation Board User Guide www.xilinx.com 19
UG954 (v1.5) September 10, 2015
Feature Descriptions
Send Feedback
Table 1-4: DDR3 SODIMM Socket J1 Connections to the XC7Z045 AP SoC (Cont’d)
XC7Z045 (U1)
Pin
B4 PL_DDR3_D26 SSTL15 67 DQ26
B5 PL_DDR3_D27 SSTL15 69 DQ27
A3 PL_DDR3_D28 SSTL15 56 DQ28
B1 PL_DDR3_D29 SSTL15 58 DQ29
C1 PL_DDR3_D30 SSTL15 68 DQ30
C4 PL_DDR3_D31 SSTL15 70 DQ31
K10 PL_DDR3_D32 SSTL15 129 DQ32
L9 PL_DDR3_D33 SSTL15 131 DQ33
K12 PL_DDR3_D34 SSTL15 141 DQ34
J9 PL_DDR3_D35 SSTL15 143 DQ35
K11 PL_DDR3_D36 SSTL15 130 DQ36
L10 PL_DDR3_D37 SSTL15 132 DQ37
J10 PL_DDR3_D38 SSTL15 140 DQ38
L7 PL_DDR3_D39 SSTL15 142 DQ39
F14 PL_DDR3_D40 SSTL15 147 DQ40
F15 PL_DDR3_D41 SSTL15 149 DQ41
F13 PL_DDR3_D42 SSTL15 157 DQ42
Net Name I/O Standard
DDR3 SODIMM Memory J1
Pin Number Pin Name
G16 PL_DDR3_D43 SSTL15 159 DQ43
G15 PL_DDR3_D44 SSTL15 146 DQ44
E12 PL_DDR3_D45 SSTL15 148 DQ45
D13 PL_DDR3_D46 SSTL15 158 DQ46
E13 PL_DDR3_D47 SSTL15 160 DQ47
D15 PL_DDR3_D48 SSTL15 163 DQ48
E15 PL_DDR3_D49 SSTL15 165 DQ49
D16 PL_DDR3_D50 SSTL15 175 DQ50
E16 PL_DDR3_D51 SSTL15 177 DQ51
C17 PL_DDR3_D52 SSTL15 164 DQ52
B16 PL_DDR3_D53 SSTL15 166 DQ53
D14 PL_DDR3_D54 SSTL15 174 DQ54
B17 PL_DDR3_D55 SSTL15 176 DQ55
B12 PL_DDR3_D56 SSTL15 181 DQ56
C12 PL_DDR3_D57 SSTL15 183 DQ57
A12 PL_DDR3_D58 SSTL15 191 DQ58
A14 PL_DDR3_D59 SSTL15 193 DQ59
A13 PL_DDR3_D60 SSTL15 180 DQ60
ZC706 Evaluation Board User Guide www.xilinx.com 20
UG954 (v1.5) September 10, 2015
Feature Descriptions
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Table 1-4: DDR3 SODIMM Socket J1 Connections to the XC7Z045 AP SoC (Cont’d)
XC7Z045 (U1)
Pin
B11 PL_DDR3_D61 SSTL15 182 DQ61
C14 PL_DDR3_D62 SSTL15 192 DQ62
B14 PL_DDR3_D63 SSTL15 194 DQ63
J3 PL_DDR3_DM0 SSTL15 11 DM0
F2 PL_DDR3_DM1 SSTL15 28 DM1
E1 PL_DDR3_DM2 SSTL15 46 DM2
C2 PL_DDR3_DM3 SSTL15 63 DM3
L12 PL_DDR3_DM4 SSTL15 136 DM4
G14 PL_DDR3_DM5 SSTL15 153 DM5
C16 PL_DDR3_DM6 SSTL15 170 DM6
C11 PL_DDR3_DM7 SSTL15 187 DM7
K2 PL_DDR3_DQS0_N DIFF_SSTL15 10 DQS0_N
K3 PL_DDR3_DQS0_P DIFF_SSTL15 12 DQS0_P
H1 PL_DDR3_DQS1_N DIFF_SSTL15 27 DQS1_N
J1 PL_DDR3_DQS1_P DIFF_SSTL15 29 DQS1_P
D5 PL_DDR3_DQS2_N DIFF_SSTL15 45 DQS2_N
E6 PL_DDR3_DQS2_P DIFF_SSTL15 47 DQS2_P
Net Name I/O Standard
DDR3 SODIMM Memory J1
Pin Number Pin Name
A4 PL_DDR3_DQS3_N DIFF_SSTL15 62 DQS3_N
A5 PL_DDR3_DQS3_P DIFF_SSTL15 64 DQS3_P
K8 PL_DDR3_DQS4_N DIFF_SSTL15 135 DQS4_N
L8 PL_DDR3_DQS4_P DIFF_SSTL15 137 DQS4_P
F12 PL_DDR3_DQS5_N DIFF_SSTL15 152 DQS5_N
G12 PL_DDR3_DQS5_P DIFF_SSTL15 154 DQS5_P
E17 PL_DDR3_DQS6_N DIFF_SSTL15 169 DQS6_N
F17 PL_DDR3_DQS6_P DIFF_SSTL15 171 DQS6_P
A15 PL_DDR3_DQS7_N DIFF_SSTL15 186 DQS7_N
B15 PL_DDR3_DQS7_P DIFF_SSTL15 188 DQS7_P
G7 PL_DDR3_ODT0 SSTL15 116 ODT0
C9 PL_DDR3_ODT1 SSTL15 120 ODT1
G17 PL_DDR3_RESET_B SSTL15 30 RESET_B
J11 PL_DDR3_S0_B SSTL15 114 S0_B
H8 PL_DDR3_S1_B SSTL15 121 S1_B
M10 PL_DDR3_TEMP_EVE
NT
F7 PL_DDR3_WE_B SSTL15 113 WE_B
SSTL15 198 EVENT_B
ZC706 Evaluation Board User Guide www.xilinx.com 21
UG954 (v1.5) September 10, 2015
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Table 1-4: DDR3 SODIMM Socket J1 Connections to the XC7Z045 AP SoC (Cont’d)
XC7Z045 (U1)
Pin
E7 PL_DDR3_CAS_B SSTL15 115 CAS_B
H11 PL_DDR3_RAS_B SSTL15 110 RAS_B
D10 PL_DDR3_CKE0 SSTL15 73 CKE0
C7 PL_DDR3_CKE1 SSTL15 74 CKE1
F10 PL_DDR3_CLK0_N DIFF_SSTL15 103 CK0_N
G10 PL_DDR3_CLK0_P DIFF_SSTL15 101 CK0_P
D8 PL_DDR3_CLK1_N DIFF_SSTL15 104 CK1_N
D9 PL_DDR3_CLK1_P DIFF_SSTL15 102 CK1_P
Net Name I/O Standard
DDR3 SODIMM Memory J1
Pin Number Pin Name
The ZC706 DDR3 SODIMM interface adheres to the constraints guidelines documented in
the “Dynamic Memory” section of the Zynq-7000 All Programmable SoC PCB Design and Pin
Planning Guide (UG933
). The ZC706 DDR3 SODIMM interface is a 40Ω impedance
implementation. For more details, see the MT8JTF12864HZ-1G6G1 data sheet [Ref 34].
DDR3 Component Memory (PS)
[Figure 1-2, callout 3]
The 1 GB, 32-bit wide DDR3 component memory system is comprised of four 256 Mb x 8
SDRAMs (Micron MT41J256M8HX-15E) at U2-U5. This memory system is connected to the
XC7Z045 AP SoC Processing System (PS) memory interface bank 502. The DDR3 0.75V VTT
termination voltage is sourced from linear regulator U27. The connections between the
DDR3 component memory and XC7Z045 AP SoC bank 502 are listed in Tab le 1 -5.
Table 1-5: DDR3 Component Memory Connections to the XC7Z045 AP SoC
Component Memory
XC7Z045 (U1) Pin Net Name
Pin Number Pin Name Ref. Des.
E26 PS_DDR3_DQ0 B3 DQ0 U2
A25 PS_DDR3_DQ1 C7 DQ1 U2
E27 PS_DDR3_DQ2 C2 DQ2 U2
E25 PS_DDR3_DQ3 C8 DQ3 U2
D26 PS_DDR3_DQ4 E3 DQ4 U2
B25 PS_DDR3_DQ5 E8 DQ5 U2
D25 PS_DDR3_DQ6 D2 DQ6 U2
B27 PS_DDR3_DQ7 E7 DQ7 U2
A27 PS_DDR3_DQ8 B3 DQ8 U3
A28 PS_DDR3_DQ9 C7 DQ9 U3
A29 PS_DDR3_DQ10 C2 DQ10 U3
ZC706 Evaluation Board User Guide www.xilinx.com 22
UG954 (v1.5) September 10, 2015
Feature Descriptions
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Table 1-5: DDR3 Component Memory Connections to the XC7Z045 AP SoC (Cont’d)
XC7Z045 (U1) Pin Net Name
C28 PS_DDR3_DQ11 C8 DQ11 U3
D30 PS_DDR3_DQ12 E3 DQ12 U3
A30 PS_DDR3_DQ13 E8 DQ13 U3
D29 PS_DDR3_DQ14 D2 DQ14 U3
D28 PS_DDR3_DQ15 E7 DQ15 U3
H27 PS_DDR3_DQ16 B3 DQ16 U4
G27 PS_DDR3_DQ17 C7 DQ17 U4
H28 PS_DDR3_DQ18 C2 DQ18 U4
E28 PS_DDR3_DQ19 C8 DQ19 U4
E30 PS_DDR3_DQ20 E3 DQ20 U4
F28 PS_DDR3_DQ21 E8 DQ21 U4
G30 PS_DDR3_DQ22 D2 DQ22 U4
F30 PS_DDR3_DQ23 E7 DQ23 U4
K27 PS_DDR3_DQ24 B3 DQ24 U5
J30 PS_DDR3_DQ25 C7 DQ25 U5
J28 PS_DDR3_DQ26 C2 DQ26 U5
J29 PS_DDR3_DQ27 C8 DQ27 U5
Component Memory
Pin Number Pin Name Ref. Des.
K30 PS_DDR3_DQ28 E3 DQ28 U5
M29 PS_DDR3_DQ29 E8 DQ29 U5
L30 PS_DDR3_DQ30 D2 DQ30 U5
M30 PS_DDR3_DQ31 E7 DQ31 U5
C27 PS_DDR3_DM0 B7 DM0 U2
C26 PS_DDR3_DQS0_P C3 DQS0_P U2
B26 PS_DDR3_DQS0_N D3 DQS0_N U2
B30 PS_DDR3_DM1 B7 DM1 U3
C29 PS_DDR3_DQS1_P C3 DQS1_P U3
B29 PS_DDR3_DQS1_N D3 DQS1_N U3
H29 PS_DDR3_DM2 B7 DM2 U4
G29 PS_DDR3_DQS2_P C3 DQS2_P U4
F29 PS_DDR3_DQS2_N D3 DQS2_N U4
K28 PS_DDR3_DM3 B7 DM3 U5
L28 PS_DDR3_DQS3_P C3 DQS3_P U5
L29 PS_DDR3_DQS3_N D3 DQS3_N U5
L25 PS_DDR3_A0 K3 A0 U2, U3, U4, U5
K26 PS_DDR3_A1 L7 A1 U2, U3, U4, U5
ZC706 Evaluation Board User Guide www.xilinx.com 23
UG954 (v1.5) September 10, 2015
Feature Descriptions
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Table 1-5: DDR3 Component Memory Connections to the XC7Z045 AP SoC (Cont’d)
XC7Z045 (U1) Pin Net Name
L27 PS_DDR3_A2 L3 A2 U2, U3, U4, U5
G25 PS_DDR3_A3 K2 A3 U2, U3, U4, U5
J26 PS_DDR3_A4 L8 A4 U2, U3, U4, U5
G24 PS_DDR3_A5 L2 A5 U2, U3, U4, U5
H26 PS_DDR3_A6 M8 A6 U2, U3, U4, U5
K22 PS_DDR3_A7 M2 A7 U2, U3, U4, U5
F27 PS_DDR3_A8 N8 A8 U2, U3, U4, U5
J23 PS_DDR3_A9 M3 A9 U2, U3, U4, U5
G26 PS_DDR3_A10 H7 A10 U2, U3, U4, U5
H24 PS_DDR3_A11 M7 A11 U2, U3, U4, U5
K23 PS_DDR3_A12 K7 A12 U2, U3, U4, U5
H23 PS_DDR3_A13 N3 A13 U2, U3, U4, U5
J24 PS_DDR3_A14 N7 A14 U2, U3, U4, U5
M27 PS_DDR3_BA0 J2 BA0 U2, U3, U4, U5
M26 PS_DDR3_BA1 K8 BA1 U2, U3, U4, U5
M25 PS_DDR3_BA2 J3 BA2 U2, U3, U4, U5
K25 PS_DDR3_CLK_P F7 CK U2, U3, U4, U5
Component Memory
Pin Number Pin Name Ref. Des.
J25 PS_DDR3_CLK_N G7 CK_B U2, U3, U4, U5
M22 PS_DDR3_CKE G9 CKE U2, U3, U4, U5
N23 PS_DDR3_WE_B H3 WE_B U2, U3, U4, U5
M24 PS_DDR3_CAS_B G3 CAS_B U2, U3, U4, U5
N24 PS_DDR3_RAS_B F3 RAS_B U2, U3, U4, U5
F25 PS_DDR3_RESET_B N2 RESET_B U2, U3, U4, U5
N22 PS_DDR3_CS_B H2 CS_B U2, U3, U4, U5
L23 PS_DDR3_ODT G1 ODT U2, U3, U4, U5
N21 PS_VRN
M21 PS_VRP
L22 VTTVREF_PS
L24 VTTVREF_PS
The ZC706 DDR3 component interface adheres to the constraints guidelines documented in
the DDR3 Design Guidelines section of Zynq-7000 All Programmable SoC PCB Design and
Pin Planning Guide (UG933
). The ZC706 DDR3 component interface is a 40Ω impedance
implementation. For more details, see the MT41J256M8HX-15E data sheet [Ref 34].
ZC706 Evaluation Board User Guide www.xilinx.com 24
UG954 (v1.5) September 10, 2015
Quad-SPI Flash Memory
Send Feedback
[Figure 1-2, callout 4]
The Quad-SPI flash memory located at U58 and U59 provides 2 x 128 Mb of nonvolatile
storage that can be used for configuration and data storage.
• Part number: S25FL128SAGMFIR01 (Spansion)
•Supply voltage: 1.8V
• Datapath width: 4 bits
• Data rate: Various depending on Single/Dual/Quad mode
The connections between the SPI flash memory and the XC7Z045 AP SoC are listed in
Tab le 1- 6.
Table 1-6: Quad-SPI Flash Memory Connections to the XC7Z045 AP SoC
Feature Descriptions
XC7Z045 (U1)
Pin Name Bank Pin Number Pin Number Pin Name Ref. Des.
PS_MIO6 500 D24 QSPI0_CLK
PS_MIO5 500 C24 QSPI0_IO3
PS_MIO4 500 E23 QSPI0_IO2
PS_MIO3 500 C23 QSPI0_IO1
PS_MIO2 500 F23 QSPI0_IO0
PS_MIO1 500 D23 QSPI0_CS_B
PS_MIO9 500 A24 QSPI1_CLK
PS_MIO13 500 F22 QSPI1_IO3
PS_MIO12 500 E21 QSPI1_IO2
PS_MIO11 500 A23 QSPI1_IO1
PS_MIO10 500 E22 QSPI1_IO0
PS_MIO0 500 F24 QSPI1_CS_B
Schematic
Net Name
Quad-SPI Flash Memory QSPI Device
16 C U58 J74.2
1 DQ3_HOLD_B U58 J73.2
9 WP_B U58 J72.2
8 DQ1 U58 J71.2
15 DQ0 U58 J70.2
7S_BU58N/A
16 C U59 N/A
1DQ3_HOLD_BU59 N/A
9WP_BU59N/A
8DQ1U59N/A
15 DQ0 U59 N/A
7S_BU59N/A
The configuration section of the Zynq-7000 All Programmable SoC Technical Reference
Manual UG585
, provides details on using the Quad-SPI flash memory.
MIO Select
Header
ZC706 Evaluation Board User Guide www.xilinx.com 25
UG954 (v1.5) September 10, 2015
Figure 1-6 shows the connections of the linear Quad-SPI flash memory on the ZC706
evaluation board. For more details, see the Spansion S25FL128SAGMFIR01 data sheet
[Ref 16].
X-Ref Target - Figure 1-6
Send Feedback
Feature Descriptions
VCCP1V8 VCC3V3_PS VCCP1V8
C39
1
0.1UF
25V
2
X5R
GND
QSPI0_IO3
QSPI0_CS_B
QSPI0_IO1
C40
1
0.1UF
25V
2
X5R
C714
1
R531
1
R207
1
330
1/10W
2
5%
0
1/10W
2
5%
R527
1
DNP
DNP
2
DNP
R528
1
DNP
DNP
2
DNP
2
GND
0.1UF
25V
X5R
S25FL128SAGMFIR01
QSPI0_CLK
QSPI0_IO0
QSPI0_IO2
NC
NC
NC
NC
1
DQ3_HOLD_B
2
VCC
3
NC0
4
NC1
5
NC2
6
NC3
7
S_B
8
DQ1
DQ0
NC7
NC6
NC5
NC4
VSS
DQ2_VPP_WP_B
16
C
15
14
13
NC
12
NC
11
NC
10
9
SO16_50P300X413U58
GND
VCCP1V8 VCC3V3_PS VCCP1V8
C715
1
R532
1
R208
1
330
1/10W
2
5%
0
1/10W
2
5%
R530
1
DNP
DNP
2
DNP
R529
1
DNP
DNP
2
DNP
0.1UF
25V
2
X5R
QSPI1_IO3
QSPI1_CS_B
QSPI1_IO1
S25FL128SAGMFIR01
NC
NC
NC
NC
1
DQ3_HOLD_B
2
VCC
3
NC0
4
NC1
5
NC2
6
NC3
7
S_B
8
DQ1
DQ2_VPP_WP_B
DQ0
NC7
NC6
NC5
NC4
VSS
16
C
15
14
13
NC
12
NC
11
NC
10
9
SO16_50P300X413U59
GND
Figure 1-6: 128 Mb Quad-SPI Flash Memory
QSPI1_CLK
QSPI1_IO0
QSPI1_IO2
UG954_c1_06_073013
ZC706 Evaluation Board User Guide www.xilinx.com 26
UG954 (v1.5) September 10, 2015
Feature Descriptions
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USB 2.0 ULPI Transceiver
[Figure 1-2, callout 19]
The ZC706 evaluation board uses a Standard Microsystems Corporation USB3320 USB 2.0
ULPI Transceiver at U12 to support a USB connection to the host computer. A USB cable is
supplied in the ZC706 evaluation kit (Standard-A connector to host computer, Micro-B
connector to ZC706 evaluation board connector J2). The USB3320 is a high-speed USB 2.0
PHY supporting the UTMI+ low pin interface (ULPI) interface standard. The ULPI standard
defines the interface between the USB controller IP and the PHY device which drives the
physical USB bus. Use of the ULPI standard reduces the interface pin count between the USB
controller IP and the PHY device.
The USB3320 is clocked by a 24 MHz crystal. Consult the SMSC USB3320 data sheet for
clocking mode details [Ref 17].
The interface to the USB3320 transceiver is implemented through the IP in the XC7Z045
AP SoC Processor System.
Tab le 1- 7 describes the jumper settings for the USB 2.0 circuit. Bold text identifies the
default OTG mode settings.
Table 1-7: USB Jumper Settings
Header Function Shunt Position Notes
J11
J10
J48
J50
J49
J51
USB PHY reset Shunt ON = USB PHY reset
Shunt OFF = USB PHY normal operation
V
5V Supply Shunt ON = Host or OTG mode
BUS
RVBUS select Position 1–2 = Device mode only (10 KΩ )
CVBUS select Position 1-2 = OTG and Device mode 1 μF
Cable ID select Position 1-2 = A/B cable detect
USB Micro-B Position 1-2 = Shield connected to GND
Shunt OFF = Device mode
Position 2–3 = OTG or Host mode (1 KΩ )
Position 2-3 = Host mode 120 μF
Position 2-3 = ID not used
Position 2-3 = Shield floating
Clean reset requires external
debouncing
Overvoltage protection
V
load capacitance
BUS
Used in OTG mode
ZC706 Evaluation Board User Guide www.xilinx.com 27
UG954 (v1.5) September 10, 2015
Feature Descriptions
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The connections between the USB Micro-B connector at J2 and the PHY at U12 are listed in
Tab le 1- 8.
Table 1-8: USB Connector Pin Assignments and Signal Definitions Between J2 and U12
USB Connector
J1
Net Name Description
Pin Name
1 VBUS USB_VBUS_SEL +5V from host system 22
2 D_N USB_D_N Bidirectional differential serial data (N-side) 19
3 D_P USB_D_P Bidirectional differential serial data (P-side) 18
5 GND GND Signal ground 33
The connections between the USB 2.0 PHY at U12 and the XC7Z045 AP SoC are listed in
Tab le 1- 9.
Table 1-9: USB 2.0 ULPI Transceiver Connections to the XC7Z045 AP SoC
XC7Z045 (U1)
Schematic Net Name USB3320 (U12) Pin
Pin Name Bank Pin Number
PS_MIO36 501 H17 USB_CLKOUT 1
PS_MIO31 501 H21 USB_NXT 2
PS_MIO32 501 K17 USB_DATA0 3
PS_MIO33 501 G22 USB_DATA1 4
USB3320 (U12)
Pin
PS_MIO34 501 K18 USB_DATA2 5
PS_MIO35 501 G21 USB_DATA3 6
PS_MIO28 501 L17 USB_DATA4 7
PS_MIO37 501 B21 USB_DATA5 9
PS_MIO38 501 A20 USB_DATA6 10
PS_MIO39 501 F18 USB_DATA7 13
PS_MIO30 501 L18 USB_STP 29
PS_MIO29 501 E8 USB_DIR 31
PS_MIO7 500 D5 USB_RESET_B_AND 27 (via AND gate U13)
For additional information on the Zynq-7000 AP SoC device USB controllers, see Zynq-7000
All Programmable SoC Overview (DS190
Reference Manual (UG585
).
) and Zynq-7000 All Programmable SoC Technical
ZC706 Evaluation Board User Guide www.xilinx.com 28
UG954 (v1.5) September 10, 2015
X-Ref Target - Figure 1-7
Send Feedback
8
8
8
8
8
8
8
Feature Descriptions
Figure 1-7 shows the USB 2.0 ULPI transceiver circuitry. Note that the shield for the USB
Micro-B connector (J2) can be tied to GND by a jumper on header J51 pins 1–2 (default).
The USB shield can optionally be connected through a capacitor to GND by installing a
capacitor (body size 0402) at location C335 and jumping pins 2-3 on header J51.
9
9
USB_CLKOUT
USB_NXT
USB_DATA0
USB_DATA1
USB_DATA2
USB_DATA3
USB_DATA4
VCCP1V8
3 PLACES
31
2 PLACES
VCCMIO
C70
C71
C74
1
0.1UF
2
25V
GND
USB3320_QFN32
1
CLKOUT_1
2
NXT_2
3
DATA0_3
DATA1_4
5
DATA2_5
6
DATA3_6
7
DATA4_7
8
REFSEL0_8
U12
USB_DIR
USB_STP
USB_RESET_B
1
29
VDD18_30
REFSEL1_11
12
NC
STP_29
NC_12
27
28
VDD18_28
DATA7_13
14
13415 26
USB_DATA7
8
RESETB_27
REFSEL2_14
SPK_L_15 REFCLK_26
NC
R389
1/10W
R403
16 25
NC
261
1.0M
1/10W
XO_25
SPK_R_16
VCC3V3
5%
CTR_GND_33
USB3320_QFN32
1
2
2
RBIAS_23
VBUS_22
VBAT_21
VDD33_P
CPEN33_17
1
1
2
2
32
31
30
DIR_31
VDDIO_32
DATA6_10
DATA5_9
9
10
11
USB_DATA5
USB_DATA6
8
8
C496
1
18PF
2
50V
NPO
GND
24
USB_ID
23
ID_23
22
21
20
USB_D_N
19
DM_19
USB_D_P
18
DP_18
17
33
GND
DS25
21
LED-RED-SMT
X2
21
C497
1
24.000MHZ
18PF
2
50V
NPO
GND
R178
8.06K
1/10W
1%
2
1
31
USB_VDD33
27
31
C209
1
31
2.2UF
6.3V
2
GND
1
R267
10.0K
1/10W
2
1
1-2 = DEVICE MODE
2-3 = HOST OR OTG MODE
USB HOST POWER
MIC2025_SOP8
18
EN OUT2
2
FLG
3
GND
4
NC
NC1
U22
GND
GND
2
1
2
3
VCC5V0
2125V
GND
R359
1.00K
1/16W
J48
7
IN
6
OUT1
5
NC2
SOP127P500X600_8
C72
0.1UF
USB_VBUS_SEL
NC
1
2
VCC5V0
1
2
GND
J10
C76
0.1UF
25V
USB_VBUS_SEL
C380
1
1UF
2
16V
J50
X5R
CVBUS Select:
1-2: OTG Mode
2-3: Host Mode
GND
ON = HOST OR OTG MODE
OFF = DEVICE MODE
1
C469
150UF
2
10V
TANT
GND
L11
FERRITE-220
C447
12
1
5.6UF
2
10V
12
FERRITE-220
GND
27
C75
1
0.1UF
27
2
25V
L12
J49
1
3
2
C484
1
120UF
20V
TANT
2
GND
1-2 = A/B CABLE DETECT
2-3 = ID NOT USED
USB_D_N
USB_D_P
1
2
3
USB_ID
USB_VDD33
1
2
3
4
5
ZX62D_AB_5P8
VBUS
D_N
D_P
ID
GND
27
GND
27
SHLD1
SHLD2
SHLD3
SHLD4
SHLD5
9
7
8
6
10
J51
UG954_c1_07_041113
SHLD6
11
123
J2
1
C335
2
DNP
GND
Figure 1-7: USB 2.0 ULPI Transceiver
SD Card Interface
[Figure 1-2, callout 5]
The ZC706 evaluation board includes a secure digital input/output (SDIO) interface to
provide user-logic access to general purpose nonvolatile SDIO memory cards and
peripherals. Information for the SD I/O card specification can be found at the SanDisk and
SD card websites [Ref 18], [Ref 19].
The SDIO signals are connected to XC7Z045 AP SoC PS bank 501 which has its VCCMIO set
to 1.8V. A MAX13035E high-speed logic-level translator (U11) is used between XC7Z045 AP
SoC 1.8V PS bank 501 and the 3.3V SD card connector (J30).
ZC706 Evaluation Board User Guide www.xilinx.com 29
UG954 (v1.5) September 10, 2015
X-Ref Target - Figure 1-8
Send Feedback
Feature Descriptions
Figure 1-8 shows the connections of the SD card interface on the ZC706 evaluation board.
VCCP1V8
1
2
R28
4.7 KΩ
1/10W
5%
1
R29
4.7 KΩ
1/10W
2
5%
VCC3V3_PS
1
2
GND
C41
0.1 μF
25V
X5R
GND
67840-8001
1
CD_DAT3
2
CMD
3
VSS1
4
VDD
5
CLK
6
VSS2
7
DAT0
8
DAT1
9
DAT2
10
DETECT
11
PROTECT
12
DETECT_PROTECT
J30
IOGND2
IOGND1
GNDTAB4
GNDTAB3
GNDTAB2
GNDTAB1
UG954_c1_08_041113
18
17
16
15
14
13
GND
SDIO_CD_DAT322
22 SDIO_CMD
22 SDIO_CLK
SDIO_DAT022
22 SDIO_DAT1
SDIO_DAT222
SDIO_SDDET8
SDIO_SDWP8
Figure 1-8: SD Card Interface
Tab le 1- 10 lists the SD card interface connections to the XC7Z045 AP SoC
Table 1-10: SDIO Connections to the XC7Z045 AP SoC
XC7Z045 (U1) Pin
Level Shifter (U11) SDIO Connector (J30)
Schematic
Pin Name Bank
Pin
Number
Net Name
PS_MIO15 500 C22 SDIO_SDWP N/A N/A 11 PROTECT
1.8V Side
Pin
3.3V Side
Pin
Pin
Number
Name
Pin
PS_MIO14 500 B22 SDIO_SDDET N/A N/A 10 DETECT
PS_MIO41 501 J18 SDIO_CMD_LS 4 20 2 CMD
PS_MIO40 501 B20 SDIO_CLK_LS 9 19 5 CLK
PS_MIO44 501 E20 SDIO_DAT2_LS 1 23 9 DAT2
PS_MIO43 501 E18 SDIO_DAT1_LS 7 16 8 DAT1
PS_MIO42 501 D20 SDIO_DAT0_LS 6 18 7 DAT0
PS_MIO45 501 H18 SDIO_CD_DAT3_LS 3 22 1 CD_DAT3
ZC706 Evaluation Board User Guide www.xilinx.com 30
UG954 (v1.5) September 10, 2015
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