Xilinx ZC706 User Manual

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ZC706 Evaluation Board for the Zynq-7000 XC7Z045 All Programmable SoC

User Guide

UG954 (v1.5) September 10, 2015

Notice of Disclaimer

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The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, prof its, goodwill, or any type of lo ss o r damage suffered as a result of any action broug ht by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx’s limited warranty, please refer to Xilinx’s Terms of Sale which can be viewed at www.xilinx.com/legal.htm#tos subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx’s Terms of Sale which can be viewed at www.xilinx.com/legal.htm#tos

Automotive Applications Disclaimer

XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE ERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III) USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.

© Copyright 2012–2015 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

; IP cores may be

Revision History

The following table shows the revision history for this document.

Date Version Revision

10/08/2012 1.0

11/21/2012 1.1

Initial Xilinx release.

Added additional user LED in ZC706 Evaluation Board Features section, Ta bl e 1- 1,

User I/O section, Figure 1-25, and Tab le 1- 28 . In Tab le 1- 1, added fan sink

information and updated notes for 10/100/1000 Ethernet PHY, user pushbuttons, user DIP switch, and FPGA PROG pushbutton. Added Encryption Key Backup Circuit section. Updated second paragraph in DDR3 SODIMM Memory (PL) section. Updated second paragraph in SD Card Interface section. Updated Tab le 1- 11 . Added U53 information to first paragraph in HDMI Video Output section. Added fourth bullet to Real T ime Clock (RTC) section. Updated Figure 1-23. Added pin A17 to Tab le 1- 28 . Updated Figure 1-32. Replaced UCF in Appendix C. Added additional reference to References in Appendix F.

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UG954 (v1.5) September 10, 2015

Date Version Revision

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04/24/2013 1.2

07/31/2013 1.3

04/28/2015 1.4

Chapter 1, ZC706 Evaluation Board Features: Tab le 1-1 feature descriptions are now

linked to their respective sections in the book. Figure 1-2, Figure 1-33, and

Figure 1-34 were replaced. Table 1-2 was removed because it was a duplicate of Tab le 1-1 1. Tab le 1- 2: Switch SW11 Configuration Option Settings was added. FMC Connector JTAG Bypass, page 33 was updated. Default lane size information below Figure 1-17 was changed. Figure 1-18 PCI Express Lane Size Select Jumper J19 was

added. The names of pins 18 and 19 changed in Tabl e 1-1 7. The address of I PMBUS_DATA/CLOCK changed in Tab le 1- 25 . Reference designator DS35 was added to Ta bl e 1 -2 7. Callout numbers in the User I/O, page 57 section are now linked to

Tab le 1-1 . SW13 information was added to the section User Pushbuttons, page 59.

In Tab le 1-3 3, J5 pin H22 changed to XC7Z045 (U1) pin AH26 and H23 changed to AH27. The section ZC706 Board Power System, page 72 was added. Voltage levels were changed in VADJ Voltage Control, page 79. Tab le 1-3 7 was modified and

Tab le 1-3 8 was added. Appendix A, Default Switch and Jumper Settings: The SW11 selection in Ta bl e A- 1

changed.

Appendix G, Regulatory and Compliance Information: A link to the master answer

record was added.

Updated Tabl e 1- 22 . Replaced the master User Constraints File (UCF) list in

Appendix C, Master Constraints File Listing with the master Xilinx Design

Constraints (XDC) list. Updated references throughout the document.

Updated “LMZ22000 Family Regulator Description” to LMZ31500 and LMZ31700

Family Regulator Description. Updated Ta bl e 1 -4, Tab le 1-7 , Tab le 1-1 3, Tab le 1- 23 , Tab le 1-2 8 through Ta bl e 1 -3 0, Ta bl e 1- 32 through Tab le 1-3 4, Tab le 1-3 6, and Tab le A-2 . Added Figure A-1. Updated Appendix C, Master Constraints File Listing.

C bus

09/10/2015 1.5

Updated J48 header jumper setting (third row in Tab le 1 -7 ).

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Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Chapter 1: ZC706 Evaluation Board Features

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

ZC706 Evaluation Board Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Feature Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Zynq-7000 XC7Z045 AP SoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Encryption Key Backup Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

I/O Voltage Rails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

DDR3 SODIMM Memory (PL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

DDR3 Component Memory (PS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Quad-SPI Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

USB 2.0 ULPI Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

SD Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Programmable Logic JTAG Programming Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Programmable Logic JTAG Select Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

FMC Connector JTAG Bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Programmable User Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

User SMA Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Processing System Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

GTX SMA Clock (SMA_MGT_REFCLK_P and SMA_MGT_REFCLK_N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Jitter Attenuated Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

GTX Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

PCI Express Endpoint Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

SFP/SFP+ Module Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

10/100/1000 Mb/s Tri-Speed Ethernet PHY (PL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Ethernet PHY Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

USB-to-UART Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

HDMI Video Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Real Time Clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Status and User LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Ethernet PHY User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

User I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

User Pushbuttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

GPIO DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

User PMOD GPIO Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

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Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

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Power On/Off Slide Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Program_B Pushbutton . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

PS Power-On and System Reset Pushbuttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

FPGA Mezzanine (FMC) Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

HPC Connector J37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

LPC Connector J5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

ZC706 Board Power System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

UCD90120A Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

LMZ31500 and LMZ31700 Family Regulator Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

XADC Power System Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

VADJ Voltage Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

AP SoC Programmable Logic (PL) Voltage Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Monitoring Voltage and Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Cooling Fan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

XADC Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Appendix A: Default Switch and Jumper Settings

Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Appendix B: VITA 57.1 FMC Connector Pinouts

Appendix C: Master Constraints File Listing

ZC706 Evaluation Board XDC Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Appendix D: Board Setup

Installing the ZC706 Board in a PC Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Appendix E: Board Specifications

Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Environmental . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

Humidity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

Operating Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

Appendix F: Additional Resources

Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Appendix G: Regulatory and Compliance Information

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Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Declaration of Conformity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

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Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

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Overview

The ZC706 evaluation board for the XC7Z045 All Programmable SoC (AP SoC) provides a hardware environment for developing and evaluating designs targeting the Zynq®-7000 XC7Z045-2FFG900C AP SoC. The ZC706 evaluation board provides features common to many embedded processing systems, including DDR3 SODIMM and component memory, a four-lane PCI Express® interface, an Ethernet PHY, general purpose I/O, and two UART interfaces. Other features can be supported using VITA-57 FPGA mezzanine cards (FMC) attached to the low pin count (LPC) FMC and high pin count (HPC) FMC connectors.

ZC706 Evaluation Board Features

Chapter 1

The ZC706 evaluation board features are listed in here. Detailed information for each feature is provided in Feature Descriptions starting on page 14.

• Zynq-7000 XC7Z045-2FFG900C AP SoC

• 1 GB DDR3 memory SODIMM on the programmable logic (PL) side

• 1 GB DDR3 component memory (four [256 Mb x 8] devices) on the processing system (PS) side

• Two 128 Mb Quad-SPI (QSPI) flash memory (Dual Quad-SPI)

• USB 2.0 ULPI (UTMI+ low pin interface) transceiver with micro-B USB connector

• Secure Digital (SD) connector

• USB JTAG interface via Digilent module with micro-B USB connector

• Clock sources:

Fixed 200 MHz LVDS oscillator (differential)

I2C programmable LVDS oscillator (differential)

Fixed 33.33 MHz LVCMOS oscillator (single-ended)

Subminiature version A (SMA) connectors (differential)

ZC706 Evaluation Board User Guide www.xilinx.com 7

UG954 (v1.5) September 10, 2015

SMA connectors for GTX transceiver clocking (differential)

•GTX transceivers

Send Feedback

FMC HPC connector (eight GTX transceivers)

FMC LPC connector (one GTX transceiver)

SMA connectors (one pair each for TX, RX and REFCLK)

PCI Express (four lanes)

Small form-factor pluggable plus (SFP+) connector

Ethernet PHY RGMII interface

• PCI Express endpoint connectivity

Gen1 4-lane (x4)

Gen2 4-lane (x4)

• SFP+ Connector

• Ethernet PHY RGMII interface with RJ-45 connector

Overview

• USB-to-UART bridge with mini-B USB connector

• HDMI codec with HDMI connector

I2C bus

•

I2C bus multiplexed to:

•

Si570 user clock

ADV7511 HDMI codec

M24C08 EEPROM (1 kB)

1-to-16 TCA6416APWR port expander

DDR3 SODIMM

RTC-8564JE real time clock

FMC HPC connector

FMC LPC connector

PMBUS data/clock

•Status LEDs:

ZC706 Evaluation Board User Guide www.xilinx.com 8

UG954 (v1.5) September 10, 2015

Ethernet status

TI Power Good

Linear Power Good

PS DDR3 Component Vtt Good

PL DDR3 SODIMM Vtt Good

FMC Power Good

Send Feedback

12V Input Power On

FPGA INIT

FPGA DONE

•User I/O:

Four (PL) user LEDs

Three (PL) user pushbuttons

One (PL) user DIP switch (4-pole)

Two Dual row Pmod GPIO headers

• AP SoC PS Reset Pushbuttons:

SRST_B PS reset button

POR_B PS reset button

Overview

• VITA 57.1 FMC HPC connector

• VITA 57.1 FMC LPC connector

• Power on/off slide switch

•Program_B pushbutton

• Power management with PMBus voltage and current monitoring through TI power controller

• Dual 12-bit 1 MSPS XADC analog-to-digital front end

• Configuration options:

Dual Quad-SPI flash memory

USB JTAG configuration port (Digilent module)

Platform cable header JTAG configuration port

20-pin PL PJTAG header

ZC706 Evaluation Board User Guide www.xilinx.com 9

UG954 (v1.5) September 10, 2015

X-Ref Target - Figure 1-1

Zync-7000 AP SoC

XC7Z045-2FFG900C

Processing

System

Programmable Logic

UG954_c1_01_1002012

JTAG Module

and

JTAG Header

Page 16

Dual Quad-SPI

Flash Memory

Page 21

PCIe

x 4-Lane

Page 42

SD Card

Connector

Page 22

FMC HPC Connector

Pages 24-27

10/100/1,000

Ethernet PHY

(RGMII only)

Page 29, 30

USB 2.0 ULPI

Transceiver

and Connector

Page 31

Clock and

Reset/POR

Pushbuttons

Pages 15, 34

USB UART

and

Connector

Page 40

ARM PJTAG

Header

Page 39

Switches

LEDs and

Pushbuttons

Page 38

Mechanicals

Page 58

I2C

Real Time

Clock

Page 37

DDR3

SODIMM

Page 23

DDR3 Memory 4 x 256 Mb x 8

SDRAM

Pages 17-20

HDMI Codec

and

Connector

Pages 32, 33

I2C Multiplexer

and

I2C EEPROM

Page 36

XADC

Header

Page 35

Configurable

Clocks

Page 34

FMC LPC Connector

Page 28

Note: Page numbers reference the page number of schematic 0381513.

Send Feedback

Overview

Block Diagram

The ZC706 evaluation board block diagram is shown in Figure 1-1.

Figure 1-1: ZC706 Evaluation Board Block Diagram

Board Layout

Figure 1-2 shows the ZC706 evaluation board. Each numbered feature that is referenced in Figure 1-2 is described in Tab le 1- 1 with a link to detailed information provided under Feature Descriptions starting on page 14.

Note: The image in Figure 1-2 is for reference only and might not reflect the current revision of the

board.

CAUTION! The ZC706 evaluation board can be damaged by electrostatic discharge (ESD). Follow ESD

prevention measures when handling the board.

ZC706 Evaluation Board User Guide www.xilinx.com 10

UG954 (v1.5) September 10, 2015

X-Ref Target - Figure 1-2

Square callout references a component on the back side of the board

Round callout references a component on the front side of the board

UG954_c1_02_042114

Send Feedback

Overview

Figure 1-2: ZC706 Evaluation Board Component Locations

Table 1-1: ZC706 Evaluation Board Component Descriptions

Callout Feature Notes

Zynq-7000 XC7Z045 AP SoC, page 14

Zynq-7000 All Programmable SoC with fan sink

DDR3 SODIMM Memory (PL), page 18

DDR3 SODIMM Memory Socket (J1)

DDR3 Component Memory (PS), page 22

DDR3 Memory 1GB (4x256M U2-U5)

Quad-SPI Flash Memory, page 25

Dual Quad-SPI Flash (128Mb) (U58-U59)

SD Card Interface, page 29

SD Card Interface Connector (J30)

USB 2.0 ULPI Transceiver, page 27

USB JTAG Interface w/Micro-B Connector (U30)

System Clock, page 34

System Clock, 2.5V LVDS (U64)

XC7Z045T-2FFG900C with Radian INC3001-7_1.5BU_LI98 fan sink

Micron MT8JTF12864HZ-1G6G1

Micron MT41J256M8HX-15E

Spansion S25FL128SAGMFIR01

Molex 67840-8001

Digilent USB JTAG Module

SiTime SIT9102-243N25E200.0000

Schematic

0381513

Page Number

17-20

ZC706 Evaluation Board User Guide www.xilinx.com 11

UG954 (v1.5) September 10, 2015

Table 1-1: ZC706 Evaluation Board Component Descriptions (Cont’d)

Send Feedback

Callout Feature Notes

Programmable User Clock, page 35

C Prog. User Clock 3.3V LVDS (U37, bottom of

board)

User SMA Clock Source, page 36

User Differential SMA Clock P/N (J67/J68)

GTX SMA Clock (SMA_MGT_REFCLK_P and SMA_MGT_REFCLK_N), page 37

GTX Differential SMA Clock P/N (J36/J31)

Jitter Attenuated Clock, page 38

Jitter Attenuated Clock (U60, bottom of board)

GTX Transceivers, page 39

GTX Transceivers

PCI Express Endpoint Connectivity, page 44

PCI Express Connector (P4)

SFP/SFP+ Module Connector, page 46

SFP/SFP+ Module Connector (P2)

10/100/1000 Mb/s Tri-Speed Ethernet PHY (PL), page 47

RGMII only 10/100/1000 Mb/s Ethernet PHY w/RJ45 (U51, P3)

GTX Differential SMA TX and RX P/N (J35/J34and J32/J33)

USB-to-UART Bridge, page 49

USB-to-UART Bridge with Mini-B Connector (U52, J21)

HDMI Video Output, page 50

HDMI Controller (U53), HDMI Video Connector (P1)

USB 2.0 ULPI Transceiver, page 27

USB 2.0 ULPI Controller w/ Micro-B Connector (U12, J2)

I2C Bus, page 53

C Bus MUX (U65, bottom of board)

Ethernet PHY User LEDs, page 57

Ethernet PHY Status LEDs (DS28-DS30)

User LEDs, page 58

User LEDs (DS8-DS10, DS35)

User Pushbuttons, page 59

User pushbuttons, active-High (SW7, 9, 8)

Silicon Labs SI570BAB0000544DG, default 156.250 MHz

Rosenberger 32K10K-400L5

Silicon Labs SI5324C-C-GM

Embedded within AP SoC U1

4-lane card edge connector

Molex 74441-0010

Marvell 88E1116RA0-NNC1C000

Rosenberger 32K10K-400L5

Silicon Labs CP2103GM bridge

Analog Devices ADV7511KSTZ-P, Molex 500254-1927,

SMSC USB3320C-EZK

TI PCA9548ARGER

EPHY status LED, GREEN single-stack

GPIO LEDs, GREEN 0603

E-Switch TL3301EF100QG in Left, Center, Right pattern

Overview

Schematic

0381513

Page Number

32, 33

ZC706 Evaluation Board User Guide www.xilinx.com 12

UG954 (v1.5) September 10, 2015

Table 1-1: ZC706 Evaluation Board Component Descriptions (Cont’d)

Send Feedback

Callout Feature Notes

GPIO DIP Switch, page 60

4-pole C&K SDA04H1SBD

GPIO DIP Switch (SW12)

ARM® core PJTAG Header (J64) 2x10 0.1inch male header, Samtec

TST-110-01-G-D

User PMOD GPIO Headers, page 60

2x6 0.1 inch male header

PMOD Headers (J57, J58)

Power On/Off Slide Switch, page 62

C&K 1201M2S3AQE2

Power On/Off Switch (SW1)

Program_B Pushbutton, page 63

E-Switch TL3301EF100QG

FPGA PROG pushbutton (SW10)

AP SoC MIO Config. DIP Switch (SW11) 5-pole DPDT CTS 206-125 15

HPC Connector J37, page 65

Samtec ASP_134486_01

FMC HPC connector (J37)

LPC Connector J5, page 69

Samtec ASP_134603_01

FMC LPC connector (J5)

Power Management, page 77

Power Management System (top and bottom of

TI UCD90120ARGC in conjunction w/various regulators

board)

XADC Analog-to-Digital Converter, page 83

XADC Connector (J63)

Programmable Logic JTAG Select Switch,

2x10 0.1inch male header, Samtec TST-110-01-G-D

2-pole C&K SDA02H1SBD

page 31

JTAG Configuration DIP Switch (SW4)

JTAG Flying Lead Header (J62) 2x10 0.1inch male header, Samtec

TST-110-01-G-D

2x5 shrouded PMBus connector J4 ASSMAN HW10G-0202 48

2x7 2mm shrouded JTAG cable connector J3 MOLEX 87832-1420 16

12V power input 2x6 connector J22 MOLEX-39-30-1060 48

Overview

Schematic

0381513

Page Number

37, 39

24-27

48-57

Notes:

1. Jumper header locations are identified in Appendix A, Default Switch and Jumper Settings.

ZC706 Evaluation Board User Guide www.xilinx.com 13

UG954 (v1.5) September 10, 2015

Feature Descriptions

Application

Processor Unit (APU)

Common

Peripherals

Custom

Peripherals

Common Accelerators

Custom Accelerators

Memory

Interfaces

Processing

System

(PS)

Programmable

Logic

(PL)

Input Output

Peripherals

(IOP)

High-Bandwidth

AMBA

AXI Interfaces

UG954_c1_03_100112

Interconnect

Send Feedback

Feature Descriptions

Detailed information for each feature shown in Figure 1-2 and listed in Table 1 -1 is provided in this section.

Zynq-7000 XC7Z045 AP SoC

[Figure 1-2, callout 1]

The ZC706 evaluation board is populated with the Zynq-7000 XC7Z045-2FFG900C AP SoC.

The XC7Z045 AP SoC consists of an integrated processing system (PS) and programmable logic (PL), on a single die. The high-level block diagram is shown in Figure 1-3.

X-Ref Target - Figure 1-3

ZC706 Evaluation Board User Guide www.xilinx.com 14

UG954 (v1.5) September 10, 2015

Figure 1-3: High-Level Block Diagram

The PS integrates two ARM® Cortex™-A9 MPCore™ application processors, AMBA® interconnect, internal memories, external memory interfaces, and peripherals including USB, Ethernet, SPI, SD/SDIO, and boots at power-up or reset.

A system level block diagram is shown in Figure 1-4.

I2C, CAN, UART, and GPIO. The PS runs independently of the PL

X-Ref Target - Figure 1-4

2x USB

2x GigE

2x SD

Zynq-7000 AP SoC

I/O

Peripherals

IRQ

EMIO

SelectIO

Resources

DMA 8

Channel

CoreSight

Components

Programmable Logic

DAP

DevC

SWDT

DMA

Sync

Notes:

1) Arrow direction shows control (master to slave)

2) Data flows in both directions: AXI 32-Bit/64-Bit, AXI 64-Bit, AXI 32-Bit, AHB 32-Bit, APB 32-Bit, Custom

ACP

256K

SRAM

Application Processor Unit

TTC

System-

Level

Control

Regs

GigE

CAN

SDIO

UART

GPIO

UART

CAN

I2C

SRAM/

NOR

ONFI 1.0

NAND

Processing System

Memory

Interfaces

Q-SPI

CTRL

USB

GigE

I2C

USB

SDIO

SPI

Programmable Logic to

Memory Interconnect

MMU

FPU and NEON Engine

Snoop Controller, AWDT, Timer

GIC

32 KB

I-Cache

ARM Cortex-A9

CPU

ARM Cortex-A9

CPU

MMU

FPU and NEON Engine

Config

AES/

SHA

XADC

12-Bit ADC

Memory

Interfaces

512 KB L2 Cache & Controller

OCM

Interconnect

DDR2/3, LPDDR2

Controller

UG954_c1_04_100112

32 KB

D-Cache

32 KB

I-Cache

32 KB

D-Cache

MIO

Clock

Generation

Reset

Central

Interconnect

General-Purpose

Por ts

High-Performance Ports

Send Feedback

Feature Descriptions

For additional information on Zynq-7000 SoC devices, see Zynq-7000 All Programmable SoC Overview (DS190

(UG585

Figure 1-4: Zynq-7000 Block Diagram

) and Zynq-7000 All Programmable SoC Technical Reference Manual

Device Configuration

the Zynq-7000 XC7Z045 AP SoC uses a multi-stage boot process that supports both a non-secure and a secure boot. The PS is the master of the boot and configuration process. For a secure boot, the PL must be powered on to enable the use of the security block located within the PL, which provides 256-bit AES and SHA decryption/authentication.

The ZC706 evaluation board supports these configuration options:

• PS Configuration: Quad-SPI flash memory

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UG954 (v1.5) September 10, 2015

• PS Configuration: Processor System Boot from SD Card (J30)

Feature Descriptions

Send Feedback

• PL Configuration: USB JTAG configuration port (Digilent module U30)

• PL Configuration: Platform cable header J3 and flying lead header J62 JTAG configuration ports

TIP: Designs using serial configuration based on Quad-SPI flash memory can take advantage of

low-cost commodity SPI flash memory.

The JTAG configuration option is selected by setting SW11 (PS) as shown in Tab le 1 -2 and SW4 (PL) as described in Programmable Logic JTAG Programming Options, page 31. SW11 is callout 29 in Figure 1-2.

Table 1-2: Switch SW11 Configuration Option Settings

Boot Mode SW11.1 SW11.2 SW11.3 SW11.4 SW11.5

JTAG mode

(1)

00000

Independent JTAG mode

QSPI mode

SD mode

MIO configuration pin

Notes:

1. Default switch setting

10000

00010

00110

MIO2 MIO3 MIO4 MIO5 MIO6

For more information about Zynq-7000 AP SoC configuration settings, see Zynq-7000 All

Programmable SoC Technical Reference Manual (UG585

Encryption Key Backup Circuit

The XC7Z045 AP SoC U1 implements bitstream encryption key technology. The ZC706 board provides the encryption key backup battery circuit shown in Figure 1-5. The Seiko TS518FE rechargeable 1.5V lithium button-type battery B2 is soldered to the board with the positive output connected to the XC7Z045 AP SoC U1 VCCBATT pin P9. The battery supply current IBATT specification is 150 nA max when board power is off. B2 is charged from the VCCAUX 1.8V rail through a series diode with a typical forward voltage drop of 0.38V and

4.7 K

Ω current limit resistor. The nominal charging voltage is 1.42V.

ZC706 Evaluation Board User Guide www.xilinx.com 16

UG954 (v1.5) September 10, 2015

X-Ref Target - Figure 1-5

Send Feedback

To XC7Z045 AP SoC

U1 Pin P9

(VCCBATT)

40V

200 mW

FPGA_VBATT

Feature Descriptions

VCCAUX

BAS40-04

4.70K 1% 1/16W

Lithium Battery Seiko TS518SE_FL35E

1.5V

GND

UG954_c1_05_041113

Figure 1-5: Encryption Key Backup Circuit

I/O Voltage Rails

There are eleven I/O banks available on the XC7Z045 AP SoC. The voltages applied to the XC7Z045 AP SoC I/O banks used by the ZC706 evaluation board are listed in Tab le 1 -3.

Table 1-3: I/O Voltage Rails

XC7Z045 (U1)

Bank

PL Bank 0 VCC3V3_FPGA 3.3V AP SoC Configuration Bank 0

PL Bank 9

PL Bank 10 FMC_LPC, PL_JTAG,GPIO

PL Bank 11 FMC_HPC, GPIO_LED, HDMI

PL Bank 12 FMC_LPC, HDMI

PL Bank 13 FMC_HPC, HDMI

Net Name Voltage Connected To

PMOD, USER_SMA_CLOCK, SM_FAN, REC_CLOCK, SFP_TX_DISABLE

VADJ_FPGA 2.5V

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UG954 (v1.5) September 10, 2015

PL Bank 33

PL Bank 34 PL_DDR3_A, SYSCLK

VCC1V5_PL 1.5V

PL_DDR3_D[31:0]

PL Bank 35 PL_DDR3_D[63:32], XADC

Table 1-3: I/O Voltage Rails (Cont’d)

Send Feedback

Feature Descriptions

XC7Z045 (U1)

Bank

PS Bank 500

PS Bank 501 PHY_IF,SDIO_IF,USB_IF

PS Bank 502 PS_DDR3_IF

Notes:

1. The ZC706 evaluation board is shipped with V

Net Name Voltage Connected To

QSPI0,QSPI1

VCCP1V8 1.8V

set to 2.5V.

ADJ

DDR3 SODIMM Memory (PL)

[Figure 1-2, callout 2]

The memory module at J1 is a 1 GB DDR3 small outline dual-inline memory module (SODIMM). It provides volatile synchronous dynamic random access memory (SDRAM) for storing user code and data.

• Part number: MT8JTF12864HZ-1G6G1 (Micron Technology)

• Supply voltage: 1.5V

• Datapath width: 64 bits

• Data rate: Up to 1,600 MT/s

The DDR3 interface is implemented across the PL-side I/O banks. Bank 33 and bank 35 have a dedicated DCI VRP/N resistor connection. An external 0.75V reference VTTREF_SODIMM is provided for data interface banks. Any interface connected to these banks that requires the VTTREF voltage must use this FPGA voltage reference. The connections between the DDR3 memory and the AP SoC are listed in Tab le 1- 4.

Table 1-4: DDR3 SODIMM Socket J1 Connections to the XC7Z045 AP SoC

XC7Z045 (U1)

E10 PL_DDR3_A0 SSTL15 98 A0

B9 PL_DDR3_A1 SSTL15 97 A1

E11 PL_DDR3_A2 SSTL15 96 A2

A9 PL_DDR3_A3 SSTL15 95 A3

D11 PL_DDR3_A4 SSTL15 92 A4

B6 PL_DDR3_A5 SSTL15 91 A5

F9 PL_DDR3_A6 SSTL15 90 A6

E8 PL_DDR3_A7 SSTL15 86 A7

B10 PL_DDR3_A8 SSTL15 89 A8

Net Name I/O Standard

DDR3 SODIMM Memory J1

Pin Number Pin Name

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UG954 (v1.5) September 10, 2015

J8 PL_DDR3_A9 SSTL15 85 A9

Feature Descriptions

Send Feedback

Table 1-4: DDR3 SODIMM Socket J1 Connections to the XC7Z045 AP SoC (Cont’d)

XC7Z045 (U1)

D6 PL_DDR3_A10 SSTL15 107 A10/AP

B7 PL_DDR3_A11 SSTL15 84 A11

H12 PL_DDR3_A12 SSTL15 83 A12_BC_N

A10 PL_DDR3_A13 SSTL15 119 A13

G11 PL_DDR3_A14 SSTL15 80 A14

C6 PL_DDR3_A15 SSTL15 78 A15

F8 PL_DDR3_BA0 SSTL15 109 BA0

H7 PL_DDR3_BA1 SSTL15 108 BA1

A7 PL_DDR3_BA2 SSTL15 79 BA2

L1 PL_DDR3_D0 SSTL15 5 DQ0

L2 PL_DDR3_D1 SSTL15 7 DQ1

K5 PL_DDR3_D2 SSTL15 15 DQ2

J4 PL_DDR3_D3 SSTL15 17 DQ3

K1 PL_DDR3_D4 SSTL15 4 DQ4

L3 PL_DDR3_D5 SSTL15 6 DQ5

J5 PL_DDR3_D6 SSTL15 16 DQ6

K6 PL_DDR3_D7 SSTL15 18 DQ7

Net Name I/O Standard

DDR3 SODIMM Memory J1

Pin Number Pin Name

G6 PL_DDR3_D8 SSTL15 21 DQ8

H4 PL_DDR3_D9 SSTL15 23 DQ9

H6 PL_DDR3_D10 SSTL15 33 DQ10

H3 PL_DDR3_D11 SSTL15 35 DQ11

G1 PL_DDR3_D12 SSTL15 22 DQ12

H2 PL_DDR3_D13 SSTL15 24 DQ13

G5 PL_DDR3_D14 SSTL15 34 DQ14

G4 PL_DDR3_D15 SSTL15 36 DQ15

E2 PL_DDR3_D16 SSTL15 39 DQ16

E3 PL_DDR3_D17 SSTL15 41 DQ17

D4 PL_DDR3_D18 SSTL15 51 DQ18

E5 PL_DDR3_D19 SSTL15 53 DQ19

F4 PL_DDR3_D20 SSTL15 40 DQ20

F3 PL_DDR3_D21 SSTL15 42 DQ21

D1 PL_DDR3_D22 SSTL15 50 DQ22

D3 PL_DDR3_D23 SSTL15 52 DQ23

A2 PL_DDR3_D24 SSTL15 57 DQ24

B2 PL_DDR3_D25 SSTL15 59 DQ25

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UG954 (v1.5) September 10, 2015

Feature Descriptions

Send Feedback

Table 1-4: DDR3 SODIMM Socket J1 Connections to the XC7Z045 AP SoC (Cont’d)

XC7Z045 (U1)

B4 PL_DDR3_D26 SSTL15 67 DQ26

B5 PL_DDR3_D27 SSTL15 69 DQ27

A3 PL_DDR3_D28 SSTL15 56 DQ28

B1 PL_DDR3_D29 SSTL15 58 DQ29

C1 PL_DDR3_D30 SSTL15 68 DQ30

C4 PL_DDR3_D31 SSTL15 70 DQ31

K10 PL_DDR3_D32 SSTL15 129 DQ32

L9 PL_DDR3_D33 SSTL15 131 DQ33

K12 PL_DDR3_D34 SSTL15 141 DQ34

J9 PL_DDR3_D35 SSTL15 143 DQ35

K11 PL_DDR3_D36 SSTL15 130 DQ36

L10 PL_DDR3_D37 SSTL15 132 DQ37

J10 PL_DDR3_D38 SSTL15 140 DQ38

L7 PL_DDR3_D39 SSTL15 142 DQ39

F14 PL_DDR3_D40 SSTL15 147 DQ40

F15 PL_DDR3_D41 SSTL15 149 DQ41

F13 PL_DDR3_D42 SSTL15 157 DQ42

Net Name I/O Standard

DDR3 SODIMM Memory J1

Pin Number Pin Name

G16 PL_DDR3_D43 SSTL15 159 DQ43

G15 PL_DDR3_D44 SSTL15 146 DQ44

E12 PL_DDR3_D45 SSTL15 148 DQ45

D13 PL_DDR3_D46 SSTL15 158 DQ46

E13 PL_DDR3_D47 SSTL15 160 DQ47

D15 PL_DDR3_D48 SSTL15 163 DQ48

E15 PL_DDR3_D49 SSTL15 165 DQ49

D16 PL_DDR3_D50 SSTL15 175 DQ50

E16 PL_DDR3_D51 SSTL15 177 DQ51

C17 PL_DDR3_D52 SSTL15 164 DQ52

B16 PL_DDR3_D53 SSTL15 166 DQ53

D14 PL_DDR3_D54 SSTL15 174 DQ54

B17 PL_DDR3_D55 SSTL15 176 DQ55

B12 PL_DDR3_D56 SSTL15 181 DQ56

C12 PL_DDR3_D57 SSTL15 183 DQ57

A12 PL_DDR3_D58 SSTL15 191 DQ58

A14 PL_DDR3_D59 SSTL15 193 DQ59

A13 PL_DDR3_D60 SSTL15 180 DQ60

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UG954 (v1.5) September 10, 2015

Feature Descriptions

Send Feedback

Table 1-4: DDR3 SODIMM Socket J1 Connections to the XC7Z045 AP SoC (Cont’d)

XC7Z045 (U1)

B11 PL_DDR3_D61 SSTL15 182 DQ61

C14 PL_DDR3_D62 SSTL15 192 DQ62

B14 PL_DDR3_D63 SSTL15 194 DQ63

J3 PL_DDR3_DM0 SSTL15 11 DM0

F2 PL_DDR3_DM1 SSTL15 28 DM1

E1 PL_DDR3_DM2 SSTL15 46 DM2

C2 PL_DDR3_DM3 SSTL15 63 DM3

L12 PL_DDR3_DM4 SSTL15 136 DM4

G14 PL_DDR3_DM5 SSTL15 153 DM5

C16 PL_DDR3_DM6 SSTL15 170 DM6

C11 PL_DDR3_DM7 SSTL15 187 DM7

K2 PL_DDR3_DQS0_N DIFF_SSTL15 10 DQS0_N

K3 PL_DDR3_DQS0_P DIFF_SSTL15 12 DQS0_P

H1 PL_DDR3_DQS1_N DIFF_SSTL15 27 DQS1_N

J1 PL_DDR3_DQS1_P DIFF_SSTL15 29 DQS1_P

D5 PL_DDR3_DQS2_N DIFF_SSTL15 45 DQS2_N

E6 PL_DDR3_DQS2_P DIFF_SSTL15 47 DQS2_P

Net Name I/O Standard

DDR3 SODIMM Memory J1

Pin Number Pin Name

A4 PL_DDR3_DQS3_N DIFF_SSTL15 62 DQS3_N

A5 PL_DDR3_DQS3_P DIFF_SSTL15 64 DQS3_P

K8 PL_DDR3_DQS4_N DIFF_SSTL15 135 DQS4_N

L8 PL_DDR3_DQS4_P DIFF_SSTL15 137 DQS4_P

F12 PL_DDR3_DQS5_N DIFF_SSTL15 152 DQS5_N

G12 PL_DDR3_DQS5_P DIFF_SSTL15 154 DQS5_P

E17 PL_DDR3_DQS6_N DIFF_SSTL15 169 DQS6_N

F17 PL_DDR3_DQS6_P DIFF_SSTL15 171 DQS6_P

A15 PL_DDR3_DQS7_N DIFF_SSTL15 186 DQS7_N

B15 PL_DDR3_DQS7_P DIFF_SSTL15 188 DQS7_P

G7 PL_DDR3_ODT0 SSTL15 116 ODT0

C9 PL_DDR3_ODT1 SSTL15 120 ODT1

G17 PL_DDR3_RESET_B SSTL15 30 RESET_B

J11 PL_DDR3_S0_B SSTL15 114 S0_B

H8 PL_DDR3_S1_B SSTL15 121 S1_B

M10 PL_DDR3_TEMP_EVE

F7 PL_DDR3_WE_B SSTL15 113 WE_B

SSTL15 198 EVENT_B

ZC706 Evaluation Board User Guide www.xilinx.com 21

UG954 (v1.5) September 10, 2015

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Table 1-4: DDR3 SODIMM Socket J1 Connections to the XC7Z045 AP SoC (Cont’d)

XC7Z045 (U1)

E7 PL_DDR3_CAS_B SSTL15 115 CAS_B

H11 PL_DDR3_RAS_B SSTL15 110 RAS_B

D10 PL_DDR3_CKE0 SSTL15 73 CKE0

C7 PL_DDR3_CKE1 SSTL15 74 CKE1

F10 PL_DDR3_CLK0_N DIFF_SSTL15 103 CK0_N

G10 PL_DDR3_CLK0_P DIFF_SSTL15 101 CK0_P

D8 PL_DDR3_CLK1_N DIFF_SSTL15 104 CK1_N

D9 PL_DDR3_CLK1_P DIFF_SSTL15 102 CK1_P

Net Name I/O Standard

DDR3 SODIMM Memory J1

Pin Number Pin Name

The ZC706 DDR3 SODIMM interface adheres to the constraints guidelines documented in the “Dynamic Memory” section of the Zynq-7000 All Programmable SoC PCB Design and Pin Planning Guide (UG933

). The ZC706 DDR3 SODIMM interface is a 40Ω impedance

implementation. For more details, see the MT8JTF12864HZ-1G6G1 data sheet [Ref 34].

DDR3 Component Memory (PS)

[Figure 1-2, callout 3]

The 1 GB, 32-bit wide DDR3 component memory system is comprised of four 256 Mb x 8 SDRAMs (Micron MT41J256M8HX-15E) at U2-U5. This memory system is connected to the XC7Z045 AP SoC Processing System (PS) memory interface bank 502. The DDR3 0.75V VTT termination voltage is sourced from linear regulator U27. The connections between the DDR3 component memory and XC7Z045 AP SoC bank 502 are listed in Tab le 1 -5.

Table 1-5: DDR3 Component Memory Connections to the XC7Z045 AP SoC

Component Memory

XC7Z045 (U1) Pin Net Name

Pin Number Pin Name Ref. Des.

E26 PS_DDR3_DQ0 B3 DQ0 U2

A25 PS_DDR3_DQ1 C7 DQ1 U2

E27 PS_DDR3_DQ2 C2 DQ2 U2

E25 PS_DDR3_DQ3 C8 DQ3 U2

D26 PS_DDR3_DQ4 E3 DQ4 U2

B25 PS_DDR3_DQ5 E8 DQ5 U2

D25 PS_DDR3_DQ6 D2 DQ6 U2

B27 PS_DDR3_DQ7 E7 DQ7 U2

A27 PS_DDR3_DQ8 B3 DQ8 U3

A28 PS_DDR3_DQ9 C7 DQ9 U3

A29 PS_DDR3_DQ10 C2 DQ10 U3

ZC706 Evaluation Board User Guide www.xilinx.com 22

UG954 (v1.5) September 10, 2015

Feature Descriptions

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Table 1-5: DDR3 Component Memory Connections to the XC7Z045 AP SoC (Cont’d)

XC7Z045 (U1) Pin Net Name

C28 PS_DDR3_DQ11 C8 DQ11 U3

D30 PS_DDR3_DQ12 E3 DQ12 U3

A30 PS_DDR3_DQ13 E8 DQ13 U3

D29 PS_DDR3_DQ14 D2 DQ14 U3

D28 PS_DDR3_DQ15 E7 DQ15 U3

H27 PS_DDR3_DQ16 B3 DQ16 U4

G27 PS_DDR3_DQ17 C7 DQ17 U4

H28 PS_DDR3_DQ18 C2 DQ18 U4

E28 PS_DDR3_DQ19 C8 DQ19 U4

E30 PS_DDR3_DQ20 E3 DQ20 U4

F28 PS_DDR3_DQ21 E8 DQ21 U4

G30 PS_DDR3_DQ22 D2 DQ22 U4

F30 PS_DDR3_DQ23 E7 DQ23 U4

K27 PS_DDR3_DQ24 B3 DQ24 U5

J30 PS_DDR3_DQ25 C7 DQ25 U5

J28 PS_DDR3_DQ26 C2 DQ26 U5

J29 PS_DDR3_DQ27 C8 DQ27 U5

Component Memory

Pin Number Pin Name Ref. Des.

K30 PS_DDR3_DQ28 E3 DQ28 U5

M29 PS_DDR3_DQ29 E8 DQ29 U5

L30 PS_DDR3_DQ30 D2 DQ30 U5

M30 PS_DDR3_DQ31 E7 DQ31 U5

C27 PS_DDR3_DM0 B7 DM0 U2

C26 PS_DDR3_DQS0_P C3 DQS0_P U2

B26 PS_DDR3_DQS0_N D3 DQS0_N U2

B30 PS_DDR3_DM1 B7 DM1 U3

C29 PS_DDR3_DQS1_P C3 DQS1_P U3

B29 PS_DDR3_DQS1_N D3 DQS1_N U3

H29 PS_DDR3_DM2 B7 DM2 U4

G29 PS_DDR3_DQS2_P C3 DQS2_P U4

F29 PS_DDR3_DQS2_N D3 DQS2_N U4

K28 PS_DDR3_DM3 B7 DM3 U5

L28 PS_DDR3_DQS3_P C3 DQS3_P U5

L29 PS_DDR3_DQS3_N D3 DQS3_N U5

L25 PS_DDR3_A0 K3 A0 U2, U3, U4, U5

K26 PS_DDR3_A1 L7 A1 U2, U3, U4, U5

ZC706 Evaluation Board User Guide www.xilinx.com 23

UG954 (v1.5) September 10, 2015

Feature Descriptions

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Table 1-5: DDR3 Component Memory Connections to the XC7Z045 AP SoC (Cont’d)

XC7Z045 (U1) Pin Net Name

L27 PS_DDR3_A2 L3 A2 U2, U3, U4, U5

G25 PS_DDR3_A3 K2 A3 U2, U3, U4, U5

J26 PS_DDR3_A4 L8 A4 U2, U3, U4, U5

G24 PS_DDR3_A5 L2 A5 U2, U3, U4, U5

H26 PS_DDR3_A6 M8 A6 U2, U3, U4, U5

K22 PS_DDR3_A7 M2 A7 U2, U3, U4, U5

F27 PS_DDR3_A8 N8 A8 U2, U3, U4, U5

J23 PS_DDR3_A9 M3 A9 U2, U3, U4, U5

G26 PS_DDR3_A10 H7 A10 U2, U3, U4, U5

H24 PS_DDR3_A11 M7 A11 U2, U3, U4, U5

K23 PS_DDR3_A12 K7 A12 U2, U3, U4, U5

H23 PS_DDR3_A13 N3 A13 U2, U3, U4, U5

J24 PS_DDR3_A14 N7 A14 U2, U3, U4, U5

M27 PS_DDR3_BA0 J2 BA0 U2, U3, U4, U5

M26 PS_DDR3_BA1 K8 BA1 U2, U3, U4, U5

M25 PS_DDR3_BA2 J3 BA2 U2, U3, U4, U5

K25 PS_DDR3_CLK_P F7 CK U2, U3, U4, U5

Component Memory

Pin Number Pin Name Ref. Des.

J25 PS_DDR3_CLK_N G7 CK_B U2, U3, U4, U5

M22 PS_DDR3_CKE G9 CKE U2, U3, U4, U5

N23 PS_DDR3_WE_B H3 WE_B U2, U3, U4, U5

M24 PS_DDR3_CAS_B G3 CAS_B U2, U3, U4, U5

N24 PS_DDR3_RAS_B F3 RAS_B U2, U3, U4, U5

F25 PS_DDR3_RESET_B N2 RESET_B U2, U3, U4, U5

N22 PS_DDR3_CS_B H2 CS_B U2, U3, U4, U5

L23 PS_DDR3_ODT G1 ODT U2, U3, U4, U5

N21 PS_VRN

M21 PS_VRP

L22 VTTVREF_PS

L24 VTTVREF_PS

The ZC706 DDR3 component interface adheres to the constraints guidelines documented in the DDR3 Design Guidelines section of Zynq-7000 All Programmable SoC PCB Design and Pin Planning Guide (UG933

). The ZC706 DDR3 component interface is a 40Ω impedance

implementation. For more details, see the MT41J256M8HX-15E data sheet [Ref 34].

ZC706 Evaluation Board User Guide www.xilinx.com 24

UG954 (v1.5) September 10, 2015

Quad-SPI Flash Memory

Send Feedback

[Figure 1-2, callout 4]

The Quad-SPI flash memory located at U58 and U59 provides 2 x 128 Mb of nonvolatile storage that can be used for configuration and data storage.

• Part number: S25FL128SAGMFIR01 (Spansion)

•Supply voltage: 1.8V

• Datapath width: 4 bits

• Data rate: Various depending on Single/Dual/Quad mode

The connections between the SPI flash memory and the XC7Z045 AP SoC are listed in

Tab le 1- 6.

Table 1-6: Quad-SPI Flash Memory Connections to the XC7Z045 AP SoC

Feature Descriptions

XC7Z045 (U1)

Pin Name Bank Pin Number Pin Number Pin Name Ref. Des.

PS_MIO6 500 D24 QSPI0_CLK

PS_MIO5 500 C24 QSPI0_IO3

PS_MIO4 500 E23 QSPI0_IO2

PS_MIO3 500 C23 QSPI0_IO1

PS_MIO2 500 F23 QSPI0_IO0

PS_MIO1 500 D23 QSPI0_CS_B

PS_MIO9 500 A24 QSPI1_CLK

PS_MIO13 500 F22 QSPI1_IO3

PS_MIO12 500 E21 QSPI1_IO2

PS_MIO11 500 A23 QSPI1_IO1

PS_MIO10 500 E22 QSPI1_IO0

PS_MIO0 500 F24 QSPI1_CS_B

Schematic Net Name

Quad-SPI Flash Memory QSPI Device

16 C U58 J74.2

1 DQ3_HOLD_B U58 J73.2

9 WP_B U58 J72.2

8 DQ1 U58 J71.2

15 DQ0 U58 J70.2

7S_BU58N/A

16 C U59 N/A

1DQ3_HOLD_BU59 N/A

9WP_BU59N/A

8DQ1U59N/A

15 DQ0 U59 N/A

7S_BU59N/A

The configuration section of the Zynq-7000 All Programmable SoC Technical Reference

Manual UG585

, provides details on using the Quad-SPI flash memory.

MIO Select

Header

ZC706 Evaluation Board User Guide www.xilinx.com 25

UG954 (v1.5) September 10, 2015

Figure 1-6 shows the connections of the linear Quad-SPI flash memory on the ZC706

evaluation board. For more details, see the Spansion S25FL128SAGMFIR01 data sheet

[Ref 16].

X-Ref Target - Figure 1-6

Send Feedback

Feature Descriptions

VCCP1V8 VCC3V3_PS VCCP1V8

C39

0.1UF 25V

X5R

GND

QSPI0_IO3

QSPI0_CS_B QSPI0_IO1

C40

0.1UF 25V

X5R

C714

R531

R207

330 1/10W

0 1/10W

R527

DNP DNP

DNP

R528

DNP DNP

DNP

GND

0.1UF 25V X5R

S25FL128SAGMFIR01

QSPI0_CLK

QSPI0_IO0

QSPI0_IO2

NC NC NC NC

DQ3_HOLD_B

VCC

NC0

NC1

NC2

NC3

S_B

DQ1

DQ0 NC7 NC6 NC5 NC4 VSS

DQ2_VPP_WP_B

15 14 13

NC 10 9

SO16_50P300X413U58

GND

VCCP1V8 VCC3V3_PS VCCP1V8

C715

R532

R208

330 1/10W

0 1/10W

R530

DNP DNP

DNP

R529

DNP DNP

DNP

0.1UF 25V

X5R

QSPI1_IO3

QSPI1_CS_B QSPI1_IO1

S25FL128SAGMFIR01

NC NC NC NC

DQ3_HOLD_B

VCC

NC0

NC1

NC2

NC3

S_B

DQ1

DQ2_VPP_WP_B

DQ0 NC7 NC6 NC5 NC4 VSS

15 14 13

NC 12

NC 11

NC 10 9

SO16_50P300X413U59

GND

Figure 1-6: 128 Mb Quad-SPI Flash Memory

QSPI1_CLK

QSPI1_IO0

QSPI1_IO2

UG954_c1_06_073013

ZC706 Evaluation Board User Guide www.xilinx.com 26

UG954 (v1.5) September 10, 2015

Feature Descriptions

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USB 2.0 ULPI Transceiver

[Figure 1-2, callout 19]

The ZC706 evaluation board uses a Standard Microsystems Corporation USB3320 USB 2.0 ULPI Transceiver at U12 to support a USB connection to the host computer. A USB cable is supplied in the ZC706 evaluation kit (Standard-A connector to host computer, Micro-B connector to ZC706 evaluation board connector J2). The USB3320 is a high-speed USB 2.0 PHY supporting the UTMI+ low pin interface (ULPI) interface standard. The ULPI standard defines the interface between the USB controller IP and the PHY device which drives the physical USB bus. Use of the ULPI standard reduces the interface pin count between the USB controller IP and the PHY device.

The USB3320 is clocked by a 24 MHz crystal. Consult the SMSC USB3320 data sheet for clocking mode details [Ref 17].

The interface to the USB3320 transceiver is implemented through the IP in the XC7Z045 AP SoC Processor System.

Tab le 1- 7 describes the jumper settings for the USB 2.0 circuit. Bold text identifies the

default OTG mode settings.

Table 1-7: USB Jumper Settings

Header Function Shunt Position Notes

J11

J10

J48

J50

J49

J51

USB PHY reset Shunt ON = USB PHY reset

Shunt OFF = USB PHY normal operation

5V Supply Shunt ON = Host or OTG mode

BUS

RVBUS select Position 1–2 = Device mode only (10 KΩ )

CVBUS select Position 1-2 = OTG and Device mode 1 μF

Cable ID select Position 1-2 = A/B cable detect

USB Micro-B Position 1-2 = Shield connected to GND

Shunt OFF = Device mode

Position 2–3 = OTG or Host mode (1 KΩ )

Position 2-3 = Host mode 120 μF

Position 2-3 = ID not used

Position 2-3 = Shield floating

Clean reset requires external debouncing

Overvoltage protection

load capacitance

BUS

Used in OTG mode

ZC706 Evaluation Board User Guide www.xilinx.com 27

UG954 (v1.5) September 10, 2015

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The connections between the USB Micro-B connector at J2 and the PHY at U12 are listed in

Tab le 1- 8.

Table 1-8: USB Connector Pin Assignments and Signal Definitions Between J2 and U12

USB Connector

Net Name Description

Pin Name

1 VBUS USB_VBUS_SEL +5V from host system 22

2 D_N USB_D_N Bidirectional differential serial data (N-side) 19

3 D_P USB_D_P Bidirectional differential serial data (P-side) 18

5 GND GND Signal ground 33

The connections between the USB 2.0 PHY at U12 and the XC7Z045 AP SoC are listed in

Tab le 1- 9.

Table 1-9: USB 2.0 ULPI Transceiver Connections to the XC7Z045 AP SoC

XC7Z045 (U1)

Schematic Net Name USB3320 (U12) Pin

Pin Name Bank Pin Number

PS_MIO36 501 H17 USB_CLKOUT 1

PS_MIO31 501 H21 USB_NXT 2

PS_MIO32 501 K17 USB_DATA0 3

PS_MIO33 501 G22 USB_DATA1 4

USB3320 (U12)

PS_MIO34 501 K18 USB_DATA2 5

PS_MIO35 501 G21 USB_DATA3 6

PS_MIO28 501 L17 USB_DATA4 7

PS_MIO37 501 B21 USB_DATA5 9

PS_MIO38 501 A20 USB_DATA6 10

PS_MIO39 501 F18 USB_DATA7 13

PS_MIO30 501 L18 USB_STP 29

PS_MIO29 501 E8 USB_DIR 31

PS_MIO7 500 D5 USB_RESET_B_AND 27 (via AND gate U13)

For additional information on the Zynq-7000 AP SoC device USB controllers, see Zynq-7000

All Programmable SoC Overview (DS190 Reference Manual (UG585

) and Zynq-7000 All Programmable SoC Technical

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UG954 (v1.5) September 10, 2015

X-Ref Target - Figure 1-7

Send Feedback

Feature Descriptions

Figure 1-7 shows the USB 2.0 ULPI transceiver circuitry. Note that the shield for the USB

Micro-B connector (J2) can be tied to GND by a jumper on header J51 pins 1–2 (default). The USB shield can optionally be connected through a capacitor to GND by installing a capacitor (body size 0402) at location C335 and jumping pins 2-3 on header J51.

USB_CLKOUT

USB_NXT

USB_DATA0

USB_DATA1

USB_DATA2

USB_DATA3

USB_DATA4

VCCP1V8

3 PLACES

2 PLACES

VCCMIO

C70 C71 C74

0.1UF 2

25V

GND

USB3320_QFN32

CLKOUT_1

NXT_2

DATA0_3

DATA1_4

DATA2_5

DATA3_6

DATA4_7

REFSEL0_8

U12

USB_DIR

USB_STP

USB_RESET_B

VDD18_30

REFSEL1_11

STP_29

NC_12

VDD18_28

DATA7_13

13415 26

USB_DATA7

RESETB_27

REFSEL2_14

SPK_L_15 REFCLK_26

R389

1/10W

R403

16 25

261

1.0M

1/10W

XO_25

SPK_R_16

VCC3V3

CTR_GND_33

USB3320_QFN32

RBIAS_23

VBUS_22

VBAT_21

VDD33_P

CPEN33_17

DIR_31

VDDIO_32

DATA6_10

DATA5_9

USB_DATA5

USB_DATA6

C496

18PF

50V NPO

GND

USB_ID

ID_23

USB_D_N

DM_19

USB_D_P

DP_18

GND

DS25

LED-RED-SMT

C497

24.000MHZ

18PF

50V NPO

GND

R178

8.06K

1/10W

USB_VDD33

C209

2.2UF

6.3V

GND

R267

10.0K 1/10W

1-2 = DEVICE MODE 2-3 = HOST OR OTG MODE

USB HOST POWER

MIC2025_SOP8

EN OUT2

FLG

GND

NC1

U22

GND

VCC5V0

2125V

GND

R359

1.00K 1/16W

J48

OUT1

NC2

SOP127P500X600_8

C72

0.1UF

USB_VBUS_SEL

VCC5V0

GND

J10

C76

0.1UF 25V

USB_VBUS_SEL

C380

1UF

16V

J50

X5R

CVBUS Select: 1-2: OTG Mode 2-3: Host Mode

GND

ON = HOST OR OTG MODE OFF = DEVICE MODE

C469

150UF

10V TANT

GND

L11

FERRITE-220

C447

5.6UF 2

10V

FERRITE-220

GND

C75

0.1UF

25V

L12

J49

C484

120UF 20V TANT

GND

1-2 = A/B CABLE DETECT 2-3 = ID NOT USED

USB_D_N

USB_D_P

USB_ID

USB_VDD33

ZX62D_AB_5P8

VBUS

D_N

D_P

GND

SHLD1

SHLD2

SHLD3

SHLD4

SHLD5

J51

UG954_c1_07_041113

SHLD6

123

C335

DNP

GND

Figure 1-7: USB 2.0 ULPI Transceiver

SD Card Interface

[Figure 1-2, callout 5]

The ZC706 evaluation board includes a secure digital input/output (SDIO) interface to provide user-logic access to general purpose nonvolatile SDIO memory cards and peripherals. Information for the SD I/O card specification can be found at the SanDisk and SD card websites [Ref 18], [Ref 19].

The SDIO signals are connected to XC7Z045 AP SoC PS bank 501 which has its VCCMIO set to 1.8V. A MAX13035E high-speed logic-level translator (U11) is used between XC7Z045 AP SoC 1.8V PS bank 501 and the 3.3V SD card connector (J30).

ZC706 Evaluation Board User Guide www.xilinx.com 29

UG954 (v1.5) September 10, 2015

X-Ref Target - Figure 1-8

Send Feedback

Feature Descriptions

Figure 1-8 shows the connections of the SD card interface on the ZC706 evaluation board.

VCCP1V8

R28

4.7 KΩ 1/10W 5%

R29

4.7 KΩ 1/10W

VCC3V3_PS

GND

C41

0.1 μF 25V X5R

GND

67840-8001

CD_DAT3

CMD

VSS1

VDD

CLK

VSS2

DAT0

DAT1

DAT2

DETECT

PROTECT

DETECT_PROTECT

J30

IOGND2

IOGND1 GNDTAB4 GNDTAB3 GNDTAB2 GNDTAB1

UG954_c1_08_041113

18 17 16 15 14 13

GND

SDIO_CD_DAT322

22 SDIO_CMD

22 SDIO_CLK

SDIO_DAT022

22 SDIO_DAT1

SDIO_DAT222

SDIO_SDDET8 SDIO_SDWP8

Figure 1-8: SD Card Interface

Tab le 1- 10 lists the SD card interface connections to the XC7Z045 AP SoC

Table 1-10: SDIO Connections to the XC7Z045 AP SoC

XC7Z045 (U1) Pin

Level Shifter (U11) SDIO Connector (J30)

Schematic

Pin Name Bank

Number

Net Name

PS_MIO15 500 C22 SDIO_SDWP N/A N/A 11 PROTECT

1.8V Side Pin

3.3V Side Pin

Number

Name

PS_MIO14 500 B22 SDIO_SDDET N/A N/A 10 DETECT

PS_MIO41 501 J18 SDIO_CMD_LS 4 20 2 CMD

PS_MIO40 501 B20 SDIO_CLK_LS 9 19 5 CLK

PS_MIO44 501 E20 SDIO_DAT2_LS 1 23 9 DAT2

PS_MIO43 501 E18 SDIO_DAT1_LS 7 16 8 DAT1

PS_MIO42 501 D20 SDIO_DAT0_LS 6 18 7 DAT0

PS_MIO45 501 H18 SDIO_CD_DAT3_LS 3 22 1 CD_DAT3

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UG954 (v1.5) September 10, 2015

X-Ref Target - Figure 1-9

Send Feedback

U30

J62

Programmable Logic JTAG Programming Options

[Figure 1-2, callout 6]

The ZC706 evaluation board JTAG chain is shown in Figure 1-9.

SPST Bus Switch U31

FMC LPC

Connector

TDI

TDO

JTAG

Header

TDO

TDI

JTAG

Module

TDO

TDI

JTAG

Header

TDO

TDI

U45 U46 U47

3:1

Analog

Switch

SW4

SPST Bus Switch U32

N.C. N.C.

J37

FMC HPC

Connector

TDI

TDO

3.3V3.3V

U10

SN74AVC2T245

and

SN74LV541APWR

Buffers

TDI TDO

Feature Descriptions

Zynq-7000

XC7Z045

AP SoC

TDI

TDO

UG954_c1_09_041113

Figure 1-9: JTAG Chain Block Diagram

Programmable Logic JTAG Select Switch

[Figure 1-2, callout 35]

The PL JTAG chain can be programmed by three different methods made available through a 3-to-1 analog switch (U45, U46, and U47) controlled by a 2-position DIP switch at SW4.

Figure 1-10 shows the JTAG analog switches and DIP switch SW4.

ZC706 Evaluation Board User Guide www.xilinx.com 31

UG954 (v1.5) September 10, 2015

X-Ref Target - Figure 1-10

Send Feedback

Feature Descriptions

VCC3V3

To J3

Parallel Cable or

Platform Cable

(14 pins)

To U30

USB-to-JTAG

Digilent bridge

To J62

Parallel Cable

(20 Pins)

14PIN_JTAG_TDI

14PIN_JTAG_TMS

14PIN_JTAG_TCK

DIGILENT_TDI

DIGILENT_TMS

DIGILENT_TCK

20PIN_JTAG_TDI

20PIN_JTAG_TMS

20PIN_JTAG_TCK

U45

TS5A3359

ANALOG SWITCH

NO0

NO1

NO2

GND

U46

TS5A3359

ANALOG SWITCH

NO0

NO1

NO2

GND

U47

TS5A3359

ANALOG SWITCH

NO0

NO1

NO2

GND

SP3T

IN1

IN2

IN1

IN2

IN1

IN2

COM

V+

VCC3V3

SW4

SDA02H1SBD

JTAG_SEL_1

JTAG_SEL_2

R21

4.7kΩ

0.1 W 5%

R20

4.7kΩ

0.1 W 5%

GND

JTAG_TDI

JTAG_TMS

JTAG_TCK

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UG954 (v1.5) September 10, 2015

UG954_c1_10_041113

Figure 1-10: PL JTAG Programming Source Analog Switch

DIP switch SW4[1:2] setting 10 selects the 14-pin header J3 for configuration using either a Parallel Cable IV (PC4) or Platform Cable USB II. DIP switch SW4 setting 01 selects the USB-to-JTAG Digilent bridge U30 for configuration over a Standard-A to Micro-B USB cable. DIP switch SW4 setting 11 selects the JTAG 20-pin header at J62. The four JTAG signals TDI, TDO, TCK, and TMS would be connected to J62 through flying leads from a JTAG cable. The 3-to-1 analog switch settings are shown in Tabl e 1-1 1.

Table 1-11: Switch SW4 Configuration Option Settings

Send Feedback

Feature Descriptions

Configuration Source

None

Cable Connector J3

Digilent USB-to-JTAG interface U30

JTAG (flying lead) Header J62

Notes:

1. 0 = open, 1 = closed

2. Default switch setting

(2)

FMC Connector JTAG Bypass

When an FPGA mezzanine card (FMC) is attached to HPC J37 or LPC J5 it is automatically added to the JTAG chain through electronically controlled single-pole single-throw (SPST) switches U32 and U31 respectively. The SPST switches are normally closed and transition to an open state when an FMC is attached. Switch U32 adds an attached FMC to the JTAG chain as determined by the FMC_HPC_PRSNT_M2C_B signal. Switch U31 adds an attached FMC to the JTAG chain as determined by the FMC_LPC_PRSNT_M2C_B signal. The attached FMC card must implement a TDI-to-TDO connection through a device or bypass jumper for the JTAG chain to be completed to the AP SoC U1.

Switch 1

DIP Switch SW4

(1)

JTAG_SEL_1 Switch 2

(1)

JTAG_SEL_2

The JTAG connectivity on the ZC706 board allows a host computer to download bitstreams to the AP SoC using the Xilinx® iMPACT software. In addition, the JTAG connector allows debug tools such as the Vivado serial I/O analyzer or a software debugger to access the SoC. The iMPACT software tool can also indirectly program the linear QSPI flash memory. To accomplish this, the iMPACT software configures the SoC with a temporary design to access and program the QSPI memory device.

Clock Generation

[Figure 1-2, callouts 7, 8, and 9]

The ZC706 evaluation board provides four clock sources for the XC7Z045 AP SoC.

Tab le 1- 12 lists the source devices for each clock.

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UG954 (v1.5) September 10, 2015

Table 1-12: ZC706 Evaluation Board Clock Sources

Send Feedback

Clock Name Clock Source Description

Feature Descriptions

System Clock U64

User Clock U37

User SMA Clock J67(P), J68(N)

PS Clock U24

GTX SMA REF Clock J36(P), J31(N)

Jitter Attenuated Clock U60

Tab le 1- 13 lists the pin-to-pin connections from each clock source to the XC7Z045 AP SoC.

Table 1-13: Clock Connections, Source to XC7Z045 AP SoC

Clock Source Pin Net Name I/O Standard XC7Z045 (U1) Pin

U64.5

U64.4

U37.5

SYSCLK_N

SYSCLK_P

USRCLK_N

SiT9102 2.5V LVDS 200 MHz fixed-frequency oscillator (SiTime). See System Clock, page 34.

Si570 3.3V LVDS I (Silicon Labs). See Programmable User Clock, page 35.

User clock input SMAs, limit input swing voltage to VADJ_FPGA setting (1.8V, 2.5V, 3.3V). See User SMA Clock Source, page 36.

SIT8103 1.8V single-ended CMOS 33.3333 MHz fixed frequency oscillator (SiTime). See Processing System Clock Source, page 37.

User clock input SMAs. See GTX SMA Clock (SMA_MGT_REFCLK_P and

SMA_MGT_REFCLK_N), page 37.

Si5324C LVDS precision clock multiplier/jitter attenuator (Silicon Labs). See Jitter Attenuated Clock, page 38.

C programmable oscillator, 156.250 MHz default

LVDS G9

LVDS H9

LVDS_25 AG14

U37.4

J67.1

J68.1

J24.3

J36.1

J31.1

U60.29

U60.28

U60.17

U60.16

U60.3

U60.1

Notes:

1. PS-side and GTX nets do not have an assigned I/O standard.

USRCLK_P

USER_SMA_CLOCK_P

USER_SMA_CLOCK_N

PS_CLK

SMA_MGT_REFCLK_P

SMA_MGT_REFCLK_N

SI5324_OUT_C_N

SI5324_OUT_C_P

REC_CLOCK_C_N

REC_CLOCK_C_P

SI5324_INT_ALM_LS

SI5324_RST_LS

LVDS_25 AF14

LVDS_25 AD18

LVDS_25 AD19

NA(1) A22 (Bank 500)

NA(1) W8

NA(1) W7

NA(1) AC7

NA(1) AC8

LVDS_25 AE20

LVDS_25 AD20

LVCMOS25 AJ25

LVCMOS25 W23

System Clock

[Figure 1-2, callout 7]

ZC706 Evaluation Board User Guide www.xilinx.com 34

UG954 (v1.5) September 10, 2015

Feature Descriptions

UG954_c1_11_041113

GND

VCC2V5

SIT9102

200 MHz

Oscillator

OE NC GND

VCC

OUT_B

OUT

1 2 3

6 5 4

U64

R322 100Ω 1/20W 5%

SYSCLK_P

SYSCLK_N

C89

0.1 µF 10V X5R

Send Feedback

The system clock source is an LVDS 200 MHz oscillator at U64. It is wired to a multi-region clock capable (MRCC) input on programmable logic (PL) bank 34. The signal pair is named SYSCLK_P and SYSCLK_N and each signal is connected to U1 (pins H9 and G9, respectively) on the XC7Z045 AP SoC.

• Oscillator: SiTime SiT9102AI-243N25E200.00000 (200 MHz)

• Frequency tolerance: 50 ppm

• LVDS Differential Output

The system clock circuit is shown in Figure 1-11.

X-Ref Target - Figure 1-11

Figure 1-11: System Clock Source

For more details, see the SiTime SiT9102 data sheet [Ref 20].

Programmable User Clock

[Figure 1-2, callout 8]

The ZC706 evaluation board has a programmable low-jitter 3.3V LVDS differential oscillator (U37) connected to the MRCC inputs of bank 10. This USRCLK_P and USRCLK_N clock signal pair is connected to XC7Z045 AP SoC U1 pins AF14 and AG14, respectively. On power-up the user clock defaults to an output frequency of 156.250 MHz. User applications can change the output frequency within the range of 10 MHz to 810 MHz through an I interface. Power cycling the ZC706 evaluation board reverts the user clock to the default frequency of 156.250 MHz.

• Programmable Oscillator: Silicon Labs Si570BAB0000544DG (10 MHz–810 MHz)

• Frequency tolerance: 50 ppm

• LVDS Differential Output

ZC706 Evaluation Board User Guide www.xilinx.com 35

UG954 (v1.5) September 10, 2015

The user clock circuit is shown in Figure 1-12.

UG954_c1_12_041113

GND

VCC3V3

1 2

U37

R37

4.7KΩ 1/10W 5%

C348

0.01 μF 25V X7R

GND

VCC3V3

10 MHz-810 MHz

50PPM

Si570

Programmable

Oscillator

NC OE

GND

SCL

SDA

VDD

OUT_B-

OUT+

R323 100Ω 1/20W 5%

USRCLK SFP SDA

USRCLK SFP SCL

USRCLK N

USRCLK P

Send Feedback

X-Ref Target - Figure 1-12

Figure 1-12: User Clock Source

Feature Descriptions

See the Silicon Labs Si570 data sheet [Ref 21].

User SMA Clock Source

The ZC706 board provides a pair of SMAs for differential user clock input into PL Bank 9 (see

Figure 1-13). The P-side SMA J67 signal USER_SMA_CLOCK_P is connected to U1 pin AD18,

with the N-side SMA J68 signal USER_SMA_CLOCK_N connected to U1 pin AD19. Bank 9 Vcco is VADJ_FPGA, a variable voltage (1.8V, 2.5V, 3.3V) depending on the ZC706 FMC interface banks voltage. The USER_SMA_CLOCK input voltage swing should not exceed the board VADJ_FPGA voltage setting.

X-Ref Target - Figure 1-13

ZC706 Evaluation Board User Guide www.xilinx.com 36

UG954 (v1.5) September 10, 2015

Figure 1-13: User SMA Clock

UG954_c1_13_041113

Feature Descriptions

Send Feedback

Processing System Clock Source

The Processing System (PS) clock source is a 1.8V LVCMOS single-ended fixed

33.33333 MHz oscillator at U24. It is wired to PS bank 500, pin A22 (PS_CLK), on the XC7Z045 AP SoC.

• Oscillator: SiTime SiT8103AC-23-18E-33.33333 (33.3 MHz)

• Frequency tolerance: 50 ppm

• Single-ended output

The system clock circuit is shown in Figure 1-14.

X-Ref Target - Figure 1-14

VCCP1V8

R38

4.7KΩ

1/10W 5%

U24

SiT8103

Oscillator

33.33333 MHz 50 PPM

VCC

VCCP1V8

C349

0.01 μF 25V

X7R

GND

OUT

R173

24.9Ω 1/10W 1%

PS CLK

UG954_c1_14_041113

GND

Figure 1-14: Processing System Clock Source

For more details, see the SiTime SiT8103 data sheet [Ref 20].

GTX SMA Clock (SMA_MGT_REFCLK_P and SMA_MGT_REFCLK_N)

[Figure 1-2, callout 10]

The ZC706 board includes a pair of SMA connectors for a GTX clock wired to GTX Quad bank

111. This differential clock has signal names SMA_MGT_REFCLK_P and SMA_REFCLK_N, which are connected to AP SoC U1 pins W8 and W7 respectively.

• External user-provided GTX reference clock on SMA input connectors

• Differential Input

ZC706 Evaluation Board User Guide www.xilinx.com 37

UG954 (v1.5) September 10, 2015

Figure 1-15 shows this AC-coupled clock circuit.

Send Feedback

X-Ref Target - Figure 1-15

J36

SMA

Connector

J31

GND

SMA

Connector

C145

0.01 μF 25V X7R

C144

0.01 μF 25V X7R

Feature Descriptions

SMA_MGT_REFCLK_PSMA_MGT_REFCLK_C_P

SMA_MGT_REFCLK_NSMA_MGT_REFCLK_C_N

GND

UG954_c1_15_041113

Figure 1-15: GTX SMA Clock Source

Jitter Attenuated Clock

[Figure 1-2, callout 11]

The ZC706 board includes a Silicon Labs Si5324 jitter attenuator U60 on the back side of the board. AP SoC user logic can implement a clock recovery circuit and then output this clock to a differential I/O pair on I/O bank 9 (REC_CLOCK_C_P, AP SoC U1 pin AD20 and REC_CLOCK_C_N, AP SoC U1 pin AE20) for jitter attenuation. The jitter attenuated clock (Si5324_OUT_C_P, Si5324_OUT_C_N) is then routed as a reference clock to GTX Quad 110 inputs MGTREFCLK1P (AP SoC U1 pin AC8) and MGTREFCLK1N (AP SoC U1 pin AC7).

The primary purpose of this clock is to support CPRI/OBSAI applications that perform clock recovery from a user-supplied SFP/SFP+ module and use the jitter attenuated recovered clock to drive the reference clock inputs of a GTX transceiver. The jitter attenuated clock circuit is shown in Figure 1-16.

ZC706 Evaluation Board User Guide www.xilinx.com 38

UG954 (v1.5) September 10, 2015

X-Ref Target - Figure 1-16

UG954_c1_16_041113

R89

4.7 KΩ 5%

SI5324_VCC

Si5324C-C-GM Clock Multiplier/ Jitter Attenuator

VDD3

GND

NC5

U60

CKOUT1_N

CKOUT1_P

C137

0.1 μF 25V X5R

C136

0.1 μF 25V X5R

SI5324_XTAL_XA

GND2

GND1

114.285 MHz 20 ppm

SI5324_OUT_C_N

SI5324_OUT_C_P

SI5324_OUT_N

SI5324_OUT_P

SI5324_XTAL_XB

GND

NC4

C138

0.1 μF 25V X5R

C141

0.1 μF 25V X5R

REC_CLOCK_P

REC_CLOCK_N

REC_CLOCK_C_P

REC_CLOCK_C_N

R251 100Ω

CKIN1_P

CKIN1_N

NCNC12

CKIN2_P

CKIN2_N

VDD2

VDD1

NC3

NC2

NC1

CKOUT2_P

CKOUT2_N

SI5324_INT_ALM 3

NC 4

NC 11

NC 15

NC 18

SI5324_RST 1

GND2

GND1

A2_SS

RTC SI5324_SCL

SCL

RTC SI5324_SDA

SDA_SDO

SDI

CMODE

GND

GND4

GND3

LOL

RATE1

RATE0

C2B

INT_C1B

CS_CA

RST_B

GNDPAD

0.1W 1%

Send Feedback

Feature Descriptions

See the Silicon Labs Si5324 data sheet [Ref 21].

GTX Transceivers

[Figure 1-2, callout 12]

ZC706 Evaluation Board User Guide www.xilinx.com 39

UG954 (v1.5) September 10, 2015

The ZC706 board provides access to 16 GTX transceivers:

• Four of the GTX transceivers are wired to the PCI Express x4 endpoint edge connector

• Eight of the GTX transceivers are wired to the FMC HPC connector (J37)

• One GTX transceiver is wired to the FMC LPC connector (J5)

(P4) fingers

• One GTX transceiver is wired to SMA connectors (RX: J32, J33 TX: J35, J34)

• One GTX transceiver is wired to the SFP/SFP+ Module connector (P2)

Figure 1-16: Jitter Attenuated Clock

Feature Descriptions

Send Feedback

• One GTX transceiver is unused and is wired in a capacitively coupled TX-to-RX loopback configuration

The GTX transceivers in Zynq-7000 series AP SoCs are grouped into four channels described as Quads. The reference clock for a Quad can be sourced from the Quad above or Quad below the GTX Quad of interest. There are four GTX Quads on the ZC706 board with connectivity as shown here:

• Quad 109:

MGTREFCLK0 - FMC_HPC_GBTCLK0_M2C clock

MGTREFCLK1 - not connected

Contains 4 GTX transceivers allocated to FMC_HPC_DP[3:0]_C2M_P/N

• Quad 110:

MGTREFCLK0 - FMC_HPC_GBTCLK1_M2C clock

MGTREFCLK1 - SI5324_OUT_C_P/N jitter attenuator clock

Contains 4 GTX transceivers allocated to FMC_HPC_DP[7:4]_C2M_P/N

• Quad 111:

MGTREFCLK0 - FMC_LPC_GBTCLK0_M2C_C_P/N

MGTREFCLK1 - SMA_MGT_REFCLK_P/N SMA GTX clock input

Contains 1 GTX transceiver allocated to FMC_LPC_DP0_C2M_P/N

Contains 1 GTX transceiver allocated to SMA_MGT_TX_P/N and RX_P/N SMA

connectors

Contains 1 GTX transceiver allocated to SFP_TX and _RX_P/N SFP/SFP+ connector

Contains 1 GTX transceiver which is unused and is wired in TX-to-RX loopback

configuration

• Quad 112:

MGTREFCLK0 - PCIE_CLK_Q0_P/N PCIe edge connector clock

MGTREFCLK1 - not connected

Contains 4 GTX transceivers allocated to PCIe lanes 0-3

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UG954 (v1.5) September 10, 2015

Tab le 1- 14 lists the GTX Banks 109 and 110 interface connections between the AP SoC U1

Send Feedback

and FMC HPC connector J37.

Table 1-14: AP SoC GTX Banks 109 and 110 Interface Connections to FMC HPC J37

Feature Descriptions

Transceiver

Bank

GTX_BANK_109

AP SoC U1

AP SoC U1 Pin Name Schematic Net Name

Connected

Number

AK10 MGTPTXP0_109 FMC_HPC_DP0_C2M_P C2

AK9 MGTPTXN0_109 FMC_HPC_DP0_C2M_N C3

AH10 MGTPRXP0_109 FMC_HPC_DP0_M2C_P C6

AH9 MGTPRXN0_109 FMC_HPC_DP0_M2C_N C7

AK6 MGTPTXP1_109 FMC_HPC_DP1_C2M_P A22

AK5 MGTPTXN1_109 FMC_HPC_DP1_C2M_N A23

AJ8 MGTPRXP1_109 FMC_HPC_DP1_M2C_P A2

AJ7 MGTPRXN1_109 FMC_HPC_DP1_M2C_N A3

AJ4 MGTPTXP2_109 FMC_HPC_DP2_C2M_P A26

AJ3 MGTPTXN2_109 FMC_HPC_DP2_C2M_N A27

AG8 MGTPRXP2_109 FMC_HPC_DP2_M2C_P A6

AG7 MGTPRXN2_109 FMC_HPC_DP2_M2C_N A7

AK2 MGTPTXP3_109 FMC_HPC_DP3_C2M_P A30

AK1 MGTPTXN3_109 FMC_HPC_DP3_C2M_N A31

AE8 MGTPRXP3_109 FMC_HPC_DP3_M2C_P A10

Connected

Device

FMC HPC J37

AE7 MGTPRXN3_109 FMC_HPC_DP3_M2C_N A11

(1)

AD10 MGTREFCLK0P_109 FMC_HPC_GBTCLK0_M2C_C_P

AD9 MGTREFCLK0N_109 FMC_HPC_GBTCLK0_M2C_C_N

AF10 MGTREFCLK1P_109 NC NA NA

AF9 MGTREFCLK1N_109 NC NA NA

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UG954 (v1.5) September 10, 2015

Feature Descriptions

Send Feedback

Table 1-14: AP SoC GTX Banks 109 and 110 Interface Connections to FMC HPC J37 (Cont’d)

Transceiver

Bank

GTX_BANK_110

AP SoC U1

AP SoC U1 Pin Name Schematic Net Name

Connected

Number

AH2 MGTPTXP0_110 FMC_HPC_DP4_C2M_P A34

AH1 MGTPTXN0_110 FMC_HPC_DP4_C2M_N A35

AH6 MGTPRXP0_110 FMC_HPC_DP4_M2C_P A14

AH5 MGTPRXN0_110 FMC_HPC_DP4_M2C_N A15

AF2 MGTPTXP1_110 FMC_HPC_DP5_C2M_P A38

AF1 MGTPTXN1_110 FMC_HPC_DP5_C2M_N A39

AG4 MGTPRXP1_110 FMC_HPC_DP5_M2C_P A18

AG3 MGTPRXN1_110 FMC_HPC_DP5_M2C_N A19

AE4 MGTPTXP2_110 FMC_HPC_DP6_C2M_P B36

AE3 MGTPTXN2_110 FMC_HPC_DP6_C2M_N B37

AF6 MGTPRXP2_110 FMC_HPC_DP6_M2C_P B16

AF5 MGTPRXN2_110 FMC_HPC_DP6_M2C_N B17

AD2 MGTPTXP3_110 FMC_HPC_DP7_C2M_P B32

AD1 MGTPTXN3_110 FMC_HPC_DP7_C2M_N B33

AD6 MGTPRXP3_110 FMC_HPC_DP7_M2C_P B12

Connected

Device

FMC HPC J37

AD5 MGTPRXN3_110 FMC_HPC_DP7_M2C_N B13

AA8 MGTREFCLK0P_110 FMC_HPC_GBTCLK1_M2C_P

AA7 MGTREFCLK0N_110 FMC_HPC_GBTCLK1_M2C_N

AC8 MGTREFCLK1P_110 SI5324_OUT_C_P

AC7 MGTREFCLK1N_110 SI5324_OUT_C_N

Notes:

1. AP SoC U1 GTX input clock nets are capacitively coupled to the FMC HPC J37 pins.

2. AP SoC U1 GTX input clock nets are capacitively coupled to the SI5324C Recovery Clock U60 output pins.

(2)

(1)

B20

B21

SI5324C U60

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UG954 (v1.5) September 10, 2015

Tab le 1- 15 lists the GTX Bank interface connections between the AP SoC U1 and FMC LPC

Send Feedback

connector J5.

Table 1-15: AP SoC GTX Bank 111 Interface Connections to FMC LPC J5

Feature Descriptions

Transceiver

Bank

GTX_BANK_11 1

AP SoC U1

Number

AB2 MGTPTXP0_111 FMC_LPC_DP0_C2M_P C2

AB1 MGTPTXN0_111 FMC_LPC_DP0_C2M_N C3

AC4 MGTPRXP0_111 FMC_LPC_DP0_M2C_P C6

AC3 MGTPRXN0_111 FMC_LPC_DP0_M2C_N C7

Y2 MGTPTXP1_111 SMA_MGT_TX_P J35.1

Y1 MGTPTXN1_111 SMA_MGT_TX_N J34.1

AB6 MGTPRXP1_111 SMA_MGT_RX_P

AB5 MGTPRXN1_111 SMA_MGT_RX_N

W4 MGTPTXP2_111 SFP_TX_P 18

W3 MGTPTXN2_111 SFP_TX_N 19

Y6 MGTPRXP2_111 SFP_RX_P 13

Y5 MGTPRXN2_111 SFP_RX_N 12

V2 MGTPTXP3_111 (capacitively coupled to AA4) U1.AA4

V1 MGTPTXN3_111 (Cooperatively coupled to AA3) U1.AA3

AA4 MGTPRXP3_111 See Pin V2 loopback U1.V2

AA3 MGTPRXN3_111 See Pin V1 loopback U1.V1

U8 MGTREFCLK0P_111 FMC_LPC_GBTCLK0_M2C_C_P

U7 MGTREFCLK0N_111 FMC_LPC_GBTCLK0_M2C_C_N

W8 MGTREFCLK1P_111 SMA_MGT_REFCLK_P

W7 MGTREFCLK1N_111 SMA_MGT_REFCLK_N

AP SoC U1 Pin

Name

Schematic Net Name

(2)

Connected

J32.1

J33.1

(1)

J36.1 GTX

J31.1

Connected

Device

FMC LPC J5

GTX TX/RX SMA

SFP+ Conn. P2

AP SoC U1 GTX Loopback

FMC LPC J5

REFCLK SMA

Notes:

1. AP SoC U1 GTX input clock nets are capacitively coupled to the FMC LPC J5 pins.

2. AP SoC U1 GTX input nets are capacitively coupled to the RX and MGT_REFCLK SMA pins.

ZC706 Evaluation Board User Guide www.xilinx.com 43

UG954 (v1.5) September 10, 2015

For additional information on Zynq-7000 GTX transceivers, see 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476

Feature Descriptions

UG954_c1_18_041113

PCIE_PRSNT_BPCIE_PRSNT_X1

PCIE_PRSNT_X4

J19

1 3

2 4

Send Feedback

PCI Express Endpoint Connectivity

[Figure 1-2, callout 13]

The 4-lane PCI Express edge connector performs data transfers at the rate of 2.5 GT/s for a Gen1 application and 5.0 GT/s for a Gen2 application. The PCIe transmit and receive signal data paths have a characteristic impedance of 85Ω ±10%. The PCIe clock is routed as a 100Ω differential pair.

The XC7Z045-2FFG900C AP SoC (-2 speed grade) included with the ZC706 board supports up to Gen2 x4.

The PCIe clock is input from the edge connector. It is AC coupled to the AP SoC through the MGTREFCLK0 pins of Quad 112. PCIE_CLK_Q0_P is connected to AP SoC U1 pin N8, and the _N net is connected to pin N7. The PCI Express clock circuit is shown in Figure 1-17.

X-Ref Target - Figure 1-17

PCI Express

Eight-Lane

Edge connector

GND

REFCLK+

REFCLK-

GND

A12

A13

A14

A15

PCIE_CLK_Q0_C_P

PCIE_CLK_Q0_C_N

GND

C352

0.01μF 25V X7R

PCIE_CLK_Q0_P

PCIE_CLK_Q0_N

C353

0.01μF 25V X7R

UG954_c1_17_041113

X-Ref Target - Figure 1-18

Figure 1-17: PCI Express Clock

PCIe lane width/size is selected by jumper J19 (Figure 1-17). The default lane size selection is 4-lane (J19 pins 3 and 4 jumpered).

Figure 1-18: PCI Express Lane Size Select Jumper J19

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UG954 (v1.5) September 10, 2015

Feature Descriptions

Send Feedback

Tab le 1- 17 lists the GTX Bank 112 interface connections between the AP SoC U1 and PCIe

4-lane connector P4.

Table 1-16: AP SoC GTX Bank 112 Interface Connections to PCIe 4-Lane Connector P4

Transceiver

Bank

GTX_BANK_112 T2 MGTPTXP0_112 PCIE_TX3_P A29 (1)

AP SoC U1 Pin

Number

T1 MGTPTXN0_112 PCIE_TX3_N A30 (1)

V6 MGTPRXP0_112 PCIE_RX3_P B27

V5 MGTPRXN0_112 PCIE_RX3_N B28

R4 MGTPTXP1_112 PCIE_TX2_P A25 (1)

R3 MGTPTXN1_112 PCIE_TX2_N A26 (1)

U4 MGTPRXP1_112 PCIE_RX2_P B23

U3 MGTPRXN1_112 PCIE_RX2_N B24

P2 MGTPTXP2_112 PCIE_TX1_P A21 (1)

P1 MGTPTXN2_112 PCIE_TX1_N A22 (1)

T6 MGTPRXP2_112 PCIE_RX1_P B19

T5 MGTPRXN2_112 PCIE_RX1_N B20

N4 MGTPTXP3_112 PCIE_TX0_P A16 (1)

N3 MGTPTXN3_112 PCIE_TX0_N A17 (1)

P6 MGTPRXP3_112 PCIE_RX0_P B14

AP SoC U1 Pin Name Schematic Net Name

PCIe 4-Lane Conn. P4

Pin Number

P5 MGTPRXN3_112 PCIE_RX0_N B15

N8 MGTREFCLK0P_112 PCIE_CLK_QO_P A13 (1)

N7 MGTREFCLK0N_112 PCIE_CLK_QO_N A14 (1)

R8 MGTREFCLK1P_112 NC NA

R7 MGTREFCLK1N_112 NC NA

Notes:

1. PCIE_TXn_P/N and PCIE_CLK_Q0_P/N are capacitively coupled to the PCIe edge connector P4.

For additional information about Zynq-7000 PCIe functionality, see 7SeriesFPGAs Integrated Block for PCI Express Product Guide for Vivado Design Suite ( information about the PCI Express standard is available [Ref 22].

PG054). Additional

ZC706 Evaluation Board User Guide www.xilinx.com 45

UG954 (v1.5) September 10, 2015

X-Ref Target - Figure 1-19

Send Feedback

Feature Descriptions

SFP/SFP+ Module Connector

[Figure 1-2, callout 14]

The ZC706 board contains a small form-factor pluggable (SFP/SFP+) connector and cage assembly P2 that accepts SFP or SFP+ modules. Figure 1-19 shows the SFP/SFP+ module connector circuitry.

VCCR

VCCT

VEER_1

VEER_2

VEER_3

VEET_1

VEET_2

VEET_3

GND1

GND2

GND3

GND4

GND5

GND6

GND7

GND8

GND9

GND10

GND11

GND12

SFP+ Module

Connector

74441-0010

RD_N

RD_P

TD_P

TD_N

TX_FAULT

TX_DISABLE

MOD_ABS

SFP_RX_N

SFP_RX_P

SFP_TX_P

SFP_TX_N

SFP_IIC_SDA

SDA

SFP_IIC_SCL

SCL

SFP_TX_FAULT

SFP_TX_DISABLE_TRANS

SFP_MOD_DETECT

SFP_LOS

LOS

SFP Enable

GND

SFP_RS1

RS1

SFP_RS0

RS0

J17

HDR_1X2

R84

4.7KΩ

VCC3V3

R87

R83

4.7KΩ

Q12 NDS331N

460 mW

SFP_TX_DISABLE

HDR_1X3 J38 J39

VCC3V3

R85

4.7KΩ

R86

4.7KΩ

VCC3V3

HDR_1X1

R88

4.7KΩ

J22

J21

J20

C198 22μF

VCC3V3

C134

0.1μF

4.7μH

3.0 A

C199 22μF

VCC3V3

GND

4.7μH

3.0 A

SFP_VCCR

SFP_VCCT

C135

0.1μF

GND

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UG954 (v1.5) September 10, 2015

1-2: FULL BW RX

2-3: LOW BW RX

Figure 1-19: SFP+ Module Connector

Tab le 1- 17 lists the SFP+ module RX and TX connections to the AP SoC.

GNDGND

1-2: FULL BW TX

2-3: LOW BW TX

UG954_c1_19_041113

Table 1-17: AP SoC U1 to SFP+ Module Connections

Send Feedback

Feature Descriptions

AP SoC (U1) Pin Schematic Net name

SFP+ Module (P2)

Pin Name

Y5 SFP_RX_N 12 RD_N

Y6 SFP_RX_P 13 RD_P

W4 SFP_TX_P 18 TD_P

W3 SFP_TX_N 19 TD_N

AA18 SFP_TX_DISABLE_TRANS 3 TX_DISABLE

Tab le 1- 18 lists the SFP+ module control and status connections to the AP SoC.

Table 1-18: SFP+ Module Control and Status Connections

SFP Control/ Status

Signal

SFP_TX_FAULT Test Point J23

SFP_TX_DISABLE Jumper 17

SFP_MOD_DETECT Test Point J24

SFP_RS0 Jumper 56

Board Connection

High = Fault

Low = Normal operation

Off = SFP Disabled

On = SFP enabled

High = Module not present

Low = Module present

Jumper pins 1-2 = Full RX bandwidth

Jumper pins 2-3 = Reduced RX bandwidth

SFP_RS1 Jumper 55

SFP_LOS Test Point J25

Jumper pins 1-2 = Full TX bandwidth

Jumper pins 2-3 = Reduced TX bandwidth

High = Loss of receiver signal

Low = Normal operation

For additional information about the enhanced Small Form Factor Pluggable (SFP+) module, see the SFF-8431 specification [Ref 23].

10/100/1000 Mb/s Tri-Speed Ethernet PHY (PL)

[Figure 1-2, callout 15]

The ZC706 evaluation board uses the Marvell Alaska PHY device (88E1116R) at U51 for Ethernet communications at 10 Mb/s, 100 Mb/s, or 1000 Mb/s. The board supports RGMII mode only. The PHY connection to a user-provided Ethernet cable is through a Halo HFJ11-1G01E RJ-45 connector (P3) with built-in magnetics.

On power-up, or on reset, the PHY is configured to operate in RGMII mode with PHY address 0b00111 using the settings shown in Tab le 1- 19. These settings can be overwritten via software commands passed over the MDIO interface.

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UG954 (v1.5) September 10, 2015

Table 1-19: Board Connections for PHY Configuration Pins

Send Feedback

U51 Pin Setting Configuration

CONFIG (64) VCCP1V8 PHYAD[1]=1 PHYAD[0]=1

CONFIG1 (1) PHY_LED0 PHYAD[3]=0 PHYAD[2]=1

GND ENA_XC=0 PHYAD[4]=0

Feature Descriptions

CONFIG2 (2)

CONFIG3 (3)

PHY_LED0 ENA_XC=0 PHYAD[4]=1

VCCP1V8 ENA_XC=1 PHYAD[4]=1

GND RGMII_TX=0 RGMII_RX=0

PHY_LED0 RGMII_TX=0 RGMII_RX=1

PHY_LED1 RGMII_TX=1 RGMII_RX=0

VCCP1V8 RGMII_TX=1 RGMII_RX=1

The Ethernet connections from the XC7Z045 AP SoC at U1 to the 88E1116R PHY device at U51 are listed in Table 1 -20 .

Table 1-20: Ethernet Connections, XC7Z045 AP SoC to the PHY Device

XC7Z045 (U1) Pin

M88E1116R PHY U51

Schematic

Pin Name Bank

PS_MIO53 501 C18 PHY_MDIO 45 MDIO

PS_MIO52 501 D19 PHY_MDC 48 MDC

PS_MIO16 501 L19 PHY_TX_CLK 60 TX_CLK

PS_MIO21 501 J19 PHY_TX_CTRL 63 TX_CTRL

PS_MIO20 501 M20 PHY_TXD3 62 TXD3

Number

Net Name

Pin Name

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UG954 (v1.5) September 10, 2015

PS_MIO19 501 J20 PHY_TXD2 61 TXD2

PS_MIO18 501 K20 PHY_TXD1 59 TXD1

PS_MIO17 501 K21 PHY_TXD0 58 TXD0

PS_MIO22 501 L20 PHY_RX_CLK 53 RX_CLK

PS_MIO27 501 G20 PHY_RX_CTRL 49 RX_CTRL

PS_MIO26 501 M17 PHY_RXD3 55 RXD3

PS_MIO25 501 G19 PHY_RXD2 54 RXD2

PS_MIO24 501 M19 PHY_RXD1 51 RXD1

PS_MIO23 501 J21 PHY_RXD0 50 RXD0

Ethernet PHY Clock Source

A 25.00 MHz 50 ppm crystal at X1 is the clock source for the 881116R PHY at U51.

Figure 1-20 shows the clock source.

X-Ref Target - Figure 1-20

UG954_c1_20_041113

GND

R355

DNP

C495 18 pF 50V NPO

C494 18 pF 50V NPO

PHY XTAL OUT

25.00 MHz 50 PPM

PHY XTAL IN

Send Feedback

Feature Descriptions

Figure 1-20: Ethernet PHY Clock Source

The data sheet can be obtained under NDA with Marvell. Contact information can be found at their website [Ref 24].

For additional information on the Zynq-7000 AP SoC device gigabit Ethernet controller, see

Zynq-7000 All Programmable SoC Overview (DS190 Technical Reference Manual (UG585

) and Zynq-7000 All Programmable SoC

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UG954 (v1.5) September 10, 2015

USB-to-UART Bridge

[Figure 1-2, callout 17]

The ZC706 evaluation board contains a Silicon Labs CP2103GM USB-to-UART bridge device (U52) which allows a connection to a host computer with a USB port. The USB cable is supplied in the ZC706 evaluation kit (Standard-A end to host computer, Type Mini-B end to ZC706 evaluation board connector J21). The CP2103GM is powered by the USB 5V provided by the host PC when the USB cable is plugged into the USB port on the ZC706 evaluation board.

The CP2013GM TX and RX pins are wired to the UART_1 IP block within the XC7Z045 AP SoC PS I/O Peripherals set. The XC7Z045 AP SoC supports the USB-to-UART bridge using two signal pins: Transmit (TX) and Receive (RX).

Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers for the host computer. These drivers permit the CP2103GM USB-to-UART bridge to appear as a COM port to communications application software (for example, TeraTerm or HyperTerm) that runs on the host computer. The VCP device drivers must be installed on the host PC prior to establishing communications with the ZC706 evaluation board.

The USB Connector pin assignments and signal definitions between J21 and U52 are listed in Tab le 1 -21 .

Table 1-21: USB Connector J21 Pin Assignments and Signal Definitions

Send Feedback

Feature Descriptions

USB Connector (J21)

CP2103GM (U52)

Net Name Description

Pin Name Pin Name

1 VBUS USB_UART_VBUS +5V VBUS Powered

2 D_N USB_UART_D_N Bidirectional differential serial data (N-side) 4 D –

3 D_P USB_UART_D_P Bidirectional differential serial data (P-side) 3 D +

5 GND USB_UART_GND Signal ground

7REGIN

8VBUS

2GND1

29 CNR_GND

Tab le 1- 22 lists the USB connections between the XC7Z045 AP SoC PS Bank 501 and the

CP2103 UART bridge.

Table 1-22: XC7Z045 AP SoC to CP2103 Connections

XC7045 AP SoC (U1)

Pin Name Bank PIN Function Direction IOSTANDARD PIN Function Direction

PS_MIO48 501 C19 TX Output LVCMOS18 USB_UART_RX 24 RXD Input

PS_MIO49 501 D18 RX Input LVCMOS18 USB_UART_TX 25 TXD Output

Schematic Net

Name

CP2103GM Device (U52)

Refer to the Silicon Labs website for technical information on the CP2103GM and the VCP drivers [Ref 21].

For additional information on the Zynq-7000 AP SoC device UART controller, see Zynq-7000

All Programmable SoC Overview (DS190 Reference Manual (UG585

) and Zynq-7000 All Programmable SoC Technical

HDMI Video Output

[Figure 1-2, callout 18]

The ZC706 evaluation board provides a high-definition multimedia interface (HDMI®) video output using an Analog Devices ADV7511KSTZ-P HDMI transmitter at U53. The HDMI transmitter U53 is connected to the XC7Z045 AP SoC PL-side banks 12 and 13 and its output is provided on a Molex 500254-1927 HDMI type-A receptacle at P1. The ADV7511 supports 1080P 60Hz, YCbCr 4:4:4 encoding via 24-bit input data mapping.

The ZC706 evaluation board supports the following HDMI device interfaces:

• 24 data lines

•Independent VSYNC, HSYNC

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UG954 (v1.5) September 10, 2015

• Single-ended input CLK

• Interrupt Out pin to XC7Z045 AP SoC

X-Ref Target - Figure 1-21

Send Feedback

•I2C

•SPDIF

Figure 1-21 shows the HDMI codec circuit.

VCC3V3

VADJ

Feature Descriptions

VCC2V5

HDMI_INT

IIC_SCL_HDMI IIC_SDA_HDMI

HDMI_VSYNC HDMI_HSYNC

HDMI_CLK

HDMI_HEAC_C_N

To HDMI

Connector

R163

2.43 KΩ 1/10W 1%

HDMI_D35 HDMI_D34 HDMI_D33 HDMI_D32 HDMI_D31 HDMI_D30 HDMI_D28 HDMI_D28

HDMI_D23 HDMI_D22 HDMI_D21 HDMI_D20 HDMI_D19 HDMI_D18 HDMI_D17 HDMI_D16

HDMI_D11 HDMI_D10 HDMI_D9 HDMI_D8 HDMI_D7 HDMI_D6 HDMI_D5 HDMI_D4

HDMI_DE

HDMI_SPDIF

R164

R165

2.43KΩ 1/10W 1%

GND

2.43 KΩ 1/10W 1%

R158 887Ω

1/10W 1%

U53

ADV7511

INT

SCL CEC_CLK

SDA

VSYNC

HSYNC

CLK

HPD

D35

D34

D33

D32

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

SPDIF

DSD0

DSD1

DSD2

DSD3

DSD4

DSD5

DSD_CLK

MCLK

I2S0

I2S1

I2S2

I2S3

SCLK

LRCLK

R_EXT

SPDIF_OUT

PVDD1 PVDD2 PVDD3

AVDD1 AVDD2 AVDD3

DVDD1 DVDD2 DVDD3 DVDD4 DVDD5

DVDD_3V

BGVDD

TX0_P TX0_N TX1_P TX1_N TX2_P

TX2_N TXC_P TXC_N

DDCSDA DDCSCL

HEAC_P HEAC_N

CEC

GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8

GND9 GND10 GND11

HDMI_SPDIF_OUT

21 24 25

29 34 41

76 77 49 19 1

HDMI_D0_P

HDMI_D0_N

HDMI_D1_P

HDMI_D1_N

HDMI_D2_P

HDMI_D2_N

HDMI_CLK_P

HDMI_CLK_N

HDMI_DDCSDA

54 53

HDMI_DDCSCL

HDMI_HEAC_P

HDMI_HEAC_N

HDMI_CEC

99 100 18

20 22

23 27 31 37 44 75

HDMI_DVDD_3V

GND

R172

24.9Ω 1/10W 1%

HDMI_AVDDHDMI_PLVDD

HDMI_AVDD

HDMI_DVDD

HDMI_PLVDD

C88

0.1μF 25V

X5R

To HDMI Connector

U50

12.00000 MHZ

VCC

GND

SIT8102

50 PPM

UG954_c1_21_041113

GNDOUT

GND

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UG954 (v1.5) September 10, 2015

Figure 1-21: HDMI Codec Circuit

Feature Descriptions

Send Feedback

Tab le 1- 23 lists the connections between the codec and the XC7Z045 AP SoC.

Table 1-23: XC7Z045 AP SoC U1 to HDMI Codec Connections (ADV7511)

XC7Z045 (U1)

U24 HDMI_R_D4 LVCMOS25 92 D4

T22 HDMI_R_D5 LVCMOS25 91 D5

R23 HDMI_R_D6 LVCMOS25 90 D6

AA25 HDMI_R_D7 LVCMOS25 89 D7

AE28 HDMI_R_D8 LVCMOS25 88 D8

T23 HDMI_R_D9 LVCMOS25 87 D9

AB25 HDMI_R_D10 LVCMOS25 86 D10

T27 HDMI_R_D11 LVCMOS25 85 D11

AD26 HDMI_R_D16 LVCMOS25 80 D16

AB26 HDMI_R_D17 LVCMOS25 78 D17

AA28 HDMI_R_D18 LVCMOS25 74 D18

AC26 HDMI_R_D19 LVCMOS25 73 D19

AE30 HDMI_R_D20 LVCMOS25 72 D20

Y25 HDMI_R_D21 LVCMOS25 71 D21

AA29 HDMI_R_D22 LVCMOS25 70 D22

AD30 HDMI_R_D23 LVCMOS25 69 D23

Y28 HDMI_R_D28 LVCMOS25 64 D28

Net Name I/O Standard

Pin Number Pin Name

ADV7511 (U53)

AF28 HDMI_R_D29 LVCMOS25 63 D29

V22 HDMI_R_D30 LVCMOS25 62 D30

AA27 HDMI_R_D31 LVCMOS25 61 D31

U22 HDMI_R_D32 LVCMOS25 60 D32

N28 HDMI_R_D33 LVCMOS25 59 D33

V21 HDMI_R_D34 LVCMOS25 58 D34

AC22 HDMI_R_D35 LVCMOS25 57 D35

V24 HDMI_R_DE LVCMOS25 97 DE

R22 HDMI_R_HSYNC LVCMOS25 98 HSYNC

U21 HDMI_R_VSYNC LVCMOS25 2 VSYNC

P28 HDMI_R_CLK LVCMOS25 79 CLK

AC23 HDMI_INT LVCMOS25 45 INT

AC21 HDMI_R_SPDIF LVCMOS25 10 SPDIF

AB22 HDMI_SPDIF_OUT_LS LVCMOS25 46 SPDIF_OUT

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UG954 (v1.5) September 10, 2015

Feature Descriptions

Send Feedback

Tab le 1- 24 lists the connections between the codec and the HDMI receptacle P1.

Table 1-24: ADV7511 to HDMI Receptacle Connections

ADV7511 (U53) Net Name

36 HDMI_D0_P 7

35 HDMI_D0_N 9

40 HDMI_D1_P 4

39 HDMI_D1_N 6

43 HDMI_D2_P 1

42 HDMI_D2_N 3

33 HDMI_CLK_P 10

32 HDMI_CLK_N 12

54 HDMI_DDCSDA 16

53 HDMI_DDCSCL 15

52 HDMI_HEAC_P 14

51 HDMI_HEAC_N 19

48 HDMI_CEC 13

HDMI Receptacle

P1 Pin

Information about the ADV7511KSTZ-P is available on the Analog Devices website [Ref 25].

For additional information about HDMI IP options, see the LogiCORE IP DisplayPort Product Guide for Vivado Design Suite (PG064

I2C Bus

[Figure 1-2, callout 20]

The ZC706 evaluation board implements two

I2C port (IIC_SDA and _SCL_MAIN) is routed to level shifter U87. The PS-side I2C port

(PS_SDA and _SCL_MAIN) is routed to level shifter U88. The "output" side of the two level shifters are wired to the common

I2C bus IIC_SDA and _SCL_MAIN which is connected to TI

Semiconductor PCA9548 1-to-8 channel at speeds up to 400 kHz.

IMPORTANT: The PCA9548 U65 RESET_B pin 24 is connected to FPGA U1 bank 501 pin F20 via

level-shifter U25. FPGA pin F20 net IIC_MUX_RESET_B_LS must be driven High to enable I2C bus transactions with the devices connected to U65.

I2C ports on the XC7Z045 AP SoC. The PL-side

I2C bus switch (U65). The bus switch can operated

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UG954 (v1.5) September 10, 2015

Feature Descriptions

CH7 - PMBUS_DATA/CLK

PCA9548

12C 1-to-8

Bus Switch

U65

CH6 - FMC_LPC_IIC_SDA/SCL

CH5 - FMC_HPC_IIC_SDA/SCL

CH4 - IIC_RTC_SDA/SCL

CH3 - PORT_EXPANDER_SDA/SCL

CH2 - EEPROM_IIC_SDA/SCL

CH1 - IIC_SDA/SCL_HDMI

CH0 - USRCLK_SFP_SDA/SCL

XC7Z045 AP SoC

PS Bank 501

(1.8V)

UG954_c1_22_04113

XC7Z045 AP SoC

PL Bank 10

(2.5V)

PCA9517

Level Shifter

U87

3.3 V

VADJ 2.5V

PCA9517

Level Shifter

U88

3.3 V

VCCMIO_PS 1.8V

IIC_SDA/SCL_MAIN

PS_SDA/SCL_MAIN

IIC_SCL/SDA_MAIN

Send Feedback

X-Ref Target - Figure 1-22

The ZC706 evaluation board I

C bus topology is shown in Figure 1-22.

Figure 1-22: I2C Bus Topology

User applications that communicate with devices on one of the downstream I first set up a path to the desired bus through the U65 bus switch at I

C address 0x74

(0b01110100). Tab le 1- 25 lists the address for each bus.

C buses must

Table 1-25: I2C Bus Addresses

Device I

PCA9548 8-Channel bus switch NA

Si570 clock 0

ADV7511 HDMI 1

I2C EEPROM 2

I2C port expander and DDR3 SODIMM

I2C real time clock and Si5324 clock

FMC HPC 5

FMC LPC 6

UCD90120A pmbus 7

Information about the PCA9548 is available on the TI Semiconductor website at [Ref 26].

For additional information on the Zynq-7000 AP SoC device I

All Programmable SoC Overview (DS190 Reference Manual (UG585

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UG954 (v1.5) September 10, 2015

C Switch Position I2C Address Device

0b1110100 PCA9548 U65

0b1011101 Si570 U37

0b1010000 SFP+ Conn. P2

0b0111001 ADV7511 U53

0b1010100 M24C08 U9

0b0100001 Port Expander U16

) and Zynq-7000 All Programmable SoC Technical

0b1010000

0b0011000

0b1010001 RTC8564JE U26

0b1101000 SI5324 U60

0bxxxxx00 FMC HPC J37

0bxxxxx00 FMC LPC J5

0b1100101 UCD90120A U48

C controller, see Zynq-7000

DDR3 SODIMM J1

Feature Descriptions

Send Feedback

Real Time Clock (RTC)

The Epson RTC-8564JE (U26) is an I2C bus interface real-time clock that has a built-in

32.768 KHz oscillator with these features:

• Frequency output options: 32.768 KHz, 1,024 Hz, 32 Hz or 1 Hz

• Calendar output functions: Year, month, day, weekday, hour, minute and second

• Clock counter, alarm and fixed-cycle timer interrupt functions

• Back-up battery B3 Panasonic ML621S/DN, 3.0V rechargeable cell

Programming information for the RTC-8564JE is available in the RTC-8564JE/NB Application Manual [Ref 29].

Figure 1-23 shows the real time clock circuit.

X-Ref Target - Figure 1-23

IIC_RTC_SDA

IIC_RTC_SCL

IIC_RTC_IRQ_1_B

VADJ

R270

10.0 KΩ

0.1W

U26

SDA

SCL

INT

RTC-8564JE

Real Time Clock

Module

CLKOE

CLKOUT

VCC

GND

J60 YELLOW

GND

VCC3V3 VCC2V5

D4 BAT54T1G 30V 400 mW

D6 BAT54T1G 30V 400 mW

C350

0.01μF 25V X7R

GND

D5 BAT54T1G 30V 400 mW

R501

4.7 KΩ

0.1WW

B3 Panasonic ML621S/DN 3V

UG954_c1_23_041113

Figure 1-23: Real Time Clock Circuit

Real time clock connections to the XC7Z045 AP SoC and the PCA9548 8-Channel bus switch are listed in Tab le 1 -26 . Refer to Tab le 1 -25 for the RTC I

C address.

Table 1-26: Real Time Clock Connections

RTC-8564JE (U16) Pin Net Name Connects To

6 IIC_RTC_SCL U65.11 (PCA9548 SC4)

7 IIC_RTC_SDA U65.10 (PCA9548 SD4)

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UG954 (v1.5) September 10, 2015

10 IIC_RTC_IRQ_1_B U1.AA17 (XC7Z045 AP SoC PL BANK 10)

Information about the RTC-8564JE is available at the Epson Electronics America website

[Ref 30].

Status and User LEDs

Send Feedback

Tab le 1- 27 defines the status and user LEDs.

Table 1-27: Status LEDs

Feature Descriptions

Reference

Designator

DS1

DS2

DS3

DS8

DS9

DS10

DS11

DS13

DS15

DS16

DS20

DS21

DS22

DS23

DS24

Net Name LED Color Description

POR

FPGA_INIT_B

DONE

GPIO_LED_LEFT

GPIO_LED_CENTER

GPIO_LED_RIGHT

VCCINT

VCC1V5_PL

VADJ_FPGA

VCC3V3_FPGA

PS_DDR_LINEAR_PG

SODIMM_DDR_LINEAR_PG

VCC12_P

PWRCTL1_FMC_PG_C2M

CTRL1_PWRGOOD

RED

GRN/RED

GRN

Processor System Power-ON reset is active

Green: FPGA initialization was successful Red: FPGA initialization is in progress

FPGA bit file download is complete

Geographically LEFT located user LED

Geographically CENTER located user LED

Geographically RIGHT located user LED

VCCINT voltage on indicator

VCC1V5_PL voltage on indicator

VADJ_FPGA voltage on indicator

VCC3V3 voltage on indicator

VTTDDR_PS voltage on indicator

VTTDDR_SODIMM voltage on indicator

VCC12_P voltage on indicator

FMC power good INDICATOR

Power Controller controlled voltage regulator outputs are all ≥ their minimum “good” threshold

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UG954 (v1.5) September 10, 2015

DS25

DS26

DS27

DS28

DS29

DS30

DS35

U22_FLG

LINEAR_POWER_GOOD

VCCAUX

PHY_LED0

PHY_LED1

PHY_LED2

GPIO_LED_0

RED

GRN

USB 2.0 MOSFET power switch fault

MGTAVCC, MGTAVTT, MGTVCCAUX voltage regulator outputs are all ≥ their minimum “good” threshold

VCCAUX voltage on indicator

Ethernet PHY LED0

Ethernet PHY LED1

Ethernet PHY LED2

General Purpose user LED

Feature Descriptions

Send Feedback

Ethernet PHY User LEDs

[Figure 1-2, callout 21]

The three Ethernet PHY user LEDs shown in Figure 1-24 are located near the RJ45 Ethernet jack P3. The on/off state for each LED is software dependent and has no specific meaning at Ethernet PHY power on.

Refer to the Marvell 881116R Alaska Gigabit Ethernet transceiver data sheet for details concerning the use of the Ethernet PHY user LEDs. They are referred to in the data sheet as LED0, LED1, and LED2. See the data sheet and other product information for the Marvell 881116R Alaska Gigabit Ethernet Transceiver [Ref 24].

X-Ref Target - Figure 1-24

VCC3V3

GNDGNDGND

UG954_c1_24_041113

386 261Ω

0.1W

DS30

Q4 NDS331N 460 mW

PHY LED 0

VCC3V3

388 261Ω

0.1W

DS28

Q6 NDS331N 460 mW

PHY LED1

VCC3V3

387 261Ω

0.1W

DS29

Q5 NDS331N 460 mW

PHY LED 2

Figure 1-24: Ethernet PHY User LEDs

User I/O

[Figure 1-2, callout 22–24]

The ZC706 evaluation board provides the following user and general purpose I/O capabilities:

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UG954 (v1.5) September 10, 2015

• Four user LEDs (callout 22)

GPIO_LED_LEFT DS8, GPIO_LED_CENTER DS9, GPIO_LED_RIGHT DS10,

GPIO_LED_0 DS35

• Three user pushbuttons (callout 23)

GPIO_SW_LEFT SW7, GPIO_SW_CENTER SW9, GPIO_SW_RIGHT SW8

• PL CPU reset pushbutton

PL_CPU_RESET SW13

• 4-position user DIP Switch (callout 24)

Feature Descriptions

Send Feedback

GPIO_DIP_SW[3:0] SW12

• Two user GPIO male pin headers (callout 26)

• 2 x 6 0.1 in. pitch PMOD1 J57

• 2 x 6 0.1 in. pitch PMOD2 J58

User LEDs

[Figure 1-2, callout 22]

The ZC706 evaluation board supports four user LEDs connected to XC7Z045 AP SoC Banks 11, 33, and 35. Figure 1-25 shows the user LED circuits.

X-Ref Target - Figure 1-25

LEFT

VCC3V3

DS8

R390 261Ω

0.1W 1%

Q7 NDS331N 460 mW

GPIO_LED_

GND

CENTER

VCC3V3

DS9

R391 261Ω

0.1W 1%

Q8 NDS331N 460 mW

GND

GPIO_LED_

RIGHT

VCC3V3

DS10

R392 261Ω

0.1W 1%

Q9 NDS331N 460 mW

GND

VCC3V3

DS35

R544 261Ω

0.1W

Q30

GPIO_LED_0GPIO_LED_

NDS331N 460 mW

GND

UG954_c1_25_041113

Figure 1-25: User LEDs

Tab le 1- 28 lists the user LED connections to XC7Z045 AP SoC U1.

Table 1-28: User LED Connections to XC7Z045 AP SoC U1

XC7Z045 AP SoC (U1) Pin Net Name I/O Standard LED Reference

ZC706 Evaluation Board User Guide www.xilinx.com 58

UG954 (v1.5) September 10, 2015

Y21 GPIO_LED_LEFT LVCMOS25 DS8

G2 GPIO_LED_CENTER LVCMOS25 DS9

W21 GPIO_LED_RIGHT LVCMOS25 DS10

A17 GPIO_LED_0 LVCMOS25 DS35

X-Ref Target - Figure 1-26

VADJ

GPIO_SW_LEFT

R66

4.7 kΩ

0.1 W 5%

GND

SW7

VADJ

GPIO_SW_CENTER

R72

4.7 kΩ

0.1 W 5%

GND

SW9

UG954_c1_26_041113

VADJ

GPIO_SW_RIGHT

R67

4.7 kΩ

0.1 W 5%

GND

SW8

VCC1V5_PL

PL_CPU_RESET

R516

1.00K 1/16 W 1%

GND

SW13

Send Feedback

Feature Descriptions

User Pushbuttons

[Figure 1-2, callout 23]

Figure 1-26 shows the user pushbutton circuits.

Tab le 1- 29 lists the user pushbutton connections to XC7Z045 AP SoC U1.

Table 1-29: User Pushbutton Connections to XC7Z045 AP SoC U1

XC7Z045 AP SoC (U1) Pin Net Name I/O Standard Pushbutton Reference

AK25 GPIO_SW_LEFT LVCMOS25 SW7

K15 GPIO_SW_CENTER LVCMOS25 SW9

R27 GPIO_SW_RIGHT LVCMOS25 SW8

A8 PL_CPU_RESET LVCMOS15 SW13

Figure 1-26: User Pushbuttons

ZC706 Evaluation Board User Guide www.xilinx.com 59

UG954 (v1.5) September 10, 2015

GPIO DIP Switch

UG954_c1_27_041113

SDA02H1SBD

SW12

VADJ

GPIO_DIP_SW0

GPIO_DIP_SW1

R70

4.7 kΩ

0.1 W 5%

R71

4.7 kΩ

0.1 W 5%

R68

4.7 kΩ

0.1 W 5%

R69

4.7 kΩ

0.1 W 5%

GND

GPIO_DIP_SW2

GPIO_DIP_SW3

Send Feedback

Figure 1-27 shows the GPIO DIP switch circuit.

X-Ref Target - Figure 1-27

Figure 1-27: GPIO DIP Switch

Feature Descriptions

ZC706 Evaluation Board User Guide www.xilinx.com 60

UG954 (v1.5) September 10, 2015

Tab le 1- 30 lists the GPIO DIP switch connections to XC7Z045 AP SoC U1.

Table 1-30: GPIO DIP Switch Connections to XC7Z045 AP SoC at U1

XC7Z045 AP S0C (U1) Pin Net Name I/O Standard DIP Switch SW12 Pin

AB17 GPIO_DIP_SW0 LVCMOS25 1

AC16 GPIO_DIP_SW1 LVCMOS25 2

AC17 GPIO_DIP_SW2 LVCMOS25 3

AJ13 GPIO_DIP_SW3 LVCMOS25 4

User PMOD GPIO Headers

[Figure 1-2, callout 26]

The ZC706 evaluation board GPIO 2 x 6 male headers J57 and J58 support Digilent Pmod Peripheral Modules. J57 pins (IIC_PMOD_[0:7]) are connected to the TI TCA6416APWR I2C expansion port device U16. J58 pins (PMOD1_[0:7]) are connected to the TI TXS0108E

3.3V-to-VADJ level-shifter U40.

See the Digilent website for information on Digilent Pmod Peripheral Modules [Ref 35].

Information about the TCA641APWR and TXS0108E devices is available at the Texas Instruments website [Ref 26].

X-Ref Target - Figure 1-28

Send Feedback

VCC3V3_PS

R330

1/10W

PMOD1_0_LS PMOD1_1_LS PMOD1_2_LS PMOD1_3_LS PMOD1_4_LS PMOD1_5_LS PMOD1_6_LS PMOD1_7_LS

Figure 1-28 shows the user GPIO male pin header circuits.

VCC3V3_PS

121

R310

DNP DNP DNP

R65

4.7 1/10W 5%

PORT_EXPANDER_DDR3_SDA PORT_EXPANDER_DDR3_SCL

C105

0.1UF 10V

X5R

TXS0108E

VCCA

C97

0.1UF 10V

X5R

TCA6416APWR

VCCP

VCCI

SDA

SCL

ADDR

RESET_B

INT_B

GND

U16

GND

VCCB

GND

VADJ VCC3V3

GND

C96

0.1UF

10V X5R

GND

P00 P01 P02 P03 P04 P05 P06 P07

P10 P11 P12 P13 P14 P15 P16 P17

TCA6416APWR

C104

0.1UF 10V X5R

19 20

GND

IIC_PMOD_0

IIC_PMOD_1

IIC_PMOD_2

IIC_PMOD_3

IIC_PMOD_4

IIC_PMOD_5

IIC_PMOD_6

IIC_PMOD_7

FMC_VADJ_ON_R_B

FMC_LPC_PRSNT_M2C_B

FMC_HPC_PRSNT_M2C_B

FMC_HPC_PG_M2C

XADC_MUX_ADDR0

XADC_MUX_ADDR1

XADC_MUX_ADDR2

PL_PWR_ON_R

PMOD1_0 PMOD1_1 PMOD1_2 PMOD1_3 PMOD1_4 PMOD1_5 PMOD1_6 PMOD1_7

IIC_PMOD_0

IIC_PMOD_1

IIC_PMOD_2

IICPMOD_3

PMOD1_0

PMOD1_1

PMOD1_2

PMOD1_3

Feature Descriptions

J57

HDR_2X6

VCC3V3_PS

J58

HDR_2X6

VCC3V3

IIC_PMOD_4

IIC_PMOD_5

IIC_PMOD_6

IIC_PMOD_7

GNDGND

PMOD1_4

PMOD1_5

PMOD1_6

PMOD1_7

GNDGND

ZC706 Evaluation Board User Guide www.xilinx.com 61

UG954 (v1.5) September 10, 2015

U40

TSSOP_20

GND

UG954_c1_28_031715

Figure 1-28: User GPIO Headers

Tab le 1- 31 lists the GPIO Header connections to XC7Z045 AP SoC U1.

Send Feedback

Table 1-31: GPIO Header Connections to XC7Z045 AP SoC at U1

TCA6416APWR (U16) PORT: Pin Net Name GPIO Header J57 Pin

P00:4 IIC_PMOD_0 J57.1

P01:5 IIC_PMOD_1 J57.3

P02:6 IIC_PMOD_2 J57.5

P03:7 IIC_PMOD_3 J57.7

P04:8 IIC_PMOD_4 J57.2

P05:9 IIC_PMOD_5 J57.4

P06:10 IIC_PMOD_6 J57.6

P07:11 IIC_PMOD_7 J57.8

XC7Z045 AP SoC (U1) Pin Net Name GPIO Header J58 Pin

AJ21 PMOD1_0 J58.1

AK21 PMOD1_1 J58.3

Feature Descriptions

AB21 PMOD1_2 J58.5

AB16 PMOD1_3 J58.7

Y20 PMOD1_4 J58.2

AA20 PMOD1_5 J58.4

AC18 PMOD1_6 J58.6

AC19 PMOD1_7 J58.8

See Zynq-7000 All Programmable SoC Technical Reference Manual (UG585

) for information

about the PS PJTAG functionality.

Switches

The ZC706 evaluation board includes a power and a configuration (PL PROG_B) switch:

• Power On/Off slide switch SW1 (callout 27)

• SW10 (FPGA_PROG_B), active-Low pushbutton (callout 28)

• PS System Reset Pushbuttons

Power On/Off Slide Switch

ZC706 Evaluation Board User Guide www.xilinx.com 62

UG954 (v1.5) September 10, 2015

[Figure 1-2, callout 27]

The ZC706 evaluation board power switch is SW1. Sliding the switch actuator from the Off to On position applies 12V power from J22 a 6-pin mini-fit connector. Green LED DS22 illuminates when the ZC706 evaluation board power is on. See Power Management for details on the onboard power system.

Feature Descriptions

UG954_c1_30_041113

VCC12_P_IN

VCC12_P

R171

2.15kΩ

.1W

INPUT_GND

SW1

GND

C568 330 μF 25V

C319

1μF 25V

GND

DS22

J22

12V

N/C

COM

12V

N/C

COM

INPUT_GND

U18 50Ω

Send Feedback

CAUTION! Do NOT plug a PC ATX power supply 6-pin connector into J22 on the ZC706 Evaluation

Board. The ATX 6-pin connector has a different pinout than J22. Connecting an ATX 6-pin connector into J22 will damage the ZC706 Evaluation Board and void the board warranty.

The ZC706 evaluation kit provides the adapter cable shown in Figure 1-29 for powering the ZC706 board from the ATX power supply 4-pin peripheral connector. The Xilinx part number for this cable is 2600304, and is equivalent to Sourcegate Technologies part number AZCBL-WH-1109-RA4. For information on ordering this cable, see [Ref 36].

X-Ref Target - Figure 1-29

To ATX 4-Pin Peripheral

Power Connector

To J22 on ZC706 Board

UG954_c1_29_041113

Figure 1-29: ATX Power Supply Adapter Cable

Figure 1-30 shows the power connector J22, power switch SW1 and indicator LED DS22.

X-Ref Target - Figure 1-30

ZC706 Evaluation Board User Guide www.xilinx.com 63

UG954 (v1.5) September 10, 2015

Figure 1-30: Power On/Off Switch SW1

Program_B Pushbutton

[Figure 1-2, callout 28]

Switch SW10 grounds the XC7Z045 AP SoC PROG_B pin when pressed. This action clears the programmable logic configuration. The FPGA_PROG_B signal is connected to XC7Z045 AP SoC U1 pin Y9.

See 7 Series FPGAs Configuration User Guide, (UG470 7 series FPGAs.

) for further details on configuring the

Figure 1-31 shows SW10.

UG954_c1_32_041113

MAX16025

Dual Voltage Monitor

and Sequencer

TH1

TH0

TOL

MR_B

EN2

EN1

IN2

IN1

GND

EPAD

CRESET

CDLY2

CDLY1

OUT2

OUT1

RST_B

VCC

VCCP1V8

R177

8.06 KΩ

0.1W 1%

R264

10.0 Ω

0.1W 1%

VCCP1V8

R265

10.0 KΩ

0.1W 1%

R149 249Ω

0.1W 1%

R176

8.06 KΩ

0.1W 1%

R256

10.0 KΩ

0.1W 1%

R263

10.0 KΩ

0.1W 1%

R262

10.0 KΩ

0.1W 1%

R261

10.0 K

0.1W 1%

SW3

SW2

GND

VCCP1V8

PS_POR_B

PS_SRST_B

C8 DNP DNP

xxx

0.1 µf 25V

X5R

270pF

25V

X5R

GND

VCC3V3_PS

DS1

GND

PS_POR_B_SW

PS_SRST_B_SW

J44

VCCP1V8

R266

10.0 KΩ

0.1W 1%

J43

PS_POR_B

PS_SRST_B

VCC3V3

C8 = DNP, SRST delay = 35 µS C6 = 270 pF, POR delay = 1.08 mS

Send Feedback

X-Ref Target - Figure 1-31

FPGA_PROG B

VCC3V3

R73

4.7 kΩ

0.1 W 5%

SW10

Feature Descriptions

X-Ref Target - Figure 1-32

UG954_c1_31_041113

GND

Figure 1-31: PROG_B Pushbutton SW10

PS Power-On and System Reset Pushbuttons

Figure 1-32 shows the reset circuitry for the processing system.

Depressing and then releasing pushbutton SW1 causes PS_POR_B_SW to strobe low.

PS_POR_B: This reset is used to hold the PS in reset until all PS power supplies are at the required voltage levels. It must be held Low through PS power-up. PS_POR_B should be generated by the power supply power-good signal.

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UG954 (v1.5) September 10, 2015

Figure 1-32: PS Power On and System Reset Circuitry

Feature Descriptions

Send Feedback

Depressing and then releasing pushbutton SW3 causes PS_SRST_B_SW (connected to the XC7Z045 AP SoC U1 dedicated PS Bank 500 pin D21) to strobe low.

PS_SRST_B: This reset is used to force a system reset. It can be tied or pulled High, and can be High during the PS supply power ramps.

See Zynq-7000 All Programmable SoC Technical Reference Manual (UG585 concerning the resets.

) for information

FPGA Mezzanine (FMC) Card Interface

[Figure 1-2, callout 30 and 31]

The ZC706 evaluation board supports the VITA 57.1 FPGA Mezzanine Card (FMC) specification by providing subset implementations of the high pin count (HPC) connector at J37 and low pin count (LPC) version at J5. Both connectors use a 10 x 40 form factor. The HPC connector is populated with 400 pins, while the LPC connector is partially populated with 160 pins. The connectors are keyed so that a mezzanine card, when installed in either of these FMC connectors on the ZC706 evaluation board, faces away from the ZC706 board.

Connector Type:

• Samtec SEAF Series, 1.27 mm (0.050 in) pitch. Mates with SEAM series connector

More information about SEAF series connectors is available at the Samtec website [Ref 31]. More information about the VITA 57.1 FMC specification is available at the VITA FMC Marketing Alliance website [Ref 37].

HPC Connector J37

[Figure 1-2, callout 30]

The 400-pin HPC connector defined by the FMC specification (Figure B-2, page 91) provides connectivity for up to:

• 160 single-ended or 80 differential user-defined signals

•10 GTX transceivers

•2 GTX clocks

• 4 differential clocks

• 159 ground and 15 power connections

The connections between the HPC connector at J37 and AP SoC U1 (Ta ble 1 -32 ) implements a subset of this connectivity:

• 34 differential user-defined pairs (34 LA pairs, LA00–LA33)

ZC706 Evaluation Board User Guide www.xilinx.com 65

UG954 (v1.5) September 10, 2015

•8 GTX transceivers

Send Feedback

•2 GTX clocks

• 2 differential clocks

• 159 ground and 15 power connections

Feature Descriptions

The ZC706 board V

voltage for the J37 and J5 connectors is determined by the FMC V

ADJ

power sequencing logic described in the Power Management, page 77.

Note:

HPC FMC (J37) GA0 = GA1 = 0 = GND.

Tab le 1- 32 shows the J37 HPC FMC to AP SoC U1 connections.

Table 1-32: J37 HPC FMC Connections to XC7Z045 AP SoC U1

J37 FMC HPC Pin

A2 FMC_HPC_DP1_M2C_P

A3 FMC_HPC_DP1_M2C_N

A6 FMC_HPC_DP2_M2C_P

A7 FMC_HPC_DP2_M2C_N

A10 FMC_HPC_DP3_M2C_P

A11 FMC_HPC_DP3_M2C_N

A14 FMC_HPC_DP4_M2C_P

A15 FMC_HPC_DP4_M2C_N

A18 FMC_HPC_DP5_M2C_P

A19 FMC_HPC_DP5_M2C_N

A22 FMC_HPC_DP1_C2M_P

A23 FMC_HPC_DP1_C2M_N

A26 FMC_HPC_DP2_C2M_P

A27 FMC_HPC_DP2_C2M_N

A30 FMC_HPC_DP3_C2M_P

A31 FMC_HPC_DP3_C2M_N

A34 FMC_HPC_DP4_C2M_P

A35 FMC_HPC_DP4_C2M_N

A38 FMC_HPC_DP5_C2M_P

A39 FMC_HPC_DP5_C2M_N

C2 FMC_HPC_DP0_C2M_P

C3 FMC_HPC_DP0_C2M_N

C6 FMC_HPC_DP0_M2C_P

C7 FMC_HPC_DP0_M2C_N

C10 FMC_HPC_LA06_P LVCMOS25 AG22 D9 FMC_HPC_LA01_CC_N LVCMOS25 AH21

C11 FMC_HPC_LA06_N LVCMOS25 AH22 D11 FMC_HPC_LA05_P LVCMOS25 AH23

Net Name I/O Standard

(1)

XC7Z045

(U1) Pin

AJ8 B1 NC N/A N/A

AJ7 B4 NC N/A N/A

AG8 B5 NC N/A N/A

AG7 B8 NC N/A N/A

AE8 B9 NC N/A N/A

AE7 B12 FMC_HPC_DP7_M2C_P

AH6 B13 FMC_HPC_DP7_M2C_N

AH5 B16 FMC_HPC_DP6_M2C_P

AG4 B17 FMC_HPC_DP6_M2C_N

AG3 B20 FMC_HPC_GBTCLK1_M2C_P

AK6 B21 FMC_HPC_GBTCLK1_M2C_N

AK5 B24 NC N/A N/A

AJ4 B25 NC N/A N/A

AJ3 B28 NC N/A N/A

AK2 B29 NC N/A N/A

AK1 B32 FMC_HPC_DP7_C2M_P

AH2 B33 FMC_HPC_DP7_C2M_N

AH1 B36 FMC_HPC_DP6_C2M_P

AF2 B37 FMC_HPC_DP6_C2M_N

AF1 B40 NC N/A N/A

AK10 D1 PWRCTL1_FMC_PG_C2M LVCMOS25 AB20

AK9 D4 FMC_HPC_GBTCLK0_M2C_P

AH10 D5 FMC_HPC_GBTCLK0_M2C_N

AH9 D8 FMC_HPC_LA01_CC_P LVCMOS25 AG21

J37 FMC

HPC Pin

Net Name I/O Standard

(1)

ADJ

XC7Z045

(U1) Pin

AD6

AD5

AF6

AF5

AA8

AA7

AD2

AD1

AE4

AE3

AD10

AD9

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UG954 (v1.5) September 10, 2015

Table 1-32: J37 HPC FMC Connections to XC7Z045 AP SoC U1 (Cont’d)

Send Feedback

Feature Descriptions

J37 FMC HPC Pin

C14 FMC_HPC_LA10_P LVCMOS25 AG24 D12 FMC_HPC_LA05_N LVCMOS25 AH24

C15 FMC_HPC_LA10_N LVCMOS25 AG25 D14 FMC_HPC_LA09_P LVCMOS25 AD21

C18 FMC_HPC_LA14_P LVCMOS25 AC24 D15 FMC_HPC_LA09_N LVCMOS25 AE21

C19 FMC_HPC_LA14_N LVCMOS25 AD24 D17 FMC_HPC_LA13_P LVCMOS25 AA22

C22 FMC_HPC_LA18_CC_P LVCMOS25 W25 D18 FMC_HPC_LA13_N LVCMOS25 AA23

C23 FMC_HPC_LA18_CC_N LVCMOS25 W26 D20 FMC_HPC_LA17_CC_P LVCMOS25 V23

C26 FMC_HPC_LA27_P LVCMOS25 V28 D21 FMC_HPC_LA17_CC_N LVCMOS25 W24

C27 FMC_HPC_LA27_N LVCMOS25 V29 D23 FMC_HPC_LA23_P LVCMOS25 P25

C30 FMC_HPC_IIC_SCL N/A U65.13 D24 FMC_HPC_LA23_N LVCMOS25 P26

C31 FMC_HPC_IIC_SDA N/A U65.12 D26 FMC_HPC_LA26_P LVCMOS25 R28

C34 GA0 = 0 = GND N/A N/A D27 FMC_HPC_LA26_N LVCMOS25 T28

C35 VCC12_P N/A N/A D29 FMC_HPC_TCK_BUF N/A U23.15

C37 VCC12_P N/A N/A D30 FMC_TDI_BUF N/A U23.18

C39 VCC3V3 N/A N/A D31 FMC_HPC_TDO_FMC_LPC_TDI N/A U32.2

E2 NC N/A N/A F1 FMC_HPC_PG_M2C N/A U16.16

E3 NC N/A N/A F4 NC N/A N/A

E6 NC N/A N/A F5 NC N/A N/A

E7 NC N/A N/A F7 NC N/A N/A

E9 NC N/A N/A F8 NC N/A N/A

E10 NC N/A N/A F10 NC N/A N/A

E12 NC N/A N/A F11 NC N/A N/A

E13 NC N/A N/A F13 NC N/A N/A

E15 NC N/A N/A F14 NC N/A N/A

E16 NC N/A N/A F16 NC N/A N/A

E18 NC N/A N/A F17 NC N/A N/A

E19 NC N/A N/A F19 NC N/A N/A

E21 NC N/A N/A F20 NC N/A N/A

E22 NC N/A N/A F22 NC N/A N/A

E24 NC N/A N/A F23 NC N/A N/A

E25 NC N/A N/A F25 NC N/A N/A

Net Name I/O Standard

XC7Z045

(U1) Pin

J37 FMC

HPC Pin

D32 VCC3V3 N/A N/A

D33 FMC_HPC_TMS_BUF N/A U23.17

D34 NC N/A N/A

D35 GA1 = 0 = GND N/A N/A

D36 VCC3V3 N/A N/A

D38 VCC3V3 N/A N/A

D40 VCC3V3 N/A N/A

Net Name I/O Standard

XC7Z045

(U1) Pin

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UG954 (v1.5) September 10, 2015

Table 1-32: J37 HPC FMC Connections to XC7Z045 AP SoC U1 (Cont’d)

Send Feedback

Feature Descriptions

J37 FMC HPC Pin

E27 NC N/A N/A F26 NC N/A N/A

E28 NC N/A N/A F28 NC N/A N/A

E30 NC N/A N/A F29 NC N/A N/A

E31 NC N/A N/A F31 NC N/A N/A

E33 NC N/A N/A F32 NC N/A N/A

E34 NC N/A N/A F34 NC N/A N/A

E36 NC N/A N/A F35 NC N/A N/A

E37 NC N/A N/A F37 NC N/A N/A

E39 VADJ N/A N/A F38 NC N/A N/A

G2 FMC_HPC_CLK1_M2C_P LVCMOS25 U26 H1 NC N/A N/A

G3 FMC_HPC_CLK1_M2C_N LVCMOS25 U27 H2 FMC_HPC_PRSNT_M2C_B N/A U16.15

G6 FMC_HPC_LA00_CC_P LVCMOS25 AF20 H4 FMC_HPC_CLK0_M2C_P LVCMOS25 AE22

G7 FMC_HPC_LA00_CC_N LVCMOS25 AG20 H5 FMC_HPC_CLK0_M2C_N LVCMOS25 AF22

G9 FMC_HPC_LA03_P LVCMOS25 AH19 H7 FMC_HPC_LA02_P LVCMOS25 AK17

G10 FMC_HPC_LA03_N LVCMOS25 AJ19 H8 FMC_HPC_LA02_N LVCMOS25 AK18

G12 FMC_HPC_LA08_P LVCMOS25 AF19 H10 FMC_HPC_LA04_P LVCMOS25 AJ20

G13 FMC_HPC_LA08_N LVCMOS25 AG19 H11 FMC_HPC_LA04_N LVCMOS25 AK20

G15 FMC_HPC_LA12_P LVCMOS25 AF23 H13 FMC_HPC_LA07_P LVCMOS25 AJ23

G16 FMC_HPC_LA12_N LVCMOS25 AF24 H14 FMC_HPC_LA07_N LVCMOS25 AJ24

G18 FMC_HPC_LA16_P LVCMOS25 AA24 H16 FMC_HPC_LA11_P LVCMOS25 AD23

G19 FMC_HPC_LA16_N LVCMOS25 AB24 H17 FMC_HPC_LA11_N LVCMOS25 AE23

G21 FMC_HPC_LA20_P LVCMOS25 U25 H19 FMC_HPC_LA15_P LVCMOS25 Y22

G22 FMC_HPC_LA20_N LVCMOS25 V26 H20 FMC_HPC_LA15_N LVCMOS25 Y23

G24 FMC_HPC_LA22_P LVCMOS25 V27 H22 FMC_HPC_LA19_P LVCMOS25 T24

G25 FMC_HPC_LA22_N LVCMOS25 W28 H23 FMC_HPC_LA19_N LVCMOS25 T25

G27 FMC_HPC_LA25_P LVCMOS25 T29 H25 FMC_HPC_LA21_P LVCMOS25 W29

G28 FMC_HPC_LA25_N LVCMOS25 U29 H26 FMC_HPC_LA21_N LVCMOS25 W30

G30 FMC_HPC_LA29_P LVCMOS25 R25 H28 FMC_HPC_LA24_P LVCMOS25 T30

G31 FMC_HPC_LA29_N LVCMOS25 R26 H29 FMC_HPC_LA24_N LVCMOS25 U30

G33 FMC_HPC_LA31_P LVCMOS25 N29 H31 FMC_HPC_LA28_P LVCMOS25 P30

G34 FMC_HPC_LA31_N LVCMOS25 P29 H32 FMC_HPC_LA28_N LVCMOS25 R30

G36 FMC_HPC_LA33_P LVCMOS25 N26 H34 FMC_HPC_LA30_P LVCMOS25 P23

G37 FMC_HPC_LA33_N LVCMOS25 N27 H35 FMC_HPC_LA30_N LVCMOS25 P24

G39 VADJ N/A N/A H37 FMC_HPC_LA32_P LVCMOS25 P21

Net Name I/O Standard

F40 VADJ N/A N/A

XC7Z045

(U1) Pin

J37 FMC

HPC Pin

Net Name I/O Standard

XC7Z045

(U1) Pin

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UG954 (v1.5) September 10, 2015

Table 1-32: J37 HPC FMC Connections to XC7Z045 AP SoC U1 (Cont’d)

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Feature Descriptions

J37 FMC HPC Pin

J2 NC N/A N/A K1 NC N/A N/A

J3 NC N/A N/A K4 NC N/A N/A

J6 NC N/A N/A K5 NC N/A N/A

J7 NC N/A N/A K7 NC N/A N/A

J9 NC N/A N/A K8 NC N/A N/A

J10 NC N/A N/A K10 NC N/A N/A

J12 NC N/A N/A K11 NC N/A N/A

J13 NC N/A N/A K13 NC N/A N/A

J15 NC N/A N/A K14 NC N/A N/A

J16 NC N/A N/A K16 NC N/A N/A

J18 NC N/A N/A K17 NC N/A N/A

J19 NC N/A N/A K19 NC N/A N/A

J21 NC N/A N/A K20 NC N/A N/A

J22 NC N/A N/A K22 NC N/A N/A

J24 NC N/A N/A K23 NC N/A N/A

J25 NC N/A N/A K25 NC N/A N/A

J27 NC N/A N/A K26 NC N/A N/A

J28 NC N/A N/A K28 NC N/A N/A

J30 NC N/A N/A K29 NC N/A N/A

J31 NC N/A N/A K31 NC N/A N/A

J33 NC N/A N/A K32 NC N/A N/A

J34 NC N/A N/A K34 NC N/A N/A

J36 NC N/A N/A K35 NC N/A N/A

J37 NC N/A N/A K37 NC N/A N/A

J39 NC N/A N/A K38 NC N/A N/A

Net Name I/O Standard

H38 FMC_HPC_LA32_N LVCMOS25 R21

XC7Z045

(U1) Pin

J37 FMC

HPC Pin

H40 VADJ N/A N/A

K40 NC N/A N/A

Net Name I/O Standard

XC7Z045

(U1) Pin

Notes:

1. No I/O standards are associated with MGT connections.

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UG954 (v1.5) September 10, 2015

LPC Connector J5

[Figure 1-2, callout 31]

The 160-pin LPC connector defined by the FMC specification (Figure B-1, page 90) provides connectivity for up to:

Feature Descriptions

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• 68 single-ended or 34 differential user-defined signals

•1 GTX transceiver

•1 GTX clock

• 2 differential clocks

• 61 ground and 10 power connections

The connections between the HPC connector at J5 and AP SoC U1 implements a subset of this connectivity:

• 34 differential user-defined pairs (34 LA pairs, LA00–LA33)

•1 GTX transceiver

•1 GTX clock

• 2 differential clocks

• 61 ground and 9 power connections

Note:

LPC FMC (J5) GA0 = GA1 = 0 = GND.

Tab le 1- 33 shows the FMC LPC connections between J5 and XC7Z045 AP SoC U1.

Table 1-33: J5 LPC FMC Connections to AP SoC U1

J5 FMC

LPC Pin

C2 FMC_LPC_DP0_C2M_P

C3 FMC_LPC_DP0_C2M_N

C6 FMC_LPC_DP0_M2C_P

C7 FMC_LPC_DP0_M2C_N

C10 FMC_LPC_LA06_P LVCMOS25 AB12 D9 FMC_LPC_LA01_CC_N LVCMOS25 AG15

C11 FMC_LPC_LA06_N LVCMOS25 AC12 D11 FMC_LPC_LA05_P LVCMOS25 AE16

C14 FMC_LPC_LA10_P LVCMOS25 AC14 D12 FMC_LPC_LA05_N LVCMOS25 AE15

C15 FMC_LPC_LA10_N LVCMOS25 AC13 D14 FMC_LPC_LA09_P LVCMOS25 AH14

C18 FMC_LPC_LA14_P LVCMOS25 AF18 D15 FMC_LPC_LA09_N LVCMOS25 AH13

C19 FMC_LPC_LA14_N LVCMOS25 AF17 D17 FMC_LPC_LA13_P LVCMOS25 AH17

C22 FMC_LPC_LA18_CC_P LVCMOS25 AE27 D18 FMC_LPC_LA13_N LVCMOS25 AH16

C23 FMC_LPC_LA18_CC_N LVCMOS25 AF27 D20 FMC_LPC_LA17_CC_P LVCMOS25 AB27

C26 FMC_LPC_LA27_P LVCMOS25 AJ28 D21 FMC_LPC_LA17_CC_N LVCMOS25 AC27

C27 FMC_LPC_LA27_N LVCMOS25 AJ29 D23 FMC_LPC_LA23_P LVCMOS25 AJ26

C30 FMC_LPC_IIC_SCL N/A U65.15 D24FMC_LPC_LA23_NLVCMOS25AK26

C31 FMC_LPC_IIC_SDA N/A U65.14 D26 FMC_LPC_LA26_P LVCMOS25 AJ30

C34 GA0 = 0 = GND N/A N/A D27 FMC_LPC_LA26_N LVCMOS25 AK30

C35 VCC12_P N/A N/A D29 FMC_LPC_TCK_BUF N/A U23.14

C37 VCC12_P N/A N/A D30 FMC_HPC_TDO_FMC_LPC_TDI N/A U31.1

Net Name I/O Standard

(1)

XC7Z045

(U1) Pin

J5 FMC LPC Pin

AB2 D1 PWRCTL1_FMC_PG_C2M LVCMOS25 AB20

AB1 D4 FMC_LPC_GBTCLK0_M2C_P

AC4 D5 FMC_LPC_GBTCLK0_M2C_N

AC3 D8 FMC_LPC_LA01_CC_P LVCMOS25 AF15

Net Name I/O Standard

(1)

XC7Z045

(U1) Pin

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UG954 (v1.5) September 10, 2015

Table 1-33: J5 LPC FMC Connections to AP SoC U1 (Cont’d)

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Feature Descriptions

J5 FMC

LPC Pin

C39 VCC3V3 N/A N/A D31 FMC_LPC_TDO_FPGA_TDI N/A U31.2

G2 FMC_LPC_CLK1_M2C_P LVCMOS25 AC28 H1 NC LVCMOS25

G3 FMC_LPC_CLK1_M2C_N LVCMOS25 AD28 H2 FMC_LPC_PRSNT_M2C_B LVCMOS25 U16.14

G6 FMC_LPC_LA00_CC_P LVCMOS25 AE13 H4 FMC_LPC_CLK0_M2C_P LVCMOS25 AG17

G7 FMC_LPC_LA00_CC_N LVCMOS25 AF13 H5 FMC_LPC_CLK0_M2C_N LVCMOS25 AG16

G9 FMC_LPC_LA03_P LVCMOS25 AG12 H7 FMC_LPC_LA02_P LVCMOS25 AE12

G10 FMC_LPC_LA03_N LVCMOS25 AH12 H8 FMC_LPC_LA02_N LVCMOS25 AF12

G12 FMC_LPC_LA08_P LVCMOS25 AD14 H10 FMC_LPC_LA04_P LVCMOS25 AJ15

G13 FMC_LPC_LA08_N LVCMOS25 AD13 H11 FMC_LPC_LA04_N LVCMOS25 AK15

G15 FMC_LPC_LA12_P LVCMOS25 AD16 H13 FMC_LPC_LA07_P LVCMOS25 AA15

G16 FMC_LPC_LA12_N LVCMOS25 AD15 H14 FMC_LPC_LA07_N LVCMOS25 AA14

G18 FMC_LPC_LA16_P LVCMOS25 AE18 H16 FMC_LPC_LA11_P LVCMOS25 AJ16

G19 FMC_LPC_LA16_N LVCMOS25 AE17 H17 FMC_LPC_LA11_N LVCMOS25 AK16

G21 FMC_LPC_LA20_P LVCMOS25 AG26 H19 FMC_LPC_LA15_P LVCMOS25 AB15

G22 FMC_LPC_LA20_N LVCMOS25 AG27 H20 FMC_LPC_LA15_N LVCMOS25 AB14

G24 FMC_LPC_LA22_P LVCMOS25 AK27 H22 FMC_LPC_LA19_P LVCMOS25 AH26

G25 FMC_LPC_LA22_N LVCMOS25 AK28 H23 FMC_LPC_LA19_N LVCMOS25 AH27

G27 FMC_LPC_LA25_P LVCMOS25 AF29 H25 FMC_LPC_LA21_P LVCMOS25 AH28

G28 FMC_LPC_LA25_N LVCMOS25 AG29 H26 FMC_LPC_LA21_N LVCMOS25 AH29

G30 FMC_LPC_LA29_P LVCMOS25 AE25 H28 FMC_LPC_LA24_P LVCMOS25 AF30

G31 FMC_LPC_LA29_N LVCMOS25 AF25 H29 FMC_LPC_LA24_N LVCMOS25 AG30

G33 FMC_LPC_LA31_P LVCMOS25 AC29 H31 FMC_LPC_LA28_P LVCMOS25 AD25

G34 FMC_LPC_LA31_N LVCMOS25 AD29 H32 FMC_LPC_LA28_N LVCMOS25 AE26

G36 FMC_LPC_LA33_P LVCMOS25 Y30 H34 FMC_LPC_LA30_P LVCMOS25 AB29

G37 FMC_LPC_LA33_N LVCMOS25 AA30 H35 FMC_LPC_LA30_N LVCMOS25 AB30

G39 VADJ N/A N/A H37 FMC_LPC_LA32_P LVCMOS25 Y26

Net Name I/O Standard

D32 VCC3V3 N/A N/A

H38 FMC_LPC_LA32_N LVCMOS25 Y27

XC7Z045

(U1) Pin

J5 FMC LPC Pin

D33 FMC_LPC_TMS_BUF N/A U23.16

D34 NC N/A N/A

D35 GA1 = 0 = GND N/A N/A

D36 VCC3V3 N/A N/A

D38 VCC3V3 N/A N/A

D40 VCC3V3 N/A N/A

H40 VADJ N/A N/A

Net Name I/O Standard

XC7Z045

(U1) Pin

Notes:

1. No I/O standards are associated with MGT connections.

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UG954 (v1.5) September 10, 2015

Feature Descriptions

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ZC706 Board Power System

The ZC706 board hosts a power system based on the Texas Instruments (TI) UCD90120A power supply sequencer and monitor, and the LMZ31500 and LMZ31700 family voltage regulators.

UCD90120A Description

The UCD90120A is a 12-rail PMBus/I2C addressable power-supply sequencer and monitor. The device integrates a 12-bit ADC for monitoring up to 12 power-supply voltage inputs. Twenty-six GPIO pins can be used for power supply enables, power-on reset signals, external interrupts, cascading, or other system functions. Twelve of these pins offer pulse width modulation (PWM) functionality. Using these pins, the UCD90120A offers support for margining and general purpose PWM functions.

The TI Fusion Digital Power™ designer software is provided for device configuration. This PC-based graphical user interface (GUI) offers an intuitive interface for configuring, storing, and monitoring all system operating parameters.

LMZ31500 and LMZ31700 Family Regulator Description

The LMZ31520 SIMPLE SWITCHER® power module is a step-down DC-DC solution capable of driving up to 20A load. The LMZ31520 module can accept an input voltage rail between 3V and 14.5V and deliver an adjustable and highly accurate output voltage as low as 0.6V.

The LMZ31506 SIMPLE SWITCHER® power module is a step-down DC-DC solution capable of driving up to 6A load. The LMZ31506 module can accept an input voltage rail between 3V and 14.5V and deliver an adjustable and highly accurate output voltage as low as 0.6V. In older documentation this regulator was known as the TI TPS84621.

The LMZ31710 SIMPLE SWITCHER® power module is a step-down DC-DC solution capable of driving up to 10A load. The LMZ31710 module can accept an input voltage rail between

4.5V and 17V and deliver an adjustable and highly accurate output voltage as low as 0.6V.

These modules only requires two external resistors plus external capacitors to provide a complete power solution. These modules offer the following protection features: thermal shutdown, programmable input under-voltage lockout, output over-voltage protection, short-circuits protection, output current limit, and each allows startup into a pre-biased output.

The LMZ31710 sync input allows synchronization over the 200 kHz to 1,200 kHz switching frequency range and up to six modules can be connected in parallel for higher load currents.

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UG954 (v1.5) September 10, 2015

Tab le 1- 34 shows the ZC706 board TI power system configuration for controller U48.

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Table 1-34: ZC706 TI Controller U48 Power System Configuration

Feature Descriptions

Sequencer

Regulator Type, U# Voltage Current

Page Contents Net Name

49 UCD90120A

Schematic Page

50 Addr 101, Rail 1 VCCINT LMZ31520 U42

U48 PMBus

51 Addr 101, Rail 2 VCCAUX, VCC1V8 LMZ31710 U98

Addr 101

5 Rails

52 Addr 101, Rail 3 VCC1V5_PL LMZ31506 U85

53 Addr 101, Rail 4 VADJ_FPGA,VADJ LMZ31506 U86

54 Addr 101, Rail 5 VCC3V3_FPGA,VCC3V3 LMZ31710 U15

Notes:

ZC706 boards prior to Rev. 2.0 implemented different voltage regulators for VCCINT, VCCAUX/VCC1V8, VCC1V5_PL, VADJ_FPGA/VADJ and VCC3V3_FPGA/VCC3V3. Refer to UG954 v1.3 and earlier, and to the schematic for the particular version of the ZC706 board prior to Rev. 2.0. Notes on ZC706 boards prior to Rev. 2.0:

1. VCCINT is implemented utilizing 2xLMZ22008 8A components (U42, U43) in parallel which provides 16A capability.

2. The 1.8V rails are supplied from a LMZ22010 10A component (U98).

3. VCC1V5_PL and the 2.5V rails are supplied from TPS84621 6A components (U85, U86).

4. The 3.3V rails are supplied from a LMZ22010 10A component (U15).

(1)

(2)

(3)

(2)

(4)

1.0V 16A

1.8V 10A

1.5V 6A

2.5V 6A

3.3V 10A

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UG954 (v1.5) September 10, 2015

Figure 1-33 shows the power system for UCD90120A U48 controller.

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X-Ref Target - Figure 1-33

UCD90120A Controller U48

GPIO (out)

FPWM (out)

ADC (in)

GPIO (out)

FPWM (out)

ADC (in)

GPIO (out)

FPWM (out)

ADC (in)

GPIO (out)

FPWM (out)

ADC (in)

FMC_ADJ_SEL[1:0]

[ 1 0 ]

GPIO (out)

FPWM (out)

ADC (in)

Rail Enable

PWM Margin

Current Sense

Voltage Sense

Low Pwr Select

Rail Enable

PWM Margin

Current Sense

Voltage Sense

Rail Enable

PWM Margin

Current Sense

Voltage Sense

Rail Enable

PWM Margin

Current Sense

Voltage Sense

FMC_ADJ_SEL[1:0]

Rail Enable

PWM Margin

Current Sense

Voltage Sense

Dual 4-to-1 Mux

U66

I0B I1B I2B I3B S[1:0]

12V

VCCINT 1.0V Nom.

Input Filter

LMZ31520

Vin

U42

Vout

VCCAUX 1.8V Nom.

LMZ31710

Vin

U98

Vout

VCC1V5_PL 1.5V Nom.

LMZ31506

Vin

U85

Vout

VADJ_FPGA 2.5V Nom.

LMZ31506

Vin

U86

Vout

VCC3V3 FPGA 3.3V Nom.

LMZ31710

Vin

U15

Vout

Bulk Filter Caps

Low Power || Radj Low = 1.0V (Default) High = 0.9V

Bulk Filter Caps

Feature Descriptions

VCCINT 1.0V

Sense Connected at Point of Load

VCC1V8 1.8V

VCCAUX 1.8V

Sense Connected at Point of Load

VCC1V5_PL 1.5V

Sense Connected at Point of Load

VADDJ 2.5V

VADJ_FPGA 2.5V

Sense Connected at Point of Load

VCC3V3 3.3V

VCC3V3 FPGA 3.3V

Sense Connected at Point of Load

Notes:

1. Capacitors labeled Cf are bulk filter capacitors.

2. Voltage Sense is connected a point of load.

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UG954 (v1.5) September 10, 2015

UG954_c1_33_041615

Figure 1-33: ZC706 TI UCD90120A Controller U48 Power System

Feature Descriptions

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The LMZ31520, LMZ31506, and LMZ31710 adjustable voltage regulators have their output voltage set through an external resistor. The regulator topology on the ZC706 board permits the TI UCD90120A module to monitor rail voltage and current. Voltage margining at +5% and -5% is also implemented.

Each voltage regulator’s external V

setting resistor is calculated and implemented as if

OUT

the regulator is stand-alone. The TI UCD90120A module has two ADC inputs allocated per voltage rail, one input for the remote voltage sense connection, the other for the current sense resistor op amp output voltage connection. The TI UCD90120A ADC full scale input is

2.5V. The remote voltage feedback is scaled to approximately 2V if it exceeds 2V, that is, the V

CCO_VADJ

rail for the 2.5V and 3.3V modes, and the FPGA_3V3 rail also at 3.3V are resistor-attenuated to scale the remotely sensed voltage at a ratio of 0.606 to give approximately 2V at the ADC input pin for a 3.3V remote sense value. Rails below 2V are not scaled.

Each rail’s current sense op amp has its gain set to provide approximately 2V maximum at the TI UCD90120A ADC input pin when the rail current is at its expected maximum current level, as can be seen in the U48 controller power system figure (Figure 1-33).

The TI UCD90120A module has an assignable group of GPIO pins with PWM capability. Each controller “channel” has a PWM GPIO pin wired to the associated voltage regulator V The external V

setting resistor is also wired to this pin. The PWM GPIO pin is configured

OUT

ADJ

pin.

in 3-state mode. This pin is not driven unless a Margin command is executed. The Margin command is available within the TI Fusion Digital Power™ designer software.

During the margin-High or Low operation, the PWM GPIO pin drives a voltage into the voltage regulator V V

moving to the margin +5% or -5% voltage commanded.

OUT

pin, which causes a slight voltage change resulting in the regulator

ADJ

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UG954 (v1.5) September 10, 2015

XADC Power System Measurement

The ZC706 board XADC interface includes power system voltage and current measuring capability. The V voltage measurement capability. Other rails are measured through an external Analog Devices ADG707BRU multiplexer U6. Each rail has a separate TI INA333 op amp strapped across its series current sense resistor Kelvin terminals. This op amp has its gain adjusted to give approximately 1V at the expected full scale current value for the rail.

CCINT

and V

rail voltages are measured using the XADC internal

CCAUX

X-Ref Target - Figure 1-34

Notes:

1. _XADC_P/N = Remote Voltage Sense

2. _XADC_CS_P/N = Current Sense From OP Amp

UG954_c1_34_041113

3.3 Scaled to 0.825V

ADG707BRU

Bank 35

ADIP L13

10PF

3.01K

1.00K

GND

49.9

A[2:0]

P14 17

P15 18

P16 19

S1A/B

S2A/B

S3A/B

S4A/B

S5A/B

S6A/B

S7A/B

S8A/B

VCC3V3_FPGA_SENSE_P

VCC3V3_FPGA_XADC_P

VCC3V3_FPGA_SENSE_N

VADJ 2.5V Scaled to 0.625V

3.01K

1.00K

GND

VCC3V3_FPGA_SENSE_P

VCC3V3_FPGA_XADC_P

VCC3V3_FPGA_SENSE_N

Scaled to 0.75V

3.01K

1.00K

GND

VCC3V3_FPGA_SENSE_P

VCC3V3_FPGA_XADC_P

VCC3V3_FPGA_SENSE_N

VCCINT_XADC_CS_P/N

VCCAUX_XADC_CS_P/N

VCC1V5_PL_XADC_P/N

VCC1V5_PL_XADC_CS_P/N

VADJ_FPGA_XADC_P/N

VADJ_FPGA_XADC_CS_P/N

VCC3V3_PL_XADC_P/N

VCC3V3_PL_XADC_CS_P/N

AD1N K13

U16

XC7Z045

TCA6416APWR

12C Port

Expander

Send Feedback

Feature Descriptions

Figure 1-34 shows the XADC external MUX block diagram.

See Tab le 1-3 5 which lists the ZC706 XADC power system voltage and current measurement details for the external MUX U6.

Table 1-35: XADC Measurements through MUX U6

Meas.

Type

V VCCINT NA NA NA NA XADC INTERNAL NA NA NA

I VCCINT CS 0A-8A U69 20 0V-0.8V VCCINT_XADC_CS_P 19 S1A 000

V VCCAUX NA NA NA NA XADC INTERNAL NA NA NA

I VCCAUX CS 0A-4A U68 50 0V-1V VCCAUX_XADC_CS_P 20 S2A 001

V VCC1V5_PL NA VCC1V5_PL REMOTE SENSE DIVIDED

I VCC1V5_PL CS 0A-2A U67 100 0V-1V VCC1V5_PL_XADC_CS_P 22 S4A 011

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UG954 (v1.5) September 10, 2015

Rail Name

Figure 1-34: XADC External MUX Block Diagram

Current

Range

Isense Op Amp

Reference

Designator

Gain Vo Range

TO DELIVER 0.75V ON

VCC1V5_PL_XADC_P

8-to-1 MUX U6

Schematic Net Name

VCCINT_XADC_CS_N 11 S1B

VCCAUX_XADC_CS_N 10 S2B

VCC1V5_PL_XADC_P 21 S3A 010

VCC1V5_PL_SENSE_N 9 S3B

VCC1V5_PL_XADC_CS_N 8 S4B

Num

Name

MUX A[2:0]

Table 1-35: XADC Measurements through MUX U6 (Cont’d)

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Feature Descriptions

Meas.

Type

V VADJ_FPGA NA VADJ_FPGA 2.5V REMOTE SENSE

I VADJ_FPGA CS 0A-2A U70 100 0V-1V VADJ_FPGA_XADC_CS_P 24 S6A 101

V VCC3V3_FPGA NA VCC3V3_FPGA REMOTE SENSE

I VCC3V3_FPGA CS 0A-2A U97 100 0V-1V VCC3V3_FPGA_XADC_CS_P 26 S8A 111

Rail Name

Current

Range

Reference

Designator

DIVIDED TO DELIVER 0.625V ON

DIVIDED TO DELIVER 0.825V ON

Isense Op Amp

Gain Vo Range

VADJ_FPGA_X ADC _P

VCC3V3_FPGA_XADC_P

Schematic Net Name

VADJ_FPGA_X ADC _P 23 S5A 100

VADJ_FPGA_SENSE_N 7 S5B

VADJ_FPGA_XADC_CS_N 6 S6B

VCC3V3_FPGA_XADC_P 25 S7A 110

VCC3V3_FPGA_SENSE_N 5 S7B

VCC3V3_FPGA_XADC_CS_N 4 S8B

8-to-1 MUX U6

Num

Name

MUX A[2:0]

Power Management

[Figure 1-2, callout 32]

The ZC706 board uses power regulators and a PMBus-compliant system controller from Texas Instruments to supply core and auxiliary voltages. The Texas Instruments Fusion Digital Power graphical user interface is used to monitor the voltage and current levels of the board power modules.

The PCB layout and power system design meet the recommended criteria described in Zynq-7000 All Programmable SoC PCB Design and Pin Planning Guide (UG933

The ZC706 evaluation board power distribution diagram is shown in Figure 1-35.

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UG954 (v1.5) September 10, 2015

Switching Module VCC1V8/VCCAUX 1.8V @ 10A U98 p. 51

Switching Module

VCC1V5_PL 1.5V @ 6A

U85 p. 52

Switching Module VADJ/VADJ _FPGA 2.5V @ 6A U96 p. 53

Switching Module

VCC3V3/VCC3V3_FPGA 3.3V @ 10A

U15 p. 54

Linear Regulator

MGTVCCAUX 1.8V @ 3A

U95 p. 57

Linear Regulator

VCC2V5 2.5V @ 1.5A

U19 p. 57

Linear Regulator

MGTAVCC 1.0V @ 3A

U93 p. 57

Linear Regulator

MGTAVTT 1.2V @ 3A

U94 p. 57

Linear Regulator

VCCAUX_IO 2.0V @ 3A

U92 p. 57

Source/Sink Regulator

VTTDDR_PL 0.75V @ 3A

U28 p. 56

Source/Sink Regulator

VTTDDR_PS 0.75V @ 0.5A (3A Max)

U27 p. 56

Switching Module

VCCINT 1.00V @ 16A

Power Controller 1

PMBus 0x65

Note: Page numbers reference the pages on schematic 0381513

12V

PWR

Jack

J22

U42 p. 50

U48 p. 49

p. 48

Switching Dual

VCC1V5_PS 1.5V @ 2.5A

U104 p. 55

Switching Dual

VCCPINT 1.0V @ 1.5A

U104 p. 55

Switching Dual

VCC3V3_PS 3.3V @ 2.5A

U105 p. 55

Switching Dual

VCCP1V8 1.8V @ 1.5A

U105 p. 55

Linear Regulator

V33D_CTL1 3.3V @ 0.25A

U20 p. 49

Switching Regulator

VCC5V0 5.0V @ 2A

U44 p. 56

UG954_c1_35_031615

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X-Ref Target - Figure 1-35

Feature Descriptions

The ZC706 evaluation board uses power regulators and PMBus compliant PWM system controllers from Texas Instruments to supply the core and auxiliary voltages listed in

Tab le 1- 36.

Figure 1-35: Onboard Power Regulators

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Table 1-36: Onboard Power System Devices

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Feature Descriptions

(1)(6)

(7)

(8)

Reference

Designator

U42 16A 0.6 - 3.6V Adj. Switching Regulator VCCINT

U98 10A 0.6V - 5.5V Adj. Switching Regulator VCCAUX

U15 10A 0.6V - 5.5V Adj. Switching Regulator VCC3V3_FPGA

2.5A 0.8V - 10V Adj. Switching Regulator VCCPINT 1.00V 55

U104

2.5A 0.8V - 10V Adj. Switching Regulator VCC1V5_PS 1.50V 55

2.5A 0.8V - 10V Adj. Switching Regulator VCCP1V8 1.80V 55

U105

2.5A 0.8V - 10V Adj. Switching Regulator VCC3V3_PS 3.30V 55

U44 2A 0.6V - 5.5V Adj. Switching Regulator VCC5V0 5.00V 56

Description

Device Type

UCD90120A U48 PMBus Controller, PMBus Addr = 101 49

LMZ31520RLG

LMZ31710RVQ

LMZ31506RUQ U85 6A 0.6V - 5.5V Adj. Switching Regulator VCC1V5_PL 1.50V 52

LMZ31506RUQ U86 6A 0.6V - 5.5V Adj. Switching Regulator VADJ_FPGA

LMZ31710RVQ

TPS54291PWP (Dual Output)

TPS51200DR U27 3A Push/Pull Tracking Regulator VTTDDR_PS 0.75V 56

TPS51200DR U28 3A Push/Pull Tracking Regulator VTTDDR_SODIMM 0.75V 56

TPS74901RGW U92 3A 0.8V - 3.6V Adj. Linear Regulator VCCAUX_IO 2.00V 57

TPS74901RGW U93 3A 0.8V - 3.6V Adj. Linear Regulator MGTAVCC 1.00V 57

TPS74901RGW U94 3A 0.8V - 3.6V Adj. Linear Regulator MGTAVTT 1.20V 57

TPS74901RGW U95 3A 0.8V - 3.6V Adj. Linear Regulator MGTVCCAUX 1.80V 57

TL1963A U19 1.5A 1.21V - 3.3V Adj. Linear Regulator VCC2V5 2.50V 57

TPS79433 U20 0.25A 3.3V Fixed Linear Regulator V33D_CTL1 3.30V 49

LMZ31704RVQ

Power Rail

Net Name

(2)

(3)

(4)

(5)

Power Rail

Volta ge

1.00V 50

1.80V 51

2.50V 53

3.30V 54

Schematic

Page

Notes:

1. VCCINT max. current is 16A

2. VCCBRAM 1.0V is also sourced from the Vccint rail

3. VCC1V8 1.80V is also sourced from the Vccaux rail

4. VADJ (1.80V/2.50V/3.30V) for the FMC connectors is also sourced from the Vadj_fpga rail

5. VCC3V3 3.30V is also sourced from the Vcc3v3_fpga rail

6. Paralleled dual LMZ22008TZ (U42/U43) 8A 0.8V - 6V Adj. Switching Regulators on ZC706 board versions prior to Rev. 2.0

7. LMZ22010TZ (U98 VCCAUX, U15 VCC3V3_FPGA) 10A 0.8 - 6V Adj. Switching Regulators on ZC706 board versions prior to Rev.

2.0

8. LMZ12002TZ U44 2A 0.8 - 6V Adj. Switching Regulator on ZC706 board versions prior to Rev. 2.0

VADJ Voltage Control

The V FMC_VADJ_ON_B signal wired to header J18 is sampled by the TI UCD90120A controller U48. If a jumper is installed on J18 signal FMC_VADJ_ON_B is held Low, and the TI controller U48 energizes the V

rail is set to 2.5V. When the ZC706 evaluation board is powered on, the state of the

ADJ

rail at power on.

ADJ

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Feature Descriptions

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Because the rail turn on decision is made at power on time based on the presence of the J18 jumper, removing the jumper at J18 after the board is powered up does not affect the 2.5V power delivered to the V

rail and it remains on.

ADJ

A jumper installed at J18 is the default setting.

In this mode the user can control when to turn on V

2.5V, 3.3V). With V

off the XC7Z045 AP SoC still configures and has access to the TI

ADJ

and to which voltage level (1.8V,

ADJ

controller PMBUS along with the FMC_VADJ_ON_B signal. The combination of these allows the user to develop code to command the V default setting of 2.5V. Once the new V

ADJ

controller U48, the FMC_VADJ_ON_B signal can be driven low by the user logic and the V rail comes up at the new V powers up in the V

off (no jumper on J18 at ZC706 power up) mode turns on the V

ADJ

voltage level. Installing a jumper at J18 after a ZC706 board

ADJ

The FMC_VADJ_ON_B signal is connected to the TCA6416APWR I

rail to be set to something other than the

ADJ

voltage level has been programmed into TI

ADJ

C port expander U16 pin

ADJ

rail.

13 (see Figure 1-28). The XC7Z045 AP SoC is thus able to drive the FMC_VADJ_ON_B signal by writing to the I²C port expander U16.

The I

C port expander IIC_PORT_EXPANDER SDA/SCL bus is wired to the PCA9548ARGER I2C

U65 bus switch (see I2C Bus, page 53).

Documentation describing PMBUS programming for the UCD90120A power controller is available at the website [Ref 26].

AP SoC Programmable Logic (PL) Voltage Control

All PL and PS power rails are enabled by default. When the ZC706 board is powered on, the state of the PL_PWR_ON signal wired to 2-pin header J66 is sampled by the TI UCD90120A controller U48. If a jumper is not installed on J66, signal PL_PWR_ON is held high, and the TI controller U48 energizes all the PL and PS power rails.

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Because the rail turn on decision is made at power on time based on the presence of the J66 jumper, installing the jumper at J66 after the board is powered up does not affect power delivered to the any PS or PL rails, all rails remain on.

A jumper not installed at J66 is the default setting.

If a jumper is installed on J66 when the ZC706 board is powered on, signal PL_PWR_ON is held low, and the ZC706 board does not energize the PL side power rails at power on.

Monitoring Voltage and Current

Voltage and current monitoring and control are available for selected power rails through Texas Instruments' Fusion Digital Power Designer graphical user interface. The onboard TI power controller (U48 at address 101) is accessed through the PMBus connector J4, which is provided for use with the TI USB Interface Adapter PMBus pod (TI part number EVM USB-TO-GPIO), which can be ordered from the Texas Instruments website [Ref 27] and

Feature Descriptions

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associated TI Fusion Digital Power Designer GUI (downloadable from the TI site [Ref 28]. This is the simplest and most convenient way to monitor the voltage and current values for the power rails listed in Table 1 -37 .

In the table, the Power Good (PG) On Threshold is the setpoint at or above which the particular rail is deemed "good". The PG Off Threshold is the setpoint at or below which the particular rail is no longer deemed "good". The controller internally OR's these per rail PG conditions together and drives an output PG pin high only if all active rail PG states are "good". The On and Off Delay and parameters are relative to when the board power on-off slide switch SW12 is turned on and off.

Tab le 1- 37 Power Rail Specifications for UCD90120A PMBus controller at Address 101

defines the voltage and current values for each power rail controlled by the UCD90120A U48.

IMPORTANT: In Ta b le 1- 37, the values defined in the Shutdown columns are the voltage and current

thresholds that cause the regulator to shut down if the value is exceeded.

Table 1-37: Power Rail Specifications for UCD90120A PMBus Controller at Address 101

Device Address Rail

Nominal

Voltage

Power

Good

Power

Good

Off

Turn

Delay

(ms)

(2)

Turn

Off

Delay

(ms)

Shutdown

Over

Voltage

(1)

Over

Current

101d 1 VCCINT 1.000 0.900 0.850

2 VCCAUX 1.800 1.620 1.530

UCD90120A

U48

Notes:

1. The values defined in these columns are the voltage and current thresholds that cause the regulator to shut down if the value is exceeded.

2. See Tab le 1- 39 for rail turn on dependency details.

3 VCC1V5_PL 1.500 1.350 1.275

4 VADJ_FPGA 2.500 2.250 2.125

5 VCC3V3_FPGA 3.300 2.970 2.805

0.0 25.0

5.0 20.0

5.0 10.0

5.0 5.0

5.0 15.0

1.150 11.50

2.070 6.91

1.725 3.50

2.875 3.50

3.795 6.91

The ZC706 power system rail turn on timing is not strictly controlled through the Turn On Delay shown in Tab le 1- 37. The Ta ble 1 -37 Turn On Delay delay values are applied after the preceding rail has reached 90% of its nominal voltage. See Tab le 1- 38 for rail turn on dependency details.

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Feature Descriptions

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Table 1-38: Power Rail Sequence On Dependencies for UCD90120A PMBus Controller at Address 101

Device Address Rail

1 VCCINT 1.000 1 Turn on at board power-on

2 VCCAUX 1.800 2 5ms after VCCINT hits 90%

UCD90120A 101d

5 VCC3V3_FPGA 3.300 3 5ms after VCCAUX hits 90%

3 VCC1V5_PL 1.500 4 5ms after VCC3V3 hits 90%

4 VADJ_FPGA 2.500 5 5ms after VCC1V5_PL hits 90%

Cooling Fan

The XC7Z045 AP SoC cooling fan connector is shown in Figure 1-36.

X-Ref Target - Figure 1-36

Keyed Fan Header

22_11_2032

J61

R369

1.00K

1/16W

SM FAN PWM

VADJ

Nominal

Voltage

Turn On Order Turn On Timing

VCC12_P

R279

10.0K 1/10W

1 2

SM FAN TACH

R278

10.0K 1/10W 1%

R190

4.75K 1/10W

MM3Z2V7B

2.7V 460MW

2 4

DL4148 100V

460MW

1.3W NDT3055L

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GND GND

UG954_c1_36_073013

Figure 1-36: Cooling Fan Circuit

When V

is modified from a default of 2.5V to 1.8V or a lower V

ADJ

setting, the AP SoC U1

ADJ

cooling fan turns off. Transistor Q1 is used to switch on the fan and has a max VGS of 2V, hence the fan is not guaranteed to work at 1.8V or lower V

setting. See [Ref 15].

ADJ,

The fan turns on when the ZC706 is powered up due to pull-up resistor R369. The SM_FAN_PWM and SM_FAN_TACH signals are wired to XC7Z045 AP SoC U1 pins AB19 and

X-Ref Target - Figure 1-37

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Feature Descriptions

AA19 respectively, enabling the user to implement their own fan speed control IP in the AP SoC PL logic.

More information about the power system components used by the ZC706 evaluation board are available from the Texas Instruments digital power website [Ref 32].

XADC Analog-to-Digital Converter

[Figure 1-2, callout 33]

The XC7Z045 AP SoC provides an Analog Front End XADC block. The XADC block includes a dual 12-bit, 1 MSPS Analog-to-Digital Convertor (ADC) and on-chip sensors. See 7Series

FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide (UG480

Figure 1-37 shows the XADC block diagram.

XC7Z020

AP SoC

VCCADC

)for details on the capabilities of the analog front end.

VCCAUX

Ferrite Bead

To J54

XADC_VCC

100 nF Close to Package Pins

XADC_AGND

J53

XADC_VCC Header J40

10 μF

1.8V 150 mV max

U14

ADP123

Out

Gnd

XADC_VCC5V0 To Header J63

Ferrite Bead

J14

10 μF

VCC5V0

Header

J63

Dual Use IO

(Analog/Digital)

100Ω

1 nF

100Ω

1 nF

100Ω

VAUX0P

VAUX0N

VAUX8P

VAUX8N

GNDADC

REFP

REFN

DXP

DXN

XADC_AGND

XADC_VREFP

100 nF

Close to Package Pins

100Ω

1 nF

100Ω

XADC_AGND

To Header J63

XADC_VREF

J52

XADC_AGND

Header

J63

U38

(1.25V)

Out In

10 μF

XADC_AGND

Connection

Figure 1-37: XADC Block Diagram

REF3012

Gnd

Star Grid

Ferrite Bead

J12

J54

XADC_VCC

J13

GND

UG8954_c1_37_041715

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X-Ref Target - Figure 1-38

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Feature Descriptions

The ZC706 evaluation board supports both the internal XC7Z045 AP SoC sensor measurements and the external measurement capabilities of the XADC. Internal measurements of the die temperature, VCCINT, VCCAUX, and VCCBRAM are available.

Jumper J52 can be used to select either an external voltage reference (VREF) or on-chip voltage reference for the analog-to-digital converter.

For external measurements an XADC header (J63) is provided. This header can be used to provide analog inputs to the XC7Z045 AP SoC's dedicated VP/VN channel, and to the VAUXP[0]/VAUXN[0], VAUXP[8]/VAUXN[8] auxiliary analog input channels. Simultaneous sampling of Channel 0 and Channel 8 is supported.

A user-provided analog signal multiplexer card can be used to sample additional external analog inputs using the 4 GPIO pins available on the XADC header as multiplexer address lines. Figure 1-38 shows the XADC header connections.

VCC1V5_PL

XADC_VCC5V0

XADC_VN XADC_VAUX0P

XADC_VAUX8N XADC_DXP XADC_VREF

XADC_GPIO_1 XADC_GPIO_3

J63

9 11 13 15 17 19

12 14 16 18 20

XADC_VCC_HEADER

XADC_VP

XADC_VAUX0N

XADC_VAUX8P

XADC_DXN

XADC_GPIO_0 XADC_GPIO_2

Figure 1-38: XADC Header (J63)

Tab le 1- 39 describes the XADC header J40 pin functions.

Table 1-39: XADC Header J63 Pinout

Net Name

VN, VP 1, 2 Dedicated analog input channel for the XADC.

XADC_VAUX0P, N 3, 6

XADC_VAUX8N, P 7, 8

DXP, DXN 9, 12 Access to thermal diode.

XADC_AGND 4, 5, 10 Analog ground reference.

XADC_VREF 11 1.25V reference from the board.

XADC_VCC5V0 13 Filtered 5V supply from board.

XADC_VCC_HEADER 14 Analog 1.8V supply for XADC.

J63 Pin

Number

Auxiliary analog input channel 0. Also supports use as I/O inputs when anti alias capacitor is not present.

Auxiliary analog input channel 8. Also supports use as I/O inputs when anti alias capacitor is not present.

XADC_AGNDXADC_AGND

Description

GND

UG954_c1_38_041113

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VCC1V5_PL 15 VCCO supply for bank which is the source of DIO pins.

Table 1-39: XADC Header J63 Pinout (Cont’d)

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Feature Descriptions

Net Name

GND 16 Digital Ground (board) Reference

XADC_GPIO_3, 2, 1, 0

J63 Pin

Number

19, 20, 17,

Description

Digital I/O. These pins should come from the same bank. These IOs should not be shared with other functions because they are required to support three-state operation.

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Appendix A

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Default Switch and Jumper Settings

The default switch and jumper settings for the ZC706 evaluation board are provided in this appendix.

Switches

[Figure 1-2, callout 24]

Default switch settings are listed in Tabl e A-1 . The locations of the ZC706 jumper headers called out in Tab le A -2 are shown in Figure A-1.

Table A-1: Default Switch Settings

Switch Function Default Selects

SW1 Board main power On-Off Slide Switch

SW4 2-pole SPST DIP Switch, JTAG mode select

signals JTAG_SEL_[1:2]

SW11 5-pole DPDT DIP Switch, PS Boot Mode select

signals MIO[6:2]_SELECT

SW12 4-pole SPST DIP Switch, user signals

GPIO_DIP_SW[0:3], poles [1:4]

OFF

All Down

All OFF

Delivered in OFF position

JTAG = cable connector J3

JTAG flat cable header J3

All = 0 (4.7K p/d to GND)

Figure 1-2

Callout

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Jumpers

Send Feedback

[Figure 1-2, callout 24]

Default jumper positions are listed in Tabl e A-2 .

Table A-2: Default Jumper Settings

Jumpers

Jumper

Callout

Jumper Function

HDR_1 X 2

1J6

J65

2 J7 U8 MAX16025 POR Device Reset MR_B pin 13 logic

3 J8 JTAG Header J62 pin 2 can be connected to 3.3V OPEN J62 pin 2 is NC 16

4 J9 U51 Ethernet PHY CONFIG2 pin 2 1K pull-down to

5 J10 U12 USB3320 2.0 Host/OTG or Device Select

6 J11 U12 USB3320 2.0 RESET Header OPEN U12 not held in RESET 31

7 J12 U38 REF3012 VREF XADC_AGND-to-GND L3

8 J13 U38 REF3012 VREF XADC_AGND-to-GND Select

9 J14 XADC circuit VCC5V0 sources XADC_VCC5V0 Select

10 J15 ARM PJTAG Header J64 pin 2 can be connected to

11 J17 SPF+ P2 pin 3 SFP_TX_DISABLE_TRANS logic 0/1

12 J18 FMC_VADJ_ON_B Select Header 1-2 FMC VADJ enabled (U48

13 J19 PCIe® Lane Width Select Header 3-4 4-Lane PCIe selected 42

14 J66 PL_PWR_ON Header OPEN PL Power enabled

15 J69 XADC Power System Vccint CS OpAmp U69 Gain

16 J70 MIO Select Header MIO2 (Note: DIP SW11 pole 1

17 J71 MIO Select Header MIO3 (Note: DIP SW11 pole 2

AP SoC U1 Bank 0 CFGBVS pin V9 logic 0/1 Select

(call out #1 applies to this, too):

J65 is an INIT_B (pin 1) and DONE (pin 2) test header

0/1 Select

logic 0 (GND)

Header

inductor bypass

Header

VADJ

Select Header

affects this signal)

Default Jumper

Position

OPEN

OPEN U8 MR_B pin 13 = 1 15

1-2 U51 pin 2 CONFIG2 = 0

1-2 HOST source VBUS power

OPEN L3 not bypassed 35

1-2 XADC_AGND connected to

1-2 XADC_VCC5V0 = filtered

OPEN J64 pin 2 is NC 39

OPEN SPF+ P2 SFP TX is enabled

OPEN U69 Current Sense OpAmp

1-2 QSPI0_IO0 = MIO2_SELECT 15

1-2 QSPI0_IO1 = MIO3_SELECT 15

Option Selected

CFGBVS pin V9 = 1

N/A

(from U22)

GND

(L1) VCC5V0

(P2 pin 3 = 1)

UCD90120A pin 37 = logic

(U48 UCD90120A pin 24 = logic 1)

Gain = 1 0

Schematic

0381513

Page

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Table A-2: Default Jumper Settings (Cont’d)

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Jumpers

Jumper

Callout

Jumper Function

18 J72 MIO Select Header MIO4 (Note: DIP SW11 pole 3

affects this signal)

19 J73 MIO Select Header MIO5 (Note: DIP SW11 pole 4

affects this signal)

20 J74 MIO Select Header MIO6 (Note: DIP SW11 pole 5

affects this signal)

HDR_1 X 3

21 J43 PS_SRST_B Select Header 1-2 PS_SRST_B = PS_SRST_B_SW

22 J44 PS_POR_B Select Header 1-2 PS_POR_B = PS_POR_B_SW

23 J45 U51 Ethernet PHY CONFIG3 pin 3 1K pull-up to 1.8V

or 1 KΩ pull-down to GND Select Header

24 J46 U51 Ethernet PHY CONFIG2 pin 2 tie to 1.8V or

LED0 Select Header

25 J47 U51 Ethernet PHY CONFIG3 pin 3 LED1 or LED0

Select Header

26 J48 U12 USB3320 2.0 MODE Select Header 2-3 HOST/OTG Mode selected 31

27 J49 USB 2.0 Micro-B connector J2 ID pin 4 function

Select Header

28 J50 USB_VBUS_SEL 1uF/120 uF capacitor to GND Select

Header

29 J51 USB 2.0 Micro-B connector J2 ID shield pins

connection Select Header

30 J52 XADC_VREFP source Select Header 1-2 XADC_VREFP = XADC_VREF 35

31 J53 XADC_VCC source Select Header 1-2 XADC_VCC = VCCAUX 1.8V 35

32 J54 U38 REF3012 VREF Vin Select Header 2-3 U38 powered by XADC_VCC

33 J55 SPF+ P2 SFP_RS1 BW Select Header 2-3 LOW BW TX selected 41

34 J56 SPF+ P2 SFP_RS0 BW Select Header 2-3 LOW BW RX selected 41

Default Jumper

Position

1-2 QSPI0_IO4 = MIO2_SELECT 15

1-2 QSPI0_IO5 = MIO2_SELECT 15

1-2 QSPI0_CLK = MIO6_SELECT 15

1-2 U51 pin 3 CONFIG3 = 1 (p/u

OPEN J9 sets U51 pin 2 CONFIG2

OPEN No connection to LED0 or

1-2 J2 ID pin 4 connected to

2-3 USB_VBUS_SEL net has 120

1-2 J2 shield pins to GND 31

Option Selected

(MAX16025 U8 pin 10)

(MAX16025 U8 pin 11)

to 1.8V)

condition

LED1, J45 sets U51 pin 3 CONFIG3 condition

USB3320 U12 pin 23 ID

uF to GND

(U14 1.85V)

Schematic

0381513

Page

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X-Ref Target - Figure A-1

UG954_aA_01_042415

24 25

31 9 30

26 28

21 22

17 18

Send Feedback

Jumpers

Figure A-1: ZC706 Jumper Header Locations

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VITA 57.1 FMC Connector Pinouts

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Figure B-1 shows the pinout of the FPGA mezzanine card (FMC) low pin count (LPC)

connector defined by the VITA 57.1 FMC specification. For a description of how the ZC706 evaluation board implements the FMC specification, see FPGA Mezzanine (FMC) Card

Interface, page 65 and LPC Connector J5, page 69.

X-Ref Target - Figure B-1

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

KJHGFEDCBA

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

VREF_A_M2C

PRSNT_M2C_L

GND CLK0_M2C_P CLK0_M2C_N

GND

LA02_P LA02_N

GND

LA04_P LA04_N

GND

LA07_P LA07_N

GND

LA11_P LA11_N

GND

LA15_P LA15_N

GND

LA19_P LA19_N

GND

LA21_P LA21_N

GND

LA24_P LA24_N

GND

LA28_P LA28_N

GND

LA30_P LA30_N

GND

LA32_P LA32_N

GND

VADJ

GND CLK1_M2C_P CLK1_M2C_N

GND

LA00_P_CC LA00_N_CC

GND

LA03_P

LA03_N

GND

LA08_P

LA08_N

GND

LA12_P

LA12_N

GND

LA16_P

LA16_N

GND

LA20_P

LA20_N

GND

LA22_P

LA22_N

GND

LA25_P

LA25_N

GND

LA29_P

LA29_N

GND

LA31_P

LA31_N

GND

LA33_P

LA33_N

GND

VADJ

GND

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

PG_C2M

GND

GND GBTCLK0_M2C_P GBTCLK0_M2C_N

GND

LA01_P_CC LA01_N_CC

GND

LA05_P

LA05_N

GND

LA09_P

LA09_N

GND

LA13_P

LA13_N

GND

LA17_P_CC LA17_N_CC

GND

LA23_P

LA23_N

GND

LA26_P

LA26_N

GND

TCK TDI

TDO

3P3VAUX

TMS

TRST_L

GA1 3P3V GND 3P3V GND 3P3V

GND DP0_C2M_P DP0_C2M_N

GND

GND DP0_M2C_P DP0_M2C_N

GND

LA06_P LA06_N

GND

LA10_P LA10_N

GND

LA14_P LA14_N

GND

LA18_P_CC LA18_N_CC

GND

LA27_P LA27_N

GND

SCL

SDA GND GND

GA0

12P0V

GND

12P0V

GND 3P3V GND

Appendix B

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

UG954_aB_01_100112

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Figure B-1: FMC LPC Connector Pinout

Figure B-2 shows the pinout of the FPGA mezzanine card (FMC) high pin count (HPC)

connector defined by the VITA 57.1 FMC specification. For a description of how the ZC706 evaluation board implements the FMC specification, see FPGA Mezzanine (FMC) Card

Interface, page 65 and HPC Connector J37, page 65.

X-Ref Target - Figure B-2

UG954_aB_02_100112

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

VREF_B_M2C

GND GND

CLK2_M2C_P

CLK2_M2C_N

GND HA02_P HA02_N

GND HA06_P HA06_N

GND HA10_P HA10_N

GND

HA17_P_CC HA17_N_CC

GND HA21_P HA21_N

GND HA23_P HA23_N

GND

HB00_P_CC HB00_N_CC

GND

HB06_P_CC HB06_N_CC

GND HB10_P HB10_N

GND HB14_P HB14_N

GND

HB17_P_CC HB17_N_CC

GND

VIO_B_M2C

GND CLK3_M2C_P CLK3_M2C_N

GND

HA03_P HA03_N

GND

HA07_P HA07_N

GND

HA11_P HA11_N

GND

HA14_P HA14_N

GND

HA18_P HA18_N

GND

HA22_P HA22_N

GND

HB01_P HB01_N

GND

HB07_P HB07_N

GND

HB11_P HB11_N

GND

HB15_P HB15_N

GND

HB18_P HB18_N

GND

VIO_B_M2C

GND

VREF_A_M2C

PRSNT_M2C_L

GND

CLK0_M2C_P

CLK0_M2C_N

GND LA02_P LA02_N

GND LA04_P LA04_N

GND LA07_P LA07_N

GND LA11_P LA11_N

GND LA15_P LA15_N

GND LA19_P LA19_N

GND LA21_P LA21_N

GND LA24_P LA24_N

GND LA28_P LA28_N

GND LA30_P LA30_N

GND LA32_P LA32_N

GND

VADJ

GND

DP1_M2C_P

DP1_M2C_N

GND GND

DP2_M2C_P

DP2_M2C_N

GND GND

DP3_M2C_P

DP3_M2C_N

GND GND

DP4_M2C_P

DP4_M2C_N

GND GND

DP5_M2C_P

DP5_M2C_N

GND GND

DP1_C2M_P

DP1_C2M_N

GND GND

DP2_C2M_P

DP2_C2M_N

GND GND

DP3_C2M_P

DP3_C2M_N

GND GND

DP4_C2M_P

DP4_C2M_N

GND GND

DP5_C2M_P

DP5_C2M_N

GND

RES1

GND

GND DP9_M2C_P DP9_M2C_N

GND

GND DP8_M2C_P DP8_M2C_N

GND

GND DP7_M2C_P DP7_M2C_N

GND

GND DP6_M2C_P DP6_M2C_N

GND

GBTCLK1_M2C_P GBTCLK1_M2C_N

GND

GND DP9_C2M_P DP9_C2M_N

GND

GND DP8_C2M_P DP8_C2M_N

GND

GND DP7_C2M_P DP7_C2M_N

GND

GND DP6_C2M_P DP6_C2M_N

GND

RES0

GND DP0_C2M_P DP0_C2M_N

GND

GND DP0_M2C_P DP0_M2C_N

GND

LA06_P LA06_N

GND

LA10_P LA10_N

GND

LA14_P LA14_N

GND

GND LA18_P_CC LA18_N_CC

GND

LA27_P LA27_N

GND

SCL

SDA

GND

GA0

12P0V

GND

12P0V

GND

3P3V

GND

PG_C2M

GND

GND GBTCLK0_M2C_P GBTCLK0_M2C_N

GND

LA01_P_CC LA01_N_CC

GND

LA05_P LA05_N

GND

LA09_P LA09_N

GND

LA13_P LA13_N

GND

LA17_P_CC LA17_N_CC

GND

LA23_P LA23_N

GND

LA26_P LA26_N

GND

TCK

TDI

TDO

3P3VAUX

TMS

TRST_L

GA1

3P3V

GND

3P3V

GND

3P3V

GND HA01_P_CC HA01_N_CC

GND

HA05_P HA05_N

GND

HA09_P HA09_N

GND

HA13_P HA13_N

GND

HA16_P HA16_N

GND

HA20_P HA20_N

GND

HB03_P HB03_N

GND

HB05_P HB05_N

GND

HB09_P HB09_N

GND

HB13_P HB13_N

GND

HB19_P HB19_N

GND

HB21_P HB21_N

GND

VADJ

GND

PG_M2C

GND

GND HA00_P_CC HA00_N_CC

GND

HA04_P HA04_N

GND

HA08_P HA08_N

GND

HA12_P HA12_N

GND

HA15_P HA15_N

GND

HA19_P HA19_N

GND

HB02_P HB02_N

GND

HB04_P HB04_N

GND

HB08_P HB08_N

GND

HB12_P HB12_N

GND

HB16_P HB16_N

GND

HB20_P HB20_N

GND

VADJ

GND CLK1_M2C_P CLK1_M2C_N

GND

LA00_P_CC LA00_N_CC

GND

LA03_P LA03_N

GND

LA08_P LA08_N

GND

LA12_P LA12_N

GND

LA16_P LA16_N

GND

LA20_P LA20_N

GND

LA22_P LA22_N

GND

LA25_P LA25_N

GND

LA29_P LA29_N

GND

LA31_P LA31_N

GND

LA33_P LA33_N

GND

VADJ

GND

KJHGFEDCBA

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Figure B-2: FMC HPC Connector Pinout

Master Constraints File Listing

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The master Xilinx Design Constraints (XDC) file template for the ZC706 board provides for designs targeting the ZC706 evaluation board. Net names in the constraints listed below correlate with net names on the latest ZC706 evaluation board schematic. Users must identify the appropriate pins and replace the net names with net names in the user RTL. See Vivado Design Suite User Guide: Using Constraints (UG903

For detailed I/O standards information required for a particular interface, users can refer to the constraint files generated by tools like the Memory Interface Generator (MIG) and Base System Builder (BSB).

) for more information.

Appendix C

The FMC connectors J37 and J5 are connected to 2.5V V cards implement different circuitry, the FMC bank I/O standards must be uniquely defined by each customer.

Note:

Xilinx Zynq-7000 All Programmable SoC ZC706 Evaluation Kit product page (www.xilinx.com/zc706 for the latest pins constraints file.

The constraints file listed in this appendix might not be the latest version. Always refer to the

banks. Because different FMC

ADJ

ZC706 Evaluation Board XDC Listing

#Clocks set_property PACKAGE_PIN G9 [get_ports SYSCLK_N] set_property IOSTANDARD LVDS [get_ports SYSCLK_N] set_property PACKAGE_PIN H9 [get_ports SYSCLK_P] set_property IOSTANDARD LVDS [get_ports SYSCLK_P] set_property PACKAGE_PIN AG14 [get_ports USRCLK_N] set_property IOSTANDARD LVDS_25 [get_ports USRCLK_N] set_property PACKAGE_PIN AF14 [get_ports USRCLK_P] set_property IOSTANDARD LVDS_25 [get_ports USRCLK_P] set_property PACKAGE_PIN AD19 [get_ports USER_SMA_CLOCK_N] set_property IOSTANDARD LVDS_25 [get_ports USER_SMA_CLOCK_N] set_property PACKAGE_PIN AD18 [get_ports USER_SMA_CLOCK_P] set_property IOSTANDARD LVDS_25 [get_ports USER_SMA_CLOCK_P] set_property PACKAGE_PIN W7 [get_ports SMA_MGT_REFCLK_N] set_property PACKAGE_PIN W8 [get_ports SMA_MGT_REFCLK_P] set_property PACKAGE_PIN AC7 [get_ports SI5324_OUT_C_N set_property PACKAGE_PIN AC8 [get_ports SI5324_OUT_C_P set_property PACKAGE_PIN AE20 [get_ports REC_CLOCK_C_N] set_property IOSTANDARD LVDS_25 [get_ports REC_CLOCK_C_N]

)

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ZC706 Evaluation Board XDC Listing

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set_property PACKAGE_PIN AD20 [get_ports REC_CLOCK_C_P] set_property IOSTANDARD LVDS_25 [get_ports REC_CLOCK_C_P] set_property PACKAGE_PIN AJ25 [get_ports SI5324_INT_ALMS] set_property IOSTANDARD LVCMOS25 [get_ports SI5324_INT_ALM_LS] set_property PACKAGE_PIN W23 [get_ports SI5324_RST_LS] set_property IOSTANDARD LVCMOS25 [get_ports SI5324_RST_LS]

#FMC HPC #CLK set_property PACKAGE_PIN AF22 [get_ports FMC_HPC_CLK0_M2C_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_CLK0_M2C_N] set_property PACKAGE_PIN AE22 [get_ports FMC_HPC_CLK0_M2C_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_CLK0_M2C_P] set_property PACKAGE_PIN U27 [get_ports FMC_HPC_CLK1_M2C_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_CLK1_M2C_N] set_property PACKAGE_PIN U26 [get_ports FMC_HPC_CLK1_M2C_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_CLK1_M2C_P]

#DP set_property PACKAGE_PIN AK9 [get_ports FMC_HPC_DP0_C2M_N] set_property PACKAGE_PIN AK10 [get_ports FMC_HPC_DP0_C2M_P] set_property PACKAGE_PIN AH9 [get_ports FMC_HPC_DP0_M2C_N] set_property PACKAGE_PIN AH10 [get_ports FMC_HPC_DP0_M2C_P] set_property PACKAGE_PIN AK5 [get_ports FMC_HPC_DP1_C2M_N] set_property PACKAGE_PIN AK6 [get_ports FMC_HPC_DP1_C2M_P] set_property PACKAGE_PIN AJ7 [get_ports FMC_HPC_DP1_M2C_N] set_property PACKAGE_PIN AJ8 [get_ports FMC_HPC_DP1_M2C_P] set_property PACKAGE_PIN AJ3 [get_ports FMC_HPC_DP2_C2M_N] set_property PACKAGE_PIN AJ4 [get_ports FMC_HPC_DP2_C2M_P] set_property PACKAGE_PIN AG7 [get_ports FMC_HPC_DP2_M2C_N] set_property PACKAGE_PIN AG8 [get_ports FMC_HPC_DP2_M2C_P] set_property PACKAGE_PIN AK1 [get_ports FMC_HPC_DP3_C2M_N] set_property PACKAGE_PIN AK2 [get_ports FMC_HPC_DP3_C2M_P] set_property PACKAGE_PIN AE7 [get_ports FMC_HPC_DP3_M2C_N] set_property PACKAGE_PIN AE8 [get_ports FMC_HPC_DP3_M2C_P] set_property PACKAGE_PIN AH1 [get_ports FMC_HPC_DP4_C2M_N] set_property PACKAGE_PIN AH2 [get_ports FMC_HPC_DP4_C2M_P] set_property PACKAGE_PIN AH5 [get_ports FMC_HPC_DP4_M2C_N] set_property PACKAGE_PIN AH6 [get_ports FMC_HPC_DP4_M2C_P] set_property PACKAGE_PIN AF1 [get_ports FMC_HPC_DP5_C2M_N] set_property PACKAGE_PIN AF2 [get_ports FMC_HPC_DP5_C2M_P] set_property PACKAGE_PIN AG3 [get_ports FMC_HPC_DP5_M2C_N] set_property PACKAGE_PIN AG4 [get_ports FMC_HPC_DP5_M2C_P] set_property PACKAGE_PIN AE3 [get_ports FMC_HPC_DP6_C2M_N] set_property PACKAGE_PIN AE4 [get_ports FMC_HPC_DP6_C2M_P] set_property PACKAGE_PIN AF5 [get_ports FMC_HPC_DP6_M2C_N] set_property PACKAGE_PIN AF6 [get_ports FMC_HPC_DP6_M2C_P] set_property PACKAGE_PIN AD1 [get_ports FMC_HPC_DP7_C2M_N] set_property PACKAGE_PIN AD2 [get_ports FMC_HPC_DP7_C2M_P] set_property PACKAGE_PIN AD5 [get_ports FMC_HPC_DP7_M2C_N] set_property PACKAGE_PIN AD6 [get_ports FMC_HPC_DP7_M2C_P]

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#GBTCLK set_property PACKAGE_PIN AD9 [get_ports FMC_HPC_GBTCLK0_M2C_C_N]

ZC706 Evaluation Board XDC Listing

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set_property PACKAGE_PIN AD10 [get_ports FMC_HPC_GBTCLK0_M2C_C_P] set_property PACKAGE_PIN AA7 [get_ports FMC_HPC_GBTCLK1_M2C_C_N] set_property PACKAGE_PIN AA8 [get_ports FMC_HPC_GBTCLK1_M2C_C_P]

#LA set_property PACKAGE_PIN AG20 [get_ports FMC_HPC_LA00_CC_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA00_CC_N] set_property PACKAGE_PIN AF20 [get_ports FMC_HPC_LA00_CC_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA00_CC_P] set_property PACKAGE_PIN AH21 [get_ports FMC_HPC_LA01_CC_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA01_CC_N] set_property PACKAGE_PIN AG21 [get_ports FMC_HPC_LA01_CC_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA01_CC_P] set_property PACKAGE_PIN AK18 [get_ports FMC_HPC_LA02_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA02_N] set_property PACKAGE_PIN AK17 [get_ports FMC_HPC_LA02_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA02_P] set_property PACKAGE_PIN AJ19 [get_ports FMC_HPC_LA03_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA03_N] set_property PACKAGE_PIN AH19 [get_ports FMC_HPC_LA03_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA03_P] set_property PACKAGE_PIN AK20 [get_ports FMC_HPC_LA04_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA04_N] set_property PACKAGE_PIN AJ20 [get_ports FMC_HPC_LA04_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA04_P] set_property PACKAGE_PIN AH24 [get_ports FMC_HPC_LA05_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA05_N] set_property PACKAGE_PIN AH23 [get_ports FMC_HPC_LA05_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA05_P] set_property PACKAGE_PIN AH22 [get_ports FMC_HPC_LA06_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA06_N] set_property PACKAGE_PIN AG22 [get_ports FMC_HPC_LA06_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA06_P] set_property PACKAGE_PIN AJ24 [get_ports FMC_HPC_LA07_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA07_N] set_property PACKAGE_PIN AJ23 [get_ports FMC_HPC_LA07_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA07_P] set_property PACKAGE_PIN AG19 [get_ports FMC_HPC_LA08_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA08_N] set_property PACKAGE_PIN AF19 [get_ports FMC_HPC_LA08_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA08_P] set_property PACKAGE_PIN AE21 [get_ports FMC_HPC_LA09_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA09_N] set_property PACKAGE_PIN AD21 [get_ports FMC_HPC_LA09_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA09_P] set_property PACKAGE_PIN AG25 [get_ports FMC_HPC_LA10_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA10_N] set_property PACKAGE_PIN AG24 [get_ports FMC_HPC_LA10_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA10_P] set_property PACKAGE_PIN AE23 [get_ports FMC_HPC_LA11_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA11_N] set_property PACKAGE_PIN AD23 [get_ports FMC_HPC_LA11_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA11_P] set_property PACKAGE_PIN AF24 [get_ports FMC_HPC_LA12_N]

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set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA12_N] set_property PACKAGE_PIN AF23 [get_ports FMC_HPC_LA12_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA12_P] set_property PACKAGE_PIN AA23 [get_ports FMC_HPC_LA13_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA13_N] set_property PACKAGE_PIN AA22 [get_ports FMC_HPC_LA13_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA13_P] set_property PACKAGE_PIN AD24 [get_ports FMC_HPC_LA14_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA14_N] set_property PACKAGE_PIN AC24 [get_ports FMC_HPC_LA14_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA14_P] set_property PACKAGE_PIN Y23 [get_ports FMC_HPC_LA15_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA15_N] set_property PACKAGE_PIN Y22 [get_ports FMC_HPC_LA15_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA15_P] set_property PACKAGE_PIN AB24 [get_ports FMC_HPC_LA16_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA16_N] set_property PACKAGE_PIN AA24 [get_ports FMC_HPC_LA16_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA16_P] set_property PACKAGE_PIN W24 [get_ports FMC_HPC_LA17_CC_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA17_CC_N] set_property PACKAGE_PIN V23 [get_ports FMC_HPC_LA17_CC_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA17_CC_P] set_property PACKAGE_PIN W26 [get_ports FMC_HPC_LA18_CC_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA18_CC_N] set_property PACKAGE_PIN W25 [get_ports FMC_HPC_LA18_CC_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA18_CC_P] set_property PACKAGE_PIN T25 [get_ports FMC_HPC_LA19_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA19_N] set_property PACKAGE_PIN T24 [get_ports FMC_HPC_LA19_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA19_P] set_property PACKAGE_PIN V26 [get_ports FMC_HPC_LA20_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA20_N] set_property PACKAGE_PIN U25 [get_ports FMC_HPC_LA20_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA20_P] set_property PACKAGE_PIN W30 [get_ports FMC_HPC_LA21_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA21_N] set_property PACKAGE_PIN W29 [get_ports FMC_HPC_LA21_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA21_P] set_property PACKAGE_PIN W28 [get_ports FMC_HPC_LA22_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA22_N] set_property PACKAGE_PIN V27 [get_ports FMC_HPC_LA22_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA22_P] set_property PACKAGE_PIN P26 [get_ports FMC_HPC_LA23_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA23_N] set_property PACKAGE_PIN P25 [get_ports FMC_HPC_LA23_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA23_P] set_property PACKAGE_PIN U30 [get_ports FMC_HPC_LA24_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA24_N] set_property PACKAGE_PIN T30 [get_ports FMC_HPC_LA24_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA24_P] set_property PACKAGE_PIN U29 [get_ports FMC_HPC_LA25_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA25_N] set_property PACKAGE_PIN T29 [get_ports FMC_HPC_LA25_P]

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set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA25_P] set_property PACKAGE_PIN T28 [get_ports FMC_HPC_LA26_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA26_N] set_property PACKAGE_PIN R28 [get_ports FMC_HPC_LA26_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA26_P] set_property PACKAGE_PIN V29 [get_ports FMC_HPC_LA27_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA27_N] set_property PACKAGE_PIN V28 [get_ports FMC_HPC_LA27_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA27_P] set_property PACKAGE_PIN R30 [get_ports FMC_HPC_LA28_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA28_N] set_property PACKAGE_PIN P30 [get_ports FMC_HPC_LA28_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA28_P] set_property PACKAGE_PIN R26 [get_ports FMC_HPC_LA29_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA29_N] set_property PACKAGE_PIN R25 [get_ports FMC_HPC_LA29_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA29_P] set_property PACKAGE_PIN P24 [get_ports FMC_HPC_LA30_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA30_N] set_property PACKAGE_PIN P23 [get_ports FMC_HPC_LA30_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA30_P] set_property PACKAGE_PIN P29 [get_ports FMC_HPC_LA31_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA31_N] set_property PACKAGE_PIN N29 [get_ports FMC_HPC_LA31_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA31_P] set_property PACKAGE_PIN R21 [get_ports FMC_HPC_LA32_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA32_N] set_property PACKAGE_PIN P21 [get_ports FMC_HPC_LA32_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA32_P] set_property PACKAGE_PIN N27 [get_ports FMC_HPC_LA33_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA33_N] set_property PACKAGE_PIN N26 [get_ports FMC_HPC_LA33_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA33_P]

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#FMC LPC #CLK set_property PACKAGE_PIN AG16 [get_ports FMC_LPC_CLK0_M2C_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_CLK0_M2C_N] set_property PACKAGE_PIN AG17 [get_ports FMC_LPC_CLK0_M2C_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_CLK0_M2C_P] set_property PACKAGE_PIN AD28 [get_ports FMC_LPC_CLK1_M2C_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_CLK1_M2C_N] set_property PACKAGE_PIN AC28 [get_ports FMC_LPC_CLK1_M2C_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_CLK1_M2C_P]

#DP set_property PACKAGE_PIN AB1 [get_ports FMC_LPC_DP0_C2M_N] set_property PACKAGE_PIN AB2 [get_ports FMC_LPC_DP0_C2M_P] set_property PACKAGE_PIN AC3 [get_ports FMC_LPC_DP0_M2C_N] set_property PACKAGE_PIN AC4 [get_ports FMC_LPC_DP0_M2C_P]

#GBTCLK set_property PACKAGE_PIN U7 [get_ports FMC_LPC_GBTCLK0_M2C_C_N] set_property PACKAGE_PIN U8 [get_ports FMC_LPC_GBTCLK0_M2C_C_P]

ZC706 Evaluation Board XDC Listing

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#LA set_property PACKAGE_PIN AF13 [get_ports FMC_LPC_LA00_CC_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA00_CC_N] set_property PACKAGE_PIN AE13 [get_ports FMC_LPC_LA00_CC_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA00_CC_P] set_property PACKAGE_PIN AG15 [get_ports FMC_LPC_LA01_CC_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA01_CC_N] set_property PACKAGE_PIN AF15 [get_ports FMC_LPC_LA01_CC_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA01_CC_P] set_property PACKAGE_PIN AF12 [get_ports FMC_LPC_LA02_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA02_N] set_property PACKAGE_PIN AE12 [get_ports FMC_LPC_LA02_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA02_P] set_property PACKAGE_PIN AH12 [get_ports FMC_LPC_LA03_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA03_N] set_property PACKAGE_PIN AG12 [get_ports FMC_LPC_LA03_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA03_P] set_property PACKAGE_PIN AK15 [get_ports FMC_LPC_LA04_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA04_N] set_property PACKAGE_PIN AJ15 [get_ports FMC_LPC_LA04_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA04_P] set_property PACKAGE_PIN AE15 [get_ports FMC_LPC_LA05_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA05_N] set_property PACKAGE_PIN AE16 [get_ports FMC_LPC_LA05_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA05_P] set_property PACKAGE_PIN AC12 [get_ports FMC_LPC_LA06_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA06_N] set_property PACKAGE_PIN AB12 [get_ports FMC_LPC_LA06_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA06_P] set_property PACKAGE_PIN AA14 [get_ports FMC_LPC_LA07_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA07_N] set_property PACKAGE_PIN AA15 [get_ports FMC_LPC_LA07_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA07_P] set_property PACKAGE_PIN AD13 [get_ports FMC_LPC_LA08_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA08_N] set_property PACKAGE_PIN AD14 [get_ports FMC_LPC_LA08_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA08_P] set_property PACKAGE_PIN AH13 [get_ports FMC_LPC_LA09_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA09_N] set_property PACKAGE_PIN AH14 [get_ports FMC_LPC_LA09_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA09_P] set_property PACKAGE_PIN AC13 [get_ports FMC_LPC_LA10_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA10_N] set_property PACKAGE_PIN AC14 [get_ports FMC_LPC_LA10_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA10_P] set_property PACKAGE_PIN AK16 [get_ports FMC_LPC_LA11_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA11_N] set_property PACKAGE_PIN AJ16 [get_ports FMC_LPC_LA11_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA11_P] set_property PACKAGE_PIN AD15 [get_ports FMC_LPC_LA12_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA12_N] set_property PACKAGE_PIN AD16 [get_ports FMC_LPC_LA12_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA12_P]

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set_property PACKAGE_PIN AH16 [get_ports FMC_LPC_LA13_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA13_N] set_property PACKAGE_PIN AH17 [get_ports FMC_LPC_LA13_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA13_P] set_property PACKAGE_PIN AF17 [get_ports FMC_LPC_LA14_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA14_N] set_property PACKAGE_PIN AF18 [get_ports FMC_LPC_LA14_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA14_P] set_property PACKAGE_PIN AB14 [get_ports FMC_LPC_LA15_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA15_N] set_property PACKAGE_PIN AB15 [get_ports FMC_LPC_LA15_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA15_P] set_property PACKAGE_PIN AE17 [get_ports FMC_LPC_LA16_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA16_N] set_property PACKAGE_PIN AE18 [get_ports FMC_LPC_LA16_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA16_P] set_property PACKAGE_PIN AC27 [get_ports FMC_LPC_LA17_CC_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA17_CC_N] set_property PACKAGE_PIN AB27 [get_ports FMC_LPC_LA17_CC_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA17_CC_P] set_property PACKAGE_PIN AF27 [get_ports FMC_LPC_LA18_CC_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA18_CC_N] set_property PACKAGE_PIN AE27 [get_ports FMC_LPC_LA18_CC_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA18_CC_P] set_property PACKAGE_PIN AH27 [get_ports FMC_LPC_LA19_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA19_N] set_property PACKAGE_PIN AH26 [get_ports FMC_LPC_LA19_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA19_P] set_property PACKAGE_PIN AG27 [get_ports FMC_LPC_LA20_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA20_N] set_property PACKAGE_PIN AG26 [get_ports FMC_LPC_LA20_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA20_P] set_property PACKAGE_PIN AH29 [get_ports FMC_LPC_LA21_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA21_N] set_property PACKAGE_PIN AH28 [get_ports FMC_LPC_LA21_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA21_P] set_property PACKAGE_PIN AK28 [get_ports FMC_LPC_LA22_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA22_N] set_property PACKAGE_PIN AK27 [get_ports FMC_LPC_LA22_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA22_P] set_property PACKAGE_PIN AK26 [get_ports FMC_LPC_LA23_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA23_N] set_property PACKAGE_PIN AJ26 [get_ports FMC_LPC_LA23_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA23_P] set_property PACKAGE_PIN AG30 [get_ports FMC_LPC_LA24_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA24_N] set_property PACKAGE_PIN AF30 [get_ports FMC_LPC_LA24_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA24_P] set_property PACKAGE_PIN AG29 [get_ports FMC_LPC_LA25_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA25_N] set_property PACKAGE_PIN AF29 [get_ports FMC_LPC_LA25_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA25_P] set_property PACKAGE_PIN AK30 [get_ports FMC_LPC_LA26_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA26_N]

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set_property PACKAGE_PIN AJ30 [get_ports FMC_LPC_LA26_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA26_P] set_property PACKAGE_PIN AJ29 [get_ports FMC_LPC_LA27_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA27_N] set_property PACKAGE_PIN AJ28 [get_ports FMC_LPC_LA27_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA27_P] set_property PACKAGE_PIN AE26 [get_ports FMC_LPC_LA28_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA28_N] set_property PACKAGE_PIN AD25 [get_ports FMC_LPC_LA28_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA28_P] set_property PACKAGE_PIN AF25 [get_ports FMC_LPC_LA29_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA29_N] set_property PACKAGE_PIN AE25 [get_ports FMC_LPC_LA29_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA29_P] set_property PACKAGE_PIN AB30 [get_ports FMC_LPC_LA30_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA30_N] set_property PACKAGE_PIN AB29 [get_ports FMC_LPC_LA30_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA30_P] set_property PACKAGE_PIN AD29 [get_ports FMC_LPC_LA31_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA31_N] set_property PACKAGE_PIN AC29 [get_ports FMC_LPC_LA31_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA31_P] set_property PACKAGE_PIN Y27 [get_ports FMC_LPC_LA32_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA32_N] set_property PACKAGE_PIN Y26 [get_ports FMC_LPC_LA32_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA32_P] set_property PACKAGE_PIN AA30 [get_ports FMC_LPC_LA33_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA33_N] set_property PACKAGE_PIN Y30 [get_ports FMC_LPC_LA33_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA33_P]

#GPIO DIP SW set_property PACKAGE_PIN AB17 [get_ports GPIO_DIP_SW0] set_property IOSTANDARD LVCMOS25 [get_ports GPIO_DIP_SW0] set_property PACKAGE_PIN AC16 [get_ports GPIO_DIP_SW1] set_property IOSTANDARD LVCMOS25 [get_ports GPIO_DIP_SW1] set_property PACKAGE_PIN AC17 [get_ports GPIO_DIP_SW2] set_property IOSTANDARD LVCMOS25 [get_ports GPIO_DIP_SW2] set_property PACKAGE_PIN AJ13 [get_ports GPIO_DIP_SW3] set_property IOSTANDARD LVCMOS25 [get_ports GPIO_DIP_SW3]

#GPIO P.B. SW set_property PACKAGE_PIN K15 [get_ports GPIO_SW_CENTER] set_property IOSTANDARD LVCMOS15 [get_ports GPIO_SW_CENTER] set_property PACKAGE_PIN AK25 [get_ports GPIO_SW_LEFT] set_property IOSTANDARD LVCMOS25 [get_ports GPIO_SW_LEFT] set_property PACKAGE_PIN R27 [get_ports GPIO_SW_RIGHT] set_property IOSTANDARD LVCMOS25 [get_ports GPIO_SW_RIGHT] set_property PACKAGE_PIN A8 [get_ports PL_CPU_RESET] set_property IOSTANDARD LVCMOS15 [get_ports PL_CPU_RESET]

#GPIO LEDs set_property PACKAGE_PIN A17 [get_ports GPIO_LED_0] set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_0]

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set_property PACKAGE_PIN G2 [get_ports GPIO_LED_CENTER] set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_CENTER] set_property PACKAGE_PIN Y21 [get_ports GPIO_LED_LEFT] set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_LEFT] set_property PACKAGE_PIN W21 [get_ports GPIO_LED_RIGHT] set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_RIGHT]

#GPIO PMOD1 set_property PACKAGE_PIN AJ21 [get_ports PMOD1_0_LS] set_property IOSTANDARD LVCMOS25 [get_ports PMOD1_0_LS] set_property PACKAGE_PIN AK21 [get_ports PMOD1_1_LS] set_property IOSTANDARD LVCMOS25 [get_ports PMOD1_1_LS] set_property PACKAGE_PIN AB21 [get_ports PMOD1_2_LS] set_property IOSTANDARD LVCMOS25 [get_ports PMOD1_2_LS] set_property PACKAGE_PIN AB16 [get_ports PMOD1_3_LS] set_property IOSTANDARD LVCMOS25 [get_ports PMOD1_3_LS] set_property PACKAGE_PIN Y20 [get_ports PMOD1_4_LS] set_property IOSTANDARD LVCMOS25 [get_ports PMOD1_4_LS] set_property PACKAGE_PIN AA20 [get_ports PMOD1_5_LS] set_property IOSTANDARD LVCMOS25 [get_ports PMOD1_5_LS] set_property PACKAGE_PIN AC18 [get_ports PMOD1_6_LS] set_property IOSTANDARD LVCMOS25 [get_ports PMOD1_6_LS] set_property PACKAGE_PIN AC19 [get_ports PMOD1_7_LS] set_property IOSTANDARD LVCMOS25 [get_ports PMOD1_7_LS]

#HDMI set_property PACKAGE_PIN AC23 [get_ports HDMI_INT] set_property IOSTANDARD LVCMOS25 [get_ports HDMI_INT] set_property PACKAGE_PIN P28 [get_ports HDMI_R_CLK] set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_CLK] set_property PACKAGE_PIN U24 [get_ports HDMI_R_D4] set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D4] set_property PACKAGE_PIN T22 [get_ports HDMI_R_D5] set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D5] set_property PACKAGE_PIN R23 [get_ports HDMI_R_D6] set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D6] set_property PACKAGE_PIN AA25 [get_ports HDMI_R_D7] set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D7] set_property PACKAGE_PIN AE28 [get_ports HDMI_R_D8] set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D8] set_property PACKAGE_PIN T23 [get_ports HDMI_R_D9] set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D9] set_property PACKAGE_PIN AB25 [get_ports HDMI_R_D10] set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D10] set_property PACKAGE_PIN T27 [get_ports HDMI_R_D11] set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D11] set_property PACKAGE_PIN AD26 [get_ports HDMI_R_D16] set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D16] set_property PACKAGE_PIN AB26 [get_ports HDMI_R_D17] set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D17] set_property PACKAGE_PIN AA28 [get_ports HDMI_R_D18] set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D18] set_property PACKAGE_PIN AC26 [get_ports HDMI_R_D19] set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D19]

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Xilinx ZC706 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Revision History

Table of Contents

ZC706 Evaluation Board Features

Overview

Block Diagram

Board Layout

Feature Descriptions

Zynq-7000 XC7Z045 AP SoC

Device Configuration

Encryption Key Backup Circuit

I/O Voltage Rails

DDR3 SODIMM Memory (PL)

DDR3 Component Memory (PS)

Quad-SPI Flash Memory

USB 2.0 ULPI Transceiver

SD Card Interface

Programmable Logic JTAG Programming Options

Programmable Logic JTAG Select Switch

FMC Connector JTAG Bypass

Clock Generation

System Clock

Programmable User Clock

User SMA Clock Source

Processing System Clock Source

GTX SMA Clock (SMA_MGT_REFCLK_P and SMA_MGT_REFCLK_N)

Jitter Attenuated Clock

GTX Transceivers

PCI Express Endpoint Connectivity

SFP/SFP+ Module Connector

10/100/1000 Mb/s Tri-Speed Ethernet PHY (PL)

Ethernet PHY Clock Source

USB-to-UART Bridge

HDMI Video Output

I2C Bus

Real Time Clock (RTC)

Status and User LEDs

Ethernet PHY User LEDs

User I/O

User LEDs

User Pushbuttons

GPIO DIP Switch

User PMOD GPIO Headers

Switches

Power On/Off Slide Switch

Program_B Pushbutton

PS Power-On and System Reset Pushbuttons

FPGA Mezzanine (FMC) Card Interface

HPC Connector J37

LPC Connector J5

ZC706 Board Power System

UCD90120A Description

LMZ31500 and LMZ31700 Family Regulator Description

XADC Power System Measurement

Power Management

VADJ Voltage Control

AP SoC Programmable Logic (PL) Voltage Control

Monitoring Voltage and Current

Cooling Fan

XADC Analog-to-Digital Converter

Switches

Jumpers

ZC706 Evaluation Board XDC Listing