XILINX XQR4062XL-3CB228M, XQR4036XL-3CB228M, XQR4013XL-3CB228M Datasheet
DS071 (v1.1) June 25, 2000 www.xilinx.com 1
Product Specification 1-800-255-7778
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All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
XQR4000XL Series Features
• Radiation-hardened FPGAs for space and satellite
applications
• Guaranteed total ionizing dose
• Latch-up immune
• Low soft upset rate
• Guaranteed to meet full electrical specifications over
–55°C to +125°C
• Available in -3 speed
• Sy stem fea tur ed FPGA s
- SelectRAM™ memory: on-chip ultra-fast RAM with
· synchronous write option
· dual-port RAM option
- Abundant flip-flops
- Flexible function generators
- Dedicated high-speed carry logic
- Wide edge decoders on each edge
- Hierarchy of interconnect lines
- Internal 3-state bus capability
- Eight global low-skew clock or signal distribution
networks
• System performance beyond 60 MHz
• Flexible array architec t ur e
• Low power segmented routing architecture
• Systems-ori ent ed features
- IEEE 1149.1-compat ible boundar y scan logic
support
- Individually programmable output slew rate
- Programmable input pull-up or pull-down resistors
- 12 mA sink current per output
• Configured by loading binary file
- Unlimited reprogrammability
• Readback capability
- Program verification
- Inter nal node observability
• Development system runs on most common computer
platforms
- Interfaces to popular design environments
- Fully automatic mapping , placement and ro uting
- Interactive design editor for design optimization
• Highest capacity: over 130,000 usable gates
• Buffered interconnect for maximum speed
• New latch capability in configurable logic blocks
• Improved VersaRing™ I/O interconnect for better fixed
pinout flexibility
- Virtually unlimited number of clock signals
• Optional multiplexer or 2-input function generator on
device outputs
• 5V tolerant I/Os
• Advanced 0.35µ process
• Processed on Xi linx QML line
0
QPRO XQR4000XL Radiation
Hardened FPGAs
DS071 (v1.1) June 25, 2000
02
Produc t S pecif i catio n
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Table 1: XQR4000XL Series Radiation Hardened Field Programmable Gate Arrays
Device
Logic
Cells
Max.
Logic
Gates
(No RAM)
Max. RAM
Bits
(No Logic)
Typical
Gate Range
(Logic and
RAM)
(1)
CLB
Matrix
Total
CLBs
Number
of
Flip-Flops
Max.
User
I/O Packages
XQR4013XL 1,368 13,000 18,432 10,000 - 30,000 24 x 24 576 1,536 192 CB228
XQR4036XL 3,078 36,000 41,472 22,000 - 65,000 36 x 36 1,296 3,168 288 CB228
XQR4062XL 5,472 62,000 73,728 40,000 - 130,000 48 x 48 2,304 5,376 384 CB228
Notes:
1. Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
QPRO XQR4000XL Radiation Hardened FPGAs
2 www.xilinx.com DS071 (v1.1) June 25, 2000
1-800-255-7778 Product Specification
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Radiation Specif ica tio ns
Symbol Description Min Max Units
TID Total ionizing dose - 60K RAD(Si)
SEL Single event Latch-up LET> 100 MeV CM
2
/mg. @ +125°C- 0
SEU Single event upset galactic p+
(1)
- 2.43E – 8 Upsets/
Bit-Day
SEU Single event upset galactic heavy Ion
(1)
- 9.54E – 8 Upsets/
Bit-Day
SEU Single event upset trapped p+
(1)
- 2.50E – 7 Upsets/
Bit-Day
SEU Single event upset galactic p+
(2)
- 5.62E – 8 Upsets/
Bit-Day
SEU Single event upset galactic heavy Ion
(2)
- 2.43E – 7 Upsets/
Bit-Day
Notes:
1. 680 Km LEO, 98
o
Inclination, 100-mil Al Shielding
2. 35,000 Km GEO , 0
o
Inclination, 100-mil Al Shielding
3. Simulations done using Space Radiati on Version 2.5 code from Sev ern Communication Corp.
QPRO XQR4000XL Radiation Hardened FPGAs
DS071 (v1.1) June 25, 2000 www.xilinx.com 3
Product Specification 1-800-255-7778
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XQR4000XL Switching Characteristics
Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These term s are defined as
follows:
Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or
devicefamilies. Values are subject to change. Use as estimates, not for production.
Preliminary: Based on preliminary characterization. Further changes are not expected.
Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final.
Except for pin-to-pin input and output parameters, the AC parameter delay specifications included i n this document are
derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction
temperature conditions.
All specifications subject to change without notice.
Additio nal Specif icati ons
Except for pin-to-pin input and output parameters, the a.c.
parameter delay specifications included in this document
are derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage
and junction temperature conditions. The parameters
included are common to popular designs and typical appli-
cations. For design considerations requiring more detailed
timing information, se e the appropriate family AC supplements available on the Xilinx web site at:
http://www.xilinx.com/partinfo/databook.htm
.
Absolute Maxim u m Rati ng s
(1)
Recommended Operating Conditions
(1)
Symbol Description Units
V
CC
Supply voltage relative to GND –0.5 to 4.0 V
V
IN
Input voltage relative to GND
(2)
–0.5 to 5.5 V
V
TS
Voltage applied to High-Z output
(2)
–0.5 to 5.5 V
V
CCt
Longest supply voltage rise time from 1V to 3V 50 ms
T
STG
Storage temperature (ambient) –65 to +150 °C
T
SOL
Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260 °C
T
J
Junction temperature +150 °C
Notes:
1. Stresses be yond those listed under Absolute Maximum Rati ngs may cause permanent damage to the device. These are stress
ratings only, and functional operat ion of the device at these or any other conditions beyon d those listed under Operat ing Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
2. Maximum DC ov ershoot or undershoot above V
CC
or below GND must be limited to either 0.5V or 10 mA, whichever is easier to
achieve. During transitions, the device pins may undershoot to –2. 0 V or over shoot to V
CC
+ 2.0V, provi ded this over- or undershoot
lasts less than 10 ns and with the forcing current being limited to 200 mA.
Symbol Description Min Max Units
V
CC
Supply voltage relative to GND, TC = –55°C to +125°C3.03.6V
V
IH
High-level input voltage
(2)
50% of V
CC
5.5 V
V
IL
Low-level input vol tag e 0 30% of V
CC
V
T
IN
Input signal transition time - 250 ns
Notes:
1. At junction temperatures above those listed as Ope rating Conditions, all delay par am eters increase by 0.35% per °C.
2. Input and output measurement threshold is ~50% of V
CC
.
QPRO XQR4000XL Radiation Hardened FPGAs
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1-800-255-7778 Product Specification
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XQR4000XL DC Characteristics Over Recommended Operating Conditions
Power-On Power Supply Requirements
Xilinx FPGAs require a minimum rated power supply current
capacity to insure proper initialization, and the power supply
ramp-up time does affect the current required. A fast
ramp-up time requires more current than a slow ramp-up
time. The slowest ramp-up time is 50 ms. Current capacity
is not specified for a ramp-up time faster than 2 ms. The cur-
rent capacity varies linealy with ramp-up time, e.g., an
XQR4036XL with a ram p-up time of 25 ms would require a
capacity predicted by the po int on the straight line drawn
from 1A at 120 µs to 500 mA at 50 ms at the 25 ms time
mark. This point is approximately 750 m A
.
Symbol Description Min Max Units
V
OH
High-level output voltage at IOH = –4 mA, VCC min (LVTTL) 2.4 - V
High-level output voltage at I
OH
= –500 µA, (LVCMOS) 90% V
CC
-V
V
OL
Low-lev el output voltage at IOL = 12 mA, VCC min (LVTTL)
(1)
-0.4V
Low-lev el output voltage at I
OL
= 1500 µA, (LVCMOS) - 10% V
CC
V
V
DR
Data retention supply voltage (below which configuration data may be lost) 2.5 - V
I
CCO
Quiescent FPGA supply current
(2)
-5mA
I
L
Input or output leakage current –10 +10 µA
C
IN
Input capacitance (sample tested) - 10 pF
I
RPU
Pad pull-up (when selected) at VIN = 0V (sample tested) 0.02 0.25 mA
I
RPD
Pad pull-down (when selected) at VIN = 3.6V (sample tested) 0.02 0.15 mA
I
RLL
Horizontal longline pull-up (when selected) at logic Low 0.3 2.0 mA
Notes:
1. With up to 64 pins simultaneously sinki ng 12 mA.
2. With no output current loads, no active input or Longline pull-up resisto rs, all I/O pins in a High-Z stat e and fl oating.
Product Descriptio n
Ramp-up Time
Fast (120 µs) Slow (50 ms)
XQR4013 - 36XL Minimum required current supply 1A 500 mA
XC4062XL Minimum required current supply 2A 500 mA
Notes:
1. Devices are guaranteed to initialize properly with the minimum current listed above. A larger capacity power supply may result in a
large r initializati o n c u rrent.
2. This specification applies to Commercial and Industrial grade products only.
3. Ramp-up Time is measur ed fr om 0V
DC
to 3.6VDC. Peak current required lasts less than 3 ms, and occurs near the internal power
on reset threshold voltage. Afte r in itialization and before configur ati on, I
CC
max is less than 10 mA.
QPRO XQR4000XL Radiation Hardened FPGAs
DS071 (v1.1) June 25, 2000 www.xilinx.com 5
Product Specification 1-800-255-7778
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XQR4000 XL AC Switching Cha ra ct er ist ic
Testing of the switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuri ng i nter n al tes t patter ns. Listed below
are representative values where one global clock input
drives one vertical clock line in each accessibl e column, and
where all accessible IOB and CLB flip-flops are cl ocked by
the global clock net.
When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are
driven from the same gl obal clock, the delay is longer. For
more specific, more precise, and worst-case guaranteed
data, reflecting the actual routing struc ture, use the values
provided by the static timing analyzer (TRCE in the Xilinx
Development System) and back-annotated to the simulation
netlist. These path delays, provided as a guideline, have
been extracted from the static timing analyzer report. All
timing parameters assume worst-case operating conditions
(supply voltage and junction temperature)
Global Buffer Switching Characteristics
Global Early BUFGEs 1, 2, 5, and 6 to IOB Clock Characteristics
Global Early BUFGEs 3, 4, 7, and 8 to IOB Clock Characteristics
Symbol Description Device
-3
UnitsMin Max
T
GLS
Delay from pad through Global Low Skew buffer, to any
clo ck K
XQR4013XL 0.6 3.6 ns
XQR4036XL 1.1 4.8 ns
XQR4062XL 1.4 6.3 ns
Symbol Description Device
-3
UnitsMin Max
T
GE
Delay from pad through Global Early buffer, to any IOB
clock. Values are for BUFGEs 1, 2, 5 and 6.
XQR4013XL 0.4 2.4 ns
XQR4036XL 0.3 3.1 ns
XQR4062XL 0.3 4.9 ns
Symbol Description Device
-3
UnitsMin Max
T
GE
Delay from pad through Global Early buffer, to any IOB
clock. Values are for BUFGEs 3, 4, 7 and 8.
XQR4013XL 0.7 2.4 ns
XQR4036XL 0.9 4.7 ns
XQR4062XL 1.2 5.9 ns
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1-800-255-7778 Product Specification
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XQR4000XL CLB Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuri ng i nter n al tes t patter ns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use t he values reported
by the static timing analyzer (TRCE in the Xilinx Development System) an d back-ann otated to th e simu lation n etlist.
All timing parameters ass ume worst-case operating con ditions (supply voltage and junction temperature). Values
apply to all XQR4 000XL devices and expressed in nanoseconds unless otherwise noted.
CLB Switching Characteristics
Symbol Description
-3
UnitsMin Max
Combinatorial Delays
T
ILO
F/G inputs to X/Y outputs - 1.6 ns
T
IHO
F/G inputs via H ’ to X/Y outputs - 2.7 ns
T
ITO
F/G inputs via transparent latch to Q outputs - 2.9 ns
T
HH0O
C inputs via SR/H0 via H to X/Y outputs - 2.5 ns
T
HH1O
C inputs via H1 via H to X/Y outputs - 2.4 ns
T
HH2O
C inputs via DIN/H2 via H to X/Y outputs - 2.5 ns
T
CBYP
C inputs via EC, DIN/H2 to YQ, XQ output (bypass) - 1.5 ns
CLB Fast Carry Logic
T
OPCY
Operand inputs (F1, F2, G1, G4) to C
OUT
-2.7ns
T
ASCY
Add/subtract input (F3) to C
OUT
-3.3ns
T
INCY
Initialization inputs (F1, F3) to C
OUT
-2.0ns
T
SUM
CIN through function generators to X/Y outputs - 2.8 ns
T
BYP
C
IN
to C
OUT
, bypass function generators - 0.26 ns
T
NET
Carry net delay, C
OUT
to C
IN
-0.32ns
Sequential Delays
T
CKO
Clock K to flip-flop outputs Q - 2.1 ns
T
CKLO
Clock K to latch outputs Q - 2.1 ns
Setup Time Before Clock K
T
ICK
F/G inputs 1.1 - ns
T
IHCK
F/G in puts via H 2.2 - ns
T
HH0CK
C inputs via H0 through H 2.0 - ns
T
HH1CK
C inputs via H1 through H 1.9 - ns
T
HH2CK
C inputs via H2 through H 2.0 - ns
T
DICK
C inputs via D
IN
0.9 - ns
T
ECCK
C inputs via EC 1.0 - ns
T
RCK
C inputs via S/R, going Low (inactive) 0.6 - ns
T
CCK
CIN input via F/G 2.3 - ns
T
CHCK
CIN input via F/G and H 3.4 - ns
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