XILINX XQ4028EX-4HQ240N, XQ4028EX-4PG299M, XQ4028EX-4CB228M, XQ4028EX-4BG352N, XQ4028EX-3PG299M Datasheet
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DS021 (v2.2) June 25, 2000 www.xilinx.com 1
Product Specification 1-800-255-7778
© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Product Features
• Certified to MIL-PRF-38535, appendix A QML
(Qualified Manufacturers Listing)
• Also available under the fol lo wing Standard Microcircuit
Drawings (SMD)
- XC4005E 5962-97522
- XC4010E 5962-97523
- XC4013E 5962-97524
- XC4025E 5962-97525
- XC4028EX 5962-98509
• For more information contact the Defense Supply
Center Columbus (DSCC)
http://www.dscc.dla.mis/v/va/smd/smdsrch.html
• System featured Field-Programmable Gate Arrays
- Select-RAM
TM
memory: on-chip ultra-fast RAM with
· Synchronous write option
· Dual-port RAM option
- Abundant flip-flops
- Flexible function generators
- Dedicated high-speed carry logic
- Wide edge decoders on each edge
- Hierarchy of interconnect lines
- Internal 3-state bus capability
- Eight global low-skew clock or signal distribution
networks
• System Performance beyond 60 MHz
• Flexible Array Archit ec tur e
• Low Power Segmented Routing Architecture
• Systems-Oriented Features
- IEEE 1149.1- co mpatible boundary scan logic
support
- Individually programmable output slew rate
- Programmable input pull-up or pull-down resistors
- 12 mA sink current per XQ4000E/EX output
• Configured by Loading Binary Fi le
- Unlimited reprogrammability
• Readback Capability
- Program verification
- Inter nal node observability
• Backward Compatible with XC4000 Devices
• Development System runs on most common computer
platforms
- Interfaces to popular design environments
- Fully automatic mapping , placement and routi ng
- Interactive design editor for design optimization
• Available Speed Grades:
- XQ4000E -3 for plastic packages only
- -4 for ceramic packages only
- XQ4028EX -4 for all packages
More Information
For more information refer to Xilinx XC4000E and XC4000X
series Field Programmable Gate A rrays product specification. This data sheet contains pinout tables for XQ4010E
only. Refer to Xilinx web site for pinout tables for other
devices. (Pinouts for XQ4000E/EX are identical to
XC4000E/EX.)
(http://www.xilinx.com/partinfo/databook.htm
)
0
QPRO XQ4000E/ EX
QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000
02
Produc t S pecif i catio n
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XQ4000E Switching Characteristics
XQ4000E Absolute Maximum Ratings
(1)
Table 1: XQ4000E/ EX Field Progr ammab le Gate Array s
Device
Max.
Logic
Gates
(No RAM)
Max.
RAM Bits
(No
Logic)
Typical
Gate Range
(Logic and
RAM)
(1)
CLB
Matrix
Total
CLBs
Number
of
Flip-Flops
Max.
Decode
Inputs
per Side
Max.
User
I/O Packages
XQ4005E 5,000 6,272 3,000 - 9,000 14 x 14 196 616 42 112 PG156,
CB164
XQ4010E 10,000 12,800 7,000 - 20,000 20 x 20 400 1,120 60 160 PG191,
CB196,
HQ208
XQ4013E 13,000 18,432 10,000 - 30,000 24 x 24 576 1,536 72 192 PG223,
CB228,
HQ240
XQ4025E 25,000 32,768 15,000 - 45,000 32 x 32 1,024 2,560 96 256 PG299,
CB228
XQ4028EX 28,000 32,768 18,000 - 50,000 32 x 32 1,024 2,560 96 256 PG299,
CB228,
HQ240,
BG352
Notes:
1. Max values of Typ ical Gate Range include 20- 30% of CLBs used as RAM.
Symbol Description Units
V
CC
Supply voltage relative to GND –0.5 to +7.0 V
V
IN
Input voltage relative to GND
(2)
–0.5 to VCC + 0.5 V
V
TS
Voltage applied to High-Z output
(2)
–0.5 to VCC + 0.5 V
T
STG
Storage temperature (ambient) –65 to +150 °C
T
SOL
Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260 °C
T
J
Junction temperature Ceramic package +150 °C
Plastic package +125 °C
Notes:
1. Stresses beyond those listed under Absolu te Maximum Ratings may cause permanent damage to the device. These are str ess
ratings only, and functional operat ion of the device at these or any other conditions beyon d those listed under Operat ing Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
2. Maximum DC excursion a bov e V
CC
or below Ground must be limited t o ei ther 0.5V or 10 mA, whi chever is easier to achieve . During
transitions, the device pins may undershoot to –2.0V or overshoot to V
CC
+ 2.0V, provided this over or undershoot lasts less than
10 ns and with the forcing current being limited to 200 mA.
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Product Specification 1-800-255-7778
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XQ4000E Recommended Operating Conditions
(1,2)
XQ4000E DC Characteristics Over Recommended Operating Conditions
Symbol Description Min Max Units
V
CC
Supply voltage relative to GND, TJ = –55°C to +125°CPlastic 4.5 5.5 V
Supply voltage relative to GND, T
C
= –55°C to +125°C Ceramic 4.5 5.5 V
V
IH
High-Level Input Voltage TTL inputs 2.0 V
CC
V
CMOS inputs 70% 100% V
CC
V
IL
Low-Level Input Voltage TTL inputs 0 0.8 V
CMOS inputs 0 20% V
CC
T
IN
Input signal transition time - 250 ns
Notes:
1. At junction temperatures above those l isted as Operating Condi tions, all delay parameter s increase by 0.35% per °C.
2. Input and output measurement thr eshold are 1.5V for TTL and 2.5V for CMOS.
Symbol Description Min Max Units
V
OH
High-level output voltage @ IOH = –4.0 mA, VCC min TTL outputs 2.4 - V
High-level output voltage @ I
OH
= –1.0 mA, VCC min CMOS outputs VCC – 0.5 - V
V
OL
Low-lev el output voltage @ IOL = 12.0 mA, VCC min
(1)
TTL outputs - 0.4 V
CMOS outputs - 0.4 V
I
CCO
Quiescent FPGA supply current
(2)
-50mA
I
L
Input or output leakage current –10 +10 µA
C
IN
Input capacitance (sample tested) - 16 pF
I
RIN
Pad pull-up (when selected) at VIN = 0V (sample tested)
(3)
–0.02 –0.25 mA
I
RLL
Horizontal longline pull-up (when selected) at logic Low
(3)
0.2 2.5 mA
Notes:
1. With 50% of the outputs simultaneously sinking 12 mA, up to a maximum of 64 pins.
2. With no output cu rrent loads , no a ctiv e input or Longli ne pul l-up resist ors , a ll pa c kage pi ns a t V
CC
or GND, and the FPGA configured
with the dev elopment system Tie opti on.
3. Characterized Only.
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XQ4000E Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuri ng i nter n al tes t patter ns. Listed below
are representative values where one global clock input
drives one vertical clock line in each accessibl e column, and
where all accessible IOB and CLB flip-flops are cl ocked by
the global clock net.
When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are
driven from the same global c lock, the delay is longer. For
more specific, more precise, and worst-case guaranteed
data, reflecting the actual routing struc ture, use the values
provided by the static timing analyzer (TRCE in the Xilinx
Development System) and back-annotated to the simulation
netlist. These path delays, provided as a guideline, have
been extracted from the static timing analyzer report. All
timing parameters assume worst-case operating conditions
(supply voltage and junction temperature).
Note: -3 Speed Grade only applies to XQ4010E and
XQ4013E Plastic Package options only. -4 Speed Grade
applies to all XQ devices and is only available in
Ceramic Packages only.
XQ4000E Global Buffer Switching Characteristics
Symbol Description Device
-3
(1)
-4
(2)
UnitsMax Max
T
PG
From pad through primary buffer, to any clock K XQ4005E - 7.0 ns
XQ4010E 6.3 11.0 ns
XQ4013E 6.8 11.5 ns
XQ4025E - 12.5 ns
T
SG
From pad through secondary buffer, to any clock K XQ4005E - 7.5 ns
XQ4010E 6.8 11.5 ns
XQ4013E 7.3 12.0 ns
XQ4025E - 13.0 ns
Notes:
1. For plastic package options only.
2. For ceramic package options only.
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Product Specification 1-800-255-7778
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XQ4000E Horizontal Longline Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuri ng i nter n al tes t patter ns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use t he values reported
by the static timing analyzer (TRCE i n the X ilinx Development System) and back-annotated t o t he simulation net list.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (supply voltage and junction tempe rature). Values apply to all
XQ4000E devices unless otherwise noted.
The following guidelines reflect worst-case values over the
recommended operating conditions.
Symbol Description Device
-3 -4
UnitsMax Max
TBUF Driving a Horizontal Longline (LL) :
T
IO1
I going High or Low to LL going High or Low, while T is Low.
Buffer is constantly active.
(1)
XQ4005E - 5.0 ns
XQ4010E 6.4 8.0 ns
XQ4013E 7.2 9.0 ns
XQ4025E - 11.0 ns
T
IO2
I going Low to LL going from resistive pull-up High to active Low.
TBUF configured as open-drain.
(1)
XQ4005E - 6.0 ns
XQ4010E 6.9 10.5 ns
XQ4013E 7.7 11.0 ns
XQ4025E - 12.0 ns
T
ON
T going Low to LL going from resistive pull-up or floating High to
active Low. TBUF configured as open-drain or active buffer with
I=Low.
(1)
XQ4005E - 7.0 ns
XQ4010E 7.3 8.5 ns
XQ4013E 7.5 8.7 ns
XQ4025E - 11.0 ns
T
OFF
T going High to TBUF going inactive, not driving LL. XQ4005E - 1.8 ns
XQ4010E 1.5 1.8 ns
XQ4013E 1.5 1.8 ns
XQ4025E - 1.8 ns
T
PUS
T going High to LL going from Low to High, pulled up by a single
resistor.
(1)
XQ4005E - 23.0 ns
XQ4010E 22.0 29.0 ns
XQ4013E 26.0 32.0 ns
XQ4025E - 42.0 ns
T
PUF
T going High to LL going from Low to High, pulled up by two
resistors.
(1)
XQ4005E - 10.0 ns
XQ4010E 11.0 13.5 ns
XQ4013E 13.0 15.0 ns
XQ4025E - 18.0 ns
Notes:
1. These values include a minimum load. Use the static timing analyzer t o determine the delay for each destinat ion.
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XQ4000E Wide Decoder Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuri ng i nter n al tes t patter ns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use t he values reported
by the static timing analyzer (TRCE i n the X ilinx Development System) and back-annotated t o t he simulation net list.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (supply voltage and junction tempe rature). Values apply to all
XQ4000E devices unless otherwise noted.
The following guidelines reflect worst-case values over the
recommended operating conditions.
Symbol Description
(1,2)
Device
-3 -4
UnitsMax Max
T
WAF
Full length, both pull-ups, inputs from IOB I-pins XQ4005E - 9. 5 ns
XQ4010E 9.0 15.0 ns
XQ4013E 11.0 16.0 ns
XQ4025E - 18.0 ns
T
WAFL
Full length, both pull-ups, inputs from internal logic XQ4005E - 12.5 ns
XQ4010E 11.0 18.0 ns
XQ4013E 13.0 19.0 ns
XQ4025E - 21.0 ns
T
WAO
Half length, one pull-up, inputs from IOB I-pins XQ4005E - 10.5 ns
XQ4010E 10.0 16.0 ns
XQ4013E 12.0 17.0 ns
XQ4025E - 19.0 ns
T
WAOL
Half length, one pull-up, inputs from internal logic XQ4005E - 12.5 ns
XQ4010E 12.0 18.0 ns
XQ4013E 14.0 19.0 ns
XQ4025E - 21.0 ns
Notes:
1. These delays are specified from the decoder input to the decoder output.
2. Fewer than t he specified numbe r of pull-up resistors can be used, if desi red. Using fewer pull-ups reduces powe r consumption but
increases delays. Use the static timing analyzer to determine delays if fewer pull-ups are used.
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Product Specification 1-800-255-7778
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XQ4000E CLB Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuri ng i nter n al tes t patter ns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use t he values reported
by the static ti ming analyzer (TR CE in the Xilinx Development System) and back-annotated to the simulation netlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (supply voltage and junction tempe rature). Values apply to all
XQ4000E devices unless otherwise noted.
Symbol Description
-3 -4
UnitsMin Max Min Max
Combinatorial Delays
T
ILO
F/G inputs to X/Y outputs - 2. 01 - 2.7 ns
T
IHO
F/G inputs via H to X/Y outputs - 4.3 - 4.7 ns
T
HH0O
C inputs via SR through H to X/Y outputs - 3.3 - 4.1 ns
T
HH1O
C inputs via H to X/Y outputs - 3.6 - 3.7 ns
T
HH2O
C inputs via DIN through H to X/Y outputs - 3.6 - 4.5 ns
CLB Fast Carry Logic
T
OPCY
Operand inputs (F1, F2, G1, G4) to C
OUT
-2.6-3.2ns
T
ASCY
Add/Subtract input (F3) to C
OUT
-4.4-5.5ns
T
INCY
Initialization inputs (F1, F3) to C
OUT
-1.7-1.7ns
T
SUM
CIN through function generators to X/Y outputs - 3.3 - 3.8 ns
T
BYP
C
IN
to C
OUT
, bypass function generators - 0.7 - 1.0 ns
Sequential Delays
T
CKO
Clock K to outputs Q - 2.8 - 3.7 ns
Setup Time before Clock K
T
ICK
F/G inputs 3.0 - 4. 0 - ns
T
IHCK
F/G in puts via H 4.6 - 6.1 - ns
T
HH0CK
C inputs via H0 through H 3.6 - 4.5 - ns
T
HH1CK
C inputs via H1 through H 4.1 - 5.0 - ns
T
HH2CK
C inputs via H2 through H 3.8 - 4.8 - ns
T
DICK
C inputs via D
IN
2.4 - 3. 0 - ns
T
ECCK
C inputs via EC 3.0 - 4.0 - ns
T
RCK
C inputs via S/R, going Low (inactive) 4.0 - 4.2 - ns
T
CCK
CIN input via F/G 2.1 - 2. 5 - ns
T
CHCK
CIN input via F/G and H 3.5 - 4. 2 - ns
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XQ4000E CLB Switching Characteristic Guidelines (continued)
Symbol
Description
-3 -4
UnitsMin Max Min Max
Hold Time after Clock K
T
CKI
F/G inputs 0 - 0 - n s
T
CKIH
F/G inputs via H 0 - 0 - n s
T
CKHH0
C inputs via H0 through H 0 - 0 - ns
T
CKHH1
C inputs via H1 through H 0 - 0 - ns
T
CKHH2
C inputs via H2 through H 0 - 0 - ns
T
CKDI
C inputs via DIN/H2 0 - 0 - ns
T
CKEC
C inputs via EC 0 - 0 - ns
T
CKR
C inputs via SR, going Low (inactive) 0 - 0 - ns
Clock
T
CH
Clock High time 4.0 - 4.5 - ns
T
CL
Clock Low time 4.0 - 4.5 - ns
Set/Reset Direct
T
RPW
Width (High) 4.0 - 5.5 - ns
T
RIO
Delay from C inputs via S/R, going High to Q - 4.0 - 6.5 ns
Master Set/Reset
(1)
T
MRW
Width (High or Low) 11. 5 - 13.0 - ns
T
MRQ
Delay from Global Set/Reset net to Q - 18.7 - 23.0 ns
T
MRK
Global Set/Reset inactive to first active clock K edge - 18.7 - 23.0 ns
F
TOG
Toggle Frequency
(2)
- 125 - 111 MHz
Notes:
1. Timing is based on the XC4005E. For other devices see the static timing analyzer.
2. Export Control Max. flip-flop toggle rate.
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Product Specification 1-800-255-7778
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XQ4000E CLB Edge-Triggered (Synchro nous) RAM Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuri ng i nter n al tes t patter ns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use t he values reported
by the static timing analyzer (TRCE in the Xilinx Development System) an d back-ann otated to th e simu lation n etlist.
All timing parameters ass ume worst-case operating con ditions (supply voltage and junction temperature). Values
apply to all XQ4000E/EX devices unless otherwise noted.
Single-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
Symbol Write Operation Description Size
-3 -4
UnitsMin Max Min Max
T
WCS
Address write cycle time (clock K period) 16x2 14.4 - 15.0 - ns
T
WCTS
32x1 14.4 - 15.0 - ns
T
WPS
Clock K pulse width (active edge) 16x2 7.2 1 ms 7.5 1 ms ns
T
WPTS
32x1 7.2 1 ms 7 .5 1 ms ns
T
ASS
Address setup time before clock K 16x2 2.4 - 2.8 - ns
T
ASTS
32x1 2. 4 - 2.8 - ns
T
AHS
Address hold time after clock K 16x2 0 - 0 - ns
T
AHTS
32x1 0 - 0 - ns
T
DSS
DIN setup time before clock K 16x2 3.2 - 3.5 - ns
T
DSTS
32x1 1. 9 - 2.5 - ns
T
DHS
D
IN
hold time after clock K 16x 2 0 - 0 - ns
T
DHTS
32x1 0 - 0 - ns
T
WSS
WE setup time before clock K 16x2 2.0 - 2 .2 - ns
T
WSTS
32x1 2. 0 - 2.2 - ns
T
WHS
WE hold time after clock K 16x2 0 - 0 - ns
T
WHTS
32x1 0 - 0 - ns
T
WOS
Data valid after clock K 16x2 8.8 - - 10.3 ns
T
WOTS
32x1 10.3 - - 11.6 ns
Notes:
1. Timing for the 16x1 RAM option is identical to 16x2 RAM timing.
2. Applicable Read timing specifications are ide ntical to Level-Sensitive Read timing.
Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
Symbol Write Operation Description Size
(1)
-3 -4
UnitsMin Max Min Max
T
WCDS
Address write cycle time (clock K period) 16x1 14.4 15.0 ns
T
WPDS
Clock K pulse width (active edge) 16x1 7.2 1 ms 7.5 1 ms ns
T
ASDS
Address setup time before clock K 16x1 2.5 - 2.8 - ns
T
AHDS
Address hold time after clock K 16x1 0 - 0 - ns
T
DSDS
DIN setup time before clock K 16x1 2. 5 - 2.2 - ns
T
DHDS
DIN hold time after clock K 16x1 0 - 0 - ns
T
WSDS
WE setup time before clock K 16x1 1.8 - 2.2 - ns
T
WHDS
WE hold time after clock K 16x1 0 - 0.3 - ns
T
WODS
Data valid after clock K 16x1 - 7.8 - 10.0 ns
Notes:
1. Applicable Read timing specifications are ide ntical to Level-Sensitive Read timing.
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XQ4000E CLB RAM Synchronous (Edge-Triggered) Write Timing Waveform
XQ4000E CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing Waveform
DS021_01_060100
WCLK (K)
WE
ADDRESS
DATA IN
DATA OUT
OLD NEW
T
DSS
T
DHS
T
ASS
T
AHS
T
WSS
T
WPS
T
WHS
T
WOS
T
ILO
T
ILO
DS021_02_060100
WCLK (K)
WE
ADDRESS
DATA IN
DATA OUT
OLD NEW
T
DSDS
T
DHDS
T
ASDS
T
AHDS
T
WSS
T
WPDS
T
WHS
T
WODS
T
ILO
T
ILO
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Product Specification 1-800-255-7778
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XQ4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuri ng i nter n al tes t patter ns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use t he values reported
by the static timing analyzer (TRCE in the Xilinx Development System) an d back-ann otated to th e simu lation n etlist.
All timing parameters ass ume worst-case operating con ditions (supply voltage and junction temperature). Values
apply to all XQ4000E devices unless otherwise noted.
Symbol Single Port RAM Size
-3 -4
UnitsMin Max Min Max
Write Operation
T
WC
Address write cycle time 16x2 8.0 - 8 .0 - ns
T
WCT
32x1 8. 0 - 8.0 - ns
T
WP
Write Enable pulse width (High) 16x2 4.0 - 4.0 - ns
T
WPT
32x1 4. 0 - 4.0 - ns
T
AS
Address setup time before WE 16x2 2.0 - 2.0 - ns
T
AST
32x1 2. 0 - 2.0 - ns
T
AH
Address hold time after end of WE 16x2 2.0 - 2.5 - ns
T
AHT
32x1 2. 0 - 2.0 - ns
T
DS
DIN setup time before end of WE 16x2 2.2 - 4 .0 - ns
T
DST
32x1 2. 2 - 5.0 - ns
T
DH
DIN hold time after end of WE 16x2 2.0 - 2.0 - ns
T
DHT
32x1 2. 0 - 2.0 - ns
Read Operation
T
RC
Address read cycle time 16x2 3.1 - 4.5 - ns
T
RCT
32x1 5. 5 - 6.5 - ns
T
ILO
Data valid after address change (no Write Enable) 16x2 - 1.8 - 2.7 ns
T
IHO
32x1 - 3.2 - 4.7 ns
Read Operation, Clocking Data into Flip-Flop
T
ICK
Address setup time before clock K 16x2 3.0 - 4.0 - ns
T
IHCK
32x1 4. 6 - 6.1 - ns
Read During Write
T
WO
Data valid after WE goes active (DIN stable before WE) 16x2 - 6.0 - 10.0 ns
T
WOT
32x1 - 7.3 - 12.0 ns
T
DO
Data valid after DIN (DIN changes during WE) 16x2 - 6.6 - 9.0 ns
T
DOT
32x1 - 7.6 - 11.0 ns
Read During Write, Clocking Data into Flip-Flop
T
WCK
WE setup time before clock K 16x2 6.0 - 8 .0 - ns
T
WCKT
32x1 6. 8 - 9.6 - ns
T
DCK
Data setup time before clock K 16x2 5.2 - 7.0 - ns
T
DOCK
32x1 6. 2 - 8.0 - ns
Notes:
1. Timing for the 16x1 RAM option is identical to 16x2 RAM timing.
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