XILINX XCV600E-8HQ240I, XCV600E-8HQ240C, XCV600E-8FG900I, XCV600E-8FG900C, XCV600E-8FG680I Datasheet
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DS022-1 (v2.2) November 9, 2001 www.xilinx.com Module 1 of 4
Preliminary Product Specification 1-800-255-7778 1
Features
• Fast, High-Density 1.8 V FPGA Family
- Densities from 58 k to 4 M system gates
- 130 MHz internal performance (four LUT levels)
- Designed for low-power operation
- PCI compliant 3.3 V, 32/64-bit, 33/ 66-MHz
• Highly Flexible SelectI/O+™ Technology
- Supports 20 high-performance interface standards
- Up to 804 singled-ended I/Os or 344 differential I/O
pairs for an aggregate bandwidth of > 100 Gb/s
• Differential Signalling Support
- LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL
- Differential I/O signals can be input, output, or I/O
- Compatible with standard differential devices
- LVPECL and LVDS clock inputs for 300+ MHz
clocks
• Proprietary High-Performance SelectLink™
Technology
- Double Data Rate (DDR) to Virtex-E link
- Web-based HDL generation methodology
• Sophisticated SelectRAM+™ Memory Hierarchy
- 1 Mb of internal configurable distributed RAM
- Up to 832 Kb of synchronous internal block RAM
- True Dual-Port™ BlockRAM capability
- Memory bandwidth up to 1.66 Tb/s (equivalent
bandwidth of over 100 RAMBUS channels)
- Designed for high-performance Interfaces to
External Memories
- 200 MHz ZBT* SRAMs
- 200 Mb/s DDR SDRAMs
- Supported by free Synthesizable reference design
• High-Performance Built-In Clock Management Circuitry
- Eight fully digital Delay-Locked Loops (DLLs)
- Digitally-Synthesized 50% duty cycle for Double
Data Rate (DDR) Applications
- Clock Multiply and Divide
- Zero-delay conversion of high-speed LVPECL/LVDS
clocks to any I/O standard
• Flexible Architecture Balances Speed and Density
- Dedicated carry logic for high-speed arithmetic
- Dedicated multiplier support
- Cascade chain for wide-input function
- Abundant registers/latches with clock enable, and
dual synchronous/asynchronous set and reset
- Internal 3-state bussing
- IEEE 1149.1 boundary-scan logic
- Die-temperature sensor diode
• Supported by Xilinx Foundation™ and Alliance Series™
Development Systems
- Further compile time reduction of 50%
- Internet Team Design (ITD) tool ideal for
million-plus gate density designs
- Wide selection of PC and workstation platforms
• SRAM-Based In-System Configuration
- Unlimited re-programmability
• Advanced Packaging Options
- 0.8 mm Chip-scale
- 1.0 mm BGA
-1.27mm BGA
-HQ/PQ
•0.18
m
m 6-Layer Metal Process
• 100% Factory Tested
* ZBT is a trademark of Integrated Device Technology, Inc.
0
Virtex™-E 1.8 V
Field Programmable Gate Arrays
DS022-1 (v2.2) November 9, 2001
00
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
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Module 1 of 4 www.xilinx.com DS022-1 (v2.2) November 9, 2001
2 1-800-255-7778 Preliminary Product Specification
Virtex-E Compared to Virtex Devices
The Virtex-E family offers up to 43,200 logic cells in devices
up to 30% faster than the Virtex family.
I/O performance is increased to 622 Mb/s using Source
Synchronous data transmission architectures and synchronous system performance up to 240 MHz using singled-ended SelectI/O technology. Additional I/O standards
are supported, notably LVPECL, LVDS, and BLVDS, which
use two pins per signal. Almost all signal pins can be used
for these new standards.
Virtex-E devices have up to 640 Kb of faster (250 MHz)
block SelectRAM, but the individual RAMs are the same
size and structure as in the Virtex family. They also have
eight DLLs instead of the four in Virtex devices. Each individual DLL is slightly improved with easier clock mirroring
and 4x frequency multiplication.
V
CCINT
, the supply voltage for the internal logic and memory, is 1.8 V, instead of 2.5 V for Virtex devices. Advanced
processing and 0.18
m
m design rules have resulted in
smaller dice, faster speed, and lower power consumption.
I/O pins are 3 V tolerant, and can be 5 V tolerant with an
external 100
W
resistor. PCI 5 V is not supported. With the
addition of appropriate external resistors, any pin can tolerate any voltage desired.
Banking rules are different. With Virtex devices, all input
buffers are powered by V
CCINT
. With Virtex-E devices, the
LVTTL, LVCMOS2, and PCI input buffers are powered by
the I/O supply voltage V
CCO
.
The Virtex-E family is not bitstream-compatible with the Virtex family, but Virtex designs can be compiled into equivalent Virtex-E devices.
The same device in the same package for the Virtex-E and
Virtex families are pin-compatible with some minor exceptions. See the data sheet pinout section for details.
General Description
The Virtex-E FPGA family delivers high-performance,
high-capacity programmable logic solutions. Dramatic
increases in silicon efficiency result from optimizing the new
architecture for place-and-route efficiency and exploiting an
aggressive 6-layer metal 0.18
m
m CMOS process. These
advances make Virtex-E FPGAs powerful and flexible alternatives to mask-programmed gate arrays. The Virtex-E family includes the nine members in Ta b le 1 .
Building on experience gained from Virtex FPGAs, the
Virtex-E family is an evolutionary step forward in programmable logic design. Combining a wide variety of programmable system features, a rich hierarchy of fast, flexible
interconnect resources, and advanced process technology,
the Virtex-E family delivers a high-speed and high-capacity
programmable logic solution that enhances design flexibility
while reducing time-to-market.
Virtex-E Architecture
Virtex-E devices feature a flexible, regular architecture that
comprises an array of configurable logic blocks (CLBs) surrounded by programmable input/output blocks (IOBs), all
interconnected by a rich hierarchy of fast, versatile routing
Table 1: Virtex-E Field-Programmable Gate Array Family Members
Device
System
Gates
Logic
Gates
CLB
Array
Logic
Cells
Differential
I/O Pairs
User
I/O
BlockRAM
Bits
Distributed
RAM Bits
XCV50E 71,693 20,736 16 x 24 1,728 83 176 65,536 24,576
XCV100E 128,236 32,400 20 x 30 2,700 83 196 81,920 38,400
XCV200E 306,393 63,504 28 x 42 5,292 119 284 114,688 75,264
XCV300E 411,955 82,944 32 x 48 6,912 137 316 131,072 98,304
XCV400E 569,952 129,600 40 x 60 10,800 183 404 163,840 153,600
XCV600E 985,882 186,624 48 x 72 15,552 247 512 294,912 221,184
XCV1000E 1,569,178 331,776 64 x 96 27,648 281 660 393,216 393,216
XCV1600E 2,188,742 419,904 72 x 108 34,992 344 724 589,824 497,664
XCV2000E 2,541,952 518,400 80 x 120 43,200 344 804 655,360 614,400
XCV2600E 3,263,755 685,584 92 x 138 57,132 344 804 753,664 812,544
XCV3200E 4,074,387 876,096 104 x 156 73,008 344 804 851,968 1,038,336
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