XILINX XCR3384XL-10FG324I, XCR3384XL-10FG324C, XCR3384XL-12FT256I, XCR3384XL-12FT256C, XCR3384XL-12FG324I Datasheet
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DS024 (v1.4) January 8, 2002 www.xilinx.com 1
Advance Product Specification 1-800-255-7778
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
• Lowest power 384 macrocell CPLD
• 7.5 ns pin-to-pin logic delays
• System frequencies up to 127 MHz
• 384 macrocells with 9,000 usable gates
• Available in small footprint packages
- 144-pin TQFP (118 user I/O)
- 208-pin PQFP (172 user I/O)
- 256-ball FBGA (212 user I/O)
- 324-ball FBGA (220 user I/O)
• Optimized for 3.3V systems
- Ultra low power operation
- 5V tolerant I/O pins with 3.3V core supply
- Advanced 0.35 micron five layer metal EEPROM
process
- Fast Zero Power™ (FZP) CMOS design
technology
• Advanced syste m features
- In-system programming
- Input registers
- Predictable timing model
- Up to 23 clocks available per function block
- Excellent pin retention during design changes
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Four global clocks
- Eight product term control term s per function block
• Fast ISP programming times
• Port Enable pin for additional I/O
• 2.7V to 3.6V supply voltage at industrial grade voltage
range
• Programmable slew rate control per output
• Security bit prevents unauthorized access
• Refer to XPLA3 family data sheet (DS012
) for
architecture description
Description
The XCR3384XL is a 3.3V, 384 macrocell CPLD targeted at
power sensitive designs that require leading edge programmable logic solutions. A total of 24 function blocks provide
9,000 usable gates. Pin-to-pin propagation delays are
7.5 ns with a maximum system frequency of 127 MHz.
TotalCMOS Design Technique for Fast
Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technology and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate implementation allows Xilinx to offer CPLDs that are both high
performance and low power, breaking the paradigm that to
have low power, you must have low performance. Refer to
Figure 1 and Table 1 showing t he I
CC
vs. Frequency of our
XCR3384XL TotalCMOS CPLD (data taken with 24
resetable up/down, 16-bit counters at 3.3V, 25°C).
0
XCR3384XL: 384 Macrocell CPLD
DS024 (v1.4) January 8, 2002
014
Advance Product Specification
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Figure 1: XCR3384XL Typical ICC vs. Frequency at
V
CC
= 3.3V, 25°C
0
20
40
60
80
100
120
140
0 20 40 60 80 100 120 140 160
DS024_01_112700
Frequency (MHz)
Typical ICC (mA)
Table 1: Typical ICC vs. Frequency at VCC = 3.3V, 25°C
Frequency (MHz) 0 1 10 20 40 60 80 100 120 140
Typical I
CC
(mA) TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
XCR3384XL: 384 Macrocell CPLD
2 www.xilinx.com DS024 (v1.4) Janu ary 8, 2002
1-800-255-7778 Advance Product Specification
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DC Electrical Char acteristics Over Reco mmended Operating Conditions
(1)
Symbol Parameter Test Conditions Min. Max. Unit
V
OH
(2)
Output High voltage VCC = 3.0V to 3.6V, IOH = –8 mA 2.4 - V
V
CC
= 2.7V to 3.0V, IOH = –8 mA 2.0
(3)
-V
I
OH
= –500 µA 90% V
CC
-V
V
OL
Output Low voltage IOL = 8 mA - 0.4 V
I
IL
Input leakage current VIN = GND or V
CC
–10 10 µA
I
IH
I/O High-Z leakage current VIN = GND or V
CC
–10 10 µA
I
CCSB
Standby current VCC = 3.6V - 100 µA
I
CC
Dynamic current
(4,5)
f = 1 MHz - TBD mA
f = 50 MHz - TBD mA
C
IN
Input pin capacitance
(6)
f = 1 MHz - 8 pF
C
CLK
Clock input capacitance
(6)
f = 1 MHz 5 12 pF
C
I/O
I/O pin capacitance
(6)
f = 1 MHz - 10 pF
Notes:
1. See XPLA3 family data sheet (
DS012) for recommended operating conditions
2. See Figure 2 for output drive characteristics of the XPLA3 family.
3. This parameter guaranteed by design and characterizati on, not by testing.
4. See T able 1, Figure 1 for typical values.
5. Thi s parameter measu red with a 16-bit, re setabl e up/down counter loaded into e very function b lock, wi th all outputs di sabled and
unloaded. Inputs are tied to V
CC
or ground. This parameter guaranteed by design and characterization, not testing.
6. Typical values, not tested.
Figure 2: Typical I/V Curve for the XPLA3 Family
0
0
1
0
2
0
30
4
0
50
60
7
0
80
90
1
00
0.51.52.5.54.5
Volt
s
L
3.3V
)
H
3.3V
)
H
2.7V
)
A
DS012_10_04190
1
XCR3384XL: 384 Macrocell CPLD
DS024 (v1.4) January 8, 2002 www.xilinx.com 3
Advance Product Specification 1-800-255-7778
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AC Electrical Characteristics Over Recommended Operating Conditions
(1,2)
Symbol Parameter
-7 -10 -12
Unit Min. Max. Min. Max. Min. Max.
T
PD1
Propagation delay time (single p-term) - 7.0 - 9.0 - 10.8 ns
T
PD2
Propagation delay time (OR array)
(3)
- 7.5 - 10.0 - 12.0 ns
T
CO
Clock to output (global synchronous pin clock) - 4.5 - 5.8 - 6.9 ns
T
SUF
Setup time(fast input register) 2.5 - 3.0 - 3.0 - ns
T
SU1
(4)
Setup time (single p-term) 4.3 - 5.5 - 6.7 - ns
T
SU2
Setup time (OR array) 4.8 - 6.5 - 7.9 - ns
T
H
(4)
Hold time 0-0-0-ns
T
WLH
(4)
Global Clock pulse width (High or Low) 3.0 - 4.0 - 5.0 - ns
Tt
PLH
(4)
P-term clock pulse width 4.5 - 6.0 - 7.5 - ns
T
R
(4)
Inpu t r ise ti me - 20 - 20 - 20 ns
T
L
(4)
Input fall time - 20 - 20 - 20 ns
f
SYSTEM
(4)
Maximum system frequency - 127 - 102 - 83 MHz
T
CONFIG
(4)
Configuration time
(5)
- 120 - 120 - 120 µs
T
INIT
(4)
ISP initialization time - 120 - 120 - 120 µs
T
POE
(4)
P-term OE to output enabled - 9.0 - 11.0 - 13.0 ns
T
POD
(4)
P-term OE to output disabled
(6)
- 9.0 - 11.0 - 13.0 ns
T
PCO
(4)
P-term clock to output - 8.0 - 10. 3 - 12.4 ns
T
PAO
(4)
P-term set/reset to output valid - 9.0 - 11.0 - 13.0 ns
Notes:
1. Specifications mea sured with one output sw it ching.
2. See XPLA3 family data sheet (
DS012) for recommended operating conditions.
3. See Figure 4 for derating.
4. These parameters gua ranteed by design and/or characteriz ati on, not testing.
5. Typical current draw during configuration is 10 mA at 3.6V.
6. O utput C
L
= 5 pF.
XCR3384XL: 384 Macrocell CPLD
4 www.xilinx.com DS024 (v1.4) Janu ary 8, 2002
1-800-255-7778 Advance Product Specification
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Internal Timing Parameters
(1,2)
Symbol Parameter
-7 -10 -12
UnitMin. Max. Min. Max. Min. Max.
Buffer Delays
T
IN
Input buffer delay - 2.5 - 3.3 - 4.0 ns
T
FIN
Fast input buffer delay - 2.7 - 3.3 - 3.3 ns
T
GCK
Global clock buffer delay - 1.0 - 1.3 - 1 .5 ns
T
OUT
Output buffer delay - 2.5 - 3.3 - 3.8 ns
T
EN
Output buffer enable/disable delay - 4.5 - 5.2 - 6 .0 ns
Internal Register and Combinatorial Delays
T
LDI
Latch transparent delay - 1.3 - 1.6 - 2.0 ns
T
SUI
Register setup time 0.8 - 1.0 - 1.2 - ns
T
HI
Register hold time 0.3 - 0.5 - 0.7 - ns
T
ECSU
Register clock enable setup time 2.0 - 2.5 - 3.0 - ns
T
ECHO
Register clock enable hold time 3.0 - 4.5 - 5.5 - ns
T
COI
Register clock to output delay - 1.0 - 1.3 - 1.6 ns
T
AOI
Register async. S/R to output delay - 2.0 - 2.0 - 2.2 ns
T
RAI
Register async. recovery - 5.0 - 7.0 - 8.0 ns
T
LOGI1
Internal logic delay (single p-term) - 2. 0 - 2.5 - 3.0 ns
T
LOGI2
Internal logic delay (PLA OR term) - 2. 5 - 3.5 - 4.2 ns
Feedback Delays
T
F
ZIA delay - 3.6 - 4.0 - 5.0 ns
Time Adders
T
LOGI3
Fold-back NAND delay - 2.0 - 2.5 - 3.0 ns
T
UDA
Universal delay - 2.2 - 2.8 - 3.5 ns
T
SLEW
Slew rate limited delay - 4.0 - 5.0 - 6.0 ns
Notes:
1. These parameters gua ranteed by design and/or characteriz ati on, not testing.
2. See XPLA3 family data sheet (
DS012) for timing model .
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