XILINX XCR3256XL-7TQ144C, XCR3256XL-7PQ208C, XCR3256XL-7FT256C, XCR3256XL-7CS280C, XCR3256XL-12TQ144I Datasheet

DS013 (v1.9) January 8, 2002 www.xilinx.com 1
Preliminary Product Specification 1-800-255-7778

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All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

Features

• Lowest power 256 macrocell CPLD

• 7.5 ns pin-to-pin logic delays

• System frequencies up to 140 MHz

• 256 macrocells with 6,000 usable gates

• Available in small footprint packages

- 144-pin TQFP (120 user I/O pins)

- 208-pin PQFP (164 user I/O)

- 256-ball FBGA (164 user I/O)

- 280-ball CS BGA (164 user I/O)

• Optimized for 3.3V systems

- Ultra low power operation

- 5V tolerant I/O pins with 3.3V core supply

- Advanced 0.35 micron five layer metal EEPROM
process

- Fast Zero Power™ (FZP) CMOS design
technology

• Advanced syste m features

- In-system programming

- Input registers

- Predictable timing model

- Up to 23 clocks available per function block

- Excellent pin retention during design changes

- Full IEEE Standard 1149.1 boundary-scan (JTAG)

- Four global clocks

- Eight product term control term s per function block

• Fast ISP programming times

• Port Enable pin for additional I/O

• 2.7V to 3.6V supply voltage at industrial grade voltage
range

• Programmable slew rate control per output

• Security bit prevents unauthorized access

• Refer to XPLA3 family data sheet (DS012

) for

architecture description

Description

The XCR3256XL is a 3.3V, 256 macrocell CPLD targeted at
power sensitive designs that require leading edge program­mable logic solutions. A total of 16 function blocks provide
6,000 usable gates. Pin-to-pin propagation delays are

7.5 ns with a maximum system frequency of 140 MHz.

TotalCMOS Design Technique for Fast
Zero Power

Xilinx offers a TotalCMOS CPLD, both in process technol­ogy and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate imple­mentation allows Xilinx to offer CPLDs that are both high
performance and low power, breaking the paradigm that to
have low power, you must have low performance. Refer to

Figure 1 and Table 1 showing the I

CC

vs. Frequency of our
XCR3256XL TotalCMOS CPLD (data taken with 16
resetable up/down, 16-bit counters at 3.3V, 25°C).

0

XCR3256XL 256 Macrocell CPLD

DS013 (v1.9) January 8, 2002

014

Preliminary Product Specification

R

Figure 1: XCR3256XL Typical ICC vs. Frequency at

V

CC

= 3.3V, 25°C

0

2

0

4

0

60

80

1

00

12

0

DS013_01_10240

1

2

040100120140160

Frequency (MHz)

pical I

(

mA

)

Table 1: Typical ICC vs. Frequency at VCC = 3.3V, 25°C

Frequency (MHz) 0 1 10 20 40 60 80 100 120 140

Typica l I

CC

(mA) 0.02 0.91 8.87 17.7 34.8 51.5 68 84.2 100.1 116.6

XCR3256XL 256 Macrocell CPLD

2 www.xilinx.com DS013 (v1.9) Janu ary 8, 2002

1-800-255-7778 Preliminary Product Specification

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DC Electrical Char acteristics Over Reco mmended Operating Conditions

(1)

Symbol Parameter Test Conditions Min. Max. Unit

V

OH

(2)

Output High voltage IOH = –8 mA 2.4 - V

V

OL

Output Low voltage for 3.3V outputs IOL = 8 mA - 0.4 V

I

IL

Input leakage current VIN = GND or V

CC

–10 10 µA

I

IH

I/O High-Z leakage current VIN = GND or V

CC

–10 10 µA

I

CCSB

Standby current VCC = 3.6V - 100 µA

I

CC

Dynamic current

(3,4)

f = 1 MHz - 2 mA
f = 50 MHz - 60 mA

C

IN

Input pin capacitance

(5)

f = 1 MHz - 8 pF

C

CLK

Clock input capacitance

(5)

f = 1 MHz 5 12 pF

C

I/O

I/O pin capacitance

(5)

f = 1 MHz - 10 pF

Notes:

1. See XPLA3 family data sheet (DS012) for rec om me nded operating condit ions.

2. See Figure 2 for output drive characteristics of the XPLA3 family.

3. See Table 1, Figure 1 for typical values.

4. This parameter measured with a 16-bit, resetable up/down counter loaded into every function block, with all outputs disabled and
unloaded. Inputs are tied to V

CC

or ground. This parameter guaranteed by design and characterization, not testing.

5. Typical values, not tested.

Figure 2: Typical I/V Curve for the XPLA3 Family

1

0

2

0

4

0

7

0

1

00

.

51.52.5.54.5

Volt

s

L

3.3V

)

H

3.3V

)

H

2.7V

)

DS012_10_04190

1

XCR3256XL 256 Macrocell CPLD

DS013 (v1.9) January 8, 2002 www.xilinx.com 3
Preliminary Product Specification 1-800-255-7778

R

AC Electrical Characteristics Over Recommended Operating Conditions

(1,2)

Symbol Parameter

-7 -10 -12
Unit Min. Max. Min. Max. Min. Max.

T

PD1

Propagation delay time (single p-term) - 7.0 - 9.0 - 10.8 ns

T

PD2

Propagation delay time (OR array)

(3)

- 7.5 - 10.0 - 12.0 ns

T

CO

Clock to output (global synchronous pin clock) - 4.5 - 5.8 - 6.9 ns

T

SUF

Setup time (fast input register) 2.5 - 3.0 - 3.0 - ns

T

SU1

(4)

Setup time (single p-term) 4.3 - 5.5 - 6.7 - ns

T

SU2

Setup time (OR array) 4.8 - 6.5 - 7.9 - ns

T

H

(4)

Hold time 0-0-0-ns

T

WLH

(4)

Global Clock pulse width (High or Low) 3.0 - 4.0 - 5.0 - ns

Tt

PLH

(4)

P-term clock pulse width 4 .5 - 6.0 - 7. 5 - ns

T

R

(4)

Inpu t r ise ti me - 20 - 20 - 20 n s

T

L

(4)

Input fall time - 20 - 20 - 20 n s

f

SYSTEM

(4)

Maximum system frequency - 140 - 105 - 88 MHz

T

CONFIG

(4)

Configuration time

(5)

- 120 - 120 - 120 µs

T

INIT

(4)

ISP initialization time - 120 - 120 - 120 µs

T

POE

(4)

P-term OE to output enabled - 9.0 - 11.0 - 13.0 ns

T

POD

(4)

P-term OE to output disabled

(6)

- 9.0 - 11.0 - 13.0 ns

T

PCO

(4)

P-term clock to output - 8.0 - 10.3 - 12.4 ns

T

PAO

(4)

P-term set/reset to output valid - 9.0 - 11.0 - 13.0 ns

Notes:

1. Specification s mea sured with one output s wit ching.

2. See XPLA3 family data sheet (

DS012) for recommended operating conditions.

3. See Figure 4 for derating.

4. These parameters guaranteed by design and/or characterization, not testing.

5. Typical current draw during configur ation is 10 mA at 3.6V.

6. Output C

L

= 5 pF.

XCR3256XL 256 Macrocell CPLD

4 www.xilinx.com DS013 (v1.9) Janu ary 8, 2002

1-800-255-7778 Preliminary Product Specification

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Internal Timing Parameters

(1,2)

Symbol Parameter

-7 -10 -12
UnitMin. Max. Min. Max. Min. Max.

Buffer Delays

T

IN

Input buffer delay - 2.5 - 3.3 - 4.0 ns

T

FIN

Fast input buffer delay - 2.2 - 2.8 - 3.3 ns

T

GCK

Global clock buffer delay - 1.0 - 1.3 - 1.5 ns

T

OUT

Output buffer delay - 2.5 - 2.8 - 3.3 ns

T

EN

Output buffer enable/disable delay - 4.5 - 5.2 - 6.0 ns

Internal Register and Combinatorial Delays

T

LDI

Latch transparent delay - 1.3 - 1.6 - 2 .0 ns

T

SUI

Register setup time 0.8 - 1.0 - 1. 2 - ns

T

HI

Register hold time 0.3 - 0.5 - 0.7 - ns

T

ECSU

Register clock enable setup time 2.0 - 2.5 - 3.0 - ns

T

ECHO

Register clock enable hold time 3.0 - 4.5 - 5.5 - ns

T

COI

Register clock to output delay - 1.0 - 1.3 - 1.6 ns

T

AOI

Register async. S/R to output delay - 2.0 - 2.0 - 2 .2 ns

T

RAI

Register async. recovery - 5.0 - 7.0 - 8 .0 ns

T

LOGI1

Internal logic delay (single p-term) - 2.0 - 2.5 - 3.0 ns

T

LOGI2

Internal logic delay (PLA OR term) - 2.5 - 3.5 - 4.2 ns

Feedback Delays

T

F

ZIA delay - 2.8 - 3.7 - 4 .4 ns

Time Adders

T

LOGI3

Fold-back NAND delay - 6. 0 - 8. 0 - 9.5 ns

T

UDA

Universal delay - 2.0 - 2.5 - 3.0 ns

T

SLEW

Slew rate limited delay - 4.0 - 5.0 - 6.0 ns

Notes:

1. These parameters guaranteed by design and/or characterization, not testing.

2. See XPLA3 family data sheet (

DS012) for the timing model.