XILINX XCR3128XL-7VQ100I, XCR3128XL-7VQ100C, XCR3128XL-7TQ144I, XCR3128XL-7TQ144C, XCR3128XL-7CS144I Datasheet
...
DS016 (v1.8) January 8, 2002 www.xilinx.com 1
Preliminary Product Specification 1-800-255-7778
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Features
• Lowest power 128 macrocell CPLD
• 6.0 ns pin-to-pin logic delays
• System frequencies up to 145 MHz
• 128 macrocells with 3,000 usable gates
• Available in small footprint packages
- 144-pin TQFP (108 user I/O pins)
- 144-ball CS BGA (108 user I/O)
- 100-pin VQFP (84 user I/O)
• Optimized for 3.3V systems
- Ultra low power operation
- 5V tolerant I/O pins with 3.3V core supply
- Advanced 0.35 micron five layer metal EEPROM
process
- Fast Zero Power™ (FZP) CMOS design
technology
• Advanced syste m features
- In-system programming
- Input registers
- Predictable timing model
- Up to 23 available clocks per function block
- Excellent pin retention during design changes
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Four global clocks
- Eight product term control term s per function block
• Fast ISP programming times
• Port Enable pin for additional I/O
• 2.7V to 3.6V supply voltage at industrial temperature
range
• Programmable slew rate control per output
• Security bit prevents unauthorized access
• Refer to XPLA3 family data sheet (DS012
) for
architecture description
Description
The XCR3128XL is a 3.3V 128 macrocell CPLD targeted at
power sensitive designs that require leading edge programmable logic solutions. A total of eight function blocks provide
3,000 usable gates. Pin-to-pin propagation delays are
6.0 ns with a maximum system frequency of 145 MHz.
TotalCMOS Design Technique for Fast
Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technology and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate implementation allows Xilinx to offer CPLDs that are both high
performance and low power, breaking the paradigm that to
have low power, you must have low performance. Refer to
Figure 1 and Table 1 showing the I
CC
vs. Frequency of our
XCR3128XL TotalCMOS CPLD (data taken with eight
resetable up/down, 16-bit counters at 3.3V, 25°C).
0
XCR3128XL 128 Macrocell CPLD
DS016 (v1.8) January 8, 2002
014
Preliminary Product Specification
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Figure 1: Typical ICC vs. Frequency at VCC = 3.3V, 25°C
Frequency (MHz)
DS016_01_112100
Typical I
CC
(mA)
0
0
10
20
30
50
70
40
60
120 140100806040
20
Table 1: Typical ICC vs. Frequency at VCC = 3.3V, 25°C
Frequency (MHz) 0 1 5 10 20 40 60 80 100 120 140
Typical I
CC
(mA) 0 0.5 2.2 4.4 8.7 17.1 25.3 33.6 41.6 49.7 57.7
XCR3128XL 128 Macrocell CPLD
2 www.xilinx.com DS016 (v1.8) Janu ary 8, 2002
1-800-255-7778 Preliminary Product Specification
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DC Electrical Char acteristics Over Reco mmended Operating Conditions
(1)
Symbol Parameter Test Conditions Min. Max. Unit
V
OH
(2)
Output High voltage IOH = –8 mA 2.4 - V
V
OL
Output Low voltage for 3.3V outputs IOL = 8 mA - 0.4 V
I
IL
Input leakage current VIN = GND or V
CC
–10 10 µA
I
IH
I/O High-Z leakage current VIN = GND or V
CC
–10 10 µA
I
CCSB
Standby current VCC = 3.6V - 100 µA
I
CC
Dynamic current
(3,4)
f = 1 MHz - 1 m A
f = 50 MHz - 30 mA
C
IN
Input pin capacitance
(5)
f = 1 MHz - 8 p F
C
CLK
Clock input capacitance
(5)
f = 1 MHz - 12 pF
C
I/O
I/O pin capacitance
(5)
f = 1 MHz - 10 pF
Notes:
1. See XPLA3 family dat a sheet (
DS012) for recommended operating conditions.
2. See Figure 2 for output drive characteristics of the XPLA3 family.
3. See Table 1, Figure1 for typical values.
4. This parameter measured with a 16-bit, resetable up/down counter loaded into every function block, with all outputs disabled and
unloaded. Inputs are tied to V
CC
or ground. This parameter guaranteed by design and characterization, not testing.
5. Typical values, not tested.
Figure 2: Typical I/V Curve for the XPLA3 Family
0
0
1
0
2
0
30
4
0
50
60
7
0
80
90
1
00
0.51.52.5.54.5
Volt
s
L
3.3V
)
H
3.3V
)
H
2.7V
)
DS012_10_04190
1
XCR3128XL 128 Macrocell CPLD
DS016 (v1.8) January 8, 2002 www.xilinx.com 3
Preliminary Product Specification 1-800-255-7778
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AC Electrical Characteristics Over Recommended Operating Conditions
(1,2)
Symbol Parameter
-6 -7 -10
Unit Min. Max. Min. Max. Min. Max.
T
PD1
Propagation delay time (single p-term) - 5.5 - 7.0 - 9.1 ns
T
PD2
Propagation delay time (OR array)
(3)
-6.0-7.5-10.0ns
T
CO
Clock to output (global synchronous pin clock) - 4.0 5.0 - 6.5 ns
T
SUF
Setup time (fast input register) 2.5 - 3.0 - 3.0 - ns
T
SU1
(4)
Setup time (single p-term) 3.5 - 4.3 - 5.4 - ns
T
SU2
Setup time (OR array) 4.0 - 4.8 - 6.3 - ns
T
H
(4)
Hold time 0-0-0-ns
T
WLH
(4)
Global Clock pulse width (High or Low) 2.5 - 3.0 - 4.0 - ns
Tt
PLH
(4)
P-term clock pulse width 4.0 - 5.0 - 6.0 - ns
T
R
(4)
Input rise time - 20 - 20 - 20 ns
T
L
(4)
Input fall time - 20 - 20 - 20 ns
f
SYSTEM
(4)
Maximum system frequency - 145 - 119 - 95 MHz
T
CONFIG
(4)
Configuration time
(5)
-60-60-60µs
T
INIT
(4)
ISP initialization tim e - 60 - 60 - 60 µs
T
POE
(4)
P-term OE to output enabled - 7.5 - 9.3 - 11.2 ns
T
POD
(4)
P-term OE to output disabled
(6)
-7.5-9.3-11.2ns
T
PCO
(4)
P-term clock to output - 6.5 - 8.3 - 10.7 ns
T
PAO
(4)
P-term set/reset to output valid - 8.0 - 9.3 - 11.2 ns
Advance Preliminary
Notes:
1. Specificat ions measured with one output switching.
2. See XPLA3 family dat a sheet (
DS012) for recommended operating condi tions.
3. See Figure 4 for derating.
4. These paramet ers guaranteed by design and/or characterization, not test ing.
5. Typical current draw during configuration is 9 mA at 3.6V.
6. Output C
L
= 5 pF.
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