XILINX XC9572-7TQ100C, XC9572-7PQ100C, XC9572-7PC84C, XC9572-7PC44C, XC9572-10PQ100I Datasheet
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December 4, 1998 (Version 3.0) 1
Features
• 7.5 ns pin-to-pin logic delays on all pins
•f
CNT
to 125 MHz
• 72 macrocells with 1,600 usable gates
• Up to 72 user I/O pins
• 5 V in-system programmable (ISP)
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
• Programmable power reduction mode in each
macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design protection
• High-drive 24 mA outputs
• 3.3 V or 5 V I/O capability
• Advanced CMOS 5V FastFLASH technology
• Supports parallel programming of more than one
XC9500 concurrently
• Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP
and 100-pin TQFP packages
Description
The XC9572 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of four
36V18 Function Blocks, providing 1,600 usable gates with
propagation delays of 7.5 ns. See Figure2 for the architecture overview.
Power Management
Power dissipation can be reduced in the XC9572 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power
dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
I
CC
(mA) =
MC
HP
(1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MC
HP
= Macrocells in high-performance mode
MC
LP
= Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure1 shows a typical calculation for the XC9572 device.
1
XC9572 In-System Programmable
CPLD
December 4, 1998 (Version 3.0)
11*
Product Specification
Figure 1: Typical ICC vs. Frequency for XC9572
0
100
200
(65)
(125)
(160)
(100)
Typical I
cc
(ma)
50 100
Clock Frequency (MHz)
L
o
w
P
o
w
e
r
H
i
g
h
P
e
r
f
o
r
m
a
n
c
e
XC9572 In-System Programmable CPLD
2 December 4, 1998 (Version 3.0)
In-System Programming Controller
JTAG
Controller
I/O
Blocks
Function
Block 1
Macrocells
1 to 18
Macrocells
1 to 18
Macrocells
1 to 18
Macrocells
1 to 18
JTAG Port
3
36
I/O/GTS
I/O/GSR
I/O/GCK
I/O
I/O
I/O
I/O
2
1
I/O
I/O
I/O
I/O
3
X5921
1
Function
Block 2
36
Function
Block 3
36
Function
Block 4
36
18
18
18
18
FastCONNECT Switch Matrix
Figure 2: XC9572 Architecture
Note:
Function Block outputs (indicated by the bold line) drive the I/O Blocks directly
December 4, 1998 (Version 3.0) 3
XC9572 In-System Programmable CPLD
Absolute Maximum Ratings
Warning:Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods
of time may affect device reliability.
Recommended Operation Conditions
1
Note: 1. Numbers in parenthesis are for industrial temperature range versions.
Endurance Characteristics
Symbol Parameter Value Units
V
CC
Supply voltage relative to GND -0.5 to 7.0 V
V
IN
DC input voltage relative to GND -0.5 to VCC + 0.5 V
V
TS
Voltage applied to 3-state output with respect to GND -0.5 to VCC + 0.5 V
T
STG
Storage temperature -65 to +150 °C
T
SOL
Max soldering temperature (10 s @ 1/16 in = 1.5 mm) +260 °C
Symbol Parameter Min Max Units
V
CCINT
Supply voltage for internal logic and input buffer 4.75
(4.5)
5.25
(5.5)
V
V
CCIO
Supply voltage for output drivers for 5 V operation 4.75 (4.5) 5.25 (5.5) V
Supply voltage for output drivers for 3.3 V operation 3.0 3.6 V
V
IL
Low-level input voltage 0 0.80 V
V
IH
High-level input voltage 2.0 V
CCINT
+0.5 V
V
O
Output voltage 0 V
CCIO
V
Symbol Parameter Min Max Units
t
DR
Data Retention 20 - Years
N
PE
Program/Erase Cycles 10,000 - Cycles
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