XILINX XC9536XV-7CS48I, XC9536XV-7CS48C, XC9536XV-5VQ44C, XC9536XV-5PC44C, XC9536XV-5CS48C Datasheet
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DS053 (v2.2) August 27, 2001 www.xilinx.com 1
Advance Product Specification 1-800-255-7778
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All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
• 36 macrocells with 800 usable gates
• Available in small footprint packages
- 44-pin PLCC (34 user I/O pins)
- 44-pin VQFP (34 user I/O pins)
- 48-pin CSP (36 user I/O pins)
• Optimized for high-perfo rmance 2.5V systems
- Low power operation
- Multi-voltage operation
• Advanced system features
- In-system programmable
- Superior pin-locking and routability with
FastCONNECT II™ switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with
individual product-term allocation
- Local clock inversion with three global and one
product-term clocks
- Individual output enable per output pin
- Input hysteresis on all user and boundary-scan pin
inputs
- Bus-hold circuitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
• Fast concurrent programming
• Slew rate control on individual outputs
• Enhanced data security features
• Excellent quality and reliability
- Endurance exceeding 10,000 program/erase
cycles
- 20 year data retention
- ESD protection exceeding 2,000V
• Pin-compatible with 3.3V-core XC9536XL device in the
44-pin PLCC, 44-pin VQFP, and 48-pin CSP packages
Description
The XC9536XV is a 2.5V CPLD targeted for high-performance, low-voltage applications in leading-edge communications and computing systems. It is comprised of two
54V18 Function Blocks, providing 800 usable gates with
propagation delays of 3.5 ns. See Figure 2 for architecture
overview.
Power Estimation
Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XV device may be configured for low-power
mode (from the default high-performance mode). In ad dition, unused product-terms and macrocells are automatically deactivated by the software to further conserve power.
For a general estimate of I
CC
, the following equation may be
used:
I
CC
(mA) =
MC
HP
(0.36) + MCLP(0.23) + MC(0.005 mA/MHz) f
Where:
MC
HP
= Macrocells in high-performance (default) mode
MC
LP
= Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
This calculation is based on typical operating conditions
using a pattern of 16-bit up/down counters in each Function
Block with no output loading. The actual I
CC
value varies
with the design application and should be verified during
normal system operation.
Figure 1 shows the above estimation in a graphical form.
0
XC9536XV High-performance
CPLD
DS053 (v2.2) August 27, 2001
01
Advance Product Specification
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Figure 1: Typi cal ICC vs. Frequency for XC9536XV
Clock Frequency (MHz)
Typical I
CC
(mA)
0 100 200
DS053_01_012501
60
20
120 MHz
200 MHz
30
L
ow
Power
15050
10
40
50
H
i
g
hPerfo
r
mance
XC9536XV High-performance CPLD
2 www.xilinx.com DS053 (v2.2) Augus t 27, 2001
1-800-255-7778 Advance Product Specification
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Figure 2: XC9536XV Architecture
Function block outputs (indicated by the bold line) drive the I/O Blocks directly.
In-System Programming Controller
JTAG
Controller
I/O
Blocks
Function
Block 1
Macrocells
1 to 18
Macrocells
1 to 18
JTAG Port
3
54
I/O/GTS
I/O/GSR
I/O/GCK
I/O
I/O
I/O
I/O
2
1
I/O
I/O
I/O
I/O
3
DS053_02_041200
1
Function
Block 2
54
18
18
FastCONNECT II Switch Matrix
XC9536XV High-performance CPLD
DS053 (v2.2) August 27, 2001 www.xilinx.com 3
Advance Product Specification 1-800-255-7778
R
Absolute Maximum Ratings
Recommended Operation Conditions
Quality and Reliability Characteristics
Symbol Description Value Units
V
CC
Supply voltage relative to GND –0.5 to 2.7 V
V
CCIO
Supply voltage for output drivers –0.5 to 3.6 V
V
IN
Input voltage relative to GND
(1)
–0.5 to 3.6 V
V
TS
Voltage applied to 3-state output
(1)
–0.5 to 3.6 V
T
STG
Storage temperature (ambient) –65 to +150
o
C
T
SOL
Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260
o
C
T
J
Junction temperature +150
o
C
Notes:
1. Maximum DC under shoot bel ow GND mus t be l imite d to ei ther 0 .5V or 10 mA, whiche ve r is e asi er to achie v e . During t ransi tio ns , the
device pins may undershoot to –2.0V or ov ershoot to +3.6V, provided this over- or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions be yond those listed under O perating Conditions
is not implied. Exposure to Absolute Maximum Ratings condition s for ext ended periods of time may affect device reliability.
Symbol Parameter Min Max Units
V
CCINT
Supply voltage for internal logic
and input buffers
Comme r c ial TA = 0oC to +70oC2.37 2.62 V
Industrial T
A
= –40oC to +85oC2.37 2.62
V
CCIO
Supply voltage for output drivers for 3.3V operation 3.13 3.46 V
Supply voltage for output drivers for 2.5V operation 2.37 2.62 V
Supply voltage for output drivers for 1.8V operation 1.71 1.89 V
V
IL
Low-level input voltage 0 0.8 V
V
IH
High-level input voltage 1.7 3.6 V
V
O
Output voltage 0 V
CCIO
V
Symbol Parameter Min Max Units
T
DR
Data Retention 20 - Years
N
PE
Program/Erase Cycles (Endurance) 10,000 - Cycles
V
ESD
Electrostatic Discharge (ESD) 2,000 - Volts
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