XILINX XC95288XV-7FG256C, XC95288XV-7CS280C, XC95288XV-5TQ144C, XC95288XV-5PQ208C, XC95288XV-5FG256C Datasheet
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DS050 (v2.2) August 27, 2001 www.xilinx.com 1
Advance Product Specification 1-800-255-7778
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
• 288 macrocells with 6,400 usable gates
• Available in small footprint packages
- 144-pin TQFP (117 user I/O pins)
- 208-pin PQFP (168 user I/O pins)
- 280-pin CSP (192 user I/O pins)
- 256-pin FBGA (192 user I/O pins)
• Optimized for high-perfo rmance 2.5V systems
- Low power operation
- Multi-voltage operation
• Advanced system features
- In-system programmable
- Four separate output banks
- Superior pin-locking and routability with
FastCONNECT II™ switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with
individual product-term allocation
- Local clock inversion with three global and one
product-term clocks
- Individual output enable per output pin
- Input hysteresis on all user and boundary-scan pin
inputs
- Bus-hold ciruitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
• Fast concurrent programming
• Slew rate control on individual outputs
• Enhanced data security features
• Excellent quality and reliability
- Endurance exceeding 10,000 program/erase
cycles
- 20 year data retention
- ESD protection exceeding 2,000V
Description
The XC95288XV is a 2.5V CPLD targeted for high-performance, low-voltage applications in leading-edge communications and computing systems. It is comprised of 16
54V18 Function Blocks, providing 6,400 usable gates with
propagation delays of 5 ns.
Power Estimation
Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XV device may be configured for low-power
mode (from the default high-performance mode). In ad dition, unused product-terms and macrocells are automatically deactivated by the software to further conserve power.
For a general estimate of I
CC
, the following equation may be
used:
I
CC
(mA) =
MC
HP
(0.36) + MCLP(0.23) + MC(0.005 mA/MHz) f
Where:
MC
HP
= Macrocells in high-performance (default) mode
MC
LP
= Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
This calculation is based on typical operating conditions
using a pattern of 16-bit up/down counters in each Function
Block with no output loading. The actual I
CC
value varies
with the design application and should be verified during
normal system operation.
Figure 1 shows the above estimation in a graphical form.
0
XC95288XV High-Performance
CPLD
DS050 (v2.2) August 27, 2001
05
Advance Product Specification
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Figure 1: Typical I
CC
vs. Frequency for XC95288XV
Clock Frequency (MHz)
Typical I
CC
(mA)
100 200 250
DS050_01_012501
200
250
300
350
400
450
50
50 150
150
100
0
120 MHz
H
i
gh P
e
r
form
a
nce
200 MHz
Low Powe
r
XC95288XV High-Performance CPLD
2 www.xilinx.com DS050 (v2.2) Augus t 27, 2001
1-800-255-7778 Advance Product Specification
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Figure 2: XC9528 8X V Architecture
(Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.)
In-System Programming Controller
JTAG
Controller
I/O
Blocks
Function
Block 1
Macrocells
1 to 18
Macrocells
1 to 18
JTAG Port
3
54
I/O/GTS
I/O/GSR
I/O/GCK
I/O
I/O
I/O
I/O
4
1
I/O
I/O
I/O
I/O
3
DS055_02_101300
1
Function
Block 2
54
18
18
Function
Block 3
Macrocells
1 to 18
Macrocells
1 to 18
54
Function
Block 16
54
18
18
Function
Block 4
Macrocells
1 to 18
54
18
FastCONNECT II Switch Matrix
XC95288XV High-Performance CPLD
DS050 (v2.2) August 27, 2001 www.xilinx.com 3
Advance Product Specification 1-800-255-7778
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Absolute Maximum Ratings
Recommended Operation Conditions
Quality and Reliability Characteristics
Symbol Description Value Units
V
CC
Supply voltage relative to GND –0.5 to 2.7 V
V
CCIO
Supply voltage for output drivers –0.5 to 3.6 V
V
IN
Input voltage relative to GND
(1)
–0.5 to 3.6 V
V
TS
Voltage applied to 3-state output
(1)
–0.5 to 3.6 V
T
STG
Storage temperature (ambient) –65 to +150
o
C
T
SOL
Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260
o
C
T
J
Junction temperature +150
o
C
Notes:
1. Maximum DC unders hoot bel ow GND must be l imit ed to ei ther 0. 5V or 10 mA , whi chever is easi er to a chie v e . During tr a nsitions , the
device pins may undershoot to –2.0V or overshoot to +3.6V, provided this over- or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions bey ond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings condition s for ext ended periods of time may affect device reliability.
Symbol Parameter Min Max Units
V
CCINT
Supply voltage for internal logic
and input buffers
Commercial TA = 0oC to +70oC2.372.62 V
Industrial T
A
= –40oC to +85oC2.372.62
V
CCIO
Supply voltage for output drivers for 3.3V operation 3.13 3.46 V
Supply voltage for output drivers for 2.5V operation 2.37 2.62 V
Supply voltage for output drivers for 1.8V operation 1.71 1.89 V
V
IL
Low-level input volt ag e 0 0.8 V
V
IH
High-level input voltage 1.7 3.6 V
V
O
Output voltage 0 V
CCIO
V
Symbol Parameter Min Max Units
T
DR
Data retention 20 - Years
N
PE
Program/Erase cycles (endurance) 10,000 - Cycles
V
ESD
Electrostatic Discharge (ESD) 2,000 - Volts
XC95288XV High-Performance CPLD
4 www.xilinx.com DS050 (v2.2) Augus t 27, 2001
1-800-255-7778 Advance Product Specification
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DC Characteristics Over Recommended Operating Conditions
AC Characteristics
Symbol Parameter Test Conditions Min Max Units
V
OH
Output high voltage for 3.3V outputs IOH = –4.0 mA 2.4 - V
Output high voltage for 2.5V outputs I
OH
= –1.0 mA 2.0 - V
Output high voltage for 1.8V outputs I
OH
= –100 µA90%
V
CCIO
-V
V
OL
Output low voltage for 3.3V outputs IOL = 8.0 mA - 0.4 V
Output low voltage for 2.5V outputs I
OL
= 1.0 mA - 0.4 V
Output low voltage for 1.8V outputs I
OL
= 100 µA-0.4V
I
IL
Input leakagelow current VCC = 2.62V
V
CCIO
= 3.6V
V
IN
= GND or 3.6V
-10µA
I
IH
Input leakage high current VCC = 2.62V
V
CCIO
= 3.6V
V
IN
= GND or 3.6V
-10µA
C
IN
I/O capacitance VIN = GND
f = 1.0 MHz
-10pF
I
CC
Operating Supply Current
(low power mode, active)
VI = GND, No load
f = 1.0 MHz
59 mA
Symbol Parameter
XC95288XV-5 XC95288XV-7 XC95288XV-10
UnitsMin Max Min Max Min Max
T
PD
I/O to output valid - 5.0 - 7.5 - 10 ns
T
SU
I/O setup time before GCK 3.5 - 4.8 - 6.5 - ns
T
H
I/O hold time after GCK 0 - 0 - 0 - ns
T
CO
GCK to output valid - 3.5 - 4.5 - 5.8 ns
f
SYSTEM
Multiple FB internal operating
frequency
- 222.2 - 125.0 - 100.0 MHz
T
PSU
I/O setup time before p-term clock
input
1.0 - 1.6 - 2.1 - ns
T
PH
I/O hold time after p-term clock input 2.5 - 3.2 - 4.4 - ns
T
PCO
P-term clock output valid - 6.0 - 7.7 - 10.2 ns
T
OE
GTS to output valid - 4.0 - 5 .0 - 7.0 ns
T
OD
GTS to output disable - 4.0 - 5 .0 - 7.0 ns
T
POE
Product term OE to output enabled - 7.0 - 9.5 - 11.0 ns
T
POD
Product term OE to output disabled - 7.0 - 9.5 - 11.0 ns
T
AO
GSR to output valid - 10.0 - 12.0 - 14.5 ns
T
PAO
P-term S/R to output valid - 10.7 - 12. 6 - 15.3 ns
T
WLH
GCK pulse width (High or Low) 2.2 - 4.0 - 5.0 - ns
T
PLH
P-term clock pulse width (High or Low) 5.0 - 6.5 - 7.0 - ns
Advance Information Preliminary Information
Notes:
1.
Please c on t ac t X ilin x for up-to-date infor mation on ad vanc e specificat ions.
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