XILINX XC95288-15HQ208C, XC95288-15BG352I, XC95288-15BG352C, XC95288-10HQ208C, XC95288-10BG352C Datasheet
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September 15, 1999 (Version 4.0) 1
Features
• 10 ns pin-to-pin logic delays on all pins
•f
CNT
to 95 MHz
• 288 macrocells with 6,400 usable gates
• Up to 192 user I/O pins
• 5 V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
• Programmable power reduction mode in each
macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design protection
• High-drive 24 mA outputs
• 3.3 V or 5 V I/O capability
• Advanced CMOS 5V FastFLASH technology
• Supports parallel programming of more than one
XC9500 concurrently
• Available in 352-pin BGA and 208-pin HQFP packages
Description
The XC95288 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of sixteen
36V18 Function Blocks, providing 6,400 usable gates with
propagation delays of 10 ns. See Figure 2 for the architecture overview.
Power Management
Power dissipation can be reduced in the XC95288 by configuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
I
CC
(mA) =
MC
HP
(1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MC
HP
= Macrocells in high-performance mode
MC
LP
= Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical calculation for the XC95288
device.
0
XC95288 In-System Programmable
CPLD
September 15, 1999 (Version 4.0)
05*
Product Specification
Clock Frequency (MHz)
Typical I
CC
(mA)
050
300
(500)
(700)
(500)
600
900
100
High Performance
Low Power
X7131
Figure 1: Typical ICC vs. Frequency For XC95288
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XC95288 In-System Programmable CPL D
2 September 15, 1999 (Version 4.0)
In-System Programming Controller
JTAG
Controller
I/O
Blocks
Function
Block 1
Macrocells
1 to 18
Macrocells
1 to 18
Macrocells
1 to 18
Macrocells
1 to 18
JTAG Port
3
36
I/O/GTS
I/O/GSR
I/O/GCK
I/O
I/O
I/O
I/O
2
1
I/O
I/O
I/O
I/O
3
X5924
1
Function
Block 2
36
Function
Block 3
36
Function
Block 4
36
Macrocells
1 to 18
Function
Block 16
36
18
18
18
18
18
FastCONNECT Switch Matrix
Figure 2: XC95288 Architecture
Note: Function Bloc k outputs (indicated by the bold line) drive the I/O Blocks directly
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September 15, 1999 (Version 4.0) 3
XC95288 In-System Programmable CPLD
5
Absolute Maximum Ratings
Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods
of time may affect device reliability.
Recommended Operation Conditions
1
Note: 1. Numbers in parenthesis are for industrial-temperature range versions.
Endurance Characteristics
Symbol Parameter Value Units
V
CC
Supply voltage relative to GND -0.5 to 7.0 V
V
IN
DC input voltage relative to GND -0.5 to VCC + 0.5 V
V
TS
Voltage applied to 3-state output with respect to GND -0.5 to VCC + 0.5 V
T
STG
Storage temperature -65 to +150 °C
T
SOL
Max soldering temperature (10 s @ 1/16 in = 1.5 mm) +260 °C
Symbol Parameter Min Max Units
V
CCINT
Supply voltage for internal logic and input buffer 4.75
(4.5)
5.25
(5.5)
V
V
CCIO
Supply voltage for output drivers for 5 V operation 4.75 (4.5) 5.25 (5.5) V
Supply voltage for output drivers for 3.3 V operation 3.0 3.6 V
V
IL
Low-level input voltage 0 0.80 V
V
IH
High-level input voltage 2.0 V
CCINT
+0.5 V
V
O
Output voltage 0 V
CCIO
V
Symbol Parameter Min Max Units
t
DR
Data Retention 20 - Years
N
PE
Program/Erase Cycles 10,000 - Cycles
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XC95288 In-System Programmable CPL D
4 September 15, 1999 (Version 4.0)
DC Characteristics Over Recommended Operating Conditions
AC Characteristics
Note: 1. f
CNT
is the fastest 16-bit counter frequency available, using the local feedback when applicable.
f
CNT
is also the Export Control Maximum flip-flop toggle rate, f
TOG
.
2. f
SYSTEM
is the internal operating frequency for general purpose system designs spanning multi ple FBs.
Symbol Parameter Test Conditions Min Max Units
V
OH
Output high voltage for 5 V operation IOH = -4.0 mA
V
CC
= Min
2.4 V
Output high voltage for 3.3 V operation I
OH
= -3.2 mA
V
CC
= Min
2.4 V
V
OL
Output low voltage for 5 V operation IOL = 24 mA
V
CC
= Min
0.5 V
Output low voltage for 3.3 V operation I
OL
= 10 mA
V
CC
= Min
0.4 V
I
IL
Input leakage current VCC = Max
V
IN
= GND or V
CC
±10.0 µA
I
IH
I/O high-Z leakage current VCC = Max
V
IN
= GND or V
CC
±10.0 µA
C
IN
I/O capacitance VIN = GND
f = 1.0 MHz
±10.0 pF
I
CC
Operating Supply Current
(low power mode, active)
VI = GND, No load
f = 1.0 MHz
300 (Typ) m a
Symbol Parameter
XC95288-10 XC95288-15 XC95288-20
Units
Min Max Min Max Min Max
t
PD
I/O to output valid 10.0 15.0 20.0 ns
t
SU
I/O setup time before GCK 6.0 8.0 10.0 ns
t
H
I/O hold time after GCK 0.0 0.0 0.0 ns
t
CO
GCK to output valid 6.0 8.0 10.0 ns
f
CNT
1
16-bit counter frequency 111.1 95.2 83.3 MHz
f
SYSTEM
2
Multiple FB internal operating frequency 66.7 55.6 50.0 MHz
t
PSU
I/O setup time before p-term clock input 2.0 4.0 4.0 ns
t
PH
I/O hold time after p-term clock input 4.0 4.0 6.0 ns
t
PCO
P-term clock to output valid 10.0 12.0 16.0 ns
t
OE
GTS to output valid 6.0 11.0 16.0 ns
t
OD
GTS to output disable 6.0 11.0 16.0 ns
t
POE
Product term OE to output enabled 10.0 14.0 18.0 ns
t
POD
Product term OE to output disabled 10.0 14.0 18.0 ns
t
WLH
GCK pulse width (High or Low) 4.5 5.5 5.5 ns
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