XILINX XC95144XL-7TQ100C, XC95144XL-7CS144C, XC95144XL-5TQ100C, XC95144XL-10TQ100I, XC95144XL-10TQ100C Datasheet
November 13, 1998 (Version 1.2) 1
Features
•5 ns pin-to-pin logic delays
•System frequency up to 178 MHz
•144 macrocells with 3,200 usable gates
•Available in small footprint packages
- 100-pin TQFP (81 user I/O pins)
- 144-pin TQFP (117 user I/O pins)
- 144-pin CSP (117 user I/O pins)
•Optimized for high-performance 3.3 V systems
- Low power operation
- 5 V tolerant I/O pins accept 5 V, 3.3 V, and 2.5 V
signals
- 3.3 V or 2.5 V output capability
- Advanced 0.35 micron feature size CMOS
FastFLASH™ technology
•Advanced system features
- In-system programmable
- Superior pin-locking and routability with
FastCONNECT II™ switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with individual
product-term allocation
- Local clock inversion with 3 global and one productterm clocks
- Individual output enable per output pin with local
inversion
- Input hysteresis on all user and boundary-scan pin
inputs
- Bus-hold ciruitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
•Fast concurrent programming
•Slew rate control on individual outputs
•Enhanced data security features
• Excellent quality and reliability
- Endurance exceeding 10,000 program/erase cycles
- 20 year data retention
- ESD protection exceeding 2,000 V
•Pin-compatible with 5 V-core XC95144 device in the
100-pin TQFP package
Description
The XC95144XL is a 3.3 V CPLD targeted for high-performance, low-voltage applications in leading-edge communications and computing systems. It is comprised of eight
54V18 Function Blocks, providing 3,200 usable gates wi th
propagation delays of 5 ns. See Figure2 for architecture
overview.
Power Estimation
Power dissipation in CPLDs c an very subs tantiall y depending on the system frequency, design application, and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XL device may be configured for low-power
mode (from the default high-performance mode). In addition, unused product-terms and macrocells are automatically deactivated by the software to further conserve power.
For a general estimate of I
CC
, the following equation may
be used:
ICC (mA) = MCHP(0.5) + MCLP(0.3) + MC(0.0045 mA/MHz) f
Where:
MC
HP
= Macrocells in high-performance (default) mode
MC
LP
= Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
This calculation is based on typical operating conditions
using a pattern of 16-bit up/down counters in each Function
Block with no output loading. T he actual I
CC
value varies
with the design application and should be verified during
normal system operation.
Figure1 shows the above estimation in graphical form.
Figure 1: Typical I
cc
vs. Frequency for XC95144XL
XC95144XL High Performance
CPLD
November 13, 1998 (Version 1.2)
Preliminary Product Specification
Clock Frequency (MHz)
Typical I
CC
(mA)
0 100 200
X5898C
200
100
178 MHz
104 MHz
Low Power
High Performance
50
150
50
150
XC95144XL High Performance CPLD
2 November 13, 1998 (Version 1.2)
In-System Programming Controller
JTAG
Controller
I/O
Blocks
Function
Block 1
Macrocells
1 to 18
Macrocells
1 to 18
Macrocells
1 to 18
Macrocells
1 to 18
JTAG Port
3
54
I/O/GTS
I/O/GSR
I/O/GCK
I/O
I/O
I/O
I/O
4
1
I/O
I/O
I/O
I/O
3
X5922B
1
Function
Block 2
54
Function
Block 3
54
Function
Block 4
54
Macrocells
1 to 18
Function
Block 8
54
18
18
18
18
18
FastCONNECT II Switch Matrix
Figure 2: XC95144XL Architecture
Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.
November 13, 1998 (Version 1.2) 3
Absolute Maximum Ratings
Recommended Operation Conditions
Quality and Reliability Characteristics
DC Characteristics Over Recommended Operating Conditions
Symbol Description Value Units
V
CC
Supply voltage relative to GND -0.5 to 4.0 V
V
IN
Input voltage relative to GND (Note 1) -0.5 to 5.5 V
V
TS
Voltage applied to 3-state output (Note 1) -0.5 to 5.5 V
T
STG
Storage temperature (ambient) -65 to +150
o
C
T
SOL
Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260
o
C
T
J
Junction temperature
+150
o
C
Note 1: Maximum DC undershoot below GND must be limited to either 0.5 V or 10 mA, whichever is easier to achieve. During
transitions, the device pins may undershoot to -2.0 V or overshoot to +7. 0 V, provided this over- or undershoot lasts less
than 10 ns and with the f orci ng current being limited to 200 mA.
Note 2: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those l isted under Operating
Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device
reliability.
Symbol Parameter Min Max Units
V
CCINT
Supply voltage for internal logic
and input buffers
Commercial TA = 0oC to 70oC3.0 3.6 V
Industrial T
A
= -40oC to +85oC3.0 3.6 V
V
CCIO
Supply voltage for output drivers for 3.3 V operation 3.0 3.6 V
Supply voltage for output drivers for 2.5 V operation 2.3 2.7 V
V
IL
Low-level input voltage 0 0.80 V
V
IH
High-level input voltage 2.0 5.5 V
V
O
Output voltage 0 V
CCIO
V
Symbol Parameter Min Max Units
t
DR
Data Retention 20 - Years
N
PE
Program/Erase Cycles (Endurance) 10,000 - Cycles
V
ESD
Electrostatic Discharge (ESD) 2,000 - Volts
Symbol Parameter Test Conditions Min Max Units
V
OH
Output high voltage for 3.3 V outputs IOH = -4.0 mA 2.4 V
Output high voltage for 2.5 V outputs I
OH
= -500 µA90% V
CCIO
V
V
OL
Output low voltage for 3.3 V outputs IOL = 8.0 mA 0.4 V
Output low voltage for 2.5 V outputs I
OL
= 500 µA0.4V
I
IL
Input leakage current VCC = Max
V
IN
= GND or V
CC
± 10.0 µA
I
IH
I/O high-Z leakage current VCC = Max
V
IN
= GND or V
CC
± 10.0 µA
C
IN
I/O capacitance VIN = GND
f = 1.0 MHz
10.0 pF
I
CC
Operating Supply Current
(low power mode, active)
VI = GND, No load
f = 1.0 MHz
45 ma
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