XILINX XC4085XLA-09BG560I, XC4085XLA-09BG560C, XC4085XLA-09BG432I, XC4085XLA-09BG432C, XC4085XLA-09BG352I Datasheet

DS015 (v1.3) October 18, 1999 - Product Specification 6-157

6

XC4000XLA/XV Family Features

Note: XC4000XLA devices are improved versions of

XC4000XL devices. The XC4000XV devices have the
same features as XLA devices, incorporate additional inter­connect resources and extend gate capacity to 500,000
system gates. The XC4000XV devices require a separate

2.5V power supply for internal logic but maintain 5V I/O
compatibility via a separate 3.3V I/O power supply. For
additional information about the XC4000XLA/XV device
architecture, refer to the XC4000E/X FPGA Series general
and functional descriptions.

• System-featured Field-Programmable Gate Arrays

- Select-RAMTM memory: on-chip ultra-fast RAM with

- Synchronous write option

- Dual-port RAM option

- Flexible function generators and abundant flip-flops

- Dedicated high-speed carry logic

- Internal 3-state bus capability

- Eight global low-skew clock or signal distribution
networks

• Flexible Array Architecture

• Low-power Segmented Routing Architecture

• Systems-oriented Features

- IEEE 1149.1-compatible boundary scan

- Individually programmable output slew rate

- Programmable input pull-up or pull-down resistors

- Unlimited reprogrammability

• Read Back Capability

- Program verification and internal node observability

Electrical Features

• XLA Devices Require 3.0 - 3.6 V (VCC)

• XV Devices Require 2.3- 2.7 V (VCCINT)
and 3.0 - 3.6 V (VCCIO)

• 5.0 V TTL compatible I/O

• 3.3 V LVTTL, LVCMOS compliant I/O

• 5.0 V and 3.0 V PCI Compliant I/O

• 12 mA or 24 mA Current Sink Capability

• Safe under All Power-up Sequences

• XLA Consumes 40% Less Power than XL

• XV Consumes 65% Less Power than XL

• Optional Input Clamping to VCC (XLA) or VCCIO (XV)

Additional Features

• Footprint Compatible with XC4000XL FPGAs - Lower
cost with improved performance and lower power

• Advanced Technology — 5 layermetal, 0.25 µm CMOS
process (XV) or 0.35 µm CMOS process (XLA)

• Highest Performance — System erformance beyond
100 MHz

• High Capacity — Up to 500,000 system gates and
270,000 synchronous SRAM bits

• Low Power — 3.3 V/2.5 V technology plus segmented
routing architecture

• Safe and Easy to Use — Interfaces to any combination
of 3.3 V and 5.0 V TTL compatible devices

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XC4000XLA/XV Field Programmable
Gate Arrays

DS015 (v1.3) October 18, 1999

00*

Product Specification

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*

Table 1: XC4000XLA Series Field Programmable Gate Arrays

Device

Logic

Cells

Max Logic

Gates

(No RAM)

Max. RAM

Bits

(No Logic)

Typical

Gate Range

(Logic and RAM)*

CLB

Matrix

Total

CLBs

Number

of

Flip-Flops

Max.

User I/O

Required
Configur-

ation Bits

XC4013XLA 1,368 13,000 18,432 10,000 - 30,000 24 x 24 576 1,536 192 393,632
XC4020XLA 1,862 20,000 25,088 13,000 - 40,000 28 x 28 784 2,016 224 521,880
XC4028XLA 2,432 28,000 32,768 18,000 - 50,000 32 x 32 1,024 2,560 256 668,184
XC4036XLA 3,078 36,000 41,472 22,000 - 65,000 36 x 36 1,296 3,168 288 832,528
XC4044XLA 3,800 44,000 51,200 27,000 - 80,000 40 x 40 1,600 3,840 320 1,014,928
XC4052XLA 4,598 52,000 61,952 33,000 - 100,000 44 x 44 1,936 4,576 352 1,215,368
XC4062XLA 5,472 62,000 73,728 40,000 - 130,000 48 x 48 2,304 5,376 384 1,433,864
XC4085XLA 7,448 85,000 100,352 55,000 - 180,000 56 x 56 3,136 7,168 448 1,924,992
XC40110XV 9,728 110,000 131,072 75,000 - 235,000 64 x 64 4,096 9,216 448 2,686,136
XC40150XV 12,312 150,000 165,888 100,000 - 300,000 72 x 72 5,184 11,520 448 3,373,448
XC40200XV 16,758 200,000 225,792 130,000 - 400,000 84 x 84 7,056 15,456 448 4,551,056
XC40250XV 20,102 250,000 270,848 180,000 - 500,000 92 x 92 8,464 18,400 448 5,433,888

* Maximum values of gate range assume 20-30% of CLBs used as RAM

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XC4000XLA/XV Field Programmable Gate Arrays

6-158 DS015 (v1.3) October 18, 1999 - Product Specification

General Description

XC4000 Series high-performance, high-capacity Field Pro­grammable Gate Arrays (FPGAs) provide the benefits of
custom CMOS VLSI, while avoiding the initial cost, long
development cycle, and inherent risk of a conventional
masked gate array.

The result of fifteen years of FPGA design experience and
feedbackfromthousandsofcustomers, these FPGAs com­bine architectural versatility, increased speed, abundant
routing resources, and new, sophisticated software to
achieve fully automated implementation of complex,
high-density, high-performance designs.

Technology Advantage

XC4000XLA/XV FPGAs use 5 layer metal silicon technol­ogy to improve performance while reducing device cost and
power. In addition, IOB enhancements provide full PCI
compliance and the JTAG functionality is expanded.

Low Power Internal Logic

XC4000XV FPGAs incorporate all the features of the XLA
devices but require a separate 2.5V power supply for inter­nal logic. I/O pads are still driven from a 3.3V power supply.
The 2.5V logic supply is named VCCINT and the 3.3 V IO
supply is named VCCIO.

The XV devices also incorporate additional routing
resources in the form of 8 octal-length segmented routing
channels vertically and horizontally per row and column.

XLA/XV and XL Family Differences

The XC4000XLA/XV families of FPGAs are logically identi­cal to XC4000EX and XC4000XL FPGAs, however I/O,
configuration logic, JTAG functionality, and performance
have been enhanced. In addition, they deliver:

• Improved Performance
XLA/XV devices benefit from advance processing
technology and a reduction in interconnect capacitance
which improves performance over XL devices by more
than 30%.

• Lower Power
XLA/XV devices have reduced power requirements
compared to equivalent XL devices.

• Shorter routing delays
The smaller die of XLA/XV devices directly reduces
clock delays and the delay of high-fanout signals. The
reduction in clock delay allows improved pin-to-pin I/O
specifications.

• Lower Cost
XLA/XV device cost is directly related to the die size
and has been reduced significantly from that of
equivalent XL devices.

• Express mode configuration
Express mode configuration is availableon the XLA and
XV devices.

IOB Enhancements

• 12/24 mA Output Drive
The XLA/XV family of FPGAs allow individual IOBs to
be configured as high drive outputs. Each output can be
configured to have 24 mA drive strength as opposed to
the standard default strength of 12 mA.

• VCC Clamping Diode
XLA and XV FPGAs have an optional clamping diode
connected from each output to VCC (VCCIO for XV).
When enabled they clamp ringing transients back to the

3.3V supply rail. This clamping action is required in

3.3V PCI applications. VCC clamping is a global option
affecting all I/O pins. If enabled, TTL I/O compatibility is
maintained, but full 5.0 Volt I/O tolerance is sacrificed.

• Enhanced ESD protection
An improved ESD structure allows XV devices to safely
pass the stringent 5V PCI (4.2.1.3) ringing test. This
test applies an 11V pulse to each IOB for 11 ns via a 55
ohm resistor.

• Full 3.3V and 5.0V PCI compliance
The addition of 12/24 mA drive, optional 3.3V clamping
and improved ESD provides full compliance with either

3.3V or 5.0V PCI specifications.

Figure 1: Cross Section of Xilinx 0.25 micron, 5 layer
metal XC4000XV FPGA. Visible features are five layers of

metallization, tungsten plug vias and trench isolation. The
small gaps above the lowest layer are 0.25 micron
polysilicon MOSFET gates. The excellent planarity of each
metal layer is due to the use of “chemical-mechanical
polishing” or CMP.In effect, each layer is ground flat before
a new layer is added.

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DS015 (v1.3) October 18, 1999 - Product Specification 6-159

XC4000XLA/XV Field Programmable Gate Arrays

6

Three-State Register

XC4000XLA/XV devices incorporate an optional register
controlling the three-state enable in the IOBs.The use of
the three-state control register can significantly improve
output enable and disable time.

FastCLK Clock Buffers

The XLA/XV devices incorporate FastCLK clock buffers.
Two FastCLK buffers are available on each of the right and
left edges of the die. Each FastCLK buffer can provide a
fast clock signal (typically < 1.5 ns clock delay) to all the
IOBs within the IOB octant containing the buffer. The Fast­CLK buffers can be instantiated by use of the BUFFCLK
symbols. (In addition to FastCLK buffers, the Global Early
BUFGE clock buffers #1, #2, #5, and #6 can also provide
fast clock signals (typically < 1.5 ns clock delay) to IOBs on
the top and bottom of the die.

XLA/XV Power Requirements

XC4000XLA devices require 40% less power per CLB than
equivalent XL devices. XC4000XV devices require 42%
less power per CLB than equivalent XLA devices and 65%
less power than XL devices The representative K-Factor for
the following families can be foundin Table 2. The K-Factor
predicts device current for typical user designs and is
based on filling the FPGA with active 16-Bit counters and
measuring the device current at 1 MHz. This technique is
described in XBRF14 “A Simple Method of Estimating
Power in XC4000XL/EX/E FPGAs”. To predict device
power (P) using the K-Factor use the following formula:

P=V*K*N*F; where:
P= Device Power

V= Power supply voltage
K= the Device K-Factor
N = number of active registers
F = Frequency in MHz

XLA/XV Logic Performance

XC4000XLA/XV devices feature 30% faster device speed
than XL devices, and consistent performance is achieved
across all family members. Table 3 illustrates the perfor­mance of the XLA devices. For details regarding the imple­mentation of these benchmarks refer to XBRF15 “Speed
Metrics for High Performance FPGAs”.

Table 2: K-Factor and Relative Power.

FPGA Family K-Factor

Power

RelativeTo

XL

Power

RelativeTo

XLA

XC4000XL 28 1.00 1.65

XC4000XLA 17 0.60 1.00

XC4000XV 13 0.35 0.58

Table 3: XLA/XV Estimated Benchmark Performance

Register - Register

Benchmarks

Size

Maximum

Frequency

Adder

8-Bit 172 MHz
16-Bit 144 MHz
32-Bit 108 MHz

2 Cascaded Adders 16-Bit 94 MHz
4 Cascaded Adders 16-Bit 57 MHz

Cascaded 4LUTs

1 Level 314 MHz
2 Level 193 MHz
4 Level 108 MHz
6 Level 75 MHz

Interconnect

(Manhattan Distance)

1 CLBs 325 MHz

4 CLBs 260 MHz
16 CLBs 185 MHz
64 CLBs 108 MHz

128 CLBs 81 MHz

Dual Port RAM

(Pipelined)

8-Bits by 16 172 MHz

8-Bits by 256 172 MHz

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XC4000XLA/XV Field Programmable Gate Arrays

6-160 DS015 (v1.3) October 18, 1999 - Product Specification

Using Fast I/O CLKS

There are severalissues associated with implementing fast
I/O clocks by using multiple FastCLK and BUFGE clock
buffers for I/O transfers and a BUFGLS clock buffer for
internal logic.

Reduced Clock to Out Period - When transferring data
from a BUFGLS clocked register to an IOB output register
which is clocked with a fast I/O clock, the total amount of
time available for the transfer is reduced.

Using Fast Capture Latch in IOB input - It is necessary to
transfer data captured with the fast I/O clock edge to a
delayed BUFGLS clock without error. The use of the Fast
Capture Latch in the IOBs provides this functionality.

Driving multiple clock inputs - Since each FastCLK input
can only reach one octant of IOBs it will usually be neces­sary to drive multiple FastCLK and BUFGE input pads with
a copy of the system clock. Xilinx recommends that sys­tems which use multiple FastCLK and BUFGE input buffers
use a “Zero Delay” clock buffer such as the Cypress
CY2308 to driveup to 8 input pins. These devices contain a
Phase locked loop to eliminate clock delay, and specify less
than 250ps output jitter.

PCB layout - The recommended layoutis to place the PLL
underneath the FPGA on the reverse side of the PCB. All 8
clock lines should be of equal length. This arrangement will
allow all the clock line to be less than 2 cm in length which
will generally eliminate the need for clock termination.

Advancing the FPGAs clock - An additional advantage to
using a PLL-equipped clock bufferis that it can advance the
FPGA clocks relative to the system clock by incorporating
additional board delay in the feedback path. Approximately
6 inches of trace length are necessary to delay the signal
by 1 ns.

Advancing the FPGA’s clock directly reduces input hold
requirements and improves clock to out delay. FPGA clocks
should not be advanced more than the guaranteed mini­mum Output Hold Time (minus any associated clock jitter)
or the outputs may change state before the system clock
edge. For XLA and XV FPGAs the Output Hold Time is
specified as a minimum Clock to Output Delay in the tables
in the respective family Electrical Specification sections.
The maximum recommended clock advance equals this
value minus any clock jitter.

Instantiating I/O elements- Depending on the design
environment, it may be necessary to instantiate the fast I/O
elements. They are found in the libraries as:

• BUFGE (I,O) - The Global Early Buffer

• BUFGLS (I,O)- The Global Low Skew Buffer

• BUFFCLK (I,O) - The FastCLK Buffer

• ILFFX (D, GF, CE, C, Q) - The Fast Capture Latch
Macro

Locating I/O elements - It is necessary to connect these
elements to a particular I/O pad in order to select which
buffer or fast capture latch will be used.

Restricted Clock Loading - Because the input hold
requirement is a function of internal clock delay, it may be
necessary to restrict the routing of BUFGE to IOBs along
the top and bottom of the die to obtain sub-ns clock delays.

BUFGE 1

BUFGE 2

FCLK 3

FCLK 4

BUFGE 5

FCLK 2

FCLK 1

BUFGE 6

BUFGLS 2

Figure 2: Location of FastCLK, BUFGE and BUFGLS
Clock Buffers in XC4000XLA/XV FPGAs

BUFGE1
BUFGE2

BUFGE5
BUFGE6

FCLK1
FCLK2
FCLK3
FCLK4

PLL

Clock

Buffer

O0
O1
O2
O3
O4
O5
O6
O7

FB
Ref

XC4000XLA
XC4000XV

SysClk

Figure 3: Diagram of XC4000XLA/XV FPGA
Connected to PLL Clock Buffer Driving 4 BUFGE and
4 FastCLK Clock Buffers.

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DS015 (v1.3) October 18, 1999 - Product Specification 6-161

XC4000XLA/XV Field Programmable Gate Arrays

6

JTAG Enhancements

XC4000XLA/XV devices have improved JTAG functionality
and performance in the following areas:

• IDCODE - The IDCODE register in JTAG is now
supported. All future Xilinx FPGAs will support the
IDCODE register. By using the IDCODE, the device
connected to the JTAG port can be determined. The
use of the IDCODE enables selective configuration
dependent upon the FPGA found. The IDCODE register
has the following binary format:

vvvv:ffff:fffa:aaaa:aaaa:cccc:cccc:ccc1

Where:
c = the company code;
a = the array dimension in CLBs;
f = the Family code;
v = the die version number

Xilinx company code = 49 (hex)

• Configuration State - The configuration state is
available to JTAG controllers.

• Configure Disable - The JTAG port can be prevented
from reconfiguring the FPGA

• TCK Startup - TCK can now be used to clock the
start-up block in addition to other user clocks.

• CCLK holdoff - Changed the requirement for Boundary
Scan Configure or EXTEST to be issued prior to the
release of INIT pin and CCLK cycling.

• Reissue configure - The Boundary Scan Configure
can be reissued to recover from an unfinished attempt
to configure the device.

• Bypass FF - Bypass FF and IOB is modified to provide
DRCLOCK only during BYPASS for the bypass flip-flop
and during EXTEST or SAMPLE/PRELOAD forthe IOB
register.

XV and XLA Family Differences

The high density of the XC4000XV family FPGAs is
achieved by using advanced 0.25 micron silicon technol­ogy. A 2.5 Voltpower supply (VCCINT) is necessary to pro­vide the reduced supply voltage required by 0.25 micron
internal logic, however to maintain TTL compatibility a 3.3V
power supply (VCCIO) is required by the I/O.

To accommodate the higher gate capacity of XV devices,
additional interconnect has been added. These differences
are detailed below.

• VCCINT (2.5 Volt) Power Supply Pins
The XV family of FPGAs requires a 2.5V power supply
for internal logic, which is named VCCINT. The pins
assigned to the VCCINT supply are named in the pinout
guide forthe XC4000XV FPGAs and in Table 5 on page

162.

• VCCIO (3.3 Volt) Power Supply Pins
Both the XV and XLA FPGAs use a 3.3V power supply
to power the I/O pins. The I/O supply is named VCCIO
in the XV family.

• Octal-Length Interconnect Channels
The XC40110XV, XC40150XV, XC40200XV, and
XC40250XV have enhanced routing. Eight routing
channels of octal length have been added to each CLB
in both vertical and horizontal dimensions.

XLA-to-XL Socket Compatibility

The XC4000XLA devices are generally available in the
same packages as equivalent XL devices, however the
range of packages available for the XC4085XLA has been
extended to include smaller packages such as the HQ240.

XV-to-XL/XLA Socket Compatibility

XC4000XV devices are available in five package options,
pin-grid PG599 and ball-grid BG560, BG432, and BG352
and quad-flatpack HQ240. With the exception of the
VCCINT power pins, XC4000XV FPGAs are compatible
with XL and XLA devices in these packages if the following
guidelines are followed:

• Lay out the PCB for the XV pinout.

• When an XL or XLA device is installed disconnect the
VCCINT (2.5 V) supply.Forthe PG599, VCCINT should
be connected to 3.3V. For BG560, BG432 and BG352
and HQ240 packages, the VCCINT voltage source
should be left unconnected. The unused I/O pins in the
XL/XLA devices connected to VCCINT will be pulled up
to 3.3V. Care must be taken to insure that these pins
are not driven when the XL/XLA device is operative.

• When an XC4000XV is installed, the VCCINT pins must

Family Codes = 01 for XLA;

= 02 for SpartanXL;
= 03 for Virtex;
= 07 for XV.

Table 4: IDCODEs assigned to XC4000XLA/XV FPGAs

FPGA IDCODE

XC4013XLA 0x00218093
XC4020XLA 0x0021c093
XC4028XLA 0x00220093
XC4036XLA 0x00224093
XC4044XLA 0x00228093
XC4052XLA 0x0022c093
XC4062XLA 0x00230093
XC4085XLA 0x00238093
XC40110XV 0x00e40093
XC40150XV 0x00e48093
XC40200XV 0x00e54093
XC40250XV 0x00e5c093