• Complete line of four related Field Programmable Gate
Array product families
- XC3000A, XC3000L, XC3100A, XC3100L
• Ideal for a wide range of custom VLSI design tasks
- Replaces TTL, MSI, and other PLD logic
- Integrates complete sub-systems into a single
package
- Avoids the NRE, t ime del ay, and ris k of conv ent ional
masked gate arrays
• High-performance CMOS static memory technology
- Guaranteed toggle rates of 70 to 370 MHz, logic
delays from 7 to 1.5 ns
- System clock speeds over 85 MHz
- Low quiescent and active power consumption
• Flexible FPGA arch ite ctu re
- Compatible arrays ranging from 1,000 to 7,500 gate
complexity
- Extensive register, combinatorial, and I/O
capabilities
- High fan-out signal distribution, low-skew clock nets
- Internal 3-state bus capabilities
- TTL or CMOS input th resholds
- On-chip crystal oscillator amplifier
• Unlimited reprogrammability
- Easy design iteration
- In-system logic changes
• Extensive packaging options
- Over 20 different packages
- Plastic and ceramic surface-mount and pin-grid-
array packages
- Thin and Very Thin Quad Flat Pack (TQFP and
VQFP) options
• Ready for volume production
- Standard, off-the-shelf product availability
- 100% factory pre-tested devices
- Excellent reliability record
Product Description
• Complete Development System
- Schematic capture, automatic place and route
- Logic and timing simulation
- Interactive design editor for design optimization
- Timing calculator
- Interfaces to popular design environments like
Viewlogic, Cadence, Mentor Graphics, and others
Additional XC3100A Features
• Ultra-high-speed FPGA family with six memb e rs
- 50-85 MHz system clock rates
- 190 to 370 MHz guaranteed flip-flop toggle rates
- 1.55 to 4.1 ns logic delays
• High-end addit ional family member in the 22 X 22 CLB
array-size XC3195A device
• 8 mA output sink cu rr en t an d 8 mA so ur ce cur re nt
• Maximum power-down and quiescent current is 5 mA
• 100% architecture and pin-out compatible with other
XC3000 families
• Software and bitstream compatibl e with the XC3000,
XC3000A, and XC3000L families
XC3100A combines the features of the XC3000A and
XC3100 families:
• Additional interconnect resources for TBUFs and CE
inputs
• Error checking of the configura tion bitstream
• Soft startup holds all outputs slew-rate limited during
initial power-up
• More advanced CMOS process
Low-Voltage Ve r sions Available
• Low-voltage devices function at 3.0 - 3.6 V
• XC3000L - Low-voltage versions of XC3000A devices
• XC3100L - Low-voltage versions of XC3100A devices
7
Device
XC3020A, 3020L, 3120A1,5001,000 - 1,500648 x 8642561614,779
XC3030A, 3030L, 3130A2,0001,500 - 2,00010010 x 10803602022,176
XC3042A, 3042L, 3142A, 3142L3,0002,000 - 3,00014412 x 12964802430,784
XC3064A, 3064L, 3164A4,5003,500 - 4,50022416 x 141206883246,064
XC3090A, 3090L, 3190A, 3190L6,0005,000 - 6,00032016 x 201449284064,160
XC3195A7,5006,500 - 7,50048422 x 221761,3204494,984
Max Logic
Gates
Typical Gate
Range
CLBs Array
User I/Os
Max
Flip-Flops
Horizontal
Longlines
Configuration
Data Bits
November 9, 1998 (Version 3.1)7-3
XC3000 Series Field Programmable Gate Arrays
R
Introduction
XC3000-Series Field Programmable Gate Arrays (FPGAs)
provide a group of high-performance, high-density, digital
integrated circuits. Their regular, extendable, flexible,
user-programmable array architecture is composed of a
configuration program store plus three types of configurable elements: a pe rimeter of I/O Blocks (IO Bs), a core
array of Configurable Logic Bocks (CLBs) and resources
for interconnection. The general structure of an FPGA is
shown in Figure 2. The development system provides
schematic capture and auto place-and-route for design
entry. Logic and timing simulation, and in-circuit emulation
are availabl e as desig n verifi cation alternat ives. Th e design
editor is used for interactive design optimization, and to
compile the data pattern that represents the configuration
program.
The FPGA user logic functions and interconnections are
determined by the configuration program data stored in
internal static memory cells. The program can be loaded in
any of several modes to accommodate various system
requirements. The program data resides externally in an
EEPROM, EPROM or ROM on the application circuit
board, or on a flop py d isk o r har d di sk. O n-ch ip in itia liza tion
logic provides for optional automatic loading of program
data at power-up. The companion XC17XX Serial Configuration PROMs provide a very simple serial configuration
program storage in a one-time programmable package.
The XC3000 Field Prog ramm able Ga te Array familie s provide a variety of logic capacities, package styles, temperature ranges and speed grades.
XC3000 Series Overview
There are now four distinct family groupings within the
XC3000 Series of FPGA devices:
• XC3000A Family
• XC3000L Family
• XC3100A Family
• XC3100L Family
All four families share a common architecture, develop-
ment software, design and programming methodology, and
also common package pin-outs. An extensive Product
Description covers these co mmon aspects.
Detailed parametric information for the XC3000A,
XC3000L, XC3100A, and XC3100L product families is then
provided. (The XC300 0 and XC3100 families are not recommended for new designs.)
Here is a simple overview of those XC3000 products currently emphasized:
• XC3000A Family — The XC3000A is an enhanced
version of the basic XC3000 family, featuring additional
interconnect resources and other user-friendly
enhancements.
• XC3000L Family — The XC3000L is identical in
architecture and features to the XC3000A family, but
operates at a nom inal supply volta ge of 3.3 V. The
XC3000L is the right solution for battery-operated and
low-power applications.
• XC3100A Family — The XC3100A is a
performance-optimized relati ve of the XC3000A fami ly.
While both families are bitstream and footprint
compatible, the XC 3100A fa mily ex tends t oggle rates to
370 MHz and in-system performance to over 80 MHz.
The XC3100A family also offers one additional array
size, the XC3195A.
• XC3100L Family — The XC3100L is identical in
architectures and features to the XC3100A family, but
operates at a nom inal supply voltage of 3.3V.
Figure 1 illustrates the relationships betw een the families.
Compared to the original XC3000 family, XC3000A offers
additional fu nctiona lity and increas ed speed. The XC3000 L
family offers the same additional functionality, but reduced
speed due to its lower supply voltage of 3.3 V. The
XC3100A family offers substantially higher speed and
higher density with the XC3195A.
New XC3000 Series Compared to Original
XC3000 Family
For readers already familiar with the original XC3000 family
of FPGAs, the major new features in the XC3000A,
XC3000L, XC3100A, and XC3100L families are listed in
this section.
All of these new families are upward-compatible extensions
of the original XC3000 FPGA architecture. Any bitstream
used to configure an XC 30 00 d evic e will co nfig ur e th e co r responding XC3000A, XC3000L, XC3100A, or XC3100L
device exactly the same way.
The XC3100A and XC3100L FPGA architectures are
upward-compatible extensions of the XC3000A and
XC3000L architec tures . Any bits tream used to conf igure an
XC3000A or XC3000L device will configure the corresponding XC3100A or XC3100L device exactly the same
way.
7-4November 9, 1998 (Version 3.1)
R
Improvements in the XC3000A and XC3000L
Families
The XC3000A and XC3000L families offer the following
enhancements over the popular XC3000 family:
The XC3000A and XC3000L families have additional interconnect resources to drive the I-inputs of TBUFs driving
horizontal Longlines. The CLB Clock Enable input can be
driven from a secon d vert ical Lon glin e. These two ad dition s
result in more efficient and faster designs when horizontal
Longlines are used for data bussing.
During configuration, the XC3000A and XC3000L devices
check the bit-stream format for stop bits in the appropriate
positions. Any error terminates the configuration and pulls
INIT Low.
When the configuration process is finished and the device
starts up in user mode , the first ac tivation of the outputs is
automatically slew-rate limited. This feature, called Soft
Startup, avoids the potential ground bounce when all
out-puts are turn ed on simultaneously. After start-up, the
slew rate of the indi vidual outputs i s, as in the XC 3000 family, determined by the individu al configuration option.
XC3000 Series Field Programmable Gate Arrays
Functionality
XC3100A
XC3100L
XC3100
XC3000A
XC3000L
Speed
(XC3195A)
Gate Capacity
X7068
Figure 1: XC3000 FPGA Families
Improvements in the XC3100A and XC3100L
Families
Based on a more advanced CMOS process, the XC3100A
and XC3100L families are architecturally- identical, performance-optimized relatives of the XC3000A and XC3000L
families. While all families are footprint compatible, the
XC3100A family extends achievable system performance
beyond 85 MHz.
7
November 9, 1998 (Version 3.1)7-5
XC3000 Series Field Programmable Gate Arrays
Detailed Functional Description
The perimeter of configurable Input/Output Blocks (IOBs)
provides a programmable interface between the internal
logic array and the device package pins. The array of Configurable Log ic Bloc ks (CLBs ) perfo rms user- specif ied log ic
functions. The interconnect resources are programmed to
form networks, carrying logic signals among blocks, analogous to printed circuit board traces connecting MSI/SSI
packages.
The block logic functions are implemented by programmed
look-up table s. Fu nc t iona l op tio ns ar e imp l eme nted b y pro gram-controlled multiplexers. Interconnecting networks
between blocks are implemented with metal segments
joined by program-controlled pass transistors.
These FPGA functions are established by a configuration
program which is loaded into an internal, distributed array
of configuration memory cells. The configuration program
is loaded into the device at power-up and may be reloaded
on command. Th e FPGA includes logic and control signals
to implement automatic or passive configuration. Program
R
data may be either bit serial or byte parallel. The development system generates the configuration program bitstream used to configure the device. The memory loading
process is independent of the user logic functions.
Configuration Memory
The static mem ory cell used for the config uration m emory
in the Field Programmable Gate Array has been designed
specifically for high reliability and n oise immunit y. Integrity
of the device con fi g urat i on me mor y bas ed o n th i s des i gn is
assured even under adverse conditions. As shown in
Figure 3, the basic memory cell consists of two CMOS
inverters pl us a p ass tr ansi stor used for w riti ng a nd rea ding
cell data. The cell is only written during configu ration and
only read during readback. During normal operation, the
cell provides continuous control and the pass transistor is
off and does not affect cell stability. This is quite different
from the operation of conventional memory devices, in
which the cell s are frequently re ad and rewritten.
DN
P11
TCL
KIN
P12
P13
U61
I/O Blocks
P9P8P7P6P5P4P3P2GNDPWR
3-State Buffers With Access
to Horizontal Long Lines
Interconnect Area
BBBA
Configurable Logic
Blocks
Frame Pointer
Configuration Memory
ADACABAA
X3241
Figure 2: Field Programmable Gate Array Structure.
It consists of a perimeter of programmable I/O blocks, a core of config urable logic blocks and their interconnect resources.
These are all controlled by the distributed array of configuration program memory cells.
7-6November 9, 1998 (Version 3.1)
R
Figure 3: Static Configuration Memory Cell.
It is loaded with one bit of configuration program and controls one program selection in the Field Programmable
Gate Array.
Q
Configuration
Control
Read or
Q
Write
Data
X5382
The memory cell outpu ts Q and Q use groun d and VCC levels and provide continuous, direct control. The additional
capacitive load together with the absence of address
decoding and sen se amp lifiers provid e high st ability to the
cell. Due to the structure of the configuration memory cells,
they are not affected by extreme power-supply excursions
or very high levels of alpha particle rad iation. In reliability
XC3000 Series Field Programmable Gate Arrays
testing, no soft errors have been observed even in the
presence of very high doses of alpha radiation.
The method of loading the configuration data is selectable.
Two methods use serial data, while three use byte-wide
data. The intern al configu ration log ic utilizes framin g infor mation, embedded i n the p rogram d ata by the developme nt
system, to direct memory-cell loading. The serial-data
framing and length-count preamble provide programming
compatibility for mixes of various FPGA device devices in a
synchronous, serial, daisy-chain fashion.
I/O Block
Each user-conf igurabl e IOB show n in Figur e 4, prov ides an
interface between the external package pin of the device
and the internal user logic. Each IOB includes both registered and dir ect in put paths. Each I OB pro vides a pr ogrammable 3-state output buffer, which may be driven by a
registered or direct output signal. Configuration options
allow each IOB an inversion, a controlled slew rate and a
high impedance pull-up. Each input circuit also provides
input clamping diodes to provide electrostatic protection,
and circuits to inhibit latch-up produced by input currents.
Vcc
I/O PAD
CK1
CK2
X3029
(OUTPUT ENABLE)
3- STATE
DIRECT IN
REGISTERED IN
OUT
PROGRAM
CONTROLLED
MULTIPLEXER
T
O
I
Q
OUT
INVERT
PROGRAM-CONTROLLED MEMORY CELLS
3-STATE
INVERT
FLIP
FLOP
R
FLIP
FLOP
or
LATCH
R
IKOK
=
PROGRAMMABLE INTERCONNECTION POINT or PIP
OUTPUT
SELECT
QD
DQ
TTL or
CMOS
INPUT
THRESHOLD
SLEW
RATE
OUTPUT
BUFFER
PASSIVE
PULL UP
(GLOBAL RESET)
Figure 4: Input/Output Block.
Each IOB includes input and output storage elements and I/O options selected by configuration memory cells. A choice
of two clocks is available on each die edge. The polarity of each clock line (not each flip-flop or latch) is programmable.
A clock line that triggers the fl ip-flop on the rising edge is an active Low Latch Enable (Latch transparent) signal and vic e
versa. Passive pull-up can only be enabled on inputs, not on outputs. All user inputs are programmed for TTL or CMOS
thresholds.
7
November 9, 1998 (Version 3.1)7-7
XC3000 Series Field Programmable Gate Arrays
R
The input-buffer portion of each IOB provides threshold
detection to translate external signals applied to the package pin to internal logic levels. The global input-buffer
threshold of th e IOBs can be programme d to be compa tible
with either TTL or CMOS lev els. The buffer ed input sign al
drives the data input of a storage element, which may be
configured as either a flip-flop or a latch. The clocking
polarity (rising/falling edge-triggered flip-flop, High/Low
transparent latch) is programmable for each of the two
clock lines on each of the four die edges. Note that a clock
line driving a
rising
edge-triggered f l ip- fl op mak es a ny l a tch
driven by the same line on the same edge Low-level trans-
falling
edge,
High
parent and vice ve rsa (
transparent). All
Xilinx primitives in the supported schematic-entry packages, however, are positive edge-triggered flip-flops or
High transparent latches. When one clock line m ust drive
flip-flops as well as latch es, it is nec essary t o compensa te
for the difference in clocking polarities with an additional
inverter either in the flip-flop clock input or the latch-enable
input. I/O storage elements are reset during configuration
or by the active-Low chip RESET
input. Both direct inp ut
(from IOB pi n I) a nd regi stered input (from IOB p in Q) s ignals are available for interconnect.
For reliable operation, inputs should have transition times
of less than 100 ns and should not be left floati ng. Floating
CMOS input-pin circuits might be at threshold and produce
oscillations. This can p roduce a dditional pow er dissip ation
and system noise. A typical hysteresis of about 300 mV
reduces sensitivity to input noise. Each user IOB includes a
programmable high-impedance pul l-up resistor, which may
be selected by the program to prov ide a cons tant High for
otherwise undriven package pins. Although the Field Programmable Gate Array provides circuitry to provide input
protection for electrostatic discharge, normal CMOS handling precautions should be observed.
Flip-flop loop delay s for the IOB and logic-bloc k flip-flops
are short, providing good performance under asynchronous clock and dat a conditi ons. Shor t loop del ays mini mize
the probability of a metastable condition that can result
from assertion of the clock during data transitions. Because
of the short-loop -de lay charac terist ic in th e Fie ld Pr ogr ammable Gate Ar ray, the IOB flip-flops can be used to synchronize external signals applied to the device. Once
synchronized in the IOB, the signals can be used internal ly
without further consideration of their clock relative timing,
except as it applies to the internal logic and routing-path
delays.
IOB output buffers provide CMOS-compatible 4-mA
source-or-sink drive for high fan-out CMOS or TTL- compatible signal levels (8 mA in the XC3100A family ). The network driving IOB pin O becomes the registered or direct
data source for the output buffer. The 3-state control signal
(IOB) pin T can control output activity. An open-drain output
may be obtained by using the same signal for driving the
output and 3-state signal nets so that the buffer output is
enabled only for a Low.
Configuration program bits for each IOB control features
such as optional output register, logic signal inversion, and
3-state and slew-rate control of the output.
The program-controlled memory cells of Figure 4 control
the following options.
• Logic inversion of the output is controlled by one
configuration program bit per IOB.
• Logic 3-state control of each IOB output buffer is
determined by the states of configuration program bits
that turn the buffer on, or off, or select the output buffer
3-state cont rol interconnection (IOB pin T). When this
IOB output con tr ol s i gn al i s Hi g h, a l og ic o ne, t he buffer
is disabled and the package pin is high impedance.
When this IOB outp ut contr ol signa l is Low, a logic ze ro,
the buffer is enabled and the package pin is active.
Inversion of the buffer 3-state control-logic sense
(output enable) is controlled by an additional
configuration program bit.
• Direct or registered output is selectable for each IOB.
The register uses a posit ive-e dge, clo cked f lip- flo p. The
clock source may be supplied (IOB pin OK) by either of
two metal lines available along each die edge. Each of
these lines is driven by an invertible buffer.
• Increased output transition speed can be selecte d to
improve cri tical timing. Slower transiti ons reduce
capacitive-load peak currents of non-criti cal outputs
and minimize system noise.
• An internal high-impedance pull-up resistor (active by
default) prevents unconnected inputs from floating.
Unlike the original XC3000 series, the XC3000A,
XC3000L, XC3100A, and XC3100L families include the
Soft Startup feature. When the configuration process is finished and the device starts up in user mode, the first activation of the o utputs is automa tically slew-rate lim ited. This
feature avoids potential ground bounce when all outputs
are turned on si multaneously. After start-up, the sle w rate
of the individual outputs is determined by the individual
configuration option.
Summary of I/O Options
• Inputs
-Direct
- Flip-flop/latch
- CMOS/TTL threshold (chip inputs)
- Pull-up resistor/open circuit
• Outputs
- Direct/registered
- Inverted/not
- 3-state/on/off
- Full speed/slew limited
- 3-state/output enable (inverse)
7-8November 9, 1998 (Version 3.1)
R
XC3000 Series Field Programmable Gate Arrays
Configurable Logic Block
The array of CLBs provides the functional elements from
which the user’s logic is constructed. The logic blocks are
arranged in a matrix within the perimeter of IOBs. For
example, the XC3020A has 64 such blocks arranged in 8
rows and 8 colu mns. The deve lopment system is used to
compile the confi guration data which is to be loaded into
the internal configuration memory to define the operation
and interconnection of each block. User definition of CLBs
and their interconnecting networks may be done by automatic transla tion from a sche matic-c apture logi c diagram or
optionally by installing library or user macros.
Each CLB has a combina torial logic se ction, two flip -flops,
and an internal control section. See Figure 5. There are:
five logic inputs (A, B, C, D and E); a common clock input
(K); an asynchronous direct RESET input (RD); and an
enable clock (EC). All may be driven from the interconnect
DATA IN
LOGIC
VARIABLES
DI
QX
A
B
C
D
E
COMBINATORIAL
FUNCTION
QY
F
G
resources adjacent to the blocks. Each CLB also has two
outputs (X and Y) which may drive i nterconnect networks.
Data input for either flip -flop within a CLB is su pplied from
the function F or G outp uts of th e combin atorial logic, or the
block input, DI. Both flip-flops in each CLB share the asynchronous RD which, when enabled and High, is dominant
over clocked inputs. All flip-flops are reset by the
active-Low chip input, RESET
, or during the configuration
process. The flip-flops share the enable clock (EC) which,
when Low, recirculates the flip-flops’ present states and
inhibits response to the data-in or combinatorial function
inputs on a CLB. The user may enable these control inputs
and select their sources. The user may also select the
clock net input (K), as well as its active sense within each
CLB. This programmable inversion eliminates the need to
route both phases of a clock signal throughout the device.
0
F
DIN
G
F
DIN
G
MUX
1
0
MUX
1
Q
D
RD
QD
QX
F
G
QY
X
CLB OUTPUTS
Y
7
ENABLE CLOCK
CLOCK
DIRECT
RESET
EC
1 (ENABLE)
K
RD
0 (INHIBIT)
(GLOBAL RESET)
RD
X3032
Figure 5: Configurable Logic Block.
Each CLB includes a co m bi nato ria l logic section, two flip-flo ps an d a p rogr am me m o ry co nt ro lled mu ltip lex er se lectio n of
function. It has the following:
- five logic variable inputs A, B, C, D, and E
- a direct data in DI
- an enable clock E C
- a clock (invertible) K
- an asynchronous direct RESET RD
- two outputs X and Y
November 9, 1998 (Version 3.1)7-9
XC3000 Series Field Programmable Gate Arrays
Flexible routing allows use of common or individual CLB
clocking.
The combinatorial-logic portion of the CLB uses a 32 by 1
look-up table to implement Boolean functions. Variables
selected from the five logic inputs and two internal block
flip-flops are used as ta ble address inputs. The combinatorial propagation delay through the network is independent
of the logic funct ion generated and is spike fre e for single
input variable changes. This technique can generate two
independent logic functions of up to four variables each as
shown in Figure 6a, or a single function of five variab les as
shown in Figure 6b , or some function s of seven variab les
as shown in Figu re 6c. Figure 7 shows a modulo-8 binary
counter with paralle l en abl e. It us es one CL B of ea ch typ e.
The partial functio ns of six or seven variables are implemented using the input variable (E) to dynamically select
between two functions of four different variables. For the
two functions of four variables each, the independent
results (F and G) may be used as data inputs to either
flip-flop or either logic block output. For the single function
of five variables and merged functions of six or seven variables, the F and G out put s are ide nti cal. Symmetr y of t he F
and G functions and the flip-flops allows the interchange of
CLB outputs to optimiz e routing eff icienc ies of th e networ ks
interconnecting the CLBs and IOBs.
Programmable Interconnect
Programmable-interconnection resources in the Field Programmable Gate Array provide routing paths to connect
inputs and outputs of the IOBs and CLBs into logic networks. Inter connect ions between b locks are com posed o f a
two-layer grid of metal segments. Specially designed pass
transistors, each controlled by a configuration bit, form programmable interconnect points (PIPs) and switching matrices used to impl ement the n ecess ary connec tions be tween
selected metal segments and block pins. Figure 8 is an
example of a routed ne t. The develop ment system pr ovides
automatic routing of these interconnections. Interactive
routing is al so available for d esign optimization. The inputs
of the CLBs or IOBs are multiplexers which can be programmed to select an input network from the adjacent
interconnect segments.
block inputs are unidirectional, as are block outputs,
they are usabl e only for block input connect ion and n ot
for routing.
Figure 9 illustrates routing access to logic
block input variables, control inputs and block outputs.
Three types of met al reso urce s ar e pr ovide d to acco mmodate various network interconnect requirements.
• General Purpose Interconnect
• Direct Connection
• Longlines (multiplexed busses and wide AND gates)
Since the switch connections to
A
B
QX
QY
C
D
E
A
B
QX
QY
C
D
E
A
B
QX
QY
C
D
E
A
B
QX
QY
C
D
A
B
QX
QY
C
D
E
Any Function
of Up to 4
Variables
Any Function
of Up to 4
Variables
Any Function
of 5 Variables
Any Function
of Up to 4
Variables
Any Function
of Up to 4
Variables
F
G
5a
F
G
5b
F
M
U
X
G
FGM
5c
Mode
X5442
Figure 6: Combinationa l Logic Options
6a. Combinatorial Logic Option FG generates two func-
tions of four variables each. One variable, A, must be
common to bot h func t i ons. Th e se cond a nd t hir d v ar i ab le
can be any choice of B, C, QX and QY. The fourth variable can be any choice of D or E.
6b. Combinatorial Logic Option F generates any function
of five vari ables : A, D, E and two choi ces o ut of B, C, QX,
QY.
6c. Combinatorial Logic Option FGM allows variable E to
select betwee n tw o fun ction s of four vari ables : Bot h hav e
common inputs A and D and any choice out of B, C, QX
and QY for the remaining two variables. Option 3 can
then implemen t som e f unc t ion s o f s i x or se ve n v ar i able s.
R
7-10November 9, 1998 (Version 3.1)
R
Figure 7: Counter.
The modulo-8 binary counter with parallel enable and
clock enable uses one combinatorial logic block of each
option.
XC3000 Series Field Programmable Gate Arrays
Count Enable
Parallel Enable
Clock
Dual Function of 4 Variables
D0
D1
Function of 5 Variables
D2
Function of 6 Variables
D Q
D Q
D Q
Terminal
Count
Q0
FG
Mode
Q1
F
Mode
Q2
FGM
Mode
X5383
General Purpose Interconnect
General purpo se int er c onn ect, a s s ho wn i n Fig ur e 10 , con sists of a grid of five horizontal and five vertical metal segments located between the rows and columns of logic and
IOBs. Each segment is the height or width of a logic block.
Switching matrices join the ends of these segments and
allow progra mmed inte rconnect ions b etween t he meta l grid
segments of ad joining ro ws and co lumns. T he swit ches of
an unprogrammed device are all non-conducting. The connections through the switch matrix may be established by
the automatic routing or by selecting the desired pairs of
matrix pins to be connected or disconnected. The legitimate switching matrix combinations for each pin are indicated in Figure 11.
Special buffers within th e general intercon nect areas provide periodic signal isolation and restoration for improved
performance of lengthy nets. The interconnect buffers are
available to pro pagat e s ign al s in ei ther di re cti o n on a giv en
general interconnect segment. These bidirectional (bidi)
buffers a re fou nd adj acent to the switc hing ma tri ces, ab ove
Figure 8: A Design Editor vi ew of rout ing reso urces
used to form a typical interconnection network from
CLB GA.
and to the right. The other PIPs adjacent to the matrices
are accessed to or from Longlines. The development system automatically defines the buffer direction based on the
location of the inte rconnection networ k source. The delay
calculator of the development system automatically calculates and dis pla ys the blo ck, i nte rcon nect a nd buf f er d ela ys
for any paths selected. Generation of the simulation netlist
with a worst-case delay model is provided.
Direct Interconnect
Direct interconn ect, sh own in Figure 12, provides the most
efficient implementation of networks between adjacent
CLBs or I/O Blocks. Signals routed from block to block
using the dir ect in terc onne ct ex hibit mini mum int erconn ect
propagation and use no general interconnect resources.
For each CLB, the X output may be connected directly to
the B input of the CLB immediately to its right and to the C
input of th e CLB to its l eft. The Y out put ca n use di rect i nterconnect to driv e the D input of t he bloc k immed iat ely abo ve
and the A input of the block below. Direct interconnect
should be used to maxi mize the speed of high-perf ormance
portions of logic. Where logic blocks are adjacent to IOBs,
direct connect is provided alternately to the IOB inputs (I)
and outputs (O) on all four edges of the die. The right edge
provides additional direct connects from CLB outputs to
adjacent IOBs. Direc t interconnections of IOBs with CLBs
are shown in Figure 13.
7
November 9, 1998 (Version 3.1)7-11
XC3000 Series Field Programmable Gate Arrays
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Figure 9: Design Edito r Loca tio ns of i nte rconnec t ac cess , CLB c ont rol i nputs, log ic i nputs and outp uts. Th e dot patt ern
represents th e available programmable interconnection points (PIPs).
Some of the interc onnect PIPs are directional.
7-12November 9, 1998 (Version 3.1)
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Figure 10: FPGA General-Purpo se Interconnect.
Composed of a grid of metal segments that may be interconnected throug h switch matrices to form networks for
CLB and IOB inputs and outputs.
Figure 1 1: Swi tch Ma trix Int erconne ctio n Opti ons for
Each Pin.
Switch matrices on the edges are different.
XC3000 Series Field Programmable Gate Arrays
Figure 12: CLB X and Y Outputs.
The X and Y outputs of each CLB have single contact,
direct access to inputs of adjacent CLBs
7
November 9, 1998 (Version 3.1)7-13
XC3000 Series Field Programmable Gate Arrays
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Global Buffer Direct Input
Global Buffer Inerconnect
* Unbonded IOBs (6 Places)
Figure 13: XC3020A Die-Edge IOBs. The XC3020A die-edge IOB s are provided with direct access to adjacent CLBs.
7-14November 9, 1998 (Version 3.1)
Alternate Buffer Direct Input
R
XC3000 Series Field Programmable Gate Arrays
Longlines
The Longlines bypass the swi tch mat rices and are intend ed
primarily for signals that must travel a long distance, or
must have minimum skew among multiple destinations.
Longlines, shown in Figure 14, run vertically and horizo ntally the heig ht or width of the interco nnect area . Each inter connection column has three vertical Longlines, and each
interconnection row has two horizontal Longlines. Two
additional Longlines are located adjacent to the outer sets
of switching matrices. In devices larger than the XC3020A
and XC3120A FPGAs , two vertical Longlines in ea ch col-
umn are connectable half-length lines. On the XC3020A
and XC3120A FPGAs, only the outer Longlines are connectable half-length lines.
Longlines can be dri ve n b y a l og ic blo ck or IOB o utpu t on a
column-by-column bas is. This capability provides a common low skew contro l or clock line within each colu mn of
logic blocks. Interconnections of these Longlines are
shown in Figure 15. Isolation buffers are provided at each
input to a Longline and are enabled automatically by the
development sy stem when a connection is made.
7
Figure 14: Horizontal and Vertical Longlines. These Longlines provide high fan-out, low-skew signal distribution in
each row and column. The global buffer in the upper left die corner drives a common line throughout the FPGA.
November 9, 1998 (Version 3.1)7-15
XC3000 Series Field Programmable Gate Arrays
R
Figure 15: Programmable Interconnection of Longlines. T h is is provided at the edges of the routing area.
Three-state b uf f er s al low t he use of ho riz on ta l Lo ng l ines t o fo rm on- chi p wir ed AND a nd mult ip le xe d b us es. The l eft t wo
non-clock vertical Longlines per column (except XC3020A) and the outer perimeter Longlines may be programmed as
connectable half-length lines.
VCC
Z
= DA • DB • DC • ... • DN
(LOW)
D
A
D
B
D
C
D
N
VCC
X3036
Figure 16: 3-State Buffers Implement a Wired-AND Function. When all the buffer 3-state lines are High, (high
impedance), the pull-up resistor(s) provide the High output. The buffer inputs are dr iven by the control signals or a Low.
WEAK
KEEPER CIRCUIT
DAA•+=D
D
A
A
D
B
B
B•+DCC•+ DNN•Z…+
B
D
C
C
D
N
N
X1741A
Figure 17: 3-State Buffers Implement a Multiplexer. The selection is ac complished by the buffer 3-state signal.
7-16November 9, 1998 (Version 3.1)
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XC3000 Series Field Programmable Gate Arrays
A buffer in the upper left corner of the FPGA chip drives a
global net which is av ailable to all K inputs of logic bloc ks.
Using the global buffer for a clock signal provides a
skew-free, high fan-out, synchronized clock for use at any
or all of the IOBs and CLBs. Configuration bits for the K
input to each logic block can select this global line or
another routing resource as the clock source for its
flip-flops. This net may also be pr ogrammed to drive the die
edge clock lines for IOB use. An enhanced speed, CMOS
threshold, di rect acces s to thi s buffer is avail able at the s econd pad from the top of the left die edg e.
A buffer in the lower right corner of the array drives a horizontal Longline that can drive programmed connections to
a vertical Longline in each interconnection column. This
alternate buffer also has low skew and high fan-out. The
network formed by this alternate buffer’s Longlines can be
selected to drive th e K inputs of the CLBs. CMOS t hreshold, high speed access to this buffer is available from the
third pad from the bottom of the right die edge.
Internal Busses
A pair of 3- state buf fer s, lo cated a djacent to each CLB, permits logic to drive the horizontal Longlines. Logic operation
BIDIRECTIONAL
INTERCONNECT
BUFFERS
GG
GLOBAL NET
GH
of the 3-stat e buf fer c ontrols allows them t o implem ent wid e
multiplexing functions. Any 3-state buffer input can be
selected as drive for the horizontal long-line bus by applying a Low logic level on its 3-state control line. See
Figure 16. The user is required to avoid contention which
can result from multiple driv ers with op posing logic levels.
Control of the 3-state input by the same signal that drives
the buffer input , cr eate s an open -drai n wi red-AN D func tio n.
A logic High on both buffer inputs creates a high impedance, which rep res en t s n o co nten ti o n. A l ogic Lo w e nab les
the buffer t o dr iv e t he Lon gl in e Lo w. See Fig ur e 17 . Pull-up
resistors are available at each end of the Longline to provide a High output when all connected buffers are non-conducting. This forms fast, wide gating functions. When data
drives the inputs, and separate signals drive the 3-state
control lines, these buffers form multiplexers (3-state busses). In this case, care must be used to prevent contention
through multiple active buffers of conflicting levels on a
common line. Each horizontal Longline is also driven by a
weak keeper circuit that prevents undefined floating levels
by maintaining the p revio us log ic level wh en th e line is not
driven by an active buffer or a pull-up resistor. Figure18
shows 3-state buffers, Longlines and pull-up resistors.
3 VERTICAL LONG
LINES PER COLUMN
I/O CLOCKS
P48
HORIZONTAL LONG LINE
PULL-UP RESISTOR
7
P47
BCL
HG
P40P41P42P43RST
HH
OS
C
KIN
P46
.l
.lk
.q
.ck
.Q
D
P
G
M
Figure 18: Design Editor.
An extra large view of possible interconnections in the lower right corner of the XC3020A.
HORIZONTAL LONG LINE
OSCILLATOR
AMPLIFIER OUTPUT
DIRECTINPUT OF P47
TO AUXILIARY BUFFER
CRYSTAL OSCILLATOR
BUFFER
3-STATE INPUT
3-STATE CONTROL
3-STATE BUFFER
ALTERNATE BUFFER
X1245
November 9, 1998 (Version 3.1)7-17
XC3000 Series Field Programmable Gate Arrays
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Crystal Oscillator
Figure 18 also sh ows th e l o ca tio n o f an in ter nal hi gh spe ed
inverting amplifier that may be used to implement an
on-chip crystal o scillator. It is associated with the au xiliary
buffer in the lower right corner of the die. When the oscillator is configured and connected as a signal source, two
special user IOBs are also configured to connect the oscillator amplifier w ith external crystal oscillator c omponents
as shown in Figure 19. A divide by two option is available to
assure symmetry. The oscillator circuit becomes active
early in the configu ration process to allow the oscillat or to
stabilize. Actual internal co nnection is delayed until completion of configuration. In Figure 19 the feedback resistor
R1, between the output and input, biases the amplifier at
threshold. The in version of th e amplifier, together with the
R-C networks and an AT-cut series resonant crystal, produce the 360-degre e phase s hift of the Pierce os cillator. A
D Q
series resistor R2 may be included to add to the amplifier
output impedance when needed for phase-shift control,
crystal resistance m atching, or to limit the amplifier input
swing to control clipping at large amplitudes. Excess feedback voltage may be corrected by the ratio of C2/C1. The
amplifier is designed to be used from 1 MHz to about
one-half the specified CLB toggle frequency. Use at frequencies below 1 MHz may require individual characterization with res pect to a ser ies resistance . Crystal osc illators
above 20 MHz general ly require a c rystal which oper ates in
a third overtone mode, where the fundamental frequency
must be suppressed by an inductor across C2, turning this
parallel resonant circuit to double the fundamental crystal
frequency, i.e., 2/3 of the desired third harmonic frequency
network. When the oscillator inverter is not used, these
IOBs and their package pins are available for general user
I/O.
InternalExternal
Suggested Component Values
R1
0.5 – 1 MΩ
R2
0 – 1 kΩ
(may be required for low frequency, phase
Figure 19: Crystal Oscillator Inverter. When acti vated, and by selecting an output network for its bu ffer, the cryst a l
oscillator inverter uses two unconfigured package pins and external components to implement an oscillator. An optional
divide-by-two mode is available to assure symmetry.
7-18November 9, 1998 (Version 3.1)
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XC3000 Series Field Programmable Gate Arrays
Configuration
Initialization Phase
An internal power-on-reset circuit is triggered when power
is applied. Wh en V
of the FPGA device begin to operate (nominally 2.5 to 3 V),
the programmable I/O output buffers are 3-stated and a
high-impedance pull-up resistor is provided for the user
I/O pins. A time-out delay is initiated to allow the power
supply voltage to stabiliz e. During th is time the powe r-down
mode is inhibi t ed. Th e I n iti a li zati o n st at e t ime -o ut (abo ut 11
to 33 ms) is determined by a 14-bit counter driven by a
self-generated internal timer. This nominal 1-MHz timer is
subject to variations with process, temperature and power
supply. As shown in Table 1, five configuration mode
choices are available as determined by the input levels of
three mode pins; M0, M1 an d M 2.
Table 1: Configuration Mode Choices
M0 M1 M2 CCLKModeData
000 outputMasterBit Serial
001 outputMasterByte Wide Addr. = 0000 up
010—reserved—
011 outputMas te rByte Wide Addr. = FFFF down
100 —reserved—
101 outputPeripheral Byte Wide
110 —reserved—
111 i nputSlaveBit Serial
reaches the voltage at which portions
CC
In Master configuration modes, the device becomes the
source of the Configuration Clock (CCLK). The beginning
of configuration of devices using Peripheral or Slave
modes must be delayed long enough for their initialization
to be completed. An FPGA with mode lines selecting a
Master configuration mode extends its initialization state
using four times the delay (43 to 130 ms) to assure that all
daisy-chained slave devices, which it may b e driving, will
be ready even if the master is very fast, and the slave(s)
very slow . Figu re 20 shows the state sequ ences. At th e end
of Initialization, the device enters the Clear state where it
clears the configuration memory. The active Low,
open-drain initialization signal INIT
indicates when the Initialization and Clear states are complete. The FPGA tests
for the absence of an external active Low RESET
before it
makes a final sample of the mode lines and enters the Configuration s tat e. An ext erna l wir ed- AND of one or more INIT
pins can be used to co ntrol confi guration by the asserti on of
the active-Low RESET
of a master mode device or to sig-
nal a processor that the FPG A s ar e no t yet initia lized .
If a configuration has begun, a re-assertion of RESET
for a
minimum of three in ternal timer cycles will be r ecognized
and the FPGA will initiate an ab ort, returning to the Clear
state to clear the partially loaded configuration memory
words. The FPGA will then resample RESET
and the mode
lines before re-ent er in g the C on fig ur at ion stat e.
During configuration, the XC3000A, XC3000L, XC3100A,
and XC3100L devices check the bit-stream format for stop
bits in the appropr iate positions. Any erro r terminates the
configuration and pulls INIT Low.
7
All User I/O Pins 3-Stated with High Impedance Pull-Up, HDC=High, LDC=Low
INIT Output = Low
Initialization
Power-On
Time Delay
Clear
Configuration
Memory
Power-On Delay is
14
2
Cycles for Non-Master Mode—11 to 33 ms
16
2
Cycles for Master Mode—43 to 130 ms
RESET
Active
Active RESET
Test
Mode Pins
No
Low on DONE/PROGRAM and RESET
Configuration
Program Mode
Clear Is
~ 200 Cycles for the XC3020A—130 to 400 µs
~ 250 Cycles for the XC3030A—165 to 500 µs
~ 290 Cycles for the XC3042A—195 to 580 µs
~ 330 Cycles for the XC3064A—220 to 660 µs
~ 375 Cycles for the XC3090A—250 to 750 µs
PWRDWN
Inactive
Start-Up
Figure 20: A State Diagram of the Configuration Process for Power-up and Reprogram.
Power Down
No HDC, LDC
or Pull-Up
PWRDWN
Active
Operational
Mode
Active RESET
Operates on
User Logic
X3399
November 9, 1998 (Version 3.1)7-19
XC3000 Series Field Programmable Gate Arrays
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A re-program is initiated.when a configured XC3000 series
device senses a Hig h- to -L ow trans i t ion a nd s ub seque nt >6
µs Low level on the DONE/PROG
package p in, or, if this
pin is externa ll y hel d p er man entl y Low, a High-to-Low transition and subse quent >6 µs Low time on the RESET
pack-
age pin.
The device returns to the Clear state where the configura-
tion memory is cleared and mode lines re-sampled, as for
an aborted configuration. The complete configuration program is cleared and loaded during each configuration program cycle.
Length count cont ro l allo ws a syst em of mu ltip le Fi el d Pr ogrammable Gate Arrays, of assorted size s, to begin operation in a synchronized fashion. The configuration program
For XC3120
197 Configuration Data Frames
(Each Frame Consists of:
A Start Bit (0)
A 71-Bit Data Field
Three Stop Bits
Postamble Code (4 Bits Minimum)
generated by the development system begins with a prea mb le of 111111110 0 10 fo ll ow e d b y a 24 - bi t l en gt h co un t
representing the total number of configuration clocks
needed to complete loading of the configuration program(s). The data framing is shown in Figure 21. All
FPGAs connec ted in series read and shift preamble and
length count in on positive and o ut on negati ve configuration clock edges. A device which has received the preamble and length count then presents a High Data Out until it
has intercepted the appropriate number of data frames.
When the configuration program memory of an FPGA is full
and the length count does not yet compare, the device
shifts any additional data through, as it did for preamble
and length count. When the FPGA configuration memory is
full and the length coun t com pa re s, the de vice will ex ecute
Header
Program Data
Repeated for Each Logic
Cell Array in a Daisy Chain
X5300_01
XC3020A
Device
Gates1,000 to 1,500 1,500 to 2,000 2,000 to 3,000 3,500 to 4,500 5,000 to 6,000 6,500 to 7,500
CLBs64100144224320484
Row x Col(8 x 8)(10 x 10)(12 x 12)(16 x 14)(20 x 16) (22 x 22)
IOBs648096120144 176
Flip-flops2563604806889281,320
Horizontal Longlines162024324044
TBUFs/Horizontal LL911131517 23
Bits per Frame
(including1 start and 3 st op bits)
Frames197241285329373 505
Program Data =
Bits x Frames + 4 bits
(excludes header)
PROM size (bits) =
Program Data
+ 40-bit Header
XC3020L
XC3120A
7592108140172188
14,77922,17630,78446,06464,16094,944
14,81922,21630,82446,10464,20094,984
XC3030A
XC3030L
XC3130A
XC3042A
XC3042L
XC3142A
XC3142L
XC3064A
XC3064L
XC3164A
XC3090A
XC3090L
XC3190A
XC3190LXC3195A
Figure 21: Internal Configuration Data Structure for an FPGA. This shows the preamble, length count and data
frames generat ed by the Development Sy stem.
The Length Count produced by the program = [(40-bit preamble + sum of program data + 1 per daisy chain device)
rounded up to multiple of 8] – (2 ≤ K ≤ 4) where K is a function of DONE and RESET timing selected. An additional 8 is
added if roundup increment is less than K. K additional clocks are needed to complete start-up after length count is
reached.
7-20November 9, 1998 (Version 3.1)
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XC3000 Series Field Programmable Gate Arrays
a synchronou s start -up s eque nce a nd become opera tio nal .
See Figure 22. Two CCLK cycles after the completion of
loading configuration data, the user I/O pins are enabled as
configured. As selected, the internal user-logic RESET is
released either one clock cycle before or after the I/O pins
become active. A sim ilar t iming selec tion is prog ramm able
for the DONE/PROG
output sig nal. DO NE/P ROG may also
be programmed to be an open drain or include a pull-u p
resistor to accom modate wired ANDing. T he High During
Configuration (HDC) and Low Durin g Configuration ( LDC
are two user I/O pins which are driven active while an
FPGA is in its Initialization, Clear or Configure states. They
and DONE/PROG
provide signals for control of external
logic signals such as RESET, bus enable or PROM enable
during configuration. For parallel Master configuration
modes, these signals provide PROM enable control and
allow the data pins to be shared with user logic signals.
User I/O inputs can be programmed to be either TTL or
CMOS compatible thresholds. At power-up, all inputs have
TTL thresholds and ca n change to CMOS t hres holds at the
completion of configuration if the user has selected CMOS
thresholds. The thr eshold of PWRDWN
and the direct cloc k
inputs are fixed at a CMOS level.
If the crystal oscillator is used, it will begin operation before
configuration is complete to allow time for stabilization
before it is connected to the internal circuitry.
12244
Data Frame
Configuration Data
Configuration data to define the function and interconnection within a Field Programm able Gate Ar ray is load ed from
an external st orage at power-up and aft er a re- program si gnal. Several metho ds of automat ic and contr olled loadin g of
the required data are available. Logic levels applied to
mode selection pins at the start of configuration time determine the method t o be used . See Table 1. The dat a may be
either bit-serial or byte-parallel, depending on the configu-
)
ration mode. The different FPGAs have different sizes and
numbers of data frames. To maintain compatibility between
various device type s, the Xilinx product familie s use compatible configuration formats. For the XC3020A, configuration requires 14779 bits for each device, arranged in 197
data frames. An additional 40 bits are used in the header.
See Figure22. The specific data format for each device is
produced by the development system and o ne or more of
these files can then be comb ine d and appen ded t o a lengt h
count preamble and be transformed into a PROM format
file by the developmen t system. A compatibility excep tion
precludes the use of an XC2000-series device as the master for XC3000-series devices if their DONE or RESET are
programmed to occur after their outputs become active.
The Tie Option defines ou tput leve ls of un use d block s of a
design and connects these to unused routing resources.
This prevents indeterminate levels that might produce parasitic supply currents. If unused bloc ks are not suffici ent to
complete the tie, the user can indicate net s which must not
Last Frame
3
Postamble
3
STOP
4
7
DIN
PreambleLength CountData
The configuration data consists of a composite
*
40-bit preamble/length count, followed by one or
more concatenated FPGA programs, separated by
4-bit postambles. An additional final postamble bit
is added for each slave device and the result rounded
up to a byte boundary. The length count is two less
than the number of resulting bits.
Timing of the assertion of DONE and
termination of the INTERNAL RESET
may each be programmed to occur
one cycle before or after the I/O outputs
become active.
Heavy lines indicate the default condition
Start
Bit
Stop
Start
Bit
Length Count*
Weak Pull-Up
PROGRAM
Internal Reset
I/O Active
DONE
X5988
Figure 22: Configurat ion and Start-up of One or More FPGAs.
November 9, 1998 (Version 3.1)7-21
XC3000 Series Field Programmable Gate Arrays
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be used to drive the remaining unused routing, as that
might affect timing of user nets. Tie can be omitted for quick
breadboard iterat ions where a few additional millia mps of
Icc are acceptable.
The configuration bitstream begins with eight High preamble bits, a 4-bit preamble code and a 24-bit length count.
When configuration is initiated, a counter in the FPGA is set
to zero and begins to count the total number of configuration clock cycles ap plied to th e device . As each configur ation data frame is supplied to the device, it is internally
assembled into a data word, which is then loaded in parallel
into one word of th e internal configuration memory array.
The configuration loading process is complete when the
current le ngth cou nt equ als the load ed len gth coun t and the
required configuration program data frames have been
written. In tern al user f lip -flo ps a re he ld Re set during con fig uration.
Two user-programma ble pins are defined in th e unconfigured Field Progra mmab le Gate Ar ray. High During Configuration (HDC) and Low During Configuration (LDC
as DONE/PROG
during configuration. In Master mode configurations it is
convenient to use LDC
Enable. After the last configuration data bit is loaded and
the length count compares, the user I/O pins become
active. Options allow tim ing choices o f one clock e arlier or
later for the timing of the end of the internal logic RESET
and the assertion of the DONE signal. The open-drain
DONE/PROG
and used as an active -H igh REA DY, an active-Low PROM
enable or a RESET to other portions of the system. The
state diagram of Figure 20 illustrates the configuration process.
may be used as external control signals
as an active-Low EPROM Chip
output can be AND-tied with multiple devices
) as well
Configuration Modes
Master Mode
In Master mode, the FPGA automatically loads configuration data from an external memory device. There are three
Master modes that use the internal timing source to supply
the configuration clock (CCLK) to time the incoming data.
Master Serial mode uses serial configu r ation data supplied
to Data-in (DIN) from a synch ron ous se rial so urce such as
the Xilinx Serial Configurat ion PROM shown in Figure 23.
Master Parallel Low and High modes automatically use
parallel data supplied to the D0–D7 pins in response to the
16-bit address generated by the FPGA. Figure 25 shows
an example of the parallel Master mode connections
required. T he HEX s tarting addres s is 0 000 and increme nts
for Master Low mode and it is FFFF and decrements for
Master High mode. These two modes provide address
compatibility with microp rocessors which begin execution
from opposite ends of memory.
Peripheral Mode
Peripheral mode provides a simplified interface through
which the device may be loaded byte-wide, as a processor
peripheral. Figure 27 shows the peripheral mode connections. Processor write cycles are decoded from the common assertion of the active low Write Strobe (WS
active low and one active high Chip Selects (CS0
CS2). The FPGA generates a configuration clock from the
internal timing generator and serializes the parallel input
data for internal framing or for succeeding slaves on Data
Out (DOUT). A output High on READY/BUSY
the completion of loading for each byte when the input register is read y for a n ew byte. As with Master modes, P eripheral mode may also be used as a lead device for a
daisy-chain of slave devices.
), and two
, CS1,
pin indicates
Slave Serial Mode
Slave Serial mode provides a simple interface for loading
the Field Programmable Gate Array configuration as
shown in Figure29. Serial data is supplied in conjunction
with a synch ron izi n g inpu t c loc k. M ost S lav e m ode a ppli c ations are in daisy-chain configurations in which the data
input is driven from the p revi ous FP GA’s data out, whil e th e
clock is supplied by a lead device in Master or Peripheral
mode. Data may also be supplied by a processor or other
special circuits.
Daisy Chain
The development system is used to create a composite
configuration for selected FPGAs including: a preamble, a
length count for th e total bitstream, multiple concatena ted
data programs and a postamble plus an ad ditional fill bit
per device in the serial chain. After loading and passing-on
the preamble and length count to a possible daisy-chain, a
lead device will load its configuration data frames while providing a High DOUT to possible down-stream devices as
shown in Figure 25. Loading continues while the lead
device has received its configuration program and the current length count has not reached the full value. The additional data is passed through the lead device and appears
on the Data Out ( DOU T) p in i n s er ial f or m. T he le ad d ev i ce
also generates th e Conf igura tio n Clock (C CLK) t o sync hronize the serial output data and data in of down-stream
FPGAs. Data is r ead in on DIN of sla ve devi ces by the po sitive edge of CCLK and shifted out the DOUT on the negative edge of CC LK. A p aralle l M as te r mo de d ev ice use s its
internal timing generator to produce an internal CCLK of 8
times its EPROM address rate, while a Peripheral mode
device produc es a burst of 8 CCLKs for ea ch chip select
and write-strobe cycle. The internal timing generator continues to operate for general timing and synchronization of
inputs in all modes.
7-22November 9, 1998 (Version 3.1)
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XC3000 Series Field Programmable Gate Arrays
Special Configuration Functions
The configuration data includes control over several special functions in addition to the normal user logic functions
and interconnect.
• Input thresholds
• Readback disabl e
• DONE pull-up resistor
•DONE timing
• RESET timing
• Oscillator frequen cy div ide d by two
Each of these functions is controlled by configuration data
bits which are selected as part of the normal development
system bitstream generation process.
Input Thresholds
Prior to the completion of configuration all FPGA input
thresholds a re TTL compatible. Upon completion of configuration, the input thresholds become either TTL or CMOS
compatible as programmed. The use of the TTL threshold
option requires some additional supply current for threshold shifting. The exception is the threshold of the
PWRDWN
CMOS input. Prior to the completion of configuration the
user I/O pins each have a high impedance pull-up. The
configuration program can be used to enable the IOB
pull-up resi stors in t he Op erat ional mode to a ct ei ther a s an
input load or to avoid a floating input on an otherwise
unused pin.
Readback
The contents of a Fi eld Progr amm able Gat e Arr ay ma y be
read back if it has been programmed with a bitstream in
which the Readback option has been enabled. Readback
may be used for verification of configuration and as a
method of deter mining the st ate of inte rnal logic nodes during debugging. There are three options in generating the
configuration bitstr ea m .
• “Never” inhibits the Read ba ck capa bility.
• “One-time, ” inhibits Readba ck after one Readback has
been executed to verify the configuration.
• “On-command ” allo ws unr es tric te d us e of Re ad ba ck .
Readback is ac complished without the use of any of the
user I/O pins; only M0, M1 and CCLK are used. The initiation of Readb ac k is pr odu c ed by a Lo w to Hi gh tr an sit i on o f
the M0/RTRIG (Read Trigger) pin. The CCLK input must
then be driven by ex t er nal l og ic t o re ad ba ck t he c onf ig ura tion data. The first three Low-to-High CCLK transitions
clock out dummy da ta. Th e subs equen t Low-t o-Hi gh CCLK
transitions shift the data frame information out on the
M1/RDATA
always inverted, a z ero in config uration be comes a one in
Readback, and vice ver sa. Note also that eac h Readback
frame has one Start bit (read back as a one) but, unlike in
input and direct clocks which always have a
(Read Data) pin. No te that the logic polarity is
configuration, each Readback frame has only one Stop bit
(read back as a zero). The third leading dummy bit mentioned above can be considered the Start bit of the first
frame. All data fr ames mus t be read ba ck to comp lete the
process and retu rn the Mode Sel ect and CCL K pins to thei r
normal functions.
Readback data includes the current state of each CLB
flip-flop, each input flip-flop or latch, and each device pad.
These data are imbedded into unused configuration bit
positions during Readback. This state information is used
by the development system In-Circuit Verifier to provide
visibility into the internal operation of the logic while the
system is operating. To readback a uniform time-sample of
all storage el ements , it may be nec essar y to in hibit the s ystem clock.
Reprogram
To initiate a re-programming cycle, the dual-function pin
DONE/PROG
reduce sensitivity to noise, the input signal is filtered for two
cycles of the FPGA internal timing generator. When reprogram begins, the us er-prog rammabl e I/O output buf fers are
disabled and high-impedance pull-ups are provided for the
package pins. The device returns to the Clear state and
clears the config uration memo ry before it ind icates ‘initialized’. Since this Cle ar operatio n uses chip-in dividual inte rnal timing, the master might co mplete the Clear operation
and then start co nfigurati on before th e slave has com pleted
the Clear operation. To avoid this problem, the slave INIT
pins must be AND-wired and used to force a RESET on the
master (see Figure 25). Reprogram control is often imple-
mented using an external open-collector driver which pulls
DONE/PROG
the DONE/PROG
tion has been co mple te d. Even i f t he r e- pro gr am requ es t i s
externally held Low beyond the configuration period, the
FPGA will begin oper ation upon completion of config uration.
must be given a High-to-Low transition. To
Low. Once a stable request is recognized,
pin is held Low until the new configura-
DONE Pull-up
DONE/PROG is an open-drain I/O pin that indicates the
FPGA is in the operational state. An optional internal
pull-up resistor can be enabled by the user of the development system. The DONE/PROG
a daisy-chain ma y be co nnect ed to geth er to i ndica te al l ar e
DONE or to direct them all to reprogram.
pins of multiple FPGAs in
DONE Timing
The timing of the DONE status signal can be controlled by
a selection to occur either a CCLK cycle before, or after, the
outputs going active. See Figure 22. This facilitates control
of external functions such as a PROM enable or holding a
system in a wait state.
7
November 9, 1998 (Version 3.1)7-23
XC3000 Series Field Programmable Gate Arrays
R
RESET Timing
As with DONE timing, the timing of the release of the internal reset can be controlled to occur either a CCLK cycle
before, or a fter, th e outputs going active. Se e Figure 22.
This reset keeps all user programmable flip-flops and
latches in a zero state durin g co nf igu ra tio n.
Crystal Oscillator Division
A selection allows the user to incorporate a dedicated
divide-by-two flip-flop between the crystal oscillator and the
alternate clock line. This guarantees a symmetrical clock
signal. Although t he freque ncy sta bility of a c rystal osc illator is very good, the symmetry of its waveform can be
affected by bias or feedback drive.
figuration.
Each Xilinx FPGA bitst ream consis ts of a 4 0-bit p reamble,
followed by a device-specific number of data frames. The
number of bits pe r frame is als o device-spe cific; however,
each frame ends with three stop bits (111) f ollowed by a
start bit for the next frame (0).
All devices in all XC3000 fam ilies start reading in a new
frame when the y find th e first 0 after the end of t he prev ious
frame. An original XC3000 device does not check for the
correct stop bits, but XC3000A, XC3100A, XC3000L, and
XC3100L devic es che ck that the last t hree bit s of any fra me
are actually 111 .
Under normal circumstances, all these FPGAs behave the
same way; however, if the bitstream is corrupted, an
XC3000 device will always start a n ew fram e as so on as it
finds the first 0 after the end of the previous frame, even if
the data is completely wrong or out-of-sync. Given sufficient zeros in the data stream, the device will also go Done,
but with incor rect config uration an d the po ssibility of inte rnal contention.
An XC3000A/XC3100A/XC3000L/XC3100L device starts
any new frame only if the three preceding bits are all ones.
If this check fails, it pulls INIT
configuration, although the Master CCLK keeps running.
The user must t hen start a new configuration by applying a
>6 µs Low level on RESET
This simple check does not protect against random bit
errors, but it offers almost 100 percent protection against
erroneous configuration files, defective configuration data
sources, synchronization errors between configuration
source and FPGA, or PC-board level defects, such as broken lines or solder-bridges.
Low and stops the int ernal
.
Reset Spike Protection
A separate modification slows down the RESET input
before configuration by using a two-stage shift register
driven from the in ternal cloc k. It tolerates s ubmicrose cond
High spikes on RESET
master can be connected like an XC4000 master, but with
its RESET
output only).
input used instead of INIT. (On XC3 000, INIT is
before config uration. The X C3000
Soft Start-up
After configuration, the outputs of all FPGAs in a
daisy-chain become active simultaneously, as a result of
the same CCLK edge. In the original XC3000/3100
devices, each output becomes active in either fast or
slew-rate limited mode, depending on the way it is configured. This can lead to large ground-bounce signals. In
XC3000A, XC3000L, XC3100A, and XC3100L devices, all
outputs become active first in slew-rate limited mode,
reducing the ground bounce. After this soft start-up, each
individual output slew rate is again controlled by the
respective configuration bit.
7-24November 9, 1998 (Version 3.1)
R
Configuration Timing
This section describes the configuration modes in detail.
Master Serial Mode
In Master Serial mode, the CCLK output of the lead FPGA
drives a Xilinx Serial PROM that feeds the DIN input. Each
rising edge of the CCLK output increments the Serial
PROM internal address counter. This puts the next data bit
on the SPROM data output, connected to the DIN pin. The
lead FPGA accepts this data on the subsequent rising
CCLK edge.
The lead FPGA then presents the preamble data (and all
data that over flows t he lead d evice) on its DOUT p in. There
is an internal delay of 1.5 CCLK periods, which means that
*
IF READBACK IS
ACTIVATED, A
5-kΩ RESISTOR IS
REQUIRED IN
SERIES WITH M1
DURING CONFIGURATION
THE 5 kΩ M2 PULL-DOWN
RESISTOR OVERCOMES THE
INTERNAL PULL-UP,
BUT IT ALLOWS M2 TO
BE USER I/O.
GENERAL-
PURPOSE
USER I/O
PINS
M0 M1 PWRDWN
DOUT
M2
+5V
HDC
LDC
INIT
•
•
•
OTHER
•
I/O PINS
•
*
XC3000
FPGA
DEVICE
+5 V
XC3000 Series Field Programmable Gate Arrays
DOUT changes on the falling CCLK edge, and the next
device in the daisy-chain accepts data on the subsequent
rising CCLK edge.
The SPROM CE input can be driven f rom either LDC
DONE. Using LDC
avoids potential contention on the DIN
pin, if this pin is configured as user-I/ O, but LDC
restricted to be a permanently High user output. Using
DONE also avoids contention on DIN, provided the early
DONE option is invoked.
TO DIN OF OPTIONAL
DAISY-CHAINED LCAs WITH
DIFFERENT CONFIGURATIONS
TO CCLK OF OPTIONAL
DAISY-CHAINED LCAs WITH
DIFFERENT CONFIGURATIONS
TO CCLK OF OPTIONAL
SLAVE LCAs WITH IDENTICAL
CONFIGURATIONS
TO DIN OF OPTIONAL
SLAVE LCAs WITH IDENTICAL
CONFIGURATIONS
or
is then
7
+5 V
RESET
RESET
V
DIN
CCLK
D/P
INIT
(LOW RESETS THE XC17xx ADDRESS POINTER)
CCVPP
DATA
CLK
CE
OE/RESET
SCP
XC17xx
CEO
DATA
CLK
CE
OE/RESET
CASCADED
SERIAL
MEMORY
X5989_01
Figure 23: Master Serial Mode C ircuit Diagram
November 9, 1998 (Version 3.1)7-25
XC3000 Series Field Programmable Gate Arrays
CCLK
(Output)
T
2
CKDS
T
DSCK
1
R
Serial Data In
Serial DOUT
(Output)
n – 3n – 2n – 1n
nn + 1n + 2
X3223
DescriptionSymbolMinMaxUnits
CCLK
Data In setup1T
Data In hold2C
DSCK
KDS
Notes: 1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by
holding RESET Low until V
non-monotonically rising V
after VCC has reached 4.0 V (2.5 V for the XC3000L).
2. Configuration can be controlled by holding RESET
has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a
CC
may require >6-µs Hig h le vel on RESET, f ol l owed by a >6-µs Low level on RESET and D/P
CC
Low with or until after the INIT of all daisy-chain slave-mode devices is
High.
3. Master-serial-mode timing is based on slave-mode testing.
60ns
0ns
Figure 24: Master Serial Mode Programming Switching Characteristics
7-26November 9, 1998 (Version 3.1)
R
Master Parallel Mode
In Master Par all el mo de , the le ad FP GA di r ectl y ad dre sse s
an industry-standard byte-wide EPROM and accepts eight
data bits right before incrementing (or decrementing) the
address outputs.
The eight data bits are serialized in the lead FPGA, which
then presents the preamble data (and all data that overflows the lead device) on the DOUT pin. There is an inter-
XC3000 Series Field Programmable Gate Arrays
nal delay of 1.5 CCLK periods, after the rising CCLK edge
that accepts a byte of data, and also changes the EPROM
address, until the falling CCLK edge tha t makes the LSB
(D0) of this by te appear at DOUT. This means that DOUT
changes on the falling CCLK edge, and the next device in
the daisy chain accepts data on the subsequent rising
CCLK edge.
*
If Readback is
Activated, a
5-kΩ Resistor is
Required in
Series With M1
Reprogram
System Reset
+5 V
5 kΩ5 kΩ5 kΩ
General-
Purpose
User I/O
Pins
.....
RESET
+5 V
*
M0 M1PWRDWN
CCLK
DOUT
M2
HDC
RCLK
Other
I/O Pins
FPGA
Master
D7
D6
D5
D4
D3
D2
D1
D0
A15
A14
A13
A12
A11
A10
D/P
INIT
+5 V
A15
A14
A13
EPROM
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
N.C.
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
OE
CE
D7
D6
D5
D4
D3
D2
D1
D0
8
Open
Collector
**
M0 M1PWRDWN
CCLK
FPGA
Slave #1
I/O Pins
DOUT
Other
M2
HDC
LDC
...
INIT
DIN
D/P
RESET
...
GeneralPurpose
User I/O
Pins
+5 V
M0 M1PWRDWN
CCLK
DIN
D/P
Reset
DOUT
FPGA
Slave #n
M2
HDC
LDC
Other
I/O Pins
INIT
Note: XC2000 Devices Do Not
Have INIT to Hold Off a Master
Device. Reset of a Master Device
Should be Asserted by an External
Timing Circuit to Allow for LCA CCLK
Variations in Clear State Time.
+5 V
5 kΩ Each
...
GeneralPurpose
User I/O
Pins
X5990
7
Figure 25: Master Parallel Mode Circuit Diagram
November 9, 1998 (Version 3.1)7-27
XC3000 Series Field Programmable Gate Arrays
R
A0-A15
(output)
D0-D7
RCLK
(output)
CCLK
(output)
DOUT
(output)
Address for Byte n
7 CCLKsCCLK
Byte
2
T
DRC
Address for Byte n + 1
1
T
RAC
3
T
RCD
D7D6
Byte n - 1X5380
DescriptionSymbolMinMaxUnits
0
60
0
600
4.0
RCLK
To address valid
To data setup
To data hold
RCLK High
RCLK Low
1
2
3
T
T
T
T
T
RAC
DRC
RCD
RCH
RCL
Notes: 1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by
holding RESET
non-monotonically rising V
after V
2. Configuration can be controlled by holding RESET
CC
Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a
may require a >6-µs High level on RESET, followed by a >6-µs Low level on RESET and D/P
has reached 4.0 V (2.5 V for the XC3000L).
CC
Low with or until after the INIT of all daisy-chain slave-mode devices is
High.
200ns
ns
ns
ns
µs
This timing diagram shows that the EPROM requirements are extremely relaxed:
EPROM access time can be longer than 4000 ns. EPROM data output has no hold time requirements.
Peripheral mode uses the trailing edge of the lo gic AND
condition of the CS0
byte-wide data from a microprocessor bus. In the lead
FPGA, this data is l oaded in to a dou ble-bu f fere d UART-like
parallel-to-serial converter and is serially shifted into the
internal logic. The lead FPGA presents the preamble data
(and all data that overflows the lead device) on the DOUT
pin.
The Ready/Busy output from the lead device acts as a
handshake signal to the microprocessor. RDY/BUSY
Low when a byte has been received, and goes High again
CONTROL
SIGNALS
Figure 27: Peripheral Mode Circuit Diagram
, CS1, CS2, and WS inputs to accept
ADDRESS
BUS
...
+5 V
REPROGRAM
DATA
BUS
8
D0–7
ADDRESS
DECODE
LOGIC
OC
goes
M0M1 PWR
D0–7CCLK
CS0
CS1
CS2
WS
RDY/BUSY
INIT
D/P
RESET
XC3000 Series Field Programmable Gate Arrays
when the byte -w id e in pu t b uf f er h as tr an sfer re d i ts i nf or mation into the shift register, a n d the buffer is ready to receive
new data. The length of the BUSY
activity in the UART. If the shift register had been empty
when the new byt e w as re ce i ve d, the BUS Y
only two CCLK periods. If the shift register was still full
when the new byte was received, the BUSY
as long as nine CCLK periods.
Note that after the last byte has been entered, only seven
of its bits are shif ted out. CCLK rema ins High with DOUT
equal to bit 6 (the next-to-last bit) of the last byte entered.
+5 V
*
5 kΩ
DWN
OPTIONAL
DAISY-CHAINED
FPGAs WITH DIFFERENT
CONFIGURATIONS
FPGA
DOUT
HDC
OTHER
I/O PINS
M2
LDC
GENERALPURPOSE
USER I/O
PINS
...
signal depends on the
signal lasts for
signal can be
*
IF READBACK IS
ACTIVATED, A
5-kΩ RESISTOR IS
REQUIRED IN SERIES
WITH M1
X5991
7
November 9, 1998 (Version 3.1)7-29
XC3000 Series Field Programmable Gate Arrays
WRITE TO FPGA
WS, CS0, CS1
R
RDY/BUSY
WRITE
CS2
D0-D7
CCLK
Effective Write time required
(Assertion of CS0
DIN Setup time required
DIN Hold time required
RDY/BUSY
delay after end of WS4T
1
T
CA
2
T
DC
Valid
4
T
WTRB
T
CD
3
T
BUSY
6
D6DOUT
Previous ByteNew Byte
D7D0D1D2
X5992
DescriptionS ymbolMinMaxU nits
1T
CA
100ns
, CS1, CS2, WS)
2
3
T
DC
T
CD
WTRB
60
0
60ns
ns
ns
RDY
Earliest next WS
Low time generated 6T
BUSY
after end of BUSY5T
RBWT
BUSY
0ns
2.59CCLK
periods
Notes: 1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by
holding RESET
non-monotonically rising V
after V
2. Configuration must be del ayed until the INIT
CC
3. Time from end of WS
phase of the internal timing generator for CCLK.
4. CCLK and DOUT timing is test ed i n sl ave mode.
5. T
indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest T
BUSY
occurs when a byte is loaded into an em pt y parallel-to-serial conver ter. The longest TBUSY occurs when a new word is
loaded into the input register before the second-level buffer has start ed shifting out data.
Note:
This timing diagram shows very relaxed requirements: Data need not be held beyond the rising edge of WS. BUSY
Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a
may require a >6-µs High level on RESET, followed by a >6-µs Low level on RESET and D/P
has reached 4.0 V (2.5 V for the XC3000L).
CC
of all FPGAs is High.
to CCLK cycle for the new byte of data depends on completion of previous byte processing and the
BUSY
will go active with in 60 ns after the end of WS . BUSY will stay active for several m icroseconds. WS may be asserted
immediately after the end of BUSY
In Slave Serial mode, an external signal drives the CCLK
input(s) of the FPGA( s). The serial co nfiguratio n bitstream
must be available at the DIN input of the lead FPGA a short
set-up time before each rising CCLK edge. The lead device
then presents the preamble data (and all data that over-
+5 V
Micro
Computer
STRB
D0
D1
I/O
Port
D2
D3
D4
D5
D6
D7
+5 V
XC3000 Series Field Programmable Gate Arrays
flows the le ad de vic e) o n i t s D OUT pi n. Th ere is an i nte rn al
delay of 0.5 CCLK periods, which means that DOUT
changes on the falling CCLK edge, and the next device in
the daisy-chain accepts data on the subsequent rising
CCLK edge.
*
GeneralPurpose
User I/O
Pins
If Readback is
Activated, a
5-kΩ Resistor is
Required in
Series with M1
Optional
Daisy-Chained
LCAs with
Different
Configurations
*
M0M1PWRDWN
CCLK
DIN
FPGA
D/P
INIT
Other
I/O Pins
5 kΩ
M2
DOUT
HDC
LDC
...
7
RESET
Figure 29: Slave Serial Mode Circuit Diagram
RESET
X5993
November 9, 1998 (Version 3.1)7-31
XC3000 Series Field Programmable Gate Arrays
R
DIN
1
CCLK
DOUT
(Output)
Bit nBit n + 1
2
T
DCC
T
CCD
4
T
CCH
DescriptionSymbolMinMaxUnits
T
To DOUT
DIN setup
CCLK
DIN hold
High time
Low time (Note 1)
Frequency
Notes: 1. The max limit of CCLK Low time is caused by dynamic circ ui try inside the FPGA.
2. Configuration must be del ayed until the INIT
3. At power-up, V
holding RESET
non-monotonically rising V
after V
CC
must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by
CC
Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a
has reached 4.0 V (2.5 V for the XC3000L).
may require a >6-µs High level on RESET, followed by a >6-µs Low level on RESET and D/P
CC
of all FPGAs is High.
3
CCO
T
1
DCC
T
2
CCD
T
4
CCH
T
5
CCL
F
CC
5
T
CCL
3
T
CCO
Bit nBit n - 1
X5379
60
0
0.05
0.05
100
5.0
10
ns
ns
ns
µs
µs
MHz
Figure 30: Slave Serial Mode Programming Switching Characte ristics
7-32November 9, 1998 (Version 3.1)
R
XC3000 Series Field Programmable Gate Arrays
Program Readback Switching Characteristics
DONE/PROG
(OUTPUT)
1
T
RTH
RTRIG (M0)
2
T
RTCC
4
T
CCL
CCLK(1)
5
3
T
CCRD
4
T
CCL
M1 Input/
HI-Z
RDATA Output
DescriptionSymbolMinMaxUnits
RTRIGRTRIG High1T
RTRIG setup
CCLK
RDATA
High time
delay
Low time
Notes: 1. During Readback, CCLK frequency may not exceed 1 MHz.
2. RETRIG (M0 positive t ransition) shall not be done until af ter one clock following active I/O pi ns.
3. Readback should not be i ni tiated until configuration is com pl ete.
4. T
is 5 µs min to 15 µs max for XC3000L.
CCLR
READBACK OUTPUT
VALID
RTH
T
2
RTCC
3
T
CCRD
4
T
CCHR
5
T
CCLR
VALID
READBACK OUTPUT
X6116
250ns
200
0.5
0.5
100
5
ns
ns
µs
µs
7
November 9, 1998 (Version 3.1)7-33
XC3000 Series Field Programmable Gate Arrays
General XC3000 Series Switching Characteristics
4 T
MRW
RESET
2 T
M0/M1/M2
DONE/PROG
INIT
(Output)
PWRDWN
(Valid)
V
CC
MR
5 T
PGW
6 T
PGI
3 T
RM
Clear StateConfiguration StateUser State
Note 3
V
R
CCPD
X5387
DescriptionSymbolMinMaxUnits
M0, M1, M2 setup time required
(2)
RESET
M0, M1, M2 hold time required
RESET Width (Low) req. for Abort
DONE/PROG
PWRDWN
Notes: 1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by
holding RESET
non-monotonically rising V
after Vcc has reached 4.0 V (2.5 V for XC3000L).
2. RESET
specified hold time is caus ed by a shift-register filter slowi ng down the response to RESET
3. PWRDWN
Width (Low) required for Re-config.
INIT response after D/P is pulled Low
(3) Power Down V
Low until Vcc has reached 4.0 V (2.5 V for XC3000L). A very long Vcc rise time of >100 ms, or a
timing relative to valid mod e lines (M0, M1, M2) is relevant when RESET is us ed to delay configuration. The
transitions must occur while VCC >4.0 V(2.5 V for XC3000L).
CC
may require a >1-µs High level on RESET, followed by a >6-µs Low level on RESET and D/P
CC
2
3
4
5
6
T
T
T
T
T
V
MR
RM
MRW
PGW
PGI
CCPD
1
4.5
6
6
7
2.3V
µs
µs
µs
µs
µs
during configuration.
7-34November 9, 1998 (Version 3.1)
R
XC3000 Series Field Programmable Gate Arrays
Device Performance
The XC3000 families of FPGAs can achieve very high performance. This is the result of
• A sub-micron manufacturing process, developed and
continuously being enhanced for the production of
state-of-the-art CMOS SRAMs.
• Careful optimization of transistor geometries, circuit
design, and lay-out, based on years of experience with
the XC3000 family.
• A look-up table based, coarse-grained architecture that
can collapse multiple-layer combinatorial logic into a
single function generator. One CLB can implement up
to four layers of conventional logic in as little as 1.5 ns.
Actual system performance is determined by the timing of
critical paths, including the delay through the combinatorial
and sequential logic elements within CLBs and IOBs, plus
the delay in the interconnect routing. The AC-timing specifications state the worst-case timing parameters for the various logic resources available in the XC3000-families
architecture. Figure 31 shows a variety of elements
involved in determining system performance.
Logic block performance is expressed as the propagation
time from the in te rc on n ec t p oin t at th e inp u t t o th e block to
the output of the block i n the i nter connec t area . Sinc e combinatorial logic is implemented with a memory lookup table
within a CLB, the combinatorial delay through the CLB,
called T
being implemented. For the combinatorial logic function
driving the data input of the storage element, the critical
timing is data set- up relativ e to the cloc k edge provided to
the flip-flop element. The delay from the clock source to the
output of the logic block is critical in the timing signals pro-
, is always the same, regardless of the function
ILO
duced by stora ge eleme nts . Load ing of a log ic- block outp ut
is limited only by the resulting propagation delay of the
larger interconnect network. Speed performance of the
logic block is a function of supply voltage and temperature.
See Figure 32.
Interconnect performance depends on the routing
resources used to implement the signal path. Direct interconnects to the neighboring CLB provide an extremely fast
path. Local interconnects go through switch matrices
(magic boxes) and suffer an RC delay, equal to the resistance of the pass transis tor mul tipli ed by the cap acita nce of
the driven metal line. Longlines carry the signal across the
length or breadth of the chip with only one access delay.
Generous on-chip signal buffering makes performance relatively insensitive to signal fan-out; increasing fan-out from
1 to 8 changes the CLB delay by only 10%. Clocks can be
distributed w ith two low-skew clock distribution networks.
The tools in the Development System used to place and
route a design in an XC 3000 FPGA automatica ll y cal cul a t e
the actual maximum worst-case delays along each signal
path. This timing information can be back-annotated to the
design’s netlist for use in timing simulation or examined
with, a static timing analyzer.
Actual syste m performance is applications dependent. The
maximum clock rate that can be used in a system is determined by the critical path delays within that system. These
delays are combinations of incremental logic and routing
delays, and vary from design to design. In a synchronous
system, the maximum clock rat e depends on the number of
combinatorial logic layers between re-synchronizing
flip-flops. Figure 33 shows the achievable clock rate as a
function of the number of CLB layers.
7
CLOCK
PAD
Clock to Output
T
CKO
(K)
T
PID
IOB
CombinatorialSetup
T
ILO
CLBCLBIOBCLB
T
ICK
LogicLogic
(K)
T
CKO
T
OKPO
T
OP
PAD
X3178
Figure 31: Primary Block Speed Factors. Actual timing is a function of various block factors combined with routing.
factors. Overall performance can be evaluated with the timing calculator or by an optional simulation.
November 9, 1998 (Version 3.1)7-35
XC3000 Series Field Programmable Gate Arrays
Figure 33: Clock Rate as a Function of Logic
Complexity (Number of Combinational Levels between
Flip-Flops)
1.00
R
SPECIFIED WORST-CASE VALUES
MMERCIAL (4.75 V)
0.80
0.60
NORMALIZED DELAY
0.40
0.20
– 55
– 40– 20025407080100125
Figure 32: Relative Del ay as a Function of Temperature, Supply Voltage and Processing Variations
300
250
200
150
100
XC3100A-3
System Clock (MHz)
50
XC3000A--6
0
CLB Levels:
Gate Levels:
4 CLBs
(4-16)
3 CLBs
(3-12)
2 CLBs
(2-8)
1 CLB
(1-4)
MAX CO
TYPICAL COMMERCIAL
(+ 5.0 V, 25°C)
TYPICAL MILITARY
MIN COMMERCIAL (4.75 V)
MIN COMMERCIAL (5.25 V)
TEMPERATURE (°C)
Power
Power Distribution
Power for the FPG A i s di st rib ut ed t hr ough a gr i d to ac hi ev e
high noise immunity and isolation between logic and I/O.
Inside the FPGA, a dedicated V
rounding the logic array provides power to the I/O drivers.
An independen t ma tri x o f V
interior logi c of the device. This power distribution grid provides a stable sup ply and g round for all internal lo gic, pro -
Toggle
Rate
X7065
viding the external package power pins are all connected
and appropriately decoupled. Typically a 0.1-µF capacitor
connected near the V
quate decoupling.
MAX MILITARY (4.5 V)
MIN MILITARY (4.5 V)
MIN MILITARY (5.5 V)
and ground ring sur-
CC
and groundlines supplie s the
CC
and ground pins will pro vide ade-
CC
Output buffers capable of driving the specified 4- or 8-mA
loads under worst-case conditions may be capable of driving as much as 25 to 30 times that current in a best case.
Noise can be reduced by minimizing external load capacitance and reducing simultaneous output transitions in the
same direction. It may also be beneficial to locate heavily
loaded output buffers near the ground pads. The I/O Block
output buffers have a slew-limited mode which should be
used where output r i se and f al l t i mes a re n ot s pee d cri t ic al .
Slew-limited outputs ma intain their dc drive capability, but
generate less external reflections and internal noise.
X6094
7-36November 9, 1998 (Version 3.1)
R
XC3000 Series Field Programmable Gate Arrays
Dynamic Power Consumption
XC3042AXC3042LXC3142A
One CLB driving three local interconnects0.250.170.25mW per MHz
One global cloc k buffer and clock line2.251.401.70mW per MHz
One device output with a 50 pF load1.251.251.25mW per MHz
Power Consumption
The Field Progr ammable Gat e Array e xhibit s the low power
consumption cha racteristic of CMOS ICs. For a ny design,
the configuration option of TTL chip input threshold
requires power for the threshold reference. The power
required by the static memory cells that hold the configuration data is very low and may be maintained in a
power-down mode.
Typ icall y, most of power dissipat ion is pr oduced by exter nal
capacitive loads on the output buffers. This load and frequency dependent power is 25 µW/pF/MHz per output.
Another compon en t of I/O power is the exte rn al dc loading
on all output pins.
Internal power dis sipation is a function of th e number and
size of the no des , an d t he fr eq uen cy a t w h ich th ey c han ge .
In an FPGA, the fraction of nodes changing on a given
clock is typically low (10-20%). For example, in a long
binary counter, the total activity of all counter flip-flops is
equivalent to th at of only two CLB ou tputs toggling at th e
clock frequency. Typical global clock-buffer power is
between 2.0 mW/MHz for the XC3020A and 3.5 mW/MHz
for the XC3090A. The internal capacitive load is more a
function of interconnect than fan-out. With a typical load of
three general interconnect segments, each CLB output
requires about 0.25 mW per MHz of its out put frequency.
Because the control storage of the FPGA is CMOS static
memory, its cells require a very low standby current for data
retention. In some sy stems, this low data ret ention cur rent
characteristic can be used as a method of preserving configurations in the event of a primary power loss. The FPGA
has built in powerdown logic which, when activated, will
disable normal operation of the device and retain only the
configuration data. All internal operation is suspended and
output buff ers are pl aced in t heir hig h-imped ance stat e with
no pull-ups. D i f f ere nt f ro m th e XC 30 00 fa mi l y whi ch ca n b e
powered down to a current consumption of a few microamps, the XC3100A draws 5 mA, even in power-down.
This makes power- down opera tion less m eani ngful . In contrast, I
for the XC3000L is only 10 µA.
CCPD
T o force the FPGA i nto t he Powerd own stat e, the us er must
pull the PWRDWN
tion voltage to the V
restored, V
and PWRDWN
pin Low and continue to supply a reten-
pins. When normal power is
is elevated to its normal operating voltage
CC
CC
is returned to a High. The FPGA resumes
operation with the same internal sequence that occurs at
the conclusi on of con fi g ur at ion. I n te rna l-I / O a nd log i c- bl ock
storage elements will be reset, the outputs will become
enabled and the DONE/PROG
When V
is shut down or disconnected, some power
CC
pin will be released.
might unintentionally be supplied from an incoming signal
driving an I/O pin. The conventional electrostatic input protection is implemented with diodes to the supply and
ground. A positive voltage applied to an input (or output)
will cause the positive protection diode to conduct and drive
the V
connection. This condition can produce invalid
CC
power conditions and should be avoided. A large series
resistor might be used to limit the current or a bipolar buffer
may be used to isolate the input signal.
7
November 9, 1998 (Version 3.1)7-37
XC3000 Series Field Programmable Gate Arrays
R
Pin Descriptions
Permanently Dedicated Pins
V
CC
Two to eight (depending on package type) connections to
the positive V supply voltage. All must be connected.
GND
Two to eight (depending on package type) connections to
ground. All must be connected.
PWRDWN
A Low on this CMOS-compatible input stops all internal
activity, but retains configuration. All flip -flops and latches
are reset, all outputs are 3-stated, and all inputs are interpreted as High, independent of their actual level. When
PWDWN
with DONE Low for two cycles of the internal 1-MHz clock.
Before and during configuration, PWRDWN
If not used, PWRDWN
RESET
This is an active Low input which has three functions.
Prior to the start of configuration, a Low input will delay the
start of the confi gurati on proces s. An intern al circ uit sense s
the application of power and begins a minimal time-out
cycle. When the time-out and RESET
levels of the M lines are sampled and configuration begins.
If RESET
re-initialized and restarts the configuration at the termination of RESET
If RESET
vides a global asynchronous RESET
storage elements of the FPGA.
CCLK
During confi gurat ion, Conf igur ation Cloc k is an output of an
FPGA in Master mode or Peripheral mode, but an input in
Slave mode. During Readback, CCLK is a clock input for
shifting con figuration data out of the FPGA.
CCLK drives dynamic circuitry inside the FPGA. The Low
time may, therefore, not ex ceed a f ew micro second s. When
used as an input, CCLK must be “parked High”. An internal
pull-up resistor maint ains High when the pin is not being
driven.
DONE/PROG
DONE is an open-drain output, configurable with or without
an internal pu ll-up resi stor of 2 to 8 k Ω. At the completion of
configuration, the FPGA circuitry becomes active in a synchronous order; DONE is programmed to go active High
one cycle either before or after the outputs go active.
returns High, the FPGA becomes operational
must be High.
must be tied to VCC.
are complete, the
is asserted during a configuration, the FPGA is
.
is asserted after configuration is complete, it pro-
of all IOB and CLB
(D/P)
Once configuration is done, a High-to-Low transition of this
pin will cause an initialization of the FPGA and start a
reconfiguration.
M0/RTRIG
As Mode 0, this i np ut i s sa mpl ed on powe r- on t o deter mi n e
the power-on delay (2
14
cycles if M0 is High, 216 cycles if M0
is Low). Before the start of configuration, this input is again
sampled together with M1, M2 to determine the configuration mode to be used.
A Low-to-High input transition, after configuration is complete, acts as a Read Trigger and initiates a Readback of
configuration and storage-element data clocked by CCLK.
By selecting t he app ropr i at e Rea dba ck o pti on w h en gen erating the bit stream, t his o peration may be l imite d to a si ngle
Readback, or be inhibited altogether.
M1/RDATA
As Mode 1, this input and M0, M2 are sampled before the
start of configuration to establish the configuration mode to
be used. If Read back is ne ver u sed, M1 ca n be t ied di rec tly
to ground or V
5-kΩ resistor to ground or V
. If Readback i s ev er us e d, M1 mu st us e a
CC
, to accommodate the
CC
RDATA output.
As an active-Low Read Data, after configuration is com-
plete, this pi n is the output of the Readback data.
User I/O Pins That Can Have Special
Functions
M2
During configuration, this input has a weak pull-up resistor.
Together with M0 and M1, it is sampled before the start of
configuration to establish the configuration mode to be
used. After configuration, this pin is a user-programmable
I/O pin.
HDC
During configuration, this output is held at a High level to
indicate that configuration is not yet complete. After configuration, this pin is a user-programmable I/O pin.
LDC
During Configuration, this output is held at a Low level to
indicate that the configuration is not yet complete. After
configuratio n, t his p in i s a use r- pr ogr amm abl e I/ O p i n. L DC
is particularl y useful in Maste r mode as a Low enable for an
EPROM, but it must then be programmed as a High after
configuration.
INIT
This is an activ e Low ope n-dra in outp ut w ith a we ak pul l-up
and is held Low d uring the po wer stabiliz ation and int ernal
clearing of t he co nfi gura tion me mory. It can be use d to indicate status t o a configurin g micropro cessor or, as a wired
7-38November 9, 1998 (Version 3.1)
R
XC3000 Series Field Programmable Gate Arrays
AND of several slave mode devices, a hold-off signal for a
master mode device. After configuration this pin becomes a
user-programmable I/O pin.
BCLKIN
This is a direct CMOS level input to the alternate clock
buffer (Auxiliary Buffer) in the lower right corner.
XTL1
This user I/O pin c an be used to operat e as the outp ut of an
amplifier driving an exte rn a l cryst al an d bia s circ uit ry.
XTL2
This user I/O pin can be used as the input of an amplifier
connected to an external crystal and bias circuitry. The I/O
Block is left unconfigured. The oscillator configuration is
activated by routing a net from the oscilla tor buffer symb ol
output and by the MakeBits program.
, CS1, CS2, WS
CS0
These four inputs represent a set of signals, three active
Low and one active High, that are used to control configuration-data entry in the Peripheral mode. Simultaneous
assertion of all four inputs generates a Write to the internal
data buffer. The removal of any assertion clocks in the
D0-D7 data. In Mas ter- P ar all e l mode , WS and CS 2 ar e the
A0 and A1 outputs. After configuration, these pins are
user-programmable I/O pins.
RDY/BUSY
During Peripheral Parallel mode configuration this pin indicates when the chip is ready for another byte of data to be
written to it. After configuration is complete, this pin
becomes a user- programmed I/O pin.
RCLK
During Master Parallel mode configuration, each change
on the A0-15 outputs is preceded by a rising edge on
, a redundant output signal. After configuration is
RCLK
complete, this pin becomes a user-programmed I/O pin.
D0-D7
This set of eight pins represents the parallel configuration
byte for the parallel Master and Peripheral modes. After
configuration is co mplete, they are user-program med I/O
pins.
A0-A15
During Master Parallel mode, these 16 pins present an
address output for a configura tion EPROM . After conf iguration, they are user -p ro gr a mm a ble I/O pins.
DIN
During Slave or Mast er Seria l confi guration , this pi n is used
as a serial-data input. In the Master or Peripheral configuration, this is the Data 0 input. Afte r configuration is co mplete, this pin becomes a user-programmed I/O pin.
DOUT
During configura t io n thi s pin is us ed to out put se rial - c onfi guration data to the DIN pin of a daisy-chained slave. After
configuration is complete, this pin becomes a user-programmed I/O pin.
TCLKIN
This is a direct CMO S-level input to the global clock buffer.
This pin can also be configured as a user programmable
I/O pin. Howe ver , s ince TCLKIN is the pr eferred i nput t o the
global clock net , and th e globa l clock ne t shoul d be use d as
the primary clock source, this pin is usually the clock input
to the chip.
Unrestricted User I/O Pins
I/O
An I/O pin may be programmed by the user to be an Input
or an Output pi n foll owing conf igura tio n. Al l unr estri cte d I/O
pins, plus the sp ecial pins men tioned on the followin g page,
have a weak pull-up resist or that becomes a ctive as soon
as the device powers up, and stays active until the end of
configuration.
7
Before and during configuration, all outputs that are not used for the configuration process are 3-stated with a weak
XXX XXXXC3x42A etc.
X**XXXC3x64A etc.
X**XXXXXXC3x90A etc.
PGA
176
TQFP
PQFP
208
User
Function
POWER
DWN
(1)
All Others
Generic I/O pins are not shown.
For a detailed description of the configuration modes, see page25 through page 34.
For pinout details, see page 65 through page 76.
Represents a weak pull-up before and during configuration.
INIT is an open drain output during configuration.
*
Represents an input.
(I)
Pin assignment for the XC3064A/XC3090A and XC3195A differ from those shown.
**
Peripheral mode and master parallel mode are not supported in the PC44 package.
***
Pin assignments for the XC3195A PQ208 differ from those shown.
****
Pin assignments of PGA Footprint PLCC sockets and PGA packages are not identical.
The information on this page is provided as a convenient summary. For detailed pin descriptions, see the preceding two pages.
Note
Before and during configuration, all outputs that are not used for the configuration process are 3-stated with a weak pull-up resistor.
:
7-40November 9, 1998 (Version 3.1)
R
XC3000 Series Field Programmable Gate Arrays
XC3000A Switching Characteristics
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released
device perfo rmance parameters, please request a copy of the current t e st-specification revision.
XC3000A Operating Conditions
SymbolDescriptionMinMaxUnits
V
CC
V
IHT
V
ILT
V
IHC
V
ILC
T
IN
Note:At junction tem peratures above those listed as Operating Conditions, all delay paramet ers increase by 0.3% per °C.
XC3000A DC Characteristics Over Operating Conditions
Supply voltage relative to GND Comme rc ial 0°C to +85°C junction 4.755.25V
Supply voltage relative to GND Industrial -40°C to +100°C junction 4.55.5V
High-level input voltage — TTL configuration2.0V
CC
Low-level input voltage — TTL configuration00.8V
High-level input voltage — CMOS configuration70%100%V
Low-level input voltage — CMOS configuration020%V
Input signal transition time250ns
V
CC
CC
SymbolDescriptionMinMaxUnits
V
V
V
V
V
CCPD
I
CCPD
I
CCO
I
OH
OL
OH
OL
IL
High-level output voltage (@ IOH = –4.0 mA, VCC min)
Low-level output voltage (@ IOL = 4.0 mA, VCC min)0.40V
High-level output voltage (@ IOH = –4.0 mA, VCC min)
Low-level output voltage (@ IOL = 4.0 mA, VCC min)0.40V
Commercial
Industrial
Power-down supply voltage (PWRDWN mus t be Low)2.30V
Power-down supply current
(V
CC(MAX)
@ T
)3020A
MAX
3030A
3042A
3064A
3090A
Quiescent FPGA supply current in addition to I
CCPD
Chip thresholds programmed as CMOS levels
Chip thresholds programmed as TTL levels
Input Leakage Current–10+10µA
3.86V
3.76V
100
160
240
340
500
500
10
Input capaci tance, all packages except PGA175
(sample tested)
All Pins except XTL1 and XTL2
C
IN
XTL1 and XTL2
Input capacitance, PGA 175
10
15
(sample tested)
All Pins except XTL1 and XTL2
XTL1 and XTL2
I
I
RIN
RLL
Pad pull-up (when selected) @ VIN = 0 V
Horizontal Longline pull-up (when selected) @ logic Low3.4mA
3
Notes: 1. With no output current loads, no active input or Longline pull-up resistors, all package pins at V
device configured with a tie option.
2. T otal continuous output sink current may not exceed 100 mA per ground pin. T otal continuous output source may not exceed
100 mA per V
3. Not tested. Allow an undriven pin to float High. For any other purposes use an external pull-up.
pin. The number of ground pins varies from the XC3020A to the XC3090A.
CC
0.020.17mA
or GND, and the FPGA
CC
16
20
7
µA
µA
µA
µA
µA
µA
µA
pF
pF
pF
pF
November 9, 1998 (Version 3.1)7-41
XC3000 Series Field Programmable Gate Arrays
XC3000A Absolute Maximum Ratings
SymbolDescriptionUnits
Supply voltage relative to GND–0.5 to +7.0V
Input voltage with respect to GND–0.5 to VCC +0.5V
Voltage applied to 3-state output–0.5 to VCC +0.5V
Storage temperature (ambient)–65 to +150°C
Maximum soldering tem p er at ur e (1 0 s @ 1/1 6 in.)+260°C
Junction temper at ur e pla st i c+125°C
Junction temperature ceramic+150°C
T
T
V
V
V
STG
T
CC
IN
TS
SOL
J
R
Note: Stresses beyond thos e l is ted under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions bey ond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended
periods of time may affect device reliability.
XC3000A Global Buffer Switching Characteristics Guidelines
Speed Grade-7-6
DescriptionSymbolMaxMaxUnits
Global and Alternate Clock Distribution
Either: Normal IOB input pad through clock buffer
to any CLB or IOB clock input
Or: Fast (CMOS only) input pad through clock
buffer to any CLB or IOB clock input
TBUF driving a Horizontal Longline (L.L.)
I to L.L. while T is Low (buffer ac tive)
T↓ to L.L. active and valid with single pull-up resistor
T↓ to L.L. active and valid with pair of pull-up resistors
T↑ to L.L. High with single pull-up resist or
T↑ to L.L. High with pair of pull-up resistors
BIDI
Bidirectional buffer delayT
Note: 1. Timing is based on the XC3042A, for other devices see timing calcu la to r.
1
T
PID
T
1
PIDC
T
T
T
T
PUS
T
PUF
BIDI
IO
ON
ON
7.5
6.0
4.5
9.0
11.0
16.0
10.0
1.71.5ns
7.0
5.7
4.0
8.0
10.0
14.0
8.0
ns
ns
ns
ns
ns
ns
ns
7-42November 9, 1998 (Version 3.1)
R
XC3000 Series Field Programmable Gate Arrays
XC3000A CLB Switching Characteristics Guidelines
Testing of the switchin g parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Speed Grade-7-6
DescriptionSymbolMinMaxMinMaxUnits
Combinatorial Delay
Logic VariablesA, B, C, D, E, to outputs X or Y
FG Mode
F and FGM Mode
Sequential delay
Clock k to outputs X or Y
Clock k to outputs X or Y when Q is returned
through function generators F or G to drive X or Y
FG Mode
F and FGM Mode
Set-up time before clock K
Logic Variables A, B, C, D, E
FG Mode
F and FGM Mode
Data InDI
Enable ClockEC
Hold Time after clock K
Logic VariablesA, B, C, D, E
Data InDI
2
Enable ClockEC
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
Reset Direct (RD)
RD width
delay from RD to outputs X or Y
1
Global Reset (RESET
Pad)
RESET width (Low)
delay from RESET
Notes:
1. Timing is based on the XC3042A, for other devi ces see timing calculator.
2. The CLB K to Q output delay (T
Data In hold time requirement (T
pad to outputs X or Y
, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the
Testing of the switchin g parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Speed Grade-7-6
DescriptionSymbolMinMaxMinMaxUnits
Propagation Delays (Input)
Pad to Direct In (I)
Pad to Registered In (Q) with latch transparent
Clock (IK) to Registered In (Q)
3
4
T
T
T
PID
PTG
IKRI
4.0
15.0
3.0
Set-up Time (Input)
Pad to Clock (IK) set-up time1T
PICK
14.012.0ns
Propagation Delays (Output)
Clock (OK) to Pad(fast)
same(slew rate limited)
Output (O) to Pad(fast)
same(slew-rate limited)
3-state to Pad begin hi-Z(fast)
same(slew-rate limited)
3-state to Pad a ctive and valid(fast)
same(slew -rate limited)
10
10
7
7
9
9
8
8
OKPO
T
OKPO
T
T
T
TSHZ
T
TSHZ
T
TSON
T
TSON
OPF
OPS
8.0
18.0
6.0
16.0
10.0
20.0
11.0
21.0
T
Set-up and Hold Times (Output)
Output (O) to clock (OK) set-up time
Output (O) to clock (OK) hold time
5
T
OOK
T
6
OKO
8.0
0
7.0
0
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
11
12
F
T
T
IOH
IOL
CLK
4.0
4.0
113.0
3.5
3.5
135.0
Global Reset Delays (based on XC3042A)
RESET
RESET
Pad to Registered In (Q)
Pad to output pad(fast)
(slew-rate limited)
Notes: 1. Timing is measured at pin threshold, with 50 pF exte rnal capacitive loads (incl. test fi xture). Typical slew rate limited output
rise/fall times are approxi m ately four times longer.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels . Ea ch can be configured with the internal
pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up tim e is specified with respect to the internal clock (ik). In order to cal culate system set-up time, subtract
clock delay (pad to ik) from the in put pad set-up time value. Input pad holdt i me with respect to the internal cloc k (i k) is
negative. This means that pad level changes immediately before the internal clock edge (ik) wil l no t be rec ognized.
, T
4. T
PID
PTG
, and T
are 3 ns higher for XTL2 when the pin is configured as a user input.
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released
device perfo rmance parameters, please request a copy of the current t e st-specification revision.
XC3000L Operating Conditions
SymbolDescriptionMinMaxUnits
Supply voltage relative to GND Comme rc ial 0°C to +85°C junction 3.03.6V
V
CC
V
IH
V
IL
T
IN
Notes: 1. At junction temperatures above those listed as Operating Conditio ns, all delay parameters increase by 0.3% per °C.
2. Although the present (1996) devices operate over the full supply voltage range from 3.0 to 5.25 V, Xilinx reserves the right to
XC3000L DC Characteristics Over Operating Condition s
SymbolDescriptionMinMaxUnits
V
OH
V
OL
V
OH
V
OL
V
CCPD
I
CCPD
I
CCO
I
IL
C
IN
I
RIN
I
RLL
Notes: 1. With no output current loads, no active input or Longline pull-up resistors, all package pins at V
2. T otal continuous output sink current may not exceed 100 mA per ground pin. T otal continuous output source may not exceed
3. Not tested. Allows an undriven p in to float High. For any other purpose, use an exter nal pul l -up.
High-level input voltage — TTL configuration2.0VCC+0.3V
Low-level input voltage — TTL conf igu ratio n-0.30.8V
Input signal transition time250ns
restrict operation to the 3.0 to 3.6 V range later, when smaller device geometries might preclud e o peration at 5V. Operating
conditions are guaranteed i n the 3.0 – 3.6 V V
CC
range.
High-level output voltage (@ IOH = –4.0 mA, VCC min)2.40V
Low-level output voltage (@ IOL = 4.0 mA, VCC min)0.40V
High-level output voltage (@ IOH = –4.0 mA, VCC min) VCC -0.2V
Low-level output voltage (@ IOL = 4.0 mA, VCC min)0.2V
Power-down supply voltage (PWRDWN mus t be Low)2.30V
Power-down supply current (V
CC(MAX)
Quiescent FPGA supply current in addition to I
@ T
)10µA
MAX
CCPD
1
Chip thresholds programmed as CMOS levels20µA
Input Leakage Current–10+10µA
Input capaci tance, all packages except PGA175
(sample tested)
All Pins except XTL1 and XTL2
XTL1 and XTL2
10
15
pF
pF
Input capacitance, PGA 175
(sample tested)
All Pins except XTL1 and XTL2
XTL1 and XTL2
15
20
pF
pF
Pad pull-up (when selected) @ VIN = 0 V3 0.010.17mA
Horizontal Lo ngline pull-up (when selected) @ logic Low2.50mA
or GND, and the FPGA
device configured with a tie option. I
100 mA per V
pin. The number of ground pins varies from the XC3020L to the XC3090L.
CC
is in addition to I
CCO
CCPD
.
CC
7
November 9, 1998 (Version 3.1)7-47
XC3000 Series Field Programmable Gate Arrays
XC3000L Absolute Maximum Ratings
SymbolDescriptionUnits
Supply voltage relative to GND–0.5 to +7.0V
Input voltage with respect to GND–0.5 to VCC +0.5V
Voltage applied to 3-state output–0.5 to VCC +0.5V
Storage temperature (ambient)–65 to +150°C
Maximum soldering tem p er at ur e (1 0 s @ 1/1 6 in.)+260°C
Junction temper at ur e pla st i c+125°C
Junction temperature ceramic+150°C
T
T
V
V
V
STG
T
CC
IN
TS
SOL
J
R
Note: Stresses beyond thos e l is ted under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions bey ond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended
periods of time may affect device reliability.
XC3000L Global Buffer Switching Characteristics Guidelines
Speed Grade-8
DescriptionSymbolMaxUnits
Global and Alternate Clock Distribution
Either: Normal IOB input pad through clock buffer
to any CLB or IOB clock input
Or: Fast (CMOS only) input pad through clock
buffer to any CLB or IOB clock input
TBUF driving a Horizontal Longline (L.L.)
I to L.L. while T is Low (buffer ac tive)
T↓ to L.L. active and valid with single pull-up resistor
T↑ to L.L. High with single pull-up resist or
BIDI
Bidirectional buffer delayT
Notes: 1. Timing is based on the XC3042A, for other devices see t imi ng calculator.
2. The use of two pull-up resist ors per Longline, available on other XC3000 devices, is not a valid option for XC3000L devices.
1
T
PID
T
1
PIDC
T
T
T
IO
ON
PUS
BIDI
9.0
7.0
5.0
12.0
24.0
2.0ns
ns
ns
ns
ns
ns
7-48November 9, 1998 (Version 3.1)
R
XC3000 Series Field Programmable Gate Arrays
XC3000L CLB Switching Characteristics Guidelines
Testing of the switchin g parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Speed Grade-8
DescriptionSymbolMinMaxUnits
Combinatorial Delay
Logic VariablesA, B, C, D, E, to outputs X or Y
FG Mode
F and FGM Mode
Sequential delay
Clock k to outputs X or Y
Clock k to outputs X or Y when Q is returned
through function generators F or G to drive X or Y
FG Mode
F and FGM Mode
Set-up time before clock K
Logic Variables A, B, C, D, E
FG Mode
F and FGM Mode
Data InDI
Enable ClockEC
Hold Time after clock K
Logic VariablesA, B, C, D, E
Data InDI
2
Enable ClockEC
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
Reset Direct (RD)
RD width
delay from RD to outputs X or Y
1
Global Reset (RESET
Pad)
RESET width (Low)
delay from RESET
Notes:
1. Timing is based on the XC3042L, for other d evi ces see timing calculator.
2. The CLB K to Q output delay (T
Data In hold time requirement (T
pad to outputs X or Y
, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the
Testing of the switchin g parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Speed Grade-8
DescriptionSymbolMinMaxUnits
Propagation Delays (Input)
Pad to Direct In (I)
Pad to Registered In (Q) with latch transparent
Clock (IK) to Registered In (Q)
Set-up Time (Input)
Pad to Clock (IK) set-up time1T
Propagation Delays (Output)
Clock (OK) to Pad(fast)
same(slew rate limited)
Output (O) to Pad(fast)
same(slew-rate limited)
3-state to Pad begin hi-Z(fast)
same(slew-rate limited)
3-state to Pad a ctive and valid(fast)
same(slew -rate limited)
Set-up and Hold Times (Output)
Output (O) to clock (OK) set-up time
Output (O) to clock (OK) hold time
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
Global Reset Delays (based on XC3042L)
RESET
RESET
Pad to Registered In (Q)
Pad to output pad (fast)
(slew-rate limited)
Notes:
1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Typical slew rate limited output
rise/fall times are approxi m ately four times longer.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels . Ea ch can be configured with the internal
pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up tim e is specified with respect to the internal clock (ik). In order to cal culate system set-up time, subtract
clock delay (pad to ik) from the in put pad set-up time value. Input pad holdt i me with respect to the internal cloc k (i k) is
negative. This means that pad level changes immediately before the internal clock edge (ik) wil l no t be rec ognized.
, T
4. T
PID
PTG
, and T
are 3 ns higher for XTL2 when the pin is conf i gured as a user input.
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released
device perfo rmance parameters, please request a copy of the current t e st-specification revision.
XC3100A Operating Conditions
SymbolDescriptionMinMaxUnits
Supply voltage relative to GND Comme rc ial 0°C to +85°C junction 4.255.25V
V
CC
V
IHT
V
ILT
V
IHC
V
ILC
T
IN
Note:At junction tem peratures above those listed as Operating Conditions, all delay paramet ers increase by 0.3% per °C.
XC3100A DC Characteristics Over Operating Conditions
Supply voltage relative to GND Industrial -40°C to +100°C junction 4.55.5V
High-level input voltage — TTL configuration2.0V
CC
Low-level input voltage — TTL configuration00.8V
High-level input voltage — CMOS configuration70%100%V
Low-level input voltage — CMOS configuration020%V
Input signal transition time250ns
V
CC
CC
SymbolDescriptionMinMaxUnits
V
V
V
V
V
CCPD
I
CCO
I
OH
OL
OH
OL
IL
High-level output voltage (@ IOH = –8.0 mA, VCC min)
Low-level output voltage (@ IOL = 8.0 mA, VCC min)0.40V
High-level output voltage (@ IOH = –8.0 mA, VCC min)
Low-level output voltage (@ IOL = 8.0 mA, VCC min)0.40V
Commercial
Industrial
Power-down supply voltage (PWRDWN mus t be Low)2.30V
Quiescent LCA supply current in addition to I
CCPD
1
Chip thresholds programmed as CMOS levels
Chip thresholds programmed as TTL levels
Input Leakage Current–10+10µA
3.86V
3.76V
8
14
Input capaci tance, all packages except PGA175
(sample tested)
All Pins except XTL1 and XTL2
C
IN
XTL1 and XTL2
Input capacitance, PGA 175
10
15
(sample tested)
All Pins except XTL1 and XTL2
XTL1 and XTL2
I
I
RIN
RLL
Pad pull-up (when selected) @ VIN = 0 V
Horizontal Lo ngline pull-up (when selected) @ logic Low0.202.80mA
3
Notes: 1. With no output current loads, no active input or Longline pull-up resistors, all package pins at V
device configured with a tie option.
2. T otal continuous output sink current may not exceed 100 mA per ground pin. The number of ground pins varies from two for
the XC3120A in the PC84 package, to eight for the XC3195A in the PQ208 package .
3. Not tested. Allows an undriven p in to float High. For any other purpose, use an exter nal pul l -up.
0.020.17mA
or GND, and the LCA
CC
15
20
7
mA
mA
pF
pF
pF
pF
November 9, 1998 (Version 3.1)7-53
XC3000 Series Field Programmable Gate Arrays
XC3100A Absolute Maximum Ratings
SymbolDescriptionUnits
Supply voltage relative to GND–0.5 to +7.0V
Input voltage with respect to GND–0.5 to VCC +0.5V
Voltage applied to 3-state output–0.5 to VCC +0.5V
Storage temperature (ambient)–65 to +150°C
Maximum soldering tem p er at ur e (1 0 s @ 1/1 6 in.)+260°C
Junction temper at ur e pla st i c+125°C
Junction temperature ceramic+150°C
T
T
V
V
V
STG
T
CC
IN
TS
SOL
J
R
Note: Stresses beyond thos e l is ted under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions bey ond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended
periods of time may affect device reliability.
XC3100A Global Buffer Switching Characteristics Guidelines
Speed Grade-4-3-2-1-09
DescriptionSymbolMaxMaxMaxMaxMaxUnits
Global and Alternate C lock Distribution
Either: Normal IOB input pad through clock buffer
to any CLB or IOB clock input
Or: Fast (CMOS only) input pad through clock
buffer to any CLB or IOB clock input
TBUF driving a Horizontal Longline (L.L.)
I to L.L. while T is Low (buffer active)(XC3100)
T↓ to L.L. active a nd valid with single pull-up resistor
T↓ to L.L. active and valid with pair of pull-up resistors
T↑ to L.L. High with single pull-up resist or
T↑ to L.L. High with pair of pull-up resistors
BIDI
Bidirectional buffer delayT
1
1
(XC3100A)
T
T
T
T
T
T
PID
PIDC
T
IO
T
IO
ON
ON
PUS
PUF
BIDI
6.5
5.1
3.7
3.6
5.0
6.5
13.5
10.5
5.6
4.3
3.1
3.1
4.2
5.7
11.4
8.8
4.7
3.7
3.1
4.2
5.7
11.4
8.1
4.3
3.5
2.9
4.0
5.5
10.4
7.1
3.9
3.1nsns
2.1
3.1
4.6
8.9
5.9
1.21.00.90.850.75ns
Prelim
ns
ns
ns
ns
ns
ns
Note:1. Timing is based on the XC3142A, for other devices see timi ng calculator.
The use of two pull-up resistors per longline, available on other XC3000 devices, is not a valid design opt io n for XC3100A
devices.
7-54November 9, 1998 (Version 3.1)
R
XC3000 Series Field Programmable Gate Arrays
XC3100A CLB Switching Characteristics Guidelines
Testing of the switchin g parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Testing of the switchin g parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
with latch transparent(XC3100A)Clock (IK)
to Registered In (Q)
Set-up Time (Input)
Pad to Clock (IK) set-up time
XC3120A, XC3130A
XC3142A
XC3164A
XC3190A
XC3195A
Propagation Delays (Output)
Clock (OK) to Pad (fast)
same
(slew rate limited)
Output (O) to Pad (fast)
same
(slew-rate limited)
(XC3100A)
3-state to Pad
begin hi-Z(fast)
same
(slew-rate limited)
3-state to Pad
active and valid (fast) (XC3100A)
same
(slew -rate limited)
Set-up and Hold Times (Output)
Output (O) to clock (OK) set-up time
(XC3100A)
Output (O) to clock (OK) hold time
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
Global Reset Delays
RESET Pad to Registered In(Q)
(XC3142A)
(XC3190A)
RESET Pad to output pad (f ast)
(slew-rate limited)
34T
1T
7
T
T
7
10
10
9
T
T
9
T
8
T
8
56T
T
1112T
13
T
15
T
15
PID
T
PTG
T
IKRI
PICK
OKPO
OKPO
T
OPF
T
OPS
TSHZ
TSHZ
TSON
TSON
OOK
OKO
IOH
T
IOL
F
CLK
T
RRI
RPO
RPO
10.6
10.7
11.0
11.2
11.6
4.5
0
2.0
2.0
227
2.5
12.0
2.5
5.0
12.0
3.7
11.0
6.2
6.2
10.0
17.0
15.0
25.5
20.0
27.0
9.4
9.5
9.7
9.9
10.3
1.6
1.6
270
2.2
11.0
2.2
4.4
10.0
3.3
9.0
5.5
5.5
9.0
15.0
13.0
21.0
17.0
23.0
8.9
9.0
9.2
9.4
9.8
3.6
0
1.3
1.3
323
2.0
11.0
1.9
3.7
9.7
3.0
8.7
5.0
5.0
8.5
14.2
13.0
21.0
17.0
23.0
8.0
8.1
8.3
8.5
8.9
3.2
0
1.3
1.3
323
1.7
10.0
1.7
3.4
8.4
3.0
8.0
4.5
4.5
6.5
11.5
370
13.0
21.0
17.0
22.0
Preliminary
1.55
9.2
1.55
7.2
7.3
7.5
7.7
8.1
3.3
6.9
2.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6.5
4.05
4.05
5.0
8.6
ns
ns
ns
ns
ns
2.9ns
ns
1.3
1.3
ns
ns
MHz
14.4
21.0
17.0
21.0
ns
ns
ns
ns
7
Notes:
1. Timing is measured at pin threshold, wi th 50 pF external capacitive loads (incl. test fixture). For larger capaci tive loads, see
XAPP024. Typical slew rate limited output rise/fall times are approximately four times longer.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels . Ea ch can be configured with the internal
pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up tim e is specified with respect to the internal clock (ik). In order to cal culate system set-up time, subtract
clock delay (pad to ik) from the in put pad set-up time value. Input pad holdt i me with respect to the internal cloc k (i k) is
negative. This means that pad level changes immediately before the internal clock edge (ik) wil l no t be rec ognized.
, T
4. T
PID
PTG
, and T
are 3 ns higher for XTL2 when the pin is conf i gured as a user input.
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released
device perfo rmance parameters, please request a copy of the current t e st-specification revision.
XC3100L Operating Conditions
SymbolDescriptionMinMaxUnits
V
CC
V
IH
V
IL
T
IN
Notes: 1. At junc tion temperatures above those listed as Operating Conditions, all delay pa rameters increase by 0.3% per °C.
2. Although the present (1996) devices operate over the full supply voltage range from 3.0 V to 5.25 V, Xilinx reserves the right
XC3100L DC Characteristics Over Operating Condition s
SymbolDescriptionMinMaxUnits
V
OH
V
OL
V
CCPD
I
CCO
I
IL
C
IN
I
RIN
I
RLL
Supply voltage relative to GND Comme rc ial 0°C to +85°C junction3.03.6V
High-level input voltage2.0VCC + 0.3V
Low-level input voltage-0. 30.8V
Input signal transition time250ns
to restrict operation to the 3.0 and 3. 6 V range later, when smaller device geomet ri es might preclude operation @ 5 V.
Operating conditions are guaranteed in the 3.0 – 3.6 V V
CC
range.
High-level output voltage (@ IOH = -4.0 mA, VCC min)2.4V
High-level output voltage (@ I
= -100.0 µA, VCC min)VCC -0.2V
OH
Low-level output voltage (@ IOH = 4.0 mA, VCC min)0.40V
Low-level output voltage (@ I
= +100.0 µA, VCC min)0.2V
OH
Power-down supply voltage (PWRDWN must be Low)2.30V
Quiescent FPGA supply current
Chip thresholds programmed as CMOS levels
1
1.5mA
Input Leakage Current-10+10µA
Input capacit ance
(sample tested)
All pins except XTL1 and XTL2
XTL1 and XTL2
10
15
Pad pull-up (when selected) @ VIN = 0 V 3 0.020.17mA
Horizontal long line pull-up (when selected) @ logic Low0.202.80mA
pF
pF
7
Notes: 1. With no output current loads, no active input or long line pull-up resistors, all package pins at V
configured with a tie option.
2. T otal continuous output sink current may not exceed 100 mA per ground pin. Total continuous output source current may not
exceed 100 mA per V
3. Not tested. Allows undriven pins to float High. For any other purpose, use an exte rnal pul l -up.
pin. The number of ground pins varies from the XC3142L to the XC3190L.
CC
or GND, and the FPGA
CC
November 9, 1998 (Version 3.1)7-59
XC3000 Series Field Programmable Gate Arrays
XC3100L Absolute Maximum Ratings
SymbolDescriptionUnits
Supply voltage relative to GND–0.5 to +7.0V
Input voltage with respect to GND–0.5 to VCC +0.5V
Voltage applied to 3-state output–0.5 to VCC +0.5V
Storage temperature (ambient)–65 to +150°C
Maximum soldering tem p er at ur e (1 0 s @ 1/1 6 in.)+260°C
Junction temper at ur e pla st i c+125°C
Junction temperature ceramic+150°C
T
T
V
V
V
STG
T
CC
IN
TS
SOL
J
R
Note: Stresses beyond thos e l is ted under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions bey ond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended
periods of time may affect device reliability.
XC3100L Global Buffer Switching Characteristics Guidelines
Speed Grade-3-2
DescriptionSymbolMaxMaxUnits
Global and Alternate C lock Distribution
Either:Normal IOB input pad through clock buffer
to any CLB or IOB clock input
Or: Fast (CMOS only) input pa d through clock
buffer to any CLB or IOB clock input
TBUF driving a Horizontal Longline (L.L.)
I to L.L. while T is Low (buffer ac tive)
T↓ to L.L. active and valid with single pull-up resistor
T↑ to L.L. High with single pull-up resist or
BIDI
Bidirectional buffer delayT
Notes: 1. Timing is based on the XC3142L, for other devic e s see timing calculator.
2. The use of two pull-up resistors per longline, available on other XC3000 devices, is not a valid option for XC3100L devices.
1
T
PID
T
1
PIDC
T
T
T
IO
ON
PUS
BIDI
5.6
4.3
3.1
4.2
11.4
4.7
3.7
3.1
4.2
11.4
1.00.9ns
Advance
ns
ns
ns
ns
ns
7-60November 9, 1998 (Version 3.1)
R
XC3000 Series Field Programmable Gate Arrays
XC3100L CLB Switching Characteristics Guidelines
Testing of the switchin g parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Speed Grade-3-2
DescriptionSymbolMinMaxMinMaxUnits
Combinatorial Delay
Logic Variables A, B, C, D, E, to outputs X or Y1T
Sequential delay
Clock k to outputs X or Y
Clock k to outputs X or Y when Q is returned
through funct ion generators F or G to drive X or Y
Set-up time before clock K
Logic Variables A , B, C, D, E
Data InDI
Enable ClockEC
Reset Direct Inactive RD
Hold Time after clock K
Logic VariablesA, B, C, D, E
Data InDI
Enable ClockEC
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
Reset Direct (RD)
RD width
delay from RD to outputs X or Y
Global Reset (RESET
RESET
width (Low)
Pad)
(XC3142L)
delay from RESET
pad to outputs X or Y
ILO
8T
2
4
6
3
5
7
11
12
13
9
T
T
T
T
ECCK
T
T
T
CKEC
T
T
F
T
T
T
T
CKO
QLO
ICK
DICK
CKI
CKDI
CH
CL
CLK
RPW
RIO
MRW
MRQ
2.1
1.4
2.7
1.0
0
0.9
0.7
1.6
1.6
270
2.7
12.0
2.72.2ns
2.1
4.3
1.7
3.5
1.8
1.3
2.5
1.0
0
0.9
0.7
1.3
1.3
325
MHz
2.3
3.1
2.7
12.0
12.0
12.0
Advance
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
Notes: 1. The CLB K to Q delay (T
In hold time requirement (T
2. T
, T
QLO
and T
ICK
ILO
specifications for the XC3100L family increase by 0.35 ns (-3) and 0.29 ns (-2).
, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the Data
CKO
, #5) of any CLB on the same die.
CKDI
are specified for 4-input functi ons. For 5-input functions or bas e FGM functions, each of these
Testing of the switchin g parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Speed Grade-3-2
DescriptionSymbolMinMaxMinMaxUnits
Propagation Delays (Input)
Pad to Direct In (I)
Pad to Registe r ed In (Q) with latch (XC3100L)
transparent
Clock (IK) to Registered In (Q)
Set-up Time (Input)
Pad to Clock (IK) set-up time
XC3142L
XC3190L
Propagation Delays (Output)
Clock (OK) to Pad(f ast )
same(slew rate limited)
Output (O) to Pad(fast)
same(slew-rate limited)(XC3100L)
3-state to Pad begin hi-Z(fast)
same(slew-rate limited)
3-state to Pad active and valid(fast)(XC3100L)
same(slew -rate limited)
Set-up and Hold Times (Output)
Output (O) to clock (OK) set-up time (XC3100L)
Output (O) to clock (OK) hold time
Clock
Clock High time
Clock Low time
Export Control Maximum flip-flop toggle rate
Global Reset Delays
RESET
Pad to Registered In (Q)
(XC3142L)
(XC3190L)
RESET
Pad to output pad (fast)
(slew-rate limited)
3
4
1T
7
7
10
10
9
9
8
8
5
6
11
12
13
15
15
T
PID
T
PTG
T
IKRI
PICK
T
OKPOTOK
PO
T
OPF
T
OPF
T
TSHZ
T
TSHZ
T
TSON
T
TSON
T
OOK
T
OKO
T
IOH
T
IOL
F
TOG
T
RRI
T
RPO
T
RPO
9.5
9.9
4.0
0
1.6
1.6
270
2.2
11.0
2.2
9.0
9.4
4.4
10.0
3.3
9.0
5.5
5.5
9.0
15.0
3.6
0
1.3
1.3
325
16.0
21.0
17.0
23.0
Advance
2.0
11.0
1.9
4.0
9.7
3.0
8.7
5.0
5.0
8.5
14.2
16.0
21.0
17.0
23.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
7
Notes:
1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Typical slew rate limited output
rise/fall times are approxi m ately four times longer.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels . Ea ch can be configured with the internal
pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up time is specified with respect to the internal clock (IK). In order to cal cul ate system set-up time, subtrac t
clock delay (pad to ik) from the in put pad set-up time value. Input pad holdt i me with respect to the internal cloc k (IK) is
negative. This means that pad level changes immediately before the internal clock edge (IK) will no t be rec ognized.
Xilinx offers the six differen t array sizes in the XC3000 families in a variety of surface-m ount and through -hole package
types, with pin counts from 44 to 208.
Each chip is of fered i n several pac kage type s to accommoda te the avail able PC bo ard space an d manufactur ing techn ology .
Most package types are also offered with different chips to accommodate design changes without the need for PC board
changes.
Note that there is no per fe ct ma tch b et we en the num ber of bon ding pad s on t he chi p and th e nu mbe r of pi n s on a pack ag e.
In some cases, th e chi p has mo re pad s than th ere are pins on the pac kage , as ind ica ted by the inf orma tion (“ unus ed” pad s)
below the line in the following table. The IOBs of the unconnected pads can still be used as storage elements if the specified
propagation delays and set-up times are acceptable .
In other cases, the chip ha s fewer pad s than ther e are pins on th e package; therefor e, some pack age pins are n ot connect ed
(n.c.), as shown above the line in the following table.
XC3000 Series 44-Pin PLCC Pinouts
XC3000A, XC3000L, and XC3100A families have identical pinouts
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs.
Programmed outputs are default sl ew-rate limited.
This table describes the pinouts of three different chips in three different packages. The pin-description column lists 84 of the
118 pads on the XC3042A (and 84 of the 98 pads on the XC3030A) that are connected to the 84 package pins. Ten pads,
indicated by an asterisk, do not exist on the XC3020A, which has 74 pads; therefore the corresponding pins on the 84-pin
packages have no connections to an XC3020A. Six pads on the XC3020A and 16 pads on the XC3030A, indicated by a
dash (—) in the 68 PL CC column, have no connection to the 68 PLCC, but are connected to the 84-pin packages.
November 9, 1998 (Version 3.1)7-67
XC3000 Series Field Programmable Gate Arrays
XC3064A/XC3090A/XC3195A 84-Pin PLCC Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
PLCC Pin Number XC3064A, XC3090A, XC 3195APLCC Pin NumberXC3064A , X C3090A, XC3195A
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs.
Programmed outputs are default slew-rate limited.
* In the PC84 package, XC3064A, XC3090A and XC3195A have additional VCC and GND pins and thus a different pin
definition than XC3020A/XC3030A/XC3042A.
7-68November 9, 1998 (Version 3.1)
R
XC3000 Series Field Programmable Gate Arrays
XC3000 Series 100-Pin QFP Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs.
Programmed outputs are default sl ew-rate limited.
* This table desc ribes the pin outs of th ree dif f eren t chips in thr ee di ffe rent package s. Th e pin- descr ipt ion colu mn li sts 10 0 of
the 118 pads on the XC3042A that are c onnec t ed t o the 100 pac k age pi n s. Two pads, indicated by doubl e aste ri s ks, do not
exist on the XC3030A, which has 98 pads; therefore the corresponding pins have no connections. Twenty-six pads,
indicated by single or double asteri sks, do not exist on the XC3020A, which has 74 pads; therefore, the corresponding pins
have no connections. (See table on page 65.)
November 9, 1998 (Version 3.1)7-69
XC3000 Series Field Programmable Gate Arrays
XC3000 Series 132-Pin Ceramic and Plastic PGA Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs.
Programmed outputs are default sl ew-rate limited.
* Indicates u nconnected package pins (14) for the XC3042A.
7-70November 9, 1998 (Version 3.1)
R
XC3000 Series Field Programmable Gate Arrays
XC3000 Series 144-Pin Plastic TQFP Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs.
Programmed outputs are default sl ew-rate limited.
* Indicates u nconnected package pins (24) for the XC3042A.
November 9, 1998 (Version 3.1)7-71
XC3000 Series Field Programmable Gate Arrays
XC3000 Series 160-Pin PQFP Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs.
Programmed IOBs are default slew-rate limited.
* Indicates u nconnected package pins (18) for the XC3064A.
7-72November 9, 1998 (Version 3.1)
R
XC3000 Series Field Programmable Gate Arrays
XC3000 Series 175-Pin Ceramic and Plastic PGA Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs.
Programmed outputs are default sl ew-rate limited.
Pins A2, A3, A15, A16, T1, T2, T3, T15 and T16 are not connected. Pin A1 does not exist.
November 9, 1998 (Version 3.1)7-73
XC3000 Series Field Programmable Gate Arrays
XC3000 Series 176-Pin TQFP Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs.
Programmed outputs are default sl ew-rate limited.
7-74November 9, 1998 (Version 3.1)
R
XC3000 Series 208-Pin PQFP Pinouts
XC3000A, and XC3000L families have identical pinouts
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs.
Programmed outputs are default sl ew-rate limited.
* In PQ208, XC3090A and XC3195A have different pinouts.
Unprogrammed IOBs have a def ault pull-up. This prevent s an undefi ned pad level f or unbonded or un used IOBs . Programm ed outputs are
default slew-rate limited.
In the PQ208 package, pins 15, 16, 64, 65, 90, 91, 142, 143, 170 and 195 are not connected.
* In PQ208, XC3090A and XC3195A have different pinouts.