XILINX XC2V40, XC2V80, XC2V250, XC2V500, XC2V1000 User Manual

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DS031-1 (v1.7) October 2, 2001

Summary of Virtex®-II Features

• Industry First Platform FPGA Solution

• IP-Immersion™ Architecture

- Densities from 40K to 8M system gates

- 420 MHz internal clock speed (Advance Data)

- 840+ Mb/s I/O (Advance Data)

• SelectRAM™ Memory Hierarchy

- 3 Mb of True Dual-Port™ RAM in 18-Kbit block
SelectRAM resources

- Up to 1.5 Mb of distributed SelectRAM resources

- High-performance interfaces to external memory

· DDR-SDRAM interface

· FCRAM interface

· QDR™-SRAM interface

· Sigma RAM interface

• Arithmetic Functions

- Dedicated 18-bit x 18-bit multiplier blocks

- Fast look-ahead carry logic chains

• Flexible Logic Resources

- Up to 93,184 internal registers / latches with Clock
Enable

- Up to 93,184 look-up tables (LUTs) or cascadable
16-bit shift registers

- Wide multiplexers and wide-input function support

- Horizontal cascade chain and Sum-of-Products
support

- Internal 3-state bussing

• High-Performance Clock Management Circuitry

- Up to 12 DCM (Digital Clock Manager) modules

· Precise clock de-skew

· Flexible frequency synthesis

· High-resolution phase shifting

- 16 global clock multiplexer buffers

• Active Interconnect™ Technology

- Fourth generation segmented routing structure

- Predictable, fast routing delay, independent of
fanout

• SelectI/O-Ultra™ Technology

- Up to 1,108 user I/Os

- 19 single-ended standards and six differential
standards

- Programmable sink current (2 mA to 24 mA) per I/O

00

Virtex-II 1.5V
Field-Programmable Gate Arrays

Advance Product Specification

- Digitally Controlled Impedance (DCI) I/O: on-chip
termination resistors for single-ended I/O standards

- PCI-X @ 133 MHz, PCI @ 66 MHz and 33 MHz
compliance, and CardBus compliant

- Differential Signaling

· 840 Mb/s Low-Voltage Differential Signaling I/O

(LVDS) with current mode drivers

· Bus LVDS I/O

· Lightning Data Transport (LDT) I/O with current

driver buffers

· Low-Voltage Positive Emitter-Coupled Logic

(LVPECL) I/O

· Built-in DDR Input and Output registers

- Proprietary high-performance SelectLink™
Technology

· High-bandwidth data path

· Double Data Rate (DDR) link

· Web-based HDL generation methodology

• Supported by Xilinx Foundation™ and Alliance™

Series Development Systems

- Integrated VHDL and Verilog design flows

- Compilation of 10M system gates designs

- Internet Team Design (ITD) tool

• SRAM-Based In-System Configuration

-Fast SelectMAP™ configuration

- Triple Data Encryption Standard (DES) security
option (Bitstream Encryption)

- IEEE1532 support

- Partial reconfiguration

- Unlimited re-programmability

- Readback capability

• 0.15 µm 8-Layer Metal process with 0.12 µm
high-speed transistors

• 1.5 V (V
V

CCAUX

• IEEE 1149.1 compatible boundary-scan logic support

• Flip-Chip and Wire-Bond Ball Grid Array (BGA)

packages in three standard fine pitches (0.80mm,

1.00mm, and 1.27mm)

• 100% factory tested

) core power supply, dedicated 3.3 V

CCINT

auxiliary and V

I/O power supplies

CCO

© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS031-1 (v1.7) October 2, 2001 www.xilinx.com Module 1 of 4

Advance Product Specification 1-800-255-7778 1

Virtex-II 1.5V Field-Programmable Gate Arrays

Table 1: Virtex-II Field-Programmable Gate Array Family Members

CLB

(1 CLB = 4 slices = Max 128 bits)

SelectRAM Blocks

Maximum

Device

System

Gates

Array

Row x Col. Slices

Distributed

RAM Kbits

Multiplier

Blocks

18-Kbit
Blocks

Max RAM

(Kbits)

DCMs

Max I/O

Pads

XC2V40 40K 8 x 8 256 8 4 4 72 4 88
XC2V80 80K 16 x 8 512 16 8 8 144 4 120
XC2V250 250K 24 x 16 1,536 48 24 24 432 8 200
XC2V500 500K 32 x 24 3,072 96 32 32 576 8 264
XC2V1000 1M 40 x 32 5,120 160 40 40 720 8 432
XC2V1500 1.5M 48 x 40 7,680 240 48 48 864 8 528
XC2V2000 2M 56 x 48 10,752 336 56 56 1,008 8 624
XC2V3000 3M 64 x 56 14,336 448 96 96 1,728 12 720
XC2V4000 4M 80 x 72 23,040 720 120 120 2,160 12 912

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(1)

XC2V6000 6M 96 x 88 33,792 1,056 144 144 2,592 12 1,104
XC2V8000 8M 112 x 104 46,592 1,456 168 168 3,024 12 1,108

Notes:

1. See details in

Ta bl e 2 , “Maximum Number of User I/O Pads”.

General Description

The Virtex-II family is a platform FPGA developed for high
performance from low-density to high-density designs that
are based on IP cores and customized modules. The family
delivers complete solutions for telecommunication, wire­less, networking, video, and DSP applications, including
PCI, LVDS, and DDR interfaces.

The leading-edge 0.15µm / 0.12µm CMOS 8-layer metal
process and the Virtex-II architecture are optimized for high
speed with low power consumption. Combining a wide vari­ety of flexible features and a large range of densities up to
10 million system gates, the Virtex-II family enhances pro­grammable logic design capabilities and is a powerful alter­native to mask-programmed gates arrays. As shown in

Ta bl e 1 , the Virtex-II family comprises 12 members, ranging

from 40K to 10M system gates.

Packaging

Offerings include ball grid array (BGA) packages with

0.80mm, 1.00mm, and 1.27mm pitches. In addition to tradi­tional wire-bond interconnects, flip-chip interconnect is used
in some of the BGA offerings. The use of flip-chip intercon­nect offers more I/Os than is possible in wire-bond versions
of the similar packages. Flip-Chip construction offers the
combination of high pin count with high thermal capacity.

Ta bl e 2 shows the maximum number of user I/Os available.

The Virtex-II device/package combination table (Ta b le 6 at
the end of this section) details the maximum number of I/Os
for each device and package using wire-bond or flip-chip
technology.

Tab le 2 : Maximum Number of User I/O Pads

Device Wire-Bond Flip-Chip

XC2V40 88
XC2V80 120
XC2V250 200
XC2V500 264
XC2V1000 328 432
XC2V1500 392 528
XC2V2000 456 624
XC2V3000 516 720
XC2V4000 912
XC2V6000 1,104
XC2V8000 1,108

Module 1 of 4 www.xilinx.com DS031-1 (v1.7) October 2, 2001
2 1-800-255-7778 Advance Product Specification

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Virtex-II 1.5V Field-Programmable Gate Arrays

Architecture

Virtex-II Array Overview

Virtex-II devices are user-programmable gate arrays with various configurable elements. The Virtex-II architecture is
optimized for high-density and high-performance logic designs. As shown in Figure 1, the programmable device is
comprised of input/output blocks (IOBs) and internal configurable logic blocks (CLBs).

DCM DCM IOB

Global Clock Mux

Configurable Logic

Programmable I/Os

CLB

Figure 1: Virtex-II Architecture Overview

Programmable I/O blocks provide the interface between
package pins and the internal configurable logic. Most
popular and leading-edge I/O standards are supported by
the programmable IOBs.

The internal configurable logic includes four major elements
organized in a regular array.

• Configurable Logic Blocks (CLBs) provide functional
elements for combinatorial and synchronous logic,
including basic storage elements. BUFTs (3-state
buffers) associated with each CLB element drive
dedicated segmentable horizontal routing resources.

• Block SelectRAM memory modules provide large
18-Kbit storage elements of True Dual-Port RAM.

• Multiplier blocks are 18-bit x 18-bit dedicated
multipliers.

• DCM (Digital Clock Manager) blocks provide
self-calibrating, fully digital solutions for clock
distribution delay compensation, clock multiplication
and division, coarse and fine-grained clock phase
shifting.

A new generation of programmable routing resources called
Active Interconnect Technology interconnects all of these
elements. The general routing matrix (GRM) is an array of
routing switches. Each programmable element is tied to a
switch matrix, allowing multiple connections to the general
routing matrix. The overall programmable interconnection is
hierarchical and designed to support high-speed designs.

Block SelectRAM Multiplier

DS031_28_100900

All programmable elements, including the routing
resources, are controlled by values stored in static memory
cells. These values are loaded in the memory cells during
configuration and can be reloaded to change the functions
of the programmable elements.

Virtex-II Features

This section briefly describes Virtex-II features.

Input/Output Blocks (IOBs)

IOBs are programmable and can be categorized as follows:

• Input block with an optional single-data-rate or
double-data-rate (DDR) register

• Output block with an optional single-data-rate or DDR
register, and an optional 3-state buffer, to be driven
directly or through a single or DDR register

• Bi-directional block (any combination of input and
output configurations)

These registers are either edge-triggered D-type flip-flops
or level-sensitive latches.

IOBs support the following single-ended I/O standards:

• LVTTL, LVCMOS (3.3 V, 2.5 V, 1.8 V, and 1.5 V)

• PCI-X at 133 MHz, PCI (3.3 V at 33 MHz and 66 MHz)

• GTL and GTLP

• HSTL (Class I, II, III, and IV)

DS031-1 (v1.7) October 2, 2001 www.xilinx.com Module 1 of 4

Advance Product Specification 1-800-255-7778 3